CPUM.cpp@ 34834

Last change on this file since 34834 was 34328, checked in by vboxsync, 14 years ago
CPUM: updated the CPUID processor feature flags
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1	/* $Id: CPUM.cpp 34328 2010-11-24 14:33:57Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*/
33
34	/*******************************************************************************
35	* Header Files *
36	*******************************************************************************/
37	#define LOG_GROUP LOG_GROUP_CPUM
38	#include <VBox/cpum.h>
39	#include <VBox/cpumdis.h>
40	#include <VBox/pgm.h>
41	#include <VBox/mm.h>
42	#include <VBox/selm.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/patm.h>
45	#include <VBox/hwaccm.h>
46	#include <VBox/ssm.h>
47	#include "CPUMInternal.h"
48	#include <VBox/vm.h>
49
50	#include <VBox/param.h>
51	#include <VBox/dis.h>
52	#include <VBox/err.h>
53	#include <VBox/log.h>
54	#include <iprt/assert.h>
55	#include <iprt/asm-amd64-x86.h>
56	#include <iprt/string.h>
57	#include <iprt/mp.h>
58	#include <iprt/cpuset.h>
59	#include <include/internal/pgm.h>
60
61	/*******************************************************************************
62	* Defined Constants And Macros *
63	*******************************************************************************/
64	/** The current saved state version. */
65	#define CPUM_SAVED_STATE_VERSION 12
66	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
67	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
68	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
69	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
70	* changes. */
71	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
72	/** The saved state version for the 2.1 trunk before the MSR changes. */
73	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
74	/** The saved state version of 2.0, used for backwards compatibility. */
75	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
76	/** The saved state version of 1.6, used for backwards compatibility. */
77	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
78
79
80	/*******************************************************************************
81	* Structures and Typedefs *
82	*******************************************************************************/
83
84	/**
85	* What kind of cpu info dump to perform.
86	*/
87	typedef enum CPUMDUMPTYPE
88	{
89	CPUMDUMPTYPE_TERSE,
90	CPUMDUMPTYPE_DEFAULT,
91	CPUMDUMPTYPE_VERBOSE
92	} CPUMDUMPTYPE;
93	/** Pointer to a cpu info dump type. */
94	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97	/*******************************************************************************
98	* Internal Functions *
99	*******************************************************************************/
100	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
101	static int cpumR3CpuIdInit(PVM pVM);
102	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
103	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
104	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
105	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
106	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
107	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113
114
115	/**
116	* Initializes the CPUM.
117	*
118	* @returns VBox status code.
119	* @param pVM The VM to operate on.
120	*/
121	VMMR3DECL(int) CPUMR3Init(PVM pVM)
122	{
123	LogFlow(("CPUMR3Init\n"));
124
125	/*
126	* Assert alignment and sizes.
127	*/
128	AssertCompileMemberAlignment(VM, cpum.s, 32);
129	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
130	AssertCompileSizeAlignment(CPUMCTX, 64);
131	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
132	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
133	AssertCompileMemberAlignment(VM, cpum, 64);
134	AssertCompileMemberAlignment(VM, aCpus, 64);
135	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
136	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
137
138	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
139	pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
140	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
141
142	/* Calculate the offset from CPUMCPU to CPUM. */
143	for (VMCPUID i = 0; i < pVM->cCpus; i++)
144	{
145	PVMCPU pVCpu = &pVM->aCpus[i];
146
147	/*
148	* Setup any fixed pointers and offsets.
149	*/
150	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
151	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
152
153	pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
154	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
155	}
156
157	/*
158	* Check that the CPU supports the minimum features we require.
159	*/
160	if (!ASMHasCpuId())
161	{
162	Log(("The CPU doesn't support CPUID!\n"));
163	return VERR_UNSUPPORTED_CPU;
164	}
165	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
166	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
167
168	/* Setup the CR4 AND and OR masks used in the switcher */
169	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
170	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
171	{
172	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
173	/* No FXSAVE implies no SSE */
174	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
175	pVM->cpum.s.CR4.OrMask = 0;
176	}
177	else
178	{
179	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
180	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
181	}
182
183	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
184	{
185	Log(("The CPU doesn't support MMX!\n"));
186	return VERR_UNSUPPORTED_CPU;
187	}
188	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
189	{
190	Log(("The CPU doesn't support TSC!\n"));
191	return VERR_UNSUPPORTED_CPU;
192	}
193	/* Bogus on AMD? */
194	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
195	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
196
197	/*
198	* Detect the host CPU vendor.
199	* (The guest CPU vendor is re-detected later on.)
200	*/
201	uint32_t uEAX, uEBX, uECX, uEDX;
202	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
203	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
204	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
205
206	/*
207	* Setup hypervisor startup values.
208	*/
209
210	/*
211	* Register saved state data item.
212	*/
213	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
214	NULL, cpumR3LiveExec, NULL,
215	NULL, cpumR3SaveExec, NULL,
216	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
217	if (RT_FAILURE(rc))
218	return rc;
219
220	/*
221	* Register info handlers.
222	*/
223	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
224	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
225	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
227	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
228	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
229
230	/*
231	* Initialize the Guest CPUID state.
232	*/
233	rc = cpumR3CpuIdInit(pVM);
234	if (RT_FAILURE(rc))
235	return rc;
236	CPUMR3Reset(pVM);
237	return VINF_SUCCESS;
238	}
239
240
241	/**
242	* Detect the CPU vendor give n the
243	*
244	* @returns The vendor.
245	* @param uEAX EAX from CPUID(0).
246	* @param uEBX EBX from CPUID(0).
247	* @param uECX ECX from CPUID(0).
248	* @param uEDX EDX from CPUID(0).
249	*/
250	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
251	{
252	if ( uEAX >= 1
253	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
254	&& uECX == X86_CPUID_VENDOR_AMD_ECX
255	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
256	return CPUMCPUVENDOR_AMD;
257
258	if ( uEAX >= 1
259	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
260	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
261	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
262	return CPUMCPUVENDOR_INTEL;
263
264	/** @todo detect the other buggers... */
265	return CPUMCPUVENDOR_UNKNOWN;
266	}
267
268
269	/**
270	* Fetches overrides for a CPUID leaf.
271	*
272	* @returns VBox status code.
273	* @param pLeaf The leaf to load the overrides into.
274	* @param pCfgNode The CFGM node containing the overrides
275	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
276	* @param iLeaf The CPUID leaf number.
277	*/
278	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
279	{
280	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
281	if (pLeafNode)
282	{
283	uint32_t u32;
284	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
285	if (RT_SUCCESS(rc))
286	pLeaf->eax = u32;
287	else
288	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
289
290	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
291	if (RT_SUCCESS(rc))
292	pLeaf->ebx = u32;
293	else
294	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
295
296	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
297	if (RT_SUCCESS(rc))
298	pLeaf->ecx = u32;
299	else
300	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
301
302	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
303	if (RT_SUCCESS(rc))
304	pLeaf->edx = u32;
305	else
306	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
307
308	}
309	return VINF_SUCCESS;
310	}
311
312
313	/**
314	* Load the overrides for a set of CPUID leaves.
315	*
316	* @returns VBox status code.
317	* @param paLeaves The leaf array.
318	* @param cLeaves The number of leaves.
319	* @param uStart The start leaf number.
320	* @param pCfgNode The CFGM node containing the overrides
321	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
322	*/
323	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
324	{
325	for (uint32_t i = 0; i < cLeaves; i++)
326	{
327	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
328	if (RT_FAILURE(rc))
329	return rc;
330	}
331
332	return VINF_SUCCESS;
333	}
334
335	/**
336	* Init a set of host CPUID leaves.
337	*
338	* @returns VBox status code.
339	* @param paLeaves The leaf array.
340	* @param cLeaves The number of leaves.
341	* @param uStart The start leaf number.
342	* @param pCfgNode The /CPUM/HostCPUID/ node.
343	*/
344	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
345	{
346	/* Using the ECX variant for all of them can't hurt... */
347	for (uint32_t i = 0; i < cLeaves; i++)
348	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
349
350	/* Load CPUID leaf override; we currently don't care if the user
351	specifies features the host CPU doesn't support. */
352	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
353	}
354
355
356	/**
357	* Initializes the emulated CPU's cpuid information.
358	*
359	* @returns VBox status code.
360	* @param pVM The VM to operate on.
361	*/
362	static int cpumR3CpuIdInit(PVM pVM)
363	{
364	PCPUM pCPUM = &pVM->cpum.s;
365	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
366	uint32_t i;
367	int rc;
368
369	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
370	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
371	{ \
372	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
373	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
374	}
375	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
376	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
377	{ \
378	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
379	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
380	}
381
382	/*
383	* Read the configuration.
384	*/
385	/** @cfgm{CPUM/SyntheticCpu, boolean, false}
386	* Enables the Synthetic CPU. The Vendor ID and Processor Name are
387	* completely overridden by VirtualBox custom strings. Some
388	* CPUID information is withheld, like the cache info. */
389	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
390	AssertRCReturn(rc, rc);
391
392	/** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
393	* When non-zero CPUID features that could cause portability issues will be
394	* stripped. The higher the value the more features gets stripped. Higher
395	* values should only be used when older CPUs are involved since it may
396	* harm performance and maybe also cause problems with specific guests. */
397	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
398	AssertRCReturn(rc, rc);
399
400	AssertLogRelReturn(!pCPUM->fSyntheticCpu \|\| !pCPUM->u8PortableCpuIdLevel, VERR_INTERNAL_ERROR_2);
401
402	/*
403	* Get the host CPUID leaves and redetect the guest CPU vendor (could've
404	* been overridden).
405	*/
406	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
407	* Overrides the host CPUID leaf values used for calculating the guest CPUID
408	* leaves. This can be used to preserve the CPUID values when moving a VM
409	* to a different machine. Another use is restricting (or extending) the
410	* feature set exposed to the guest. */
411	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
412	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
413	AssertRCReturn(rc, rc);
414	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
415	AssertRCReturn(rc, rc);
416	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
417	AssertRCReturn(rc, rc);
418
419	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
420	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
421
422	/*
423	* Determine the default leaf.
424	*
425	* Intel returns values of the highest standard function, while AMD
426	* returns zeros. VIA on the other hand seems to returning nothing or
427	* perhaps some random garbage, we don't try to duplicate this behavior.
428	*/
429	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
430	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
431	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
432
433
434	/* Cpuid 1 & 0x80000001:
435	* Only report features we can support.
436	*
437	* Note! When enabling new features the Synthetic CPU and Portable CPUID
438	* options may require adjusting (i.e. stripping what was enabled).
439	*/
440	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
441	\| X86_CPUID_FEATURE_EDX_VME
442	\| X86_CPUID_FEATURE_EDX_DE
443	\| X86_CPUID_FEATURE_EDX_PSE
444	\| X86_CPUID_FEATURE_EDX_TSC
445	\| X86_CPUID_FEATURE_EDX_MSR
446	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
447	\| X86_CPUID_FEATURE_EDX_MCE
448	\| X86_CPUID_FEATURE_EDX_CX8
449	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
450	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
451	//\| X86_CPUID_FEATURE_EDX_SEP
452	\| X86_CPUID_FEATURE_EDX_MTRR
453	\| X86_CPUID_FEATURE_EDX_PGE
454	\| X86_CPUID_FEATURE_EDX_MCA
455	\| X86_CPUID_FEATURE_EDX_CMOV
456	\| X86_CPUID_FEATURE_EDX_PAT
457	\| X86_CPUID_FEATURE_EDX_PSE36
458	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
459	\| X86_CPUID_FEATURE_EDX_CLFSH
460	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
461	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
462	\| X86_CPUID_FEATURE_EDX_MMX
463	\| X86_CPUID_FEATURE_EDX_FXSR
464	\| X86_CPUID_FEATURE_EDX_SSE
465	\| X86_CPUID_FEATURE_EDX_SSE2
466	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
467	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
468	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
469	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
470	\| 0;
471	pCPUM->aGuestCpuIdStd[1].ecx &= 0
472	\| X86_CPUID_FEATURE_ECX_SSE3
473	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
474	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
475	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
476	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
477	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
478	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
479	\| X86_CPUID_FEATURE_ECX_SSSE3
480	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
481	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
482	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
483	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
484	/* ECX Bit 21 - x2APIC support - not yet. */
485	// \| X86_CPUID_FEATURE_ECX_X2APIC
486	/* ECX Bit 23 - POPCNT instruction. */
487	//\| X86_CPUID_FEATURE_ECX_POPCNT
488	\| 0;
489	if (pCPUM->u8PortableCpuIdLevel > 0)
490	{
491	PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
492	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
493	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
494	PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
495	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
496	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
497	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
498
499	Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
500	\| X86_CPUID_FEATURE_EDX_PSN
501	\| X86_CPUID_FEATURE_EDX_DS
502	\| X86_CPUID_FEATURE_EDX_ACPI
503	\| X86_CPUID_FEATURE_EDX_SS
504	\| X86_CPUID_FEATURE_EDX_TM
505	\| X86_CPUID_FEATURE_EDX_PBE
506	)));
507	Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
508	\| X86_CPUID_FEATURE_ECX_DTES64
509	\| X86_CPUID_FEATURE_ECX_CPLDS
510	\| X86_CPUID_FEATURE_ECX_VMX
511	\| X86_CPUID_FEATURE_ECX_SMX
512	\| X86_CPUID_FEATURE_ECX_EST
513	\| X86_CPUID_FEATURE_ECX_TM2
514	\| X86_CPUID_FEATURE_ECX_CNTXID
515	\| X86_CPUID_FEATURE_ECX_FMA
516	\| X86_CPUID_FEATURE_ECX_CX16
517	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
518	\| X86_CPUID_FEATURE_ECX_PDCM
519	\| X86_CPUID_FEATURE_ECX_DCA
520	\| X86_CPUID_FEATURE_ECX_MOVBE
521	\| X86_CPUID_FEATURE_ECX_AES
522	\| X86_CPUID_FEATURE_ECX_POPCNT
523	\| X86_CPUID_FEATURE_ECX_XSAVE
524	\| X86_CPUID_FEATURE_ECX_OSXSAVE
525	\| X86_CPUID_FEATURE_ECX_AVX
526	)));
527	}
528
529	/* Cpuid 0x80000001:
530	* Only report features we can support.
531	*
532	* Note! When enabling new features the Synthetic CPU and Portable CPUID
533	* options may require adjusting (i.e. stripping what was enabled).
534	*
535	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
536	*/
537	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
538	\| X86_CPUID_AMD_FEATURE_EDX_VME
539	\| X86_CPUID_AMD_FEATURE_EDX_DE
540	\| X86_CPUID_AMD_FEATURE_EDX_PSE
541	\| X86_CPUID_AMD_FEATURE_EDX_TSC
542	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
543	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
544	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
545	\| X86_CPUID_AMD_FEATURE_EDX_CX8
546	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
547	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
548	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
549	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
550	\| X86_CPUID_AMD_FEATURE_EDX_PGE
551	\| X86_CPUID_AMD_FEATURE_EDX_MCA
552	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
553	\| X86_CPUID_AMD_FEATURE_EDX_PAT
554	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
555	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
556	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
557	\| X86_CPUID_AMD_FEATURE_EDX_MMX
558	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
559	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
560	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
561	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
562	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
563	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
564	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
565	\| 0;
566	pCPUM->aGuestCpuIdExt[1].ecx &= 0
567	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
568	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
569	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
570	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
571	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
572	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
573	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
574	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
575	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
576	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
577	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
578	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
579	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
580	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
581	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
582	\| 0;
583	if (pCPUM->u8PortableCpuIdLevel > 0)
584	{
585	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
586	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
587	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
588	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
589	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
590	PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
591	PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
592
593	Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
594	\| X86_CPUID_AMD_FEATURE_ECX_SVM
595	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
596	\| X86_CPUID_AMD_FEATURE_ECX_CR8L
597	\| X86_CPUID_AMD_FEATURE_ECX_ABM
598	\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
599	\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
600	\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
601	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
602	\| X86_CPUID_AMD_FEATURE_ECX_IBS
603	\| X86_CPUID_AMD_FEATURE_ECX_SSE5
604	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
605	\| X86_CPUID_AMD_FEATURE_ECX_WDT
606	\| UINT32_C(0xffffc000)
607	)));
608	Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
609	\| X86_CPUID_AMD_FEATURE_EDX_SEP
610	\| RT_BIT(18)
611	\| RT_BIT(19)
612	\| RT_BIT(21)
613	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
614	\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
615	\| RT_BIT(28)
616	)));
617	}
618
619	/*
620	* Apply the Synthetic CPU modifications. (TODO: move this up)
621	*/
622	if (pCPUM->fSyntheticCpu)
623	{
624	static const char s_szVendor[13] = "VirtualBox ";
625	static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
626
627	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
628
629	/* Limit the nr of standard leaves; 5 for monitor/mwait */
630	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
631
632	/* 0: Vendor */
633	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
634	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
635	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
636
637	/* 1.eax: Version information. family : model : stepping */
638	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
639
640	/* Leaves 2 - 4 are Intel only - zero them out */
641	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
642	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
643	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
644
645	/* Leaf 5 = monitor/mwait */
646
647	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
648	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
649	/* AMD only - set to zero. */
650	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
651
652	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
653	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
654
655	/* 0x800000002-4: Processor Name String Identifier. */
656	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
657	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
658	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
659	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
660	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
661	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
662	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
663	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
664	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
665	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
666	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
667	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
668
669	/* 0x800000005-7 - reserved -> zero */
670	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
671	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
672	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
673
674	/* 0x800000008: only the max virtual and physical address size. */
675	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
676	}
677
678	/*
679	* Hide HTT, multicode, SMP, whatever.
680	* (APIC-ID := 0 and #LogCpus := 0)
681	*/
682	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
683	#ifdef VBOX_WITH_MULTI_CORE
684	if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
685	&& pVM->cCpus > 1)
686	{
687	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
688	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
689	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
690	}
691	#endif
692
693	/* Cpuid 2:
694	* Intel: Cache and TLB information
695	* AMD: Reserved
696	* Safe to expose; restrict the number of calls to 1 for the portable case.
697	*/
698	if ( pCPUM->u8PortableCpuIdLevel > 0
699	&& pCPUM->aGuestCpuIdStd[0].eax >= 2
700	&& (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
701	{
702	LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
703	pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
704	}
705
706	/* Cpuid 3:
707	* Intel: EAX, EBX - reserved (transmeta uses these)
708	* ECX, EDX - Processor Serial Number if available, otherwise reserved
709	* AMD: Reserved
710	* Safe to expose
711	*/
712	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
713	{
714	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
715	if (pCPUM->u8PortableCpuIdLevel > 0)
716	pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
717	}
718
719	/* Cpuid 4:
720	* Intel: Deterministic Cache Parameters Leaf
721	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
722	* AMD: Reserved
723	* Safe to expose, except for EAX:
724	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
725	* Bits 31-26: Maximum number of processor cores in this physical package**
726	* Note: These SMP values are constant regardless of ECX
727	*/
728	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
729	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
730	#ifdef VBOX_WITH_MULTI_CORE
731	if ( pVM->cCpus > 1
732	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
733	{
734	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
735	/* One logical processor with possibly multiple cores. */
736	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
737	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
738	}
739	#endif
740
741	/* Cpuid 5: Monitor/mwait Leaf
742	* Intel: ECX, EDX - reserved
743	* EAX, EBX - Smallest and largest monitor line size
744	* AMD: EDX - reserved
745	* EAX, EBX - Smallest and largest monitor line size
746	* ECX - extensions (ignored for now)
747	* Safe to expose
748	*/
749	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
750	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
751
752	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
753	/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
754	* Expose MWAIT extended features to the guest. For now we expose
755	* just MWAIT break on interrupt feature (bit 1).
756	*/
757	bool fMWaitExtensions;
758	rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
759	if (fMWaitExtensions)
760	{
761	pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
762	/* @todo: for now we just expose host's MWAIT C-states, although conceptually
763	it shall be part of our power management virtualization model */
764	#if 0
765	/* MWAIT sub C-states */
766	pCPUM->aGuestCpuIdStd[5].edx =
767	(0 << 0) /* 0 in C0 */ \|
768	(2 << 4) /* 2 in C1 */ \|
769	(2 << 8) /* 2 in C2 */ \|
770	(2 << 12) /* 2 in C3 */ \|
771	(0 << 16) /* 0 in C4 */
772	;
773	#endif
774	}
775	else
776	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
777
778	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
779	* Safe to pass on to the guest.
780	*
781	* Intel: 0x800000005 reserved
782	* 0x800000006 L2 cache information
783	* AMD: 0x800000005 L1 cache information
784	* 0x800000006 L2/L3 cache information
785	*/
786
787	/* Cpuid 0x800000007:
788	* AMD: EAX, EBX, ECX - reserved
789	* EDX: Advanced Power Management Information
790	* Intel: Reserved
791	*/
792	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
793	{
794	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
795
796	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
797
798	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
799	{
800	/* Only expose the TSC invariant capability bit to the guest. */
801	pCPUM->aGuestCpuIdExt[7].edx &= 0
802	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
803	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
804	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
805	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
806	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
807	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
808	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
809	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
810	#if 0 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
811	* Linux kernels blindly assume that the AMD performance counters work
812	* if this is set for 64 bits guests. (Can't really find a CPUID feature
813	* bit for them though.) */
814	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
815	#endif
816	\| 0;
817	}
818	else
819	pCPUM->aGuestCpuIdExt[7].edx = 0;
820	}
821
822	/* Cpuid 0x800000008:
823	* AMD: EBX, EDX - reserved
824	* EAX: Virtual/Physical/Guest address Size
825	* ECX: Number of cores + APICIdCoreIdSize
826	* Intel: EAX: Virtual/Physical address Size
827	* EBX, ECX, EDX - reserved
828	*/
829	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
830	{
831	/* Only expose the virtual and physical address sizes to the guest. */
832	pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
833	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
834	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
835	* NC (0-7) Number of cores; 0 equals 1 core */
836	pCPUM->aGuestCpuIdExt[8].ecx = 0;
837	#ifdef VBOX_WITH_MULTI_CORE
838	if ( pVM->cCpus > 1
839	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
840	{
841	/* Legacy method to determine the number of cores. */
842	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
843	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
844	}
845	#endif
846	}
847
848	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
849	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
850	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
851	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
852	*/
853	bool fNt4LeafLimit;
854	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
855	if (fNt4LeafLimit)
856	pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
857
858	/*
859	* Limit it the number of entries and fill the remaining with the defaults.
860	*
861	* The limits are masking off stuff about power saving and similar, this
862	* is perhaps a bit crudely done as there is probably some relatively harmless
863	* info too in these leaves (like words about having a constant TSC).
864	*/
865	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
866	pCPUM->aGuestCpuIdStd[0].eax = 5;
867	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
868	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
869
870	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
871	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
872	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
873	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
874	: 0;
875	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
876	i++)
877	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
878
879	/*
880	* Centaur stuff (VIA).
881	*
882	* The important part here (we think) is to make sure the 0xc0000000
883	* function returns 0xc0000001. As for the features, we don't currently
884	* let on about any of those... 0xc0000002 seems to be some
885	* temperature/hz/++ stuff, include it as well (static).
886	*/
887	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
888	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
889	{
890	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
891	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
892	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
893	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
894	i++)
895	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
896	}
897	else
898	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
899	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
900
901
902	/*
903	* Load CPUID overrides from configuration.
904	* Note: Kind of redundant now, but allows unchanged overrides
905	*/
906	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
907	* Overrides the CPUID leaf values. */
908	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
909	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
910	AssertRCReturn(rc, rc);
911	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
912	AssertRCReturn(rc, rc);
913	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
914	AssertRCReturn(rc, rc);
915
916	/*
917	* Check if PAE was explicitely enabled by the user.
918	*/
919	bool fEnable;
920	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
921	if (fEnable)
922	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
923
924	/*
925	* We don't normally enable NX for raw-mode, so give the user a chance to
926	* force it on.
927	*/
928	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
929	if (fEnable)
930	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
931
932	/*
933	* Log the cpuid and we're good.
934	*/
935	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
936	RTCPUSET OnlineSet;
937	LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
938	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
939	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
940	LogRel(("*********************** CPUID dump **********************\n"));
941	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
942	LogRel(("\n"));
943	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
944	RTLogRelSetBuffering(fOldBuffered);
945	LogRel(("****************** End of CPUID dump ********************\n"));
946
947	#undef PORTABLE_DISABLE_FEATURE_BIT
948	#undef PORTABLE_CLEAR_BITS_WHEN
949
950	return VINF_SUCCESS;
951	}
952
953
954	/**
955	* Applies relocations to data and code managed by this
956	* component. This function will be called at init and
957	* whenever the VMM need to relocate it self inside the GC.
958	*
959	* The CPUM will update the addresses used by the switcher.
960	*
961	* @param pVM The VM.
962	*/
963	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
964	{
965	LogFlow(("CPUMR3Relocate\n"));
966	for (VMCPUID i = 0; i < pVM->cCpus; i++)
967	{
968	/*
969	* Switcher pointers.
970	*/
971	PVMCPU pVCpu = &pVM->aCpus[i];
972	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
973	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
974
975	}
976	}
977
978
979	/**
980	* Apply late CPUM property changes based on the fHWVirtEx setting
981	*
982	* @param pVM The VM to operate on.
983	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
984	*/
985	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
986	{
987	/*
988	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
989	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
990	* of processors from (cpuid(4).eax >> 26) + 1.
991	*
992	* Note: this code is obsolete, but let's keep it here for reference.
993	* Purpose is valid when we artificially cap the max std id to less than 4.
994	*/
995	if (!fHWVirtExEnabled)
996	{
997	Assert(pVM->cpum.s.aGuestCpuIdStd[4].eax == 0);
998	pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
999	}
1000	}
1001
1002	/**
1003	* Terminates the CPUM.
1004	*
1005	* Termination means cleaning up and freeing all resources,
1006	* the VM it self is at this point powered off or suspended.
1007	*
1008	* @returns VBox status code.
1009	* @param pVM The VM to operate on.
1010	*/
1011	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1012	{
1013	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1014	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1015	{
1016	PVMCPU pVCpu = &pVM->aCpus[i];
1017	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1018
1019	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1020	pVCpu->cpum.s.uMagic = 0;
1021	pCtx->dr[5] = 0;
1022	}
1023	#endif
1024	return 0;
1025	}
1026
1027
1028	/**
1029	* Resets a virtual CPU.
1030	*
1031	* Used by CPUMR3Reset and CPU hot plugging.
1032	*
1033	* @param pVCpu The virtual CPU handle.
1034	*/
1035	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1036	{
1037	/** @todo anything different for VCPU > 0? */
1038	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1039
1040	/*
1041	* Initialize everything to ZERO first.
1042	*/
1043	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1044	memset(pCtx, 0, sizeof(*pCtx));
1045	pVCpu->cpum.s.fUseFlags = fUseFlags;
1046
1047	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1048	pCtx->eip = 0x0000fff0;
1049	pCtx->edx = 0x00000600; /* P6 processor */
1050	pCtx->eflags.Bits.u1Reserved0 = 1;
1051
1052	pCtx->cs = 0xf000;
1053	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
1054	pCtx->csHid.u32Limit = 0x0000ffff;
1055	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
1056	pCtx->csHid.Attr.n.u1Present = 1;
1057	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
1058
1059	pCtx->dsHid.u32Limit = 0x0000ffff;
1060	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
1061	pCtx->dsHid.Attr.n.u1Present = 1;
1062	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1063
1064	pCtx->esHid.u32Limit = 0x0000ffff;
1065	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
1066	pCtx->esHid.Attr.n.u1Present = 1;
1067	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1068
1069	pCtx->fsHid.u32Limit = 0x0000ffff;
1070	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
1071	pCtx->fsHid.Attr.n.u1Present = 1;
1072	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1073
1074	pCtx->gsHid.u32Limit = 0x0000ffff;
1075	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
1076	pCtx->gsHid.Attr.n.u1Present = 1;
1077	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1078
1079	pCtx->ssHid.u32Limit = 0x0000ffff;
1080	pCtx->ssHid.Attr.n.u1Present = 1;
1081	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
1082	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1083
1084	pCtx->idtr.cbIdt = 0xffff;
1085	pCtx->gdtr.cbGdt = 0xffff;
1086
1087	pCtx->ldtrHid.u32Limit = 0xffff;
1088	pCtx->ldtrHid.Attr.n.u1Present = 1;
1089	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1090
1091	pCtx->trHid.u32Limit = 0xffff;
1092	pCtx->trHid.Attr.n.u1Present = 1;
1093	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
1094
1095	pCtx->dr[6] = X86_DR6_INIT_VAL;
1096	pCtx->dr[7] = X86_DR7_INIT_VAL;
1097
1098	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
1099	pCtx->fpu.FCW = 0x37f;
1100
1101	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
1102	pCtx->fpu.MXCSR = 0x1F80;
1103
1104	/* Init PAT MSR */
1105	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1106
1107	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1108	* The Intel docs don't mention it.
1109	*/
1110	pCtx->msrEFER = 0;
1111	}
1112
1113
1114	/**
1115	* Resets the CPU.
1116	*
1117	* @returns VINF_SUCCESS.
1118	* @param pVM The VM handle.
1119	*/
1120	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1121	{
1122	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1123	{
1124	CPUMR3ResetCpu(&pVM->aCpus[i]);
1125
1126	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1127	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
1128
1129	/* Magic marker for searching in crash dumps. */
1130	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1131	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1132	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1133	#endif
1134	}
1135	}
1136
1137
1138	/**
1139	* Called both in pass 0 and the final pass.
1140	*
1141	* @param pVM The VM handle.
1142	* @param pSSM The saved state handle.
1143	*/
1144	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1145	{
1146	/*
1147	* Save all the CPU ID leaves here so we can check them for compatibility
1148	* upon loading.
1149	*/
1150	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1151	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1152
1153	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1154	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1155
1156	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1157	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1158
1159	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1160
1161	/*
1162	* Save a good portion of the raw CPU IDs as well as they may come in
1163	* handy when validating features for raw mode.
1164	*/
1165	CPUMCPUID aRawStd[16];
1166	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1167	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1168	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1169	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1170
1171	CPUMCPUID aRawExt[32];
1172	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1173	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1174	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1175	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1176	}
1177
1178
1179	/**
1180	* Loads the CPU ID leaves saved by pass 0.
1181	*
1182	* @returns VBox status code.
1183	* @param pVM The VM handle.
1184	* @param pSSM The saved state handle.
1185	* @param uVersion The format version.
1186	*/
1187	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1188	{
1189	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1190
1191	/*
1192	* Define a bunch of macros for simplifying the code.
1193	*/
1194	/* Generic expression + failure message. */
1195	#define CPUID_CHECK_RET(expr, fmt) \
1196	do { \
1197	if (!(expr)) \
1198	{ \
1199	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
1200	if (fStrictCpuIdChecks) \
1201	{ \
1202	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1203	RTStrFree(pszMsg); \
1204	return rcCpuid; \
1205	} \
1206	LogRel(("CPUM: %s\n", pszMsg)); \
1207	RTStrFree(pszMsg); \
1208	} \
1209	} while (0)
1210	#define CPUID_CHECK_WRN(expr, fmt) \
1211	do { \
1212	if (!(expr)) \
1213	LogRel(fmt); \
1214	} while (0)
1215
1216	/* For comparing two values and bitch if they differs. */
1217	#define CPUID_CHECK2_RET(what, host, saved) \
1218	do { \
1219	if ((host) != (saved)) \
1220	{ \
1221	if (fStrictCpuIdChecks) \
1222	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1223	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1224	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1225	} \
1226	} while (0)
1227	#define CPUID_CHECK2_WRN(what, host, saved) \
1228	do { \
1229	if ((host) != (saved)) \
1230	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1231	} while (0)
1232
1233	/* For checking raw cpu features (raw mode). */
1234	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1235	do { \
1236	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1237	{ \
1238	if (fStrictCpuIdChecks) \
1239	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1240	N_(#bit " mismatch: host=%d saved=%d"), \
1241	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1242	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1243	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1244	} \
1245	} while (0)
1246	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1247	do { \
1248	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1249	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1250	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1251	} while (0)
1252	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1253
1254	/* For checking guest features. */
1255	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1256	do { \
1257	if ( (aGuestCpuId##set [1].reg & bit) \
1258	&& !(aHostRaw##set [1].reg & bit) \
1259	&& !(aHostOverride##set [1].reg & bit) \
1260	&& !(aGuestOverride##set [1].reg & bit) \
1261	) \
1262	{ \
1263	if (fStrictCpuIdChecks) \
1264	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1265	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1266	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1267	} \
1268	} while (0)
1269	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1270	do { \
1271	if ( (aGuestCpuId##set [1].reg & bit) \
1272	&& !(aHostRaw##set [1].reg & bit) \
1273	&& !(aHostOverride##set [1].reg & bit) \
1274	&& !(aGuestOverride##set [1].reg & bit) \
1275	) \
1276	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1277	} while (0)
1278	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1279	do { \
1280	if ( (aGuestCpuId##set [1].reg & bit) \
1281	&& !(aHostRaw##set [1].reg & bit) \
1282	&& !(aHostOverride##set [1].reg & bit) \
1283	&& !(aGuestOverride##set [1].reg & bit) \
1284	) \
1285	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1286	} while (0)
1287	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1288
1289	/* For checking guest features if AMD guest CPU. */
1290	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1291	do { \
1292	if ( (aGuestCpuId##set [1].reg & bit) \
1293	&& fGuestAmd \
1294	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1295	&& !(aHostOverride##set [1].reg & bit) \
1296	&& !(aGuestOverride##set [1].reg & bit) \
1297	) \
1298	{ \
1299	if (fStrictCpuIdChecks) \
1300	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1301	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1302	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1303	} \
1304	} while (0)
1305	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1306	do { \
1307	if ( (aGuestCpuId##set [1].reg & bit) \
1308	&& fGuestAmd \
1309	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1310	&& !(aHostOverride##set [1].reg & bit) \
1311	&& !(aGuestOverride##set [1].reg & bit) \
1312	) \
1313	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1314	} while (0)
1315	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1316	do { \
1317	if ( (aGuestCpuId##set [1].reg & bit) \
1318	&& fGuestAmd \
1319	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1320	&& !(aHostOverride##set [1].reg & bit) \
1321	&& !(aGuestOverride##set [1].reg & bit) \
1322	) \
1323	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1324	} while (0)
1325	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1326
1327	/* For checking AMD features which have a corresponding bit in the standard
1328	range. (Intel defines very few bits in the extended feature sets.) */
1329	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1330	do { \
1331	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1332	&& !(fHostAmd \
1333	? aHostRawExt[1].reg & (ExtBit) \
1334	: aHostRawStd[1].reg & (StdBit)) \
1335	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1336	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1337	) \
1338	{ \
1339	if (fStrictCpuIdChecks) \
1340	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1341	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1342	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1343	} \
1344	} while (0)
1345	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1346	do { \
1347	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1348	&& !(fHostAmd \
1349	? aHostRawExt[1].reg & (ExtBit) \
1350	: aHostRawStd[1].reg & (StdBit)) \
1351	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1352	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1353	) \
1354	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1355	} while (0)
1356	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1357	do { \
1358	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1359	&& !(fHostAmd \
1360	? aHostRawExt[1].reg & (ExtBit) \
1361	: aHostRawStd[1].reg & (StdBit)) \
1362	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1363	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1364	) \
1365	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1366	} while (0)
1367	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1368
1369	/*
1370	* Load them into stack buffers first.
1371	*/
1372	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1373	uint32_t cGuestCpuIdStd;
1374	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1375	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1376	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1377	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1378
1379	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1380	uint32_t cGuestCpuIdExt;
1381	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1382	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1383	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1384	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1385
1386	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1387	uint32_t cGuestCpuIdCentaur;
1388	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1389	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1390	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1391	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1392
1393	CPUMCPUID GuestCpuIdDef;
1394	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1395	AssertRCReturn(rc, rc);
1396
1397	CPUMCPUID aRawStd[16];
1398	uint32_t cRawStd;
1399	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1400	if (cRawStd > RT_ELEMENTS(aRawStd))
1401	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1402	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1403
1404	CPUMCPUID aRawExt[32];
1405	uint32_t cRawExt;
1406	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1407	if (cRawExt > RT_ELEMENTS(aRawExt))
1408	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1409	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1410	AssertRCReturn(rc, rc);
1411
1412	/*
1413	* Note that we support restoring less than the current amount of standard
1414	* leaves because we've been allowed more is newer version of VBox.
1415	*
1416	* So, pad new entries with the default.
1417	*/
1418	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1419	aGuestCpuIdStd[i] = GuestCpuIdDef;
1420
1421	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1422	aGuestCpuIdExt[i] = GuestCpuIdDef;
1423
1424	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1425	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1426
1427	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1428	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1429
1430	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1431	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1432
1433	/*
1434	* Get the raw CPU IDs for the current host.
1435	*/
1436	CPUMCPUID aHostRawStd[16];
1437	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1438	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1439
1440	CPUMCPUID aHostRawExt[32];
1441	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1442	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1443
1444	/*
1445	* Get the host and guest overrides so we don't reject the state because
1446	* some feature was enabled thru these interfaces.
1447	* Note! We currently only need the feature leaves, so skip rest.
1448	*/
1449	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1450	CPUMCPUID aGuestOverrideStd[2];
1451	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1452	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1453
1454	CPUMCPUID aGuestOverrideExt[2];
1455	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1456	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1457
1458	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1459	CPUMCPUID aHostOverrideStd[2];
1460	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1461	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1462
1463	CPUMCPUID aHostOverrideExt[2];
1464	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1465	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1466
1467	/*
1468	* This can be skipped.
1469	*/
1470	bool fStrictCpuIdChecks;
1471	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1472
1473
1474
1475	/*
1476	* For raw-mode we'll require that the CPUs are very similar since we don't
1477	* intercept CPUID instructions for user mode applications.
1478	*/
1479	if (!HWACCMIsEnabled(pVM))
1480	{
1481	/* CPUID(0) */
1482	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1483	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1484	&& aHostRawStd[0].edx == aRawStd[0].edx,
1485	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1486	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1487	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1488	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1489	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1490	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1491
1492	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1493
1494	/* CPUID(1).eax */
1495	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1496	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1497	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1498
1499	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1500	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1501	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1502
1503	/* CPUID(1).ecx */
1504	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1505	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1506	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1507	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1508	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1509	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1510	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1511	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1512	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1513	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1514	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1515	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1516	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1517	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1518	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1519	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1520	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1521	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1522	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1523	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1524	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1525	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1526	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1527	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1528	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1529	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1530	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1531	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1532	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1533	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1534	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1535	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1536
1537	/* CPUID(1).edx */
1538	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1539	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1540	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1541	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1542	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1543	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1544	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1545	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1546	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1547	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1548	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1549	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1550	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1551	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1552	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1553	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1554	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1555	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1556	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1557	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1558	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1559	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1560	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1561	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1562	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1563	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1564	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1565	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1566	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1567	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1568	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1569	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1570
1571	/* CPUID(2) - config, mostly about caches. ignore. */
1572	/* CPUID(3) - processor serial number. ignore. */
1573	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1574	/* CPUID(5) - mwait/monitor config. ignore. */
1575	/* CPUID(6) - power management. ignore. */
1576	/* CPUID(7) - ???. ignore. */
1577	/* CPUID(8) - ???. ignore. */
1578	/* CPUID(9) - DCA. ignore for now. */
1579	/* CPUID(a) - PeMo info. ignore for now. */
1580	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1581
1582	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1583	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1584	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1585	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1586	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1587	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1588	{
1589	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1590	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1591	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1592	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1593	}
1594
1595	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1596	Note! Intel have/is marking many of the fields here as reserved. We
1597	will verify them as if it's an AMD CPU. */
1598	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1599	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1600	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
1601	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1602	{
1603	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1604	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1605	&& aHostRawExt[0].edx == aRawExt[0].edx,
1606	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1607	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1608	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1609	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1610
1611	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1612	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1613	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1614	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1615	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1616	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1617
1618	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1619	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1620	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1621	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1622
1623	/* CPUID(0x80000001).ecx */
1624	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1625	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1626	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1627	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1628	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1629	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1630	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1631	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1632	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1633	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1634	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1635	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1636	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1637	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1638	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1639	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1640	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1641	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1642	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1643	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1644	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1645	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1646	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1647	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1648	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1649	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1650	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1651	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1652	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1653	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1654	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1655	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1656
1657	/* CPUID(0x80000001).edx */
1658	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1659	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1660	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1661	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1662	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1663	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1664	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1665	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1666	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1667	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1668	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1669	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1670	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1671	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1672	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1673	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1674	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1675	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1676	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1677	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1678	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1679	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1680	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1681	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1682	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1683	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1684	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1685	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1686	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1687	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1688	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1689	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1690
1691	/** @todo verify the rest as well. */
1692	}
1693	}
1694
1695
1696
1697	/*
1698	* Verify that we can support the features already exposed to the guest on
1699	* this host.
1700	*
1701	* Most of the features we're emulating requires intercepting instruction
1702	* and doing it the slow way, so there is no need to warn when they aren't
1703	* present in the host CPU. Thus we use IGN instead of EMU on these.
1704	*
1705	* Trailing comments:
1706	* "EMU" - Possible to emulate, could be lots of work and very slow.
1707	* "EMU?" - Can this be emulated?
1708	*/
1709	/* CPUID(1).ecx */
1710	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1711	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1712	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1713	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1714	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1715	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1716	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1717	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1718	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1719	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1720	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1721	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1722	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1723	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1724	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1725	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1726	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1727	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1728	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1729	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1730	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1731	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1732	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1733	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1734	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1735	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1736	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1737	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1738	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1739	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1740	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1741	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1742
1743	/* CPUID(1).edx */
1744	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1745	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1746	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1747	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1748	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1749	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1750	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1751	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1752	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1753	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1754	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1755	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1756	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1757	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1758	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1759	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1760	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1761	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1762	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1763	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1764	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1765	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1766	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1767	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1768	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1769	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1770	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1771	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1772	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1773	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1774	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1775	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1776
1777	/* CPUID(0x80000000). */
1778	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1779	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1780	{
1781	/** @todo deal with no 0x80000001 on the host. */
1782	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1783	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1784
1785	/* CPUID(0x80000001).ecx */
1786	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1787	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1788	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1789	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1790	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1791	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1792	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1793	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1794	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1795	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1796	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1797	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1798	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1799	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1800	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1801	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1802	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1803	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1804	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1805	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1806	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1807	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1808	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1809	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1810	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1811	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1812	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1813	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1814	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1815	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1816	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1817	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1818
1819	/* CPUID(0x80000001).edx */
1820	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1821	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1822	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1823	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1824	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1825	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1826	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1827	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1828	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1829	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1830	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1831	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1832	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1833	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1834	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1835	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1836	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1837	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1838	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1839	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1840	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1841	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1842	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1843	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1844	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1845	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1846	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1847	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1848	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1849	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1850	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1851	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1852	}
1853
1854	/*
1855	* We're good, commit the CPU ID leaves.
1856	*/
1857	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1858	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1859	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1860	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1861
1862	#undef CPUID_CHECK_RET
1863	#undef CPUID_CHECK_WRN
1864	#undef CPUID_CHECK2_RET
1865	#undef CPUID_CHECK2_WRN
1866	#undef CPUID_RAW_FEATURE_RET
1867	#undef CPUID_RAW_FEATURE_WRN
1868	#undef CPUID_RAW_FEATURE_IGN
1869	#undef CPUID_GST_FEATURE_RET
1870	#undef CPUID_GST_FEATURE_WRN
1871	#undef CPUID_GST_FEATURE_EMU
1872	#undef CPUID_GST_FEATURE_IGN
1873	#undef CPUID_GST_FEATURE2_RET
1874	#undef CPUID_GST_FEATURE2_WRN
1875	#undef CPUID_GST_FEATURE2_EMU
1876	#undef CPUID_GST_FEATURE2_IGN
1877	#undef CPUID_GST_AMD_FEATURE_RET
1878	#undef CPUID_GST_AMD_FEATURE_WRN
1879	#undef CPUID_GST_AMD_FEATURE_EMU
1880	#undef CPUID_GST_AMD_FEATURE_IGN
1881
1882	return VINF_SUCCESS;
1883	}
1884
1885
1886	/**
1887	* Pass 0 live exec callback.
1888	*
1889	* @returns VINF_SSM_DONT_CALL_AGAIN.
1890	* @param pVM The VM handle.
1891	* @param pSSM The saved state handle.
1892	* @param uPass The pass (0).
1893	*/
1894	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1895	{
1896	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1897	cpumR3SaveCpuId(pVM, pSSM);
1898	return VINF_SSM_DONT_CALL_AGAIN;
1899	}
1900
1901
1902	/**
1903	* Execute state save operation.
1904	*
1905	* @returns VBox status code.
1906	* @param pVM VM Handle.
1907	* @param pSSM SSM operation handle.
1908	*/
1909	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1910	{
1911	/*
1912	* Save.
1913	*/
1914	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1915	{
1916	PVMCPU pVCpu = &pVM->aCpus[i];
1917
1918	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1919	}
1920
1921	SSMR3PutU32(pSSM, pVM->cCpus);
1922	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1923	{
1924	PVMCPU pVCpu = &pVM->aCpus[i];
1925
1926	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1927	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1928	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1929	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1930	}
1931
1932	cpumR3SaveCpuId(pVM, pSSM);
1933	return VINF_SUCCESS;
1934	}
1935
1936
1937	/**
1938	* Load a version 1.6 CPUMCTX structure.
1939	*
1940	* @returns VBox status code.
1941	* @param pVM VM Handle.
1942	* @param pCpumctx16 Version 1.6 CPUMCTX
1943	*/
1944	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1945	{
1946	#define CPUMCTX16_LOADREG(RegName) \
1947	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1948
1949	#define CPUMCTX16_LOADDRXREG(RegName) \
1950	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1951
1952	#define CPUMCTX16_LOADHIDREG(RegName) \
1953	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1954	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1955	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1956
1957	#define CPUMCTX16_LOADSEGREG(RegName) \
1958	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1959	CPUMCTX16_LOADHIDREG(RegName);
1960
1961	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1962
1963	CPUMCTX16_LOADREG(rax);
1964	CPUMCTX16_LOADREG(rbx);
1965	CPUMCTX16_LOADREG(rcx);
1966	CPUMCTX16_LOADREG(rdx);
1967	CPUMCTX16_LOADREG(rdi);
1968	CPUMCTX16_LOADREG(rsi);
1969	CPUMCTX16_LOADREG(rbp);
1970	CPUMCTX16_LOADREG(esp);
1971	CPUMCTX16_LOADREG(rip);
1972	CPUMCTX16_LOADREG(rflags);
1973
1974	CPUMCTX16_LOADSEGREG(cs);
1975	CPUMCTX16_LOADSEGREG(ds);
1976	CPUMCTX16_LOADSEGREG(es);
1977	CPUMCTX16_LOADSEGREG(fs);
1978	CPUMCTX16_LOADSEGREG(gs);
1979	CPUMCTX16_LOADSEGREG(ss);
1980
1981	CPUMCTX16_LOADREG(r8);
1982	CPUMCTX16_LOADREG(r9);
1983	CPUMCTX16_LOADREG(r10);
1984	CPUMCTX16_LOADREG(r11);
1985	CPUMCTX16_LOADREG(r12);
1986	CPUMCTX16_LOADREG(r13);
1987	CPUMCTX16_LOADREG(r14);
1988	CPUMCTX16_LOADREG(r15);
1989
1990	CPUMCTX16_LOADREG(cr0);
1991	CPUMCTX16_LOADREG(cr2);
1992	CPUMCTX16_LOADREG(cr3);
1993	CPUMCTX16_LOADREG(cr4);
1994
1995	CPUMCTX16_LOADDRXREG(0);
1996	CPUMCTX16_LOADDRXREG(1);
1997	CPUMCTX16_LOADDRXREG(2);
1998	CPUMCTX16_LOADDRXREG(3);
1999	CPUMCTX16_LOADDRXREG(4);
2000	CPUMCTX16_LOADDRXREG(5);
2001	CPUMCTX16_LOADDRXREG(6);
2002	CPUMCTX16_LOADDRXREG(7);
2003
2004	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
2005	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
2006	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
2007	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
2008
2009	CPUMCTX16_LOADREG(ldtr);
2010	CPUMCTX16_LOADREG(tr);
2011
2012	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
2013
2014	CPUMCTX16_LOADREG(msrEFER);
2015	CPUMCTX16_LOADREG(msrSTAR);
2016	CPUMCTX16_LOADREG(msrPAT);
2017	CPUMCTX16_LOADREG(msrLSTAR);
2018	CPUMCTX16_LOADREG(msrCSTAR);
2019	CPUMCTX16_LOADREG(msrSFMASK);
2020	CPUMCTX16_LOADREG(msrKERNELGSBASE);
2021
2022	CPUMCTX16_LOADHIDREG(ldtr);
2023	CPUMCTX16_LOADHIDREG(tr);
2024
2025	#undef CPUMCTX16_LOADSEGREG
2026	#undef CPUMCTX16_LOADHIDREG
2027	#undef CPUMCTX16_LOADDRXREG
2028	#undef CPUMCTX16_LOADREG
2029	}
2030
2031
2032	/**
2033	* @copydoc FNSSMINTLOADPREP
2034	*/
2035	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2036	{
2037	pVM->cpum.s.fPendingRestore = true;
2038	return VINF_SUCCESS;
2039	}
2040
2041
2042	/**
2043	* @copydoc FNSSMINTLOADEXEC
2044	*/
2045	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2046	{
2047	/*
2048	* Validate version.
2049	*/
2050	if ( uVersion != CPUM_SAVED_STATE_VERSION
2051	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2052	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2053	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2054	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2055	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2056	{
2057	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2058	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2059	}
2060
2061	if (uPass == SSM_PASS_FINAL)
2062	{
2063	/*
2064	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2065	* really old SSM file versions.)
2066	*/
2067	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2068	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2069	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2070	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2071
2072	/*
2073	* Restore.
2074	*/
2075	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2076	{
2077	PVMCPU pVCpu = &pVM->aCpus[i];
2078	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2079	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
2080
2081	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
2082	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2083	pVCpu->cpum.s.Hyper.esp = uESP;
2084	}
2085
2086	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2087	{
2088	CPUMCTX_VER1_6 cpumctx16;
2089	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
2090	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
2091
2092	/* Save the old cpumctx state into the new one. */
2093	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
2094
2095	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
2096	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
2097	}
2098	else
2099	{
2100	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2101	{
2102	uint32_t cCpus;
2103	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2104	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2105	VERR_SSM_UNEXPECTED_DATA);
2106	}
2107	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2108	\|\| pVM->cCpus == 1,
2109	("cCpus=%u\n", pVM->cCpus),
2110	VERR_SSM_UNEXPECTED_DATA);
2111
2112	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2113	{
2114	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
2115	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
2116	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
2117	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2118	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
2119	}
2120	}
2121
2122	/* Older states does not set CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID for
2123	raw-mode guest, so we have to do it ourselves. */
2124	if ( uVersion <= CPUM_SAVED_STATE_VERSION_VER3_2
2125	&& !HWACCMIsEnabled(pVM))
2126	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2127	pVM->aCpus[iCpu].cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2128	}
2129
2130	pVM->cpum.s.fPendingRestore = false;
2131
2132	/*
2133	* Guest CPUIDs.
2134	*/
2135	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2136	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2137
2138	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2139	* actually required. */
2140
2141	/*
2142	* Restore the CPUID leaves.
2143	*
2144	* Note that we support restoring less than the current amount of standard
2145	* leaves because we've been allowed more is newer version of VBox.
2146	*/
2147	uint32_t cElements;
2148	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2149	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2150	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2151	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2152
2153	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2154	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2155	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2156	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2157
2158	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2159	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2160	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2161	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2162
2163	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2164
2165	/*
2166	* Check that the basic cpuid id information is unchanged.
2167	*/
2168	/** @todo we should check the 64 bits capabilities too! */
2169	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2170	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2171	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2172	uint32_t au32CpuIdSaved[8];
2173	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2174	if (RT_SUCCESS(rc))
2175	{
2176	/* Ignore CPU stepping. */
2177	au32CpuId[4] &= 0xfffffff0;
2178	au32CpuIdSaved[4] &= 0xfffffff0;
2179
2180	/* Ignore APIC ID (AMD specs). */
2181	au32CpuId[5] &= ~0xff000000;
2182	au32CpuIdSaved[5] &= ~0xff000000;
2183
2184	/* Ignore the number of Logical CPUs (AMD specs). */
2185	au32CpuId[5] &= ~0x00ff0000;
2186	au32CpuIdSaved[5] &= ~0x00ff0000;
2187
2188	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2189	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2190	\| X86_CPUID_FEATURE_ECX_VMX
2191	\| X86_CPUID_FEATURE_ECX_SMX
2192	\| X86_CPUID_FEATURE_ECX_EST
2193	\| X86_CPUID_FEATURE_ECX_TM2
2194	\| X86_CPUID_FEATURE_ECX_CNTXID
2195	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2196	\| X86_CPUID_FEATURE_ECX_PDCM
2197	\| X86_CPUID_FEATURE_ECX_DCA
2198	\| X86_CPUID_FEATURE_ECX_X2APIC
2199	);
2200	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2201	\| X86_CPUID_FEATURE_ECX_VMX
2202	\| X86_CPUID_FEATURE_ECX_SMX
2203	\| X86_CPUID_FEATURE_ECX_EST
2204	\| X86_CPUID_FEATURE_ECX_TM2
2205	\| X86_CPUID_FEATURE_ECX_CNTXID
2206	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2207	\| X86_CPUID_FEATURE_ECX_PDCM
2208	\| X86_CPUID_FEATURE_ECX_DCA
2209	\| X86_CPUID_FEATURE_ECX_X2APIC
2210	);
2211
2212	/* Make sure we don't forget to update the masks when enabling
2213	* features in the future.
2214	*/
2215	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2216	( X86_CPUID_FEATURE_ECX_DTES64
2217	\| X86_CPUID_FEATURE_ECX_VMX
2218	\| X86_CPUID_FEATURE_ECX_SMX
2219	\| X86_CPUID_FEATURE_ECX_EST
2220	\| X86_CPUID_FEATURE_ECX_TM2
2221	\| X86_CPUID_FEATURE_ECX_CNTXID
2222	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2223	\| X86_CPUID_FEATURE_ECX_PDCM
2224	\| X86_CPUID_FEATURE_ECX_DCA
2225	\| X86_CPUID_FEATURE_ECX_X2APIC
2226	)));
2227	/* do the compare */
2228	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2229	{
2230	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2231	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2232	"Saved=%.*Rhxs\n"
2233	"Real =%.*Rhxs\n",
2234	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2235	sizeof(au32CpuId), au32CpuId));
2236	else
2237	{
2238	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2239	"Saved=%.*Rhxs\n"
2240	"Real =%.*Rhxs\n",
2241	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2242	sizeof(au32CpuId), au32CpuId));
2243	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2244	}
2245	}
2246	}
2247
2248	return rc;
2249	}
2250
2251
2252	/**
2253	* @copydoc FNSSMINTLOADPREP
2254	*/
2255	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2256	{
2257	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2258	return VINF_SUCCESS;
2259
2260	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2261	if (pVM->cpum.s.fPendingRestore)
2262	{
2263	LogRel(("CPUM: Missing state!\n"));
2264	return VERR_INTERNAL_ERROR_2;
2265	}
2266
2267	/* Notify PGM of the NXE states in case they've changed. */
2268	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2269	PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2270	return VINF_SUCCESS;
2271	}
2272
2273
2274	/**
2275	* Checks if the CPUM state restore is still pending.
2276	*
2277	* @returns true / false.
2278	* @param pVM The VM handle.
2279	*/
2280	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2281	{
2282	return pVM->cpum.s.fPendingRestore;
2283	}
2284
2285
2286	/**
2287	* Formats the EFLAGS value into mnemonics.
2288	*
2289	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2290	* @param efl The EFLAGS value.
2291	*/
2292	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2293	{
2294	/*
2295	* Format the flags.
2296	*/
2297	static const struct
2298	{
2299	const char pszSet; const char pszClear; uint32_t fFlag;
2300	} s_aFlags[] =
2301	{
2302	{ "vip",NULL, X86_EFL_VIP },
2303	{ "vif",NULL, X86_EFL_VIF },
2304	{ "ac", NULL, X86_EFL_AC },
2305	{ "vm", NULL, X86_EFL_VM },
2306	{ "rf", NULL, X86_EFL_RF },
2307	{ "nt", NULL, X86_EFL_NT },
2308	{ "ov", "nv", X86_EFL_OF },
2309	{ "dn", "up", X86_EFL_DF },
2310	{ "ei", "di", X86_EFL_IF },
2311	{ "tf", NULL, X86_EFL_TF },
2312	{ "nt", "pl", X86_EFL_SF },
2313	{ "nz", "zr", X86_EFL_ZF },
2314	{ "ac", "na", X86_EFL_AF },
2315	{ "po", "pe", X86_EFL_PF },
2316	{ "cy", "nc", X86_EFL_CF },
2317	};
2318	char *psz = pszEFlags;
2319	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2320	{
2321	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2322	if (pszAdd)
2323	{
2324	strcpy(psz, pszAdd);
2325	psz += strlen(pszAdd);
2326	*psz++ = ' ';
2327	}
2328	}
2329	psz[-1] = '\0';
2330	}
2331
2332
2333	/**
2334	* Formats a full register dump.
2335	*
2336	* @param pVM VM Handle.
2337	* @param pCtx The context to format.
2338	* @param pCtxCore The context core to format.
2339	* @param pHlp Output functions.
2340	* @param enmType The dump type.
2341	* @param pszPrefix Register name prefix.
2342	*/
2343	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2344	{
2345	/*
2346	* Format the EFLAGS.
2347	*/
2348	uint32_t efl = pCtxCore->eflags.u32;
2349	char szEFlags[80];
2350	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2351
2352	/*
2353	* Format the registers.
2354	*/
2355	switch (enmType)
2356	{
2357	case CPUMDUMPTYPE_TERSE:
2358	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2359	pHlp->pfnPrintf(pHlp,
2360	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2361	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2362	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2363	"%sr14=%016RX64 %sr15=%016RX64\n"
2364	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2365	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2366	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2367	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2368	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2369	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2370	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2371	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2372	else
2373	pHlp->pfnPrintf(pHlp,
2374	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2375	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2376	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2377	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2378	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2379	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2380	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2381	break;
2382
2383	case CPUMDUMPTYPE_DEFAULT:
2384	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2385	pHlp->pfnPrintf(pHlp,
2386	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2387	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2388	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2389	"%sr14=%016RX64 %sr15=%016RX64\n"
2390	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2391	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2392	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2393	,
2394	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2395	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2396	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2397	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2398	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2399	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2400	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2401	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2402	else
2403	pHlp->pfnPrintf(pHlp,
2404	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2405	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2406	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2407	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2408	,
2409	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2410	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2411	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2412	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2413	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2414	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2415	break;
2416
2417	case CPUMDUMPTYPE_VERBOSE:
2418	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2419	pHlp->pfnPrintf(pHlp,
2420	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2421	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2422	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2423	"%sr14=%016RX64 %sr15=%016RX64\n"
2424	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2425	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2426	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2427	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2428	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2429	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2430	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2431	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2432	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2433	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2434	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2435	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2436	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2437	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2438	,
2439	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2440	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2441	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2442	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2443	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2444	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2445	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2446	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2447	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2448	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2449	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2450	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2451	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2452	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2453	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2454	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2455	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2456	else
2457	pHlp->pfnPrintf(pHlp,
2458	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2459	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2460	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2461	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2462	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2463	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2464	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2465	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2466	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2467	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2468	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2469	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2470	,
2471	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2472	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2473	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2474	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2475	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2476	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2477	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2478	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2479	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2480	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2481	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2482	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2483
2484	pHlp->pfnPrintf(pHlp,
2485	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2486	"%sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2487	,
2488	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2489	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2490	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
2491	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2492	);
2493	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2494	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2495	{
2496	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2497	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2498	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2499	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2500	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2501	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2502	/** @todo This isn't entirenly correct and needs more work! */
2503	pHlp->pfnPrintf(pHlp,
2504	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2505	pszPrefix, iST, pszPrefix, iFPR,
2506	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2507	uTag, chSign, iInteger, u64Fraction, uExponent);
2508	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2509	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2510	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2511	else
2512	pHlp->pfnPrintf(pHlp, "\n");
2513	}
2514	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2515	pHlp->pfnPrintf(pHlp,
2516	iXMM & 1
2517	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2518	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2519	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2520	pCtx->fpu.aXMM[iXMM].au32[3],
2521	pCtx->fpu.aXMM[iXMM].au32[2],
2522	pCtx->fpu.aXMM[iXMM].au32[1],
2523	pCtx->fpu.aXMM[iXMM].au32[0]);
2524	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2525	if (pCtx->fpu.au32RsrvdRest[i])
2526	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2527	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2528
2529	pHlp->pfnPrintf(pHlp,
2530	"%sEFER =%016RX64\n"
2531	"%sPAT =%016RX64\n"
2532	"%sSTAR =%016RX64\n"
2533	"%sCSTAR =%016RX64\n"
2534	"%sLSTAR =%016RX64\n"
2535	"%sSFMASK =%016RX64\n"
2536	"%sKERNELGSBASE =%016RX64\n",
2537	pszPrefix, pCtx->msrEFER,
2538	pszPrefix, pCtx->msrPAT,
2539	pszPrefix, pCtx->msrSTAR,
2540	pszPrefix, pCtx->msrCSTAR,
2541	pszPrefix, pCtx->msrLSTAR,
2542	pszPrefix, pCtx->msrSFMASK,
2543	pszPrefix, pCtx->msrKERNELGSBASE);
2544	break;
2545	}
2546	}
2547
2548
2549	/**
2550	* Display all cpu states and any other cpum info.
2551	*
2552	* @param pVM VM Handle.
2553	* @param pHlp The info helper functions.
2554	* @param pszArgs Arguments, ignored.
2555	*/
2556	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2557	{
2558	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2559	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2560	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2561	cpumR3InfoHost(pVM, pHlp, pszArgs);
2562	}
2563
2564
2565	/**
2566	* Parses the info argument.
2567	*
2568	* The argument starts with 'verbose', 'terse' or 'default' and then
2569	* continues with the comment string.
2570	*
2571	* @param pszArgs The pointer to the argument string.
2572	* @param penmType Where to store the dump type request.
2573	* @param ppszComment Where to store the pointer to the comment string.
2574	*/
2575	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2576	{
2577	if (!pszArgs)
2578	{
2579	*penmType = CPUMDUMPTYPE_DEFAULT;
2580	*ppszComment = "";
2581	}
2582	else
2583	{
2584	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2585	{
2586	pszArgs += 5;
2587	*penmType = CPUMDUMPTYPE_VERBOSE;
2588	}
2589	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2590	{
2591	pszArgs += 5;
2592	*penmType = CPUMDUMPTYPE_TERSE;
2593	}
2594	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2595	{
2596	pszArgs += 7;
2597	*penmType = CPUMDUMPTYPE_DEFAULT;
2598	}
2599	else
2600	*penmType = CPUMDUMPTYPE_DEFAULT;
2601	*ppszComment = RTStrStripL(pszArgs);
2602	}
2603	}
2604
2605
2606	/**
2607	* Display the guest cpu state.
2608	*
2609	* @param pVM VM Handle.
2610	* @param pHlp The info helper functions.
2611	* @param pszArgs Arguments, ignored.
2612	*/
2613	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2614	{
2615	CPUMDUMPTYPE enmType;
2616	const char *pszComment;
2617	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2618
2619	/* @todo SMP support! */
2620	PVMCPU pVCpu = VMMGetCpu(pVM);
2621	if (!pVCpu)
2622	pVCpu = &pVM->aCpus[0];
2623
2624	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2625
2626	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2627	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2628	}
2629
2630
2631	/**
2632	* Display the current guest instruction
2633	*
2634	* @param pVM VM Handle.
2635	* @param pHlp The info helper functions.
2636	* @param pszArgs Arguments, ignored.
2637	*/
2638	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2639	{
2640	char szInstruction[256];
2641	/* @todo SMP support! */
2642	PVMCPU pVCpu = VMMGetCpu(pVM);
2643	if (!pVCpu)
2644	pVCpu = &pVM->aCpus[0];
2645
2646	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2647	if (RT_SUCCESS(rc))
2648	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2649	}
2650
2651
2652	/**
2653	* Display the hypervisor cpu state.
2654	*
2655	* @param pVM VM Handle.
2656	* @param pHlp The info helper functions.
2657	* @param pszArgs Arguments, ignored.
2658	*/
2659	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2660	{
2661	CPUMDUMPTYPE enmType;
2662	const char *pszComment;
2663	/* @todo SMP */
2664	PVMCPU pVCpu = &pVM->aCpus[0];
2665
2666	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2667	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2668	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2669	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2670	}
2671
2672
2673	/**
2674	* Display the host cpu state.
2675	*
2676	* @param pVM VM Handle.
2677	* @param pHlp The info helper functions.
2678	* @param pszArgs Arguments, ignored.
2679	*/
2680	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2681	{
2682	CPUMDUMPTYPE enmType;
2683	const char *pszComment;
2684	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2685	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2686
2687	/*
2688	* Format the EFLAGS.
2689	*/
2690	/* @todo SMP */
2691	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2692	#if HC_ARCH_BITS == 32
2693	uint32_t efl = pCtx->eflags.u32;
2694	#else
2695	uint64_t efl = pCtx->rflags;
2696	#endif
2697	char szEFlags[80];
2698	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2699
2700	/*
2701	* Format the registers.
2702	*/
2703	#if HC_ARCH_BITS == 32
2704	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2705	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2706	# endif
2707	{
2708	pHlp->pfnPrintf(pHlp,
2709	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2710	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2711	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2712	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2713	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2714	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2715	,
2716	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2717	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2718	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2719	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2720	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2721	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2722	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2723	}
2724	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2725	else
2726	# endif
2727	#endif
2728	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2729	{
2730	pHlp->pfnPrintf(pHlp,
2731	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2732	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2733	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2734	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2735	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2736	"r14=%016RX64 r15=%016RX64\n"
2737	"iopl=%d %31s\n"
2738	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2739	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2740	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2741	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2742	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2743	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2744	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2745	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2746	,
2747	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2748	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2749	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2750	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2751	pCtx->r11, pCtx->r12, pCtx->r13,
2752	pCtx->r14, pCtx->r15,
2753	X86_EFL_GET_IOPL(efl), szEFlags,
2754	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2755	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2756	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2757	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2758	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2759	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2760	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2761	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2762	}
2763	#endif
2764	}
2765
2766
2767	/**
2768	* Get L1 cache / TLS associativity.
2769	*/
2770	static const char getCacheAss(unsigned u, char pszBuf)
2771	{
2772	if (u == 0)
2773	return "res0 ";
2774	if (u == 1)
2775	return "direct";
2776	if (u == 255)
2777	return "fully";
2778	if (u >= 256)
2779	return "???";
2780
2781	RTStrPrintf(pszBuf, 16, "%d way", u);
2782	return pszBuf;
2783	}
2784
2785
2786	/**
2787	* Get L2 cache associativity.
2788	*/
2789	const char *getL2CacheAss(unsigned u)
2790	{
2791	switch (u)
2792	{
2793	case 0: return "off ";
2794	case 1: return "direct";
2795	case 2: return "2 way ";
2796	case 3: return "res3 ";
2797	case 4: return "4 way ";
2798	case 5: return "res5 ";
2799	case 6: return "8 way ";
2800	case 7: return "res7 ";
2801	case 8: return "16 way";
2802	case 9: return "res9 ";
2803	case 10: return "res10 ";
2804	case 11: return "res11 ";
2805	case 12: return "res12 ";
2806	case 13: return "res13 ";
2807	case 14: return "res14 ";
2808	case 15: return "fully ";
2809	default: return "????";
2810	}
2811	}
2812
2813
2814	/**
2815	* Display the guest CpuId leaves.
2816	*
2817	* @param pVM VM Handle.
2818	* @param pHlp The info helper functions.
2819	* @param pszArgs "terse", "default" or "verbose".
2820	*/
2821	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2822	{
2823	/*
2824	* Parse the argument.
2825	*/
2826	unsigned iVerbosity = 1;
2827	if (pszArgs)
2828	{
2829	pszArgs = RTStrStripL(pszArgs);
2830	if (!strcmp(pszArgs, "terse"))
2831	iVerbosity--;
2832	else if (!strcmp(pszArgs, "verbose"))
2833	iVerbosity++;
2834	}
2835
2836	/*
2837	* Start cracking.
2838	*/
2839	CPUMCPUID Host;
2840	CPUMCPUID Guest;
2841	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2842
2843	pHlp->pfnPrintf(pHlp,
2844	" RAW Standard CPUIDs\n"
2845	" Function eax ebx ecx edx\n");
2846	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2847	{
2848	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2849	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2850
2851	pHlp->pfnPrintf(pHlp,
2852	"Gst: %08x %08x %08x %08x %08x%s\n"
2853	"Hst: %08x %08x %08x %08x\n",
2854	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2855	i <= cStdMax ? "" : "*",
2856	Host.eax, Host.ebx, Host.ecx, Host.edx);
2857	}
2858
2859	/*
2860	* If verbose, decode it.
2861	*/
2862	if (iVerbosity)
2863	{
2864	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2865	pHlp->pfnPrintf(pHlp,
2866	"Name: %.04s%.04s%.04s\n"
2867	"Supports: 0-%x\n",
2868	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2869	}
2870
2871	/*
2872	* Get Features.
2873	*/
2874	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2875	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2876	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2877	if (cStdMax >= 1 && iVerbosity)
2878	{
2879	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
2880
2881	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2882	uint32_t uEAX = Guest.eax;
2883
2884	pHlp->pfnPrintf(pHlp,
2885	"Family: %d \tExtended: %d \tEffective: %d\n"
2886	"Model: %d \tExtended: %d \tEffective: %d\n"
2887	"Stepping: %d\n"
2888	"Type: %d (%s)\n"
2889	"APIC ID: %#04x\n"
2890	"Logical CPUs: %d\n"
2891	"CLFLUSH Size: %d\n"
2892	"Brand ID: %#04x\n",
2893	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2894	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2895	ASMGetCpuStepping(uEAX),
2896	(uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
2897	(Guest.ebx >> 24) & 0xff,
2898	(Guest.ebx >> 16) & 0xff,
2899	(Guest.ebx >> 8) & 0xff,
2900	(Guest.ebx >> 0) & 0xff);
2901	if (iVerbosity == 1)
2902	{
2903	uint32_t uEDX = Guest.edx;
2904	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2905	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2906	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2907	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2908	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2909	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2910	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2911	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2912	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2913	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2914	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2915	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2916	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2917	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2918	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2919	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2920	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2921	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2922	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2923	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2924	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2925	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2926	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2927	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2928	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2929	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2930	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2931	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2932	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2933	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2934	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2935	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2936	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2937	pHlp->pfnPrintf(pHlp, "\n");
2938
2939	uint32_t uECX = Guest.ecx;
2940	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2941	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2942	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2943	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2944	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2945	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2946	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2947	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2948	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2949	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2950	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2951	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2952	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2953	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2954	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2955	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2956	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2957	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2958	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
2959	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2960	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
2961	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
2962	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2963	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2964	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2965	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
2966	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2967	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2968	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2969	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2970	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2971	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2972	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2973	pHlp->pfnPrintf(pHlp, "\n");
2974	}
2975	else
2976	{
2977	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2978
2979	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2980	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2981	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2982	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2983
2984	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2985	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2986	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2987	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2988	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2989	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2990	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2991	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2992	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2993	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2994	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2995	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2996	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2997	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2998	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
2999	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3000	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3001	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3002	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3003	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3004	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3005	pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3006	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3007	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3008	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3009	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3010	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3011	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3012	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3013	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3014	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3015	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3016	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3017
3018	pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3019	pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3020	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3021	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3022	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3023	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3024	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3025	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3026	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3027	pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3028	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3029	pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3030	pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3031	pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3032	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3033	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3034	pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3035	pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3036	pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3037	pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3038	pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3039	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3040	pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3041	pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3042	pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3043	pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3044	pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3045	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3046	pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3047	pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3048	pHlp->pfnPrintf(pHlp, "31 - Reserved (always 0) = %d (%d)\n", EcxGuest.u1Reserved4, EcxHost.u1Reserved4);
3049	}
3050	}
3051	if (cStdMax >= 2 && iVerbosity)
3052	{
3053	/** @todo */
3054	}
3055
3056	/*
3057	* Extended.
3058	* Implemented after AMD specs.
3059	*/
3060	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3061
3062	pHlp->pfnPrintf(pHlp,
3063	"\n"
3064	" RAW Extended CPUIDs\n"
3065	" Function eax ebx ecx edx\n");
3066	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3067	{
3068	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3069	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3070
3071	pHlp->pfnPrintf(pHlp,
3072	"Gst: %08x %08x %08x %08x %08x%s\n"
3073	"Hst: %08x %08x %08x %08x\n",
3074	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3075	i <= cExtMax ? "" : "*",
3076	Host.eax, Host.ebx, Host.ecx, Host.edx);
3077	}
3078
3079	/*
3080	* Understandable output
3081	*/
3082	if (iVerbosity)
3083	{
3084	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3085	pHlp->pfnPrintf(pHlp,
3086	"Ext Name: %.4s%.4s%.4s\n"
3087	"Ext Supports: 0x80000000-%#010x\n",
3088	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3089	}
3090
3091	if (iVerbosity && cExtMax >= 1)
3092	{
3093	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3094	uint32_t uEAX = Guest.eax;
3095	pHlp->pfnPrintf(pHlp,
3096	"Family: %d \tExtended: %d \tEffective: %d\n"
3097	"Model: %d \tExtended: %d \tEffective: %d\n"
3098	"Stepping: %d\n"
3099	"Brand ID: %#05x\n",
3100	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3101	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3102	ASMGetCpuStepping(uEAX),
3103	Guest.ebx & 0xfff);
3104
3105	if (iVerbosity == 1)
3106	{
3107	uint32_t uEDX = Guest.edx;
3108	pHlp->pfnPrintf(pHlp, "Features EDX: ");
3109	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3110	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3111	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3112	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3113	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3114	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3115	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3116	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3117	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3118	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3119	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3120	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3121	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3122	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3123	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3124	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3125	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3126	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3127	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3128	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3129	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3130	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3131	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3132	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3133	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3134	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3135	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3136	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3137	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3138	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3139	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3140	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3141	pHlp->pfnPrintf(pHlp, "\n");
3142
3143	uint32_t uECX = Guest.ecx;
3144	pHlp->pfnPrintf(pHlp, "Features ECX: ");
3145	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3146	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3147	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3148	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3149	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3150	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3151	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3152	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3153	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3154	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3155	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3156	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3157	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3158	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3159	for (unsigned iBit = 5; iBit < 32; iBit++)
3160	if (uECX & RT_BIT(iBit))
3161	pHlp->pfnPrintf(pHlp, " %d", iBit);
3162	pHlp->pfnPrintf(pHlp, "\n");
3163	}
3164	else
3165	{
3166	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3167
3168	uint32_t uEdxGst = Guest.edx;
3169	uint32_t uEdxHst = Host.edx;
3170	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3171	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3172	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3173	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3174	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3175	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3176	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3177	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3178	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3179	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3180	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3181	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3182	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3183	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3184	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3185	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3186	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3187	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3188	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3189	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3190	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3191	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3192	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3193	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3194	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3195	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3196	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3197	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3198	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3199	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3200	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3201	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3202	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3203
3204	uint32_t uEcxGst = Guest.ecx;
3205	uint32_t uEcxHst = Host.ecx;
3206	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3207	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3208	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3209	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3210	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3211	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3212	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3213	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3214	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3215	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3216	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3217	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3218	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3219	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3220	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3221	}
3222	}
3223
3224	if (iVerbosity && cExtMax >= 2)
3225	{
3226	char szString[443+1] = {0};
3227	uint32_t pu32 = (uint32_t )szString;
3228	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3229	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3230	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3231	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3232	if (cExtMax >= 3)
3233	{
3234	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3235	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3236	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3237	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3238	}
3239	if (cExtMax >= 4)
3240	{
3241	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3242	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3243	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3244	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3245	}
3246	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3247	}
3248
3249	if (iVerbosity && cExtMax >= 5)
3250	{
3251	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3252	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3253	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3254	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3255	char sz1[32];
3256	char sz2[32];
3257
3258	pHlp->pfnPrintf(pHlp,
3259	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3260	"TLB 2/4M Data: %s %3d entries\n",
3261	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3262	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3263	pHlp->pfnPrintf(pHlp,
3264	"TLB 4K Instr/Uni: %s %3d entries\n"
3265	"TLB 4K Data: %s %3d entries\n",
3266	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3267	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3268	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3269	"L1 Instr Cache Lines Per Tag: %d\n"
3270	"L1 Instr Cache Associativity: %s\n"
3271	"L1 Instr Cache Size: %d KB\n",
3272	(uEDX >> 0) & 0xff,
3273	(uEDX >> 8) & 0xff,
3274	getCacheAss((uEDX >> 16) & 0xff, sz1),
3275	(uEDX >> 24) & 0xff);
3276	pHlp->pfnPrintf(pHlp,
3277	"L1 Data Cache Line Size: %d bytes\n"
3278	"L1 Data Cache Lines Per Tag: %d\n"
3279	"L1 Data Cache Associativity: %s\n"
3280	"L1 Data Cache Size: %d KB\n",
3281	(uECX >> 0) & 0xff,
3282	(uECX >> 8) & 0xff,
3283	getCacheAss((uECX >> 16) & 0xff, sz1),
3284	(uECX >> 24) & 0xff);
3285	}
3286
3287	if (iVerbosity && cExtMax >= 6)
3288	{
3289	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3290	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3291	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3292
3293	pHlp->pfnPrintf(pHlp,
3294	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3295	"L2 TLB 2/4M Data: %s %4d entries\n",
3296	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3297	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3298	pHlp->pfnPrintf(pHlp,
3299	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3300	"L2 TLB 4K Data: %s %4d entries\n",
3301	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3302	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3303	pHlp->pfnPrintf(pHlp,
3304	"L2 Cache Line Size: %d bytes\n"
3305	"L2 Cache Lines Per Tag: %d\n"
3306	"L2 Cache Associativity: %s\n"
3307	"L2 Cache Size: %d KB\n",
3308	(uEDX >> 0) & 0xff,
3309	(uEDX >> 8) & 0xf,
3310	getL2CacheAss((uEDX >> 12) & 0xf),
3311	(uEDX >> 16) & 0xffff);
3312	}
3313
3314	if (iVerbosity && cExtMax >= 7)
3315	{
3316	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3317
3318	pHlp->pfnPrintf(pHlp, "APM Features: ");
3319	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3320	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3321	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3322	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3323	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3324	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3325	for (unsigned iBit = 6; iBit < 32; iBit++)
3326	if (uEDX & RT_BIT(iBit))
3327	pHlp->pfnPrintf(pHlp, " %d", iBit);
3328	pHlp->pfnPrintf(pHlp, "\n");
3329	}
3330
3331	if (iVerbosity && cExtMax >= 8)
3332	{
3333	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3334	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3335
3336	pHlp->pfnPrintf(pHlp,
3337	"Physical Address Width: %d bits\n"
3338	"Virtual Address Width: %d bits\n"
3339	"Guest Physical Address Width: %d bits\n",
3340	(uEAX >> 0) & 0xff,
3341	(uEAX >> 8) & 0xff,
3342	(uEAX >> 16) & 0xff);
3343	pHlp->pfnPrintf(pHlp,
3344	"Physical Core Count: %d\n",
3345	(uECX >> 0) & 0xff);
3346	}
3347
3348
3349	/*
3350	* Centaur.
3351	*/
3352	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3353
3354	pHlp->pfnPrintf(pHlp,
3355	"\n"
3356	" RAW Centaur CPUIDs\n"
3357	" Function eax ebx ecx edx\n");
3358	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3359	{
3360	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3361	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3362
3363	pHlp->pfnPrintf(pHlp,
3364	"Gst: %08x %08x %08x %08x %08x%s\n"
3365	"Hst: %08x %08x %08x %08x\n",
3366	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3367	i <= cCentaurMax ? "" : "*",
3368	Host.eax, Host.ebx, Host.ecx, Host.edx);
3369	}
3370
3371	/*
3372	* Understandable output
3373	*/
3374	if (iVerbosity)
3375	{
3376	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3377	pHlp->pfnPrintf(pHlp,
3378	"Centaur Supports: 0xc0000000-%#010x\n",
3379	Guest.eax);
3380	}
3381
3382	if (iVerbosity && cCentaurMax >= 1)
3383	{
3384	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3385	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3386	uint32_t uEdxHst = Host.edx;
3387
3388	if (iVerbosity == 1)
3389	{
3390	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3391	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3392	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3393	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3394	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3395	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3396	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3397	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3398	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3399	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3400	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3401	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3402	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3403	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3404	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3405	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3406	for (unsigned iBit = 14; iBit < 32; iBit++)
3407	if (uEdxGst & RT_BIT(iBit))
3408	pHlp->pfnPrintf(pHlp, " %d", iBit);
3409	pHlp->pfnPrintf(pHlp, "\n");
3410	}
3411	else
3412	{
3413	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3414	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3415	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3416	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3417	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3418	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3419	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3420	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3421	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3422	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3423	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3424	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3425	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3426	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3427	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3428	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3429	for (unsigned iBit = 14; iBit < 32; iBit++)
3430	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3431	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3432	pHlp->pfnPrintf(pHlp, "\n");
3433	}
3434	}
3435	}
3436
3437
3438	/**
3439	* Structure used when disassembling and instructions in DBGF.
3440	* This is used so the reader function can get the stuff it needs.
3441	*/
3442	typedef struct CPUMDISASSTATE
3443	{
3444	/** Pointer to the CPU structure. */
3445	PDISCPUSTATE pCpu;
3446	/** The VM handle. */
3447	PVM pVM;
3448	/** The VMCPU handle. */
3449	PVMCPU pVCpu;
3450	/** Pointer to the first byte in the segment. */
3451	RTGCUINTPTR GCPtrSegBase;
3452	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3453	RTGCUINTPTR GCPtrSegEnd;
3454	/** The size of the segment minus 1. */
3455	RTGCUINTPTR cbSegLimit;
3456	/** Pointer to the current page - R3 Ptr. */
3457	void const *pvPageR3;
3458	/** Pointer to the current page - GC Ptr. */
3459	RTGCPTR pvPageGC;
3460	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3461	PGMPAGEMAPLOCK PageMapLock;
3462	/** Whether the PageMapLock is valid or not. */
3463	bool fLocked;
3464	/** 64 bits mode or not. */
3465	bool f64Bits;
3466	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3467
3468
3469	/**
3470	* Instruction reader.
3471	*
3472	* @returns VBox status code.
3473	* @param PtrSrc Address to read from.
3474	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3475	* @param pu8Dst Where to store the bytes.
3476	* @param cbRead Number of bytes to read.
3477	* @param uDisCpu Pointer to the disassembler cpu state.
3478	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3479	*/
3480	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3481	{
3482	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3483	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3484	Assert(cbRead > 0);
3485	for (;;)
3486	{
3487	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3488
3489	/* Need to update the page translation? */
3490	if ( !pState->pvPageR3
3491	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3492	{
3493	int rc = VINF_SUCCESS;
3494
3495	/* translate the address */
3496	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3497	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3498	&& !HWACCMIsEnabled(pState->pVM))
3499	{
3500	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3501	if (!pState->pvPageR3)
3502	rc = VERR_INVALID_POINTER;
3503	}
3504	else
3505	{
3506	/* Release mapping lock previously acquired. */
3507	if (pState->fLocked)
3508	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3509	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3510	pState->fLocked = RT_SUCCESS_NP(rc);
3511	}
3512	if (RT_FAILURE(rc))
3513	{
3514	pState->pvPageR3 = NULL;
3515	return rc;
3516	}
3517	}
3518
3519	/* check the segment limit */
3520	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3521	return VERR_OUT_OF_SELECTOR_BOUNDS;
3522
3523	/* calc how much we can read */
3524	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3525	if (!pState->f64Bits)
3526	{
3527	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3528	if (cb > cbSeg && cbSeg)
3529	cb = cbSeg;
3530	}
3531	if (cb > cbRead)
3532	cb = cbRead;
3533
3534	/* read and advance */
3535	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3536	cbRead -= cb;
3537	if (!cbRead)
3538	return VINF_SUCCESS;
3539	pu8Dst += cb;
3540	PtrSrc += cb;
3541	}
3542	}
3543
3544
3545	/**
3546	* Disassemble an instruction and return the information in the provided structure.
3547	*
3548	* @returns VBox status code.
3549	* @param pVM VM Handle
3550	* @param pVCpu VMCPU Handle
3551	* @param pCtx CPU context
3552	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3553	* @param pCpu Disassembly state
3554	* @param pszPrefix String prefix for logging (debug only)
3555	*
3556	*/
3557	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3558	{
3559	CPUMDISASSTATE State;
3560	int rc;
3561
3562	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3563	State.pCpu = pCpu;
3564	State.pvPageGC = 0;
3565	State.pvPageR3 = NULL;
3566	State.pVM = pVM;
3567	State.pVCpu = pVCpu;
3568	State.fLocked = false;
3569	State.f64Bits = false;
3570
3571	/*
3572	* Get selector information.
3573	*/
3574	if ( (pCtx->cr0 & X86_CR0_PE)
3575	&& pCtx->eflags.Bits.u1VM == 0)
3576	{
3577	if (CPUMAreHiddenSelRegsValid(pVCpu))
3578	{
3579	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3580	State.GCPtrSegBase = pCtx->csHid.u64Base;
3581	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3582	State.cbSegLimit = pCtx->csHid.u32Limit;
3583	pCpu->mode = (State.f64Bits)
3584	? CPUMODE_64BIT
3585	: pCtx->csHid.Attr.n.u1DefBig
3586	? CPUMODE_32BIT
3587	: CPUMODE_16BIT;
3588	}
3589	else
3590	{
3591	DBGFSELINFO SelInfo;
3592
3593	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3594	if (RT_FAILURE(rc))
3595	{
3596	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3597	return rc;
3598	}
3599
3600	/*
3601	* Validate the selector.
3602	*/
3603	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3604	if (RT_FAILURE(rc))
3605	{
3606	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3607	return rc;
3608	}
3609	State.GCPtrSegBase = SelInfo.GCPtrBase;
3610	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3611	State.cbSegLimit = SelInfo.cbLimit;
3612	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3613	}
3614	}
3615	else
3616	{
3617	/* real or V86 mode */
3618	pCpu->mode = CPUMODE_16BIT;
3619	State.GCPtrSegBase = pCtx->cs * 16;
3620	State.GCPtrSegEnd = 0xFFFFFFFF;
3621	State.cbSegLimit = 0xFFFFFFFF;
3622	}
3623
3624	/*
3625	* Disassemble the instruction.
3626	*/
3627	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3628	pCpu->apvUserData[0] = &State;
3629
3630	uint32_t cbInstr;
3631	#ifndef LOG_ENABLED
3632	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3633	if (RT_SUCCESS(rc))
3634	{
3635	#else
3636	char szOutput[160];
3637	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3638	if (RT_SUCCESS(rc))
3639	{
3640	/* log it */
3641	if (pszPrefix)
3642	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3643	else
3644	Log(("%s", szOutput));
3645	#endif
3646	rc = VINF_SUCCESS;
3647	}
3648	else
3649	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3650
3651	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3652	if (State.fLocked)
3653	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3654
3655	return rc;
3656	}
3657
3658	#ifdef DEBUG
3659
3660	/**
3661	* Disassemble an instruction and dump it to the log
3662	*
3663	* @returns VBox status code.
3664	* @param pVM VM Handle
3665	* @param pVCpu VMCPU Handle
3666	* @param pCtx CPU context
3667	* @param pc GC instruction pointer
3668	* @param pszPrefix String prefix for logging
3669	*
3670	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3671	*/
3672	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3673	{
3674	DISCPUSTATE Cpu;
3675	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3676	}
3677
3678
3679	/**
3680	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3681	*
3682	* @internal
3683	*/
3684	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3685	{
3686	/** @todo SMP support!! */
3687	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3688	}
3689
3690	#endif /* DEBUG */
3691
3692	/**
3693	* API for controlling a few of the CPU features found in CR4.
3694	*
3695	* Currently only X86_CR4_TSD is accepted as input.
3696	*
3697	* @returns VBox status code.
3698	*
3699	* @param pVM The VM handle.
3700	* @param fOr The CR4 OR mask.
3701	* @param fAnd The CR4 AND mask.
3702	*/
3703	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3704	{
3705	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3706	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3707
3708	pVM->cpum.s.CR4.OrMask &= fAnd;
3709	pVM->cpum.s.CR4.OrMask \|= fOr;
3710
3711	return VINF_SUCCESS;
3712	}
3713
3714
3715	/**
3716	* Gets a pointer to the array of standard CPUID leaves.
3717	*
3718	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3719	*
3720	* @returns Pointer to the standard CPUID leaves (read-only).
3721	* @param pVM The VM handle.
3722	* @remark Intended for PATM.
3723	*/
3724	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3725	{
3726	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3727	}
3728
3729
3730	/**
3731	* Gets a pointer to the array of extended CPUID leaves.
3732	*
3733	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3734	*
3735	* @returns Pointer to the extended CPUID leaves (read-only).
3736	* @param pVM The VM handle.
3737	* @remark Intended for PATM.
3738	*/
3739	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3740	{
3741	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3742	}
3743
3744
3745	/**
3746	* Gets a pointer to the array of centaur CPUID leaves.
3747	*
3748	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3749	*
3750	* @returns Pointer to the centaur CPUID leaves (read-only).
3751	* @param pVM The VM handle.
3752	* @remark Intended for PATM.
3753	*/
3754	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3755	{
3756	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3757	}
3758
3759
3760	/**
3761	* Gets a pointer to the default CPUID leaf.
3762	*
3763	* @returns Pointer to the default CPUID leaf (read-only).
3764	* @param pVM The VM handle.
3765	* @remark Intended for PATM.
3766	*/
3767	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3768	{
3769	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3770	}
3771
3772
3773	/**
3774	* Transforms the guest CPU state to raw-ring mode.
3775	*
3776	* This function will change the any of the cs and ss register with DPL=0 to DPL=1.
3777	*
3778	* @returns VBox status. (recompiler failure)
3779	* @param pVCpu The VMCPU handle.
3780	* @param pCtxCore The context core (for trap usage).
3781	* @see @ref pg_raw
3782	*/
3783	VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
3784	{
3785	PVM pVM = pVCpu->CTX_SUFF(pVM);
3786
3787	Assert(!pVCpu->cpum.s.fRawEntered);
3788	Assert(!pVCpu->cpum.s.fRemEntered);
3789	if (!pCtxCore)
3790	pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
3791
3792	/*
3793	* Are we in Ring-0?
3794	*/
3795	if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
3796	&& !pCtxCore->eflags.Bits.u1VM)
3797	{
3798	/*
3799	* Enter execution mode.
3800	*/
3801	PATMRawEnter(pVM, pCtxCore);
3802
3803	/*
3804	* Set CPL to Ring-1.
3805	*/
3806	pCtxCore->ss \|= 1;
3807	if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
3808	pCtxCore->cs \|= 1;
3809	}
3810	else
3811	{
3812	AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 \|\| pCtxCore->eflags.Bits.u1VM,
3813	("ring-1 code not supported\n"));
3814	/*
3815	* PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
3816	*/
3817	PATMRawEnter(pVM, pCtxCore);
3818	}
3819
3820	/*
3821	* Invalidate the hidden registers.
3822	*/
3823	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3824
3825	/*
3826	* Assert sanity.
3827	*/
3828	AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
3829	AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
3830	\|\| pCtxCore->eflags.Bits.u1VM,
3831	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3832	Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)) == (X86_CR0_PG \| X86_CR0_PE \| X86_CR0_WP));
3833
3834	pCtxCore->eflags.u32 \|= X86_EFL_IF; /* paranoia */
3835
3836	pVCpu->cpum.s.fRawEntered = true;
3837	return VINF_SUCCESS;
3838	}
3839
3840
3841	/**
3842	* Transforms the guest CPU state from raw-ring mode to correct values.
3843	*
3844	* This function will change any selector registers with DPL=1 to DPL=0.
3845	*
3846	* @returns Adjusted rc.
3847	* @param pVCpu The VMCPU handle.
3848	* @param rc Raw mode return code
3849	* @param pCtxCore The context core (for trap usage).
3850	* @see @ref pg_raw
3851	*/
3852	VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
3853	{
3854	PVM pVM = pVCpu->CTX_SUFF(pVM);
3855
3856	/*
3857	* Don't leave if we've already left (in GC).
3858	*/
3859	Assert(pVCpu->cpum.s.fRawEntered);
3860	Assert(!pVCpu->cpum.s.fRemEntered);
3861	if (!pVCpu->cpum.s.fRawEntered)
3862	return rc;
3863	pVCpu->cpum.s.fRawEntered = false;
3864
3865	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3866	if (!pCtxCore)
3867	pCtxCore = CPUMCTX2CORE(pCtx);
3868	Assert(pCtxCore->eflags.Bits.u1VM \|\| (pCtxCore->ss & X86_SEL_RPL));
3869	AssertMsg(pCtxCore->eflags.Bits.u1VM \|\| pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
3870	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3871
3872	/*
3873	* Are we executing in raw ring-1?
3874	*/
3875	if ( (pCtxCore->ss & X86_SEL_RPL) == 1
3876	&& !pCtxCore->eflags.Bits.u1VM)
3877	{
3878	/*
3879	* Leave execution mode.
3880	*/
3881	PATMRawLeave(pVM, pCtxCore, rc);
3882	/* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
3883	/** @todo See what happens if we remove this. */
3884	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3885	pCtxCore->ds &= ~X86_SEL_RPL;
3886	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3887	pCtxCore->es &= ~X86_SEL_RPL;
3888	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3889	pCtxCore->fs &= ~X86_SEL_RPL;
3890	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3891	pCtxCore->gs &= ~X86_SEL_RPL;
3892
3893	/*
3894	* Ring-1 selector => Ring-0.
3895	*/
3896	pCtxCore->ss &= ~X86_SEL_RPL;
3897	if ((pCtxCore->cs & X86_SEL_RPL) == 1)
3898	pCtxCore->cs &= ~X86_SEL_RPL;
3899	}
3900	else
3901	{
3902	/*
3903	* PATM is taking care of the IOPL and IF flags for us.
3904	*/
3905	PATMRawLeave(pVM, pCtxCore, rc);
3906	if (!pCtxCore->eflags.Bits.u1VM)
3907	{
3908	/** @todo See what happens if we remove this. */
3909	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3910	pCtxCore->ds &= ~X86_SEL_RPL;
3911	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3912	pCtxCore->es &= ~X86_SEL_RPL;
3913	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3914	pCtxCore->fs &= ~X86_SEL_RPL;
3915	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3916	pCtxCore->gs &= ~X86_SEL_RPL;
3917	}
3918	}
3919
3920	return rc;
3921	}
3922
3923
3924	/**
3925	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3926	*
3927	* Only REM should ever call this function!
3928	*
3929	* @returns The changed flags.
3930	* @param pVCpu The VMCPU handle.
3931	* @param puCpl Where to return the current privilege level (CPL).
3932	*/
3933	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3934	{
3935	Assert(!pVCpu->cpum.s.fRawEntered);
3936	Assert(!pVCpu->cpum.s.fRemEntered);
3937
3938	/*
3939	* Get the CPL first.
3940	*/
3941	*puCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
3942
3943	/*
3944	* Get and reset the flags, leaving CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID set.
3945	*/
3946	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3947	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; /* leave it set */
3948
3949	/** @todo change the switcher to use the fChanged flags. */
3950	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3951	{
3952	fFlags \|= CPUM_CHANGED_FPU_REM;
3953	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3954	}
3955
3956	pVCpu->cpum.s.fRemEntered = true;
3957	return fFlags;
3958	}
3959
3960
3961	/**
3962	* Leaves REM and works the CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID flag.
3963	*
3964	* @param pVCpu The virtual CPU handle.
3965	* @param fNoOutOfSyncSels This is @c false if there are out of sync
3966	* registers.
3967	*/
3968	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
3969	{
3970	Assert(!pVCpu->cpum.s.fRawEntered);
3971	Assert(pVCpu->cpum.s.fRemEntered);
3972
3973	if (fNoOutOfSyncSels)
3974	pVCpu->cpum.s.fChanged &= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3975	else
3976	pVCpu->cpum.s.fChanged \|= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3977
3978	pVCpu->cpum.s.fRemEntered = false;
3979	}
3980

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source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 34834

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