VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUMInternal.mac@ 7802

Last change on this file since 7802 was 7695, checked in by vboxsync, 17 years ago

Added system MSRs to the CPUMCTX structure.
Sync them in REM as well.

  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 13.3 KB
Line 
1; $Id: CPUMInternal.mac 7695 2008-04-02 12:17:19Z vboxsync $
2;; @file
3; CPUM - Internal header file.
4;
5
6;
7; Copyright (C) 2006-2007 innotek GmbH
8;
9; This file is part of VirtualBox Open Source Edition (OSE), as
10; available from http://www.virtualbox.org. This file is free software;
11; you can redistribute it and/or modify it under the terms of the GNU
12; General Public License (GPL) as published by the Free Software
13; Foundation, in version 2 as it comes in the "COPYING" file of the
14; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16;
17
18%include "VBox/asmdefs.mac"
19
20%define CPUM_USED_FPU RT_BIT(0)
21%define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
22%define CPUM_USE_SYSENTER RT_BIT(2)
23%define CPUM_USE_SYSCALL RT_BIT(3)
24%define CPUM_USE_DEBUG_REGS_HOST RT_BIT(4)
25%define CPUM_USE_DEBUG_REGS RT_BIT(5)
26
27%define CPUM_HANDLER_DS 1
28%define CPUM_HANDLER_ES 2
29%define CPUM_HANDLER_FS 3
30%define CPUM_HANDLER_GS 4
31%define CPUM_HANDLER_IRET 5
32%define CPUM_HANDLER_TYPEMASK 0ffh
33%define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
34
35%define VMMGCRET_USED_FPU 040000000h
36
37%define FPUSTATE_SIZE 512
38
39;; if anyone figures how to do %if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL) in
40; nasm please tell / fix this hack.
41%ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
42 %define fVBOX_WITH_HYBIRD_32BIT_KERNEL 1
43%else
44 %define fVBOX_WITH_HYBIRD_32BIT_KERNEL 0
45%endif
46
47struc CPUM
48 .offVM resd 1
49 .pCPUMGC RTGCPTR_RES 1 ; Guest Context pointer
50 .pCPUMHC RTHCPTR_RES 1 ; Host Context pointer
51
52
53 ;
54 ; Host context state
55 ;
56 alignb 32
57 .Host.fpu resb FPUSTATE_SIZE
58
59%if HC_ARCH_BITS == 64 || fVBOX_WITH_HYBIRD_32BIT_KERNEL
60 ;.Host.rax resq 1 - scratch
61 .Host.rbx resq 1
62 ;.Host.rcx resq 1 - scratch
63 ;.Host.rdx resq 1 - scratch
64 .Host.rdi resq 1
65 .Host.rsi resq 1
66 .Host.rbp resq 1
67 .Host.rsp resq 1
68 ;.Host.r8 resq 1 - scratch
69 ;.Host.r9 resq 1 - scratch
70 .Host.r10 resq 1
71 .Host.r11 resq 1
72 .Host.r12 resq 1
73 .Host.r13 resq 1
74 .Host.r14 resq 1
75 .Host.r15 resq 1
76 ;.Host.rip resd 1 - scratch
77 .Host.rflags resq 1
78%endif
79%if HC_ARCH_BITS == 32
80 ;.Host.eax resd 1 - scratch
81 .Host.ebx resd 1
82 ;.Host.edx resd 1 - scratch
83 ;.Host.ecx resd 1 - scratch
84 .Host.edi resd 1
85 .Host.esi resd 1
86 .Host.ebp resd 1
87 .Host.eflags resd 1
88 ;.Host.eip resd 1 - scratch
89 ; lss pair!
90 .Host.esp resd 1
91%endif
92 .Host.ss resw 1
93 .Host.ssPadding resw 1
94 .Host.gs resw 1
95 .Host.gsPadding resw 1
96 .Host.fs resw 1
97 .Host.fsPadding resw 1
98 .Host.es resw 1
99 .Host.esPadding resw 1
100 .Host.ds resw 1
101 .Host.dsPadding resw 1
102 .Host.cs resw 1
103 .Host.csPadding resw 1
104
105%if HC_ARCH_BITS == 32 && fVBOX_WITH_HYBIRD_32BIT_KERNEL == 0
106 .Host.cr0 resd 1
107 ;.Host.cr2 resd 1 - scratch
108 .Host.cr3 resd 1
109 .Host.cr4 resd 1
110
111 .Host.dr0 resd 1
112 .Host.dr1 resd 1
113 .Host.dr2 resd 1
114 .Host.dr3 resd 1
115 .Host.dr6 resd 1
116 .Host.dr7 resd 1
117
118 .Host.gdtr resb 6 ; GDT limit + linear address
119 .Host.gdtrPadding resw 1
120 .Host.idtr resb 6 ; IDT limit + linear address
121 .Host.idtrPadding resw 1
122 .Host.ldtr resw 1
123 .Host.ldtrPadding resw 1
124 .Host.tr resw 1
125 .Host.trPadding resw 1
126
127 .Host.SysEnterPadding resd 1
128 .Host.SysEnter.cs resq 1
129 .Host.SysEnter.eip resq 1
130 .Host.SysEnter.esp resq 1
131
132%else ; 64-bit
133
134 .Host.cr0 resq 1
135 ;.Host.cr2 resq 1 - scratch
136 .Host.cr3 resq 1
137 .Host.cr4 resq 1
138 .Host.cr8 resq 1
139
140 .Host.dr0 resq 1
141 .Host.dr1 resq 1
142 .Host.dr2 resq 1
143 .Host.dr3 resq 1
144 .Host.dr6 resq 1
145 .Host.dr7 resq 1
146
147 .Host.gdtr resb 10 ; GDT limit + linear address
148 .Host.gdtrPadding resw 1
149 .Host.idtr resb 10 ; IDT limit + linear address
150 .Host.idtrPadding resw 1
151 .Host.ldtr resw 1
152 .Host.ldtrPadding resw 1
153 .Host.tr resw 1
154 .Host.trPadding resw 1
155
156 .Host.SysEnter.cs resq 1
157 .Host.SysEnter.eip resq 1
158 .Host.SysEnter.esp resq 1
159 .Host.FSbase resq 1
160 .Host.GSbase resq 1
161 .Host.efer resq 1
162%endif ; 64-bit
163
164
165 ;
166 ; Hypervisor Context.
167 ; (Identical to .Host.*)
168 ;
169 alignb 32 ; the padding
170 .Hyper.fpu resb FPUSTATE_SIZE
171
172 .Hyper.edi resq 1
173 .Hyper.esi resq 1
174 .Hyper.ebp resq 1
175 .Hyper.eax resq 1
176 .Hyper.ebx resq 1
177 .Hyper.edx resq 1
178 .Hyper.ecx resq 1
179 .Hyper.esp resd 1
180 .Hyper.ss resw 1
181 .Hyper.ssPadding resw 1
182 .Hyper.rsp resq 1
183 .Hyper.gs resw 1
184 .Hyper.gsPadding resw 1
185 .Hyper.fs resw 1
186 .Hyper.fsPadding resw 1
187 .Hyper.es resw 1
188 .Hyper.esPadding resw 1
189 .Hyper.ds resw 1
190 .Hyper.dsPadding resw 1
191 .Hyper.cs resw 1
192 .Hyper.csPadding resw 3
193 .Hyper.eflags resq 1
194 .Hyper.eip resq 1
195 .Hyper.r8 resq 1
196 .Hyper.r9 resq 1
197 .Hyper.r10 resq 1
198 .Hyper.r11 resq 1
199 .Hyper.r12 resq 1
200 .Hyper.r13 resq 1
201 .Hyper.r14 resq 1
202 .Hyper.r15 resq 1
203
204 .Hyper.esHid.u32Base resd 1
205 .Hyper.esHid.u32Limit resd 1
206 .Hyper.esHid.Attr resd 1
207
208 .Hyper.csHid.u32Base resd 1
209 .Hyper.csHid.u32Limit resd 1
210 .Hyper.csHid.Attr resd 1
211
212 .Hyper.ssHid.u32Base resd 1
213 .Hyper.ssHid.u32Limit resd 1
214 .Hyper.ssHid.Attr resd 1
215
216 .Hyper.dsHid.u32Base resd 1
217 .Hyper.dsHid.u32Limit resd 1
218 .Hyper.dsHid.Attr resd 1
219
220 .Hyper.fsHid.u32Base resd 1
221 .Hyper.fsHid.u32Limit resd 1
222 .Hyper.fsHid.Attr resd 1
223
224 .Hyper.gsHid.u32Base resd 1
225 .Hyper.gsHid.u32Limit resd 1
226 .Hyper.gsHid.Attr resd 1
227
228 .Hyper.cr0 resq 1
229 .Hyper.cr2 resq 1
230 .Hyper.cr3 resq 1
231 .Hyper.cr4 resq 1
232 .Hyper.cr8 resq 1
233
234 .Hyper.dr0 resq 1
235 .Hyper.dr1 resq 1
236 .Hyper.dr2 resq 1
237 .Hyper.dr3 resq 1
238 .Hyper.dr4 resq 1
239 .Hyper.dr5 resq 1
240 .Hyper.dr6 resq 1
241 .Hyper.dr7 resq 1
242
243 .Hyper.gdtr resb 6 ; GDT limit + linear address
244 .Hyper.gdtrPadding resw 1
245 .Hyper.gdtrPadding64 resd 1
246 .Hyper.idtr resb 6 ; IDT limit + linear address
247 .Hyper.idtrPadding resw 1
248 .Hyper.idtrPadding64 resd 1
249 .Hyper.ldtr resw 1
250 .Hyper.ldtrPadding resw 1
251 .Hyper.tr resw 1
252 .Hyper.trPadding resw 1
253
254 .Hyper.SysEnter.cs resb 8
255 .Hyper.SysEnter.eip resb 8
256 .Hyper.SysEnter.esp resb 8
257
258 .Hyper.msrEFER resb 8
259 .Hyper.msrSTAR resb 8
260 .Hyper.msrPAT resb 8
261 .Hyper.msrLSTAR resb 8
262 .Hyper.msrCSTAR resb 8
263 .Hyper.msrSFMASK resb 8
264 .Hyper.msrFSBASE resb 8
265 .Hyper.msrGSBASE resb 8
266 .Hyper.msrKERNELGSBASE resb 8
267
268 .Hyper.ldtrHid.u32Base resd 1
269 .Hyper.ldtrHid.u32Limit resd 1
270 .Hyper.ldtrHid.Attr resd 1
271
272 .Hyper.trHid.u32Base resd 1
273 .Hyper.trHid.u32Limit resd 1
274 .Hyper.trHid.Attr resd 1
275
276 ; padding
277 .Hyper.padding resd 2
278
279
280
281 ;
282 ; Guest context state
283 ; (Identical to the two above chunks)
284 ;
285 alignb 32
286 .Guest.fpu resb FPUSTATE_SIZE
287
288 .Guest.edi resq 1
289 .Guest.esi resq 1
290 .Guest.ebp resq 1
291 .Guest.eax resq 1
292 .Guest.ebx resq 1
293 .Guest.edx resq 1
294 .Guest.ecx resq 1
295 .Guest.esp resd 1
296 .Guest.ss resw 1
297 .Guest.ssPadding resw 1
298 .Guest.rsp resq 1
299 .Guest.gs resw 1
300 .Guest.gsPadding resw 1
301 .Guest.fs resw 1
302 .Guest.fsPadding resw 1
303 .Guest.es resw 1
304 .Guest.esPadding resw 1
305 .Guest.ds resw 1
306 .Guest.dsPadding resw 1
307 .Guest.cs resw 1
308 .Guest.csPadding resw 3
309 .Guest.eflags resq 1
310 .Guest.eip resq 1
311 .Guest.r8 resq 1
312 .Guest.r9 resq 1
313 .Guest.r10 resq 1
314 .Guest.r11 resq 1
315 .Guest.r12 resq 1
316 .Guest.r13 resq 1
317 .Guest.r14 resq 1
318 .Guest.r15 resq 1
319
320 .Guest.esHid.u32Base resd 1
321 .Guest.esHid.u32Limit resd 1
322 .Guest.esHid.Attr resd 1
323
324 .Guest.csHid.u32Base resd 1
325 .Guest.csHid.u32Limit resd 1
326 .Guest.csHid.Attr resd 1
327
328 .Guest.ssHid.u32Base resd 1
329 .Guest.ssHid.u32Limit resd 1
330 .Guest.ssHid.Attr resd 1
331
332 .Guest.dsHid.u32Base resd 1
333 .Guest.dsHid.u32Limit resd 1
334 .Guest.dsHid.Attr resd 1
335
336 .Guest.fsHid.u32Base resd 1
337 .Guest.fsHid.u32Limit resd 1
338 .Guest.fsHid.Attr resd 1
339
340 .Guest.gsHid.u32Base resd 1
341 .Guest.gsHid.u32Limit resd 1
342 .Guest.gsHid.Attr resd 1
343
344 .Guest.cr0 resq 1
345 .Guest.cr2 resq 1
346 .Guest.cr3 resq 1
347 .Guest.cr4 resq 1
348 .Guest.cr8 resq 1
349
350 .Guest.dr0 resq 1
351 .Guest.dr1 resq 1
352 .Guest.dr2 resq 1
353 .Guest.dr3 resq 1
354 .Guest.dr4 resq 1
355 .Guest.dr5 resq 1
356 .Guest.dr6 resq 1
357 .Guest.dr7 resq 1
358
359 .Guest.gdtr resb 6 ; GDT limit + linear address
360 .Guest.gdtrPadding resw 1
361 .Guest.gdtrPadding64 resd 1
362 .Guest.idtr resb 6 ; IDT limit + linear address
363 .Guest.idtrPadding resw 1
364 .Guest.idtrPadding64 resd 1
365 .Guest.ldtr resw 1
366 .Guest.ldtrPadding resw 1
367 .Guest.tr resw 1
368 .Guest.trPadding resw 1
369
370 .Guest.SysEnter.cs resb 8
371 .Guest.SysEnter.eip resb 8
372 .Guest.SysEnter.esp resb 8
373
374 .Guest.msrEFER resb 8
375 .Guest.msrSTAR resb 8
376 .Guest.msrPAT resb 8
377 .Guest.msrLSTAR resb 8
378 .Guest.msrCSTAR resb 8
379 .Guest.msrSFMASK resb 8
380 .Guest.msrFSBASE resb 8
381 .Guest.msrGSBASE resb 8
382 .Guest.msrKERNELGSBASE resb 8
383
384 .Guest.ldtrHid.u32Base resd 1
385 .Guest.ldtrHid.u32Limit resd 1
386 .Guest.ldtrHid.Attr resd 1
387
388 .Guest.trHid.u32Base resd 1
389 .Guest.trHid.u32Limit resd 1
390 .Guest.trHid.Attr resd 1
391
392 ; padding
393 .Guest.padding resd 2
394
395
396
397 ;
398 ; Other stuff.
399 ;
400 alignb 32
401 ; hypervisor core context.
402 .pHyperCoreR3 RTR3PTR_RES 1
403 .pHyperCoreR0 RTR0PTR_RES 1
404 .pHyperCoreGC RTGCPTR_RES 1
405 ;...
406 .fUseFlags resd 1
407 .fChanged resd 1
408 .fValidHiddenSelRegs resd 1
409
410 ; CPUID eax=1
411 .CPUFeatures.edx resd 1
412 .CPUFeatures.ecx resd 1
413 ; CR4 masks
414 .CR4.AndMask resd 1
415 .CR4.OrMask resd 1
416 ; entered rawmode?
417 .fRawEntered resb 1
418%if RTHCPTR_CB == 8
419 .abPadding resb 7
420%else
421 .abPadding resb 3
422%endif
423
424 ; CPUID leafs
425 .aGuestCpuIdStd resb 16*5
426 .aGuestCpuIdExt resb 16*10
427 .aGuestCpuIdCentaur resb 16*4
428 .GuestCpuIdDef resb 16
429
430 ; CPUMCTX debug stuff...
431 .GuestEntry resb 1024
432
433endstruc
434
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