EM.cpp@ 13232

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1	/* $Id: EM.cpp 13160 2008-10-10 11:00:58Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_em EM - The Execution Monitor / Manager
23	*
24	* The Execution Monitor/Manager is responsible for running the VM, scheduling
25	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26	* Interpreted), and keeping the CPU states in sync. The function
27	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29	* emR3RemExecute).
30	*
31	* The interpreted execution is only used to avoid switching between
32	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33	* The interpretation is thus implemented as part of EM.
34	*
35	* @see grp_em
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_EM
42	#include <VBox/em.h>
43	#include <VBox/vmm.h>
44	#include <VBox/patm.h>
45	#include <VBox/csam.h>
46	#include <VBox/selm.h>
47	#include <VBox/trpm.h>
48	#include <VBox/iom.h>
49	#include <VBox/dbgf.h>
50	#include <VBox/pgm.h>
51	#include <VBox/rem.h>
52	#include <VBox/tm.h>
53	#include <VBox/mm.h>
54	#include <VBox/ssm.h>
55	#include <VBox/pdmapi.h>
56	#include <VBox/pdmcritsect.h>
57	#include <VBox/pdmqueue.h>
58	#include <VBox/hwaccm.h>
59	#include <VBox/patm.h>
60	#include "EMInternal.h"
61	#include <VBox/vm.h>
62	#include <VBox/cpumdis.h>
63	#include <VBox/dis.h>
64	#include <VBox/disopcode.h>
65	#include <VBox/dbgf.h>
66
67	#include <VBox/log.h>
68	#include <iprt/thread.h>
69	#include <iprt/assert.h>
70	#include <iprt/asm.h>
71	#include <iprt/semaphore.h>
72	#include <iprt/string.h>
73	#include <iprt/avl.h>
74	#include <iprt/stream.h>
75	#include <VBox/param.h>
76	#include <VBox/err.h>
77
78
79	/*******************************************************************************
80	* Internal Functions *
81	*******************************************************************************/
82	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
83	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
84	static int emR3Debug(PVM pVM, int rc);
85	static int emR3RemStep(PVM pVM);
86	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
87	static int emR3RawResumeHyper(PVM pVM);
88	static int emR3RawStep(PVM pVM);
89	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
90	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
91	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
92	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
93	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
94	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
95	static int emR3ForcedActions(PVM pVM, int rc);
96	static int emR3RawGuestTrap(PVM pVM);
97
98
99	/**
100	* Initializes the EM.
101	*
102	* @returns VBox status code.
103	* @param pVM The VM to operate on.
104	*/
105	VMMR3DECL(int) EMR3Init(PVM pVM)
106	{
107	LogFlow(("EMR3Init\n"));
108	/*
109	* Assert alignment and sizes.
110	*/
111	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
112	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
113	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
114	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
115
116	/*
117	* Init the structure.
118	*/
119	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
120	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
121	if (VBOX_FAILURE(rc))
122	pVM->fRawR3Enabled = true;
123	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
124	if (VBOX_FAILURE(rc))
125	pVM->fRawR0Enabled = true;
126	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
127	pVM->em.s.enmState = EMSTATE_NONE;
128	pVM->em.s.fForceRAW = false;
129
130	rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
131	AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
132	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
133	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
134
135	/*
136	* Saved state.
137	*/
138	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
139	NULL, emR3Save, NULL,
140	NULL, emR3Load, NULL);
141	if (VBOX_FAILURE(rc))
142	return rc;
143
144	/*
145	* Statistics.
146	*/
147	#ifdef VBOX_WITH_STATISTICS
148	PEMSTATS pStats;
149	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
150	if (VBOX_FAILURE(rc))
151	return rc;
152	pVM->em.s.pStatsR3 = pStats;
153	pVM->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
154	pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
155
156	STAM_REG(pVM, &pStats->StatRZEmulate, STAMTYPE_PROFILE, "/EM/RZ/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
157	STAM_REG(pVM, &pStats->StatR3Emulate, STAMTYPE_PROFILE, "/EM/R3/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
158
159	STAM_REG(pVM, &pStats->StatRZInterpretSucceeded, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
160	STAM_REG(pVM, &pStats->StatR3InterpretSucceeded, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
161
162	STAM_REG_USED(pVM, &pStats->StatRZAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
163	STAM_REG_USED(pVM, &pStats->StatR3And, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
164	STAM_REG_USED(pVM, &pStats->StatRZAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
165	STAM_REG_USED(pVM, &pStats->StatR3Add, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
166	STAM_REG_USED(pVM, &pStats->StatRZAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
167	STAM_REG_USED(pVM, &pStats->StatR3Adc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
168	STAM_REG_USED(pVM, &pStats->StatRZSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
169	STAM_REG_USED(pVM, &pStats->StatR3Sub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
170	STAM_REG_USED(pVM, &pStats->StatRZCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
171	STAM_REG_USED(pVM, &pStats->StatR3CpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
172	STAM_REG_USED(pVM, &pStats->StatRZDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
173	STAM_REG_USED(pVM, &pStats->StatR3Dec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
174	STAM_REG_USED(pVM, &pStats->StatRZHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatR3Hlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatRZInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatR3Inc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatRZInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatR3InvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatRZIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatR3Iret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatRZLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatR3LLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatRZLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
185	STAM_REG_USED(pVM, &pStats->StatR3LIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatRZLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatR3LGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatRZMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatR3Mov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatRZMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatR3MovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatRZMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatR3MovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatRZOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatR3Or, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
196	STAM_REG_USED(pVM, &pStats->StatRZPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
197	STAM_REG_USED(pVM, &pStats->StatR3Pop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
198	STAM_REG_USED(pVM, &pStats->StatRZRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
199	STAM_REG_USED(pVM, &pStats->StatR3Rdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
200	STAM_REG_USED(pVM, &pStats->StatRZSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatR3Sti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatRZXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatR3Xchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
204	STAM_REG_USED(pVM, &pStats->StatRZXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
205	STAM_REG_USED(pVM, &pStats->StatR3Xor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
206	STAM_REG_USED(pVM, &pStats->StatRZMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
207	STAM_REG_USED(pVM, &pStats->StatR3Monitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
208	STAM_REG_USED(pVM, &pStats->StatRZMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatR3MWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatRZBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatR3Btr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatRZBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatR3Bts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatRZBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatR3Btc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatRZCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatR3CmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatRZCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatR3CmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatRZXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatR3XAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatR3Rdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatRZRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatR3Wrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatRZWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatR3StosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatRZStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatRZWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatR3WbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
230
231	STAM_REG(pVM, &pStats->StatRZInterpretFailed, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
232	STAM_REG(pVM, &pStats->StatR3InterpretFailed, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
233
234	STAM_REG_USED(pVM, &pStats->StatRZFailedAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatR3FailedAnd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatRZFailedCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
237	STAM_REG_USED(pVM, &pStats->StatR3FailedCpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
238	STAM_REG_USED(pVM, &pStats->StatRZFailedDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
239	STAM_REG_USED(pVM, &pStats->StatR3FailedDec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
240	STAM_REG_USED(pVM, &pStats->StatRZFailedHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
241	STAM_REG_USED(pVM, &pStats->StatR3FailedHlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatRZFailedInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatR3FailedInc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatRZFailedInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatR3FailedInvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
246	STAM_REG_USED(pVM, &pStats->StatRZFailedIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
247	STAM_REG_USED(pVM, &pStats->StatR3FailedIret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
248	STAM_REG_USED(pVM, &pStats->StatRZFailedLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
249	STAM_REG_USED(pVM, &pStats->StatR3FailedLLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatRZFailedLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatR3FailedLIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatRZFailedLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatR3FailedLGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatRZFailedMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatR3FailedMov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatRZFailedMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatR3FailedMovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatRZFailedMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatR3FailedMovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatRZFailedOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
261	STAM_REG_USED(pVM, &pStats->StatR3FailedOr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
262	STAM_REG_USED(pVM, &pStats->StatRZFailedPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
263	STAM_REG_USED(pVM, &pStats->StatR3FailedPop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
264	STAM_REG_USED(pVM, &pStats->StatRZFailedSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
265	STAM_REG_USED(pVM, &pStats->StatR3FailedSti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
266	STAM_REG_USED(pVM, &pStats->StatRZFailedXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
267	STAM_REG_USED(pVM, &pStats->StatR3FailedXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
268	STAM_REG_USED(pVM, &pStats->StatRZFailedXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
269	STAM_REG_USED(pVM, &pStats->StatR3FailedXor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
270	STAM_REG_USED(pVM, &pStats->StatRZFailedMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
271	STAM_REG_USED(pVM, &pStats->StatR3FailedMonitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
272	STAM_REG_USED(pVM, &pStats->StatRZFailedMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
273	STAM_REG_USED(pVM, &pStats->StatR3FailedMWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
274	STAM_REG_USED(pVM, &pStats->StatRZFailedRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
275	STAM_REG_USED(pVM, &pStats->StatR3FailedRdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
276	STAM_REG_USED(pVM, &pStats->StatRZFailedRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
277	STAM_REG_USED(pVM, &pStats->StatR3FailedRdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
278	STAM_REG_USED(pVM, &pStats->StatRZFailedWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
279	STAM_REG_USED(pVM, &pStats->StatR3FailedWrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
280
281	STAM_REG_USED(pVM, &pStats->StatRZFailedMisc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
282	STAM_REG_USED(pVM, &pStats->StatR3FailedMisc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
283	STAM_REG_USED(pVM, &pStats->StatRZFailedAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
284	STAM_REG_USED(pVM, &pStats->StatR3FailedAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
285	STAM_REG_USED(pVM, &pStats->StatRZFailedAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
286	STAM_REG_USED(pVM, &pStats->StatR3FailedAdc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
287	STAM_REG_USED(pVM, &pStats->StatRZFailedBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
288	STAM_REG_USED(pVM, &pStats->StatR3FailedBtr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
289	STAM_REG_USED(pVM, &pStats->StatRZFailedBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
290	STAM_REG_USED(pVM, &pStats->StatR3FailedBts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
291	STAM_REG_USED(pVM, &pStats->StatRZFailedBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
292	STAM_REG_USED(pVM, &pStats->StatR3FailedBtc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
293	STAM_REG_USED(pVM, &pStats->StatRZFailedCli, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
294	STAM_REG_USED(pVM, &pStats->StatR3FailedCli, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
295	STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
296	STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
297	STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
298	STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
299	STAM_REG_USED(pVM, &pStats->StatRZFailedXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
300	STAM_REG_USED(pVM, &pStats->StatR3FailedXAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
301	STAM_REG_USED(pVM, &pStats->StatRZFailedMovNTPS, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
302	STAM_REG_USED(pVM, &pStats->StatR3FailedMovNTPS, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
303	STAM_REG_USED(pVM, &pStats->StatRZFailedStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
304	STAM_REG_USED(pVM, &pStats->StatR3FailedStosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
305	STAM_REG_USED(pVM, &pStats->StatRZFailedSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
306	STAM_REG_USED(pVM, &pStats->StatR3FailedSub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
307	STAM_REG_USED(pVM, &pStats->StatRZFailedWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
308	STAM_REG_USED(pVM, &pStats->StatR3FailedWbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
309
310	STAM_REG_USED(pVM, &pStats->StatRZFailedUserMode, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
311	STAM_REG_USED(pVM, &pStats->StatR3FailedUserMode, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
312	STAM_REG_USED(pVM, &pStats->StatRZFailedPrefix, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
313	STAM_REG_USED(pVM, &pStats->StatR3FailedPrefix, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
314
315	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
316	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
317	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/R3/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
318	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
319	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
320	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
321	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
322	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
323	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
324	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
325	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
326	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
327	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
328	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
329	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
330	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
331	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
332	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/R3/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
333	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
334	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
335	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
336	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
337	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
338	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
339	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
340	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
341
342	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
343	pVM->em.s.pCliStatTree = 0;
344	#endif /* VBOX_WITH_STATISTICS */
345
346	/* these should be considered for release statistics. */
347	STAM_REL_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
348	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
349	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
350	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
351
352	STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
353	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
354	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
355	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
356	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
357	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
358	STAM_REL_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
359	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
360	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
361	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
362	STAM_REL_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
363	STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
364
365
366	return VINF_SUCCESS;
367	}
368
369
370	/**
371	* Applies relocations to data and code managed by this
372	* component. This function will be called at init and
373	* whenever the VMM need to relocate it self inside the GC.
374	*
375	* @param pVM The VM.
376	*/
377	VMMR3DECL(void) EMR3Relocate(PVM pVM)
378	{
379	LogFlow(("EMR3Relocate\n"));
380	if (pVM->em.s.pStatsR3)
381	pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVM->em.s.pStatsR3);
382	}
383
384
385	/**
386	* Reset notification.
387	*
388	* @param pVM
389	*/
390	VMMR3DECL(void) EMR3Reset(PVM pVM)
391	{
392	LogFlow(("EMR3Reset: \n"));
393	pVM->em.s.fForceRAW = false;
394	}
395
396
397	/**
398	* Terminates the EM.
399	*
400	* Termination means cleaning up and freeing all resources,
401	* the VM it self is at this point powered off or suspended.
402	*
403	* @returns VBox status code.
404	* @param pVM The VM to operate on.
405	*/
406	VMMR3DECL(int) EMR3Term(PVM pVM)
407	{
408	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
409
410	return VINF_SUCCESS;
411	}
412
413
414	/**
415	* Execute state save operation.
416	*
417	* @returns VBox status code.
418	* @param pVM VM Handle.
419	* @param pSSM SSM operation handle.
420	*/
421	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
422	{
423	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
424	}
425
426
427	/**
428	* Execute state load operation.
429	*
430	* @returns VBox status code.
431	* @param pVM VM Handle.
432	* @param pSSM SSM operation handle.
433	* @param u32Version Data layout version.
434	*/
435	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
436	{
437	/*
438	* Validate version.
439	*/
440	if (u32Version != EM_SAVED_STATE_VERSION)
441	{
442	AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
443	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
444	}
445
446	/*
447	* Load the saved state.
448	*/
449	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
450	if (VBOX_FAILURE(rc))
451	pVM->em.s.fForceRAW = false;
452
453	Assert(!pVM->em.s.pCliStatTree);
454	return rc;
455	}
456
457
458	/**
459	* Enables or disables a set of raw-mode execution modes.
460	*
461	* @returns VINF_SUCCESS on success.
462	* @returns VINF_RESCHEDULE if a rescheduling might be required.
463	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
464	*
465	* @param pVM The VM to operate on.
466	* @param enmMode The execution mode change.
467	* @thread The emulation thread.
468	*/
469	VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
470	{
471	switch (enmMode)
472	{
473	case EMRAW_NONE:
474	pVM->fRawR3Enabled = false;
475	pVM->fRawR0Enabled = false;
476	break;
477	case EMRAW_RING3_ENABLE:
478	pVM->fRawR3Enabled = true;
479	break;
480	case EMRAW_RING3_DISABLE:
481	pVM->fRawR3Enabled = false;
482	break;
483	case EMRAW_RING0_ENABLE:
484	pVM->fRawR0Enabled = true;
485	break;
486	case EMRAW_RING0_DISABLE:
487	pVM->fRawR0Enabled = false;
488	break;
489	default:
490	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
491	return VERR_INVALID_PARAMETER;
492	}
493	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
494	pVM->fRawR3Enabled, pVM->fRawR0Enabled));
495	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
496	}
497
498
499	/**
500	* Raise a fatal error.
501	*
502	* Safely terminate the VM with full state report and stuff. This function
503	* will naturally never return.
504	*
505	* @param pVM VM handle.
506	* @param rc VBox status code.
507	*/
508	VMMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
509	{
510	longjmp(pVM->em.s.u.FatalLongJump, rc);
511	AssertReleaseMsgFailed(("longjmp returned!\n"));
512	}
513
514
515	/**
516	* Gets the EM state name.
517	*
518	* @returns pointer to read only state name,
519	* @param enmState The state.
520	*/
521	VMMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
522	{
523	switch (enmState)
524	{
525	case EMSTATE_NONE: return "EMSTATE_NONE";
526	case EMSTATE_RAW: return "EMSTATE_RAW";
527	case EMSTATE_HWACC: return "EMSTATE_HWACC";
528	case EMSTATE_REM: return "EMSTATE_REM";
529	case EMSTATE_HALTED: return "EMSTATE_HALTED";
530	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
531	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
532	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
533	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
534	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
535	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
536	default: return "Unknown!";
537	}
538	}
539
540
541	#ifdef VBOX_WITH_STATISTICS
542	/**
543	* Just a braindead function to keep track of cli addresses.
544	* @param pVM VM handle.
545	* @param pInstrGC The EIP of the cli instruction.
546	*/
547	static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
548	{
549	PCLISTAT pRec;
550
551	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
552	if (!pRec)
553	{
554	/* New cli instruction; insert into the tree. */
555	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
556	Assert(pRec);
557	if (!pRec)
558	return;
559	pRec->Core.Key = (AVLPVKEY)pInstrGC;
560
561	char szCliStatName[32];
562	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
563	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
564
565	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
566	Assert(fRc); NOREF(fRc);
567	}
568	STAM_COUNTER_INC(&pRec->Counter);
569	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
570	}
571	#endif /* VBOX_WITH_STATISTICS */
572
573
574	/**
575	* Debug loop.
576	*
577	* @returns VBox status code for EM.
578	* @param pVM VM handle.
579	* @param rc Current EM VBox status code..
580	*/
581	static int emR3Debug(PVM pVM, int rc)
582	{
583	for (;;)
584	{
585	Log(("emR3Debug: rc=%Vrc\n", rc));
586	const int rcLast = rc;
587
588	/*
589	* Debug related RC.
590	*/
591	switch (rc)
592	{
593	/*
594	* Single step an instruction.
595	*/
596	case VINF_EM_DBG_STEP:
597	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
598	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
599	\|\| pVM->em.s.fForceRAW /* paranoia */)
600	rc = emR3RawStep(pVM);
601	else
602	{
603	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
604	rc = emR3RemStep(pVM);
605	}
606	break;
607
608	/*
609	* Simple events: stepped, breakpoint, stop/assertion.
610	*/
611	case VINF_EM_DBG_STEPPED:
612	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
613	break;
614
615	case VINF_EM_DBG_BREAKPOINT:
616	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
617	break;
618
619	case VINF_EM_DBG_STOP:
620	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
621	break;
622
623	case VINF_EM_DBG_HYPER_STEPPED:
624	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
625	break;
626
627	case VINF_EM_DBG_HYPER_BREAKPOINT:
628	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
629	break;
630
631	case VINF_EM_DBG_HYPER_ASSERTION:
632	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
633	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
634	break;
635
636	/*
637	* Guru meditation.
638	*/
639	case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
640	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
641	break;
642
643	default: /** @todo don't use default for guru, but make special errors code! */
644	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
645	break;
646	}
647
648	/*
649	* Process the result.
650	*/
651	do
652	{
653	switch (rc)
654	{
655	/*
656	* Continue the debugging loop.
657	*/
658	case VINF_EM_DBG_STEP:
659	case VINF_EM_DBG_STOP:
660	case VINF_EM_DBG_STEPPED:
661	case VINF_EM_DBG_BREAKPOINT:
662	case VINF_EM_DBG_HYPER_STEPPED:
663	case VINF_EM_DBG_HYPER_BREAKPOINT:
664	case VINF_EM_DBG_HYPER_ASSERTION:
665	break;
666
667	/*
668	* Resuming execution (in some form) has to be done here if we got
669	* a hypervisor debug event.
670	*/
671	case VINF_SUCCESS:
672	case VINF_EM_RESUME:
673	case VINF_EM_SUSPEND:
674	case VINF_EM_RESCHEDULE:
675	case VINF_EM_RESCHEDULE_RAW:
676	case VINF_EM_RESCHEDULE_REM:
677	case VINF_EM_HALT:
678	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
679	{
680	rc = emR3RawResumeHyper(pVM);
681	if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
682	continue;
683	}
684	if (rc == VINF_SUCCESS)
685	rc = VINF_EM_RESCHEDULE;
686	return rc;
687
688	/*
689	* The debugger isn't attached.
690	* We'll simply turn the thing off since that's the easiest thing to do.
691	*/
692	case VERR_DBGF_NOT_ATTACHED:
693	switch (rcLast)
694	{
695	case VINF_EM_DBG_HYPER_ASSERTION:
696	case VINF_EM_DBG_HYPER_STEPPED:
697	case VINF_EM_DBG_HYPER_BREAKPOINT:
698	return rcLast;
699	}
700	return VINF_EM_OFF;
701
702	/*
703	* Status codes terminating the VM in one or another sense.
704	*/
705	case VINF_EM_TERMINATE:
706	case VINF_EM_OFF:
707	case VINF_EM_RESET:
708	case VINF_EM_RAW_STALE_SELECTOR:
709	case VINF_EM_RAW_IRET_TRAP:
710	case VERR_TRPM_PANIC:
711	case VERR_TRPM_DONT_PANIC:
712	case VERR_INTERNAL_ERROR:
713	return rc;
714
715	/*
716	* The rest is unexpected, and will keep us here.
717	*/
718	default:
719	AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
720	break;
721	}
722	} while (false);
723	} /* debug for ever */
724	}
725
726
727	/**
728	* Steps recompiled code.
729	*
730	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
731	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
732	*
733	* @param pVM VM handle.
734	*/
735	static int emR3RemStep(PVM pVM)
736	{
737	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
738
739	/*
740	* Switch to REM, step instruction, switch back.
741	*/
742	int rc = REMR3State(pVM, pVM->em.s.fREMFlushTBs);
743	if (VBOX_SUCCESS(rc))
744	{
745	rc = REMR3Step(pVM);
746	REMR3StateBack(pVM);
747	pVM->em.s.fREMFlushTBs = false;
748	}
749	LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
750	return rc;
751	}
752
753
754	/**
755	* Executes recompiled code.
756	*
757	* This function contains the recompiler version of the inner
758	* execution loop (the outer loop being in EMR3ExecuteVM()).
759	*
760	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
761	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
762	*
763	* @param pVM VM handle.
764	* @param pfFFDone Where to store an indicator telling wheter or not
765	* FFs were done before returning.
766	*
767	*/
768	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
769	{
770	#ifdef LOG_ENABLED
771	PCPUMCTX pCtx = pVM->em.s.pCtx;
772	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
773
774	if (pCtx->eflags.Bits.u1VM)
775	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
776	else
777	Log(("EMR%d: %08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
778	#endif
779	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
780
781	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
782	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
783	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
784	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
785	#endif
786
787	/*
788	* Spin till we get a forced action which returns anything but VINF_SUCCESS
789	* or the REM suggests raw-mode execution.
790	*/
791	*pfFFDone = false;
792	bool fInREMState = false;
793	int rc = VINF_SUCCESS;
794	for (;;)
795	{
796	/*
797	* Update REM state if not already in sync.
798	*/
799	if (!fInREMState)
800	{
801	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
802	rc = REMR3State(pVM, pVM->em.s.fREMFlushTBs);
803	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
804	if (VBOX_FAILURE(rc))
805	break;
806	fInREMState = true;
807	pVM->em.s.fREMFlushTBs = false;
808
809	/*
810	* We might have missed the raising of VMREQ, TIMER and some other
811	* imporant FFs while we were busy switching the state. So, check again.
812	*/
813	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
814	{
815	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
816	goto l_REMDoForcedActions;
817	}
818	}
819
820
821	/*
822	* Execute REM.
823	*/
824	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
825	rc = REMR3Run(pVM);
826	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
827
828
829	/*
830	* Deal with high priority post execution FFs before doing anything else.
831	*/
832	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
833	rc = emR3HighPriorityPostForcedActions(pVM, rc);
834
835	/*
836	* Process the returned status code.
837	* (Try keep this short! Call functions!)
838	*/
839	if (rc != VINF_SUCCESS)
840	{
841	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
842	break;
843	if (rc != VINF_REM_INTERRUPED_FF)
844	{
845	/*
846	* Anything which is not known to us means an internal error
847	* and the termination of the VM!
848	*/
849	AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Vra\n", rc));
850	break;
851	}
852	}
853
854
855	/*
856	* Check and execute forced actions.
857	* Sync back the VM state before calling any of these.
858	*/
859	#ifdef VBOX_HIGH_RES_TIMERS_HACK
860	TMTimerPoll(pVM);
861	#endif
862	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION \| VM_FF_CSAM_SCAN_PAGE)))
863	{
864	l_REMDoForcedActions:
865	if (fInREMState)
866	{
867	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
868	REMR3StateBack(pVM);
869	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
870	fInREMState = false;
871	}
872	STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
873	rc = emR3ForcedActions(pVM, rc);
874	STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
875	if ( rc != VINF_SUCCESS
876	&& rc != VINF_EM_RESCHEDULE_REM)
877	{
878	*pfFFDone = true;
879	break;
880	}
881	}
882
883	} /* The Inner Loop, recompiled execution mode version. */
884
885
886	/*
887	* Returning. Sync back the VM state if required.
888	*/
889	if (fInREMState)
890	{
891	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
892	REMR3StateBack(pVM);
893	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
894	}
895
896	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
897	return rc;
898	}
899
900
901	/**
902	* Resumes executing hypervisor after a debug event.
903	*
904	* This is kind of special since our current guest state is
905	* potentially out of sync.
906	*
907	* @returns VBox status code.
908	* @param pVM The VM handle.
909	*/
910	static int emR3RawResumeHyper(PVM pVM)
911	{
912	int rc;
913	PCPUMCTX pCtx = pVM->em.s.pCtx;
914	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
915	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
916
917	/*
918	* Resume execution.
919	*/
920	CPUMRawEnter(pVM, NULL);
921	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
922	rc = VMMR3ResumeHyper(pVM);
923	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
924	rc = CPUMRawLeave(pVM, NULL, rc);
925	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
926
927	/*
928	* Deal with the return code.
929	*/
930	rc = emR3HighPriorityPostForcedActions(pVM, rc);
931	rc = emR3RawHandleRC(pVM, pCtx, rc);
932	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
933	return rc;
934	}
935
936
937	/**
938	* Steps rawmode.
939	*
940	* @returns VBox status code.
941	* @param pVM The VM handle.
942	*/
943	static int emR3RawStep(PVM pVM)
944	{
945	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
946	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
947	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
948	int rc;
949	PCPUMCTX pCtx = pVM->em.s.pCtx;
950	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
951	#ifndef DEBUG_sandervl
952	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
953	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
954	#endif
955	if (fGuest)
956	{
957	/*
958	* Check vital forced actions, but ignore pending interrupts and timers.
959	*/
960	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
961	{
962	rc = emR3RawForcedActions(pVM, pCtx);
963	if (VBOX_FAILURE(rc))
964	return rc;
965	}
966
967	/*
968	* Set flags for single stepping.
969	*/
970	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
971	}
972	else
973	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
974
975	/*
976	* Single step.
977	* We do not start time or anything, if anything we should just do a few nanoseconds.
978	*/
979	CPUMRawEnter(pVM, NULL);
980	do
981	{
982	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
983	rc = VMMR3ResumeHyper(pVM);
984	else
985	rc = VMMR3RawRunGC(pVM);
986	#ifndef DEBUG_sandervl
987	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
988	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
989	#endif
990	} while ( rc == VINF_SUCCESS
991	\|\| rc == VINF_EM_RAW_INTERRUPT);
992	rc = CPUMRawLeave(pVM, NULL, rc);
993	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
994
995	/*
996	* Make sure the trap flag is cleared.
997	* (Too bad if the guest is trying to single step too.)
998	*/
999	if (fGuest)
1000	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1001	else
1002	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
1003
1004	/*
1005	* Deal with the return codes.
1006	*/
1007	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1008	rc = emR3RawHandleRC(pVM, pCtx, rc);
1009	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1010	return rc;
1011	}
1012
1013
1014	#ifdef DEBUG
1015
1016	/**
1017	* Steps hardware accelerated mode.
1018	*
1019	* @returns VBox status code.
1020	* @param pVM The VM handle.
1021	*/
1022	static int emR3HwAccStep(PVM pVM)
1023	{
1024	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1025
1026	int rc;
1027	PCPUMCTX pCtx = pVM->em.s.pCtx;
1028	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
1029
1030	/*
1031	* Check vital forced actions, but ignore pending interrupts and timers.
1032	*/
1033	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1034	{
1035	rc = emR3RawForcedActions(pVM, pCtx);
1036	if (VBOX_FAILURE(rc))
1037	return rc;
1038	}
1039	/*
1040	* Set flags for single stepping.
1041	*/
1042	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1043
1044	/*
1045	* Single step.
1046	* We do not start time or anything, if anything we should just do a few nanoseconds.
1047	*/
1048	do
1049	{
1050	rc = VMMR3HwAccRunGC(pVM);
1051	} while ( rc == VINF_SUCCESS
1052	\|\| rc == VINF_EM_RAW_INTERRUPT);
1053	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1054
1055	/*
1056	* Make sure the trap flag is cleared.
1057	* (Too bad if the guest is trying to single step too.)
1058	*/
1059	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1060
1061	/*
1062	* Deal with the return codes.
1063	*/
1064	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1065	rc = emR3RawHandleRC(pVM, pCtx, rc);
1066	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1067	return rc;
1068	}
1069
1070
1071	void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1072	{
1073	EMSTATE enmOldState = pVM->em.s.enmState;
1074
1075	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1076
1077	Log(("Single step BEGIN:\n"));
1078	for (uint32_t i = 0; i < cIterations; i++)
1079	{
1080	DBGFR3PrgStep(pVM);
1081	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1082	emR3RawStep(pVM);
1083	}
1084	Log(("Single step END:\n"));
1085	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1086	pVM->em.s.enmState = enmOldState;
1087	}
1088
1089
1090	void emR3SingleStepExecHwAcc(PVM pVM, uint32_t cIterations)
1091	{
1092	EMSTATE enmOldState = pVM->em.s.enmState;
1093
1094	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1095
1096	Log(("Single step BEGIN:\n"));
1097	for (uint32_t i = 0; i < cIterations; i++)
1098	{
1099	DBGFR3PrgStep(pVM);
1100	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1101	emR3HwAccStep(pVM);
1102	}
1103	Log(("Single step END:\n"));
1104	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1105	pVM->em.s.enmState = enmOldState;
1106	}
1107
1108
1109	void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1110	{
1111	EMSTATE enmOldState = pVM->em.s.enmState;
1112
1113	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1114
1115	Log(("Single step BEGIN:\n"));
1116	for (uint32_t i = 0; i < cIterations; i++)
1117	{
1118	DBGFR3PrgStep(pVM);
1119	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1120	emR3RemStep(pVM);
1121	}
1122	Log(("Single step END:\n"));
1123	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1124	pVM->em.s.enmState = enmOldState;
1125	}
1126
1127	#endif /* DEBUG */
1128
1129
1130	/**
1131	* Executes one (or perhaps a few more) instruction(s).
1132	*
1133	* @returns VBox status code suitable for EM.
1134	*
1135	* @param pVM VM handle.
1136	* @param rcGC GC return code
1137	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1138	* instruction and prefix the log output with this text.
1139	*/
1140	#ifdef LOG_ENABLED
1141	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1142	#else
1143	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1144	#endif
1145	{
1146	PCPUMCTX pCtx = pVM->em.s.pCtx;
1147	int rc;
1148
1149	/*
1150	*
1151	* The simple solution is to use the recompiler.
1152	* The better solution is to disassemble the current instruction and
1153	* try handle as many as possible without using REM.
1154	*
1155	*/
1156
1157	#ifdef LOG_ENABLED
1158	/*
1159	* Disassemble the instruction if requested.
1160	*/
1161	if (pszPrefix)
1162	{
1163	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1164	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1165	}
1166	#endif /* LOG_ENABLED */
1167
1168	/*
1169	* PATM is making life more interesting.
1170	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1171	* tell PATM there is a trap in this code and have it take the appropriate actions
1172	* to allow us execute the code in REM.
1173	*/
1174	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1175	{
1176	Log(("emR3RawExecuteInstruction: In patch block. eip=%VRv\n", pCtx->eip));
1177
1178	RTGCPTR pNewEip;
1179	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1180	switch (rc)
1181	{
1182	/*
1183	* It's not very useful to emulate a single instruction and then go back to raw
1184	* mode; just execute the whole block until IF is set again.
1185	*/
1186	case VINF_SUCCESS:
1187	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1188	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1189	pCtx->eip = pNewEip;
1190	Assert(pCtx->eip);
1191
1192	if (pCtx->eflags.Bits.u1IF)
1193	{
1194	/*
1195	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1196	*/
1197	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1198	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1199	}
1200	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1201	{
1202	/* special case: iret, that sets IF, detected a pending irq/event */
1203	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1204	}
1205	return VINF_EM_RESCHEDULE_REM;
1206
1207	/*
1208	* One instruction.
1209	*/
1210	case VINF_PATCH_EMULATE_INSTR:
1211	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1212	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1213	pCtx->eip = pNewEip;
1214	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1215
1216	/*
1217	* The patch was disabled, hand it to the REM.
1218	*/
1219	case VERR_PATCH_DISABLED:
1220	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1221	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1222	pCtx->eip = pNewEip;
1223	if (pCtx->eflags.Bits.u1IF)
1224	{
1225	/*
1226	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1227	*/
1228	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1229	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1230	}
1231	return VINF_EM_RESCHEDULE_REM;
1232
1233	/* Force continued patch exection; usually due to write monitored stack. */
1234	case VINF_PATCH_CONTINUE:
1235	return VINF_SUCCESS;
1236
1237	default:
1238	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1239	return VERR_INTERNAL_ERROR;
1240	}
1241	}
1242
1243	#if 0
1244	/* Try our own instruction emulator before falling back to the recompiler. */
1245	DISCPUSTATE Cpu;
1246	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1247	if (VBOX_SUCCESS(rc))
1248	{
1249	uint32_t size;
1250
1251	switch (Cpu.pCurInstr->opcode)
1252	{
1253	/* @todo we can do more now */
1254	case OP_MOV:
1255	case OP_AND:
1256	case OP_OR:
1257	case OP_XOR:
1258	case OP_POP:
1259	case OP_INC:
1260	case OP_DEC:
1261	case OP_XCHG:
1262	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1263	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1264	if (VBOX_SUCCESS(rc))
1265	{
1266	pCtx->rip += Cpu.opsize;
1267	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1268	return rc;
1269	}
1270	if (rc != VERR_EM_INTERPRETER)
1271	AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1272	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1273	break;
1274	}
1275	}
1276	#endif /* 0 */
1277	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1278	rc = REMR3EmulateInstruction(pVM);
1279	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1280
1281	return rc;
1282	}
1283
1284
1285	/**
1286	* Executes one (or perhaps a few more) instruction(s).
1287	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1288	*
1289	* @returns VBox status code suitable for EM.
1290	* @param pVM VM handle.
1291	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1292	* instruction and prefix the log output with this text.
1293	* @param rcGC GC return code
1294	*/
1295	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1296	{
1297	#ifdef LOG_ENABLED
1298	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1299	#else
1300	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1301	#endif
1302	}
1303
1304	/**
1305	* Executes one (or perhaps a few more) IO instruction(s).
1306	*
1307	* @returns VBox status code suitable for EM.
1308	* @param pVM VM handle.
1309	*/
1310	int emR3RawExecuteIOInstruction(PVM pVM)
1311	{
1312	int rc;
1313	PCPUMCTX pCtx = pVM->em.s.pCtx;
1314
1315	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1316
1317	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1318	* as io instructions tend to come in packages of more than one
1319	*/
1320	DISCPUSTATE Cpu;
1321	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "IO EMU");
1322	if (VBOX_SUCCESS(rc))
1323	{
1324	rc = VINF_EM_RAW_EMULATE_INSTR;
1325
1326	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1327	{
1328	switch (Cpu.pCurInstr->opcode)
1329	{
1330	case OP_IN:
1331	{
1332	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1333	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1334	break;
1335	}
1336
1337	case OP_OUT:
1338	{
1339	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1340	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1341	break;
1342	}
1343	}
1344	}
1345	else if (Cpu.prefix & PREFIX_REP)
1346	{
1347	switch (Cpu.pCurInstr->opcode)
1348	{
1349	case OP_INSB:
1350	case OP_INSWD:
1351	{
1352	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1353	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1354	break;
1355	}
1356
1357	case OP_OUTSB:
1358	case OP_OUTSWD:
1359	{
1360	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1361	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1362	break;
1363	}
1364	}
1365	}
1366
1367	/*
1368	* Handled the I/O return codes.
1369	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1370	*/
1371	if (IOM_SUCCESS(rc))
1372	{
1373	pCtx->rip += Cpu.opsize;
1374	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1375	return rc;
1376	}
1377
1378	if (rc == VINF_EM_RAW_GUEST_TRAP)
1379	{
1380	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1381	rc = emR3RawGuestTrap(pVM);
1382	return rc;
1383	}
1384	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1385
1386	if (VBOX_FAILURE(rc))
1387	{
1388	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1389	return rc;
1390	}
1391	AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc=%Vrc\n", rc));
1392	}
1393	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1394	return emR3RawExecuteInstruction(pVM, "IO: ");
1395	}
1396
1397
1398	/**
1399	* Handle a guest context trap.
1400	*
1401	* @returns VBox status code suitable for EM.
1402	* @param pVM VM handle.
1403	*/
1404	static int emR3RawGuestTrap(PVM pVM)
1405	{
1406	PCPUMCTX pCtx = pVM->em.s.pCtx;
1407
1408	/*
1409	* Get the trap info.
1410	*/
1411	uint8_t u8TrapNo;
1412	TRPMEVENT enmType;
1413	RTGCUINT uErrorCode;
1414	RTGCUINTPTR uCR2;
1415	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1416	if (VBOX_FAILURE(rc))
1417	{
1418	AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1419	return rc;
1420	}
1421
1422	/* Traps can be directly forwarded in hardware accelerated mode. */
1423	if (HWACCMR3IsActive(pVM))
1424	{
1425	#ifdef LOGGING_ENABLED
1426	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1427	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1428	#endif
1429	return VINF_EM_RESCHEDULE_HWACC;
1430	}
1431
1432	/** Scan kernel code that traps; we might not get another chance. */
1433	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1434	&& !pCtx->eflags.Bits.u1VM)
1435	{
1436	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1437	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1438	}
1439
1440	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1441	{
1442	DISCPUSTATE cpu;
1443
1444	/* If MONITOR & MWAIT are supported, then interpret them here. */
1445	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1446	if ( VBOX_SUCCESS(rc)
1447	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1448	{
1449	uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1450
1451	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1452
1453	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1454	{
1455	rc = TRPMResetTrap(pVM);
1456	AssertRC(rc);
1457
1458	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1459	if (VBOX_SUCCESS(rc))
1460	{
1461	pCtx->rip += cpu.opsize;
1462	return rc;
1463	}
1464	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1465	}
1466	}
1467	}
1468	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1469	{
1470	DISCPUSTATE cpu;
1471
1472	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1473	if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1474	{
1475	/*
1476	* We should really check the TSS for the IO bitmap, but it's not like this
1477	* lazy approach really makes things worse.
1478	*/
1479	rc = TRPMResetTrap(pVM);
1480	AssertRC(rc);
1481	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1482	}
1483	}
1484
1485	#ifdef LOG_ENABLED
1486	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1487	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1488
1489	/* Get guest page information. */
1490	uint64_t fFlags = 0;
1491	RTGCPHYS GCPhys = 0;
1492	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1493	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1494	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1495	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1496	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1497	#endif
1498
1499	/*
1500	* #PG has CR2.
1501	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1502	*/
1503	if (u8TrapNo == 14 /* #PG */)
1504	pCtx->cr2 = uCR2;
1505
1506	return VINF_EM_RESCHEDULE_REM;
1507	}
1508
1509
1510	/**
1511	* Handle a ring switch trap.
1512	* Need to do statistics and to install patches. The result is going to REM.
1513	*
1514	* @returns VBox status code suitable for EM.
1515	* @param pVM VM handle.
1516	*/
1517	int emR3RawRingSwitch(PVM pVM)
1518	{
1519	int rc;
1520	DISCPUSTATE Cpu;
1521	PCPUMCTX pCtx = pVM->em.s.pCtx;
1522
1523	/*
1524	* sysenter, syscall & callgate
1525	*/
1526	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1527	if (VBOX_SUCCESS(rc))
1528	{
1529	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1530	{
1531	if (pCtx->SysEnter.cs != 0)
1532	{
1533	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1534	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1535	if (VBOX_SUCCESS(rc))
1536	{
1537	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1538	return VINF_EM_RESCHEDULE_RAW;
1539	}
1540	}
1541	}
1542
1543	#ifdef VBOX_WITH_STATISTICS
1544	switch (Cpu.pCurInstr->opcode)
1545	{
1546	case OP_SYSENTER:
1547	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysEnter);
1548	break;
1549	case OP_SYSEXIT:
1550	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysExit);
1551	break;
1552	case OP_SYSCALL:
1553	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysCall);
1554	break;
1555	case OP_SYSRET:
1556	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysRet);
1557	break;
1558	}
1559	#endif
1560	}
1561	else
1562	AssertRC(rc);
1563
1564	/* go to the REM to emulate a single instruction */
1565	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1566	}
1567
1568	/**
1569	* Handle a trap (\#PF or \#GP) in patch code
1570	*
1571	* @returns VBox status code suitable for EM.
1572	* @param pVM VM handle.
1573	* @param pCtx CPU context
1574	* @param gcret GC return code
1575	*/
1576	int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1577	{
1578	uint8_t u8TrapNo;
1579	int rc;
1580	TRPMEVENT enmType;
1581	RTGCUINT uErrorCode;
1582	RTGCUINTPTR uCR2;
1583
1584	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1585
1586	if (gcret == VINF_PATM_PATCH_INT3)
1587	{
1588	u8TrapNo = 3;
1589	uCR2 = 0;
1590	uErrorCode = 0;
1591	}
1592	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
1593	{
1594	/* No active trap in this case. Kind of ugly. */
1595	u8TrapNo = X86_XCPT_GP;
1596	uCR2 = 0;
1597	uErrorCode = 0;
1598	}
1599	else
1600	{
1601	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1602	if (VBOX_FAILURE(rc))
1603	{
1604	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1605	return rc;
1606	}
1607	/* Reset the trap as we'll execute the original instruction again. */
1608	TRPMResetTrap(pVM);
1609	}
1610
1611	/*
1612	* Deal with traps inside patch code.
1613	* (This code won't run outside GC.)
1614	*/
1615	if (u8TrapNo != 1)
1616	{
1617	#ifdef LOG_ENABLED
1618	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1619	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1620
1621	DISCPUSTATE Cpu;
1622	int rc;
1623
1624	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1625	if ( VBOX_SUCCESS(rc)
1626	&& Cpu.pCurInstr->opcode == OP_IRET)
1627	{
1628	uint32_t eip, selCS, uEFlags;
1629
1630	/* Iret crashes are bad as we have already changed the flags on the stack */
1631	rc = PGMPhysSimpleReadGCPtr(pVM, &eip, pCtx->esp, 4);
1632	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1633	rc \|= PGMPhysSimpleReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1634	if (rc == VINF_SUCCESS)
1635	{
1636	if ( (uEFlags & X86_EFL_VM)
1637	\|\| (selCS & X86_SEL_RPL) == 3)
1638	{
1639	uint32_t selSS, esp;
1640
1641	rc \|= PGMPhysSimpleReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1642	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1643
1644	if (uEFlags & X86_EFL_VM)
1645	{
1646	uint32_t selDS, selES, selFS, selGS;
1647	rc = PGMPhysSimpleReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1648	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1649	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1650	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1651	if (rc == VINF_SUCCESS)
1652	{
1653	Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1654	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1655	}
1656	}
1657	else
1658	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1659	}
1660	else
1661	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1662	}
1663	}
1664	#endif /* LOG_ENABLED */
1665	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1666	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1667
1668	RTGCPTR pNewEip;
1669	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1670	switch (rc)
1671	{
1672	/*
1673	* Execute the faulting instruction.
1674	*/
1675	case VINF_SUCCESS:
1676	{
1677	/** @todo execute a whole block */
1678	Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1679	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1680	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1681
1682	pCtx->eip = pNewEip;
1683	AssertRelease(pCtx->eip);
1684
1685	if (pCtx->eflags.Bits.u1IF)
1686	{
1687	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1688	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1689	*/
1690	if ( u8TrapNo == X86_XCPT_GP
1691	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1692	{
1693	/** @todo move to PATMR3HandleTrap */
1694	Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1695	PATMR3RemovePatch(pVM, pCtx->eip);
1696	}
1697
1698	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1699	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
1700
1701	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1702	/* Interrupts are enabled; just go back to the original instruction.
1703	return VINF_SUCCESS; */
1704	}
1705	return VINF_EM_RESCHEDULE_REM;
1706	}
1707
1708	/*
1709	* One instruction.
1710	*/
1711	case VINF_PATCH_EMULATE_INSTR:
1712	Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1713	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1714	pCtx->eip = pNewEip;
1715	AssertRelease(pCtx->eip);
1716	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1717
1718	/*
1719	* The patch was disabled, hand it to the REM.
1720	*/
1721	case VERR_PATCH_DISABLED:
1722	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1723	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1724	pCtx->eip = pNewEip;
1725	AssertRelease(pCtx->eip);
1726
1727	if (pCtx->eflags.Bits.u1IF)
1728	{
1729	/*
1730	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1731	*/
1732	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1733	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1734	}
1735	return VINF_EM_RESCHEDULE_REM;
1736
1737	/* Force continued patch exection; usually due to write monitored stack. */
1738	case VINF_PATCH_CONTINUE:
1739	return VINF_SUCCESS;
1740
1741	/*
1742	* Anything else is fatal.
1743	*/
1744	default:
1745	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1746	return VERR_INTERNAL_ERROR;
1747	}
1748	}
1749	return VINF_SUCCESS;
1750	}
1751
1752
1753	/**
1754	* Handle a privileged instruction.
1755	*
1756	* @returns VBox status code suitable for EM.
1757	* @param pVM VM handle.
1758	*/
1759	int emR3RawPrivileged(PVM pVM)
1760	{
1761	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1762	PCPUMCTX pCtx = pVM->em.s.pCtx;
1763
1764	Assert(!pCtx->eflags.Bits.u1VM);
1765
1766	if (PATMIsEnabled(pVM))
1767	{
1768	/*
1769	* Check if in patch code.
1770	*/
1771	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1772	{
1773	#ifdef LOG_ENABLED
1774	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1775	#endif
1776	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1777	return VERR_EM_RAW_PATCH_CONFLICT;
1778	}
1779	if ( (pCtx->ss & X86_SEL_RPL) == 0
1780	&& !pCtx->eflags.Bits.u1VM
1781	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1782	{
1783	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1784	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1785	if (VBOX_SUCCESS(rc))
1786	{
1787	#ifdef LOG_ENABLED
1788	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1789	#endif
1790	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1791	return VINF_SUCCESS;
1792	}
1793	}
1794	}
1795
1796	#ifdef LOG_ENABLED
1797	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1798	{
1799	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1800	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1801	}
1802	#endif
1803
1804	/*
1805	* Instruction statistics and logging.
1806	*/
1807	DISCPUSTATE Cpu;
1808	int rc;
1809
1810	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1811	if (VBOX_SUCCESS(rc))
1812	{
1813	#ifdef VBOX_WITH_STATISTICS
1814	PEMSTATS pStats = pVM->em.s.CTX_SUFF(pStats);
1815	switch (Cpu.pCurInstr->opcode)
1816	{
1817	case OP_INVLPG:
1818	STAM_COUNTER_INC(&pStats->StatInvlpg);
1819	break;
1820	case OP_IRET:
1821	STAM_COUNTER_INC(&pStats->StatIret);
1822	break;
1823	case OP_CLI:
1824	STAM_COUNTER_INC(&pStats->StatCli);
1825	emR3RecordCli(pVM, pCtx->rip);
1826	break;
1827	case OP_STI:
1828	STAM_COUNTER_INC(&pStats->StatSti);
1829	break;
1830	case OP_INSB:
1831	case OP_INSWD:
1832	case OP_IN:
1833	case OP_OUTSB:
1834	case OP_OUTSWD:
1835	case OP_OUT:
1836	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1837	break;
1838
1839	case OP_MOV_CR:
1840	if (Cpu.param1.flags & USE_REG_GEN32)
1841	{
1842	//read
1843	Assert(Cpu.param2.flags & USE_REG_CR);
1844	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1845	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1846	}
1847	else
1848	{
1849	//write
1850	Assert(Cpu.param1.flags & USE_REG_CR);
1851	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1852	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1853	}
1854	break;
1855
1856	case OP_MOV_DR:
1857	STAM_COUNTER_INC(&pStats->StatMovDRx);
1858	break;
1859	case OP_LLDT:
1860	STAM_COUNTER_INC(&pStats->StatMovLldt);
1861	break;
1862	case OP_LIDT:
1863	STAM_COUNTER_INC(&pStats->StatMovLidt);
1864	break;
1865	case OP_LGDT:
1866	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1867	break;
1868	case OP_SYSENTER:
1869	STAM_COUNTER_INC(&pStats->StatSysEnter);
1870	break;
1871	case OP_SYSEXIT:
1872	STAM_COUNTER_INC(&pStats->StatSysExit);
1873	break;
1874	case OP_SYSCALL:
1875	STAM_COUNTER_INC(&pStats->StatSysCall);
1876	break;
1877	case OP_SYSRET:
1878	STAM_COUNTER_INC(&pStats->StatSysRet);
1879	break;
1880	case OP_HLT:
1881	STAM_COUNTER_INC(&pStats->StatHlt);
1882	break;
1883	default:
1884	STAM_COUNTER_INC(&pStats->StatMisc);
1885	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1886	break;
1887	}
1888	#endif /* VBOX_WITH_STATISTICS */
1889	if ( (pCtx->ss & X86_SEL_RPL) == 0
1890	&& !pCtx->eflags.Bits.u1VM
1891	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
1892	{
1893	uint32_t size;
1894
1895	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1896	switch (Cpu.pCurInstr->opcode)
1897	{
1898	case OP_CLI:
1899	pCtx->eflags.u32 &= ~X86_EFL_IF;
1900	Assert(Cpu.opsize == 1);
1901	pCtx->rip += Cpu.opsize;
1902	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1903	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1904
1905	case OP_STI:
1906	pCtx->eflags.u32 \|= X86_EFL_IF;
1907	EMSetInhibitInterruptsPC(pVM, pCtx->rip + Cpu.opsize);
1908	Assert(Cpu.opsize == 1);
1909	pCtx->rip += Cpu.opsize;
1910	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1911	return VINF_SUCCESS;
1912
1913	case OP_HLT:
1914	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1915	{
1916	PATMTRANSSTATE enmState;
1917	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1918
1919	if (enmState == PATMTRANS_OVERWRITTEN)
1920	{
1921	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1922	Assert(rc == VERR_PATCH_DISABLED);
1923	/* Conflict detected, patch disabled */
1924	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1925
1926	enmState = PATMTRANS_SAFE;
1927	}
1928
1929	/* The translation had better be successful. Otherwise we can't recover. */
1930	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1931	if (enmState != PATMTRANS_OVERWRITTEN)
1932	pCtx->eip = pOrgInstrGC;
1933	}
1934	/* no break; we could just return VINF_EM_HALT here */
1935
1936	case OP_MOV_CR:
1937	case OP_MOV_DR:
1938	#ifdef LOG_ENABLED
1939	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1940	{
1941	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1942	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1943	}
1944	#endif
1945
1946	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1947	if (VBOX_SUCCESS(rc))
1948	{
1949	pCtx->rip += Cpu.opsize;
1950	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1951
1952	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1953	&& Cpu.param1.flags == USE_REG_CR /* write */
1954	)
1955	{
1956	/* Deal with CR0 updates inside patch code that force
1957	* us to go to the recompiler.
1958	*/
1959	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1960	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1961	{
1962	PATMTRANSSTATE enmState;
1963	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1964
1965	Assert(pCtx->eflags.Bits.u1IF == 0);
1966	Log(("Force recompiler switch due to cr0 (%VGp) update\n", pCtx->cr0));
1967	if (enmState == PATMTRANS_OVERWRITTEN)
1968	{
1969	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1970	Assert(rc == VERR_PATCH_DISABLED);
1971	/* Conflict detected, patch disabled */
1972	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->rip));
1973	enmState = PATMTRANS_SAFE;
1974	}
1975	/* The translation had better be successful. Otherwise we can't recover. */
1976	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->rip));
1977	if (enmState != PATMTRANS_OVERWRITTEN)
1978	pCtx->rip = pOrgInstrGC;
1979	}
1980
1981	/* Reschedule is necessary as the execution/paging mode might have changed. */
1982	return VINF_EM_RESCHEDULE;
1983	}
1984	return rc; /* can return VINF_EM_HALT as well. */
1985	}
1986	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
1987	break; /* fall back to the recompiler */
1988	}
1989	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1990	}
1991	}
1992
1993	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1994	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
1995
1996	return emR3RawExecuteInstruction(pVM, "PRIV");
1997	}
1998
1999
2000	/**
2001	* Update the forced rawmode execution modifier.
2002	*
2003	* This function is called when we're returning from the raw-mode loop(s). If we're
2004	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2005	* if not in patch code, the flag will be cleared.
2006	*
2007	* We should never interrupt patch code while it's being executed. Cli patches can
2008	* contain big code blocks, but they are always executed with IF=0. Other patches
2009	* replace single instructions and should be atomic.
2010	*
2011	* @returns Updated rc.
2012	*
2013	* @param pVM The VM handle.
2014	* @param pCtx The guest CPU context.
2015	* @param rc The result code.
2016	*/
2017	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2018	{
2019	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2020	{
2021	/* ignore reschedule attempts. */
2022	switch (rc)
2023	{
2024	case VINF_EM_RESCHEDULE:
2025	case VINF_EM_RESCHEDULE_REM:
2026	rc = VINF_SUCCESS;
2027	break;
2028	}
2029	pVM->em.s.fForceRAW = true;
2030	}
2031	else
2032	pVM->em.s.fForceRAW = false;
2033	return rc;
2034	}
2035
2036
2037	/**
2038	* Process a subset of the raw-mode return code.
2039	*
2040	* Since we have to share this with raw-mode single stepping, this inline
2041	* function has been created to avoid code duplication.
2042	*
2043	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2044	* @returns VBox status code to return to the EM main loop.
2045	*
2046	* @param pVM The VM handle
2047	* @param rc The return code.
2048	* @param pCtx The guest cpu context.
2049	*/
2050	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2051	{
2052	switch (rc)
2053	{
2054	/*
2055	* Common & simple ones.
2056	*/
2057	case VINF_SUCCESS:
2058	break;
2059	case VINF_EM_RESCHEDULE_RAW:
2060	case VINF_EM_RESCHEDULE_HWACC:
2061	case VINF_EM_RAW_INTERRUPT:
2062	case VINF_EM_RAW_TO_R3:
2063	case VINF_EM_RAW_TIMER_PENDING:
2064	case VINF_EM_PENDING_REQUEST:
2065	rc = VINF_SUCCESS;
2066	break;
2067
2068	/*
2069	* Privileged instruction.
2070	*/
2071	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2072	case VINF_PATM_PATCH_TRAP_GP:
2073	rc = emR3RawPrivileged(pVM);
2074	break;
2075
2076	/*
2077	* Got a trap which needs dispatching.
2078	*/
2079	case VINF_EM_RAW_GUEST_TRAP:
2080	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2081	{
2082	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2083	rc = VERR_EM_RAW_PATCH_CONFLICT;
2084	break;
2085	}
2086
2087	Assert(TRPMHasTrap(pVM));
2088	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2089
2090	if (TRPMHasTrap(pVM))
2091	{
2092	uint8_t u8Interrupt;
2093	RTGCUINT uErrorCode;
2094	TRPMERRORCODE enmError = TRPM_TRAP_NO_ERRORCODE;
2095
2096	rc = TRPMQueryTrapAll(pVM, &u8Interrupt, NULL, &uErrorCode, NULL);
2097	AssertRC(rc);
2098
2099	if (uErrorCode != ~0U)
2100	enmError = TRPM_TRAP_HAS_ERRORCODE;
2101
2102	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2103	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2104	{
2105	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2106	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2107
2108	/** If it was successful, then we could go back to raw mode. */
2109	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER)
2110	{
2111	/* Must check pending forced actions as our IDT or GDT might be out of sync */
2112	EMR3CheckRawForcedActions(pVM);
2113
2114	rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8Interrupt, uErrorCode, enmError, TRPM_TRAP, -1);
2115	if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
2116	{
2117	TRPMResetTrap(pVM);
2118	return VINF_EM_RESCHEDULE_RAW;
2119	}
2120	}
2121	}
2122	}
2123	rc = emR3RawGuestTrap(pVM);
2124	break;
2125
2126	/*
2127	* Trap in patch code.
2128	*/
2129	case VINF_PATM_PATCH_TRAP_PF:
2130	case VINF_PATM_PATCH_INT3:
2131	rc = emR3PatchTrap(pVM, pCtx, rc);
2132	break;
2133
2134	case VINF_PATM_DUPLICATE_FUNCTION:
2135	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2136	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2137	AssertRC(rc);
2138	rc = VINF_SUCCESS;
2139	break;
2140
2141	case VINF_PATM_CHECK_PATCH_PAGE:
2142	rc = PATMR3HandleMonitoredPage(pVM);
2143	AssertRC(rc);
2144	rc = VINF_SUCCESS;
2145	break;
2146
2147	/*
2148	* Patch manager.
2149	*/
2150	case VERR_EM_RAW_PATCH_CONFLICT:
2151	AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2152	break;
2153
2154	/*
2155	* Memory mapped I/O access - attempt to patch the instruction
2156	*/
2157	case VINF_PATM_HC_MMIO_PATCH_READ:
2158	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2159	PATMFL_MMIO_ACCESS \| ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2160	if (VBOX_FAILURE(rc))
2161	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2162	break;
2163
2164	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2165	AssertFailed(); /* not yet implemented. */
2166	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2167	break;
2168
2169	/*
2170	* Conflict or out of page tables.
2171	*
2172	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2173	* do here is to execute the pending forced actions.
2174	*/
2175	case VINF_PGM_SYNC_CR3:
2176	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2177	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2178	rc = VINF_SUCCESS;
2179	break;
2180
2181	/*
2182	* Paging mode change.
2183	*/
2184	case VINF_PGM_CHANGE_MODE:
2185	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2186	if (VBOX_SUCCESS(rc))
2187	rc = VINF_EM_RESCHEDULE;
2188	break;
2189
2190	/*
2191	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2192	*/
2193	case VINF_CSAM_PENDING_ACTION:
2194	rc = VINF_SUCCESS;
2195	break;
2196
2197	/*
2198	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2199	*/
2200	case VINF_EM_RAW_INTERRUPT_PENDING:
2201	case VINF_EM_RAW_RING_SWITCH_INT:
2202	{
2203	uint8_t u8Interrupt;
2204
2205	Assert(TRPMHasTrap(pVM));
2206	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2207
2208	if (TRPMHasTrap(pVM))
2209	{
2210	u8Interrupt = TRPMGetTrapNo(pVM);
2211
2212	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2213	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2214	{
2215	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2216	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2217	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2218	}
2219	}
2220	rc = VINF_EM_RESCHEDULE_REM;
2221	break;
2222	}
2223
2224	/*
2225	* Other ring switch types.
2226	*/
2227	case VINF_EM_RAW_RING_SWITCH:
2228	rc = emR3RawRingSwitch(pVM);
2229	break;
2230
2231	/*
2232	* REMGCNotifyInvalidatePage() failed because of overflow.
2233	*/
2234	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2235	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2236	REMR3ReplayInvalidatedPages(pVM);
2237	rc = VINF_SUCCESS;
2238	break;
2239
2240	/*
2241	* I/O Port access - emulate the instruction.
2242	*/
2243	case VINF_IOM_HC_IOPORT_READ:
2244	case VINF_IOM_HC_IOPORT_WRITE:
2245	rc = emR3RawExecuteIOInstruction(pVM);
2246	break;
2247
2248	/*
2249	* Memory mapped I/O access - emulate the instruction.
2250	*/
2251	case VINF_IOM_HC_MMIO_READ:
2252	case VINF_IOM_HC_MMIO_WRITE:
2253	case VINF_IOM_HC_MMIO_READ_WRITE:
2254	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2255	break;
2256
2257	/*
2258	* Execute instruction.
2259	*/
2260	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2261	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2262	break;
2263	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2264	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2265	break;
2266	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2267	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2268	break;
2269	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2270	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2271	break;
2272	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2273	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2274	break;
2275
2276	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2277	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2278	rc = emR3RawPrivileged(pVM);
2279	break;
2280
2281	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2282	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2283	break;
2284
2285	case VINF_EM_RAW_EMULATE_INSTR:
2286	case VINF_PATCH_EMULATE_INSTR:
2287	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2288	break;
2289
2290	/*
2291	* Stale selector and iret traps => REM.
2292	*/
2293	case VINF_EM_RAW_STALE_SELECTOR:
2294	case VINF_EM_RAW_IRET_TRAP:
2295	/* We will not go to the recompiler if EIP points to patch code. */
2296	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2297	{
2298	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2299	}
2300	LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2301	rc = VINF_EM_RESCHEDULE_REM;
2302	break;
2303
2304	/*
2305	* Up a level.
2306	*/
2307	case VINF_EM_TERMINATE:
2308	case VINF_EM_OFF:
2309	case VINF_EM_RESET:
2310	case VINF_EM_SUSPEND:
2311	case VINF_EM_HALT:
2312	case VINF_EM_RESUME:
2313	case VINF_EM_RESCHEDULE:
2314	case VINF_EM_RESCHEDULE_REM:
2315	break;
2316
2317	/*
2318	* Up a level and invoke the debugger.
2319	*/
2320	case VINF_EM_DBG_STEPPED:
2321	case VINF_EM_DBG_BREAKPOINT:
2322	case VINF_EM_DBG_STEP:
2323	case VINF_EM_DBG_HYPER_ASSERTION:
2324	case VINF_EM_DBG_HYPER_BREAKPOINT:
2325	case VINF_EM_DBG_HYPER_STEPPED:
2326	case VINF_EM_DBG_STOP:
2327	break;
2328
2329	/*
2330	* Up a level, dump and debug.
2331	*/
2332	case VERR_TRPM_DONT_PANIC:
2333	case VERR_TRPM_PANIC:
2334	break;
2335
2336	case VERR_VMX_INVALID_VMCS_FIELD:
2337	case VERR_VMX_INVALID_VMCS_PTR:
2338	case VERR_VMX_INVALID_VMXON_PTR:
2339	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
2340	case VERR_VMX_UNEXPECTED_EXCEPTION:
2341	case VERR_VMX_UNEXPECTED_EXIT_CODE:
2342	case VERR_VMX_INVALID_GUEST_STATE:
2343	HWACCMR3CheckError(pVM, rc);
2344	break;
2345	/*
2346	* Anything which is not known to us means an internal error
2347	* and the termination of the VM!
2348	*/
2349	default:
2350	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2351	break;
2352	}
2353	return rc;
2354	}
2355
2356
2357	/**
2358	* Check for pending raw actions
2359	*
2360	* @returns VBox status code.
2361	* @param pVM The VM to operate on.
2362	*/
2363	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2364	{
2365	return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2366	}
2367
2368
2369	/**
2370	* Process raw-mode specific forced actions.
2371	*
2372	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2373	*
2374	* @returns VBox status code.
2375	* Only the normal success/failure stuff, no VINF_EM_*.
2376	* @param pVM The VM handle.
2377	* @param pCtx The guest CPUM register context.
2378	*/
2379	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2380	{
2381	/*
2382	* Note that the order is vitally important!
2383	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2384	*/
2385
2386
2387	/*
2388	* Sync selector tables.
2389	*/
2390	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2391	{
2392	int rc = SELMR3UpdateFromCPUM(pVM);
2393	if (VBOX_FAILURE(rc))
2394	return rc;
2395	}
2396
2397	/*
2398	* Sync IDT.
2399	*/
2400	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2401	{
2402	int rc = TRPMR3SyncIDT(pVM);
2403	if (VBOX_FAILURE(rc))
2404	return rc;
2405	}
2406
2407	/*
2408	* Sync TSS.
2409	*/
2410	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2411	{
2412	int rc = SELMR3SyncTSS(pVM);
2413	if (VBOX_FAILURE(rc))
2414	return rc;
2415	}
2416
2417	/*
2418	* Sync page directory.
2419	*/
2420	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2421	{
2422	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2423	if (VBOX_FAILURE(rc))
2424	return rc;
2425
2426	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2427
2428	/* Prefetch pages for EIP and ESP */
2429	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2430	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2431	if (rc == VINF_SUCCESS)
2432	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2433	if (rc != VINF_SUCCESS)
2434	{
2435	if (rc != VINF_PGM_SYNC_CR3)
2436	return rc;
2437	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2438	if (VBOX_FAILURE(rc))
2439	return rc;
2440	}
2441	/** @todo maybe prefetch the supervisor stack page as well */
2442	}
2443
2444	/*
2445	* Allocate handy pages (just in case the above actions have consumed some pages).
2446	*/
2447	if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
2448	{
2449	int rc = PGMR3PhysAllocateHandyPages(pVM);
2450	if (VBOX_FAILURE(rc))
2451	return rc;
2452	}
2453
2454	return VINF_SUCCESS;
2455	}
2456
2457
2458	/**
2459	* Executes raw code.
2460	*
2461	* This function contains the raw-mode version of the inner
2462	* execution loop (the outer loop being in EMR3ExecuteVM()).
2463	*
2464	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2465	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2466	*
2467	* @param pVM VM handle.
2468	* @param pfFFDone Where to store an indicator telling whether or not
2469	* FFs were done before returning.
2470	*/
2471	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2472	{
2473	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2474
2475	int rc = VERR_INTERNAL_ERROR;
2476	PCPUMCTX pCtx = pVM->em.s.pCtx;
2477	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2478	pVM->em.s.fForceRAW = false;
2479	*pfFFDone = false;
2480
2481
2482	/*
2483	*
2484	* Spin till we get a forced action or raw mode status code resulting in
2485	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2486	*
2487	*/
2488	for (;;)
2489	{
2490	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2491
2492	/*
2493	* Check various preconditions.
2494	*/
2495	#ifdef VBOX_STRICT
2496	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2497	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2498	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2499	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2500	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2501	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2502	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2503	{
2504	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2505	return VERR_INTERNAL_ERROR;
2506	}
2507	#endif /* VBOX_STRICT */
2508
2509	/*
2510	* Process high priority pre-execution raw-mode FFs.
2511	*/
2512	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2513	{
2514	rc = emR3RawForcedActions(pVM, pCtx);
2515	if (VBOX_FAILURE(rc))
2516	break;
2517	}
2518
2519	/*
2520	* If we're going to execute ring-0 code, the guest state needs to
2521	* be modified a bit and some of the state components (IF, SS/CS RPL,
2522	* and perhaps EIP) needs to be stored with PATM.
2523	*/
2524	rc = CPUMRawEnter(pVM, NULL);
2525	if (rc != VINF_SUCCESS)
2526	{
2527	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2528	break;
2529	}
2530
2531	/*
2532	* Scan code before executing it. Don't bother with user mode or V86 code
2533	*/
2534	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2535	&& !pCtx->eflags.Bits.u1VM
2536	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2537	{
2538	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2539	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2540	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2541	}
2542
2543	#ifdef LOG_ENABLED
2544	/*
2545	* Log important stuff before entering GC.
2546	*/
2547	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2548	if (pCtx->eflags.Bits.u1VM)
2549	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2550	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2551	{
2552	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2553	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2554	}
2555	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2556	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2557	#endif /* LOG_ENABLED */
2558
2559
2560
2561	/*
2562	* Execute the code.
2563	*/
2564	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2565	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2566	VMMR3Unlock(pVM);
2567	rc = VMMR3RawRunGC(pVM);
2568	VMMR3Lock(pVM);
2569	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2570	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2571
2572	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2573	LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2574
2575
2576
2577	/*
2578	* Restore the real CPU state and deal with high priority post
2579	* execution FFs before doing anything else.
2580	*/
2581	rc = CPUMRawLeave(pVM, NULL, rc);
2582	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2583	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2584	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2585
2586	#ifdef VBOX_STRICT
2587	/*
2588	* Assert TSS consistency & rc vs patch code.
2589	*/
2590	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2591	&& EMIsRawRing0Enabled(pVM))
2592	SELMR3CheckTSS(pVM);
2593	switch (rc)
2594	{
2595	case VINF_SUCCESS:
2596	case VINF_EM_RAW_INTERRUPT:
2597	case VINF_PATM_PATCH_TRAP_PF:
2598	case VINF_PATM_PATCH_TRAP_GP:
2599	case VINF_PATM_PATCH_INT3:
2600	case VINF_PATM_CHECK_PATCH_PAGE:
2601	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2602	case VINF_EM_RAW_GUEST_TRAP:
2603	case VINF_EM_RESCHEDULE_RAW:
2604	break;
2605
2606	default:
2607	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2608	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VRv for reason %Vrc\n", (RTRCPTR)CPUMGetGuestEIP(pVM), rc));
2609	break;
2610	}
2611	/*
2612	* Let's go paranoid!
2613	*/
2614	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2615	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2616	{
2617	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2618	return VERR_INTERNAL_ERROR;
2619	}
2620	#endif /* VBOX_STRICT */
2621
2622	/*
2623	* Process the returned status code.
2624	*/
2625	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2626	{
2627	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2628	break;
2629	}
2630	rc = emR3RawHandleRC(pVM, pCtx, rc);
2631	if (rc != VINF_SUCCESS)
2632	{
2633	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2634	if (rc != VINF_SUCCESS)
2635	{
2636	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2637	break;
2638	}
2639	}
2640
2641	/*
2642	* Check and execute forced actions.
2643	*/
2644	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2645	TMTimerPoll(pVM);
2646	#endif
2647	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2648	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2649	{
2650	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2651
2652	STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2653	rc = emR3ForcedActions(pVM, rc);
2654	STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2655	if ( rc != VINF_SUCCESS
2656	&& rc != VINF_EM_RESCHEDULE_RAW)
2657	{
2658	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2659	if (rc != VINF_SUCCESS)
2660	{
2661	*pfFFDone = true;
2662	break;
2663	}
2664	}
2665	}
2666	}
2667
2668	/*
2669	* Return to outer loop.
2670	*/
2671	#if defined(LOG_ENABLED) && defined(DEBUG)
2672	RTLogFlush(NULL);
2673	#endif
2674	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2675	return rc;
2676	}
2677
2678
2679	/**
2680	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2681	*
2682	* This function contains the raw-mode version of the inner
2683	* execution loop (the outer loop being in EMR3ExecuteVM()).
2684	*
2685	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2686	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2687	*
2688	* @param pVM VM handle.
2689	* @param pfFFDone Where to store an indicator telling whether or not
2690	* FFs were done before returning.
2691	*/
2692	static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2693	{
2694	int rc = VERR_INTERNAL_ERROR;
2695	PCPUMCTX pCtx = pVM->em.s.pCtx;
2696
2697	LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%VGv)\n", pCtx->cs, pCtx->rip));
2698	*pfFFDone = false;
2699
2700	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2701
2702	/*
2703	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2704	*/
2705	for (;;)
2706	{
2707	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2708
2709	/*
2710	* Check various preconditions.
2711	*/
2712	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2713
2714	/*
2715	* Process high priority pre-execution raw-mode FFs.
2716	*/
2717	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2718	{
2719	rc = emR3RawForcedActions(pVM, pCtx);
2720	if (VBOX_FAILURE(rc))
2721	break;
2722	}
2723
2724	#ifdef LOG_ENABLED
2725	/*
2726	* Log important stuff before entering GC.
2727	*/
2728	if (TRPMHasTrap(pVM))
2729	Log(("Pending hardware interrupt=0x%x cs:eip=%04X:%VGv\n", TRPMGetTrapNo(pVM), pCtx->cs, pCtx->rip));
2730
2731	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
2732	if (pCtx->eflags.Bits.u1VM)
2733	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2734	else if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
2735	Log(("HWR%d: %04X:%VGv ESP=%VGv IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2736	else
2737	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2738	#endif /* LOG_ENABLED */
2739
2740	/*
2741	* Execute the code.
2742	*/
2743	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2744	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2745	VMMR3Unlock(pVM);
2746	rc = VMMR3HwAccRunGC(pVM);
2747	VMMR3Lock(pVM);
2748	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2749
2750	/*
2751	* Deal with high priority post execution FFs before doing anything else.
2752	*/
2753	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2754	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2755	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2756
2757	/*
2758	* Process the returned status code.
2759	*/
2760	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2761	break;
2762
2763	rc = emR3RawHandleRC(pVM, pCtx, rc);
2764	if (rc != VINF_SUCCESS)
2765	break;
2766
2767	/*
2768	* Check and execute forced actions.
2769	*/
2770	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2771	TMTimerPoll(pVM);
2772	#endif
2773	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2774	{
2775	rc = emR3ForcedActions(pVM, rc);
2776	if ( rc != VINF_SUCCESS
2777	&& rc != VINF_EM_RESCHEDULE_HWACC)
2778	{
2779	*pfFFDone = true;
2780	break;
2781	}
2782	}
2783	}
2784	/*
2785	* Return to outer loop.
2786	*/
2787	#if defined(LOG_ENABLED) && defined(DEBUG)
2788	RTLogFlush(NULL);
2789	#endif
2790	return rc;
2791	}
2792
2793
2794	/**
2795	* Decides whether to execute RAW, HWACC or REM.
2796	*
2797	* @returns new EM state
2798	* @param pVM The VM.
2799	* @param pCtx The CPU context.
2800	*/
2801	DECLINLINE(EMSTATE) emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2802	{
2803	/*
2804	* When forcing raw-mode execution, things are simple.
2805	*/
2806	if (pVM->em.s.fForceRAW)
2807	return EMSTATE_RAW;
2808
2809	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2810	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2811	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2812
2813	X86EFLAGS EFlags = pCtx->eflags;
2814	if (HWACCMIsEnabled(pVM))
2815	{
2816	/* Hardware accelerated raw-mode:
2817	*
2818	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2819	*/
2820	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2821	return EMSTATE_HWACC;
2822
2823	/* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
2824	* off monitoring features essential for raw mode! */
2825	return EMSTATE_REM;
2826	}
2827
2828	/*
2829	* Standard raw-mode:
2830	*
2831	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2832	* or 32 bits protected mode ring 0 code
2833	*
2834	* The tests are ordered by the likelyhood of being true during normal execution.
2835	*/
2836	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2837	{
2838	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2839	return EMSTATE_REM;
2840	}
2841
2842	#ifndef VBOX_RAW_V86
2843	if (EFlags.u32 & X86_EFL_VM) {
2844	Log2(("raw mode refused: VM_MASK\n"));
2845	return EMSTATE_REM;
2846	}
2847	#endif
2848
2849	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2850	uint32_t u32CR0 = pCtx->cr0;
2851	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2852	{
2853	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2854	return EMSTATE_REM;
2855	}
2856
2857	if (pCtx->cr4 & X86_CR4_PAE)
2858	{
2859	uint32_t u32Dummy, u32Features;
2860
2861	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2862	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
2863	return EMSTATE_REM;
2864	}
2865
2866	unsigned uSS = pCtx->ss;
2867	if ( pCtx->eflags.Bits.u1VM
2868	\|\| (uSS & X86_SEL_RPL) == 3)
2869	{
2870	if (!EMIsRawRing3Enabled(pVM))
2871	return EMSTATE_REM;
2872
2873	if (!(EFlags.u32 & X86_EFL_IF))
2874	{
2875	Log2(("raw mode refused: IF (RawR3)\n"));
2876	return EMSTATE_REM;
2877	}
2878
2879	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2880	{
2881	Log2(("raw mode refused: CR0.WP + RawR0\n"));
2882	return EMSTATE_REM;
2883	}
2884	}
2885	else
2886	{
2887	if (!EMIsRawRing0Enabled(pVM))
2888	return EMSTATE_REM;
2889
2890	/* Only ring 0 supervisor code. */
2891	if ((uSS & X86_SEL_RPL) != 0)
2892	{
2893	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2894	return EMSTATE_REM;
2895	}
2896
2897	// Let's start with pure 32 bits ring 0 code first
2898	/** @todo What's pure 32-bit mode? flat? */
2899	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2900	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
2901	{
2902	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2903	return EMSTATE_REM;
2904	}
2905
2906	/* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2907	if (!(u32CR0 & X86_CR0_WP))
2908	{
2909	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2910	return EMSTATE_REM;
2911	}
2912
2913	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2914	{
2915	Log2(("raw r0 mode forced: patch code\n"));
2916	return EMSTATE_RAW;
2917	}
2918
2919	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2920	if (!(EFlags.u32 & X86_EFL_IF))
2921	{
2922	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2923	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2924	return EMSTATE_REM;
2925	}
2926	#endif
2927
2928	/** @todo still necessary??? */
2929	if (EFlags.Bits.u2IOPL != 0)
2930	{
2931	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2932	return EMSTATE_REM;
2933	}
2934	}
2935
2936	Assert(PGMPhysIsA20Enabled(pVM));
2937	return EMSTATE_RAW;
2938	}
2939
2940
2941	/**
2942	* Executes all high priority post execution force actions.
2943	*
2944	* @returns rc or a fatal status code.
2945	*
2946	* @param pVM VM handle.
2947	* @param rc The current rc.
2948	*/
2949	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2950	{
2951	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2952	PDMR3CritSectFF(pVM);
2953
2954	if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
2955	CSAMR3DoPendingAction(pVM);
2956
2957	return rc;
2958	}
2959
2960
2961	/**
2962	* Executes all pending forced actions.
2963	*
2964	* Forced actions can cause execution delays and execution
2965	* rescheduling. The first we deal with using action priority, so
2966	* that for instance pending timers aren't scheduled and ran until
2967	* right before execution. The rescheduling we deal with using
2968	* return codes. The same goes for VM termination, only in that case
2969	* we exit everything.
2970	*
2971	* @returns VBox status code of equal or greater importance/severity than rc.
2972	* The most important ones are: VINF_EM_RESCHEDULE,
2973	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2974	*
2975	* @param pVM VM handle.
2976	* @param rc The current rc.
2977	*
2978	*/
2979	static int emR3ForcedActions(PVM pVM, int rc)
2980	{
2981	STAM_REL_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2982	#ifdef VBOX_STRICT
2983	int rcIrq = VINF_SUCCESS;
2984	#endif
2985	int rc2;
2986	#define UPDATE_RC() \
2987	do { \
2988	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2989	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
2990	break; \
2991	if (!rc \|\| rc2 < rc) \
2992	rc = rc2; \
2993	} while (0)
2994
2995	/*
2996	* Post execution chunk first.
2997	*/
2998	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
2999	{
3000	/*
3001	* Termination request.
3002	*/
3003	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3004	{
3005	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3006	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3007	return VINF_EM_TERMINATE;
3008	}
3009
3010	/*
3011	* Debugger Facility polling.
3012	*/
3013	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3014	{
3015	rc2 = DBGFR3VMMForcedAction(pVM);
3016	UPDATE_RC();
3017	}
3018
3019	/*
3020	* Postponed reset request.
3021	*/
3022	if (VM_FF_ISSET(pVM, VM_FF_RESET))
3023	{
3024	rc2 = VMR3Reset(pVM);
3025	UPDATE_RC();
3026	VM_FF_CLEAR(pVM, VM_FF_RESET);
3027	}
3028
3029	/*
3030	* CSAM page scanning.
3031	*/
3032	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
3033	{
3034	PCPUMCTX pCtx = pVM->em.s.pCtx;
3035
3036	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3037	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3038
3039	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
3040	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3041	}
3042
3043	/* check that we got them all */
3044	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
3045	}
3046
3047	/*
3048	* Normal priority then.
3049	* (Executed in no particular order.)
3050	*/
3051	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3052	{
3053	/*
3054	* PDM Queues are pending.
3055	*/
3056	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3057	PDMR3QueueFlushAll(pVM);
3058
3059	/*
3060	* PDM DMA transfers are pending.
3061	*/
3062	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3063	PDMR3DmaRun(pVM);
3064
3065	/*
3066	* Requests from other threads.
3067	*/
3068	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3069	{
3070	rc2 = VMR3ReqProcessU(pVM->pUVM);
3071	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3072	{
3073	Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3074	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3075	return rc2;
3076	}
3077	UPDATE_RC();
3078	}
3079
3080	/* Replay the handler notification changes. */
3081	if (VM_FF_ISSET(pVM, VM_FF_REM_HANDLER_NOTIFY))
3082	REMR3ReplayHandlerNotifications(pVM);
3083
3084	/* check that we got them all */
3085	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY)));
3086	}
3087
3088	/*
3089	* Execute polling function ever so often.
3090	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING "SOON"!
3091	*/
3092	static unsigned cLast = 0;
3093	if (!((++cLast) % 4))
3094	PDMR3Poll(pVM);
3095
3096	/*
3097	* High priority pre execution chunk last.
3098	* (Executed in ascending priority order.)
3099	*/
3100	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3101	{
3102	/*
3103	* Timers before interrupts.
3104	*/
3105	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3106	TMR3TimerQueuesDo(pVM);
3107
3108	/*
3109	* The instruction following an emulated STI should always be executed!
3110	*/
3111	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3112	{
3113	Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", (RTGCPTR)CPUMGetGuestRIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3114	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3115	{
3116	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3117	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3118	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3119	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3120	*/
3121	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3122	}
3123	if (HWACCMR3IsActive(pVM))
3124	rc2 = VINF_EM_RESCHEDULE_HWACC;
3125	else
3126	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3127
3128	UPDATE_RC();
3129	}
3130
3131	/*
3132	* Interrupts.
3133	*/
3134	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3135	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_RAW)
3136	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3137	&& PATMAreInterruptsEnabled(pVM)
3138	&& !HWACCMR3IsEventPending(pVM))
3139	{
3140	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3141	{
3142	/* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3143	/** @todo this really isn't nice, should properly handle this */
3144	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3145	#ifdef VBOX_STRICT
3146	rcIrq = rc2;
3147	#endif
3148	UPDATE_RC();
3149	}
3150	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3151	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3152	{
3153	rc2 = VINF_EM_RESCHEDULE_REM;
3154	UPDATE_RC();
3155	}
3156	}
3157
3158	/*
3159	* Allocate handy pages.
3160	*/
3161	if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
3162	{
3163	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3164	UPDATE_RC();
3165	}
3166
3167	/*
3168	* Debugger Facility request.
3169	*/
3170	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3171	{
3172	rc2 = DBGFR3VMMForcedAction(pVM);
3173	UPDATE_RC();
3174	}
3175
3176	/*
3177	* Termination request.
3178	*/
3179	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3180	{
3181	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3182	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3183	return VINF_EM_TERMINATE;
3184	}
3185
3186	#ifdef DEBUG
3187	/*
3188	* Debug, pause the VM.
3189	*/
3190	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3191	{
3192	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3193	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3194	return VINF_EM_SUSPEND;
3195	}
3196
3197	#endif
3198	/* check that we got them all */
3199	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS \| VM_FF_PGM_NEED_HANDY_PAGES)));
3200	}
3201
3202	#undef UPDATE_RC
3203	Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3204	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3205	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3206	return rc;
3207	}
3208
3209
3210	/**
3211	* Execute VM.
3212	*
3213	* This function is the main loop of the VM. The emulation thread
3214	* calls this function when the VM has been successfully constructed
3215	* and we're ready for executing the VM.
3216	*
3217	* Returning from this function means that the VM is turned off or
3218	* suspended (state already saved) and deconstruction in next in line.
3219	*
3220	* All interaction from other thread are done using forced actions
3221	* and signaling of the wait object.
3222	*
3223	* @returns VBox status code.
3224	* @param pVM The VM to operate on.
3225	*/
3226	VMMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3227	{
3228	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3229	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3230	VM_ASSERT_EMT(pVM);
3231	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3232
3233	VMMR3Lock(pVM);
3234
3235	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3236	if (rc == 0)
3237	{
3238	/*
3239	* Start the virtual time.
3240	*/
3241	rc = TMVirtualResume(pVM);
3242	Assert(rc == VINF_SUCCESS);
3243	rc = TMCpuTickResume(pVM);
3244	Assert(rc == VINF_SUCCESS);
3245
3246	/*
3247	* The Outer Main Loop.
3248	*/
3249	bool fFFDone = false;
3250	rc = VINF_EM_RESCHEDULE;
3251	pVM->em.s.enmState = EMSTATE_REM;
3252	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3253	for (;;)
3254	{
3255	/*
3256	* Before we can schedule anything (we're here because
3257	* scheduling is required) we must service any pending
3258	* forced actions to avoid any pending action causing
3259	* immediate rescheduling upon entering an inner loop
3260	*
3261	* Do forced actions.
3262	*/
3263	if ( !fFFDone
3264	&& rc != VINF_EM_TERMINATE
3265	&& rc != VINF_EM_OFF
3266	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3267	{
3268	rc = emR3ForcedActions(pVM, rc);
3269	if ( ( rc == VINF_EM_RESCHEDULE_REM
3270	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3271	&& pVM->em.s.fForceRAW)
3272	rc = VINF_EM_RESCHEDULE_RAW;
3273	}
3274	else if (fFFDone)
3275	fFFDone = false;
3276
3277	/*
3278	* Now what to do?
3279	*/
3280	Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3281	switch (rc)
3282	{
3283	/*
3284	* Keep doing what we're currently doing.
3285	*/
3286	case VINF_SUCCESS:
3287	break;
3288
3289	/*
3290	* Reschedule - to raw-mode execution.
3291	*/
3292	case VINF_EM_RESCHEDULE_RAW:
3293	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3294	pVM->em.s.enmState = EMSTATE_RAW;
3295	break;
3296
3297	/*
3298	* Reschedule - to hardware accelerated raw-mode execution.
3299	*/
3300	case VINF_EM_RESCHEDULE_HWACC:
3301	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3302	Assert(!pVM->em.s.fForceRAW);
3303	pVM->em.s.enmState = EMSTATE_HWACC;
3304	break;
3305
3306	/*
3307	* Reschedule - to recompiled execution.
3308	*/
3309	case VINF_EM_RESCHEDULE_REM:
3310	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3311	pVM->em.s.enmState = EMSTATE_REM;
3312	break;
3313
3314	/*
3315	* Resume.
3316	*/
3317	case VINF_EM_RESUME:
3318	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3319	/* fall through and get scheduled. */
3320
3321	/*
3322	* Reschedule.
3323	*/
3324	case VINF_EM_RESCHEDULE:
3325	{
3326	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3327	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3328	pVM->em.s.enmState = enmState;
3329	break;
3330	}
3331
3332	/*
3333	* Halted.
3334	*/
3335	case VINF_EM_HALT:
3336	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3337	pVM->em.s.enmState = EMSTATE_HALTED;
3338	break;
3339
3340	/*
3341	* Suspend.
3342	*/
3343	case VINF_EM_SUSPEND:
3344	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3345	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3346	break;
3347
3348	/*
3349	* Reset.
3350	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3351	*/
3352	case VINF_EM_RESET:
3353	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3354	pVM->em.s.enmState = EMSTATE_REM;
3355	break;
3356
3357	/*
3358	* Power Off.
3359	*/
3360	case VINF_EM_OFF:
3361	pVM->em.s.enmState = EMSTATE_TERMINATING;
3362	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3363	TMVirtualPause(pVM);
3364	TMCpuTickPause(pVM);
3365	VMMR3Unlock(pVM);
3366	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3367	return rc;
3368
3369	/*
3370	* Terminate the VM.
3371	*/
3372	case VINF_EM_TERMINATE:
3373	pVM->em.s.enmState = EMSTATE_TERMINATING;
3374	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3375	TMVirtualPause(pVM);
3376	TMCpuTickPause(pVM);
3377	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3378	return rc;
3379
3380	/*
3381	* Guest debug events.
3382	*/
3383	case VINF_EM_DBG_STEPPED:
3384	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3385	case VINF_EM_DBG_STOP:
3386	case VINF_EM_DBG_BREAKPOINT:
3387	case VINF_EM_DBG_STEP:
3388	if (pVM->em.s.enmState == EMSTATE_RAW)
3389	{
3390	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3391	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3392	}
3393	else
3394	{
3395	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3396	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3397	}
3398	break;
3399
3400	/*
3401	* Hypervisor debug events.
3402	*/
3403	case VINF_EM_DBG_HYPER_STEPPED:
3404	case VINF_EM_DBG_HYPER_BREAKPOINT:
3405	case VINF_EM_DBG_HYPER_ASSERTION:
3406	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3407	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3408	break;
3409
3410	/*
3411	* Any error code showing up here other than the ones we
3412	* know and process above are considered to be FATAL.
3413	*
3414	* Unknown warnings and informational status codes are also
3415	* included in this.
3416	*/
3417	default:
3418	if (VBOX_SUCCESS(rc))
3419	{
3420	AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3421	rc = VERR_EM_INTERNAL_ERROR;
3422	}
3423	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3424	Log(("EMR3ExecuteVM returns %d\n", rc));
3425	break;
3426	}
3427
3428
3429	/*
3430	* Any waiters can now be woken up
3431	*/
3432	VMMR3Unlock(pVM);
3433	VMMR3Lock(pVM);
3434
3435	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3436	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3437
3438	/*
3439	* Act on the state.
3440	*/
3441	switch (pVM->em.s.enmState)
3442	{
3443	/*
3444	* Execute raw.
3445	*/
3446	case EMSTATE_RAW:
3447	rc = emR3RawExecute(pVM, &fFFDone);
3448	break;
3449
3450	/*
3451	* Execute hardware accelerated raw.
3452	*/
3453	case EMSTATE_HWACC:
3454	rc = emR3HwAccExecute(pVM, &fFFDone);
3455	break;
3456
3457	/*
3458	* Execute recompiled.
3459	*/
3460	case EMSTATE_REM:
3461	rc = emR3RemExecute(pVM, &fFFDone);
3462	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3463	break;
3464
3465	/*
3466	* hlt - execution halted until interrupt.
3467	*/
3468	case EMSTATE_HALTED:
3469	{
3470	STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3471	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3472	STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3473	break;
3474	}
3475
3476	/*
3477	* Suspended - return to VM.cpp.
3478	*/
3479	case EMSTATE_SUSPENDED:
3480	TMVirtualPause(pVM);
3481	TMCpuTickPause(pVM);
3482	VMMR3Unlock(pVM);
3483	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3484	return VINF_EM_SUSPEND;
3485
3486	/*
3487	* Debugging in the guest.
3488	*/
3489	case EMSTATE_DEBUG_GUEST_REM:
3490	case EMSTATE_DEBUG_GUEST_RAW:
3491	TMVirtualPause(pVM);
3492	TMCpuTickPause(pVM);
3493	rc = emR3Debug(pVM, rc);
3494	TMVirtualResume(pVM);
3495	TMCpuTickResume(pVM);
3496	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3497	break;
3498
3499	/*
3500	* Debugging in the hypervisor.
3501	*/
3502	case EMSTATE_DEBUG_HYPER:
3503	{
3504	TMVirtualPause(pVM);
3505	TMCpuTickPause(pVM);
3506	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3507
3508	rc = emR3Debug(pVM, rc);
3509	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3510	if (rc != VINF_SUCCESS)
3511	{
3512	/* switch to guru meditation mode */
3513	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3514	VMMR3FatalDump(pVM, rc);
3515	return rc;
3516	}
3517
3518	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3519	TMVirtualResume(pVM);
3520	TMCpuTickResume(pVM);
3521	break;
3522	}
3523
3524	/*
3525	* Guru meditation takes place in the debugger.
3526	*/
3527	case EMSTATE_GURU_MEDITATION:
3528	{
3529	TMVirtualPause(pVM);
3530	TMCpuTickPause(pVM);
3531	VMMR3FatalDump(pVM, rc);
3532	emR3Debug(pVM, rc);
3533	VMMR3Unlock(pVM);
3534	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3535	return rc;
3536	}
3537
3538	/*
3539	* The states we don't expect here.
3540	*/
3541	case EMSTATE_NONE:
3542	case EMSTATE_TERMINATING:
3543	default:
3544	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3545	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3546	TMVirtualPause(pVM);
3547	TMCpuTickPause(pVM);
3548	VMMR3Unlock(pVM);
3549	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3550	return VERR_EM_INTERNAL_ERROR;
3551	}
3552	} /* The Outer Main Loop */
3553	}
3554	else
3555	{
3556	/*
3557	* Fatal error.
3558	*/
3559	LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3560	TMVirtualPause(pVM);
3561	TMCpuTickPause(pVM);
3562	VMMR3FatalDump(pVM, rc);
3563	emR3Debug(pVM, rc);
3564	VMMR3Unlock(pVM);
3565	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3566	/** @todo change the VM state! */
3567	return rc;
3568	}
3569
3570	/* (won't ever get here). */
3571	AssertFailed();
3572	}
3573

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 13232

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