VirtualBox

Changeset 13232 in vbox


Ignore:
Timestamp:
Oct 13, 2008 8:03:48 PM (16 years ago)
Author:
vboxsync
Message:

#1865: changed some validation into pure assertions or assert-return. added some todos, update a comment or five and adjusted lots of whitespace.

Location:
trunk
Files:
9 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/pgm.h

    r13198 r13232  
    305305
    306306
    307 VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVM pVM);
    308 VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode);
    309 VMMDECL(RTHCPHYS) PGMGetEPTCR3(PVM pVM);
    310 VMMDECL(RTHCPHYS) PGMGetHyper32BitCR3(PVM pVM);
    311 VMMDECL(RTHCPHYS) PGMGetHyperPaeCR3(PVM pVM);
    312 VMMDECL(RTHCPHYS) PGMGetHyperAmd64CR3(PVM pVM);
    313 VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM);
    314 VMMDECL(RTHCPHYS) PGMGetInterGCCR3(PVM pVM);
    315 VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM);
    316 VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM);
    317 VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM);
    318 VMMDECL(int)    PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
    319 VMMDECL(int)    PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage);
    320 VMMDECL(int)    PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess);
    321 VMMDECL(int)    PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess);
    322 VMMDECL(int)    PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
    323 VMMDECL(int)    PGMMap(PVM pVM, RTGCUINTPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
    324 VMMDECL(int)    PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
    325 VMMDECL(int)    PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
    326 VMMDECL(int)    PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
    327 VMMDECL(int)    PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
    328 VMMDECL(int)    PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
    329 VMMDECL(int)    PGMShwSyncLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
    330 VMMDECL(int)    PGMShwGetLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
    331 VMMDECL(int)    PGMShwGetEPTPDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
    332 VMMDECL(int)    PGMShwSyncPAEPDPtr(PVM pVM, RTGCUINTPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
    333 VMMDECL(int)    PGMShwGetPAEPDPtr(PVM pVM, RTGCUINTPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
    334 VMMDECL(int)    PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
    335 VMMDECL(bool)   PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr);
    336 VMMDECL(int)    PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
    337 VMMDECL(int)    PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
    338 VMMDECL(X86PDPE) PGMGstGetPaePDPtr(PVM pVM, unsigned iPdPt);
    339 
    340 VMMDECL(int)    PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal);
    341 VMMDECL(int)    PGMUpdateCR3(PVM pVM, uint64_t cr3);
    342 VMMDECL(int)    PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
    343 VMMDECL(int)    PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer);
    344 VMMDECL(PGMMODE) PGMGetGuestMode(PVM pVM);
    345 VMMDECL(PGMMODE) PGMGetShadowMode(PVM pVM);
    346 VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
     307VMMDECL(RTHCPHYS)   PGMGetHyperCR3(PVM pVM);
     308VMMDECL(RTHCPHYS)   PGMGetNestedCR3(PVM pVM, PGMMODE enmShadowMode);
     309VMMDECL(RTHCPHYS)   PGMGetEPTCR3(PVM pVM);
     310VMMDECL(RTHCPHYS)   PGMGetHyper32BitCR3(PVM pVM);
     311VMMDECL(RTHCPHYS)   PGMGetHyperPaeCR3(PVM pVM);
     312VMMDECL(RTHCPHYS)   PGMGetHyperAmd64CR3(PVM pVM);
     313VMMDECL(RTHCPHYS)   PGMGetInterHCCR3(PVM pVM);
     314VMMDECL(RTHCPHYS)   PGMGetInterRCCR3(PVM pVM);
     315VMMDECL(RTHCPHYS)   PGMGetInter32BitCR3(PVM pVM);
     316VMMDECL(RTHCPHYS)   PGMGetInterPaeCR3(PVM pVM);
     317VMMDECL(RTHCPHYS)   PGMGetInterAmd64CR3(PVM pVM);
     318VMMDECL(int)        PGMTrap0eHandler(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
     319VMMDECL(int)        PGMPrefetchPage(PVM pVM, RTGCPTR GCPtrPage);
     320VMMDECL(int)        PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess);
     321VMMDECL(int)        PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess);
     322VMMDECL(int)        PGMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
     323VMMDECL(int)        PGMMap(PVM pVM, RTGCUINTPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
     324VMMDECL(int)        PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
     325VMMDECL(int)        PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
     326VMMDECL(int)        PGMShwGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
     327VMMDECL(int)        PGMShwSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
     328VMMDECL(int)        PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
     329VMMDECL(int)        PGMShwSyncLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
     330VMMDECL(int)        PGMShwGetLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
     331VMMDECL(int)        PGMShwGetEPTPDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PEPTPDPT *ppPdpt, PEPTPD *ppPD);
     332VMMDECL(int)        PGMShwSyncPAEPDPtr(PVM pVM, RTGCUINTPTR GCPtr, PX86PDPE pGstPdpe, PX86PDPAE *ppPD);
     333VMMDECL(int)        PGMShwGetPAEPDPtr(PVM pVM, RTGCUINTPTR GCPtr, PX86PDPT *ppPdpt, PX86PDPAE *ppPD);
     334VMMDECL(int)        PGMGstGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
     335VMMDECL(bool)       PGMGstIsPagePresent(PVM pVM, RTGCPTR GCPtr);
     336VMMDECL(int)        PGMGstSetPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
     337VMMDECL(int)        PGMGstModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
     338VMMDECL(X86PDPE)    PGMGstGetPaePDPtr(PVM pVM, unsigned iPdPt);
     339
     340VMMDECL(int)        PGMFlushTLB(PVM pVM, uint64_t cr3, bool fGlobal);
     341VMMDECL(int)        PGMUpdateCR3(PVM pVM, uint64_t cr3);
     342VMMDECL(int)        PGMSyncCR3(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
     343VMMDECL(int)        PGMChangeMode(PVM pVM, uint64_t cr0, uint64_t cr4, uint64_t efer);
     344VMMDECL(PGMMODE)    PGMGetGuestMode(PVM pVM);
     345VMMDECL(PGMMODE)    PGMGetShadowMode(PVM pVM);
     346VMMDECL(PGMMODE)    PGMGetHostMode(PVM pVM);
    347347VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
    348 VMMDECL(int)    PGMHandlerPhysicalRegisterEx(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
    349                                              R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
    350                                              R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
    351                                              RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
    352                                              R3PTRTYPE(const char *) pszDesc);
    353 VMMDECL(int)    PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
    354 VMMDECL(int)    PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
    355 VMMDECL(int)    PGMHandlerPhysicalChangeCallbacks(PVM pVM, RTGCPHYS GCPhys,
    356                                                   R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
    357                                                   R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
    358                                                   RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
    359                                                   R3PTRTYPE(const char *) pszDesc);
    360 VMMDECL(int)    PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
    361 VMMDECL(int)    PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
    362 VMMDECL(int)    PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
    363 VMMDECL(int)    PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
    364 VMMDECL(int)    PGMHandlerPhysicalPageReset(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
    365 VMMDECL(bool)   PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
    366 VMMDECL(bool)   PGMPhysIsA20Enabled(PVM pVM);
    367 VMMDECL(bool)   PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
    368 VMMDECL(bool)   PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
    369 VMMDECL(int)    PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
    370 VMMDECL(int)    PGMPhysGCPtr2GCPhys(PVM pVM, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
    371 VMMDECL(int)    PGMPhysGCPtr2HCPhys(PVM pVM, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
    372 VMMDECL(void)   PGMPhysInvalidatePageGCMapTLB(PVM pVM);
    373 VMMDECL(void)   PGMPhysInvalidatePageR0MapTLB(PVM pVM);
    374 VMMDECL(void)   PGMPhysInvalidatePageR3MapTLB(PVM pVM);
     348VMMDECL(int)        PGMHandlerPhysicalRegisterEx(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
     349                                                 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
     350                                                 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
     351                                                 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
     352                                                 R3PTRTYPE(const char *) pszDesc);
     353VMMDECL(int)        PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
     354VMMDECL(int)        PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
     355VMMDECL(int)        PGMHandlerPhysicalChangeCallbacks(PVM pVM, RTGCPHYS GCPhys,
     356                                                      R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
     357                                                      R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
     358                                                      RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
     359                                                      R3PTRTYPE(const char *) pszDesc);
     360VMMDECL(int)        PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
     361VMMDECL(int)        PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
     362VMMDECL(int)        PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
     363VMMDECL(int)        PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
     364VMMDECL(int)        PGMHandlerPhysicalPageReset(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
     365VMMDECL(bool)       PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
     366VMMDECL(bool)       PGMPhysIsA20Enabled(PVM pVM);
     367VMMDECL(bool)       PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
     368VMMDECL(bool)       PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
     369VMMDECL(int)        PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
     370VMMDECL(int)        PGMPhysGCPtr2GCPhys(PVM pVM, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
     371VMMDECL(int)        PGMPhysGCPtr2HCPhys(PVM pVM, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
     372VMMDECL(void)       PGMPhysInvalidatePageGCMapTLB(PVM pVM);
     373VMMDECL(void)       PGMPhysInvalidatePageR0MapTLB(PVM pVM);
     374VMMDECL(void)       PGMPhysInvalidatePageR3MapTLB(PVM pVM);
    375375
    376376/**
    … …  
    396396typedef PGMPAGEMAPLOCK *PPGMPAGEMAPLOCK;
    397397
    398 VMMDECL(int)    PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
    399 VMMDECL(int)    PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
    400 VMMDECL(int)    PGMPhysGCPtr2CCPtr(PVM pVM, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
    401 VMMDECL(int)    PGMPhysGCPtr2CCPtrReadOnly(PVM pVM, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
    402 VMMDECL(void)   PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
     398VMMDECL(int)        PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
     399VMMDECL(int)        PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
     400VMMDECL(int)        PGMPhysGCPtr2CCPtr(PVM pVM, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
     401VMMDECL(int)        PGMPhysGCPtr2CCPtrReadOnly(PVM pVM, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
     402VMMDECL(void)       PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
    403403
    404404/**
    … …  
    408408 * @param   pLock       The lock structure initialized by the mapping function.
    409409 */
    410 DECLINLINE(bool) PGMPhysIsPageMappingLockValid(PVM pVM, PPGMPAGEMAPLOCK pLock)
     410DECLINLINE(bool)    PGMPhysIsPageMappingLockValid(PVM pVM, PPGMPAGEMAPLOCK pLock)
    411411{
    412412    /** @todo -> complete/change this  */
    … …  
    418418}
    419419
    420 VMMDECL(int)    PGMPhysGCPhys2HCPtr(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange, PRTHCPTR pHCPtr);
    421 VMMDECL(RTHCPTR) PGMPhysGCPhys2HCPtrAssert(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange);
    422 VMMDECL(int)    PGMPhysGCPtr2HCPtr(PVM pVM, RTGCPTR GCPtr, PRTHCPTR pHCPtr);
    423 VMMDECL(int)    PGMPhysGCPtr2HCPtrByGstCR3(PVM pVM, RTGCPTR GCPtr, uint64_t cr3, unsigned fFlags, PRTHCPTR pHCPtr);
    424 VMMDECL(void)   PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
    425 VMMDECL(void)   PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
     420VMMDECL(int)        PGMPhysGCPhys2HCPtr(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange, PRTHCPTR pHCPtr);
     421VMMDECL(RTHCPTR)    PGMPhysGCPhys2HCPtrAssert(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange);
     422VMMDECL(int)        PGMPhysGCPtr2HCPtr(PVM pVM, RTGCPTR GCPtr, PRTHCPTR pHCPtr);
     423VMMDECL(int)        PGMPhysGCPtr2HCPtrByGstCR3(PVM pVM, RTGCPTR GCPtr, uint64_t cr3, unsigned fFlags, PRTHCPTR pHCPtr);
     424VMMDECL(void)       PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
     425VMMDECL(void)       PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
    426426#ifndef IN_GC /* Only ring 0 & 3. */
    427 VMMDECL(int)    PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
    428 VMMDECL(int)    PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
    429 VMMDECL(int)    PGMPhysSimpleReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
    430 VMMDECL(int)    PGMPhysSimpleWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
    431 VMMDECL(int)    PGMPhysReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
    432 VMMDECL(int)    PGMPhysWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
    433 VMMDECL(int)    PGMPhysSimpleDirtyWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
    434 VMMDECL(int)    PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage);
     427VMMDECL(int)        PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
     428VMMDECL(int)        PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
     429VMMDECL(int)        PGMPhysSimpleReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
     430VMMDECL(int)        PGMPhysSimpleWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
     431VMMDECL(int)        PGMPhysReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
     432VMMDECL(int)        PGMPhysWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
     433VMMDECL(int)        PGMPhysSimpleDirtyWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
     434VMMDECL(int)        PGMInvalidatePage(PVM pVM, RTGCPTR GCPtrPage);
    435435#endif /* !IN_GC */
    436 VMMDECL(int)    PGMPhysInterpretedRead(PVM pVM, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb);
     436VMMDECL(int)        PGMPhysInterpretedRead(PVM pVM, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb);
    437437#ifdef VBOX_STRICT
    438 VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
    439 VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
    440 VMMDECL(unsigned) PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4);
     438VMMDECL(unsigned)   PGMAssertHandlerAndFlagsInSync(PVM pVM);
     439VMMDECL(unsigned)   PGMAssertNoMappingConflicts(PVM pVM);
     440VMMDECL(unsigned)   PGMAssertCR3(PVM pVM, uint64_t cr3, uint64_t cr4);
    441441#endif /* VBOX_STRICT */
    442442
    443443#if defined(IN_GC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
    444 VMMDECL(int)    PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv);
    445 VMMDECL(int)    PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv);
    446 VMMDECL(int)    PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv);
    447 VMMDECL(int)    PGMDynMapHCPageOff(PVM pVM, RTHCPHYS HCPhys, void **ppv);
     444VMMDECL(int)        PGMDynMapGCPage(PVM pVM, RTGCPHYS GCPhys, void **ppv);
     445VMMDECL(int)        PGMDynMapGCPageOff(PVM pVM, RTGCPHYS GCPhys, void **ppv);
     446VMMDECL(int)        PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv);
     447VMMDECL(int)        PGMDynMapHCPageOff(PVM pVM, RTHCPHYS HCPhys, void **ppv);
    448448#endif
    449449
    … …  
    454454 * @{
    455455 */
    456 VMMRCDECL(int)  PGMGCInvalidatePage(PVM pVM, RTGCPTR GCPtrPage);
     456VMMRCDECL(int)      PGMGCInvalidatePage(PVM pVM, RTGCPTR GCPtrPage);
    457457/** @} */
    458458#endif /* IN_GC */
    … …  
    464464 * @{
    465465 */
    466 VMMR0DECL(int)  PGMR0PhysAllocateHandyPages(PVM pVM);
    467 VMMR0DECL(int)  PGMR0Trap0eHandlerNestedPaging(PVM pVM, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
     466VMMR0DECL(int)      PGMR0PhysAllocateHandyPages(PVM pVM);
     467VMMR0DECL(int)      PGMR0Trap0eHandlerNestedPaging(PVM pVM, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
    468468/** @} */
    469469#endif /* IN_RING0 */
    … …  
    476476 * @{
    477477 */
    478 VMMR3DECL(int)  PGMR3Init(PVM pVM);
    479 VMMR3DECL(int)  PGMR3InitDynMap(PVM pVM);
    480 VMMR3DECL(int)  PGMR3InitFinalize(PVM pVM);
    481 VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
    482 VMMR3DECL(void) PGMR3Reset(PVM pVM);
    483 VMMR3DECL(int)  PGMR3Term(PVM pVM);
    484 VMMR3DECL(int)  PGMR3LockCall(PVM pVM);
    485 VMMR3DECL(int)  PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable);
    486 VMMR3DECL(int)  PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode);
     478VMMR3DECL(int)      PGMR3Init(PVM pVM);
     479VMMR3DECL(int)      PGMR3InitDynMap(PVM pVM);
     480VMMR3DECL(int)      PGMR3InitFinalize(PVM pVM);
     481VMMR3DECL(void)     PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
     482VMMR3DECL(void)     PGMR3Reset(PVM pVM);
     483VMMR3DECL(int)      PGMR3Term(PVM pVM);
     484VMMR3DECL(int)      PGMR3LockCall(PVM pVM);
     485VMMR3DECL(int)      PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable);
     486VMMR3DECL(int)      PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode);
    487487
    488488#ifndef VBOX_WITH_NEW_PHYS_CODE
    489 VMMR3DECL(int)  PGM3PhysGrowRange(PVM pVM, PCRTGCPHYS GCPhys);
     489VMMR3DECL(int)      PGM3PhysGrowRange(PVM pVM, PCRTGCPHYS GCPhys);
    490490#endif /* !VBOX_WITH_NEW_PHYS_CODE */
    491 VMMR3DECL(int)  PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
    492 VMMR3DECL(int)  PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
    493                                       R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
    494                                       R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
    495                                       RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
    496                                       R3PTRTYPE(const char *) pszDesc);
    497 VMMR3DECL(int)  PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
    498 VMMR3DECL(int)  PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc);
    499 VMMR3DECL(int)  PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion);
    500 VMMR3DECL(int)  PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
    501 VMMR3DECL(int)  PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
    502 VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
    503 VMMR3DECL(int)  PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
     491VMMR3DECL(int)      PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
     492VMMR3DECL(int)      PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
     493                                          R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
     494                                          R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
     495                                          RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
     496                                          R3PTRTYPE(const char *) pszDesc);
     497VMMR3DECL(int)      PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
     498VMMR3DECL(int)      PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc);
     499VMMR3DECL(int)      PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion);
     500VMMR3DECL(int)      PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
     501VMMR3DECL(int)      PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
     502VMMR3DECL(bool)     PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
     503VMMR3DECL(int)      PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
    504504
    505505/** @group PGMR3PhysRegisterRom flags.
    … …  
    512512/** @} */
    513513
    514 VMMR3DECL(int)  PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
    515                                      const void *pvBinary, uint32_t fFlags, const char *pszDesc);
    516 VMMR3DECL(int)  PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
    517 VMMR3DECL(int)  PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
     514VMMR3DECL(int)      PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
     515                                         const void *pvBinary, uint32_t fFlags, const char *pszDesc);
     516VMMR3DECL(int)      PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
     517VMMR3DECL(int)      PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
    518518#ifndef VBOX_WITH_NEW_PHYS_CODE
    519 VMMR3DECL(int)  PGMR3PhysRegisterChunk(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
     519VMMR3DECL(int)      PGMR3PhysRegisterChunk(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
    520520#endif /* !VBOX_WITH_NEW_PHYS_CODE */
    521 VMMR3DECL(int)  PGMR3PhysSetFlags(PVM pVM, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, unsigned fMask);
    522 VMMDECL(void)   PGMR3PhysSetA20(PVM pVM, bool fEnable);
    523 VMMR3DECL(int)  PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, PFNPGMRELOCATE pfnRelocate, void *pvUser, const char *pszDesc);
    524 VMMR3DECL(int)  PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
    525 VMMR3DECL(int)  PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
    526 VMMR3DECL(int)  PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
    527 VMMR3DECL(int)  PGMR3MappingsUnfix(PVM pVM);
    528 VMMR3DECL(int)  PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
    529 VMMR3DECL(bool) PGMR3MapHasConflicts(PVM pVM, uint64_t cr3, bool fRawR0);
    530 VMMR3DECL(int)  PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
    531 VMMR3DECL(int)  PGMR3HandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
    532                                              PFNPGMR3PHYSHANDLER pfnHandlerR3, void *pvUserR3,
    533                                              const char *pszModR0, const char *pszHandlerR0, RTR0PTR pvUserR0,
    534                                              const char *pszModRC, const char *pszHandlerRC, RTRCPTR pvUserRC, const char *pszDesc);
    535 VMMDECL(int)    PGMHandlerVirtualRegisterEx(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
    536                                             R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3,
    537                                             R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3,
    538                                             RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC,
    539                                             R3PTRTYPE(const char *) pszDesc);
    540 VMMR3DECL(int)  PGMR3HandlerVirtualRegister(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
    541                                             PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
    542                                             PFNPGMR3VIRTHANDLER pfnHandlerR3,
    543                                             const char *pszHandlerRC, const char *pszModRC, const char *pszDesc);
    544 VMMDECL(int)    PGMHandlerVirtualChangeInvalidateCallback(PVM pVM, RTGCPTR GCPtr, R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3);
    545 VMMDECL(int)    PGMHandlerVirtualDeregister(PVM pVM, RTGCPTR GCPtr);
    546 VMMR3DECL(int)  PGMR3PoolGrow(PVM pVM);
     521VMMR3DECL(int)      PGMR3PhysSetFlags(PVM pVM, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, unsigned fMask);
     522VMMDECL(void)       PGMR3PhysSetA20(PVM pVM, bool fEnable);
     523VMMR3DECL(int)      PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, PFNPGMRELOCATE pfnRelocate, void *pvUser, const char *pszDesc);
     524VMMR3DECL(int)      PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
     525VMMR3DECL(int)      PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
     526VMMR3DECL(int)      PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
     527VMMR3DECL(int)      PGMR3MappingsUnfix(PVM pVM);
     528VMMR3DECL(int)      PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
     529VMMR3DECL(bool)     PGMR3MapHasConflicts(PVM pVM, uint64_t cr3, bool fRawR0);
     530VMMR3DECL(int)      PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
     531VMMR3DECL(int)      PGMR3HandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
     532                                                 PFNPGMR3PHYSHANDLER pfnHandlerR3, void *pvUserR3,
     533                                                 const char *pszModR0, const char *pszHandlerR0, RTR0PTR pvUserR0,
     534                                                 const char *pszModRC, const char *pszHandlerRC, RTRCPTR pvUserRC, const char *pszDesc);
     535VMMDECL(int)        PGMHandlerVirtualRegisterEx(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
     536                                                R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3,
     537                                                R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3,
     538                                                RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC,
     539                                                R3PTRTYPE(const char *) pszDesc);
     540VMMR3DECL(int)      PGMR3HandlerVirtualRegister(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
     541                                                PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
     542                                                PFNPGMR3VIRTHANDLER pfnHandlerR3,
     543                                                const char *pszHandlerRC, const char *pszModRC, const char *pszDesc);
     544VMMDECL(int)        PGMHandlerVirtualChangeInvalidateCallback(PVM pVM, RTGCPTR GCPtr, R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3);
     545VMMDECL(int)        PGMHandlerVirtualDeregister(PVM pVM, RTGCPTR GCPtr);
     546VMMR3DECL(int)      PGMR3PoolGrow(PVM pVM);
    547547#ifdef ___VBox_dbgf_h /** @todo fix this! */
    548 VMMR3DECL(int)  PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
     548VMMR3DECL(int)      PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
    549549#endif
    550 VMMR3DECL(int)  PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch);
    551 
    552 VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys);
     550VMMR3DECL(int)      PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch);
     551
     552VMMR3DECL(uint8_t)  PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys);
    553553VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys);
    554554VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys);
    555555VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys);
    556 VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value);
    557 VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value);
    558 VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value);
    559 VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value);
    560 VMMR3DECL(int)  PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
    561 VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
    562 VMMR3DECL(int)  PGMR3PhysAllocateHandyPages(PVM pVM);
    563 
    564 VMMR3DECL(int)  PGMR3CheckIntegrity(PVM pVM);
    565 
    566 VMMR3DECL(int)  PGMR3DbgR3Ptr2GCPhys(PVM pVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
    567 VMMR3DECL(int)  PGMR3DbgR3Ptr2HCPhys(PVM pVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
    568 VMMR3DECL(int)  PGMR3DbgHCPhys2GCPhys(PVM pVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
    569 VMMR3DECL(int)  PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
    570 VMMR3DECL(int)  PGMR3DbgScanVirtual(PVM pVM, RTGCUINTPTR GCPtr, RTGCUINTPTR cbRange, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
     556VMMR3DECL(void)     PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value);
     557VMMR3DECL(void)     PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value);
     558VMMR3DECL(void)     PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value);
     559VMMR3DECL(void)     PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value);
     560VMMR3DECL(int)      PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
     561VMMR3DECL(void)     PGMR3PhysChunkInvalidateTLB(PVM pVM);
     562VMMR3DECL(int)      PGMR3PhysAllocateHandyPages(PVM pVM);
     563
     564VMMR3DECL(int)      PGMR3CheckIntegrity(PVM pVM);
     565
     566VMMR3DECL(int)      PGMR3DbgR3Ptr2GCPhys(PVM pVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
     567VMMR3DECL(int)      PGMR3DbgR3Ptr2HCPhys(PVM pVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
     568VMMR3DECL(int)      PGMR3DbgHCPhys2GCPhys(PVM pVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
     569VMMR3DECL(int)      PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
     570VMMR3DECL(int)      PGMR3DbgScanVirtual(PVM pVM, RTGCUINTPTR GCPtr, RTGCUINTPTR cbRange, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
    571571/** @} */
    572572#endif /* IN_RING3 */

  • trunk/src/VBox/VMM/PGMBth.h

    r13067 r13232  
    5353
    5454    /* Ring 3 */
    55     pModeData->pfnR3BthRelocate          = PGM_BTH_NAME(Relocate);
    56     pModeData->pfnR3BthSyncCR3           = PGM_BTH_NAME(SyncCR3);
    57     pModeData->pfnR3BthInvalidatePage    = PGM_BTH_NAME(InvalidatePage);
    58     pModeData->pfnR3BthSyncPage          = PGM_BTH_NAME(SyncPage);
    59     pModeData->pfnR3BthPrefetchPage      = PGM_BTH_NAME(PrefetchPage);
     55    pModeData->pfnR3BthRelocate             = PGM_BTH_NAME(Relocate);
     56    pModeData->pfnR3BthSyncCR3              = PGM_BTH_NAME(SyncCR3);
     57    pModeData->pfnR3BthInvalidatePage       = PGM_BTH_NAME(InvalidatePage);
     58    pModeData->pfnR3BthSyncPage             = PGM_BTH_NAME(SyncPage);
     59    pModeData->pfnR3BthPrefetchPage         = PGM_BTH_NAME(PrefetchPage);
    6060    pModeData->pfnR3BthVerifyAccessSyncPage = PGM_BTH_NAME(VerifyAccessSyncPage);
    6161#ifdef VBOX_STRICT
    62     pModeData->pfnR3BthAssertCR3         = PGM_BTH_NAME(AssertCR3);
     62    pModeData->pfnR3BthAssertCR3            = PGM_BTH_NAME(AssertCR3);
    6363#endif
    6464
    … …  
    6969#if PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT /* No AMD64 for traditional virtualization, only VT-x and AMD-V. */
    7070        /* GC */
    71         rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(Trap0eHandler),  &pModeData->pfnRCBthTrap0eHandler);
     71        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_BTH_NAME_RC_STR(Trap0eHandler),       &pModeData->pfnRCBthTrap0eHandler);
    7272        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_RC_STR(Trap0eHandler),  rc), rc);
    73         rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(InvalidatePage), &pModeData->pfnRCBthInvalidatePage);
     73        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_BTH_NAME_RC_STR(InvalidatePage),      &pModeData->pfnRCBthInvalidatePage);
    7474        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_RC_STR(InvalidatePage), rc), rc);
    75         rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(SyncCR3), &pModeData->pfnRCBthSyncCR3);
     75        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_BTH_NAME_RC_STR(SyncCR3),            &pModeData->pfnRCBthSyncCR3);
    7676        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_RC_STR(SyncPage), rc), rc);
    77         rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(SyncPage), &pModeData->pfnRCBthSyncPage);
     77        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_BTH_NAME_RC_STR(SyncPage),            &pModeData->pfnRCBthSyncPage);
    7878        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_RC_STR(SyncPage), rc), rc);
    79         rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(PrefetchPage), &pModeData->pfnRCBthPrefetchPage);
     79        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_BTH_NAME_RC_STR(PrefetchPage),        &pModeData->pfnRCBthPrefetchPage);
    8080        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_RC_STR(PrefetchPage), rc), rc);
    81         rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(VerifyAccessSyncPage), &pModeData->pfnRCBthVerifyAccessSyncPage);
     81        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_BTH_NAME_RC_STR(VerifyAccessSyncPage),&pModeData->pfnRCBthVerifyAccessSyncPage);
    8282        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_RC_STR(VerifyAccessSyncPage), rc), rc);
    8383# ifdef VBOX_STRICT
    84         rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_BTH_NAME_RC_STR(AssertCR3), &pModeData->pfnRCBthAssertCR3);
     84        rc = PDMR3LdrGetSymbolRC(pVM, NULL,       PGM_BTH_NAME_RC_STR(AssertCR3),          &pModeData->pfnRCBthAssertCR3);
    8585        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_RC_STR(AssertCR3), rc), rc);
    8686# endif
    … …  
    8888
    8989        /* Ring 0 */
    90         rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(Trap0eHandler),  &pModeData->pfnR0BthTrap0eHandler);
     90        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_BTH_NAME_R0_STR(Trap0eHandler),       &pModeData->pfnR0BthTrap0eHandler);
    9191        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_R0_STR(Trap0eHandler),  rc), rc);
    92         rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(InvalidatePage), &pModeData->pfnR0BthInvalidatePage);
     92        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_BTH_NAME_R0_STR(InvalidatePage),      &pModeData->pfnR0BthInvalidatePage);
    9393        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_R0_STR(InvalidatePage), rc), rc);
    94         rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(SyncCR3), &pModeData->pfnR0BthSyncCR3);
     94        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_BTH_NAME_R0_STR(SyncCR3),            &pModeData->pfnR0BthSyncCR3);
    9595        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_R0_STR(SyncCR3), rc), rc);
    96         rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(SyncPage), &pModeData->pfnR0BthSyncPage);
     96        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_BTH_NAME_R0_STR(SyncPage),            &pModeData->pfnR0BthSyncPage);
    9797        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_R0_STR(SyncPage), rc), rc);
    98         rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(PrefetchPage), &pModeData->pfnR0BthPrefetchPage);
     98        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_BTH_NAME_R0_STR(PrefetchPage),        &pModeData->pfnR0BthPrefetchPage);
    9999        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_R0_STR(PrefetchPage), rc), rc);
    100         rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(VerifyAccessSyncPage), &pModeData->pfnR0BthVerifyAccessSyncPage);
     100        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_BTH_NAME_R0_STR(VerifyAccessSyncPage),&pModeData->pfnR0BthVerifyAccessSyncPage);
    101101        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_R0_STR(VerifyAccessSyncPage), rc), rc);
    102102#ifdef VBOX_STRICT
    103         rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_BTH_NAME_R0_STR(AssertCR3), &pModeData->pfnR0BthAssertCR3);
     103        rc = PDMR3LdrGetSymbolR0(pVM, NULL,       PGM_BTH_NAME_R0_STR(AssertCR3),          &pModeData->pfnR0BthAssertCR3);
    104104        AssertMsgRCReturn(rc, ("%s -> rc=%Vrc\n", PGM_BTH_NAME_R0_STR(AssertCR3), rc), rc);
    105105#endif

  • trunk/src/VBox/VMM/SELM.cpp

    r13144 r13232  
    390390
    391391    /* trap 08 */
    392     pVM->selm.s.TssTrap08.cr3    = PGMGetInterGCCR3(pVM);                   /* this should give use better survival chances. */
     392    pVM->selm.s.TssTrap08.cr3    = PGMGetInterRCCR3(pVM);                   /* this should give use better survival chances. */
    393393    pVM->selm.s.TssTrap08.ss0    = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
    394394    pVM->selm.s.TssTrap08.ss     = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
    … …  
    474474{
    475475    pVM->selm.s.Tss.cr3       = PGMGetHyperCR3(pVM);
    476     pVM->selm.s.TssTrap08.cr3 = PGMGetInterGCCR3(pVM);
     476    pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM);
    477477}
    478478

  • trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

    r13198 r13232  
    403403            STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eSVReserved);
    404404    }
    405 #endif
     405#endif /* VBOX_WITH_STATISTICS */
    406406
    407407    /*
    … …  
    476476 * @param   cbSize      Access size
    477477 * @param   fAccess     Access type (r/w, user/supervisor (X86_PTE_*))
     478 * @remarks Current not in use.
    478479 */
    479480VMMDECL(int) PGMIsValidAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
    … …  
    531532VMMDECL(int) PGMVerifyAccess(PVM pVM, RTGCUINTPTR Addr, uint32_t cbSize, uint32_t fAccess)
    532533{
    533     /*
    534      * Validate input.
    535      */
    536     if (fAccess & ~(X86_PTE_US | X86_PTE_RW))
    537     {
    538         AssertMsgFailed(("PGMVerifyAccess: invalid access type %08x\n", fAccess));
    539         return VERR_INVALID_PARAMETER;
    540     }
    541 
     534    AssertMsg(!(fAccess & ~(X86_PTE_US | X86_PTE_RW)), ("PGMVerifyAccess: invalid access type %08x\n", fAccess));
     535
     536    /*
     537     * Get going.
     538     */
    542539    uint64_t fPageGst;
    543540    int rc = PGMGstGetPage(pVM, (RTGCPTR)Addr, &fPageGst, NULL);
    … …  
    567564    {
    568565        /*
    569         * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
    570         */
     566         * Next step is to verify if we protected this page for dirty bit tracking or for CSAM scanning
     567         */
    571568        rc = PGMShwGetPage(pVM, (RTGCPTR)Addr, NULL, NULL);
    572569        if (    rc == VERR_PAGE_NOT_PRESENT
    … …  
    678675     * Inform CSAM about the flush
    679676     */
    680     /** @note this is to check if monitored pages have been changed; when we implement callbacks for virtual handlers, this is no longer required. */
     677    /* note: This is to check if monitored pages have been changed; when we implement callbacks for virtual handlers, this is no longer required. */
    681678    CSAMR3FlushPage(pVM, GCPtrPage);
    682679# endif
    … …  
    753750 * @remark  You must use PGMMapModifyPage() for pages in a mapping.
    754751 */
    755 VMMDECL(int)  PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
    756 {
    757     /*
    758      * Validate input.
    759      */
    760     if (fFlags & X86_PTE_PAE_PG_MASK)
    761     {
    762         AssertMsgFailed(("fFlags=%#llx\n", fFlags));
    763         return VERR_INVALID_PARAMETER;
    764     }
    765     if (!cb)
    766     {
    767         AssertFailed();
    768         return VERR_INVALID_PARAMETER;
    769     }
     752VMMDECL(int) PGMShwModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
     753{
     754    AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
     755    Assert(cb);
    770756
    771757    /*
    … …  
    870856}
    871857
    872 
    873858#ifndef IN_GC
     859
    874860/**
    875861 * Syncs the SHADOW page directory pointer for the specified address. Allocates
    … …  
    909895            PX86PML4E pPml4eGst = &pPGM->pGstPaePML4HC->a[iPml4e];
    910896
    911             rc = pgmPoolAlloc(pVM, pPml4eGst->u & X86_PML4E_PG_MASK, PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e, &pShwPage);
     897            rc = pgmPoolAlloc(pVM, pPml4eGst->u & X86_PML4E_PG_MASK,
     898                              PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e, &pShwPage);
    912899        }
    913900        else
    914             rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(63) /* hack: make the address unique */, PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4e, &pShwPage);
     901            rc = pgmPoolAlloc(pVM, GCPtr + RT_BIT_64(63) /* hack: make the address unique */,
     902                              PGMPOOLKIND_64BIT_PDPT_FOR_PHYS, PGMPOOL_IDX_NESTED_ROOT, iPml4e, &pShwPage);
    915903
    916904        if (rc == VERR_PGM_POOL_FLUSHED)
    … …  
    978966}
    979967
     968
    980969/**
    981970 * Gets the SHADOW page directory pointer for the specified address.
    … …  
    10181007    return VINF_SUCCESS;
    10191008}
     1009
    10201010
    10211011/**
    … …  
    11061096}
    11071097
    1108 #endif
     1098#endif /* IN_GC */
    11091099
    11101100/**
    … …  
    11791169     * Validate input.
    11801170     */
    1181     if (fFlags & X86_PTE_PAE_PG_MASK)
    1182     {
    1183         AssertMsgFailed(("fFlags=%#llx\n", fFlags));
    1184         STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
    1185         return VERR_INVALID_PARAMETER;
    1186     }
    1187 
    1188     if (!cb)
    1189     {
    1190         AssertFailed();
    1191         STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,GstModifyPage), a);
    1192         return VERR_INVALID_PARAMETER;
    1193     }
     1171    AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#llx\n", fFlags));
     1172    Assert(cb);
    11941173
    11951174    LogFlow(("PGMGstModifyPage %VGv %d bytes fFlags=%08llx fMask=%08llx\n", GCPtr, cb, fFlags, fMask));
    … …  
    12111190}
    12121191
     1192
    12131193/**
    12141194 * Gets the specified page directory pointer table entry.
    … …  
    12581238}
    12591239
     1240
    12601241/**
    12611242 * Gets the current CR3 register value for the nested memory context.
    … …  
    12841265}
    12851266
     1267
    12861268/**
    12871269 * Gets the current CR3 register value for the EPT paging memory context.
    … …  
    12931275    return pVM->pgm.s.HCPhysNestedRoot;
    12941276}
     1277
    12951278
    12961279/**
    … …  
    13601343
    13611344/**
    1362  * Gets the current CR3 register value for the GC intermediate memory context.
     1345 * Gets the current CR3 register value for the RC intermediate memory context.
    13631346 * @returns CR3 value.
    13641347 * @param   pVM         The VM handle.
    13651348 */
    1366 VMMDECL(RTHCPHYS) PGMGetInterGCCR3(PVM pVM)
     1349VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM)
    13671350{
    13681351    switch (pVM->pgm.s.enmShadowMode)
    … …  
    14941477}
    14951478
    1496 /**
    1497  * Performs and schedules necessary updates following a CR3 load or reload,
    1498  * without actually flushing the TLB as with PGMFlushTLB.
     1479
     1480/**
     1481 * Performs and schedules necessary updates following a CR3 load or reload when
     1482 * using nested or extended paging.
     1483 *
     1484 * This API is an alterantive to PDMFlushTLB that avoids actually flushing the
     1485 * TLB and triggering a SyncCR3.
    14991486 *
    15001487 * This will normally involve mapping the guest PD or nPDPT
    … …  
    15351522    return rc;
    15361523}
     1524
    15371525
    15381526/**
    … …  
    19341922
    19351923#else  /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
     1924    /** @todo @bugref{3202}: Implement ring-0 mapping cache similar to the one in
     1925     *        RC. To begin with, a simple but expensive one based on
     1926     *        RTR0MemObjEnterPhys can be used to get things started. Later a
     1927     *        global cache with mappings per CPU (to avoid shootdown) should be
     1928     *        employed. */
    19361929    AssertFailed();
    19371930    return VERR_NOT_IMPLEMENTED;
    … …  
    19611954
    19621955#endif /* IN_GC || VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
    1963 
    19641956#ifdef VBOX_STRICT
    19651957

  • trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

    r13203 r13232  
    9999     * Get PDs.
    100100     */
    101     int       rc;
     101    int             rc;
    102102#  if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
    103103#   if PGM_GST_TYPE == PGM_TYPE_32BIT
    … …  
    677677                        }
    678678#    ifdef CSAM_DETECT_NEW_CODE_PAGES
    679                         else
    680                         if (    uErr == X86_TRAP_PF_RW
    681                             &&  pRegFrame->ecx >= 0x100         /* early check for movswd count */
    682                             &&  pRegFrame->ecx < 0x10000
    683                            )
     679                        else if (    uErr == X86_TRAP_PF_RW
     680                                 &&  pRegFrame->ecx >= 0x100         /* early check for movswd count */
     681                                 &&  pRegFrame->ecx < 0x10000)
    684682                        {
    685683                            /* In case of a write to a non-present supervisor shadow page, we'll take special precautions
    … …  
    885883    && PGM_SHW_TYPE != PGM_TYPE_NESTED \
    886884    && PGM_SHW_TYPE != PGM_TYPE_EPT
    887     int rc;
     885    int             rc;
    888886
    889887    LogFlow(("InvalidatePage %VGv\n", GCPtrPage));
    … …  
    19651963
    19661964
    1967 
    19681965#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
    1969 
    19701966/**
    19711967 * Investigate page fault and handle write protection page faults caused by
    … …  
    20192015    {
    20202016        uPageFaultLevel = 0;
    2021         goto UpperLevelPageFault;
     2017        goto l_UpperLevelPageFault;
    20222018    }
    20232019    Assert(pPdpeSrc);
    … …  
    20402036    {
    20412037        uPageFaultLevel = 1;
    2042         goto UpperLevelPageFault;
     2038        goto l_UpperLevelPageFault;
    20432039    }
    20442040# endif
    … …  
    20562052    {
    20572053        uPageFaultLevel = 2;
    2058         goto UpperLevelPageFault;
     2054        goto l_UpperLevelPageFault;
    20592055    }
    20602056
    … …  
    22332229
    22342230
    2235 UpperLevelPageFault:
    2236     /* Pagefault detected while checking the PML4E, PDPE or PDE.
     2231l_UpperLevelPageFault:
     2232    /*
     2233     * Pagefault detected while checking the PML4E, PDPE or PDE.
    22372234     * Single exit handler to get rid of duplicate code paths.
    22382235     */
    … …  
    22742271    return VINF_EM_RAW_GUEST_TRAP;
    22752272}
    2276 
    22772273#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
    22782274
    … …  
    23032299    && PGM_SHW_TYPE != PGM_TYPE_EPT
    23042300
    2305     int rc = VINF_SUCCESS;
     2301    int             rc = VINF_SUCCESS;
    23062302
    23072303    /*
    … …  
    27032699    PX86PDPAE       pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
    27042700# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
    2705     const unsigned  iPdpte   = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
    2706     const unsigned  iPDDst   = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
     2701    const unsigned  iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
     2702    const unsigned  iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
    27072703    PX86PDPAE       pPDDst;
    27082704    PX86PDPT        pPdptDst;
    … …  
    27122708
    27132709    /* Fetch the pgm pool shadow descriptor. */
    2714     PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
     2710    PPGMPOOLPAGE    pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
    27152711    Assert(pShwPde);
    27162712# elif PGM_SHW_TYPE == PGM_TYPE_EPT
    … …  
    28532849#  if PGM_GST_TYPE == PGM_TYPE_PROT
    28542850        /* AMD-V nested paging */
    2855         X86PML4E     Pml4eSrc;
    2856         X86PDPE      PdpeSrc;
    2857         PX86PML4E    pPml4eSrc = &Pml4eSrc;
     2851        X86PML4E        Pml4eSrc;
     2852        X86PDPE         PdpeSrc;
     2853        PX86PML4E       pPml4eSrc = &Pml4eSrc;
    28582854
    28592855        /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
    … …  
    28892885    }
    28902886    return rc;
     2887
    28912888#elif PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
    28922889    return VINF_SUCCESS; /* ignore */
    … …  
    29242921    }
    29252922# endif
     2923
    29262924    /*
    29272925     * Get guest PD and index.
    29282926     */
    2929 
    29302927# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
    29312928#  if PGM_GST_TYPE == PGM_TYPE_32BIT
    … …  
    29562953    const unsigned  iPDSrc = 0;
    29572954# endif
    2958     int         rc = VINF_SUCCESS;
     2955    int             rc = VINF_SUCCESS;
    29592956
    29602957    /*
    … …  
    29622959     */
    29632960# if PGM_SHW_TYPE == PGM_TYPE_32BIT
    2964     PX86PDE     pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
     2961    PX86PDE         pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
    29652962# elif PGM_SHW_TYPE == PGM_TYPE_PAE
    2966     PX86PDEPAE  pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
     2963    PX86PDEPAE      pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
    29672964# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
    29682965    const unsigned  iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
    … …  
    29722969#  if PGM_GST_TYPE == PGM_TYPE_PROT
    29732970    /* AMD-V nested paging */
    2974     X86PML4E     Pml4eSrc;
    2975     X86PDPE      PdpeSrc;
    2976     PX86PML4E    pPml4eSrc = &Pml4eSrc;
     2971    X86PML4E        Pml4eSrc;
     2972    X86PDPE         PdpeSrc;
     2973    PX86PML4E       pPml4eSrc = &Pml4eSrc;
    29772974
    29782975    /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
    … …  
    33693366                    Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
    33703367#  endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) || PGM_WITHOUT_MAPPINGS */
     3368
    33713369                    /*
    3372                     * Sync page directory entry.
    3373                     *
    3374                     * The current approach is to allocated the page table but to set
    3375                     * the entry to not-present and postpone the page table synching till
    3376                     * it's actually used.
    3377                     */
     3370                     * Sync page directory entry.
     3371                     *
     3372                     * The current approach is to allocated the page table but to set
     3373                     * the entry to not-present and postpone the page table synching till
     3374                     * it's actually used.
     3375                     */
    33783376#  if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
    33793377                    for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
    … …  
    34753473                {
    34763474                    /*
    3477                     * Check if there is any page directory to mark not present here.
    3478                     */
     3475                     * Check if there is any page directory to mark not present here.
     3476                     */
    34793477#  if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
    34803478                    for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
    … …  
    36253623
    36263624#if PGM_GST_TYPE == PGM_TYPE_PAE
    3627     /* @todo currently broken; crashes below somewhere */
     3625    /** @todo currently broken; crashes below somewhere */
    36283626    AssertFailed();
    36293627#endif
    … …  
    36343632
    36353633#  if PGM_GST_TYPE == PGM_TYPE_AMD64
    3636     bool        fBigPagesSupported = true;
     3634    bool            fBigPagesSupported = true;
    36373635#  else
    3638     bool        fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
    3639 #  endif
    3640     PPGM        pPGM = &pVM->pgm.s;
    3641     RTGCPHYS    GCPhysGst;              /* page address derived from the guest page tables. */
    3642     RTHCPHYS    HCPhysShw;              /* page address derived from the shadow page tables. */
     3636    bool            fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
     3637#  endif
     3638    PPGM            pPGM = &pVM->pgm.s;
     3639    RTGCPHYS        GCPhysGst;              /* page address derived from the guest page tables. */
     3640    RTHCPHYS        HCPhysShw;              /* page address derived from the shadow page tables. */
    36433641# ifndef IN_RING0
    3644     RTHCPHYS    HCPhys;                 /* general usage. */
    3645 # endif
    3646     int         rc;
     3642    RTHCPHYS        HCPhys;                 /* general usage. */
     3643# endif
     3644    int             rc;
    36473645
    36483646    /*
    … …  
    36753673# if PGM_SHW_TYPE == PGM_TYPE_32BIT
    36763674    unsigned        cPDEs       = X86_PG_ENTRIES;
    3677     unsigned        ulIncrement = X86_PG_ENTRIES * PAGE_SIZE;
     3675    unsigned        cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
    36783676# elif PGM_SHW_TYPE == PGM_TYPE_PAE
    36793677#  if PGM_GST_TYPE == PGM_TYPE_32BIT
    … …  
    36823680    unsigned        cPDEs       = X86_PG_PAE_ENTRIES;
    36833681#  endif
    3684     unsigned        ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
     3682    unsigned        cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
    36853683# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
    36863684    unsigned        cPDEs       = X86_PG_PAE_ENTRIES;
    3687     unsigned        ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
     3685    unsigned        cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
    36883686# endif
    36893687    if (cb != ~(RTGCUINTPTR)0)
    … …  
    36933691
    36943692# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
    3695     PPGMPOOL    pPool         = pVM->pgm.s.CTX_SUFF(pPool);
     3693    PPGMPOOL        pPool       = pVM->pgm.s.CTX_SUFF(pPool);
    36963694# endif
    36973695
    … …  
    37013699    for (; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
    37023700    {
    3703         PPGMPOOLPAGE pShwPdpt = NULL;
    3704         PX86PML4E    pPml4eSrc, pPml4eDst;
    3705         RTGCPHYS     GCPhysPdptSrc;
     3701        PPGMPOOLPAGE    pShwPdpt = NULL;
     3702        PX86PML4E       pPml4eSrc;
     3703        PX86PML4E       pPml4eDst;
     3704        RTGCPHYS        GCPhysPdptSrc;
    37063705
    37073706        pPml4eSrc     = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
    … …  
    37113710        if (!pPml4eDst->n.u1Present)
    37123711        {
    3713             GCPtr += UINT64_C(_2M * 512 * 512);
     3712            GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
    37143713            continue;
    37153714        }
    … …  
    37253724        {
    37263725            AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
    3727             GCPtr += UINT64_C(_2M * 512 * 512);
     3726            GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
    37283727            cErrors++;
    37293728            continue;
    … …  
    37333732        {
    37343733            AssertMsgFailed(("Physical address doesn't match! iPml4e %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
    3735             GCPtr += UINT64_C(_2M * 512 * 512);
     3734            GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
    37363735            cErrors++;
    37373736            continue;
    … …  
    37433742        {
    37443743            AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
    3745             GCPtr += UINT64_C(_2M * 512 * 512);
     3744            GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
    37463745            cErrors++;
    37473746            continue;
    … …  
    38333832# endif
    38343833# if PGM_GST_TYPE == PGM_TYPE_32BIT
    3835             const GSTPD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
     3834            const GSTPD    *pPDSrc = CTXSUFF(pPGM->pGuestPD);
    38363835#  if PGM_SHW_TYPE == PGM_TYPE_32BIT
    3837             const X86PD    *pPDDst = pPGM->CTXMID(p,32BitPD);
     3836            PCX86PD         pPDDst = pPGM->CTXMID(p,32BitPD);
    38383837#  else
    3839             const PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];      /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
     3838            PCX86PDPAE      pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
    38403839#  endif
    38413840# endif
    … …  
    38483847            for (;
    38493848                iPDDst < cPDEs;
    3850                 iPDDst++, GCPtr += ulIncrement)
     3849                iPDDst++, GCPtr += cIncrement)
    38513850            {
    38523851                const SHWPDE PdeDst = pPDDst->a[iPDDst];

  • trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

    r13087 r13232  
    6060# define PGSTPDE                    PSHWPDE
    6161# define GST_PTE_PG_MASK            SHW_PTE_PG_MASK
     62
    6263#elif PGM_GST_TYPE == PGM_TYPE_32BIT
    6364# define GSTPT                      X86PT
    … …  
    8182# define GST_PT_MASK                X86_PT_MASK
    8283# define GST_CR3_PAGE_MASK          X86_CR3_PAGE_MASK
     84
    8385#elif   PGM_GST_TYPE == PGM_TYPE_PAE \
    8486     || PGM_GST_TYPE == PGM_TYPE_AMD64
    … …  
    503505
    504506                Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
    505 try_again:
     507l_try_again:
    506508                rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.pHCShwAmd64CR3);
    507509                if (rc == VERR_PGM_POOL_FLUSHED)
    … …  
    511513                    rc = pgmPoolSyncCR3(pVM);
    512514                    AssertRC(rc);
    513                     goto try_again;
     515                    goto l_try_again;
    514516                }
    515517                pVM->pgm.s.pHCPaePML4    = (PX86PML4)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.pHCShwAmd64CR3);
    … …  
    649651        pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
    650652    }
     653
    651654    /*
    652655     * Do the 4 PDs.
    … …  
    783786#endif
    784787
    785     unsigned    offPage = GCPtr & PAGE_OFFSET_MASK;
    786     unsigned    iPage = 0;
     788    unsigned        offPage = GCPtr & PAGE_OFFSET_MASK;
     789    unsigned        iPage = 0;
    787790    while (iPage < pCur->cPages)
    788791    {
    … …  
    10431046
    10441047#endif /* PGM_TYPE_32BIT && !IN_RING3 */
    1045 
    1046 
    10471048#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
    10481049

  • trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp

    r13085 r13232  
    9292     * Validate input.
    9393     */
    94     if (GCPhys >= GCPhysLast)
    95     {
    96         AssertMsgFailed(("GCPhys >= GCPhysLast (%#x >= %#x)\n", GCPhys, GCPhysLast));
    97         return VERR_INVALID_PARAMETER;
    98     }
     94    AssertMsgReturn(GCPhys < GCPhysLast, ("GCPhys >= GCPhysLast (%#x >= %#x)\n", GCPhys, GCPhysLast), VERR_INVALID_PARAMETER);
    9995    switch (enmType)
    10096    {
    … …  
    107103            return VERR_INVALID_PARAMETER;
    108104    }
    109     if (    (RTRCUINTPTR)pvUserRC >= 0x10000
    110         &&  MMHyperR3ToRC(pVM, MMHyperRCToR3(pVM, pvUserRC)) != pvUserRC)
    111     {
    112         AssertMsgFailed(("Not RC pointer! pvUserRC=%RRv\n", pvUserRC));
    113         return VERR_INVALID_PARAMETER;
    114     }
     105    AssertMsgReturn(    (RTRCUINTPTR)pvUserRC < 0x10000
     106                    ||  MMHyperR3ToRC(pVM, MMHyperRCToR3(pVM, pvUserRC)) == pvUserRC,
     107                    ("Not RC pointer! pvUserRC=%RRv\n", pvUserRC),
     108                    VERR_INVALID_PARAMETER);
    115109    AssertReturn(pfnHandlerR3 || pfnHandlerR0 || pfnHandlerRC, VERR_INVALID_PARAMETER);
    116110
    … …  
    659653    pgmLock(pVM);
    660654    PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
    661     if (pCur)
    662     {
    663         if (GCPhysSplit <= pCur->Core.KeyLast)
     655    if (RT_LIKELY(pCur))
     656    {
     657        if (RT_LIKELY(GCPhysSplit <= pCur->Core.KeyLast))
    664658        {
    665659            /*
    … …  
    673667            pCur->cPages        = (pCur->Core.KeyLast - (pCur->Core.Key & X86_PTE_PAE_PG_MASK) + PAGE_SIZE) >> PAGE_SHIFT;
    674668
    675             if (RTAvlroGCPhysInsert(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, &pNew->Core))
     669            if (RT_LIKELY(RTAvlroGCPhysInsert(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, &pNew->Core)))
    676670            {
    677671                LogFlow(("PGMHandlerPhysicalSplit: %VGp-%VGp and %VGp-%VGp\n",
    … …  
    716710    pgmLock(pVM);
    717711    PPGMPHYSHANDLER pCur1 = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys1);
    718     if (pCur1)
     712    if (RT_LIKELY(pCur1))
    719713    {
    720714        PPGMPHYSHANDLER pCur2 = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys2);
    721         if (pCur2)
     715        if (RT_LIKELY(pCur2))
    722716        {
    723717            /*
    724718             * Make sure that they are adjacent, and that they've got the same callbacks.
    725719             */
    726             if (pCur1->Core.KeyLast + 1 == pCur2->Core.Key)
     720            if (RT_LIKELY(pCur1->Core.KeyLast + 1 == pCur2->Core.Key))
    727721            {
    728                 if (    pCur1->pfnHandlerRC == pCur2->pfnHandlerRC
    729                     &&  pCur1->pfnHandlerR0 == pCur2->pfnHandlerR0
    730                     &&  pCur1->pfnHandlerR3 == pCur2->pfnHandlerR3)
     722                if (RT_LIKELY(    pCur1->pfnHandlerRC == pCur2->pfnHandlerRC
     723                              &&  pCur1->pfnHandlerR0 == pCur2->pfnHandlerR0
     724                              &&  pCur1->pfnHandlerR3 == pCur2->pfnHandlerR3))
    731725                {
    732726                    PPGMPHYSHANDLER pCur3 = (PPGMPHYSHANDLER)RTAvlroGCPhysRemove(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys2);
    733                     if (pCur3 == pCur2)
     727                    if (RT_LIKELY(pCur3 == pCur2))
    734728                    {
    735729                        pCur1->Core.KeyLast  = pCur2->Core.KeyLast;
    … …  
    794788    int rc;
    795789    PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
    796     if (pCur)
     790    if (RT_LIKELY(pCur))
    797791    {
    798792        /*
    … …  
    871865     */
    872866    PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
    873     if (pCur)
    874     {
    875         if (    GCPhysPage >= pCur->Core.Key
    876             &&  GCPhysPage <= pCur->Core.KeyLast)
     867    if (RT_LIKELY(pCur))
     868    {
     869        if (RT_LIKELY(    GCPhysPage >= pCur->Core.Key
     870                      &&  GCPhysPage <= pCur->Core.KeyLast))
    877871        {
    878872            Assert(!(pCur->Core.Key & PAGE_OFFSET_MASK));
    … …  
    925919     */
    926920    PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhys);
    927     if (pCur)
    928     {
    929         if (    GCPhysPage >= pCur->Core.Key
    930             &&  GCPhysPage <= pCur->Core.KeyLast)
     921    if (RT_LIKELY(pCur))
     922    {
     923        if (RT_LIKELY(    GCPhysPage >= pCur->Core.Key
     924                      &&  GCPhysPage <= pCur->Core.KeyLast))
    931925        {
    932926            Assert(!(pCur->Core.Key & PAGE_OFFSET_MASK));
    … …  
    961955 *
    962956 * @returns boolean
    963  * @param   pVM         VM Handle
     957 * @param   pVM         VM Handle.
    964958 * @param   GCPhys      Start physical address earlier passed to PGMR3HandlerPhysicalRegister().
    965959 */
    … …  
    11431137}
    11441138
    1145 
    11461139#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
     1140
    11471141/**
    11481142 * Worker for pgmHandlerVirtualDumpPhysPages.
    … …  
    11721166                           pgmHandlerVirtualDumpPhysPagesCallback, 0);
    11731167}
     1168
    11741169#endif /* VBOX_STRICT || LOG_ENABLED */
    1175 
    11761170#ifdef VBOX_STRICT
    11771171

  • trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp

    r13019 r13232  
    5555    AssertMsg(cbPages > 0 && RT_ALIGN_32(cbPages, PAGE_SIZE) == cbPages, ("Invalid cbPages=%#x\n",  cbPages));
    5656    AssertMsg(!(fFlags & X86_PDE_PG_MASK), ("Invalid flags %#x\n", fFlags));
    57     //Assert(HCPhys < _4G); ---  Don't *EVER* try 32-bit shadow mode on a PAE/AMD64 box with memory above 4G !!!
    5857
    5958    /* hypervisor defaults */
    … …  
    148147     * Validate input.
    149148     */
    150     if (fFlags & X86_PTE_PAE_PG_MASK)
    151     {
    152         AssertMsgFailed(("fFlags=%#x\n", fFlags));
    153         return VERR_INVALID_PARAMETER;
    154     }
    155     if (!cb)
    156     {
    157         AssertFailed();
    158         return VERR_INVALID_PARAMETER;
    159     }
     149    AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#x\n", fFlags));
     150    Assert(cb);
    160151
    161152    /*
    … …  
    175166        if (off < pCur->cb)
    176167        {
    177             if (off + cb > pCur->cb)
    178             {
    179                 AssertMsgFailed(("Invalid page range %#x LB%#x. mapping '%s' %#x to %#x\n",
    180                                  GCPtr, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast));
    181                 return VERR_INVALID_PARAMETER;
    182             }
     168            AssertMsgReturn(off + cb <= pCur->cb,
     169                            ("Invalid page range %#x LB%#x. mapping '%s' %#x to %#x\n",
     170                             GCPtr, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast),
     171                            VERR_INVALID_PARAMETER);
    183172
    184173            /*

  • trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

    r13203 r13232  
    6060# define SHW_PT_MASK            X86_PT_MASK
    6161# define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_PD
     62
    6263#elif PGM_SHW_TYPE == PGM_TYPE_EPT
    6364# define SHWPT                  EPTPT
    … …  
    8081# define SHW_TOTAL_PD_ENTRIES   (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
    8182# define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_NESTED_ROOT      /* do not use! exception is real mode & protected mode without paging. */
     83
    8284#else
    8385# define SHWPT                  X86PTPAE
    … …  
    9597# define SHW_PT_SHIFT           X86_PT_PAE_SHIFT
    9698# define SHW_PT_MASK            X86_PT_PAE_MASK
    97 #if PGM_SHW_TYPE == PGM_TYPE_AMD64
    98 # define SHW_PDPT_SHIFT         X86_PDPT_SHIFT
    99 # define SHW_PDPT_MASK          X86_PDPT_MASK_AMD64
    100 # define SHW_PDPE_PG_MASK       X86_PDPE_PG_MASK
    101 # define SHW_TOTAL_PD_ENTRIES   (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
    102 # define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_PAE_PD      /* do not use! exception is real mode & protected mode without paging. */
    103 #else /* 32 bits PAE mode */
    104 # define SHW_PDPT_SHIFT         X86_PDPT_SHIFT
    105 # define SHW_PDPT_MASK          X86_PDPT_MASK_PAE
    106 # define SHW_PDPE_PG_MASK       X86_PDPE_PG_MASK
    107 # define SHW_TOTAL_PD_ENTRIES   (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
    108 # define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_PAE_PD
    109 #endif
     99# if PGM_SHW_TYPE == PGM_TYPE_AMD64
     100#  define SHW_PDPT_SHIFT        X86_PDPT_SHIFT
     101#  define SHW_PDPT_MASK         X86_PDPT_MASK_AMD64
     102#  define SHW_PDPE_PG_MASK      X86_PDPE_PG_MASK
     103#  define SHW_TOTAL_PD_ENTRIES  (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
     104#  define SHW_POOL_ROOT_IDX     PGMPOOL_IDX_PAE_PD      /* do not use! exception is real mode & protected mode without paging. */
     105# else /* 32 bits PAE mode */
     106#  define SHW_PDPT_SHIFT        X86_PDPT_SHIFT
     107#  define SHW_PDPT_MASK         X86_PDPT_MASK_PAE
     108#  define SHW_PDPE_PG_MASK      X86_PDPE_PG_MASK
     109#  define SHW_TOTAL_PD_ENTRIES  (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
     110#  define SHW_POOL_ROOT_IDX     PGMPOOL_IDX_PAE_PD
     111# endif
    110112#endif
    111113
    … …  
    143145     */
    144146# if PGM_SHW_TYPE == PGM_TYPE_AMD64
    145     bool      fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
     147    bool            fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
    146148    X86PDEPAE Pde;
    147149
    148150    /* PML4 */
    149     const unsigned iPml4  = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     151    const unsigned  iPml4  = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    150152    X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
    151153    if (!Pml4e.n.u1Present)
    … …  
    153155
    154156    /* PDPT */
    155     PX86PDPT pPDPT;
     157    PX86PDPT        pPDPT;
    156158    int rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
    157159    if (VBOX_FAILURE(rc))
    158160        return rc;
    159     const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
    160     X86PDPE Pdpe = pPDPT->a[iPDPT];
     161    const unsigned  iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
     162    X86PDPE         Pdpe = pPDPT->a[iPDPT];
    161163    if (!Pdpe.n.u1Present)
    162164        return VERR_PAGE_TABLE_NOT_PRESENT;
    163165
    164166    /* PD */
    165     PX86PDPAE pPd;
     167    PX86PDPAE       pPd;
    166168    rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
    167169    if (VBOX_FAILURE(rc))
    168170        return rc;
    169     const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
     171    const unsigned  iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
    170172    Pde = pPd->a[iPd];
    171173
    … …  
    177179
    178180# elif PGM_SHW_TYPE == PGM_TYPE_PAE
    179     bool           fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
    180     const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
    181     const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
    182     X86PDEPAE      Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
     181    bool            fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
     182    const unsigned  iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
     183    const unsigned  iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
     184    X86PDEPAE       Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
     185
    183186# elif PGM_SHW_TYPE == PGM_TYPE_EPT
    184187    const unsigned  iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
    … …  
    194197    Assert(pPDDst);
    195198    Pde = pPDDst->a[iPd];
     199
    196200# else /* PGM_TYPE_32BIT */
    197     const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
    198     X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
     201    const unsigned  iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
     202    X86PDE          Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
    199203# endif
    200204    if (!Pde.n.u1Present)
    … …  
    206210     * Get PT entry.
    207211     */
    208     PSHWPT pPT;
     212    PSHWPT          pPT;
    209213    if (!(Pde.u & PGM_PDFLAGS_MAPPING))
    210214    {
    … …  
    230234# endif
    231235    }
    232     const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
    233     SHWPTE Pte = pPT->a[iPt];
     236    const unsigned  iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
     237    SHWPTE          Pte = pPT->a[iPt];
    234238    if (!Pte.n.u1Present)
    235239        return VERR_PAGE_NOT_PRESENT;
    … …  
    290294         */
    291295# if PGM_SHW_TYPE == PGM_TYPE_AMD64
    292         X86PDEPAE Pde;
     296        X86PDEPAE       Pde;
    293297        /* PML4 */
    294         const unsigned iPml4  = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
    295         X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
     298        const unsigned  iPml4  = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
     299        X86PML4E        Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
    296300        if (!Pml4e.n.u1Present)
    297301            return VERR_PAGE_TABLE_NOT_PRESENT;
    298302
    299303        /* PDPT */
    300         PX86PDPT pPDPT;
     304        PX86PDPT        pPDPT;
    301305        rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
    302306        if (VBOX_FAILURE(rc))
    303307            return rc;
    304         const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
    305         X86PDPE Pdpe = pPDPT->a[iPDPT];
     308        const unsigned  iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
     309        X86PDPE         Pdpe = pPDPT->a[iPDPT];
    306310        if (!Pdpe.n.u1Present)
    307311            return VERR_PAGE_TABLE_NOT_PRESENT;
    308312
    309313        /* PD */
    310         PX86PDPAE pPd;
     314        PX86PDPAE       pPd;
    311315        rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
    312316        if (VBOX_FAILURE(rc))
    … …  
    316320
    317321# elif PGM_SHW_TYPE == PGM_TYPE_PAE
    318         const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
    319         const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
     322        const unsigned  iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
     323        const unsigned  iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
    320324        X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
    321325
    … …  
    333337        Assert(pPDDst);
    334338        Pde = pPDDst->a[iPd];
     339
    335340# else /* PGM_TYPE_32BIT */
    336         const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
    337         X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
     341        const unsigned  iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
     342        X86PDE          Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
    338343# endif
    339344        if (!Pde.n.u1Present)
    … …  
    343348         * Map the page table.
    344349         */
    345         PSHWPT pPT;
     350        PSHWPT          pPT;
    346351        rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
    347352        if (VBOX_FAILURE(rc))
    348353            return rc;
    349354
    350         unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
     355        unsigned        iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
    351356        while (iPTE < RT_ELEMENTS(pPT->a))
    352357        {
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