VirtualBox

source: vbox/trunk/src/VBox/VMM/EMHandleRCTmpl.h@ 22016

Last change on this file since 22016 was 21653, checked in by vboxsync, 15 years ago

TPR patching updates
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File size: 11.2 KB
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1/* $Id: EMHandleRCTmpl.h 21653 2009-07-16 15:18:07Z vboxsync $ */
2/** @file
3 * EM - emR3[Raw|Hwaccm]HandleRC template.
4 */
5
6/*
7 * Copyright (C) 2006-2009 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___EMHandleRCTmpl_h
23#define ___EMHandleRCTmpl_h
24
25/**
26 * Process a subset of the raw-mode return code.
27 *
28 * Since we have to share this with raw-mode single stepping, this inline
29 * function has been created to avoid code duplication.
30 *
31 * @returns VINF_SUCCESS if it's ok to continue raw mode.
32 * @returns VBox status code to return to the EM main loop.
33 *
34 * @param pVM The VM handle
35 * @param pVCpu The VMCPU handle
36 * @param rc The return code.
37 * @param pCtx The guest cpu context.
38 */
39#ifdef EMHANDLERC_WITH_PATM
40int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
41#elif defined(EMHANDLERC_WITH_HWACCM)
42int emR3HwaccmHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
43#endif
44{
45 switch (rc)
46 {
47 /*
48 * Common & simple ones.
49 */
50 case VINF_SUCCESS:
51 break;
52 case VINF_EM_RESCHEDULE_RAW:
53 case VINF_EM_RESCHEDULE_HWACC:
54 case VINF_EM_RAW_INTERRUPT:
55 case VINF_EM_RAW_TO_R3:
56 case VINF_EM_RAW_TIMER_PENDING:
57 case VINF_EM_PENDING_REQUEST:
58 rc = VINF_SUCCESS;
59 break;
60
61#ifdef EMHANDLERC_WITH_PATM
62 /*
63 * Privileged instruction.
64 */
65 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
66 case VINF_PATM_PATCH_TRAP_GP:
67 rc = emR3RawPrivileged(pVM, pVCpu);
68 break;
69
70 case VINF_EM_RAW_GUEST_TRAP:
71 /*
72 * Got a trap which needs dispatching.
73 */
74 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
75 {
76 AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
77 rc = VERR_EM_RAW_PATCH_CONFLICT;
78 break;
79 }
80 rc = emR3RawGuestTrap(pVM, pVCpu);
81 break;
82
83 /*
84 * Trap in patch code.
85 */
86 case VINF_PATM_PATCH_TRAP_PF:
87 case VINF_PATM_PATCH_INT3:
88 rc = emR3PatchTrap(pVM, pVCpu, pCtx, rc);
89 break;
90
91 case VINF_PATM_DUPLICATE_FUNCTION:
92 Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
93 rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
94 AssertRC(rc);
95 rc = VINF_SUCCESS;
96 break;
97
98 case VINF_PATM_CHECK_PATCH_PAGE:
99 rc = PATMR3HandleMonitoredPage(pVM);
100 AssertRC(rc);
101 rc = VINF_SUCCESS;
102 break;
103
104 /*
105 * Patch manager.
106 */
107 case VERR_EM_RAW_PATCH_CONFLICT:
108 AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
109 break;
110#endif /* EMHANDLERC_WITH_PATM */
111
112#ifdef VBOX_WITH_VMI
113 /*
114 * PARAV function.
115 */
116 case VINF_EM_RESCHEDULE_PARAV:
117 rc = PARAVCallFunction(pVM);
118 break;
119#endif
120
121#ifdef EMHANDLERC_WITH_PATM
122 /*
123 * Memory mapped I/O access - attempt to patch the instruction
124 */
125 case VINF_PATM_HC_MMIO_PATCH_READ:
126 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
127 PATMFL_MMIO_ACCESS | ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
128 if (RT_FAILURE(rc))
129 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
130 break;
131
132 case VINF_PATM_HC_MMIO_PATCH_WRITE:
133 AssertFailed(); /* not yet implemented. */
134 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
135 break;
136#endif /* EMHANDLERC_WITH_PATM */
137
138 /*
139 * Conflict or out of page tables.
140 *
141 * VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
142 * do here is to execute the pending forced actions.
143 */
144 case VINF_PGM_SYNC_CR3:
145 AssertMsg(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
146 ("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
147 rc = VINF_SUCCESS;
148 break;
149
150 /*
151 * Paging mode change.
152 */
153 case VINF_PGM_CHANGE_MODE:
154 rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
155 if (rc == VINF_SUCCESS)
156 rc = VINF_EM_RESCHEDULE;
157 AssertMsg(RT_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
158 break;
159
160#ifdef EMHANDLERC_WITH_PATM
161 /*
162 * CSAM wants to perform a task in ring-3. It has set an FF action flag.
163 */
164 case VINF_CSAM_PENDING_ACTION:
165 rc = VINF_SUCCESS;
166 break;
167
168 /*
169 * Invoked Interrupt gate - must directly (!) go to the recompiler.
170 */
171 case VINF_EM_RAW_INTERRUPT_PENDING:
172 case VINF_EM_RAW_RING_SWITCH_INT:
173 Assert(TRPMHasTrap(pVCpu));
174 Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
175
176 if (TRPMHasTrap(pVCpu))
177 {
178 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
179 uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
180 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
181 {
182 CSAMR3CheckGates(pVM, u8Interrupt, 1);
183 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
184 /* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
185 }
186 }
187 rc = VINF_EM_RESCHEDULE_REM;
188 break;
189
190 /*
191 * Other ring switch types.
192 */
193 case VINF_EM_RAW_RING_SWITCH:
194 rc = emR3RawRingSwitch(pVM, pVCpu);
195 break;
196#endif /* EMHANDLERC_WITH_PATM */
197
198 /*
199 * I/O Port access - emulate the instruction.
200 */
201 case VINF_IOM_HC_IOPORT_READ:
202 case VINF_IOM_HC_IOPORT_WRITE:
203 rc = emR3ExecuteIOInstruction(pVM, pVCpu);
204 break;
205
206 /*
207 * Memory mapped I/O access - emulate the instruction.
208 */
209 case VINF_IOM_HC_MMIO_READ:
210 case VINF_IOM_HC_MMIO_WRITE:
211 case VINF_IOM_HC_MMIO_READ_WRITE:
212 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
213 break;
214
215#ifdef EMHANDLERC_WITH_HWACCM
216 /*
217 * (MM)IO intensive code block detected; fall back to the recompiler for better performance
218 */
219 case VINF_EM_RAW_EMULATE_IO_BLOCK:
220 rc = HWACCMR3EmulateIoBlock(pVM, pCtx);
221 break;
222
223 case VINF_EM_HWACCM_PATCH_TPR_INSTR:
224 rc = HWACCMR3PatchTprInstr(pVM, pVCpu, pCtx);
225 break;
226#endif
227
228#ifdef EMHANDLERC_WITH_PATM
229 /*
230 * Execute instruction.
231 */
232 case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
233 rc = emR3ExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
234 break;
235 case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
236 rc = emR3ExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
237 break;
238 case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
239 rc = emR3ExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
240 break;
241 case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
242 rc = emR3ExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
243 break;
244 case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
245 rc = emR3ExecuteInstruction(pVM, pVCpu, "PD FAULT: ");
246 break;
247 case VINF_EM_RAW_EMULATE_INSTR_HLT:
248 /** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
249 rc = emR3RawPrivileged(pVM, pVCpu);
250 break;
251#endif
252
253#ifdef EMHANDLERC_WITH_PATM
254 case VINF_PATM_PENDING_IRQ_AFTER_IRET:
255 rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
256 break;
257
258 case VINF_PATCH_EMULATE_INSTR:
259#else
260 case VINF_EM_RAW_GUEST_TRAP:
261#endif
262 case VINF_EM_RAW_EMULATE_INSTR:
263 rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ");
264 break;
265
266#ifdef EMHANDLERC_WITH_PATM
267 /*
268 * Stale selector and iret traps => REM.
269 */
270 case VINF_EM_RAW_STALE_SELECTOR:
271 case VINF_EM_RAW_IRET_TRAP:
272 /* We will not go to the recompiler if EIP points to patch code. */
273 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
274 {
275 pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
276 }
277 LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
278 rc = VINF_EM_RESCHEDULE_REM;
279 break;
280#endif
281
282 /*
283 * Up a level.
284 */
285 case VINF_EM_TERMINATE:
286 case VINF_EM_OFF:
287 case VINF_EM_RESET:
288 case VINF_EM_SUSPEND:
289 case VINF_EM_HALT:
290 case VINF_EM_RESUME:
291 case VINF_EM_NO_MEMORY:
292 case VINF_EM_RESCHEDULE:
293 case VINF_EM_RESCHEDULE_REM:
294 case VINF_EM_WAIT_SIPI:
295 break;
296
297 /*
298 * Up a level and invoke the debugger.
299 */
300 case VINF_EM_DBG_STEPPED:
301 case VINF_EM_DBG_BREAKPOINT:
302 case VINF_EM_DBG_STEP:
303 case VINF_EM_DBG_HYPER_BREAKPOINT:
304 case VINF_EM_DBG_HYPER_STEPPED:
305 case VINF_EM_DBG_HYPER_ASSERTION:
306 case VINF_EM_DBG_STOP:
307 break;
308
309 /*
310 * Up a level, dump and debug.
311 */
312 case VERR_TRPM_DONT_PANIC:
313 case VERR_TRPM_PANIC:
314 case VERR_VMM_RING0_ASSERTION:
315 case VERR_VMM_HYPER_CR3_MISMATCH:
316 case VERR_VMM_RING3_CALL_DISABLED:
317 break;
318
319#ifdef EMHANDLERC_WITH_HWACCM
320 /*
321 * Up a level, after HwAccM have done some release logging.
322 */
323 case VERR_VMX_INVALID_VMCS_FIELD:
324 case VERR_VMX_INVALID_VMCS_PTR:
325 case VERR_VMX_INVALID_VMXON_PTR:
326 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
327 case VERR_VMX_UNEXPECTED_EXCEPTION:
328 case VERR_VMX_UNEXPECTED_EXIT_CODE:
329 case VERR_VMX_INVALID_GUEST_STATE:
330 case VERR_VMX_UNABLE_TO_START_VM:
331 case VERR_VMX_UNABLE_TO_RESUME_VM:
332 HWACCMR3CheckError(pVM, rc);
333 break;
334#endif
335
336 /*
337 * Anything which is not known to us means an internal error
338 * and the termination of the VM!
339 */
340 default:
341 AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
342 break;
343 }
344 return rc;
345}
346
347#endif
348
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