VirtualBox

Changeset 22016 in vbox


Ignore:
Timestamp:
Aug 6, 2009 9:07:11 AM (16 years ago)
Author:
vboxsync
Message:

MSR bitmap must be per-VCPU

Location:
trunk/src/VBox/VMM
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/HWACCMInternal.h

    r21989 r22016  
    417417        R0PTRTYPE(void *)           pIOBitmap;
    418418
    419         /** R0 memory object for the MSR bitmap (8kb). */
    420         RTR0MEMOBJ                  pMemObjMSRBitmap;
    421         /** Physical address of the MSR bitmap (8kb). */
    422         RTHCPHYS                    pMSRBitmapPhys;
    423         /** Virtual address of the MSR bitmap. */
    424         R0PTRTYPE(void *)           pMSRBitmap;
    425 
    426419        /** SVM revision. */
    427420        uint32_t                    u32Rev;
    … …  
    641634        PFNHWACCMSVMVMRUN           pfnVMRun;
    642635
     636        /** R0 memory object for the MSR bitmap (8kb). */
     637        RTR0MEMOBJ                  pMemObjMSRBitmap;
     638        /** Physical address of the MSR bitmap (8kb). */
     639        RTHCPHYS                    pMSRBitmapPhys;
     640        /** Virtual address of the MSR bitmap. */
     641        R0PTRTYPE(void *)           pMSRBitmap;
    643642    } svm;
    644643

  • trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

    r21988 r22016  
    5555static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
    5656static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
    57 static void svmR0SetMSRPermission(PVM pVM, unsigned ulMSR, bool fRead, bool fWrite);
     57static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
    5858
    5959/*******************************************************************************
    … …  
    132132
    133133    pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
    134     pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
    135134
    136135    /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
    … …  
    143142    /* Set all bits to intercept all IO accesses. */
    144143    ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
    145 
    146     /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
    147     rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
    148     if (RT_FAILURE(rc))
    149         return rc;
    150 
    151     pVM->hwaccm.s.svm.pMSRBitmap     = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
    152     pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
    153     /* Set all bits to intercept all MSR accesses. */
    154     ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
    155144
    156145    /* Erratum 170 which requires a forced TLB flush for each world switch:
    … …  
    190179        PVMCPU pVCpu = &pVM->aCpus[i];
    191180
    192         pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
    193         pVCpu->hwaccm.s.svm.pMemObjVMCB     = NIL_RTR0MEMOBJ;
     181        pVCpu->hwaccm.s.svm.pMemObjVMCBHost  = NIL_RTR0MEMOBJ;
     182        pVCpu->hwaccm.s.svm.pMemObjVMCB      = NIL_RTR0MEMOBJ;
     183        pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
    194184
    195185        /* Allocate one page for the host context */
    … …  
    210200        pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
    211201        ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
     202
     203        /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
     204        rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
     205        if (RT_FAILURE(rc))
     206            return rc;
     207
     208        pVCpu->hwaccm.s.svm.pMSRBitmap     = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);
     209        pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
     210        /* Set all bits to intercept all MSR accesses. */
     211        ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
    212212    }
    213213
    … …  
    242242            pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
    243243        }
     244        if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
     245        {
     246            RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);
     247            pVCpu->hwaccm.s.svm.pMSRBitmap       = 0;
     248            pVCpu->hwaccm.s.svm.pMSRBitmapPhys   = 0;
     249            pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
     250        }
    244251    }
    245252    if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
    … …  
    249256        pVM->hwaccm.s.svm.pIOBitmapPhys   = 0;
    250257        pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
    251     }
    252     if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
    253     {
    254         RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
    255         pVM->hwaccm.s.svm.pMSRBitmap       = 0;
    256         pVM->hwaccm.s.svm.pMSRBitmapPhys   = 0;
    257         pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
    258258    }
    259259    return VINF_SUCCESS;
    … …  
    269269{
    270270    int         rc = VINF_SUCCESS;
    271     SVM_VMCB   *pVMCB;
    272271
    273272    AssertReturn(pVM, VERR_INVALID_PARAMETER);
    … …  
    277276    for (unsigned i=0;i<pVM->cCPUs;i++)
    278277    {
    279         pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
     278        PVMCPU    pVCpu = &pVM->aCpus[i];
     279        SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
     280
    280281        AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
    281282
    … …  
    352353        /* Set IO and MSR bitmap addresses. */
    353354        pVMCB->ctrl.u64IOPMPhysAddr  = pVM->hwaccm.s.svm.pIOBitmapPhys;
    354         pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
     355        pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;
    355356
    356357        /* No LBR virtualization. */
    … …  
    362363        /** Setup the PAT msr (nested paging only) */
    363364        pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
    364     }
    365 
    366     /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
    367      * to modify them directly.
    368      */
    369     svmR0SetMSRPermission(pVM, MSR_K8_LSTAR, true, true);
    370     svmR0SetMSRPermission(pVM, MSR_K8_CSTAR, true, true);
    371     svmR0SetMSRPermission(pVM, MSR_K6_STAR, true, true);
    372     svmR0SetMSRPermission(pVM, MSR_K8_SF_MASK, true, true);
    373     svmR0SetMSRPermission(pVM, MSR_K8_FS_BASE, true, true);
    374     svmR0SetMSRPermission(pVM, MSR_K8_GS_BASE, true, true);
    375     svmR0SetMSRPermission(pVM, MSR_K8_KERNEL_GS_BASE, true, true);
    376     svmR0SetMSRPermission(pVM, MSR_IA32_SYSENTER_CS, true, true);
    377     svmR0SetMSRPermission(pVM, MSR_IA32_SYSENTER_ESP, true, true);
    378     svmR0SetMSRPermission(pVM, MSR_IA32_SYSENTER_EIP, true, true);
     365        /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
     366         * to modify them directly.
     367         */
     368        svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
     369        svmR0SetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
     370        svmR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
     371        svmR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
     372        svmR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
     373        svmR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
     374        svmR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
     375        svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
     376        svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
     377        svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
     378    }
     379
    379380    return rc;
    380381}
    … …  
    384385 * Sets the permission bits for the specified MSR
    385386 *
    386  * @param   pVM         The VM to operate on.
     387 * @param   pVCpu       The VMCPU to operate on.
    387388 * @param   ulMSR       MSR value
    388389 * @param   fRead       Reading allowed/disallowed
    389390 * @param   fWrite      Writing allowed/disallowed
    390391 */
    391 static void svmR0SetMSRPermission(PVM pVM, unsigned ulMSR, bool fRead, bool fWrite)
     392static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
    392393{
    393394    unsigned ulBit;
    394     uint8_t *pMSRBitmap = (uint8_t *)pVM->hwaccm.s.svm.pMSRBitmap;
     395    uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.svm.pMSRBitmap;
    395396
    396397    if (ulMSR <= 0x00001FFF)
    … …  
    10851086            {
    10861087                /* A TPR change could activate a pending interrupt, so catch lstar writes. */
    1087                 svmR0SetMSRPermission(pVM, MSR_K8_LSTAR, true, false);
     1088                svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
    10881089            }
    10891090            else
    … …  
    10911092                 * There are enough world switches for detecting pending interrupts.
    10921093                 */
    1093                 svmR0SetMSRPermission(pVM, MSR_K8_LSTAR, true, true);
     1094                svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
    10941095        }
    10951096        else
    … …  
    12361237    Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
    12371238    Assert(pVMCB->ctrl.u64IOPMPhysAddr  == pVM->hwaccm.s.svm.pIOBitmapPhys);
    1238     Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
     1239    Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);
    12391240    Assert(pVMCB->ctrl.u64LBRVirt == 0);
    12401241
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