HWACCMInternal.h@ 7802

Last change on this file since 7802 was 7496, checked in by vboxsync, 17 years ago
Moved VMCS allocation to ring 0.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 12.0 KB

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1	/* $Id: HWACCMInternal.h 7496 2008-03-19 10:22:50Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HWACCMInternal_h
19	#define ___HWACCMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/em.h>
24	#include <VBox/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/hwaccm.h>
27	#include <VBox/pgm.h>
28	#include <iprt/memobj.h>
29
30	__BEGIN_DECLS
31
32
33	/** @defgroup grp_hwaccm_int Internal
34	* @ingroup grp_hwaccm
35	* @internal
36	* @{
37	*/
38
39
40	/**
41	* Converts a HWACCM pointer into a VM pointer.
42	* @returns Pointer to the VM structure the EM is part of.
43	* @param pHWACCM Pointer to HWACCM instance data.
44	*/
45	#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
46
47	/** Maximum number of exit reason statistics counters. */
48	#define MAX_EXITREASON_STAT 0x100
49	#define MASK_EXITREASON_STAT 0xff
50
51	/** @name Changed flags
52	* These flags are used to keep track of which important registers that
53	* have been changed since last they were reset.
54	* @{
55	*/
56	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
57	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
58	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
59	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
60	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
61	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
62	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
63	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
64	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
65	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
66	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
67	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
68
69	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
70	\| HWACCM_CHANGED_GUEST_CR0 \
71	\| HWACCM_CHANGED_GUEST_CR3 \
72	\| HWACCM_CHANGED_GUEST_CR4 \
73	\| HWACCM_CHANGED_GUEST_GDTR \
74	\| HWACCM_CHANGED_GUEST_IDTR \
75	\| HWACCM_CHANGED_GUEST_LDTR \
76	\| HWACCM_CHANGED_GUEST_TR \
77	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
78	\| HWACCM_CHANGED_GUEST_FPU \
79	\| HWACCM_CHANGED_GUEST_DEBUG \
80	\| HWACCM_CHANGED_HOST_CONTEXT)
81
82	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
83	\| HWACCM_CHANGED_GUEST_CR0 \
84	\| HWACCM_CHANGED_GUEST_CR3 \
85	\| HWACCM_CHANGED_GUEST_CR4 \
86	\| HWACCM_CHANGED_GUEST_GDTR \
87	\| HWACCM_CHANGED_GUEST_IDTR \
88	\| HWACCM_CHANGED_GUEST_LDTR \
89	\| HWACCM_CHANGED_GUEST_TR \
90	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
91	\| HWACCM_CHANGED_GUEST_DEBUG \
92	\| HWACCM_CHANGED_GUEST_FPU)
93
94	/** @} */
95
96	/** @name Intercepted traps
97	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
98	* Currently #NM and #PF only
99	*/
100	#ifdef VBOX_STRICT
101	#define HWACCM_VMX_TRAP_MASK RT_BIT(0) \| RT_BIT(7) \| RT_BIT(14) \| RT_BIT(6) \| RT_BIT(11) \| RT_BIT(12) \| RT_BIT(13) \| RT_BIT(16)
102	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
103	#else
104	#define HWACCM_VMX_TRAP_MASK RT_BIT(7) \| RT_BIT(14)
105	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
106	#endif
107	/** @} */
108
109
110	/** Maxium resume loops allowed in ring 0 (safety precaution) */
111	#define HWACCM_MAX_RESUME_LOOPS 1024
112
113	/** HWACCM SSM version
114	*/
115	#define HWACCM_SSM_VERSION 3
116
117	/**
118	* HWACCM VM Instance data.
119	* Changes to this must checked against the padding of the cfgm union in VM!
120	*/
121	typedef struct HWACCM
122	{
123	/** Offset to the VM structure.
124	* See HWACCM2VM(). */
125	RTUINT offVM;
126
127	/** Set when we've initialized VMX or SVM. */
128	bool fInitialized;
129	/** Set when we're using VMX/SVN at that moment. */
130	bool fActive;
131
132	/** Set when hardware acceleration is allowed. */
133	bool fAllowed;
134
135	/** HWACCM_CHANGED_* flags. */
136	uint32_t fContextUseFlags;
137
138	/** Old style FPU reporting trap mask override performed (optimization) */
139	uint32_t fFPUOldStyleOverride;
140
141	struct
142	{
143	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
144	bool fSupported;
145
146	/** Set when we've enabled VMX. */
147	bool fEnabled;
148
149	/** Set if we can use VMXResume to execute guest code. */
150	bool fResumeVM;
151
152	/** R0 memory object for the VM control structure (VMCS). */
153	RTR0MEMOBJ pMemObjVMCS;
154	/** Physical address of the VM control structure (VMCS). */
155	RTHCPHYS pVMCSPhys;
156	/** Virtual address of the VM control structure (VMCS). */
157	R0PTRTYPE(void *) pVMCS;
158
159	/** R0 memory object for the TSS page used for real mode emulation. */
160	RTR0MEMOBJ pMemObjRealModeTSS;
161	/** Physical address of the TSS page used for real mode emulation. */
162	RTHCPHYS pRealModeTSSPhys;
163	/** Virtual address of the TSS page used for real mode emulation. */
164	R0PTRTYPE(PVBOXTSS) pRealModeTSS;
165
166	/** Host CR4 value (set by ring-0 VMX init) */
167	uint64_t hostCR4;
168
169	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
170	uint64_t proc_ctls;
171
172	/** Current CR0 mask. */
173	uint64_t cr0_mask;
174	/** Current CR4 mask. */
175	uint64_t cr4_mask;
176
177	/** VMX MSR values */
178	struct
179	{
180	uint64_t feature_ctrl;
181	uint64_t vmx_basic_info;
182	uint64_t vmx_pin_ctls;
183	uint64_t vmx_proc_ctls;
184	uint64_t vmx_exit;
185	uint64_t vmx_entry;
186	uint64_t vmx_misc;
187	uint64_t vmx_cr0_fixed0;
188	uint64_t vmx_cr0_fixed1;
189	uint64_t vmx_cr4_fixed0;
190	uint64_t vmx_cr4_fixed1;
191	uint64_t vmx_vmcs_enum;
192	} msr;
193
194	/* Last instruction error */
195	uint32_t ulLastInstrError;
196	} vmx;
197
198	struct
199	{
200	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
201	bool fSupported;
202
203	/** Set when we've enabled SVM. */
204	bool fEnabled;
205
206	/** Set if we don't have to flush the TLB on VM entry. */
207	bool fResumeVM;
208
209	/** R0 memory object for the VM control block (VMCB). */
210	RTR0MEMOBJ pMemObjVMCB;
211	/** Physical address of the VM control block (VMCB). */
212	RTHCPHYS pVMCBPhys;
213	/** Virtual address of the VM control block (VMCB). */
214	R0PTRTYPE(void *) pVMCB;
215
216	/** R0 memory object for the host VM control block (VMCB). */
217	RTR0MEMOBJ pMemObjVMCBHost;
218	/** Physical address of the host VM control block (VMCB). */
219	RTHCPHYS pVMCBHostPhys;
220	/** Virtual address of the host VM control block (VMCB). */
221	R0PTRTYPE(void *) pVMCBHost;
222
223	/** R0 memory object for the IO bitmap (12kb). */
224	RTR0MEMOBJ pMemObjIOBitmap;
225	/** Physical address of the IO bitmap (12kb). */
226	RTHCPHYS pIOBitmapPhys;
227	/** Virtual address of the IO bitmap. */
228	R0PTRTYPE(void *) pIOBitmap;
229
230	/** R0 memory object for the MSR bitmap (8kb). */
231	RTR0MEMOBJ pMemObjMSRBitmap;
232	/** Physical address of the MSR bitmap (8kb). */
233	RTHCPHYS pMSRBitmapPhys;
234	/** Virtual address of the MSR bitmap. */
235	R0PTRTYPE(void *) pMSRBitmap;
236
237	/** SVM revision. */
238	uint32_t u32Rev;
239
240	/** Maximum ASID allowed. */
241	uint32_t u32MaxASID;
242	} svm;
243
244	struct
245	{
246	uint32_t u32AMDFeatureECX;
247	uint32_t u32AMDFeatureEDX;
248	} cpuid;
249
250	/* Event injection state. */
251	struct
252	{
253	uint32_t fPending;
254	uint32_t errCode;
255	uint64_t intInfo;
256	} Event;
257
258	/** Saved error from detection */
259	int32_t lLastError;
260
261	/** HWACCMR0Init was run */
262	bool fHWACCMR0Init;
263
264	/** Currenty shadow paging mode. */
265	PGMMODE enmShadowMode;
266
267	STAMPROFILEADV StatEntry;
268	STAMPROFILEADV StatExit;
269	STAMPROFILEADV StatInGC;
270
271	STAMCOUNTER StatIntInject;
272
273	STAMCOUNTER StatExitShadowNM;
274	STAMCOUNTER StatExitGuestNM;
275	STAMCOUNTER StatExitShadowPF;
276	STAMCOUNTER StatExitGuestPF;
277	STAMCOUNTER StatExitGuestUD;
278	STAMCOUNTER StatExitGuestSS;
279	STAMCOUNTER StatExitGuestNP;
280	STAMCOUNTER StatExitGuestGP;
281	STAMCOUNTER StatExitGuestDE;
282	STAMCOUNTER StatExitGuestMF;
283	STAMCOUNTER StatExitInvpg;
284	STAMCOUNTER StatExitInvd;
285	STAMCOUNTER StatExitCpuid;
286	STAMCOUNTER StatExitRdtsc;
287	STAMCOUNTER StatExitCRxWrite;
288	STAMCOUNTER StatExitCRxRead;
289	STAMCOUNTER StatExitDRxWrite;
290	STAMCOUNTER StatExitDRxRead;
291	STAMCOUNTER StatExitCLTS;
292	STAMCOUNTER StatExitLMSW;
293	STAMCOUNTER StatExitIOWrite;
294	STAMCOUNTER StatExitIORead;
295	STAMCOUNTER StatExitIOStringWrite;
296	STAMCOUNTER StatExitIOStringRead;
297	STAMCOUNTER StatExitIrqWindow;
298	STAMCOUNTER StatExitMaxResume;
299	STAMCOUNTER StatIntReinject;
300	STAMCOUNTER StatPendingHostIrq;
301
302	STAMCOUNTER StatSwitchGuestIrq;
303	STAMCOUNTER StatSwitchToR3;
304
305	R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
306	R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
307	} HWACCM;
308	/** Pointer to HWACCM VM instance data. */
309	typedef HWACCM *PHWACCM;
310
311
312	#ifdef IN_RING0
313
314	#ifdef VBOX_STRICT
315	HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx);
316	HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
317	#else
318	#define HWACCMDumpRegs(a) do { } while (0)
319	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
320	#endif
321
322	#endif
323
324	/** @} */
325
326	__END_DECLS
327
328	#endif
329

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 7802

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