HWACCMInternal.h@ 8842

Last change on this file since 8842 was 8806, checked in by vboxsync, 17 years ago
Determine which AMD cpus are really affected by erratum 170 (forced TLB flush on each world switch as a workaround)
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File size: 12.3 KB

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1	/* $Id: HWACCMInternal.h 8806 2008-05-14 09:34:15Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <iprt/memobj.h>
33
34	__BEGIN_DECLS
35
36
37	/** @defgroup grp_hwaccm_int Internal
38	* @ingroup grp_hwaccm
39	* @internal
40	* @{
41	*/
42
43
44	/**
45	* Converts a HWACCM pointer into a VM pointer.
46	* @returns Pointer to the VM structure the EM is part of.
47	* @param pHWACCM Pointer to HWACCM instance data.
48	*/
49	#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
50
51	/** Maximum number of exit reason statistics counters. */
52	#define MAX_EXITREASON_STAT 0x100
53	#define MASK_EXITREASON_STAT 0xff
54
55	/** @name Changed flags
56	* These flags are used to keep track of which important registers that
57	* have been changed since last they were reset.
58	* @{
59	*/
60	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
61	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
62	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
63	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
64	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
65	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
66	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
67	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
68	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
69	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
70	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
71	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
72
73	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
74	\| HWACCM_CHANGED_GUEST_CR0 \
75	\| HWACCM_CHANGED_GUEST_CR3 \
76	\| HWACCM_CHANGED_GUEST_CR4 \
77	\| HWACCM_CHANGED_GUEST_GDTR \
78	\| HWACCM_CHANGED_GUEST_IDTR \
79	\| HWACCM_CHANGED_GUEST_LDTR \
80	\| HWACCM_CHANGED_GUEST_TR \
81	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
82	\| HWACCM_CHANGED_GUEST_FPU \
83	\| HWACCM_CHANGED_GUEST_DEBUG \
84	\| HWACCM_CHANGED_HOST_CONTEXT)
85
86	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
87	\| HWACCM_CHANGED_GUEST_CR0 \
88	\| HWACCM_CHANGED_GUEST_CR3 \
89	\| HWACCM_CHANGED_GUEST_CR4 \
90	\| HWACCM_CHANGED_GUEST_GDTR \
91	\| HWACCM_CHANGED_GUEST_IDTR \
92	\| HWACCM_CHANGED_GUEST_LDTR \
93	\| HWACCM_CHANGED_GUEST_TR \
94	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
95	\| HWACCM_CHANGED_GUEST_DEBUG \
96	\| HWACCM_CHANGED_GUEST_FPU)
97
98	/** @} */
99
100	/** @name Intercepted traps
101	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
102	* Currently #NM and #PF only
103	*/
104	#ifdef VBOX_STRICT
105	#define HWACCM_VMX_TRAP_MASK RT_BIT(0) \| RT_BIT(7) \| RT_BIT(14) \| RT_BIT(6) \| RT_BIT(11) \| RT_BIT(12) \| RT_BIT(13) \| RT_BIT(16)
106	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
107	#else
108	#define HWACCM_VMX_TRAP_MASK RT_BIT(7) \| RT_BIT(14)
109	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
110	#endif
111	/** @} */
112
113
114	/** Maxium resume loops allowed in ring 0 (safety precaution) */
115	#define HWACCM_MAX_RESUME_LOOPS 1024
116
117	/** HWACCM SSM version
118	*/
119	#define HWACCM_SSM_VERSION 3
120
121	/**
122	* HWACCM VM Instance data.
123	* Changes to this must checked against the padding of the cfgm union in VM!
124	*/
125	typedef struct HWACCM
126	{
127	/** Offset to the VM structure.
128	* See HWACCM2VM(). */
129	RTUINT offVM;
130
131	/** Set when we've initialized VMX or SVM. */
132	bool fInitialized;
133	/** Set when we're using VMX/SVN at that moment. */
134	bool fActive;
135
136	/** Set when hardware acceleration is allowed. */
137	bool fAllowed;
138
139	/** HWACCM_CHANGED_* flags. */
140	uint32_t fContextUseFlags;
141
142	/** Old style FPU reporting trap mask override performed (optimization) */
143	uint32_t fFPUOldStyleOverride;
144
145	struct
146	{
147	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
148	bool fSupported;
149
150	/** Set when we've enabled VMX. */
151	bool fEnabled;
152
153	/** Set if we can use VMXResume to execute guest code. */
154	bool fResumeVM;
155
156	/** R0 memory object for the VM control structure (VMCS). */
157	RTR0MEMOBJ pMemObjVMCS;
158	/** Physical address of the VM control structure (VMCS). */
159	RTHCPHYS pVMCSPhys;
160	/** Virtual address of the VM control structure (VMCS). */
161	R0PTRTYPE(void *) pVMCS;
162
163	/** R0 memory object for the TSS page used for real mode emulation. */
164	RTR0MEMOBJ pMemObjRealModeTSS;
165	/** Physical address of the TSS page used for real mode emulation. */
166	RTHCPHYS pRealModeTSSPhys;
167	/** Virtual address of the TSS page used for real mode emulation. */
168	R0PTRTYPE(PVBOXTSS) pRealModeTSS;
169
170	/** Host CR4 value (set by ring-0 VMX init) */
171	uint64_t hostCR4;
172
173	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
174	uint64_t proc_ctls;
175
176	/** Current CR0 mask. */
177	uint64_t cr0_mask;
178	/** Current CR4 mask. */
179	uint64_t cr4_mask;
180
181	/** VMX MSR values */
182	struct
183	{
184	uint64_t feature_ctrl;
185	uint64_t vmx_basic_info;
186	uint64_t vmx_pin_ctls;
187	uint64_t vmx_proc_ctls;
188	uint64_t vmx_exit;
189	uint64_t vmx_entry;
190	uint64_t vmx_misc;
191	uint64_t vmx_cr0_fixed0;
192	uint64_t vmx_cr0_fixed1;
193	uint64_t vmx_cr4_fixed0;
194	uint64_t vmx_cr4_fixed1;
195	uint64_t vmx_vmcs_enum;
196	} msr;
197
198	/* Last instruction error */
199	uint32_t ulLastInstrError;
200	} vmx;
201
202	struct
203	{
204	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
205	bool fSupported;
206
207	/** Set when we've enabled SVM. */
208	bool fEnabled;
209
210	/** Set if we don't have to flush the TLB on VM entry. */
211	bool fResumeVM;
212	/** Set if erratum 170 affects the AMD cpu. */
213	bool fForceTLBFlush;
214
215	/** R0 memory object for the VM control block (VMCB). */
216	RTR0MEMOBJ pMemObjVMCB;
217	/** Physical address of the VM control block (VMCB). */
218	RTHCPHYS pVMCBPhys;
219	/** Virtual address of the VM control block (VMCB). */
220	R0PTRTYPE(void *) pVMCB;
221
222	/** R0 memory object for the host VM control block (VMCB). */
223	RTR0MEMOBJ pMemObjVMCBHost;
224	/** Physical address of the host VM control block (VMCB). */
225	RTHCPHYS pVMCBHostPhys;
226	/** Virtual address of the host VM control block (VMCB). */
227	R0PTRTYPE(void *) pVMCBHost;
228
229	/** R0 memory object for the IO bitmap (12kb). */
230	RTR0MEMOBJ pMemObjIOBitmap;
231	/** Physical address of the IO bitmap (12kb). */
232	RTHCPHYS pIOBitmapPhys;
233	/** Virtual address of the IO bitmap. */
234	R0PTRTYPE(void *) pIOBitmap;
235
236	/** R0 memory object for the MSR bitmap (8kb). */
237	RTR0MEMOBJ pMemObjMSRBitmap;
238	/** Physical address of the MSR bitmap (8kb). */
239	RTHCPHYS pMSRBitmapPhys;
240	/** Virtual address of the MSR bitmap. */
241	R0PTRTYPE(void *) pMSRBitmap;
242
243	/** SVM revision. */
244	uint32_t u32Rev;
245
246	/** Maximum ASID allowed. */
247	uint32_t u32MaxASID;
248	} svm;
249
250	struct
251	{
252	uint32_t u32AMDFeatureECX;
253	uint32_t u32AMDFeatureEDX;
254	} cpuid;
255
256	/* Event injection state. */
257	struct
258	{
259	uint32_t fPending;
260	uint32_t errCode;
261	uint64_t intInfo;
262	} Event;
263
264	/** Saved error from detection */
265	int32_t lLastError;
266
267	/** HWACCMR0Init was run */
268	bool fHWACCMR0Init;
269
270	/** Currenty shadow paging mode. */
271	PGMMODE enmShadowMode;
272
273	STAMPROFILEADV StatEntry;
274	STAMPROFILEADV StatExit;
275	STAMPROFILEADV StatInGC;
276
277	STAMCOUNTER StatIntInject;
278
279	STAMCOUNTER StatExitShadowNM;
280	STAMCOUNTER StatExitGuestNM;
281	STAMCOUNTER StatExitShadowPF;
282	STAMCOUNTER StatExitGuestPF;
283	STAMCOUNTER StatExitGuestUD;
284	STAMCOUNTER StatExitGuestSS;
285	STAMCOUNTER StatExitGuestNP;
286	STAMCOUNTER StatExitGuestGP;
287	STAMCOUNTER StatExitGuestDE;
288	STAMCOUNTER StatExitGuestMF;
289	STAMCOUNTER StatExitInvpg;
290	STAMCOUNTER StatExitInvd;
291	STAMCOUNTER StatExitCpuid;
292	STAMCOUNTER StatExitRdtsc;
293	STAMCOUNTER StatExitCRxWrite;
294	STAMCOUNTER StatExitCRxRead;
295	STAMCOUNTER StatExitDRxWrite;
296	STAMCOUNTER StatExitDRxRead;
297	STAMCOUNTER StatExitCLTS;
298	STAMCOUNTER StatExitLMSW;
299	STAMCOUNTER StatExitIOWrite;
300	STAMCOUNTER StatExitIORead;
301	STAMCOUNTER StatExitIOStringWrite;
302	STAMCOUNTER StatExitIOStringRead;
303	STAMCOUNTER StatExitIrqWindow;
304	STAMCOUNTER StatExitMaxResume;
305	STAMCOUNTER StatIntReinject;
306	STAMCOUNTER StatPendingHostIrq;
307
308	STAMCOUNTER StatSwitchGuestIrq;
309	STAMCOUNTER StatSwitchToR3;
310
311	R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
312	R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
313	} HWACCM;
314	/** Pointer to HWACCM VM instance data. */
315	typedef HWACCM *PHWACCM;
316
317
318	#ifdef IN_RING0
319
320	#ifdef VBOX_STRICT
321	HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx);
322	HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
323	#else
324	#define HWACCMDumpRegs(a) do { } while (0)
325	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
326	#endif
327
328	#endif
329
330	/** @} */
331
332	__END_DECLS
333
334	#endif
335

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 8842

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