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1	/* $Id: PGM.cpp 8454 2008-04-29 11:31:44Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	*
26	*
27	* @section sec_pgm_modes Paging Modes
28	*
29	* There are three memory contexts: Host Context (HC), Guest Context (GC)
30	* and intermediate context. When talking about paging HC can also be refered to
31	* as "host paging", and GC refered to as "shadow paging".
32	*
33	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
34	* is defined by the host operating system. The mode used in the shadow paging mode
35	* depends on the host paging mode and what the mode the guest is currently in. The
36	* following relation between the two is defined:
37	*
38	* @verbatim
39	Host > 32-bit \| PAE \| AMD64 \|
40	Guest \| \| \| \|
41	==v================================
42	32-bit 32-bit PAE PAE
43	-------\|--------\|--------\|--------\|
44	PAE PAE PAE PAE
45	-------\|--------\|--------\|--------\|
46	AMD64 AMD64 AMD64 AMD64
47	-------\|--------\|--------\|--------\| @endverbatim
48	*
49	* All configuration except those in the diagonal (upper left) are expected to
50	* require special effort from the switcher (i.e. a bit slower).
51	*
52	*
53	*
54	*
55	* @section sec_pgm_shw The Shadow Memory Context
56	*
57	*
58	* [..]
59	*
60	* Because of guest context mappings requires PDPT and PML4 entries to allow
61	* writing on AMD64, the two upper levels will have fixed flags whatever the
62	* guest is thinking of using there. So, when shadowing the PD level we will
63	* calculate the effective flags of PD and all the higher levels. In legacy
64	* PAE mode this only applies to the PWT and PCD bits (the rest are
65	* ignored/reserved/MBZ). We will ignore those bits for the present.
66	*
67	*
68	*
69	* @section sec_pgm_int The Intermediate Memory Context
70	*
71	* The world switch goes thru an intermediate memory context which purpose it is
72	* to provide different mappings of the switcher code. All guest mappings are also
73	* present in this context.
74	*
75	* The switcher code is mapped at the same location as on the host, at an
76	* identity mapped location (physical equals virtual address), and at the
77	* hypervisor location.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successfull this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgmPhys PGMPhys - Physical Guest Memory Management.
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery assoicated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attemted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separeate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the otherway around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
484	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
485	* memory context for the HWACCM execution.
486	*
487	*
488	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
489	*
490	* We've considered implementing the ring-3 mapping cache page based but found
491	* that this was bother some when one had to take into account TLBs+SMP and
492	* portability (missing the necessary APIs on several platforms). There were
493	* also some performance concerns with this approach which hadn't quite been
494	* worked out.
495	*
496	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
497	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
498	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
499	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
500	* costly than a single page, although how much more costly is uncertain. We'll
501	* try address this by using a very big cache, preferably bigger than the actual
502	* VM RAM size if possible. The current VM RAM sizes should give some idea for
503	* 32-bit boxes, while on 64-bit we can probably get away with employing an
504	* unlimited cache.
505	*
506	* The cache have to parts, as already indicated, the ring-3 side and the
507	* ring-0 side.
508	*
509	* The ring-0 will be tied to the page allocator since it will operate on the
510	* memory objects it contains. It will therefore require the first ring-0 mutex
511	* discussed in @ref subsec_pgmPhys_Serializing. We
512	* some double house keeping wrt to who has mapped what I think, since both
513	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
514	*
515	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
516	* require anyone that desires to do changes to the mapping cache to do that
517	* from within this critsect. Alternatively, we could employ a separate critsect
518	* for serializing changes to the mapping cache as this would reduce potential
519	* contention with other threads accessing mappings unrelated to the changes
520	* that are in process. We can see about this later, contention will show
521	* up in the statistics anyway, so it'll be simple to tell.
522	*
523	* The organization of the ring-3 part will be very much like how the allocation
524	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
525	* having to walk the tree all the time, we'll have a couple of lookaside entries
526	* like in we do for I/O ports and MMIO in IOM.
527	*
528	* The simplified flow of a PGMPhysRead/Write function:
529	* -# Enter the PGM critsect.
530	* -# Lookup GCPhys in the ram ranges and get the Page ID.
531	* -# Calc the Allocation Chunk ID from the Page ID.
532	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
533	* If not found in cache:
534	* -# Call ring-0 and request it to be mapped and supply
535	* a chunk to be unmapped if the cache is maxed out already.
536	* -# Insert the new mapping into the AVL tree (id + R3 address).
537	* -# Update the relevant lookaside entry and return the mapping address.
538	* -# Do the read/write according to monitoring flags and everything.
539	* -# Leave the critsect.
540	*
541	*
542	* @section sec_pgmPhys_Fallback Fallback
543	*
544	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
545	* API and thus require a fallback.
546	*
547	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
548	* will return to the ring-3 caller (and later ring-0) and asking it to seed
549	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
550	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
551	* "SeededAllocPages" call to ring-0.
552	*
553	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
554	* all page sharing (zero page detection will continue). It will also force
555	* all allocations to come from the VM which seeded the page. Both these
556	* measures are taken to make sure that there will never be any need for
557	* mapping anything into ring-3 - everything will be mapped already.
558	*
559	* Whether we'll continue to use the current MM locked memory management
560	* for this I don't quite know (I'd prefer not to and just ditch that all
561	* togther), we'll see what's simplest to do.
562	*
563	*
564	*
565	* @section sec_pgmPhys_Changes Changes
566	*
567	* Breakdown of the changes involved?
568	*/
569
570
571	/** Saved state data unit version. */
572	#define PGM_SAVED_STATE_VERSION 6
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include "PGMInternal.h"
592	#include <VBox/vm.h>
593	#include <VBox/dbg.h>
594	#include <VBox/hwaccm.h>
595
596	#include <iprt/assert.h>
597	#include <iprt/alloc.h>
598	#include <iprt/asm.h>
599	#include <iprt/thread.h>
600	#include <iprt/string.h>
601	#include <VBox/param.h>
602	#include <VBox/err.h>
603
604
605
606	/*******************************************************************************
607	* Internal Functions *
608	*******************************************************************************/
609	static int pgmR3InitPaging(PVM pVM);
610	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
611	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
612	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
613	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
614	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
615	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
616	#ifdef VBOX_STRICT
617	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
618	#endif
619	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
620	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
621	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
622	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
623	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
624
625	#ifdef VBOX_WITH_STATISTICS
626	static void pgmR3InitStats(PVM pVM);
627	#endif
628
629	#ifdef VBOX_WITH_DEBUGGER
630	/** @todo all but the two last commands must be converted to 'info'. */
631	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
632	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
633	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
634	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
635	#endif
636
637
638	/*******************************************************************************
639	* Global Variables *
640	*******************************************************************************/
641	#ifdef VBOX_WITH_DEBUGGER
642	/** Command descriptors. */
643	static const DBGCCMD g_aCmds[] =
644	{
645	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
646	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
647	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
648	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
649	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
650	};
651	#endif
652
653
654
655
656	#if 1/// @todo ndef RT_ARCH_AMD64
657	/*
658	* Shadow - 32-bit mode
659	*/
660	#define PGM_SHW_TYPE PGM_TYPE_32BIT
661	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
662	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
663	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
664	#include "PGMShw.h"
665
666	/* Guest - real mode */
667	#define PGM_GST_TYPE PGM_TYPE_REAL
668	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
669	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
670	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
671	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
672	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
673	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
674	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
675	#include "PGMGst.h"
676	#include "PGMBth.h"
677	#undef BTH_PGMPOOLKIND_PT_FOR_PT
678	#undef PGM_BTH_NAME
679	#undef PGM_BTH_NAME_GC_STR
680	#undef PGM_BTH_NAME_R0_STR
681	#undef PGM_GST_TYPE
682	#undef PGM_GST_NAME
683	#undef PGM_GST_NAME_GC_STR
684	#undef PGM_GST_NAME_R0_STR
685
686	/* Guest - protected mode */
687	#define PGM_GST_TYPE PGM_TYPE_PROT
688	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
689	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
690	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
691	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
692	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
693	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
694	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
695	#include "PGMGst.h"
696	#include "PGMBth.h"
697	#undef BTH_PGMPOOLKIND_PT_FOR_PT
698	#undef PGM_BTH_NAME
699	#undef PGM_BTH_NAME_GC_STR
700	#undef PGM_BTH_NAME_R0_STR
701	#undef PGM_GST_TYPE
702	#undef PGM_GST_NAME
703	#undef PGM_GST_NAME_GC_STR
704	#undef PGM_GST_NAME_R0_STR
705
706	/* Guest - 32-bit mode */
707	#define PGM_GST_TYPE PGM_TYPE_32BIT
708	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
709	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
710	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
711	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
712	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
713	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
714	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
715	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
716	#include "PGMGst.h"
717	#include "PGMBth.h"
718	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
719	#undef BTH_PGMPOOLKIND_PT_FOR_PT
720	#undef PGM_BTH_NAME
721	#undef PGM_BTH_NAME_GC_STR
722	#undef PGM_BTH_NAME_R0_STR
723	#undef PGM_GST_TYPE
724	#undef PGM_GST_NAME
725	#undef PGM_GST_NAME_GC_STR
726	#undef PGM_GST_NAME_R0_STR
727
728	#undef PGM_SHW_TYPE
729	#undef PGM_SHW_NAME
730	#undef PGM_SHW_NAME_GC_STR
731	#undef PGM_SHW_NAME_R0_STR
732	#endif /* !RT_ARCH_AMD64 */
733
734
735	/*
736	* Shadow - PAE mode
737	*/
738	#define PGM_SHW_TYPE PGM_TYPE_PAE
739	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
740	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
741	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
742	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
743	#include "PGMShw.h"
744
745	/* Guest - real mode */
746	#define PGM_GST_TYPE PGM_TYPE_REAL
747	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
748	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
749	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
750	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
751	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
752	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
753	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
754	#include "PGMBth.h"
755	#undef BTH_PGMPOOLKIND_PT_FOR_PT
756	#undef PGM_BTH_NAME
757	#undef PGM_BTH_NAME_GC_STR
758	#undef PGM_BTH_NAME_R0_STR
759	#undef PGM_GST_TYPE
760	#undef PGM_GST_NAME
761	#undef PGM_GST_NAME_GC_STR
762	#undef PGM_GST_NAME_R0_STR
763
764	/* Guest - protected mode */
765	#define PGM_GST_TYPE PGM_TYPE_PROT
766	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
767	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
768	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
769	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
770	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
771	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
772	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
773	#include "PGMBth.h"
774	#undef BTH_PGMPOOLKIND_PT_FOR_PT
775	#undef PGM_BTH_NAME
776	#undef PGM_BTH_NAME_GC_STR
777	#undef PGM_BTH_NAME_R0_STR
778	#undef PGM_GST_TYPE
779	#undef PGM_GST_NAME
780	#undef PGM_GST_NAME_GC_STR
781	#undef PGM_GST_NAME_R0_STR
782
783	/* Guest - 32-bit mode */
784	#define PGM_GST_TYPE PGM_TYPE_32BIT
785	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
786	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
787	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
788	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
789	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
790	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
791	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
792	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
793	#include "PGMBth.h"
794	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
795	#undef BTH_PGMPOOLKIND_PT_FOR_PT
796	#undef PGM_BTH_NAME
797	#undef PGM_BTH_NAME_GC_STR
798	#undef PGM_BTH_NAME_R0_STR
799	#undef PGM_GST_TYPE
800	#undef PGM_GST_NAME
801	#undef PGM_GST_NAME_GC_STR
802	#undef PGM_GST_NAME_R0_STR
803
804	/* Guest - PAE mode */
805	#define PGM_GST_TYPE PGM_TYPE_PAE
806	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
807	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
808	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
809	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
810	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
811	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
812	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
813	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
814	#include "PGMGst.h"
815	#include "PGMBth.h"
816	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
817	#undef BTH_PGMPOOLKIND_PT_FOR_PT
818	#undef PGM_BTH_NAME
819	#undef PGM_BTH_NAME_GC_STR
820	#undef PGM_BTH_NAME_R0_STR
821	#undef PGM_GST_TYPE
822	#undef PGM_GST_NAME
823	#undef PGM_GST_NAME_GC_STR
824	#undef PGM_GST_NAME_R0_STR
825
826	#undef PGM_SHW_TYPE
827	#undef PGM_SHW_NAME
828	#undef PGM_SHW_NAME_GC_STR
829	#undef PGM_SHW_NAME_R0_STR
830
831
832	/*
833	* Shadow - AMD64 mode
834	*/
835	#define PGM_SHW_TYPE PGM_TYPE_AMD64
836	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
837	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
838	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
839	#include "PGMShw.h"
840
841	/* Guest - AMD64 mode */
842	#define PGM_GST_TYPE PGM_TYPE_AMD64
843	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
844	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
845	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
846	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
847	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
848	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
849	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
850	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
851	#include "PGMGst.h"
852	#include "PGMBth.h"
853	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
854	#undef BTH_PGMPOOLKIND_PT_FOR_PT
855	#undef PGM_BTH_NAME
856	#undef PGM_BTH_NAME_GC_STR
857	#undef PGM_BTH_NAME_R0_STR
858	#undef PGM_GST_TYPE
859	#undef PGM_GST_NAME
860	#undef PGM_GST_NAME_GC_STR
861	#undef PGM_GST_NAME_R0_STR
862
863	#undef PGM_SHW_TYPE
864	#undef PGM_SHW_NAME
865	#undef PGM_SHW_NAME_GC_STR
866	#undef PGM_SHW_NAME_R0_STR
867
868
869	/**
870	* Initiates the paging of VM.
871	*
872	* @returns VBox status code.
873	* @param pVM Pointer to VM structure.
874	*/
875	PGMR3DECL(int) PGMR3Init(PVM pVM)
876	{
877	LogFlow(("PGMR3Init:\n"));
878
879	/*
880	* Assert alignment and sizes.
881	*/
882	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
883
884	/*
885	* Init the structure.
886	*/
887	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
888	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
889	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
890	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
891	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
892	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
893	pVM->pgm.s.fA20Enabled = true;
894	pVM->pgm.s.pGstPaePDPTHC = NULL;
895	pVM->pgm.s.pGstPaePDPTGC = 0;
896	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
897	{
898	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
899	pVM->pgm.s.apGstPaePDsGC[i] = 0;
900	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
901	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
902	}
903
904	#ifdef VBOX_STRICT
905	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
906	#endif
907
908	/*
909	* Get the configured RAM size - to estimate saved state size.
910	*/
911	uint64_t cbRam;
912	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
913	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
914	cbRam = pVM->pgm.s.cbRamSize = 0;
915	else if (VBOX_SUCCESS(rc))
916	{
917	if (cbRam < PAGE_SIZE)
918	cbRam = 0;
919	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
920	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
921	}
922	else
923	{
924	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
925	return rc;
926	}
927
928	/*
929	* Register saved state data unit.
930	*/
931	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
932	NULL, pgmR3Save, NULL,
933	NULL, pgmR3Load, NULL);
934	if (VBOX_FAILURE(rc))
935	return rc;
936
937	/*
938	* Initialize the PGM critical section and flush the phys TLBs
939	*/
940	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
941	AssertRCReturn(rc, rc);
942
943	PGMR3PhysChunkInvalidateTLB(pVM);
944	PGMPhysInvalidatePageR3MapTLB(pVM);
945	PGMPhysInvalidatePageR0MapTLB(pVM);
946	PGMPhysInvalidatePageGCMapTLB(pVM);
947
948	/*
949	* Trees
950	*/
951	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
952	if (VBOX_SUCCESS(rc))
953	{
954	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
955
956	/*
957	* Alocate the zero page.
958	*/
959	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
960	}
961	if (VBOX_SUCCESS(rc))
962	{
963	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToGC(pVM, pVM->pgm.s.pvZeroPgR3);
964	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
965	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
966	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
967	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
968
969	/*
970	* Init the paging.
971	*/
972	rc = pgmR3InitPaging(pVM);
973	}
974	if (VBOX_SUCCESS(rc))
975	{
976	/*
977	* Init the page pool.
978	*/
979	rc = pgmR3PoolInit(pVM);
980	}
981	if (VBOX_SUCCESS(rc))
982	{
983	/*
984	* Info & statistics
985	*/
986	DBGFR3InfoRegisterInternal(pVM, "mode",
987	"Shows the current paging mode. "
988	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
989	pgmR3InfoMode);
990	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
991	"Dumps all the entries in the top level paging table. No arguments.",
992	pgmR3InfoCr3);
993	DBGFR3InfoRegisterInternal(pVM, "phys",
994	"Dumps all the physical address ranges. No arguments.",
995	pgmR3PhysInfo);
996	DBGFR3InfoRegisterInternal(pVM, "handlers",
997	"Dumps physical, virtual and hyper virtual handlers. "
998	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
999	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1000	pgmR3InfoHandlers);
1001	DBGFR3InfoRegisterInternal(pVM, "mappings",
1002	"Dumps guest mappings.",
1003	pgmR3MapInfo);
1004
1005	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1006	#ifdef VBOX_WITH_STATISTICS
1007	pgmR3InitStats(pVM);
1008	#endif
1009	#ifdef VBOX_WITH_DEBUGGER
1010	/*
1011	* Debugger commands.
1012	*/
1013	static bool fRegisteredCmds = false;
1014	if (!fRegisteredCmds)
1015	{
1016	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
1017	if (VBOX_SUCCESS(rc))
1018	fRegisteredCmds = true;
1019	}
1020	#endif
1021	return VINF_SUCCESS;
1022	}
1023
1024	/* Almost no cleanup necessary, MM frees all memory. */
1025	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1026
1027	return rc;
1028	}
1029
1030
1031	/**
1032	* Init paging.
1033	*
1034	* Since we need to check what mode the host is operating in before we can choose
1035	* the right paging functions for the host we have to delay this until R0 has
1036	* been initialized.
1037	*
1038	* @returns VBox status code.
1039	* @param pVM VM handle.
1040	*/
1041	static int pgmR3InitPaging(PVM pVM)
1042	{
1043	/*
1044	* Force a recalculation of modes and switcher so everyone gets notified.
1045	*/
1046	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1047	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1048	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1049
1050	/*
1051	* Allocate static mapping space for whatever the cr3 register
1052	* points to and in the case of PAE mode to the 4 PDs.
1053	*/
1054	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1055	if (VBOX_FAILURE(rc))
1056	{
1057	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1058	return rc;
1059	}
1060	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1061
1062	/*
1063	* Allocate pages for the three possible intermediate contexts
1064	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1065	* for the sake of simplicity. The AMD64 uses the PAE for the
1066	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1067	*
1068	* We assume that two page tables will be enought for the core code
1069	* mappings (HC virtual and identity).
1070	*/
1071	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1072	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1073	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1074	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1075	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1076	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1077	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1078	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1079	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1080	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1081	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1082	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1083	if ( !pVM->pgm.s.pInterPD
1084	\|\| !pVM->pgm.s.apInterPTs[0]
1085	\|\| !pVM->pgm.s.apInterPTs[1]
1086	\|\| !pVM->pgm.s.apInterPaePTs[0]
1087	\|\| !pVM->pgm.s.apInterPaePTs[1]
1088	\|\| !pVM->pgm.s.apInterPaePDs[0]
1089	\|\| !pVM->pgm.s.apInterPaePDs[1]
1090	\|\| !pVM->pgm.s.apInterPaePDs[2]
1091	\|\| !pVM->pgm.s.apInterPaePDs[3]
1092	\|\| !pVM->pgm.s.pInterPaePDPT
1093	\|\| !pVM->pgm.s.pInterPaePDPT64
1094	\|\| !pVM->pgm.s.pInterPaePML4)
1095	{
1096	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1097	return VERR_NO_PAGE_MEMORY;
1098	}
1099
1100	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1101	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1102	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1103	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1104	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1105	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1106
1107	/*
1108	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1109	*/
1110	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1111	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1112	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1113
1114	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1115	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1116
1117	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1118	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1119	{
1120	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1121	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1122	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1123	}
1124
1125	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1126	{
1127	const unsigned iPD = i % ELEMENTS(pVM->pgm.s.apInterPaePDs);
1128	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1129	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1130	}
1131
1132	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1133	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1134	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1135	\| HCPhysInterPaePDPT64;
1136
1137	/*
1138	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1139	* We allocate pages for all three posibilities to in order to simplify mappings and
1140	* avoid resource failure during mode switches. So, we need to cover all levels of the
1141	* of the first 4GB down to PD level.
1142	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1143	*/
1144	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1145	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1146	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1147	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1148	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1149	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1150	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1151	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1152	pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1153	pVM->pgm.s.pHCPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1154	if ( !pVM->pgm.s.pHC32BitPD
1155	\|\| !pVM->pgm.s.apHCPaePDs[0]
1156	\|\| !pVM->pgm.s.apHCPaePDs[1]
1157	\|\| !pVM->pgm.s.apHCPaePDs[2]
1158	\|\| !pVM->pgm.s.apHCPaePDs[3]
1159	\|\| !pVM->pgm.s.pHCPaePDPT
1160	\|\| !pVM->pgm.s.pHCPaePML4)
1161	{
1162	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1163	return VERR_NO_PAGE_MEMORY;
1164	}
1165
1166	/* get physical addresses. */
1167	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1168	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1169	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1170	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1171	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1172	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1173	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
1174	pVM->pgm.s.HCPhysPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePML4);
1175
1176	/*
1177	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1178	*/
1179	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1180
1181	ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
1182	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1183	{
1184	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1185	pVM->pgm.s.pHCPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1186	/* The flags will be corrected when entering and leaving long mode. */
1187	}
1188
1189	ASMMemZero32(pVM->pgm.s.pHCPaePML4, PAGE_SIZE);
1190	pVM->pgm.s.pHCPaePML4->a[0].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_A
1191	\| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.HCPhysPaePDPT;
1192
1193	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1194
1195	/*
1196	* Initialize paging workers and mode from current host mode
1197	* and the guest running in real mode.
1198	*/
1199	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1200	switch (pVM->pgm.s.enmHostMode)
1201	{
1202	case SUPPAGINGMODE_32_BIT:
1203	case SUPPAGINGMODE_32_BIT_GLOBAL:
1204	case SUPPAGINGMODE_PAE:
1205	case SUPPAGINGMODE_PAE_GLOBAL:
1206	case SUPPAGINGMODE_PAE_NX:
1207	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1208	break;
1209
1210	case SUPPAGINGMODE_AMD64:
1211	case SUPPAGINGMODE_AMD64_GLOBAL:
1212	case SUPPAGINGMODE_AMD64_NX:
1213	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1214	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1215	if (ARCH_BITS != 64)
1216	{
1217	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1218	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1219	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1220	}
1221	#endif
1222	break;
1223	default:
1224	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1225	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1226	}
1227	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1228	if (VBOX_SUCCESS(rc))
1229	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
1230	if (VBOX_SUCCESS(rc))
1231	{
1232	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1233	#if HC_ARCH_BITS == 64
1234	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPT=%VHp HCPhysPaePML4=%VHp\n",
1235	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1236	pVM->pgm.s.HCPhysPaePDPT, pVM->pgm.s.HCPhysPaePML4));
1237	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPT=%VHp HCPhysInterPaePML4=%VHp\n",
1238	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1239	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPT64=%VHp\n",
1240	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1241	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1242	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1243	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1244	#endif
1245
1246	return VINF_SUCCESS;
1247	}
1248
1249	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1250	return rc;
1251	}
1252
1253
1254	#ifdef VBOX_WITH_STATISTICS
1255	/**
1256	* Init statistics
1257	*/
1258	static void pgmR3InitStats(PVM pVM)
1259	{
1260	PPGM pPGM = &pVM->pgm.s;
1261	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1262	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
1263	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
1264	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
1265	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1266	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
1267	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
1268	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1269	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1270	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
1271	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1272	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1273	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1274	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1275	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1276	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1277	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1278	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1279	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1280	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
1281	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
1282	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
1283
1284	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
1285	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1286	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1287	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1288	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1289	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1290	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
1291	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1292	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1293	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1294	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1295	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1296	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1297	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1298	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1299	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1300	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1301	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1302	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1303
1304	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1305	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1306	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1307	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1308	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1309	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1310	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1311
1312	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1313	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1314	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1315	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1316	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1317	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1318	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1319
1320	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1321	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1322	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1323	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1324	STAM_REG(pVM, &pPGM->StatGCTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1325	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
1326	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
1327
1328	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulGC, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/InGC", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1329	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulR3, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1330
1331	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1332	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1333	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1334
1335	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1336	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1337
1338	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1339	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1340
1341	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1342	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1343
1344	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1345	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1346	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1347
1348	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
1349	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
1350	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
1351	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
1352	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1353	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
1354	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
1355	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1356	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1357	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1358	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
1359
1360	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
1361	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1362	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1363	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1364	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1365	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1366	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1367
1368	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1369	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1370	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1371	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1372
1373	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1374	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1375	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1376	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1377	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1378
1379	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1380	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1381	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1382	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1383	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1384	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1385	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1386	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1387	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1388	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1389	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1390	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1391
1392	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1393	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1394	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1395	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1396	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1397	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1398	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1399	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1400	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1401	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1402	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1403	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1404
1405	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
1406	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
1407	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
1408
1409	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1410	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1411
1412	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1413	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1414	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1415	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1416
1417	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
1418	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1419
1420	STAM_REG(pVM, &pPGM->StatPageHCMapTlbHits, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1421	STAM_REG(pVM, &pPGM->StatPageHCMapTlbMisses, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1422	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1423	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1424	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1425	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1426	STAM_REG(pVM, &pPGM->StatPageReplaceShared, STAMTYPE_COUNTER, "/PGM/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1427	STAM_REG(pVM, &pPGM->StatPageReplaceZero, STAMTYPE_COUNTER, "/PGM/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1428	STAM_REG(pVM, &pPGM->StatPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1429	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1430	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1431	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1432	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1433
1434	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1435	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1436	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1437	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1438	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1439	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1440	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1441	#endif
1442
1443	for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1444	{
1445	/** @todo r=bird: We need a STAMR3RegisterF()! */
1446	char szName[32];
1447
1448	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
1449	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
1450	AssertRC(rc);
1451
1452	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
1453	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
1454	AssertRC(rc);
1455
1456	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
1457	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
1458	AssertRC(rc);
1459	}
1460	}
1461	#endif /* VBOX_WITH_STATISTICS */
1462
1463	/**
1464	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1465	*
1466	* The dynamic mapping area will also be allocated and initialized at this
1467	* time. We could allocate it during PGMR3Init of course, but the mapping
1468	* wouldn't be allocated at that time preventing us from setting up the
1469	* page table entries with the dummy page.
1470	*
1471	* @returns VBox status code.
1472	* @param pVM VM handle.
1473	*/
1474	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1475	{
1476	/*
1477	* Reserve space for mapping the paging pages into guest context.
1478	*/
1479	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &pVM->pgm.s.pGC32BitPD);
1480	AssertRCReturn(rc, rc);
1481	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1482
1483	/*
1484	* Reserve space for the dynamic mappings.
1485	*/
1486	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1487	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &pVM->pgm.s.pbDynPageMapBaseGC);
1488	if ( VBOX_SUCCESS(rc)
1489	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT))
1490	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &pVM->pgm.s.pbDynPageMapBaseGC);
1491	if (VBOX_SUCCESS(rc))
1492	{
1493	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT));
1494	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1495	}
1496	return rc;
1497	}
1498
1499
1500	/**
1501	* Ring-3 init finalizing.
1502	*
1503	* @returns VBox status code.
1504	* @param pVM The VM handle.
1505	*/
1506	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1507	{
1508	/*
1509	* Map the paging pages into the guest context.
1510	*/
1511	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1512	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1513
1514	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1515	AssertRCReturn(rc, rc);
1516	pVM->pgm.s.pGC32BitPD = GCPtr;
1517	GCPtr += PAGE_SIZE;
1518	GCPtr += PAGE_SIZE; /* reserved page */
1519
1520	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1521	{
1522	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1523	AssertRCReturn(rc, rc);
1524	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1525	GCPtr += PAGE_SIZE;
1526	}
1527	/* A bit of paranoia is justified. */
1528	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1529	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1530	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1531	GCPtr += PAGE_SIZE; /* reserved page */
1532
1533	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1534	AssertRCReturn(rc, rc);
1535	pVM->pgm.s.pGCPaePDPT = GCPtr;
1536	GCPtr += PAGE_SIZE;
1537	GCPtr += PAGE_SIZE; /* reserved page */
1538
1539
1540	/*
1541	* Reserve space for the dynamic mappings.
1542	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1543	*/
1544	/* get the pointer to the page table entries. */
1545	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1546	AssertRelease(pMapping);
1547	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1548	const unsigned iPT = off >> X86_PD_SHIFT;
1549	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1550	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1551	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1552
1553	/* init cache */
1554	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1555	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1556	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1557
1558	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1559	{
1560	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1561	AssertRCReturn(rc, rc);
1562	}
1563
1564	return rc;
1565	}
1566
1567
1568	/**
1569	* Applies relocations to data and code managed by this
1570	* component. This function will be called at init and
1571	* whenever the VMM need to relocate it self inside the GC.
1572	*
1573	* @param pVM The VM.
1574	* @param offDelta Relocation delta relative to old location.
1575	*/
1576	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1577	{
1578	LogFlow(("PGMR3Relocate\n"));
1579
1580	/*
1581	* Paging stuff.
1582	*/
1583	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1584	/** @todo move this into shadow and guest specific relocation functions. */
1585	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1586	pVM->pgm.s.pGC32BitPD += offDelta;
1587	pVM->pgm.s.pGuestPDGC += offDelta;
1588	AssertCompile(ELEMENTS(pVM->pgm.s.apGCPaePDs) == ELEMENTS(pVM->pgm.s.apGstPaePDsGC));
1589	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1590	{
1591	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1592	pVM->pgm.s.apGstPaePDsGC[i] += offDelta;
1593	}
1594	pVM->pgm.s.pGstPaePDPTGC += offDelta;
1595	pVM->pgm.s.pGCPaePDPT += offDelta;
1596
1597	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1598	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1599
1600	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1601	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1602	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1603
1604	/*
1605	* Trees.
1606	*/
1607	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1608
1609	/*
1610	* Ram ranges.
1611	*/
1612	if (pVM->pgm.s.pRamRangesR3)
1613	{
1614	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesR3);
1615	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1616	#ifdef VBOX_WITH_NEW_PHYS_CODE
1617	pCur->pNextGC = MMHyperR3ToGC(pVM, pCur->pNextR3);
1618	#else
1619	{
1620	pCur->pNextGC = MMHyperR3ToGC(pVM, pCur->pNextR3);
1621	if (pCur->pavHCChunkGC)
1622	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1623	}
1624	#endif
1625	}
1626
1627	/*
1628	* Update the two page directories with all page table mappings.
1629	* (One or more of them have changed, that's why we're here.)
1630	*/
1631	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsR3);
1632	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1633	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextR3);
1634
1635	/* Relocate GC addresses of Page Tables. */
1636	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1637	{
1638	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1639	{
1640	pCur->aPTs[i].pPTGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].pPTR3);
1641	pCur->aPTs[i].paPaePTsGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].paPaePTsR3);
1642	}
1643	}
1644
1645	/*
1646	* Dynamic page mapping area.
1647	*/
1648	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1649	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1650	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1651
1652	/*
1653	* The Zero page.
1654	*/
1655	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1656	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1657
1658	/*
1659	* Physical and virtual handlers.
1660	*/
1661	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1662	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1663	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1664
1665	/*
1666	* The page pool.
1667	*/
1668	pgmR3PoolRelocate(pVM);
1669	}
1670
1671
1672	/**
1673	* Callback function for relocating a physical access handler.
1674	*
1675	* @returns 0 (continue enum)
1676	* @param pNode Pointer to a PGMPHYSHANDLER node.
1677	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1678	* not certain the delta will fit in a void pointer for all possible configs.
1679	*/
1680	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1681	{
1682	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1683	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1684	if (pHandler->pfnHandlerGC)
1685	pHandler->pfnHandlerGC += offDelta;
1686	if ((RTGCUINTPTR)pHandler->pvUserGC >= 0x10000)
1687	pHandler->pvUserGC += offDelta;
1688	return 0;
1689	}
1690
1691
1692	/**
1693	* Callback function for relocating a virtual access handler.
1694	*
1695	* @returns 0 (continue enum)
1696	* @param pNode Pointer to a PGMVIRTHANDLER node.
1697	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1698	* not certain the delta will fit in a void pointer for all possible configs.
1699	*/
1700	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1701	{
1702	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1703	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1704	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
1705	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
1706	Assert(pHandler->pfnHandlerGC);
1707	pHandler->pfnHandlerGC += offDelta;
1708	return 0;
1709	}
1710
1711
1712	/**
1713	* Callback function for relocating a virtual access handler for the hypervisor mapping.
1714	*
1715	* @returns 0 (continue enum)
1716	* @param pNode Pointer to a PGMVIRTHANDLER node.
1717	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1718	* not certain the delta will fit in a void pointer for all possible configs.
1719	*/
1720	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1721	{
1722	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1723	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1724	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
1725	Assert(pHandler->pfnHandlerGC);
1726	pHandler->pfnHandlerGC += offDelta;
1727	return 0;
1728	}
1729
1730
1731	/**
1732	* The VM is being reset.
1733	*
1734	* For the PGM component this means that any PD write monitors
1735	* needs to be removed.
1736	*
1737	* @param pVM VM handle.
1738	*/
1739	PGMR3DECL(void) PGMR3Reset(PVM pVM)
1740	{
1741	LogFlow(("PGMR3Reset:\n"));
1742	VM_ASSERT_EMT(pVM);
1743
1744	pgmLock(pVM);
1745
1746	/*
1747	* Unfix any fixed mappings and disable CR3 monitoring.
1748	*/
1749	pVM->pgm.s.fMappingsFixed = false;
1750	pVM->pgm.s.GCPtrMappingFixed = 0;
1751	pVM->pgm.s.cbMappingFixed = 0;
1752
1753	int rc = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
1754	AssertRC(rc);
1755	#ifdef DEBUG
1756	DBGFR3InfoLog(pVM, "mappings", NULL);
1757	DBGFR3InfoLog(pVM, "handlers", "all nostat");
1758	#endif
1759
1760	/*
1761	* Reset the shadow page pool.
1762	*/
1763	pgmR3PoolReset(pVM);
1764
1765	/*
1766	* Re-init other members.
1767	*/
1768	pVM->pgm.s.fA20Enabled = true;
1769
1770	/*
1771	* Clear the FFs PGM owns.
1772	*/
1773	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1774	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1775
1776	/*
1777	* Reset (zero) RAM pages.
1778	*/
1779	rc = pgmR3PhysRamReset(pVM);
1780	if (RT_SUCCESS(rc))
1781	{
1782	#ifdef VBOX_WITH_NEW_PHYS_CODE
1783	/*
1784	* Reset (zero) shadow ROM pages.
1785	*/
1786	rc = pgmR3PhysRomReset(pVM);
1787	#endif
1788	if (RT_SUCCESS(rc))
1789	{
1790	/*
1791	* Switch mode back to real mode.
1792	*/
1793	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
1794	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
1795	}
1796	}
1797
1798	pgmUnlock(pVM);
1799	//return rc;
1800	AssertReleaseRC(rc);
1801	}
1802
1803
1804	#ifdef VBOX_STRICT
1805	/**
1806	* VM state change callback for clearing fNoMorePhysWrites after
1807	* a snapshot has been created.
1808	*/
1809	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
1810	{
1811	if (enmState == VMSTATE_RUNNING)
1812	pVM->pgm.s.fNoMorePhysWrites = false;
1813	}
1814	#endif
1815
1816
1817	/**
1818	* Terminates the PGM.
1819	*
1820	* @returns VBox status code.
1821	* @param pVM Pointer to VM structure.
1822	*/
1823	PGMR3DECL(int) PGMR3Term(PVM pVM)
1824	{
1825	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1826	}
1827
1828
1829	/**
1830	* Execute state save operation.
1831	*
1832	* @returns VBox status code.
1833	* @param pVM VM Handle.
1834	* @param pSSM SSM operation handle.
1835	*/
1836	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
1837	{
1838	PPGM pPGM = &pVM->pgm.s;
1839
1840	/* No more writes to physical memory after this point! */
1841	pVM->pgm.s.fNoMorePhysWrites = true;
1842
1843	/*
1844	* Save basic data (required / unaffected by relocation).
1845	*/
1846	#if 1
1847	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
1848	#else
1849	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
1850	#endif
1851	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
1852	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
1853	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
1854	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
1855	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
1856	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
1857	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
1858	SSMR3PutU32(pSSM, ~0); /* Separator. */
1859
1860	/*
1861	* The guest mappings.
1862	*/
1863	uint32_t i = 0;
1864	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1865	{
1866	SSMR3PutU32(pSSM, i);
1867	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1868	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
1869	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1870	/* flags are done by the mapping owners! */
1871	}
1872	SSMR3PutU32(pSSM, ~0); /* terminator. */
1873
1874	/*
1875	* Ram range flags and bits.
1876	*/
1877	i = 0;
1878	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
1879	{
1880	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1881
1882	SSMR3PutU32(pSSM, i);
1883	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
1884	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
1885	SSMR3PutGCPhys(pSSM, pRam->cb);
1886	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
1887
1888	/* Flags. */
1889	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1890	for (unsigned iPage = 0; iPage < cPages; iPage++)
1891	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
1892
1893	/* any memory associated with the range. */
1894	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1895	{
1896	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1897	{
1898	if (pRam->pavHCChunkHC[iChunk])
1899	{
1900	SSMR3PutU8(pSSM, 1); /* chunk present */
1901	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1902	}
1903	else
1904	SSMR3PutU8(pSSM, 0); /* no chunk present */
1905	}
1906	}
1907	else if (pRam->pvHC)
1908	{
1909	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
1910	if (VBOX_FAILURE(rc))
1911	{
1912	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1913	return rc;
1914	}
1915	}
1916	}
1917	return SSMR3PutU32(pSSM, ~0); /* terminator. */
1918	}
1919
1920
1921	/**
1922	* Execute state load operation.
1923	*
1924	* @returns VBox status code.
1925	* @param pVM VM Handle.
1926	* @param pSSM SSM operation handle.
1927	* @param u32Version Data layout version.
1928	*/
1929	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1930	{
1931	/*
1932	* Validate version.
1933	*/
1934	if (u32Version != PGM_SAVED_STATE_VERSION)
1935	{
1936	Log(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
1937	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1938	}
1939
1940	/*
1941	* Call the reset function to make sure all the memory is cleared.
1942	*/
1943	PGMR3Reset(pVM);
1944
1945	/*
1946	* Load basic data (required / unaffected by relocation).
1947	*/
1948	PPGM pPGM = &pVM->pgm.s;
1949	#if 1
1950	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
1951	#else
1952	uint32_t u;
1953	SSMR3GetU32(pSSM, &u);
1954	pPGM->fMappingsFixed = u;
1955	#endif
1956	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
1957	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
1958
1959	RTUINT cbRamSize;
1960	int rc = SSMR3GetU32(pSSM, &cbRamSize);
1961	if (VBOX_FAILURE(rc))
1962	return rc;
1963	if (cbRamSize != pPGM->cbRamSize)
1964	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
1965	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
1966	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
1967	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
1968	RTUINT uGuestMode;
1969	SSMR3GetUInt(pSSM, &uGuestMode);
1970	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
1971
1972	/* check separator. */
1973	uint32_t u32Sep;
1974	SSMR3GetU32(pSSM, &u32Sep);
1975	if (VBOX_FAILURE(rc))
1976	return rc;
1977	if (u32Sep != (uint32_t)~0)
1978	{
1979	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1980	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1981	}
1982
1983	/*
1984	* The guest mappings.
1985	*/
1986	uint32_t i = 0;
1987	for (;; i++)
1988	{
1989	/* Check the seqence number / separator. */
1990	rc = SSMR3GetU32(pSSM, &u32Sep);
1991	if (VBOX_FAILURE(rc))
1992	return rc;
1993	if (u32Sep == ~0U)
1994	break;
1995	if (u32Sep != i)
1996	{
1997	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1998	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1999	}
2000
2001	/* get the mapping details. */
2002	char szDesc[256];
2003	szDesc[0] = '\0';
2004	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2005	if (VBOX_FAILURE(rc))
2006	return rc;
2007	RTGCPTR GCPtr;
2008	SSMR3GetGCPtr(pSSM, &GCPtr);
2009	RTGCUINTPTR cPTs;
2010	rc = SSMR3GetU32(pSSM, &cPTs);
2011	if (VBOX_FAILURE(rc))
2012	return rc;
2013
2014	/* find matching range. */
2015	PPGMMAPPING pMapping;
2016	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2017	if ( pMapping->cPTs == cPTs
2018	&& !strcmp(pMapping->pszDesc, szDesc))
2019	break;
2020	if (!pMapping)
2021	{
2022	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
2023	cPTs, szDesc, GCPtr));
2024	AssertFailed();
2025	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2026	}
2027
2028	/* relocate it. */
2029	if (pMapping->GCPtr != GCPtr)
2030	{
2031	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
2032	#if HC_ARCH_BITS == 64
2033	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
2034	#endif
2035	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2036	}
2037	else
2038	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
2039	}
2040
2041	/*
2042	* Ram range flags and bits.
2043	*/
2044	i = 0;
2045	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2046	{
2047	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2048	/* Check the seqence number / separator. */
2049	rc = SSMR3GetU32(pSSM, &u32Sep);
2050	if (VBOX_FAILURE(rc))
2051	return rc;
2052	if (u32Sep == ~0U)
2053	break;
2054	if (u32Sep != i)
2055	{
2056	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2057	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2058	}
2059
2060	/* Get the range details. */
2061	RTGCPHYS GCPhys;
2062	SSMR3GetGCPhys(pSSM, &GCPhys);
2063	RTGCPHYS GCPhysLast;
2064	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2065	RTGCPHYS cb;
2066	SSMR3GetGCPhys(pSSM, &cb);
2067	uint8_t fHaveBits;
2068	rc = SSMR3GetU8(pSSM, &fHaveBits);
2069	if (VBOX_FAILURE(rc))
2070	return rc;
2071	if (fHaveBits & ~1)
2072	{
2073	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2074	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2075	}
2076
2077	/* Match it up with the current range. */
2078	if ( GCPhys != pRam->GCPhys
2079	\|\| GCPhysLast != pRam->GCPhysLast
2080	\|\| cb != pRam->cb
2081	\|\| fHaveBits != !!pRam->pvHC)
2082	{
2083	LogRel(("Ram range: %VGp-%VGp %VGp bytes %s\n"
2084	"State : %VGp-%VGp %VGp bytes %s\n",
2085	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
2086	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2087	/*
2088	* If we're loading a state for debugging purpose, don't make a fuss if
2089	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2090	*/
2091	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2092	\|\| GCPhys < 8 * _1M)
2093	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2094
2095	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2096	while (cPages-- > 0)
2097	{
2098	uint16_t u16Ignore;
2099	SSMR3GetU16(pSSM, &u16Ignore);
2100	}
2101	continue;
2102	}
2103
2104	/* Flags. */
2105	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2106	for (unsigned iPage = 0; iPage < cPages; iPage++)
2107	{
2108	uint16_t u16 = 0;
2109	SSMR3GetU16(pSSM, &u16);
2110	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2111	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2112	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2113	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2114	}
2115
2116	/* any memory associated with the range. */
2117	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2118	{
2119	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2120	{
2121	uint8_t fValidChunk;
2122
2123	rc = SSMR3GetU8(pSSM, &fValidChunk);
2124	if (VBOX_FAILURE(rc))
2125	return rc;
2126	if (fValidChunk > 1)
2127	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2128
2129	if (fValidChunk)
2130	{
2131	if (!pRam->pavHCChunkHC[iChunk])
2132	{
2133	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2134	if (VBOX_FAILURE(rc))
2135	return rc;
2136	}
2137	Assert(pRam->pavHCChunkHC[iChunk]);
2138
2139	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2140	}
2141	/* else nothing to do */
2142	}
2143	}
2144	else if (pRam->pvHC)
2145	{
2146	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
2147	if (VBOX_FAILURE(rc))
2148	{
2149	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
2150	return rc;
2151	}
2152	}
2153	}
2154
2155	/*
2156	* We require a full resync now.
2157	*/
2158	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2159	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2160	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2161	pPGM->fPhysCacheFlushPending = true;
2162	pgmR3HandlerPhysicalUpdateAll(pVM);
2163
2164	/*
2165	* Change the paging mode.
2166	*/
2167	return pgmR3ChangeMode(pVM, pPGM->enmGuestMode);
2168	}
2169
2170
2171	/**
2172	* Show paging mode.
2173	*
2174	* @param pVM VM Handle.
2175	* @param pHlp The info helpers.
2176	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2177	*/
2178	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2179	{
2180	/* digest argument. */
2181	bool fGuest, fShadow, fHost;
2182	if (pszArgs)
2183	pszArgs = RTStrStripL(pszArgs);
2184	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2185	fShadow = fHost = fGuest = true;
2186	else
2187	{
2188	fShadow = fHost = fGuest = false;
2189	if (strstr(pszArgs, "guest"))
2190	fGuest = true;
2191	if (strstr(pszArgs, "shadow"))
2192	fShadow = true;
2193	if (strstr(pszArgs, "host"))
2194	fHost = true;
2195	}
2196
2197	/* print info. */
2198	if (fGuest)
2199	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2200	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2201	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2202	if (fShadow)
2203	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2204	if (fHost)
2205	{
2206	const char *psz;
2207	switch (pVM->pgm.s.enmHostMode)
2208	{
2209	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2210	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2211	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2212	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2213	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2214	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2215	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2216	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2217	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2218	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2219	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2220	default: psz = "unknown"; break;
2221	}
2222	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2223	}
2224	}
2225
2226
2227	/**
2228	* Dump registered MMIO ranges to the log.
2229	*
2230	* @param pVM VM Handle.
2231	* @param pHlp The info helpers.
2232	* @param pszArgs Arguments, ignored.
2233	*/
2234	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2235	{
2236	NOREF(pszArgs);
2237	pHlp->pfnPrintf(pHlp,
2238	"RAM ranges (pVM=%p)\n"
2239	"%.s %.s\n",
2240	pVM,
2241	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2242	sizeof(RTHCPTR) * 2, "pvHC ");
2243
2244	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2245	pHlp->pfnPrintf(pHlp,
2246	"%RGp-%RGp %RHv %s\n",
2247	pCur->GCPhys,
2248	pCur->GCPhysLast,
2249	pCur->pvHC,
2250	pCur->pszDesc);
2251	}
2252
2253	/**
2254	* Dump the page directory to the log.
2255	*
2256	* @param pVM VM Handle.
2257	* @param pHlp The info helpers.
2258	* @param pszArgs Arguments, ignored.
2259	*/
2260	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2261	{
2262	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2263	/* Big pages supported? */
2264	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2265	/* Global pages supported? */
2266	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2267
2268	NOREF(pszArgs);
2269
2270	/*
2271	* Get page directory addresses.
2272	*/
2273	PX86PD pPDSrc = pVM->pgm.s.pGuestPDHC;
2274	Assert(pPDSrc);
2275	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2276
2277	/*
2278	* Iterate the page directory.
2279	*/
2280	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2281	{
2282	X86PDE PdeSrc = pPDSrc->a[iPD];
2283	if (PdeSrc.n.u1Present)
2284	{
2285	if (PdeSrc.b.u1Size && fPSE)
2286	{
2287	pHlp->pfnPrintf(pHlp,
2288	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2289	iPD,
2290	PdeSrc.u & X86_PDE_PG_MASK,
2291	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2292	}
2293	else
2294	{
2295	pHlp->pfnPrintf(pHlp,
2296	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2297	iPD,
2298	PdeSrc.u & X86_PDE4M_PG_MASK,
2299	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2300	}
2301	}
2302	}
2303	}
2304
2305
2306	/**
2307	* Serivce a VMMCALLHOST_PGM_LOCK call.
2308	*
2309	* @returns VBox status code.
2310	* @param pVM The VM handle.
2311	*/
2312	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
2313	{
2314	return pgmLock(pVM);
2315	}
2316
2317
2318	/**
2319	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2320	*
2321	* @returns PGM_TYPE_*.
2322	* @param pgmMode The mode value to convert.
2323	*/
2324	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2325	{
2326	switch (pgmMode)
2327	{
2328	case PGMMODE_REAL: return PGM_TYPE_REAL;
2329	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2330	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2331	case PGMMODE_PAE:
2332	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2333	case PGMMODE_AMD64:
2334	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2335	default:
2336	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2337	}
2338	}
2339
2340
2341	/**
2342	* Gets the index into the paging mode data array of a SHW+GST mode.
2343	*
2344	* @returns PGM::paPagingData index.
2345	* @param uShwType The shadow paging mode type.
2346	* @param uGstType The guest paging mode type.
2347	*/
2348	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2349	{
2350	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_AMD64);
2351	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2352	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_32BIT + 1)
2353	+ (uGstType - PGM_TYPE_REAL);
2354	}
2355
2356
2357	/**
2358	* Gets the index into the paging mode data array of a SHW+GST mode.
2359	*
2360	* @returns PGM::paPagingData index.
2361	* @param enmShw The shadow paging mode.
2362	* @param enmGst The guest paging mode.
2363	*/
2364	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2365	{
2366	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2367	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2368	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2369	}
2370
2371
2372	/**
2373	* Calculates the max data index.
2374	* @returns The number of entries in the pagaing data array.
2375	*/
2376	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2377	{
2378	return pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64) + 1;
2379	}
2380
2381
2382	/**
2383	* Initializes the paging mode data kept in PGM::paModeData.
2384	*
2385	* @param pVM The VM handle.
2386	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2387	* This is used early in the init process to avoid trouble with PDM
2388	* not being initialized yet.
2389	*/
2390	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2391	{
2392	PPGMMODEDATA pModeData;
2393	int rc;
2394
2395	/*
2396	* Allocate the array on the first call.
2397	*/
2398	if (!pVM->pgm.s.paModeData)
2399	{
2400	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2401	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2402	}
2403
2404	/*
2405	* Initialize the array entries.
2406	*/
2407	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2408	pModeData->uShwType = PGM_TYPE_32BIT;
2409	pModeData->uGstType = PGM_TYPE_REAL;
2410	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2411	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2412	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2413
2414	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2415	pModeData->uShwType = PGM_TYPE_32BIT;
2416	pModeData->uGstType = PGM_TYPE_PROT;
2417	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2418	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2419	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2420
2421	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2422	pModeData->uShwType = PGM_TYPE_32BIT;
2423	pModeData->uGstType = PGM_TYPE_32BIT;
2424	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2425	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2426	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2427
2428	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2429	pModeData->uShwType = PGM_TYPE_PAE;
2430	pModeData->uGstType = PGM_TYPE_REAL;
2431	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2432	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2433	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2434
2435	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2436	pModeData->uShwType = PGM_TYPE_PAE;
2437	pModeData->uGstType = PGM_TYPE_PROT;
2438	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2439	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2440	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2441
2442	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2443	pModeData->uShwType = PGM_TYPE_PAE;
2444	pModeData->uGstType = PGM_TYPE_32BIT;
2445	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2446	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2447	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2448
2449	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2450	pModeData->uShwType = PGM_TYPE_PAE;
2451	pModeData->uGstType = PGM_TYPE_PAE;
2452	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2453	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2454	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2455
2456	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2457	pModeData->uShwType = PGM_TYPE_AMD64;
2458	pModeData->uGstType = PGM_TYPE_AMD64;
2459	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2460	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2461
2462	return VINF_SUCCESS;
2463	}
2464
2465
2466	/**
2467	* Swtich to different (or relocated in the relocate case) mode data.
2468	*
2469	* @param pVM The VM handle.
2470	* @param enmShw The the shadow paging mode.
2471	* @param enmGst The the guest paging mode.
2472	*/
2473	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2474	{
2475	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(enmShw, enmGst)];
2476
2477	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2478	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2479
2480	/* shadow */
2481	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2482	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2483	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2484	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2485	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2486	pVM->pgm.s.pfnR3ShwGetPDEByIndex = pModeData->pfnR3ShwGetPDEByIndex;
2487	pVM->pgm.s.pfnR3ShwSetPDEByIndex = pModeData->pfnR3ShwSetPDEByIndex;
2488	pVM->pgm.s.pfnR3ShwModifyPDEByIndex = pModeData->pfnR3ShwModifyPDEByIndex;
2489
2490	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
2491	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
2492	pVM->pgm.s.pfnGCShwGetPDEByIndex = pModeData->pfnGCShwGetPDEByIndex;
2493	pVM->pgm.s.pfnGCShwSetPDEByIndex = pModeData->pfnGCShwSetPDEByIndex;
2494	pVM->pgm.s.pfnGCShwModifyPDEByIndex = pModeData->pfnGCShwModifyPDEByIndex;
2495
2496	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2497	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2498	pVM->pgm.s.pfnR0ShwGetPDEByIndex = pModeData->pfnR0ShwGetPDEByIndex;
2499	pVM->pgm.s.pfnR0ShwSetPDEByIndex = pModeData->pfnR0ShwSetPDEByIndex;
2500	pVM->pgm.s.pfnR0ShwModifyPDEByIndex = pModeData->pfnR0ShwModifyPDEByIndex;
2501
2502
2503	/* guest */
2504	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2505	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2506	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2507	Assert(pVM->pgm.s.pfnR3GstGetPage);
2508	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2509	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2510	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2511	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2512	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2513	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2514	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2515	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2516	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2517	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2518
2519	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2520	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2521	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2522	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2523	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2524	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2525	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2526	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2527	pVM->pgm.s.pfnGCGstPAEWriteHandlerCR3 = pModeData->pfnGCGstPAEWriteHandlerCR3;
2528
2529	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2530	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2531	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2532	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2533	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2534	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2535	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2536	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2537	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2538
2539
2540	/* both */
2541	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2542	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2543	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2544	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2545	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2546	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2547	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2548	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2549	#ifdef VBOX_STRICT
2550	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2551	#endif
2552
2553	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2554	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2555	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2556	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2557	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2558	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2559	#ifdef VBOX_STRICT
2560	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2561	#endif
2562
2563	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2564	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2565	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2566	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2567	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2568	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2569	#ifdef VBOX_STRICT
2570	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2571	#endif
2572	}
2573
2574
2575	#ifdef DEBUG_bird
2576	#include <stdlib.h> /* getenv() remove me! */
2577	#endif
2578
2579	/**
2580	* Calculates the shadow paging mode.
2581	*
2582	* @returns The shadow paging mode.
2583	* @param enmGuestMode The guest mode.
2584	* @param enmHostMode The host mode.
2585	* @param enmShadowMode The current shadow mode.
2586	* @param penmSwitcher Where to store the switcher to use.
2587	* VMMSWITCHER_INVALID means no change.
2588	*/
2589	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2590	{
2591	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2592	switch (enmGuestMode)
2593	{
2594	/*
2595	* When switching to real or protected mode we don't change
2596	* anything since it's likely that we'll switch back pretty soon.
2597	*
2598	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2599	* and is supposed to determin which shadow paging and switcher to
2600	* use during init.
2601	*/
2602	case PGMMODE_REAL:
2603	case PGMMODE_PROTECTED:
2604	if (enmShadowMode != PGMMODE_INVALID)
2605	break; /* (no change) */
2606	switch (enmHostMode)
2607	{
2608	case SUPPAGINGMODE_32_BIT:
2609	case SUPPAGINGMODE_32_BIT_GLOBAL:
2610	enmShadowMode = PGMMODE_32_BIT;
2611	enmSwitcher = VMMSWITCHER_32_TO_32;
2612	break;
2613
2614	case SUPPAGINGMODE_PAE:
2615	case SUPPAGINGMODE_PAE_NX:
2616	case SUPPAGINGMODE_PAE_GLOBAL:
2617	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2618	enmShadowMode = PGMMODE_PAE;
2619	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2620	#ifdef DEBUG_bird
2621	if (getenv("VBOX_32BIT"))
2622	{
2623	enmShadowMode = PGMMODE_32_BIT;
2624	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2625	}
2626	#endif
2627	break;
2628
2629	case SUPPAGINGMODE_AMD64:
2630	case SUPPAGINGMODE_AMD64_GLOBAL:
2631	case SUPPAGINGMODE_AMD64_NX:
2632	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2633	enmShadowMode = PGMMODE_PAE;
2634	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2635	break;
2636
2637	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2638	}
2639	break;
2640
2641	case PGMMODE_32_BIT:
2642	switch (enmHostMode)
2643	{
2644	case SUPPAGINGMODE_32_BIT:
2645	case SUPPAGINGMODE_32_BIT_GLOBAL:
2646	enmShadowMode = PGMMODE_32_BIT;
2647	enmSwitcher = VMMSWITCHER_32_TO_32;
2648	break;
2649
2650	case SUPPAGINGMODE_PAE:
2651	case SUPPAGINGMODE_PAE_NX:
2652	case SUPPAGINGMODE_PAE_GLOBAL:
2653	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2654	enmShadowMode = PGMMODE_PAE;
2655	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2656	#ifdef DEBUG_bird
2657	if (getenv("VBOX_32BIT"))
2658	{
2659	enmShadowMode = PGMMODE_32_BIT;
2660	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2661	}
2662	#endif
2663	break;
2664
2665	case SUPPAGINGMODE_AMD64:
2666	case SUPPAGINGMODE_AMD64_GLOBAL:
2667	case SUPPAGINGMODE_AMD64_NX:
2668	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2669	enmShadowMode = PGMMODE_PAE;
2670	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2671	break;
2672
2673	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2674	}
2675	break;
2676
2677	case PGMMODE_PAE:
2678	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2679	switch (enmHostMode)
2680	{
2681	case SUPPAGINGMODE_32_BIT:
2682	case SUPPAGINGMODE_32_BIT_GLOBAL:
2683	enmShadowMode = PGMMODE_PAE;
2684	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2685	break;
2686
2687	case SUPPAGINGMODE_PAE:
2688	case SUPPAGINGMODE_PAE_NX:
2689	case SUPPAGINGMODE_PAE_GLOBAL:
2690	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2691	enmShadowMode = PGMMODE_PAE;
2692	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2693	break;
2694
2695	case SUPPAGINGMODE_AMD64:
2696	case SUPPAGINGMODE_AMD64_GLOBAL:
2697	case SUPPAGINGMODE_AMD64_NX:
2698	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2699	enmShadowMode = PGMMODE_PAE;
2700	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2701	break;
2702
2703	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2704	}
2705	break;
2706
2707	case PGMMODE_AMD64:
2708	case PGMMODE_AMD64_NX:
2709	switch (enmHostMode)
2710	{
2711	case SUPPAGINGMODE_32_BIT:
2712	case SUPPAGINGMODE_32_BIT_GLOBAL:
2713	enmShadowMode = PGMMODE_PAE;
2714	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
2715	break;
2716
2717	case SUPPAGINGMODE_PAE:
2718	case SUPPAGINGMODE_PAE_NX:
2719	case SUPPAGINGMODE_PAE_GLOBAL:
2720	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2721	enmShadowMode = PGMMODE_PAE;
2722	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
2723	break;
2724
2725	case SUPPAGINGMODE_AMD64:
2726	case SUPPAGINGMODE_AMD64_GLOBAL:
2727	case SUPPAGINGMODE_AMD64_NX:
2728	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2729	enmShadowMode = PGMMODE_AMD64;
2730	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
2731	break;
2732
2733	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2734	}
2735	break;
2736
2737
2738	default:
2739	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2740	return PGMMODE_INVALID;
2741	}
2742
2743	*penmSwitcher = enmSwitcher;
2744	return enmShadowMode;
2745	}
2746
2747
2748	/**
2749	* Performs the actual mode change.
2750	* This is called by PGMChangeMode and pgmR3InitPaging().
2751	*
2752	* @returns VBox status code.
2753	* @param pVM VM handle.
2754	* @param enmGuestMode The new guest mode. This is assumed to be different from
2755	* the current mode.
2756	*/
2757	int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
2758	{
2759	LogFlow(("pgmR3ChangeMode: Guest mode: %d -> %d\n", pVM->pgm.s.enmGuestMode, enmGuestMode));
2760	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
2761
2762	/*
2763	* Calc the shadow mode and switcher.
2764	*/
2765	VMMSWITCHER enmSwitcher;
2766	PGMMODE enmShadowMode = pgmR3CalcShadowMode(enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
2767	if (enmSwitcher != VMMSWITCHER_INVALID)
2768	{
2769	/*
2770	* Select new switcher.
2771	*/
2772	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
2773	if (VBOX_FAILURE(rc))
2774	{
2775	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
2776	return rc;
2777	}
2778	}
2779
2780	/*
2781	* Exit old mode(s).
2782	*/
2783	/* shadow */
2784	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2785	{
2786	LogFlow(("pgmR3ChangeMode: Shadow mode: %d -> %d\n", pVM->pgm.s.enmShadowMode, enmShadowMode));
2787	if (PGM_SHW_PFN(Exit, pVM))
2788	{
2789	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
2790	if (VBOX_FAILURE(rc))
2791	{
2792	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
2793	return rc;
2794	}
2795	}
2796
2797	}
2798
2799	/* guest */
2800	if (PGM_GST_PFN(Exit, pVM))
2801	{
2802	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2803	if (VBOX_FAILURE(rc))
2804	{
2805	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
2806	return rc;
2807	}
2808	}
2809
2810	/*
2811	* Load new paging mode data.
2812	*/
2813	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
2814
2815	/*
2816	* Enter new shadow mode (if changed).
2817	*/
2818	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2819	{
2820	int rc;
2821	pVM->pgm.s.enmShadowMode = enmShadowMode;
2822	switch (enmShadowMode)
2823	{
2824	case PGMMODE_32_BIT:
2825	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
2826	break;
2827	case PGMMODE_PAE:
2828	case PGMMODE_PAE_NX:
2829	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
2830	break;
2831	case PGMMODE_AMD64:
2832	case PGMMODE_AMD64_NX:
2833	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
2834	break;
2835	case PGMMODE_REAL:
2836	case PGMMODE_PROTECTED:
2837	default:
2838	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
2839	return VERR_INTERNAL_ERROR;
2840	}
2841	if (VBOX_FAILURE(rc))
2842	{
2843	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
2844	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
2845	return rc;
2846	}
2847	}
2848
2849	/*
2850	* Enter the new guest and shadow+guest modes.
2851	*/
2852	int rc = -1;
2853	int rc2 = -1;
2854	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
2855	pVM->pgm.s.enmGuestMode = enmGuestMode;
2856	switch (enmGuestMode)
2857	{
2858	case PGMMODE_REAL:
2859	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
2860	switch (pVM->pgm.s.enmShadowMode)
2861	{
2862	case PGMMODE_32_BIT:
2863	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
2864	break;
2865	case PGMMODE_PAE:
2866	case PGMMODE_PAE_NX:
2867	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
2868	break;
2869	case PGMMODE_AMD64:
2870	case PGMMODE_AMD64_NX:
2871	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2872	default: AssertFailed(); break;
2873	}
2874	break;
2875
2876	case PGMMODE_PROTECTED:
2877	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
2878	switch (pVM->pgm.s.enmShadowMode)
2879	{
2880	case PGMMODE_32_BIT:
2881	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
2882	break;
2883	case PGMMODE_PAE:
2884	case PGMMODE_PAE_NX:
2885	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
2886	break;
2887	case PGMMODE_AMD64:
2888	case PGMMODE_AMD64_NX:
2889	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2890	default: AssertFailed(); break;
2891	}
2892	break;
2893
2894	case PGMMODE_32_BIT:
2895	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
2896	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
2897	switch (pVM->pgm.s.enmShadowMode)
2898	{
2899	case PGMMODE_32_BIT:
2900	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
2901	break;
2902	case PGMMODE_PAE:
2903	case PGMMODE_PAE_NX:
2904	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
2905	break;
2906	case PGMMODE_AMD64:
2907	case PGMMODE_AMD64_NX:
2908	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2909	default: AssertFailed(); break;
2910	}
2911	break;
2912
2913	//case PGMMODE_PAE_NX:
2914	case PGMMODE_PAE:
2915	{
2916	uint32_t u32Dummy, u32Features;
2917
2918	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2919	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
2920	{
2921	/* Pause first, then inform Main. */
2922	rc = VMR3SuspendNoSave(pVM);
2923	AssertRC(rc);
2924
2925	VMSetRuntimeError(pVM, true, "PAEmode",
2926	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage."));
2927	/* we must return TRUE here otherwise the recompiler will assert */
2928	return VINF_SUCCESS;
2929	}
2930	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
2931	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
2932	switch (pVM->pgm.s.enmShadowMode)
2933	{
2934	case PGMMODE_PAE:
2935	case PGMMODE_PAE_NX:
2936	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
2937	break;
2938	case PGMMODE_32_BIT:
2939	case PGMMODE_AMD64:
2940	case PGMMODE_AMD64_NX:
2941	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2942	default: AssertFailed(); break;
2943	}
2944	break;
2945	}
2946
2947	//case PGMMODE_AMD64_NX:
2948	case PGMMODE_AMD64:
2949	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask and make CR3 64-bit in this case! */
2950	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
2951	switch (pVM->pgm.s.enmShadowMode)
2952	{
2953	case PGMMODE_AMD64:
2954	case PGMMODE_AMD64_NX:
2955	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
2956	break;
2957	case PGMMODE_32_BIT:
2958	case PGMMODE_PAE:
2959	case PGMMODE_PAE_NX:
2960	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
2961	default: AssertFailed(); break;
2962	}
2963	break;
2964
2965	default:
2966	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2967	rc = VERR_NOT_IMPLEMENTED;
2968	break;
2969	}
2970
2971	/* status codes. */
2972	AssertRC(rc);
2973	AssertRC(rc2);
2974	if (VBOX_SUCCESS(rc))
2975	{
2976	rc = rc2;
2977	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
2978	rc = VINF_SUCCESS;
2979	}
2980
2981	/*
2982	* Notify SELM so it can update the TSSes with correct CR3s.
2983	*/
2984	SELMR3PagingModeChanged(pVM);
2985
2986	/* Notify HWACCM as well. */
2987	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
2988	return rc;
2989	}
2990
2991
2992	/**
2993	* Dumps a PAE shadow page table.
2994	*
2995	* @returns VBox status code (VINF_SUCCESS).
2996	* @param pVM The VM handle.
2997	* @param pPT Pointer to the page table.
2998	* @param u64Address The virtual address of the page table starts.
2999	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3000	* @param cMaxDepth The maxium depth.
3001	* @param pHlp Pointer to the output functions.
3002	*/
3003	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3004	{
3005	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3006	{
3007	X86PTEPAE Pte = pPT->a[i];
3008	if (Pte.n.u1Present)
3009	{
3010	pHlp->pfnPrintf(pHlp,
3011	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3012	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3013	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3014	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3015	Pte.n.u1Write ? 'W' : 'R',
3016	Pte.n.u1User ? 'U' : 'S',
3017	Pte.n.u1Accessed ? 'A' : '-',
3018	Pte.n.u1Dirty ? 'D' : '-',
3019	Pte.n.u1Global ? 'G' : '-',
3020	Pte.n.u1WriteThru ? "WT" : "--",
3021	Pte.n.u1CacheDisable? "CD" : "--",
3022	Pte.n.u1PAT ? "AT" : "--",
3023	Pte.n.u1NoExecute ? "NX" : "--",
3024	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3025	Pte.u & RT_BIT(10) ? '1' : '0',
3026	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3027	Pte.u & X86_PTE_PAE_PG_MASK);
3028	}
3029	}
3030	return VINF_SUCCESS;
3031	}
3032
3033
3034	/**
3035	* Dumps a PAE shadow page directory table.
3036	*
3037	* @returns VBox status code (VINF_SUCCESS).
3038	* @param pVM The VM handle.
3039	* @param HCPhys The physical address of the page directory table.
3040	* @param u64Address The virtual address of the page table starts.
3041	* @param cr4 The CR4, PSE is currently used.
3042	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3043	* @param cMaxDepth The maxium depth.
3044	* @param pHlp Pointer to the output functions.
3045	*/
3046	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3047	{
3048	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3049	if (!pPD)
3050	{
3051	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3052	fLongMode ? 16 : 8, u64Address, HCPhys);
3053	return VERR_INVALID_PARAMETER;
3054	}
3055	int rc = VINF_SUCCESS;
3056	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3057	{
3058	X86PDEPAE Pde = pPD->a[i];
3059	if (Pde.n.u1Present)
3060	{
3061	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3062	pHlp->pfnPrintf(pHlp,
3063	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3064	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3065	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3066	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3067	Pde.b.u1Write ? 'W' : 'R',
3068	Pde.b.u1User ? 'U' : 'S',
3069	Pde.b.u1Accessed ? 'A' : '-',
3070	Pde.b.u1Dirty ? 'D' : '-',
3071	Pde.b.u1Global ? 'G' : '-',
3072	Pde.b.u1WriteThru ? "WT" : "--",
3073	Pde.b.u1CacheDisable? "CD" : "--",
3074	Pde.b.u1PAT ? "AT" : "--",
3075	Pde.b.u1NoExecute ? "NX" : "--",
3076	Pde.u & RT_BIT_64(9) ? '1' : '0',
3077	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3078	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3079	Pde.u & X86_PDE_PAE_PG_MASK);
3080	else
3081	{
3082	pHlp->pfnPrintf(pHlp,
3083	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3084	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3085	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3086	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3087	Pde.n.u1Write ? 'W' : 'R',
3088	Pde.n.u1User ? 'U' : 'S',
3089	Pde.n.u1Accessed ? 'A' : '-',
3090	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3091	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3092	Pde.n.u1WriteThru ? "WT" : "--",
3093	Pde.n.u1CacheDisable? "CD" : "--",
3094	Pde.n.u1NoExecute ? "NX" : "--",
3095	Pde.u & RT_BIT_64(9) ? '1' : '0',
3096	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3097	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3098	Pde.u & X86_PDE_PAE_PG_MASK);
3099	if (cMaxDepth >= 1)
3100	{
3101	/** @todo what about using the page pool for mapping PTs? */
3102	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3103	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3104	PX86PTPAE pPT = NULL;
3105	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3106	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3107	else
3108	{
3109	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3110	{
3111	uint64_t off = u64AddressPT - pMap->GCPtr;
3112	if (off < pMap->cb)
3113	{
3114	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3115	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3116	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3117	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3118	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3119	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3120	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3121	}
3122	}
3123	}
3124	int rc2 = VERR_INVALID_PARAMETER;
3125	if (pPT)
3126	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3127	else
3128	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3129	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3130	if (rc2 < rc && VBOX_SUCCESS(rc))
3131	rc = rc2;
3132	}
3133	}
3134	}
3135	}
3136	return rc;
3137	}
3138
3139
3140	/**
3141	* Dumps a PAE shadow page directory pointer table.
3142	*
3143	* @returns VBox status code (VINF_SUCCESS).
3144	* @param pVM The VM handle.
3145	* @param HCPhys The physical address of the page directory pointer table.
3146	* @param u64Address The virtual address of the page table starts.
3147	* @param cr4 The CR4, PSE is currently used.
3148	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3149	* @param cMaxDepth The maxium depth.
3150	* @param pHlp Pointer to the output functions.
3151	*/
3152	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3153	{
3154	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3155	if (!pPDPT)
3156	{
3157	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3158	fLongMode ? 16 : 8, u64Address, HCPhys);
3159	return VERR_INVALID_PARAMETER;
3160	}
3161
3162	int rc = VINF_SUCCESS;
3163	const unsigned c = fLongMode ? ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3164	for (unsigned i = 0; i < c; i++)
3165	{
3166	X86PDPE Pdpe = pPDPT->a[i];
3167	if (Pdpe.n.u1Present)
3168	{
3169	if (fLongMode)
3170	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3171	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3172	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3173	Pdpe.n.u1Write ? 'W' : 'R',
3174	Pdpe.n.u1User ? 'U' : 'S',
3175	Pdpe.n.u1Accessed ? 'A' : '-',
3176	Pdpe.n.u3Reserved & 1? '?' : '.', /* ignored */
3177	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
3178	Pdpe.n.u1WriteThru ? "WT" : "--",
3179	Pdpe.n.u1CacheDisable? "CD" : "--",
3180	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
3181	Pdpe.n.u1NoExecute ? "NX" : "--",
3182	Pdpe.u & RT_BIT(9) ? '1' : '0',
3183	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3184	Pdpe.u & RT_BIT(11) ? '1' : '0',
3185	Pdpe.u & X86_PDPE_PG_MASK);
3186	else
3187	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3188	"%08x 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3189	i << X86_PDPT_SHIFT,
3190	Pdpe.n.u1Write ? '!' : '.', /* mbz */
3191	Pdpe.n.u1User ? '!' : '.', /* mbz */
3192	Pdpe.n.u1Accessed ? '!' : '.', /* mbz */
3193	Pdpe.n.u3Reserved & 1? '!' : '.', /* mbz */
3194	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
3195	Pdpe.n.u1WriteThru ? "WT" : "--",
3196	Pdpe.n.u1CacheDisable? "CD" : "--",
3197	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
3198	Pdpe.n.u1NoExecute ? "NX" : "--",
3199	Pdpe.u & RT_BIT(9) ? '1' : '0',
3200	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3201	Pdpe.u & RT_BIT(11) ? '1' : '0',
3202	Pdpe.u & X86_PDPE_PG_MASK);
3203	if (cMaxDepth >= 1)
3204	{
3205	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3206	cr4, fLongMode, cMaxDepth - 1, pHlp);
3207	if (rc2 < rc && VBOX_SUCCESS(rc))
3208	rc = rc2;
3209	}
3210	}
3211	}
3212	return rc;
3213	}
3214
3215
3216	/**
3217	* Dumps a 32-bit shadow page table.
3218	*
3219	* @returns VBox status code (VINF_SUCCESS).
3220	* @param pVM The VM handle.
3221	* @param HCPhys The physical address of the table.
3222	* @param cr4 The CR4, PSE is currently used.
3223	* @param cMaxDepth The maxium depth.
3224	* @param pHlp Pointer to the output functions.
3225	*/
3226	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3227	{
3228	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3229	if (!pPML4)
3230	{
3231	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3232	return VERR_INVALID_PARAMETER;
3233	}
3234
3235	int rc = VINF_SUCCESS;
3236	for (unsigned i = 0; i < ELEMENTS(pPML4->a); i++)
3237	{
3238	X86PML4E Pml4e = pPML4->a[i];
3239	if (Pml4e.n.u1Present)
3240	{
3241	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3242	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3243	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3244	u64Address,
3245	Pml4e.n.u1Write ? 'W' : 'R',
3246	Pml4e.n.u1User ? 'U' : 'S',
3247	Pml4e.n.u1Accessed ? 'A' : '-',
3248	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3249	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3250	Pml4e.n.u1WriteThru ? "WT" : "--",
3251	Pml4e.n.u1CacheDisable? "CD" : "--",
3252	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3253	Pml4e.n.u1NoExecute ? "NX" : "--",
3254	Pml4e.u & RT_BIT(9) ? '1' : '0',
3255	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3256	Pml4e.u & RT_BIT(11) ? '1' : '0',
3257	Pml4e.u & X86_PML4E_PG_MASK);
3258
3259	if (cMaxDepth >= 1)
3260	{
3261	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3262	if (rc2 < rc && VBOX_SUCCESS(rc))
3263	rc = rc2;
3264	}
3265	}
3266	}
3267	return rc;
3268	}
3269
3270
3271	/**
3272	* Dumps a 32-bit shadow page table.
3273	*
3274	* @returns VBox status code (VINF_SUCCESS).
3275	* @param pVM The VM handle.
3276	* @param pPT Pointer to the page table.
3277	* @param u32Address The virtual address this table starts at.
3278	* @param pHlp Pointer to the output functions.
3279	*/
3280	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3281	{
3282	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3283	{
3284	X86PTE Pte = pPT->a[i];
3285	if (Pte.n.u1Present)
3286	{
3287	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3288	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3289	u32Address + (i << X86_PT_SHIFT),
3290	Pte.n.u1Write ? 'W' : 'R',
3291	Pte.n.u1User ? 'U' : 'S',
3292	Pte.n.u1Accessed ? 'A' : '-',
3293	Pte.n.u1Dirty ? 'D' : '-',
3294	Pte.n.u1Global ? 'G' : '-',
3295	Pte.n.u1WriteThru ? "WT" : "--",
3296	Pte.n.u1CacheDisable? "CD" : "--",
3297	Pte.n.u1PAT ? "AT" : "--",
3298	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3299	Pte.u & RT_BIT(10) ? '1' : '0',
3300	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3301	Pte.u & X86_PDE_PG_MASK);
3302	}
3303	}
3304	return VINF_SUCCESS;
3305	}
3306
3307
3308	/**
3309	* Dumps a 32-bit shadow page directory and page tables.
3310	*
3311	* @returns VBox status code (VINF_SUCCESS).
3312	* @param pVM The VM handle.
3313	* @param cr3 The root of the hierarchy.
3314	* @param cr4 The CR4, PSE is currently used.
3315	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3316	* @param pHlp Pointer to the output functions.
3317	*/
3318	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3319	{
3320	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3321	if (!pPD)
3322	{
3323	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3324	return VERR_INVALID_PARAMETER;
3325	}
3326
3327	int rc = VINF_SUCCESS;
3328	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3329	{
3330	X86PDE Pde = pPD->a[i];
3331	if (Pde.n.u1Present)
3332	{
3333	const uint32_t u32Address = i << X86_PD_SHIFT;
3334	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3335	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3336	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3337	u32Address,
3338	Pde.b.u1Write ? 'W' : 'R',
3339	Pde.b.u1User ? 'U' : 'S',
3340	Pde.b.u1Accessed ? 'A' : '-',
3341	Pde.b.u1Dirty ? 'D' : '-',
3342	Pde.b.u1Global ? 'G' : '-',
3343	Pde.b.u1WriteThru ? "WT" : "--",
3344	Pde.b.u1CacheDisable? "CD" : "--",
3345	Pde.b.u1PAT ? "AT" : "--",
3346	Pde.u & RT_BIT_64(9) ? '1' : '0',
3347	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3348	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3349	Pde.u & X86_PDE4M_PG_MASK);
3350	else
3351	{
3352	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3353	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3354	u32Address,
3355	Pde.n.u1Write ? 'W' : 'R',
3356	Pde.n.u1User ? 'U' : 'S',
3357	Pde.n.u1Accessed ? 'A' : '-',
3358	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3359	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3360	Pde.n.u1WriteThru ? "WT" : "--",
3361	Pde.n.u1CacheDisable? "CD" : "--",
3362	Pde.u & RT_BIT_64(9) ? '1' : '0',
3363	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3364	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3365	Pde.u & X86_PDE_PG_MASK);
3366	if (cMaxDepth >= 1)
3367	{
3368	/** @todo what about using the page pool for mapping PTs? */
3369	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3370	PX86PT pPT = NULL;
3371	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3372	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3373	else
3374	{
3375	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3376	if (u32Address - pMap->GCPtr < pMap->cb)
3377	{
3378	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3379	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3380	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3381	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3382	pPT = pMap->aPTs[iPDE].pPTR3;
3383	}
3384	}
3385	int rc2 = VERR_INVALID_PARAMETER;
3386	if (pPT)
3387	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3388	else
3389	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3390	if (rc2 < rc && VBOX_SUCCESS(rc))
3391	rc = rc2;
3392	}
3393	}
3394	}
3395	}
3396
3397	return rc;
3398	}
3399
3400
3401	/**
3402	* Dumps a 32-bit shadow page table.
3403	*
3404	* @returns VBox status code (VINF_SUCCESS).
3405	* @param pVM The VM handle.
3406	* @param pPT Pointer to the page table.
3407	* @param u32Address The virtual address this table starts at.
3408	* @param PhysSearch Address to search for.
3409	*/
3410	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3411	{
3412	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3413	{
3414	X86PTE Pte = pPT->a[i];
3415	if (Pte.n.u1Present)
3416	{
3417	Log(( /P R S A D G WT CD AT NX 4M a m d /
3418	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3419	u32Address + (i << X86_PT_SHIFT),
3420	Pte.n.u1Write ? 'W' : 'R',
3421	Pte.n.u1User ? 'U' : 'S',
3422	Pte.n.u1Accessed ? 'A' : '-',
3423	Pte.n.u1Dirty ? 'D' : '-',
3424	Pte.n.u1Global ? 'G' : '-',
3425	Pte.n.u1WriteThru ? "WT" : "--",
3426	Pte.n.u1CacheDisable? "CD" : "--",
3427	Pte.n.u1PAT ? "AT" : "--",
3428	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3429	Pte.u & RT_BIT(10) ? '1' : '0',
3430	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3431	Pte.u & X86_PDE_PG_MASK));
3432
3433	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3434	{
3435	uint64_t fPageShw = 0;
3436	RTHCPHYS pPhysHC = 0;
3437
3438	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3439	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3440	}
3441	}
3442	}
3443	return VINF_SUCCESS;
3444	}
3445
3446
3447	/**
3448	* Dumps a 32-bit guest page directory and page tables.
3449	*
3450	* @returns VBox status code (VINF_SUCCESS).
3451	* @param pVM The VM handle.
3452	* @param cr3 The root of the hierarchy.
3453	* @param cr4 The CR4, PSE is currently used.
3454	* @param PhysSearch Address to search for.
3455	*/
3456	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3457	{
3458	bool fLongMode = false;
3459	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3460	PX86PD pPD = 0;
3461
3462	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3463	if (VBOX_FAILURE(rc) \|\| !pPD)
3464	{
3465	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3466	return VERR_INVALID_PARAMETER;
3467	}
3468
3469	Log(("cr3=%08x cr4=%08x%s\n"
3470	"%-*s P - Present\n"
3471	"%-*s \| R/W - Read (0) / Write (1)\n"
3472	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3473	"%-*s \| \| \| A - Accessed\n"
3474	"%-*s \| \| \| \| D - Dirty\n"
3475	"%-*s \| \| \| \| \| G - Global\n"
3476	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3477	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3478	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3479	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3480	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3481	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3482	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3483	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3484	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3485	- W U - - - -- -- -- -- -- 010 */
3486	, cr3, cr4, fLongMode ? " Long Mode" : "",
3487	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3488	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3489
3490	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3491	{
3492	X86PDE Pde = pPD->a[i];
3493	if (Pde.n.u1Present)
3494	{
3495	const uint32_t u32Address = i << X86_PD_SHIFT;
3496
3497	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3498	Log(( /P R S A D G WT CD AT NX 4M a m d /
3499	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3500	u32Address,
3501	Pde.b.u1Write ? 'W' : 'R',
3502	Pde.b.u1User ? 'U' : 'S',
3503	Pde.b.u1Accessed ? 'A' : '-',
3504	Pde.b.u1Dirty ? 'D' : '-',
3505	Pde.b.u1Global ? 'G' : '-',
3506	Pde.b.u1WriteThru ? "WT" : "--",
3507	Pde.b.u1CacheDisable? "CD" : "--",
3508	Pde.b.u1PAT ? "AT" : "--",
3509	Pde.u & RT_BIT(9) ? '1' : '0',
3510	Pde.u & RT_BIT(10) ? '1' : '0',
3511	Pde.u & RT_BIT(11) ? '1' : '0',
3512	Pde.u & X86_PDE4M_PG_MASK));
3513	/** @todo PhysSearch */
3514	else
3515	{
3516	Log(( /P R S A D G WT CD AT NX 4M a m d /
3517	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3518	u32Address,
3519	Pde.n.u1Write ? 'W' : 'R',
3520	Pde.n.u1User ? 'U' : 'S',
3521	Pde.n.u1Accessed ? 'A' : '-',
3522	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3523	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3524	Pde.n.u1WriteThru ? "WT" : "--",
3525	Pde.n.u1CacheDisable? "CD" : "--",
3526	Pde.u & RT_BIT(9) ? '1' : '0',
3527	Pde.u & RT_BIT(10) ? '1' : '0',
3528	Pde.u & RT_BIT(11) ? '1' : '0',
3529	Pde.u & X86_PDE_PG_MASK));
3530	////if (cMaxDepth >= 1)
3531	{
3532	/** @todo what about using the page pool for mapping PTs? */
3533	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3534	PX86PT pPT = NULL;
3535
3536	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3537
3538	int rc2 = VERR_INVALID_PARAMETER;
3539	if (pPT)
3540	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3541	else
3542	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3543	if (rc2 < rc && VBOX_SUCCESS(rc))
3544	rc = rc2;
3545	}
3546	}
3547	}
3548	}
3549
3550	return rc;
3551	}
3552
3553
3554	/**
3555	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3556	*
3557	* @returns VBox status code (VINF_SUCCESS).
3558	* @param pVM The VM handle.
3559	* @param cr3 The root of the hierarchy.
3560	* @param cr4 The cr4, only PAE and PSE is currently used.
3561	* @param fLongMode Set if long mode, false if not long mode.
3562	* @param cMaxDepth Number of levels to dump.
3563	* @param pHlp Pointer to the output functions.
3564	*/
3565	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3566	{
3567	if (!pHlp)
3568	pHlp = DBGFR3InfoLogHlp();
3569	if (!cMaxDepth)
3570	return VINF_SUCCESS;
3571	const unsigned cch = fLongMode ? 16 : 8;
3572	pHlp->pfnPrintf(pHlp,
3573	"cr3=%08x cr4=%08x%s\n"
3574	"%-*s P - Present\n"
3575	"%-*s \| R/W - Read (0) / Write (1)\n"
3576	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3577	"%-*s \| \| \| A - Accessed\n"
3578	"%-*s \| \| \| \| D - Dirty\n"
3579	"%-*s \| \| \| \| \| G - Global\n"
3580	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3581	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3582	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3583	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3584	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3585	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3586	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3587	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3588	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3589	- W U - - - -- -- -- -- -- 010 */
3590	, cr3, cr4, fLongMode ? " Long Mode" : "",
3591	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3592	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3593	if (cr4 & X86_CR4_PAE)
3594	{
3595	if (fLongMode)
3596	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3597	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3598	}
3599	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3600	}
3601
3602
3603
3604	#ifdef VBOX_WITH_DEBUGGER
3605	/**
3606	* The '.pgmram' command.
3607	*
3608	* @returns VBox status.
3609	* @param pCmd Pointer to the command descriptor (as registered).
3610	* @param pCmdHlp Pointer to command helper functions.
3611	* @param pVM Pointer to the current VM (if any).
3612	* @param paArgs Pointer to (readonly) array of arguments.
3613	* @param cArgs Number of arguments in the array.
3614	*/
3615	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3616	{
3617	/*
3618	* Validate input.
3619	*/
3620	if (!pVM)
3621	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3622	if (!pVM->pgm.s.pRamRangesGC)
3623	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3624
3625	/*
3626	* Dump the ranges.
3627	*/
3628	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3629	PPGMRAMRANGE pRam;
3630	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
3631	{
3632	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3633	"%VGp - %VGp %p\n",
3634	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
3635	if (VBOX_FAILURE(rc))
3636	return rc;
3637	}
3638
3639	return VINF_SUCCESS;
3640	}
3641
3642
3643	/**
3644	* The '.pgmmap' command.
3645	*
3646	* @returns VBox status.
3647	* @param pCmd Pointer to the command descriptor (as registered).
3648	* @param pCmdHlp Pointer to command helper functions.
3649	* @param pVM Pointer to the current VM (if any).
3650	* @param paArgs Pointer to (readonly) array of arguments.
3651	* @param cArgs Number of arguments in the array.
3652	*/
3653	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3654	{
3655	/*
3656	* Validate input.
3657	*/
3658	if (!pVM)
3659	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3660	if (!pVM->pgm.s.pMappingsR3)
3661	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
3662
3663	/*
3664	* Print message about the fixedness of the mappings.
3665	*/
3666	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
3667	if (VBOX_FAILURE(rc))
3668	return rc;
3669
3670	/*
3671	* Dump the ranges.
3672	*/
3673	PPGMMAPPING pCur;
3674	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
3675	{
3676	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3677	"%08x - %08x %s\n",
3678	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
3679	if (VBOX_FAILURE(rc))
3680	return rc;
3681	}
3682
3683	return VINF_SUCCESS;
3684	}
3685
3686
3687	/**
3688	* The '.pgmsync' command.
3689	*
3690	* @returns VBox status.
3691	* @param pCmd Pointer to the command descriptor (as registered).
3692	* @param pCmdHlp Pointer to command helper functions.
3693	* @param pVM Pointer to the current VM (if any).
3694	* @param paArgs Pointer to (readonly) array of arguments.
3695	* @param cArgs Number of arguments in the array.
3696	*/
3697	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3698	{
3699	/*
3700	* Validate input.
3701	*/
3702	if (!pVM)
3703	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3704
3705	/*
3706	* Force page directory sync.
3707	*/
3708	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3709
3710	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3711	if (VBOX_FAILURE(rc))
3712	return rc;
3713
3714	return VINF_SUCCESS;
3715	}
3716
3717
3718	/**
3719	* The '.pgmsyncalways' command.
3720	*
3721	* @returns VBox status.
3722	* @param pCmd Pointer to the command descriptor (as registered).
3723	* @param pCmdHlp Pointer to command helper functions.
3724	* @param pVM Pointer to the current VM (if any).
3725	* @param paArgs Pointer to (readonly) array of arguments.
3726	* @param cArgs Number of arguments in the array.
3727	*/
3728	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3729	{
3730	/*
3731	* Validate input.
3732	*/
3733	if (!pVM)
3734	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3735
3736	/*
3737	* Force page directory sync.
3738	*/
3739	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3740	{
3741	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3742	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
3743	}
3744	else
3745	{
3746	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3747	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3748	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
3749	}
3750	}
3751
3752	#endif
3753
3754	/**
3755	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3756	*/
3757	typedef struct PGMCHECKINTARGS
3758	{
3759	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
3760	PPGMPHYSHANDLER pPrevPhys;
3761	PPGMVIRTHANDLER pPrevVirt;
3762	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
3763	PVM pVM;
3764	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
3765
3766	/**
3767	* Validate a node in the physical handler tree.
3768	*
3769	* @returns 0 on if ok, other wise 1.
3770	* @param pNode The handler node.
3771	* @param pvUser pVM.
3772	*/
3773	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3774	{
3775	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3776	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
3777	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3778	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3779	AssertReleaseMsg( !pArgs->pPrevPhys
3780	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
3781	("pPrevPhys=%p %VGp-%VGp %s\n"
3782	" pCur=%p %VGp-%VGp %s\n",
3783	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
3784	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3785	pArgs->pPrevPhys = pCur;
3786	return 0;
3787	}
3788
3789
3790	/**
3791	* Validate a node in the virtual handler tree.
3792	*
3793	* @returns 0 on if ok, other wise 1.
3794	* @param pNode The handler node.
3795	* @param pvUser pVM.
3796	*/
3797	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
3798	{
3799	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3800	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
3801	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3802	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3803	AssertReleaseMsg( !pArgs->pPrevVirt
3804	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
3805	("pPrevVirt=%p %VGv-%VGv %s\n"
3806	" pCur=%p %VGv-%VGv %s\n",
3807	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
3808	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3809	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
3810	{
3811	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
3812	("pCur=%p %VGv-%VGv %s\n"
3813	"iPage=%d offVirtHandle=%#x expected %#x\n",
3814	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
3815	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
3816	}
3817	pArgs->pPrevVirt = pCur;
3818	return 0;
3819	}
3820
3821
3822	/**
3823	* Validate a node in the virtual handler tree.
3824	*
3825	* @returns 0 on if ok, other wise 1.
3826	* @param pNode The handler node.
3827	* @param pvUser pVM.
3828	*/
3829	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3830	{
3831	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3832	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
3833	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
3834	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
3835	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
3836	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3837	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3838	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3839	" pCur=%p %VGp-%VGp\n",
3840	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3841	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3842	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3843	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3844	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3845	" pCur=%p %VGp-%VGp\n",
3846	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3847	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3848	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
3849	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3850	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3851	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3852	{
3853	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
3854	for (;;)
3855	{
3856	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3857	AssertReleaseMsg(pCur2 != pCur,
3858	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3859	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3860	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
3861	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3862	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3863	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3864	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3865	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
3866	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3867	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3868	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3869	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3870	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
3871	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3872	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3873	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3874	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3875	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3876	break;
3877	}
3878	}
3879
3880	pArgs->pPrevPhys2Virt = pCur;
3881	return 0;
3882	}
3883
3884
3885	/**
3886	* Perform an integrity check on the PGM component.
3887	*
3888	* @returns VINF_SUCCESS if everything is fine.
3889	* @returns VBox error status after asserting on integrity breach.
3890	* @param pVM The VM handle.
3891	*/
3892	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
3893	{
3894	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
3895
3896	/*
3897	* Check the trees.
3898	*/
3899	int cErrors = 0;
3900	PGMCHECKINTARGS Args = { true, NULL, NULL, NULL, pVM };
3901	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3902	Args.fLeftToRight = false;
3903	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3904	Args.fLeftToRight = true;
3905	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3906	Args.fLeftToRight = false;
3907	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3908	Args.fLeftToRight = true;
3909	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3910	Args.fLeftToRight = false;
3911	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3912	Args.fLeftToRight = true;
3913	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3914	Args.fLeftToRight = false;
3915	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3916
3917	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
3918	}
3919
3920
3921	/**
3922	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
3923	*
3924	* @returns VBox status code.
3925	* @param pVM VM handle.
3926	* @param fEnable Enable or disable shadow mappings
3927	*/
3928	PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
3929	{
3930	pVM->pgm.s.fDisableMappings = !fEnable;
3931
3932	uint32_t cb;
3933	int rc = PGMR3MappingsSize(pVM, &cb);
3934	AssertRCReturn(rc, rc);
3935
3936	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
3937	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
3938	AssertRCReturn(rc, rc);
3939
3940	return VINF_SUCCESS;
3941	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 8465

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