PGM.cpp@ 13232

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1	/* $Id: PGM.cpp 13188 2008-10-11 01:58:30Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location.
81	*
82	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
83	* simplifies switching guest CPU mode and consistency at the cost of more
84	* code to do the work. All memory use for those page tables is located below
85	* 4GB (this includes page tables for guest context mappings).
86	*
87	*
88	* @subsection subsec_pgm_int_gc Guest Context Mappings
89	*
90	* During assignment and relocation of a guest context mapping the intermediate
91	* memory context is used to verify the new location.
92	*
93	* Guest context mappings are currently restricted to below 4GB, for reasons
94	* of simplicity. This may change when we implement AMD64 support.
95	*
96	*
97	*
98	*
99	* @section sec_pgm_misc Misc
100	*
101	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
102	*
103	* The differences between legacy PAE and long mode PAE are:
104	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
105	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
106	* usual meanings while 6 is ignored (AMD). This means that upon switching to
107	* legacy PAE mode we'll have to clear these bits and when going to long mode
108	* they must be set. This applies to both intermediate and shadow contexts,
109	* however we don't need to do it for the intermediate one since we're
110	* executing with CR0.WP at that time.
111	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
112	* a page aligned one is required.
113	*
114	*
115	* @section sec_pgm_handlers Access Handlers
116	*
117	* Placeholder.
118	*
119	*
120	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
121	*
122	* Placeholder.
123	*
124	*
125	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
126	*
127	* We currently implement three types of virtual access handlers: ALL, WRITE
128	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
129	*
130	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
131	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
132	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
133	* rest of this section is going to be about these handlers.
134	*
135	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
136	* how successfull this is gonna be...
137	*
138	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
139	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
140	* and create a new node that is inserted into the AVL tree (range key). Then
141	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
142	*
143	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
144	*
145	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
146	* via the current guest CR3 and update the physical page -> virtual handler
147	* translation. Needless to say, this doesn't exactly scale very well. If any changes
148	* are detected, it will flag a virtual bit update just like we did on registration.
149	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
150	*
151	* 2b. The virtual bit update process will iterate all the pages covered by all the
152	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
153	* virtual handlers on that page.
154	*
155	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
156	* we don't miss any alias mappings of the monitored pages.
157	*
158	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
159	*
160	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
161	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
162	* will call the handlers like in the next step. If the physical mapping has
163	* changed we will - some time in the future - perform a handler callback
164	* (optional) and update the physical -> virtual handler cache.
165	*
166	* 4. \#PF(,write) on a page in the range. This will cause the handler to
167	* be invoked.
168	*
169	* 5. The guest invalidates the page and changes the physical backing or
170	* unmaps it. This should cause the invalidation callback to be invoked
171	* (it might not yet be 100% perfect). Exactly what happens next... is
172	* this where we mess up and end up out of sync for a while?
173	*
174	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
175	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
176	* this handler to NONE and trigger a full PGM resync (basically the same
177	* as int step 1). Which means 2 is executed again.
178	*
179	*
180	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
181	*
182	* There is a bunch of things that needs to be done to make the virtual handlers
183	* work 100% correctly and work more efficiently.
184	*
185	* The first bit hasn't been implemented yet because it's going to slow the
186	* whole mess down even more, and besides it seems to be working reliably for
187	* our current uses. OTOH, some of the optimizations might end up more or less
188	* implementing the missing bits, so we'll see.
189	*
190	* On the optimization side, the first thing to do is to try avoid unnecessary
191	* cache flushing. Then try team up with the shadowing code to track changes
192	* in mappings by means of access to them (shadow in), updates to shadows pages,
193	* invlpg, and shadow PT discarding (perhaps).
194	*
195	* Some idea that have popped up for optimization for current and new features:
196	* - bitmap indicating where there are virtual handlers installed.
197	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
198	* - Further optimize this by min/max (needs min/max avl getters).
199	* - Shadow page table entry bit (if any left)?
200	*
201	*/
202
203
204	/** @page pg_pgm_phys PGM Physical Guest Memory Management
205	*
206	*
207	* Objectives:
208	* - Guest RAM over-commitment using memory ballooning,
209	* zero pages and general page sharing.
210	* - Moving or mirroring a VM onto a different physical machine.
211	*
212	*
213	* @subsection subsec_pgmPhys_Definitions Definitions
214	*
215	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
216	* machinery assoicated with it.
217	*
218	*
219	*
220	*
221	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
222	*
223	* Initially we map all guest memory to the (per VM) zero page, which
224	* means that none of the read functions will cause pages to be allocated.
225	*
226	* Exception, access bit in page tables that have been shared. This must
227	* be handled, but we must also make sure PGMGst*Modify doesn't make
228	* unnecessary modifications.
229	*
230	* Allocation points:
231	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
232	* - Replacing a zero page mapping at \#PF.
233	* - Replacing a shared page mapping at \#PF.
234	* - ROM registration (currently MMR3RomRegister).
235	* - VM restore (pgmR3Load).
236	*
237	* For the first three it would make sense to keep a few pages handy
238	* until we've reached the max memory commitment for the VM.
239	*
240	* For the ROM registration, we know exactly how many pages we need
241	* and will request these from ring-0. For restore, we will save
242	* the number of non-zero pages in the saved state and allocate
243	* them up front. This would allow the ring-0 component to refuse
244	* the request if the isn't sufficient memory available for VM use.
245	*
246	* Btw. for both ROM and restore allocations we won't be requiring
247	* zeroed pages as they are going to be filled instantly.
248	*
249	*
250	* @subsection subsec_pgmPhys_FreePage Freeing a page
251	*
252	* There are a few points where a page can be freed:
253	* - After being replaced by the zero page.
254	* - After being replaced by a shared page.
255	* - After being ballooned by the guest additions.
256	* - At reset.
257	* - At restore.
258	*
259	* When freeing one or more pages they will be returned to the ring-0
260	* component and replaced by the zero page.
261	*
262	* The reasoning for clearing out all the pages on reset is that it will
263	* return us to the exact same state as on power on, and may thereby help
264	* us reduce the memory load on the system. Further it might have a
265	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
266	*
267	* On restore, as mention under the allocation topic, pages should be
268	* freed / allocated depending on how many is actually required by the
269	* new VM state. The simplest approach is to do like on reset, and free
270	* all non-ROM pages and then allocate what we need.
271	*
272	* A measure to prevent some fragmentation, would be to let each allocation
273	* chunk have some affinity towards the VM having allocated the most pages
274	* from it. Also, try make sure to allocate from allocation chunks that
275	* are almost full. Admittedly, both these measures might work counter to
276	* our intentions and its probably not worth putting a lot of effort,
277	* cpu time or memory into this.
278	*
279	*
280	* @subsection subsec_pgmPhys_SharePage Sharing a page
281	*
282	* The basic idea is that there there will be a idle priority kernel
283	* thread walking the non-shared VM pages hashing them and looking for
284	* pages with the same checksum. If such pages are found, it will compare
285	* them byte-by-byte to see if they actually are identical. If found to be
286	* identical it will allocate a shared page, copy the content, check that
287	* the page didn't change while doing this, and finally request both the
288	* VMs to use the shared page instead. If the page is all zeros (special
289	* checksum and byte-by-byte check) it will request the VM that owns it
290	* to replace it with the zero page.
291	*
292	* To make this efficient, we will have to make sure not to try share a page
293	* that will change its contents soon. This part requires the most work.
294	* A simple idea would be to request the VM to write monitor the page for
295	* a while to make sure it isn't modified any time soon. Also, it may
296	* make sense to skip pages that are being write monitored since this
297	* information is readily available to the thread if it works on the
298	* per-VM guest memory structures (presently called PGMRAMRANGE).
299	*
300	*
301	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
302	*
303	* The pages are organized in allocation chunks in ring-0, this is a necessity
304	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
305	* could easily work on a page-by-page basis if we liked. Whether this is possible
306	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
307	* become a problem as part of the idea here is that we wish to return memory to
308	* the host system.
309	*
310	* For instance, starting two VMs at the same time, they will both allocate the
311	* guest memory on-demand and if permitted their page allocations will be
312	* intermixed. Shut down one of the two VMs and it will be difficult to return
313	* any memory to the host system because the page allocation for the two VMs are
314	* mixed up in the same allocation chunks.
315	*
316	* To further complicate matters, when pages are freed because they have been
317	* ballooned or become shared/zero the whole idea is that the page is supposed
318	* to be reused by another VM or returned to the host system. This will cause
319	* allocation chunks to contain pages belonging to different VMs and prevent
320	* returning memory to the host when one of those VM shuts down.
321	*
322	* The only way to really deal with this problem is to move pages. This can
323	* either be done at VM shutdown and or by the idle priority worker thread
324	* that will be responsible for finding sharable/zero pages. The mechanisms
325	* involved for coercing a VM to move a page (or to do it for it) will be
326	* the same as when telling it to share/zero a page.
327	*
328	*
329	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
330	*
331	* There's a difficult balance between keeping the per-page tracking structures
332	* (global and guest page) easy to use and keeping them from eating too much
333	* memory. We have limited virtual memory resources available when operating in
334	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
335	* tracking structures will be attemted designed such that we can deal with up
336	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
337	*
338	*
339	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
340	*
341	* @see pg_GMM
342	*
343	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
344	*
345	* Fixed info is the physical address of the page (HCPhys) and the page id
346	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
347	* Today we've restricting ourselves to 40(-12) bits because this is the current
348	* restrictions of all AMD64 implementations (I think Barcelona will up this
349	* to 48(-12) bits, not that it really matters) and I needed the bits for
350	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
351	* decent range for the page id: 2^(28+12) = 1024TB.
352	*
353	* In additions to these, we'll have to keep maintaining the page flags as we
354	* currently do. Although it wouldn't harm to optimize these quite a bit, like
355	* for instance the ROM shouldn't depend on having a write handler installed
356	* in order for it to become read-only. A RO/RW bit should be considered so
357	* that the page syncing code doesn't have to mess about checking multiple
358	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
359	* figure out how to setup a shadow PTE. But this of course, is second
360	* priority at present. Current this requires 12 bits, but could probably
361	* be optimized to ~8.
362	*
363	* Then there's the 24 bits used to track which shadow page tables are
364	* currently mapping a page for the purpose of speeding up physical
365	* access handlers, and thereby the page pool cache. More bit for this
366	* purpose wouldn't hurt IIRC.
367	*
368	* Then there is a new bit in which we need to record what kind of page
369	* this is, shared, zero, normal or write-monitored-normal. This'll
370	* require 2 bits. One bit might be needed for indicating whether a
371	* write monitored page has been written to. And yet another one or
372	* two for tracking migration status. 3-4 bits total then.
373	*
374	* Whatever is left will can be used to record the sharabilitiy of a
375	* page. The page checksum will not be stored in the per-VM table as
376	* the idle thread will not be permitted to do modifications to it.
377	* It will instead have to keep its own working set of potentially
378	* shareable pages and their check sums and stuff.
379	*
380	* For the present we'll keep the current packing of the
381	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
382	* we'll have to change it to a struct with a total of 128-bits at
383	* our disposal.
384	*
385	* The initial layout will be like this:
386	* @verbatim
387	RTHCPHYS HCPhys; The current stuff.
388	63:40 Current shadow PT tracking stuff.
389	39:12 The physical page frame number.
390	11:0 The current flags.
391	uint32_t u28PageId : 28; The page id.
392	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
393	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
394	uint32_t u1Reserved : 1; Reserved for later.
395	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
396	@endverbatim
397	*
398	* The final layout will be something like this:
399	* @verbatim
400	RTHCPHYS HCPhys; The current stuff.
401	63:48 High page id (12+).
402	47:12 The physical page frame number.
403	11:0 Low page id.
404	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
405	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
406	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
407	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
408	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
409	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
410	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
411	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
412	@endverbatim
413	*
414	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
415	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
416	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
417	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
418	*
419	* A couple of cost examples for the total cost per-VM + kernel.
420	* 32-bit Windows and 32-bit linux:
421	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
422	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
423	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
424	* 64-bit Windows and 64-bit linux:
425	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
426	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
427	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
428	*
429	* UPDATE - 2007-09-27:
430	* Will need a ballooned flag/state too because we cannot
431	* trust the guest 100% and reporting the same page as ballooned more
432	* than once will put the GMM off balance.
433	*
434	*
435	* @subsection subsec_pgmPhys_Serializing Serializing Access
436	*
437	* Initially, we'll try a simple scheme:
438	*
439	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
440	* by the EMT thread of that VM while in the pgm critsect.
441	* - Other threads in the VM process that needs to make reliable use of
442	* the per-VM RAM tracking structures will enter the critsect.
443	* - No process external thread or kernel thread will ever try enter
444	* the pgm critical section, as that just won't work.
445	* - The idle thread (and similar threads) doesn't not need 100% reliable
446	* data when performing it tasks as the EMT thread will be the one to
447	* do the actual changes later anyway. So, as long as it only accesses
448	* the main ram range, it can do so by somehow preventing the VM from
449	* being destroyed while it works on it...
450	*
451	* - The over-commitment management, including the allocating/freeing
452	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
453	* more mundane mutex implementation is broken on Linux).
454	* - A separeate mutex is protecting the set of allocation chunks so
455	* that pages can be shared or/and freed up while some other VM is
456	* allocating more chunks. This mutex can be take from under the other
457	* one, but not the otherway around.
458	*
459	*
460	* @subsection subsec_pgmPhys_Request VM Request interface
461	*
462	* When in ring-0 it will become necessary to send requests to a VM so it can
463	* for instance move a page while defragmenting during VM destroy. The idle
464	* thread will make use of this interface to request VMs to setup shared
465	* pages and to perform write monitoring of pages.
466	*
467	* I would propose an interface similar to the current VMReq interface, similar
468	* in that it doesn't require locking and that the one sending the request may
469	* wait for completion if it wishes to. This shouldn't be very difficult to
470	* realize.
471	*
472	* The requests themselves are also pretty simple. They are basically:
473	* -# Check that some precondition is still true.
474	* -# Do the update.
475	* -# Update all shadow page tables involved with the page.
476	*
477	* The 3rd step is identical to what we're already doing when updating a
478	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
479	*
480	*
481	*
482	* @section sec_pgmPhys_MappingCaches Mapping Caches
483	*
484	* In order to be able to map in and out memory and to be able to support
485	* guest with more RAM than we've got virtual address space, we'll employing
486	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
487	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
488	* memory context for the HWACCM execution.
489	*
490	*
491	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
492	*
493	* We've considered implementing the ring-3 mapping cache page based but found
494	* that this was bother some when one had to take into account TLBs+SMP and
495	* portability (missing the necessary APIs on several platforms). There were
496	* also some performance concerns with this approach which hadn't quite been
497	* worked out.
498	*
499	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
500	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
501	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
502	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
503	* costly than a single page, although how much more costly is uncertain. We'll
504	* try address this by using a very big cache, preferably bigger than the actual
505	* VM RAM size if possible. The current VM RAM sizes should give some idea for
506	* 32-bit boxes, while on 64-bit we can probably get away with employing an
507	* unlimited cache.
508	*
509	* The cache have to parts, as already indicated, the ring-3 side and the
510	* ring-0 side.
511	*
512	* The ring-0 will be tied to the page allocator since it will operate on the
513	* memory objects it contains. It will therefore require the first ring-0 mutex
514	* discussed in @ref subsec_pgmPhys_Serializing. We
515	* some double house keeping wrt to who has mapped what I think, since both
516	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
517	*
518	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
519	* require anyone that desires to do changes to the mapping cache to do that
520	* from within this critsect. Alternatively, we could employ a separate critsect
521	* for serializing changes to the mapping cache as this would reduce potential
522	* contention with other threads accessing mappings unrelated to the changes
523	* that are in process. We can see about this later, contention will show
524	* up in the statistics anyway, so it'll be simple to tell.
525	*
526	* The organization of the ring-3 part will be very much like how the allocation
527	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
528	* having to walk the tree all the time, we'll have a couple of lookaside entries
529	* like in we do for I/O ports and MMIO in IOM.
530	*
531	* The simplified flow of a PGMPhysRead/Write function:
532	* -# Enter the PGM critsect.
533	* -# Lookup GCPhys in the ram ranges and get the Page ID.
534	* -# Calc the Allocation Chunk ID from the Page ID.
535	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
536	* If not found in cache:
537	* -# Call ring-0 and request it to be mapped and supply
538	* a chunk to be unmapped if the cache is maxed out already.
539	* -# Insert the new mapping into the AVL tree (id + R3 address).
540	* -# Update the relevant lookaside entry and return the mapping address.
541	* -# Do the read/write according to monitoring flags and everything.
542	* -# Leave the critsect.
543	*
544	*
545	* @section sec_pgmPhys_Fallback Fallback
546	*
547	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
548	* API and thus require a fallback.
549	*
550	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
551	* will return to the ring-3 caller (and later ring-0) and asking it to seed
552	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
553	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
554	* "SeededAllocPages" call to ring-0.
555	*
556	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
557	* all page sharing (zero page detection will continue). It will also force
558	* all allocations to come from the VM which seeded the page. Both these
559	* measures are taken to make sure that there will never be any need for
560	* mapping anything into ring-3 - everything will be mapped already.
561	*
562	* Whether we'll continue to use the current MM locked memory management
563	* for this I don't quite know (I'd prefer not to and just ditch that all
564	* togther), we'll see what's simplest to do.
565	*
566	*
567	*
568	* @section sec_pgmPhys_Changes Changes
569	*
570	* Breakdown of the changes involved?
571	*/
572
573
574	/** Saved state data unit version. */
575	#define PGM_SAVED_STATE_VERSION 6
576
577	/*******************************************************************************
578	* Header Files *
579	*******************************************************************************/
580	#define LOG_GROUP LOG_GROUP_PGM
581	#include <VBox/dbgf.h>
582	#include <VBox/pgm.h>
583	#include <VBox/cpum.h>
584	#include <VBox/iom.h>
585	#include <VBox/sup.h>
586	#include <VBox/mm.h>
587	#include <VBox/em.h>
588	#include <VBox/stam.h>
589	#include <VBox/rem.h>
590	#include <VBox/dbgf.h>
591	#include <VBox/rem.h>
592	#include <VBox/selm.h>
593	#include <VBox/ssm.h>
594	#include "PGMInternal.h"
595	#include <VBox/vm.h>
596	#include <VBox/dbg.h>
597	#include <VBox/hwaccm.h>
598
599	#include <iprt/assert.h>
600	#include <iprt/alloc.h>
601	#include <iprt/asm.h>
602	#include <iprt/thread.h>
603	#include <iprt/string.h>
604	#ifdef DEBUG_bird
605	# include <iprt/env.h>
606	#endif
607	#include <VBox/param.h>
608	#include <VBox/err.h>
609
610
611
612	/*******************************************************************************
613	* Internal Functions *
614	*******************************************************************************/
615	static int pgmR3InitPaging(PVM pVM);
616	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
617	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
618	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
619	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
620	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
621	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
622	#ifdef VBOX_STRICT
623	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
624	#endif
625	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
626	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
627	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
628	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
629	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
630
631	#ifdef VBOX_WITH_STATISTICS
632	static void pgmR3InitStats(PVM pVM);
633	#endif
634
635	#ifdef VBOX_WITH_DEBUGGER
636	/** @todo all but the two last commands must be converted to 'info'. */
637	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	# ifdef VBOX_STRICT
642	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
643	# endif
644	#endif
645
646
647	/*******************************************************************************
648	* Global Variables *
649	*******************************************************************************/
650	#ifdef VBOX_WITH_DEBUGGER
651	/** Command descriptors. */
652	static const DBGCCMD g_aCmds[] =
653	{
654	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
655	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
656	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
657	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
658	#ifdef VBOX_STRICT
659	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
660	#endif
661	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
662	};
663	#endif
664
665
666
667
668	/*
669	* Shadow - 32-bit mode
670	*/
671	#define PGM_SHW_TYPE PGM_TYPE_32BIT
672	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
673	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
674	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
675	#include "PGMShw.h"
676
677	/* Guest - real mode */
678	#define PGM_GST_TYPE PGM_TYPE_REAL
679	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
680	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
681	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
682	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
683	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
684	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
685	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
686	#include "PGMGst.h"
687	#include "PGMBth.h"
688	#undef BTH_PGMPOOLKIND_PT_FOR_PT
689	#undef PGM_BTH_NAME
690	#undef PGM_BTH_NAME_RC_STR
691	#undef PGM_BTH_NAME_R0_STR
692	#undef PGM_GST_TYPE
693	#undef PGM_GST_NAME
694	#undef PGM_GST_NAME_RC_STR
695	#undef PGM_GST_NAME_R0_STR
696
697	/* Guest - protected mode */
698	#define PGM_GST_TYPE PGM_TYPE_PROT
699	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
700	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
701	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
702	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
703	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
704	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
705	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
706	#include "PGMGst.h"
707	#include "PGMBth.h"
708	#undef BTH_PGMPOOLKIND_PT_FOR_PT
709	#undef PGM_BTH_NAME
710	#undef PGM_BTH_NAME_RC_STR
711	#undef PGM_BTH_NAME_R0_STR
712	#undef PGM_GST_TYPE
713	#undef PGM_GST_NAME
714	#undef PGM_GST_NAME_RC_STR
715	#undef PGM_GST_NAME_R0_STR
716
717	/* Guest - 32-bit mode */
718	#define PGM_GST_TYPE PGM_TYPE_32BIT
719	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
720	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
721	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
722	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
723	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
724	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
725	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
726	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
727	#include "PGMGst.h"
728	#include "PGMBth.h"
729	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
730	#undef BTH_PGMPOOLKIND_PT_FOR_PT
731	#undef PGM_BTH_NAME
732	#undef PGM_BTH_NAME_RC_STR
733	#undef PGM_BTH_NAME_R0_STR
734	#undef PGM_GST_TYPE
735	#undef PGM_GST_NAME
736	#undef PGM_GST_NAME_RC_STR
737	#undef PGM_GST_NAME_R0_STR
738
739	#undef PGM_SHW_TYPE
740	#undef PGM_SHW_NAME
741	#undef PGM_SHW_NAME_RC_STR
742	#undef PGM_SHW_NAME_R0_STR
743
744
745	/*
746	* Shadow - PAE mode
747	*/
748	#define PGM_SHW_TYPE PGM_TYPE_PAE
749	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
750	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
751	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
752	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
753	#include "PGMShw.h"
754
755	/* Guest - real mode */
756	#define PGM_GST_TYPE PGM_TYPE_REAL
757	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
758	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
759	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
760	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
761	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
762	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
763	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
764	#include "PGMBth.h"
765	#undef BTH_PGMPOOLKIND_PT_FOR_PT
766	#undef PGM_BTH_NAME
767	#undef PGM_BTH_NAME_RC_STR
768	#undef PGM_BTH_NAME_R0_STR
769	#undef PGM_GST_TYPE
770	#undef PGM_GST_NAME
771	#undef PGM_GST_NAME_RC_STR
772	#undef PGM_GST_NAME_R0_STR
773
774	/* Guest - protected mode */
775	#define PGM_GST_TYPE PGM_TYPE_PROT
776	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
777	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
778	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
779	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
780	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
781	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
782	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
783	#include "PGMBth.h"
784	#undef BTH_PGMPOOLKIND_PT_FOR_PT
785	#undef PGM_BTH_NAME
786	#undef PGM_BTH_NAME_RC_STR
787	#undef PGM_BTH_NAME_R0_STR
788	#undef PGM_GST_TYPE
789	#undef PGM_GST_NAME
790	#undef PGM_GST_NAME_RC_STR
791	#undef PGM_GST_NAME_R0_STR
792
793	/* Guest - 32-bit mode */
794	#define PGM_GST_TYPE PGM_TYPE_32BIT
795	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
796	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
797	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
798	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
799	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
800	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
801	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
802	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
803	#include "PGMBth.h"
804	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
805	#undef BTH_PGMPOOLKIND_PT_FOR_PT
806	#undef PGM_BTH_NAME
807	#undef PGM_BTH_NAME_RC_STR
808	#undef PGM_BTH_NAME_R0_STR
809	#undef PGM_GST_TYPE
810	#undef PGM_GST_NAME
811	#undef PGM_GST_NAME_RC_STR
812	#undef PGM_GST_NAME_R0_STR
813
814	/* Guest - PAE mode */
815	#define PGM_GST_TYPE PGM_TYPE_PAE
816	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
817	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
818	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
819	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
820	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
821	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
822	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
823	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
824	#include "PGMGst.h"
825	#include "PGMBth.h"
826	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
827	#undef BTH_PGMPOOLKIND_PT_FOR_PT
828	#undef PGM_BTH_NAME
829	#undef PGM_BTH_NAME_RC_STR
830	#undef PGM_BTH_NAME_R0_STR
831	#undef PGM_GST_TYPE
832	#undef PGM_GST_NAME
833	#undef PGM_GST_NAME_RC_STR
834	#undef PGM_GST_NAME_R0_STR
835
836	#undef PGM_SHW_TYPE
837	#undef PGM_SHW_NAME
838	#undef PGM_SHW_NAME_RC_STR
839	#undef PGM_SHW_NAME_R0_STR
840
841
842	/*
843	* Shadow - AMD64 mode
844	*/
845	#define PGM_SHW_TYPE PGM_TYPE_AMD64
846	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
847	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
848	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
849	#include "PGMShw.h"
850
851	#ifdef VBOX_WITH_64_BITS_GUESTS
852	/* Guest - AMD64 mode */
853	# define PGM_GST_TYPE PGM_TYPE_AMD64
854	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
855	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
856	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
857	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
858	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
859	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
860	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
861	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
862	# include "PGMGst.h"
863	# include "PGMBth.h"
864	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
865	# undef BTH_PGMPOOLKIND_PT_FOR_PT
866	# undef PGM_BTH_NAME
867	# undef PGM_BTH_NAME_RC_STR
868	# undef PGM_BTH_NAME_R0_STR
869	# undef PGM_GST_TYPE
870	# undef PGM_GST_NAME
871	# undef PGM_GST_NAME_RC_STR
872	# undef PGM_GST_NAME_R0_STR
873	#endif /* VBOX_WITH_64_BITS_GUESTS */
874
875	#undef PGM_SHW_TYPE
876	#undef PGM_SHW_NAME
877	#undef PGM_SHW_NAME_RC_STR
878	#undef PGM_SHW_NAME_R0_STR
879
880
881	/*
882	* Shadow - Nested paging mode
883	*/
884	#define PGM_SHW_TYPE PGM_TYPE_NESTED
885	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
886	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
887	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
888	#include "PGMShw.h"
889
890	/* Guest - real mode */
891	#define PGM_GST_TYPE PGM_TYPE_REAL
892	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
893	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
894	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
895	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
896	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
897	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
898	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
899	#include "PGMBth.h"
900	#undef BTH_PGMPOOLKIND_PT_FOR_PT
901	#undef PGM_BTH_NAME
902	#undef PGM_BTH_NAME_RC_STR
903	#undef PGM_BTH_NAME_R0_STR
904	#undef PGM_GST_TYPE
905	#undef PGM_GST_NAME
906	#undef PGM_GST_NAME_RC_STR
907	#undef PGM_GST_NAME_R0_STR
908
909	/* Guest - protected mode */
910	#define PGM_GST_TYPE PGM_TYPE_PROT
911	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
912	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
913	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
914	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
915	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
916	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
917	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
918	#include "PGMBth.h"
919	#undef BTH_PGMPOOLKIND_PT_FOR_PT
920	#undef PGM_BTH_NAME
921	#undef PGM_BTH_NAME_RC_STR
922	#undef PGM_BTH_NAME_R0_STR
923	#undef PGM_GST_TYPE
924	#undef PGM_GST_NAME
925	#undef PGM_GST_NAME_RC_STR
926	#undef PGM_GST_NAME_R0_STR
927
928	/* Guest - 32-bit mode */
929	#define PGM_GST_TYPE PGM_TYPE_32BIT
930	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
931	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
932	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
933	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
934	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
935	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
936	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
937	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
938	#include "PGMBth.h"
939	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
940	#undef BTH_PGMPOOLKIND_PT_FOR_PT
941	#undef PGM_BTH_NAME
942	#undef PGM_BTH_NAME_RC_STR
943	#undef PGM_BTH_NAME_R0_STR
944	#undef PGM_GST_TYPE
945	#undef PGM_GST_NAME
946	#undef PGM_GST_NAME_RC_STR
947	#undef PGM_GST_NAME_R0_STR
948
949	/* Guest - PAE mode */
950	#define PGM_GST_TYPE PGM_TYPE_PAE
951	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
952	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
953	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
954	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
955	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
956	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
957	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
958	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
959	#include "PGMBth.h"
960	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
961	#undef BTH_PGMPOOLKIND_PT_FOR_PT
962	#undef PGM_BTH_NAME
963	#undef PGM_BTH_NAME_RC_STR
964	#undef PGM_BTH_NAME_R0_STR
965	#undef PGM_GST_TYPE
966	#undef PGM_GST_NAME
967	#undef PGM_GST_NAME_RC_STR
968	#undef PGM_GST_NAME_R0_STR
969
970	#ifdef VBOX_WITH_64_BITS_GUESTS
971	/* Guest - AMD64 mode */
972	# define PGM_GST_TYPE PGM_TYPE_AMD64
973	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
974	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
975	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
976	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
977	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
978	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
979	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
980	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
981	# include "PGMBth.h"
982	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
983	# undef BTH_PGMPOOLKIND_PT_FOR_PT
984	# undef PGM_BTH_NAME
985	# undef PGM_BTH_NAME_RC_STR
986	# undef PGM_BTH_NAME_R0_STR
987	# undef PGM_GST_TYPE
988	# undef PGM_GST_NAME
989	# undef PGM_GST_NAME_RC_STR
990	# undef PGM_GST_NAME_R0_STR
991	#endif /* VBOX_WITH_64_BITS_GUESTS */
992
993	#undef PGM_SHW_TYPE
994	#undef PGM_SHW_NAME
995	#undef PGM_SHW_NAME_RC_STR
996	#undef PGM_SHW_NAME_R0_STR
997
998
999	/*
1000	* Shadow - EPT
1001	*/
1002	#define PGM_SHW_TYPE PGM_TYPE_EPT
1003	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1004	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1005	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1006	#include "PGMShw.h"
1007
1008	/* Guest - real mode */
1009	#define PGM_GST_TYPE PGM_TYPE_REAL
1010	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1011	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1012	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1013	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1014	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1015	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1016	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1017	#include "PGMBth.h"
1018	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1019	#undef PGM_BTH_NAME
1020	#undef PGM_BTH_NAME_RC_STR
1021	#undef PGM_BTH_NAME_R0_STR
1022	#undef PGM_GST_TYPE
1023	#undef PGM_GST_NAME
1024	#undef PGM_GST_NAME_RC_STR
1025	#undef PGM_GST_NAME_R0_STR
1026
1027	/* Guest - protected mode */
1028	#define PGM_GST_TYPE PGM_TYPE_PROT
1029	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1030	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1031	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1032	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1033	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1034	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1035	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1036	#include "PGMBth.h"
1037	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1038	#undef PGM_BTH_NAME
1039	#undef PGM_BTH_NAME_RC_STR
1040	#undef PGM_BTH_NAME_R0_STR
1041	#undef PGM_GST_TYPE
1042	#undef PGM_GST_NAME
1043	#undef PGM_GST_NAME_RC_STR
1044	#undef PGM_GST_NAME_R0_STR
1045
1046	/* Guest - 32-bit mode */
1047	#define PGM_GST_TYPE PGM_TYPE_32BIT
1048	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1049	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1050	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1051	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1052	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1053	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1054	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1055	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1056	#include "PGMBth.h"
1057	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1058	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1059	#undef PGM_BTH_NAME
1060	#undef PGM_BTH_NAME_RC_STR
1061	#undef PGM_BTH_NAME_R0_STR
1062	#undef PGM_GST_TYPE
1063	#undef PGM_GST_NAME
1064	#undef PGM_GST_NAME_RC_STR
1065	#undef PGM_GST_NAME_R0_STR
1066
1067	/* Guest - PAE mode */
1068	#define PGM_GST_TYPE PGM_TYPE_PAE
1069	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1070	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1071	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1072	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1073	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1074	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1075	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1076	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1077	#include "PGMBth.h"
1078	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1079	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1080	#undef PGM_BTH_NAME
1081	#undef PGM_BTH_NAME_RC_STR
1082	#undef PGM_BTH_NAME_R0_STR
1083	#undef PGM_GST_TYPE
1084	#undef PGM_GST_NAME
1085	#undef PGM_GST_NAME_RC_STR
1086	#undef PGM_GST_NAME_R0_STR
1087
1088	#ifdef VBOX_WITH_64_BITS_GUESTS
1089	/* Guest - AMD64 mode */
1090	# define PGM_GST_TYPE PGM_TYPE_AMD64
1091	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1092	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1093	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1094	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1095	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1096	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1097	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1098	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1099	# include "PGMBth.h"
1100	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1101	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1102	# undef PGM_BTH_NAME
1103	# undef PGM_BTH_NAME_RC_STR
1104	# undef PGM_BTH_NAME_R0_STR
1105	# undef PGM_GST_TYPE
1106	# undef PGM_GST_NAME
1107	# undef PGM_GST_NAME_RC_STR
1108	# undef PGM_GST_NAME_R0_STR
1109	#endif /* VBOX_WITH_64_BITS_GUESTS */
1110
1111	#undef PGM_SHW_TYPE
1112	#undef PGM_SHW_NAME
1113	#undef PGM_SHW_NAME_RC_STR
1114	#undef PGM_SHW_NAME_R0_STR
1115
1116
1117
1118	/**
1119	* Initiates the paging of VM.
1120	*
1121	* @returns VBox status code.
1122	* @param pVM Pointer to VM structure.
1123	*/
1124	VMMR3DECL(int) PGMR3Init(PVM pVM)
1125	{
1126	LogFlow(("PGMR3Init:\n"));
1127
1128	/*
1129	* Assert alignment and sizes.
1130	*/
1131	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1132
1133	/*
1134	* Init the structure.
1135	*/
1136	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1137	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1138	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1139	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1140	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1141	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1142	pVM->pgm.s.fA20Enabled = true;
1143	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1144	pVM->pgm.s.pGstPaePDPTHC = NULL;
1145	pVM->pgm.s.pGstPaePDPTGC = 0;
1146	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
1147	{
1148	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
1149	pVM->pgm.s.apGstPaePDsGC[i] = 0;
1150	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1151	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1152	}
1153
1154	#ifdef VBOX_STRICT
1155	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1156	#endif
1157
1158	/*
1159	* Get the configured RAM size - to estimate saved state size.
1160	*/
1161	uint64_t cbRam;
1162	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1163	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1164	cbRam = pVM->pgm.s.cbRamSize = 0;
1165	else if (VBOX_SUCCESS(rc))
1166	{
1167	if (cbRam < PAGE_SIZE)
1168	cbRam = 0;
1169	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1170	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1171	}
1172	else
1173	{
1174	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
1175	return rc;
1176	}
1177
1178	/*
1179	* Register saved state data unit.
1180	*/
1181	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1182	NULL, pgmR3Save, NULL,
1183	NULL, pgmR3Load, NULL);
1184	if (VBOX_FAILURE(rc))
1185	return rc;
1186
1187	/*
1188	* Initialize the PGM critical section and flush the phys TLBs
1189	*/
1190	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1191	AssertRCReturn(rc, rc);
1192
1193	PGMR3PhysChunkInvalidateTLB(pVM);
1194	PGMPhysInvalidatePageR3MapTLB(pVM);
1195	PGMPhysInvalidatePageR0MapTLB(pVM);
1196	PGMPhysInvalidatePageGCMapTLB(pVM);
1197
1198	/*
1199	* Trees
1200	*/
1201	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1202	if (VBOX_SUCCESS(rc))
1203	{
1204	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1205	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1206
1207	/*
1208	* Alocate the zero page.
1209	*/
1210	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1211	}
1212	if (VBOX_SUCCESS(rc))
1213	{
1214	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1215	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1216	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1217	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1218	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1219
1220	/*
1221	* Init the paging.
1222	*/
1223	rc = pgmR3InitPaging(pVM);
1224	}
1225	if (VBOX_SUCCESS(rc))
1226	{
1227	/*
1228	* Init the page pool.
1229	*/
1230	rc = pgmR3PoolInit(pVM);
1231	}
1232	if (VBOX_SUCCESS(rc))
1233	{
1234	/*
1235	* Info & statistics
1236	*/
1237	DBGFR3InfoRegisterInternal(pVM, "mode",
1238	"Shows the current paging mode. "
1239	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1240	pgmR3InfoMode);
1241	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1242	"Dumps all the entries in the top level paging table. No arguments.",
1243	pgmR3InfoCr3);
1244	DBGFR3InfoRegisterInternal(pVM, "phys",
1245	"Dumps all the physical address ranges. No arguments.",
1246	pgmR3PhysInfo);
1247	DBGFR3InfoRegisterInternal(pVM, "handlers",
1248	"Dumps physical, virtual and hyper virtual handlers. "
1249	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1250	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1251	pgmR3InfoHandlers);
1252	DBGFR3InfoRegisterInternal(pVM, "mappings",
1253	"Dumps guest mappings.",
1254	pgmR3MapInfo);
1255
1256	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1257	#ifdef VBOX_WITH_STATISTICS
1258	pgmR3InitStats(pVM);
1259	#endif
1260	#ifdef VBOX_WITH_DEBUGGER
1261	/*
1262	* Debugger commands.
1263	*/
1264	static bool fRegisteredCmds = false;
1265	if (!fRegisteredCmds)
1266	{
1267	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1268	if (VBOX_SUCCESS(rc))
1269	fRegisteredCmds = true;
1270	}
1271	#endif
1272	return VINF_SUCCESS;
1273	}
1274
1275	/* Almost no cleanup necessary, MM frees all memory. */
1276	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1277
1278	return rc;
1279	}
1280
1281
1282	/**
1283	* Init paging.
1284	*
1285	* Since we need to check what mode the host is operating in before we can choose
1286	* the right paging functions for the host we have to delay this until R0 has
1287	* been initialized.
1288	*
1289	* @returns VBox status code.
1290	* @param pVM VM handle.
1291	*/
1292	static int pgmR3InitPaging(PVM pVM)
1293	{
1294	/*
1295	* Force a recalculation of modes and switcher so everyone gets notified.
1296	*/
1297	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1298	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1299	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1300
1301	/*
1302	* Allocate static mapping space for whatever the cr3 register
1303	* points to and in the case of PAE mode to the 4 PDs.
1304	*/
1305	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1306	if (VBOX_FAILURE(rc))
1307	{
1308	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1309	return rc;
1310	}
1311	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1312
1313	/*
1314	* Allocate pages for the three possible intermediate contexts
1315	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1316	* for the sake of simplicity. The AMD64 uses the PAE for the
1317	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1318	*
1319	* We assume that two page tables will be enought for the core code
1320	* mappings (HC virtual and identity).
1321	*/
1322	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1323	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1324	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1325	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1326	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1327	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1328	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1329	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1330	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1331	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1332	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1333	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1334	if ( !pVM->pgm.s.pInterPD
1335	\|\| !pVM->pgm.s.apInterPTs[0]
1336	\|\| !pVM->pgm.s.apInterPTs[1]
1337	\|\| !pVM->pgm.s.apInterPaePTs[0]
1338	\|\| !pVM->pgm.s.apInterPaePTs[1]
1339	\|\| !pVM->pgm.s.apInterPaePDs[0]
1340	\|\| !pVM->pgm.s.apInterPaePDs[1]
1341	\|\| !pVM->pgm.s.apInterPaePDs[2]
1342	\|\| !pVM->pgm.s.apInterPaePDs[3]
1343	\|\| !pVM->pgm.s.pInterPaePDPT
1344	\|\| !pVM->pgm.s.pInterPaePDPT64
1345	\|\| !pVM->pgm.s.pInterPaePML4)
1346	{
1347	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1348	return VERR_NO_PAGE_MEMORY;
1349	}
1350
1351	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1352	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1353	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1354	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1355	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1356	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1357
1358	/*
1359	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1360	*/
1361	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1362	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1363	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1364
1365	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1366	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1367
1368	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1369	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1370	{
1371	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1372	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1373	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1374	}
1375
1376	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1377	{
1378	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1379	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1380	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1381	}
1382
1383	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1384	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1385	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1386	\| HCPhysInterPaePDPT64;
1387
1388	/*
1389	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1390	* We allocate pages for all three posibilities in order to simplify mappings and
1391	* avoid resource failure during mode switches. So, we need to cover all levels of the
1392	* of the first 4GB down to PD level.
1393	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1394	*/
1395	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1396	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1397	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1398	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1399	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1400	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1401	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1402	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1403	pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1404	pVM->pgm.s.pHCNestedRoot = MMR3PageAllocLow(pVM);
1405
1406	if ( !pVM->pgm.s.pHC32BitPD
1407	\|\| !pVM->pgm.s.apHCPaePDs[0]
1408	\|\| !pVM->pgm.s.apHCPaePDs[1]
1409	\|\| !pVM->pgm.s.apHCPaePDs[2]
1410	\|\| !pVM->pgm.s.apHCPaePDs[3]
1411	\|\| !pVM->pgm.s.pHCPaePDPT
1412	\|\| !pVM->pgm.s.pHCNestedRoot)
1413	{
1414	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1415	return VERR_NO_PAGE_MEMORY;
1416	}
1417
1418	/* get physical addresses. */
1419	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1420	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1421	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1422	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1423	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1424	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1425	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
1426	pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pHCNestedRoot);
1427
1428	/*
1429	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1430	*/
1431	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1432	ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
1433	ASMMemZero32(pVM->pgm.s.pHCNestedRoot, PAGE_SIZE);
1434	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1435	{
1436	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1437	pVM->pgm.s.pHCPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1438	/* The flags will be corrected when entering and leaving long mode. */
1439	}
1440
1441	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1442
1443	/*
1444	* Initialize paging workers and mode from current host mode
1445	* and the guest running in real mode.
1446	*/
1447	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1448	switch (pVM->pgm.s.enmHostMode)
1449	{
1450	case SUPPAGINGMODE_32_BIT:
1451	case SUPPAGINGMODE_32_BIT_GLOBAL:
1452	case SUPPAGINGMODE_PAE:
1453	case SUPPAGINGMODE_PAE_GLOBAL:
1454	case SUPPAGINGMODE_PAE_NX:
1455	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1456	break;
1457
1458	case SUPPAGINGMODE_AMD64:
1459	case SUPPAGINGMODE_AMD64_GLOBAL:
1460	case SUPPAGINGMODE_AMD64_NX:
1461	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1462	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1463	if (ARCH_BITS != 64)
1464	{
1465	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1466	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1467	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1468	}
1469	#endif
1470	break;
1471	default:
1472	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1473	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1474	}
1475	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1476	if (VBOX_SUCCESS(rc))
1477	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1478	if (VBOX_SUCCESS(rc))
1479	{
1480	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1481	#if HC_ARCH_BITS == 64
1482	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysPaePDPT=%RHp HCPhysPaePML4=%RHp\n",
1483	pVM->pgm.s.HCPhys32BitPD,
1484	pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1485	pVM->pgm.s.HCPhysPaePDPT,
1486	pVM->pgm.s.HCPhysPaePML4));
1487	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1488	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1489	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1490	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1491	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1492	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1493	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1494	#endif
1495
1496	return VINF_SUCCESS;
1497	}
1498
1499	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1500	return rc;
1501	}
1502
1503
1504	#ifdef VBOX_WITH_STATISTICS
1505	/**
1506	* Init statistics
1507	*/
1508	static void pgmR3InitStats(PVM pVM)
1509	{
1510	PPGM pPGM = &pVM->pgm.s;
1511	unsigned i;
1512
1513	/*
1514	* Note! The layout of this function matches the member layout exactly!
1515	*/
1516
1517	/* Common - misc variables */
1518	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1519	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1520	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1521	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1522	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1523	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1524
1525	/* Common - stats */
1526	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1527	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1528	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1529	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1530	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1531	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1532	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1533	#endif
1534	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1535	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1536	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1537	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1538	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1539	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1540
1541	/* R3 only: */
1542	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1543	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1544	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1545	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1546	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1547	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1548
1549	/* GC only: */
1550	STAM_REG(pVM, &pPGM->StatRCInvalidatePage, STAMTYPE_PROFILE, "/PGM/RC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1551	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1552	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1553
1554	/* RZ only: */
1555	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1556	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1557	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1558	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1559	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1560	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1561	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1562	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1563	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1564	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1565	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1566	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1567	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1568	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1569	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1570	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1571	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1572	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1573	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1574	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1575	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1576	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1577	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1578	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1579	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1580	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1581	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1582	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1583	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1584	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1585	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1586	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1587	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1588	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1589	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1590	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1591	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1592	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1593	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1594	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1595	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1596	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1597	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1598	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1599	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1600	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1601	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1602	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1603	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1604	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1605	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1606
1607	/* HC only: */
1608
1609	/* RZ & R3: */
1610	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1611	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1612	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1613	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1614	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1615	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1616	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1617	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1618	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1619	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1620	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1621	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1622	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1623	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1624	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1625	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1626	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1627	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1628	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1629	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1630	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1631	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1632	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1633	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1634	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1635	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1636	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1637	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1638	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1639	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1640	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1641	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1642	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1643	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1644	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1645	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1646	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1647	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1648	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1649	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1650	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1651	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1652	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1653	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1654	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1655	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1656	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1657	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1658	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1659	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1660	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1661	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1662	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1663	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1664
1665	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1666	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1667	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1668	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1669	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1670	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1671	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1672	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1673	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1674	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1675	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1676	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1677	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1678	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1679	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1680	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1681	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1682	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1683	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1684	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1685	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1686	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1687	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1688	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1689	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1690	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1691	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1692	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1693	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1694	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1695	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1696	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1697	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1698	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1699	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1700	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1701	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1702	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1703	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1704	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1705	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1706	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1707	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1708	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1709	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1710	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1711	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1712	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1713	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1714	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1715	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1716	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1717	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1718	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1719
1720	}
1721	#endif /* VBOX_WITH_STATISTICS */
1722
1723
1724	/**
1725	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1726	*
1727	* The dynamic mapping area will also be allocated and initialized at this
1728	* time. We could allocate it during PGMR3Init of course, but the mapping
1729	* wouldn't be allocated at that time preventing us from setting up the
1730	* page table entries with the dummy page.
1731	*
1732	* @returns VBox status code.
1733	* @param pVM VM handle.
1734	*/
1735	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1736	{
1737	RTGCPTR GCPtr;
1738	/*
1739	* Reserve space for mapping the paging pages into guest context.
1740	*/
1741	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &GCPtr);
1742	AssertRCReturn(rc, rc);
1743	pVM->pgm.s.pGC32BitPD = GCPtr;
1744	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1745
1746	/*
1747	* Reserve space for the dynamic mappings.
1748	*/
1749	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1750	if (VBOX_SUCCESS(rc))
1751	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1752
1753	if ( VBOX_SUCCESS(rc)
1754	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1755	{
1756	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1757	if (VBOX_SUCCESS(rc))
1758	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1759	}
1760	if (VBOX_SUCCESS(rc))
1761	{
1762	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1763	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1764	}
1765	return rc;
1766	}
1767
1768
1769	/**
1770	* Ring-3 init finalizing.
1771	*
1772	* @returns VBox status code.
1773	* @param pVM The VM handle.
1774	*/
1775	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1776	{
1777	/*
1778	* Map the paging pages into the guest context.
1779	*/
1780	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1781	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1782
1783	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1784	AssertRCReturn(rc, rc);
1785	pVM->pgm.s.pGC32BitPD = GCPtr;
1786	GCPtr += PAGE_SIZE;
1787	GCPtr += PAGE_SIZE; /* reserved page */
1788
1789	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1790	{
1791	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1792	AssertRCReturn(rc, rc);
1793	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1794	GCPtr += PAGE_SIZE;
1795	}
1796	/* A bit of paranoia is justified. */
1797	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1798	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1799	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1800	GCPtr += PAGE_SIZE; /* reserved page */
1801
1802	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1803	AssertRCReturn(rc, rc);
1804	pVM->pgm.s.pGCPaePDPT = GCPtr;
1805	GCPtr += PAGE_SIZE;
1806	GCPtr += PAGE_SIZE; /* reserved page */
1807
1808
1809	/*
1810	* Reserve space for the dynamic mappings.
1811	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1812	*/
1813	/* get the pointer to the page table entries. */
1814	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1815	AssertRelease(pMapping);
1816	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1817	const unsigned iPT = off >> X86_PD_SHIFT;
1818	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1819	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1820	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1821
1822	/* init cache */
1823	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1824	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1825	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1826
1827	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1828	{
1829	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1830	AssertRCReturn(rc, rc);
1831	}
1832
1833	/*
1834	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1835	* Intel only goes up to 36 bits, so we stick to 36 as well.
1836	*/
1837	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1838	uint32_t u32Dummy, u32Features;
1839	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1840
1841	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1842	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1843	else
1844	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1845
1846	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1847
1848	return rc;
1849	}
1850
1851
1852	/**
1853	* Applies relocations to data and code managed by this component.
1854	*
1855	* This function will be called at init and whenever the VMM need to relocate it
1856	* self inside the GC.
1857	*
1858	* @param pVM The VM.
1859	* @param offDelta Relocation delta relative to old location.
1860	*/
1861	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1862	{
1863	LogFlow(("PGMR3Relocate\n"));
1864
1865	/*
1866	* Paging stuff.
1867	*/
1868	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1869	/** @todo move this into shadow and guest specific relocation functions. */
1870	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1871	pVM->pgm.s.pGC32BitPD += offDelta;
1872	pVM->pgm.s.pGuestPDGC += offDelta;
1873	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apGCPaePDs) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsGC));
1874	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1875	{
1876	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1877	pVM->pgm.s.apGstPaePDsGC[i] += offDelta;
1878	}
1879	pVM->pgm.s.pGstPaePDPTGC += offDelta;
1880	pVM->pgm.s.pGCPaePDPT += offDelta;
1881
1882	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1883	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1884
1885	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1886	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1887	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1888
1889	/*
1890	* Trees.
1891	*/
1892	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1893
1894	/*
1895	* Ram ranges.
1896	*/
1897	if (pVM->pgm.s.pRamRangesR3)
1898	{
1899	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1900	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1901	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1902	}
1903
1904	/*
1905	* Update the two page directories with all page table mappings.
1906	* (One or more of them have changed, that's why we're here.)
1907	*/
1908	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1909	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1910	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1911
1912	/* Relocate GC addresses of Page Tables. */
1913	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1914	{
1915	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1916	{
1917	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1918	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1919	}
1920	}
1921
1922	/*
1923	* Dynamic page mapping area.
1924	*/
1925	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1926	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1927	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1928
1929	/*
1930	* The Zero page.
1931	*/
1932	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1933	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1934
1935	/*
1936	* Physical and virtual handlers.
1937	*/
1938	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1939	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1940	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1941
1942	/*
1943	* The page pool.
1944	*/
1945	pgmR3PoolRelocate(pVM);
1946	}
1947
1948
1949	/**
1950	* Callback function for relocating a physical access handler.
1951	*
1952	* @returns 0 (continue enum)
1953	* @param pNode Pointer to a PGMPHYSHANDLER node.
1954	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1955	* not certain the delta will fit in a void pointer for all possible configs.
1956	*/
1957	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1958	{
1959	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1960	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1961	if (pHandler->pfnHandlerRC)
1962	pHandler->pfnHandlerRC += offDelta;
1963	if (pHandler->pvUserRC >= 0x10000)
1964	pHandler->pvUserRC += offDelta;
1965	return 0;
1966	}
1967
1968
1969	/**
1970	* Callback function for relocating a virtual access handler.
1971	*
1972	* @returns 0 (continue enum)
1973	* @param pNode Pointer to a PGMVIRTHANDLER node.
1974	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1975	* not certain the delta will fit in a void pointer for all possible configs.
1976	*/
1977	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1978	{
1979	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1980	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1981	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
1982	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
1983	Assert(pHandler->pfnHandlerRC);
1984	pHandler->pfnHandlerRC += offDelta;
1985	return 0;
1986	}
1987
1988
1989	/**
1990	* Callback function for relocating a virtual access handler for the hypervisor mapping.
1991	*
1992	* @returns 0 (continue enum)
1993	* @param pNode Pointer to a PGMVIRTHANDLER node.
1994	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1995	* not certain the delta will fit in a void pointer for all possible configs.
1996	*/
1997	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1998	{
1999	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2000	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2001	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2002	Assert(pHandler->pfnHandlerRC);
2003	pHandler->pfnHandlerRC += offDelta;
2004	return 0;
2005	}
2006
2007
2008	/**
2009	* The VM is being reset.
2010	*
2011	* For the PGM component this means that any PD write monitors
2012	* needs to be removed.
2013	*
2014	* @param pVM VM handle.
2015	*/
2016	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2017	{
2018	LogFlow(("PGMR3Reset:\n"));
2019	VM_ASSERT_EMT(pVM);
2020
2021	pgmLock(pVM);
2022
2023	/*
2024	* Unfix any fixed mappings and disable CR3 monitoring.
2025	*/
2026	pVM->pgm.s.fMappingsFixed = false;
2027	pVM->pgm.s.GCPtrMappingFixed = 0;
2028	pVM->pgm.s.cbMappingFixed = 0;
2029
2030	/* Exit the guest paging mode before the pgm pool gets reset.
2031	* Important to clean up the amd64 case.
2032	*/
2033	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2034	AssertRC(rc);
2035	#ifdef DEBUG
2036	DBGFR3InfoLog(pVM, "mappings", NULL);
2037	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2038	#endif
2039
2040	/*
2041	* Reset the shadow page pool.
2042	*/
2043	pgmR3PoolReset(pVM);
2044
2045	/*
2046	* Re-init other members.
2047	*/
2048	pVM->pgm.s.fA20Enabled = true;
2049
2050	/*
2051	* Clear the FFs PGM owns.
2052	*/
2053	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2054	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2055
2056	/*
2057	* Reset (zero) RAM pages.
2058	*/
2059	rc = pgmR3PhysRamReset(pVM);
2060	if (RT_SUCCESS(rc))
2061	{
2062	#ifdef VBOX_WITH_NEW_PHYS_CODE
2063	/*
2064	* Reset (zero) shadow ROM pages.
2065	*/
2066	rc = pgmR3PhysRomReset(pVM);
2067	#endif
2068	if (RT_SUCCESS(rc))
2069	{
2070	/*
2071	* Switch mode back to real mode.
2072	*/
2073	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2074	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2075	}
2076	}
2077
2078	pgmUnlock(pVM);
2079	//return rc;
2080	AssertReleaseRC(rc);
2081	}
2082
2083
2084	#ifdef VBOX_STRICT
2085	/**
2086	* VM state change callback for clearing fNoMorePhysWrites after
2087	* a snapshot has been created.
2088	*/
2089	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2090	{
2091	if (enmState == VMSTATE_RUNNING)
2092	pVM->pgm.s.fNoMorePhysWrites = false;
2093	}
2094	#endif
2095
2096
2097	/**
2098	* Terminates the PGM.
2099	*
2100	* @returns VBox status code.
2101	* @param pVM Pointer to VM structure.
2102	*/
2103	VMMR3DECL(int) PGMR3Term(PVM pVM)
2104	{
2105	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2106	}
2107
2108
2109	/**
2110	* Execute state save operation.
2111	*
2112	* @returns VBox status code.
2113	* @param pVM VM Handle.
2114	* @param pSSM SSM operation handle.
2115	*/
2116	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2117	{
2118	PPGM pPGM = &pVM->pgm.s;
2119
2120	/* No more writes to physical memory after this point! */
2121	pVM->pgm.s.fNoMorePhysWrites = true;
2122
2123	/*
2124	* Save basic data (required / unaffected by relocation).
2125	*/
2126	#if 1
2127	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2128	#else
2129	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2130	#endif
2131	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2132	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2133	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2134	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2135	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2136	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2137	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2138	SSMR3PutU32(pSSM, ~0); /* Separator. */
2139
2140	/*
2141	* The guest mappings.
2142	*/
2143	uint32_t i = 0;
2144	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2145	{
2146	SSMR3PutU32(pSSM, i);
2147	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2148	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2149	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2150	/* flags are done by the mapping owners! */
2151	}
2152	SSMR3PutU32(pSSM, ~0); /* terminator. */
2153
2154	/*
2155	* Ram range flags and bits.
2156	*/
2157	i = 0;
2158	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2159	{
2160	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2161
2162	SSMR3PutU32(pSSM, i);
2163	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2164	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2165	SSMR3PutGCPhys(pSSM, pRam->cb);
2166	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2167
2168	/* Flags. */
2169	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2170	for (unsigned iPage = 0; iPage < cPages; iPage++)
2171	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2172
2173	/* any memory associated with the range. */
2174	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2175	{
2176	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2177	{
2178	if (pRam->paChunkR3Ptrs[iChunk])
2179	{
2180	SSMR3PutU8(pSSM, 1); /* chunk present */
2181	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2182	}
2183	else
2184	SSMR3PutU8(pSSM, 0); /* no chunk present */
2185	}
2186	}
2187	else if (pRam->pvR3)
2188	{
2189	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2190	if (VBOX_FAILURE(rc))
2191	{
2192	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2193	return rc;
2194	}
2195	}
2196	}
2197	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2198	}
2199
2200
2201	/**
2202	* Execute state load operation.
2203	*
2204	* @returns VBox status code.
2205	* @param pVM VM Handle.
2206	* @param pSSM SSM operation handle.
2207	* @param u32Version Data layout version.
2208	*/
2209	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2210	{
2211	/*
2212	* Validate version.
2213	*/
2214	if (u32Version != PGM_SAVED_STATE_VERSION)
2215	{
2216	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2217	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2218	}
2219
2220	/*
2221	* Call the reset function to make sure all the memory is cleared.
2222	*/
2223	PGMR3Reset(pVM);
2224
2225	/*
2226	* Load basic data (required / unaffected by relocation).
2227	*/
2228	PPGM pPGM = &pVM->pgm.s;
2229	#if 1
2230	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2231	#else
2232	uint32_t u;
2233	SSMR3GetU32(pSSM, &u);
2234	pPGM->fMappingsFixed = u;
2235	#endif
2236	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2237	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2238
2239	RTUINT cbRamSize;
2240	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2241	if (VBOX_FAILURE(rc))
2242	return rc;
2243	if (cbRamSize != pPGM->cbRamSize)
2244	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2245	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2246	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2247	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2248	RTUINT uGuestMode;
2249	SSMR3GetUInt(pSSM, &uGuestMode);
2250	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2251
2252	/* check separator. */
2253	uint32_t u32Sep;
2254	SSMR3GetU32(pSSM, &u32Sep);
2255	if (VBOX_FAILURE(rc))
2256	return rc;
2257	if (u32Sep != (uint32_t)~0)
2258	{
2259	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2260	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2261	}
2262
2263	/*
2264	* The guest mappings.
2265	*/
2266	uint32_t i = 0;
2267	for (;; i++)
2268	{
2269	/* Check the seqence number / separator. */
2270	rc = SSMR3GetU32(pSSM, &u32Sep);
2271	if (VBOX_FAILURE(rc))
2272	return rc;
2273	if (u32Sep == ~0U)
2274	break;
2275	if (u32Sep != i)
2276	{
2277	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2278	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2279	}
2280
2281	/* get the mapping details. */
2282	char szDesc[256];
2283	szDesc[0] = '\0';
2284	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2285	if (VBOX_FAILURE(rc))
2286	return rc;
2287	RTGCPTR GCPtr;
2288	SSMR3GetGCPtr(pSSM, &GCPtr);
2289	RTGCUINTPTR cPTs;
2290	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2291	if (VBOX_FAILURE(rc))
2292	return rc;
2293
2294	/* find matching range. */
2295	PPGMMAPPING pMapping;
2296	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2297	if ( pMapping->cPTs == cPTs
2298	&& !strcmp(pMapping->pszDesc, szDesc))
2299	break;
2300	if (!pMapping)
2301	{
2302	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
2303	cPTs, szDesc, GCPtr));
2304	AssertFailed();
2305	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2306	}
2307
2308	/* relocate it. */
2309	if (pMapping->GCPtr != GCPtr)
2310	{
2311	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
2312	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2313	}
2314	else
2315	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
2316	}
2317
2318	/*
2319	* Ram range flags and bits.
2320	*/
2321	i = 0;
2322	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2323	{
2324	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2325	/* Check the seqence number / separator. */
2326	rc = SSMR3GetU32(pSSM, &u32Sep);
2327	if (VBOX_FAILURE(rc))
2328	return rc;
2329	if (u32Sep == ~0U)
2330	break;
2331	if (u32Sep != i)
2332	{
2333	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2334	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2335	}
2336
2337	/* Get the range details. */
2338	RTGCPHYS GCPhys;
2339	SSMR3GetGCPhys(pSSM, &GCPhys);
2340	RTGCPHYS GCPhysLast;
2341	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2342	RTGCPHYS cb;
2343	SSMR3GetGCPhys(pSSM, &cb);
2344	uint8_t fHaveBits;
2345	rc = SSMR3GetU8(pSSM, &fHaveBits);
2346	if (VBOX_FAILURE(rc))
2347	return rc;
2348	if (fHaveBits & ~1)
2349	{
2350	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2351	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2352	}
2353
2354	/* Match it up with the current range. */
2355	if ( GCPhys != pRam->GCPhys
2356	\|\| GCPhysLast != pRam->GCPhysLast
2357	\|\| cb != pRam->cb
2358	\|\| fHaveBits != !!pRam->pvR3)
2359	{
2360	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2361	"State : %RGp-%RGp %RGp bytes %s\n",
2362	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2363	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2364	/*
2365	* If we're loading a state for debugging purpose, don't make a fuss if
2366	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2367	*/
2368	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2369	\|\| GCPhys < 8 * _1M)
2370	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2371
2372	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2373	while (cPages-- > 0)
2374	{
2375	uint16_t u16Ignore;
2376	SSMR3GetU16(pSSM, &u16Ignore);
2377	}
2378	continue;
2379	}
2380
2381	/* Flags. */
2382	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2383	for (unsigned iPage = 0; iPage < cPages; iPage++)
2384	{
2385	uint16_t u16 = 0;
2386	SSMR3GetU16(pSSM, &u16);
2387	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2388	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2389	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2390	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2391	}
2392
2393	/* any memory associated with the range. */
2394	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2395	{
2396	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2397	{
2398	uint8_t fValidChunk;
2399
2400	rc = SSMR3GetU8(pSSM, &fValidChunk);
2401	if (VBOX_FAILURE(rc))
2402	return rc;
2403	if (fValidChunk > 1)
2404	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2405
2406	if (fValidChunk)
2407	{
2408	if (!pRam->paChunkR3Ptrs[iChunk])
2409	{
2410	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2411	if (VBOX_FAILURE(rc))
2412	return rc;
2413	}
2414	Assert(pRam->paChunkR3Ptrs[iChunk]);
2415
2416	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2417	}
2418	/* else nothing to do */
2419	}
2420	}
2421	else if (pRam->pvR3)
2422	{
2423	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2424	if (VBOX_FAILURE(rc))
2425	{
2426	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2427	return rc;
2428	}
2429	}
2430	}
2431
2432	/*
2433	* We require a full resync now.
2434	*/
2435	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2436	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2437	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2438	pPGM->fPhysCacheFlushPending = true;
2439	pgmR3HandlerPhysicalUpdateAll(pVM);
2440
2441	/*
2442	* Change the paging mode.
2443	*/
2444	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2445
2446	/* Restore pVM->pgm.s.GCPhysCR3. */
2447	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2448	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2449	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2450	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2451	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2452	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2453	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2454	else
2455	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2456	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2457
2458	return rc;
2459	}
2460
2461
2462	/**
2463	* Show paging mode.
2464	*
2465	* @param pVM VM Handle.
2466	* @param pHlp The info helpers.
2467	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2468	*/
2469	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2470	{
2471	/* digest argument. */
2472	bool fGuest, fShadow, fHost;
2473	if (pszArgs)
2474	pszArgs = RTStrStripL(pszArgs);
2475	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2476	fShadow = fHost = fGuest = true;
2477	else
2478	{
2479	fShadow = fHost = fGuest = false;
2480	if (strstr(pszArgs, "guest"))
2481	fGuest = true;
2482	if (strstr(pszArgs, "shadow"))
2483	fShadow = true;
2484	if (strstr(pszArgs, "host"))
2485	fHost = true;
2486	}
2487
2488	/* print info. */
2489	if (fGuest)
2490	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2491	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2492	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2493	if (fShadow)
2494	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2495	if (fHost)
2496	{
2497	const char *psz;
2498	switch (pVM->pgm.s.enmHostMode)
2499	{
2500	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2501	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2502	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2503	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2504	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2505	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2506	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2507	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2508	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2509	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2510	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2511	default: psz = "unknown"; break;
2512	}
2513	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2514	}
2515	}
2516
2517
2518	/**
2519	* Dump registered MMIO ranges to the log.
2520	*
2521	* @param pVM VM Handle.
2522	* @param pHlp The info helpers.
2523	* @param pszArgs Arguments, ignored.
2524	*/
2525	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2526	{
2527	NOREF(pszArgs);
2528	pHlp->pfnPrintf(pHlp,
2529	"RAM ranges (pVM=%p)\n"
2530	"%.s %.s\n",
2531	pVM,
2532	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2533	sizeof(RTHCPTR) * 2, "pvHC ");
2534
2535	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2536	pHlp->pfnPrintf(pHlp,
2537	"%RGp-%RGp %RHv %s\n",
2538	pCur->GCPhys,
2539	pCur->GCPhysLast,
2540	pCur->pvR3,
2541	pCur->pszDesc);
2542	}
2543
2544	/**
2545	* Dump the page directory to the log.
2546	*
2547	* @param pVM VM Handle.
2548	* @param pHlp The info helpers.
2549	* @param pszArgs Arguments, ignored.
2550	*/
2551	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2552	{
2553	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2554	/* Big pages supported? */
2555	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2556
2557	/* Global pages supported? */
2558	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2559
2560	NOREF(pszArgs);
2561
2562	/*
2563	* Get page directory addresses.
2564	*/
2565	PX86PD pPDSrc = pVM->pgm.s.pGuestPDHC;
2566	Assert(pPDSrc);
2567	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2568
2569	/*
2570	* Iterate the page directory.
2571	*/
2572	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2573	{
2574	X86PDE PdeSrc = pPDSrc->a[iPD];
2575	if (PdeSrc.n.u1Present)
2576	{
2577	if (PdeSrc.b.u1Size && fPSE)
2578	pHlp->pfnPrintf(pHlp,
2579	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2580	iPD,
2581	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2582	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2583	else
2584	pHlp->pfnPrintf(pHlp,
2585	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2586	iPD,
2587	PdeSrc.u & X86_PDE_PG_MASK,
2588	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2589	}
2590	}
2591	}
2592
2593
2594	/**
2595	* Serivce a VMMCALLHOST_PGM_LOCK call.
2596	*
2597	* @returns VBox status code.
2598	* @param pVM The VM handle.
2599	*/
2600	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2601	{
2602	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2603	AssertRC(rc);
2604	return rc;
2605	}
2606
2607
2608	/**
2609	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2610	*
2611	* @returns PGM_TYPE_*.
2612	* @param pgmMode The mode value to convert.
2613	*/
2614	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2615	{
2616	switch (pgmMode)
2617	{
2618	case PGMMODE_REAL: return PGM_TYPE_REAL;
2619	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2620	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2621	case PGMMODE_PAE:
2622	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2623	case PGMMODE_AMD64:
2624	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2625	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2626	case PGMMODE_EPT: return PGM_TYPE_EPT;
2627	default:
2628	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2629	}
2630	}
2631
2632
2633	/**
2634	* Gets the index into the paging mode data array of a SHW+GST mode.
2635	*
2636	* @returns PGM::paPagingData index.
2637	* @param uShwType The shadow paging mode type.
2638	* @param uGstType The guest paging mode type.
2639	*/
2640	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2641	{
2642	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2643	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2644	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2645	+ (uGstType - PGM_TYPE_REAL);
2646	}
2647
2648
2649	/**
2650	* Gets the index into the paging mode data array of a SHW+GST mode.
2651	*
2652	* @returns PGM::paPagingData index.
2653	* @param enmShw The shadow paging mode.
2654	* @param enmGst The guest paging mode.
2655	*/
2656	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2657	{
2658	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2659	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2660	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2661	}
2662
2663
2664	/**
2665	* Calculates the max data index.
2666	* @returns The number of entries in the paging data array.
2667	*/
2668	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2669	{
2670	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2671	}
2672
2673
2674	/**
2675	* Initializes the paging mode data kept in PGM::paModeData.
2676	*
2677	* @param pVM The VM handle.
2678	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2679	* This is used early in the init process to avoid trouble with PDM
2680	* not being initialized yet.
2681	*/
2682	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2683	{
2684	PPGMMODEDATA pModeData;
2685	int rc;
2686
2687	/*
2688	* Allocate the array on the first call.
2689	*/
2690	if (!pVM->pgm.s.paModeData)
2691	{
2692	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2693	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2694	}
2695
2696	/*
2697	* Initialize the array entries.
2698	*/
2699	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2700	pModeData->uShwType = PGM_TYPE_32BIT;
2701	pModeData->uGstType = PGM_TYPE_REAL;
2702	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2703	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2704	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2705
2706	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2707	pModeData->uShwType = PGM_TYPE_32BIT;
2708	pModeData->uGstType = PGM_TYPE_PROT;
2709	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2710	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2711	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2712
2713	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2714	pModeData->uShwType = PGM_TYPE_32BIT;
2715	pModeData->uGstType = PGM_TYPE_32BIT;
2716	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2717	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2718	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2719
2720	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2721	pModeData->uShwType = PGM_TYPE_PAE;
2722	pModeData->uGstType = PGM_TYPE_REAL;
2723	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2724	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2725	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2726
2727	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2728	pModeData->uShwType = PGM_TYPE_PAE;
2729	pModeData->uGstType = PGM_TYPE_PROT;
2730	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2731	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2732	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2733
2734	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2735	pModeData->uShwType = PGM_TYPE_PAE;
2736	pModeData->uGstType = PGM_TYPE_32BIT;
2737	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2738	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2739	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2740
2741	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2742	pModeData->uShwType = PGM_TYPE_PAE;
2743	pModeData->uGstType = PGM_TYPE_PAE;
2744	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2745	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2746	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2747
2748	#ifdef VBOX_WITH_64_BITS_GUESTS
2749	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2750	pModeData->uShwType = PGM_TYPE_AMD64;
2751	pModeData->uGstType = PGM_TYPE_AMD64;
2752	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2753	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2754	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2755	#endif
2756
2757	/* The nested paging mode. */
2758	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2759	pModeData->uShwType = PGM_TYPE_NESTED;
2760	pModeData->uGstType = PGM_TYPE_REAL;
2761	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2762	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2763
2764	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2765	pModeData->uShwType = PGM_TYPE_NESTED;
2766	pModeData->uGstType = PGM_TYPE_PROT;
2767	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2768	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2769
2770	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2771	pModeData->uShwType = PGM_TYPE_NESTED;
2772	pModeData->uGstType = PGM_TYPE_32BIT;
2773	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2774	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2775
2776	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2777	pModeData->uShwType = PGM_TYPE_NESTED;
2778	pModeData->uGstType = PGM_TYPE_PAE;
2779	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2780	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2781
2782	#ifdef VBOX_WITH_64_BITS_GUESTS
2783	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2784	pModeData->uShwType = PGM_TYPE_NESTED;
2785	pModeData->uGstType = PGM_TYPE_AMD64;
2786	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2787	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2788	#endif
2789
2790	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2791	switch(pVM->pgm.s.enmHostMode)
2792	{
2793	case SUPPAGINGMODE_32_BIT:
2794	case SUPPAGINGMODE_32_BIT_GLOBAL:
2795	#ifdef VBOX_WITH_64_BITS_GUESTS
2796	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2797	#else
2798	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2799	#endif
2800	{
2801	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2802	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2803	}
2804	break;
2805
2806	case SUPPAGINGMODE_PAE:
2807	case SUPPAGINGMODE_PAE_NX:
2808	case SUPPAGINGMODE_PAE_GLOBAL:
2809	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2810	#ifdef VBOX_WITH_64_BITS_GUESTS
2811	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2812	#else
2813	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2814	#endif
2815	{
2816	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2817	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2818	}
2819	break;
2820
2821	case SUPPAGINGMODE_AMD64:
2822	case SUPPAGINGMODE_AMD64_GLOBAL:
2823	case SUPPAGINGMODE_AMD64_NX:
2824	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2825	#ifdef VBOX_WITH_64_BITS_GUESTS
2826	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2827	#else
2828	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2829	#endif
2830	{
2831	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2832	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2833	}
2834	break;
2835	default:
2836	AssertFailed();
2837	break;
2838	}
2839
2840	/* Extended paging (EPT) / Intel VT-x */
2841	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2842	pModeData->uShwType = PGM_TYPE_EPT;
2843	pModeData->uGstType = PGM_TYPE_REAL;
2844	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2845	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2846	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2847
2848	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2849	pModeData->uShwType = PGM_TYPE_EPT;
2850	pModeData->uGstType = PGM_TYPE_PROT;
2851	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2852	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2853	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2854
2855	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2856	pModeData->uShwType = PGM_TYPE_EPT;
2857	pModeData->uGstType = PGM_TYPE_32BIT;
2858	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2859	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2860	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2861
2862	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2863	pModeData->uShwType = PGM_TYPE_EPT;
2864	pModeData->uGstType = PGM_TYPE_PAE;
2865	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2866	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2867	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2868
2869	#ifdef VBOX_WITH_64_BITS_GUESTS
2870	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2871	pModeData->uShwType = PGM_TYPE_EPT;
2872	pModeData->uGstType = PGM_TYPE_AMD64;
2873	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2874	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2875	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2876	#endif
2877	return VINF_SUCCESS;
2878	}
2879
2880
2881	/**
2882	* Switch to different (or relocated in the relocate case) mode data.
2883	*
2884	* @param pVM The VM handle.
2885	* @param enmShw The the shadow paging mode.
2886	* @param enmGst The the guest paging mode.
2887	*/
2888	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2889	{
2890	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2891
2892	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2893	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2894
2895	/* shadow */
2896	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2897	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2898	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2899	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2900	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2901
2902	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2903	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2904
2905	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2906	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2907
2908
2909	/* guest */
2910	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2911	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2912	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2913	Assert(pVM->pgm.s.pfnR3GstGetPage);
2914	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2915	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2916	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2917	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2918	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2919	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2920	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2921	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2922	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2923	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2924
2925	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2926	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2927	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2928	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
2929	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
2930	pVM->pgm.s.pfnRCGstMapCR3 = pModeData->pfnRCGstMapCR3;
2931	pVM->pgm.s.pfnRCGstUnmapCR3 = pModeData->pfnRCGstUnmapCR3;
2932	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
2933	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
2934
2935	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2936	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2937	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2938	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2939	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2940	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2941	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2942	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2943	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2944
2945
2946	/* both */
2947	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2948	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2949	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2950	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2951	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2952	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2953	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2954	#ifdef VBOX_STRICT
2955	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2956	#endif
2957
2958	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2959	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2960	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2961	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2962	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2963	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2964	#ifdef VBOX_STRICT
2965	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2966	#endif
2967
2968	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2969	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2970	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2971	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2972	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2973	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2974	#ifdef VBOX_STRICT
2975	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2976	#endif
2977	}
2978
2979
2980	/**
2981	* Calculates the shadow paging mode.
2982	*
2983	* @returns The shadow paging mode.
2984	* @param pVM VM handle.
2985	* @param enmGuestMode The guest mode.
2986	* @param enmHostMode The host mode.
2987	* @param enmShadowMode The current shadow mode.
2988	* @param penmSwitcher Where to store the switcher to use.
2989	* VMMSWITCHER_INVALID means no change.
2990	*/
2991	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2992	{
2993	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2994	switch (enmGuestMode)
2995	{
2996	/*
2997	* When switching to real or protected mode we don't change
2998	* anything since it's likely that we'll switch back pretty soon.
2999	*
3000	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3001	* and is supposed to determine which shadow paging and switcher to
3002	* use during init.
3003	*/
3004	case PGMMODE_REAL:
3005	case PGMMODE_PROTECTED:
3006	if ( enmShadowMode != PGMMODE_INVALID
3007	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3008	break; /* (no change) */
3009
3010	switch (enmHostMode)
3011	{
3012	case SUPPAGINGMODE_32_BIT:
3013	case SUPPAGINGMODE_32_BIT_GLOBAL:
3014	enmShadowMode = PGMMODE_32_BIT;
3015	enmSwitcher = VMMSWITCHER_32_TO_32;
3016	break;
3017
3018	case SUPPAGINGMODE_PAE:
3019	case SUPPAGINGMODE_PAE_NX:
3020	case SUPPAGINGMODE_PAE_GLOBAL:
3021	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3022	enmShadowMode = PGMMODE_PAE;
3023	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3024	#ifdef DEBUG_bird
3025	if (RTEnvExist("VBOX_32BIT"))
3026	{
3027	enmShadowMode = PGMMODE_32_BIT;
3028	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3029	}
3030	#endif
3031	break;
3032
3033	case SUPPAGINGMODE_AMD64:
3034	case SUPPAGINGMODE_AMD64_GLOBAL:
3035	case SUPPAGINGMODE_AMD64_NX:
3036	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3037	enmShadowMode = PGMMODE_PAE;
3038	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3039	break;
3040
3041	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3042	}
3043	break;
3044
3045	case PGMMODE_32_BIT:
3046	switch (enmHostMode)
3047	{
3048	case SUPPAGINGMODE_32_BIT:
3049	case SUPPAGINGMODE_32_BIT_GLOBAL:
3050	enmShadowMode = PGMMODE_32_BIT;
3051	enmSwitcher = VMMSWITCHER_32_TO_32;
3052	break;
3053
3054	case SUPPAGINGMODE_PAE:
3055	case SUPPAGINGMODE_PAE_NX:
3056	case SUPPAGINGMODE_PAE_GLOBAL:
3057	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3058	enmShadowMode = PGMMODE_PAE;
3059	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3060	#ifdef DEBUG_bird
3061	if (RTEnvExist("VBOX_32BIT"))
3062	{
3063	enmShadowMode = PGMMODE_32_BIT;
3064	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3065	}
3066	#endif
3067	break;
3068
3069	case SUPPAGINGMODE_AMD64:
3070	case SUPPAGINGMODE_AMD64_GLOBAL:
3071	case SUPPAGINGMODE_AMD64_NX:
3072	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3073	enmShadowMode = PGMMODE_PAE;
3074	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3075	break;
3076
3077	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3078	}
3079	break;
3080
3081	case PGMMODE_PAE:
3082	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3083	switch (enmHostMode)
3084	{
3085	case SUPPAGINGMODE_32_BIT:
3086	case SUPPAGINGMODE_32_BIT_GLOBAL:
3087	enmShadowMode = PGMMODE_PAE;
3088	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3089	break;
3090
3091	case SUPPAGINGMODE_PAE:
3092	case SUPPAGINGMODE_PAE_NX:
3093	case SUPPAGINGMODE_PAE_GLOBAL:
3094	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3095	enmShadowMode = PGMMODE_PAE;
3096	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3097	break;
3098
3099	case SUPPAGINGMODE_AMD64:
3100	case SUPPAGINGMODE_AMD64_GLOBAL:
3101	case SUPPAGINGMODE_AMD64_NX:
3102	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3103	enmShadowMode = PGMMODE_PAE;
3104	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3105	break;
3106
3107	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3108	}
3109	break;
3110
3111	case PGMMODE_AMD64:
3112	case PGMMODE_AMD64_NX:
3113	switch (enmHostMode)
3114	{
3115	case SUPPAGINGMODE_32_BIT:
3116	case SUPPAGINGMODE_32_BIT_GLOBAL:
3117	enmShadowMode = PGMMODE_PAE;
3118	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3119	break;
3120
3121	case SUPPAGINGMODE_PAE:
3122	case SUPPAGINGMODE_PAE_NX:
3123	case SUPPAGINGMODE_PAE_GLOBAL:
3124	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3125	enmShadowMode = PGMMODE_PAE;
3126	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3127	break;
3128
3129	case SUPPAGINGMODE_AMD64:
3130	case SUPPAGINGMODE_AMD64_GLOBAL:
3131	case SUPPAGINGMODE_AMD64_NX:
3132	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3133	enmShadowMode = PGMMODE_AMD64;
3134	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3135	break;
3136
3137	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3138	}
3139	break;
3140
3141
3142	default:
3143	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3144	return PGMMODE_INVALID;
3145	}
3146	/* Override the shadow mode is nested paging is active. */
3147	if (HWACCMIsNestedPagingActive(pVM))
3148	enmShadowMode = HWACCMGetPagingMode(pVM);
3149
3150	*penmSwitcher = enmSwitcher;
3151	return enmShadowMode;
3152	}
3153
3154
3155	/**
3156	* Performs the actual mode change.
3157	* This is called by PGMChangeMode and pgmR3InitPaging().
3158	*
3159	* @returns VBox status code.
3160	* @param pVM VM handle.
3161	* @param enmGuestMode The new guest mode. This is assumed to be different from
3162	* the current mode.
3163	*/
3164	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3165	{
3166	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3167	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3168
3169	/*
3170	* Calc the shadow mode and switcher.
3171	*/
3172	VMMSWITCHER enmSwitcher;
3173	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3174	if (enmSwitcher != VMMSWITCHER_INVALID)
3175	{
3176	/*
3177	* Select new switcher.
3178	*/
3179	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3180	if (VBOX_FAILURE(rc))
3181	{
3182	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
3183	return rc;
3184	}
3185	}
3186
3187	/*
3188	* Exit old mode(s).
3189	*/
3190	/* shadow */
3191	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3192	{
3193	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3194	if (PGM_SHW_PFN(Exit, pVM))
3195	{
3196	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3197	if (VBOX_FAILURE(rc))
3198	{
3199	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
3200	return rc;
3201	}
3202	}
3203
3204	}
3205	else
3206	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3207
3208	/* guest */
3209	if (PGM_GST_PFN(Exit, pVM))
3210	{
3211	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3212	if (VBOX_FAILURE(rc))
3213	{
3214	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
3215	return rc;
3216	}
3217	}
3218
3219	/*
3220	* Load new paging mode data.
3221	*/
3222	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3223
3224	/*
3225	* Enter new shadow mode (if changed).
3226	*/
3227	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3228	{
3229	int rc;
3230	pVM->pgm.s.enmShadowMode = enmShadowMode;
3231	switch (enmShadowMode)
3232	{
3233	case PGMMODE_32_BIT:
3234	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3235	break;
3236	case PGMMODE_PAE:
3237	case PGMMODE_PAE_NX:
3238	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3239	break;
3240	case PGMMODE_AMD64:
3241	case PGMMODE_AMD64_NX:
3242	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3243	break;
3244	case PGMMODE_NESTED:
3245	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3246	break;
3247	case PGMMODE_EPT:
3248	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3249	break;
3250	case PGMMODE_REAL:
3251	case PGMMODE_PROTECTED:
3252	default:
3253	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3254	return VERR_INTERNAL_ERROR;
3255	}
3256	if (VBOX_FAILURE(rc))
3257	{
3258	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
3259	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3260	return rc;
3261	}
3262	}
3263
3264	/** @todo This is a bug!
3265	*
3266	* We must flush the PGM pool cache if the guest mode changes; we don't always
3267	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3268	* the shadow page tables.
3269	*
3270	* That only applies when switching between paging and non-paging modes.
3271	*/
3272	/** @todo A20 setting */
3273	if ( pVM->pgm.s.CTX_SUFF(pPool)
3274	&& !HWACCMIsNestedPagingActive(pVM)
3275	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3276	{
3277	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3278	pgmPoolFlushAll(pVM);
3279	}
3280
3281	/*
3282	* Enter the new guest and shadow+guest modes.
3283	*/
3284	int rc = -1;
3285	int rc2 = -1;
3286	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3287	pVM->pgm.s.enmGuestMode = enmGuestMode;
3288	switch (enmGuestMode)
3289	{
3290	case PGMMODE_REAL:
3291	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3292	switch (pVM->pgm.s.enmShadowMode)
3293	{
3294	case PGMMODE_32_BIT:
3295	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3296	break;
3297	case PGMMODE_PAE:
3298	case PGMMODE_PAE_NX:
3299	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3300	break;
3301	case PGMMODE_NESTED:
3302	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3303	break;
3304	case PGMMODE_EPT:
3305	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3306	break;
3307	case PGMMODE_AMD64:
3308	case PGMMODE_AMD64_NX:
3309	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3310	default: AssertFailed(); break;
3311	}
3312	break;
3313
3314	case PGMMODE_PROTECTED:
3315	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3316	switch (pVM->pgm.s.enmShadowMode)
3317	{
3318	case PGMMODE_32_BIT:
3319	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3320	break;
3321	case PGMMODE_PAE:
3322	case PGMMODE_PAE_NX:
3323	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3324	break;
3325	case PGMMODE_NESTED:
3326	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3327	break;
3328	case PGMMODE_EPT:
3329	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3330	break;
3331	case PGMMODE_AMD64:
3332	case PGMMODE_AMD64_NX:
3333	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3334	default: AssertFailed(); break;
3335	}
3336	break;
3337
3338	case PGMMODE_32_BIT:
3339	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3340	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3341	switch (pVM->pgm.s.enmShadowMode)
3342	{
3343	case PGMMODE_32_BIT:
3344	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3345	break;
3346	case PGMMODE_PAE:
3347	case PGMMODE_PAE_NX:
3348	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3349	break;
3350	case PGMMODE_NESTED:
3351	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3352	break;
3353	case PGMMODE_EPT:
3354	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3355	break;
3356	case PGMMODE_AMD64:
3357	case PGMMODE_AMD64_NX:
3358	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3359	default: AssertFailed(); break;
3360	}
3361	break;
3362
3363	case PGMMODE_PAE_NX:
3364	case PGMMODE_PAE:
3365	{
3366	uint32_t u32Dummy, u32Features;
3367
3368	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3369	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3370	{
3371	/* Pause first, then inform Main. */
3372	rc = VMR3SuspendNoSave(pVM);
3373	AssertRC(rc);
3374
3375	VMSetRuntimeError(pVM, true, "PAEmode",
3376	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage"));
3377	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3378	return VINF_SUCCESS;
3379	}
3380	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3381	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3382	switch (pVM->pgm.s.enmShadowMode)
3383	{
3384	case PGMMODE_PAE:
3385	case PGMMODE_PAE_NX:
3386	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3387	break;
3388	case PGMMODE_NESTED:
3389	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3390	break;
3391	case PGMMODE_EPT:
3392	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3393	break;
3394	case PGMMODE_32_BIT:
3395	case PGMMODE_AMD64:
3396	case PGMMODE_AMD64_NX:
3397	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3398	default: AssertFailed(); break;
3399	}
3400	break;
3401	}
3402
3403	#ifdef VBOX_WITH_64_BITS_GUESTS
3404	case PGMMODE_AMD64_NX:
3405	case PGMMODE_AMD64:
3406	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3407	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3408	switch (pVM->pgm.s.enmShadowMode)
3409	{
3410	case PGMMODE_AMD64:
3411	case PGMMODE_AMD64_NX:
3412	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3413	break;
3414	case PGMMODE_NESTED:
3415	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3416	break;
3417	case PGMMODE_EPT:
3418	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3419	break;
3420	case PGMMODE_32_BIT:
3421	case PGMMODE_PAE:
3422	case PGMMODE_PAE_NX:
3423	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3424	default: AssertFailed(); break;
3425	}
3426	break;
3427	#endif
3428
3429	default:
3430	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3431	rc = VERR_NOT_IMPLEMENTED;
3432	break;
3433	}
3434
3435	/* status codes. */
3436	AssertRC(rc);
3437	AssertRC(rc2);
3438	if (VBOX_SUCCESS(rc))
3439	{
3440	rc = rc2;
3441	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
3442	rc = VINF_SUCCESS;
3443	}
3444
3445	/*
3446	* Notify SELM so it can update the TSSes with correct CR3s.
3447	*/
3448	SELMR3PagingModeChanged(pVM);
3449
3450	/* Notify HWACCM as well. */
3451	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
3452	return rc;
3453	}
3454
3455
3456	/**
3457	* Dumps a PAE shadow page table.
3458	*
3459	* @returns VBox status code (VINF_SUCCESS).
3460	* @param pVM The VM handle.
3461	* @param pPT Pointer to the page table.
3462	* @param u64Address The virtual address of the page table starts.
3463	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3464	* @param cMaxDepth The maxium depth.
3465	* @param pHlp Pointer to the output functions.
3466	*/
3467	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3468	{
3469	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3470	{
3471	X86PTEPAE Pte = pPT->a[i];
3472	if (Pte.n.u1Present)
3473	{
3474	pHlp->pfnPrintf(pHlp,
3475	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3476	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3477	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3478	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3479	Pte.n.u1Write ? 'W' : 'R',
3480	Pte.n.u1User ? 'U' : 'S',
3481	Pte.n.u1Accessed ? 'A' : '-',
3482	Pte.n.u1Dirty ? 'D' : '-',
3483	Pte.n.u1Global ? 'G' : '-',
3484	Pte.n.u1WriteThru ? "WT" : "--",
3485	Pte.n.u1CacheDisable? "CD" : "--",
3486	Pte.n.u1PAT ? "AT" : "--",
3487	Pte.n.u1NoExecute ? "NX" : "--",
3488	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3489	Pte.u & RT_BIT(10) ? '1' : '0',
3490	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3491	Pte.u & X86_PTE_PAE_PG_MASK);
3492	}
3493	}
3494	return VINF_SUCCESS;
3495	}
3496
3497
3498	/**
3499	* Dumps a PAE shadow page directory table.
3500	*
3501	* @returns VBox status code (VINF_SUCCESS).
3502	* @param pVM The VM handle.
3503	* @param HCPhys The physical address of the page directory table.
3504	* @param u64Address The virtual address of the page table starts.
3505	* @param cr4 The CR4, PSE is currently used.
3506	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3507	* @param cMaxDepth The maxium depth.
3508	* @param pHlp Pointer to the output functions.
3509	*/
3510	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3511	{
3512	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3513	if (!pPD)
3514	{
3515	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3516	fLongMode ? 16 : 8, u64Address, HCPhys);
3517	return VERR_INVALID_PARAMETER;
3518	}
3519	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3520
3521	int rc = VINF_SUCCESS;
3522	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3523	{
3524	X86PDEPAE Pde = pPD->a[i];
3525	if (Pde.n.u1Present)
3526	{
3527	if (fBigPagesSupported && Pde.b.u1Size)
3528	pHlp->pfnPrintf(pHlp,
3529	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3530	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3531	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3532	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3533	Pde.b.u1Write ? 'W' : 'R',
3534	Pde.b.u1User ? 'U' : 'S',
3535	Pde.b.u1Accessed ? 'A' : '-',
3536	Pde.b.u1Dirty ? 'D' : '-',
3537	Pde.b.u1Global ? 'G' : '-',
3538	Pde.b.u1WriteThru ? "WT" : "--",
3539	Pde.b.u1CacheDisable? "CD" : "--",
3540	Pde.b.u1PAT ? "AT" : "--",
3541	Pde.b.u1NoExecute ? "NX" : "--",
3542	Pde.u & RT_BIT_64(9) ? '1' : '0',
3543	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3544	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3545	Pde.u & X86_PDE_PAE_PG_MASK);
3546	else
3547	{
3548	pHlp->pfnPrintf(pHlp,
3549	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3550	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3551	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3552	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3553	Pde.n.u1Write ? 'W' : 'R',
3554	Pde.n.u1User ? 'U' : 'S',
3555	Pde.n.u1Accessed ? 'A' : '-',
3556	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3557	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3558	Pde.n.u1WriteThru ? "WT" : "--",
3559	Pde.n.u1CacheDisable? "CD" : "--",
3560	Pde.n.u1NoExecute ? "NX" : "--",
3561	Pde.u & RT_BIT_64(9) ? '1' : '0',
3562	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3563	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3564	Pde.u & X86_PDE_PAE_PG_MASK);
3565	if (cMaxDepth >= 1)
3566	{
3567	/** @todo what about using the page pool for mapping PTs? */
3568	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3569	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3570	PX86PTPAE pPT = NULL;
3571	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3572	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3573	else
3574	{
3575	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3576	{
3577	uint64_t off = u64AddressPT - pMap->GCPtr;
3578	if (off < pMap->cb)
3579	{
3580	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3581	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3582	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3583	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3584	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3585	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3586	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3587	}
3588	}
3589	}
3590	int rc2 = VERR_INVALID_PARAMETER;
3591	if (pPT)
3592	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3593	else
3594	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3595	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3596	if (rc2 < rc && VBOX_SUCCESS(rc))
3597	rc = rc2;
3598	}
3599	}
3600	}
3601	}
3602	return rc;
3603	}
3604
3605
3606	/**
3607	* Dumps a PAE shadow page directory pointer table.
3608	*
3609	* @returns VBox status code (VINF_SUCCESS).
3610	* @param pVM The VM handle.
3611	* @param HCPhys The physical address of the page directory pointer table.
3612	* @param u64Address The virtual address of the page table starts.
3613	* @param cr4 The CR4, PSE is currently used.
3614	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3615	* @param cMaxDepth The maxium depth.
3616	* @param pHlp Pointer to the output functions.
3617	*/
3618	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3619	{
3620	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3621	if (!pPDPT)
3622	{
3623	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3624	fLongMode ? 16 : 8, u64Address, HCPhys);
3625	return VERR_INVALID_PARAMETER;
3626	}
3627
3628	int rc = VINF_SUCCESS;
3629	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3630	for (unsigned i = 0; i < c; i++)
3631	{
3632	X86PDPE Pdpe = pPDPT->a[i];
3633	if (Pdpe.n.u1Present)
3634	{
3635	if (fLongMode)
3636	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3637	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3638	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3639	Pdpe.lm.u1Write ? 'W' : 'R',
3640	Pdpe.lm.u1User ? 'U' : 'S',
3641	Pdpe.lm.u1Accessed ? 'A' : '-',
3642	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3643	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3644	Pdpe.lm.u1WriteThru ? "WT" : "--",
3645	Pdpe.lm.u1CacheDisable? "CD" : "--",
3646	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3647	Pdpe.lm.u1NoExecute ? "NX" : "--",
3648	Pdpe.u & RT_BIT(9) ? '1' : '0',
3649	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3650	Pdpe.u & RT_BIT(11) ? '1' : '0',
3651	Pdpe.u & X86_PDPE_PG_MASK);
3652	else
3653	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3654	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3655	i << X86_PDPT_SHIFT,
3656	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3657	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3658	Pdpe.n.u1WriteThru ? "WT" : "--",
3659	Pdpe.n.u1CacheDisable? "CD" : "--",
3660	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3661	Pdpe.u & RT_BIT(9) ? '1' : '0',
3662	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3663	Pdpe.u & RT_BIT(11) ? '1' : '0',
3664	Pdpe.u & X86_PDPE_PG_MASK);
3665	if (cMaxDepth >= 1)
3666	{
3667	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3668	cr4, fLongMode, cMaxDepth - 1, pHlp);
3669	if (rc2 < rc && VBOX_SUCCESS(rc))
3670	rc = rc2;
3671	}
3672	}
3673	}
3674	return rc;
3675	}
3676
3677
3678	/**
3679	* Dumps a 32-bit shadow page table.
3680	*
3681	* @returns VBox status code (VINF_SUCCESS).
3682	* @param pVM The VM handle.
3683	* @param HCPhys The physical address of the table.
3684	* @param cr4 The CR4, PSE is currently used.
3685	* @param cMaxDepth The maxium depth.
3686	* @param pHlp Pointer to the output functions.
3687	*/
3688	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3689	{
3690	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3691	if (!pPML4)
3692	{
3693	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3694	return VERR_INVALID_PARAMETER;
3695	}
3696
3697	int rc = VINF_SUCCESS;
3698	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3699	{
3700	X86PML4E Pml4e = pPML4->a[i];
3701	if (Pml4e.n.u1Present)
3702	{
3703	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3704	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3705	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3706	u64Address,
3707	Pml4e.n.u1Write ? 'W' : 'R',
3708	Pml4e.n.u1User ? 'U' : 'S',
3709	Pml4e.n.u1Accessed ? 'A' : '-',
3710	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3711	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3712	Pml4e.n.u1WriteThru ? "WT" : "--",
3713	Pml4e.n.u1CacheDisable? "CD" : "--",
3714	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3715	Pml4e.n.u1NoExecute ? "NX" : "--",
3716	Pml4e.u & RT_BIT(9) ? '1' : '0',
3717	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3718	Pml4e.u & RT_BIT(11) ? '1' : '0',
3719	Pml4e.u & X86_PML4E_PG_MASK);
3720
3721	if (cMaxDepth >= 1)
3722	{
3723	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3724	if (rc2 < rc && VBOX_SUCCESS(rc))
3725	rc = rc2;
3726	}
3727	}
3728	}
3729	return rc;
3730	}
3731
3732
3733	/**
3734	* Dumps a 32-bit shadow page table.
3735	*
3736	* @returns VBox status code (VINF_SUCCESS).
3737	* @param pVM The VM handle.
3738	* @param pPT Pointer to the page table.
3739	* @param u32Address The virtual address this table starts at.
3740	* @param pHlp Pointer to the output functions.
3741	*/
3742	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3743	{
3744	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3745	{
3746	X86PTE Pte = pPT->a[i];
3747	if (Pte.n.u1Present)
3748	{
3749	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3750	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3751	u32Address + (i << X86_PT_SHIFT),
3752	Pte.n.u1Write ? 'W' : 'R',
3753	Pte.n.u1User ? 'U' : 'S',
3754	Pte.n.u1Accessed ? 'A' : '-',
3755	Pte.n.u1Dirty ? 'D' : '-',
3756	Pte.n.u1Global ? 'G' : '-',
3757	Pte.n.u1WriteThru ? "WT" : "--",
3758	Pte.n.u1CacheDisable? "CD" : "--",
3759	Pte.n.u1PAT ? "AT" : "--",
3760	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3761	Pte.u & RT_BIT(10) ? '1' : '0',
3762	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3763	Pte.u & X86_PDE_PG_MASK);
3764	}
3765	}
3766	return VINF_SUCCESS;
3767	}
3768
3769
3770	/**
3771	* Dumps a 32-bit shadow page directory and page tables.
3772	*
3773	* @returns VBox status code (VINF_SUCCESS).
3774	* @param pVM The VM handle.
3775	* @param cr3 The root of the hierarchy.
3776	* @param cr4 The CR4, PSE is currently used.
3777	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3778	* @param pHlp Pointer to the output functions.
3779	*/
3780	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3781	{
3782	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3783	if (!pPD)
3784	{
3785	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3786	return VERR_INVALID_PARAMETER;
3787	}
3788
3789	int rc = VINF_SUCCESS;
3790	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3791	{
3792	X86PDE Pde = pPD->a[i];
3793	if (Pde.n.u1Present)
3794	{
3795	const uint32_t u32Address = i << X86_PD_SHIFT;
3796	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3797	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3798	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3799	u32Address,
3800	Pde.b.u1Write ? 'W' : 'R',
3801	Pde.b.u1User ? 'U' : 'S',
3802	Pde.b.u1Accessed ? 'A' : '-',
3803	Pde.b.u1Dirty ? 'D' : '-',
3804	Pde.b.u1Global ? 'G' : '-',
3805	Pde.b.u1WriteThru ? "WT" : "--",
3806	Pde.b.u1CacheDisable? "CD" : "--",
3807	Pde.b.u1PAT ? "AT" : "--",
3808	Pde.u & RT_BIT_64(9) ? '1' : '0',
3809	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3810	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3811	Pde.u & X86_PDE4M_PG_MASK);
3812	else
3813	{
3814	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3815	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3816	u32Address,
3817	Pde.n.u1Write ? 'W' : 'R',
3818	Pde.n.u1User ? 'U' : 'S',
3819	Pde.n.u1Accessed ? 'A' : '-',
3820	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3821	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3822	Pde.n.u1WriteThru ? "WT" : "--",
3823	Pde.n.u1CacheDisable? "CD" : "--",
3824	Pde.u & RT_BIT_64(9) ? '1' : '0',
3825	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3826	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3827	Pde.u & X86_PDE_PG_MASK);
3828	if (cMaxDepth >= 1)
3829	{
3830	/** @todo what about using the page pool for mapping PTs? */
3831	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3832	PX86PT pPT = NULL;
3833	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3834	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3835	else
3836	{
3837	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3838	if (u32Address - pMap->GCPtr < pMap->cb)
3839	{
3840	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3841	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3842	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3843	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3844	pPT = pMap->aPTs[iPDE].pPTR3;
3845	}
3846	}
3847	int rc2 = VERR_INVALID_PARAMETER;
3848	if (pPT)
3849	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3850	else
3851	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3852	if (rc2 < rc && VBOX_SUCCESS(rc))
3853	rc = rc2;
3854	}
3855	}
3856	}
3857	}
3858
3859	return rc;
3860	}
3861
3862
3863	/**
3864	* Dumps a 32-bit shadow page table.
3865	*
3866	* @returns VBox status code (VINF_SUCCESS).
3867	* @param pVM The VM handle.
3868	* @param pPT Pointer to the page table.
3869	* @param u32Address The virtual address this table starts at.
3870	* @param PhysSearch Address to search for.
3871	*/
3872	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3873	{
3874	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3875	{
3876	X86PTE Pte = pPT->a[i];
3877	if (Pte.n.u1Present)
3878	{
3879	Log(( /P R S A D G WT CD AT NX 4M a m d /
3880	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3881	u32Address + (i << X86_PT_SHIFT),
3882	Pte.n.u1Write ? 'W' : 'R',
3883	Pte.n.u1User ? 'U' : 'S',
3884	Pte.n.u1Accessed ? 'A' : '-',
3885	Pte.n.u1Dirty ? 'D' : '-',
3886	Pte.n.u1Global ? 'G' : '-',
3887	Pte.n.u1WriteThru ? "WT" : "--",
3888	Pte.n.u1CacheDisable? "CD" : "--",
3889	Pte.n.u1PAT ? "AT" : "--",
3890	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3891	Pte.u & RT_BIT(10) ? '1' : '0',
3892	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3893	Pte.u & X86_PDE_PG_MASK));
3894
3895	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3896	{
3897	uint64_t fPageShw = 0;
3898	RTHCPHYS pPhysHC = 0;
3899
3900	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3901	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3902	}
3903	}
3904	}
3905	return VINF_SUCCESS;
3906	}
3907
3908
3909	/**
3910	* Dumps a 32-bit guest page directory and page tables.
3911	*
3912	* @returns VBox status code (VINF_SUCCESS).
3913	* @param pVM The VM handle.
3914	* @param cr3 The root of the hierarchy.
3915	* @param cr4 The CR4, PSE is currently used.
3916	* @param PhysSearch Address to search for.
3917	*/
3918	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3919	{
3920	bool fLongMode = false;
3921	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3922	PX86PD pPD = 0;
3923
3924	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3925	if (VBOX_FAILURE(rc) \|\| !pPD)
3926	{
3927	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3928	return VERR_INVALID_PARAMETER;
3929	}
3930
3931	Log(("cr3=%08x cr4=%08x%s\n"
3932	"%-*s P - Present\n"
3933	"%-*s \| R/W - Read (0) / Write (1)\n"
3934	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3935	"%-*s \| \| \| A - Accessed\n"
3936	"%-*s \| \| \| \| D - Dirty\n"
3937	"%-*s \| \| \| \| \| G - Global\n"
3938	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3939	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3940	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3941	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3942	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3943	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3944	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3945	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3946	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3947	- W U - - - -- -- -- -- -- 010 */
3948	, cr3, cr4, fLongMode ? " Long Mode" : "",
3949	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3950	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3951
3952	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3953	{
3954	X86PDE Pde = pPD->a[i];
3955	if (Pde.n.u1Present)
3956	{
3957	const uint32_t u32Address = i << X86_PD_SHIFT;
3958
3959	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3960	Log(( /P R S A D G WT CD AT NX 4M a m d /
3961	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3962	u32Address,
3963	Pde.b.u1Write ? 'W' : 'R',
3964	Pde.b.u1User ? 'U' : 'S',
3965	Pde.b.u1Accessed ? 'A' : '-',
3966	Pde.b.u1Dirty ? 'D' : '-',
3967	Pde.b.u1Global ? 'G' : '-',
3968	Pde.b.u1WriteThru ? "WT" : "--",
3969	Pde.b.u1CacheDisable? "CD" : "--",
3970	Pde.b.u1PAT ? "AT" : "--",
3971	Pde.u & RT_BIT(9) ? '1' : '0',
3972	Pde.u & RT_BIT(10) ? '1' : '0',
3973	Pde.u & RT_BIT(11) ? '1' : '0',
3974	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3975	/** @todo PhysSearch */
3976	else
3977	{
3978	Log(( /P R S A D G WT CD AT NX 4M a m d /
3979	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3980	u32Address,
3981	Pde.n.u1Write ? 'W' : 'R',
3982	Pde.n.u1User ? 'U' : 'S',
3983	Pde.n.u1Accessed ? 'A' : '-',
3984	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3985	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3986	Pde.n.u1WriteThru ? "WT" : "--",
3987	Pde.n.u1CacheDisable? "CD" : "--",
3988	Pde.u & RT_BIT(9) ? '1' : '0',
3989	Pde.u & RT_BIT(10) ? '1' : '0',
3990	Pde.u & RT_BIT(11) ? '1' : '0',
3991	Pde.u & X86_PDE_PG_MASK));
3992	////if (cMaxDepth >= 1)
3993	{
3994	/** @todo what about using the page pool for mapping PTs? */
3995	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3996	PX86PT pPT = NULL;
3997
3998	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3999
4000	int rc2 = VERR_INVALID_PARAMETER;
4001	if (pPT)
4002	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4003	else
4004	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4005	if (rc2 < rc && VBOX_SUCCESS(rc))
4006	rc = rc2;
4007	}
4008	}
4009	}
4010	}
4011
4012	return rc;
4013	}
4014
4015
4016	/**
4017	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4018	*
4019	* @returns VBox status code (VINF_SUCCESS).
4020	* @param pVM The VM handle.
4021	* @param cr3 The root of the hierarchy.
4022	* @param cr4 The cr4, only PAE and PSE is currently used.
4023	* @param fLongMode Set if long mode, false if not long mode.
4024	* @param cMaxDepth Number of levels to dump.
4025	* @param pHlp Pointer to the output functions.
4026	*/
4027	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4028	{
4029	if (!pHlp)
4030	pHlp = DBGFR3InfoLogHlp();
4031	if (!cMaxDepth)
4032	return VINF_SUCCESS;
4033	const unsigned cch = fLongMode ? 16 : 8;
4034	pHlp->pfnPrintf(pHlp,
4035	"cr3=%08x cr4=%08x%s\n"
4036	"%-*s P - Present\n"
4037	"%-*s \| R/W - Read (0) / Write (1)\n"
4038	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4039	"%-*s \| \| \| A - Accessed\n"
4040	"%-*s \| \| \| \| D - Dirty\n"
4041	"%-*s \| \| \| \| \| G - Global\n"
4042	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4043	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4044	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4045	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4046	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4047	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4048	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4049	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4050	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4051	- W U - - - -- -- -- -- -- 010 */
4052	, cr3, cr4, fLongMode ? " Long Mode" : "",
4053	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4054	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4055	if (cr4 & X86_CR4_PAE)
4056	{
4057	if (fLongMode)
4058	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4059	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4060	}
4061	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4062	}
4063
4064	#ifdef VBOX_WITH_DEBUGGER
4065
4066	/**
4067	* The '.pgmram' command.
4068	*
4069	* @returns VBox status.
4070	* @param pCmd Pointer to the command descriptor (as registered).
4071	* @param pCmdHlp Pointer to command helper functions.
4072	* @param pVM Pointer to the current VM (if any).
4073	* @param paArgs Pointer to (readonly) array of arguments.
4074	* @param cArgs Number of arguments in the array.
4075	*/
4076	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4077	{
4078	/*
4079	* Validate input.
4080	*/
4081	if (!pVM)
4082	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4083	if (!pVM->pgm.s.pRamRangesRC)
4084	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4085
4086	/*
4087	* Dump the ranges.
4088	*/
4089	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4090	PPGMRAMRANGE pRam;
4091	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4092	{
4093	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4094	"%RGp - %RGp %p\n",
4095	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4096	if (VBOX_FAILURE(rc))
4097	return rc;
4098	}
4099
4100	return VINF_SUCCESS;
4101	}
4102
4103
4104	/**
4105	* The '.pgmmap' command.
4106	*
4107	* @returns VBox status.
4108	* @param pCmd Pointer to the command descriptor (as registered).
4109	* @param pCmdHlp Pointer to command helper functions.
4110	* @param pVM Pointer to the current VM (if any).
4111	* @param paArgs Pointer to (readonly) array of arguments.
4112	* @param cArgs Number of arguments in the array.
4113	*/
4114	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4115	{
4116	/*
4117	* Validate input.
4118	*/
4119	if (!pVM)
4120	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4121	if (!pVM->pgm.s.pMappingsR3)
4122	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4123
4124	/*
4125	* Print message about the fixedness of the mappings.
4126	*/
4127	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4128	if (VBOX_FAILURE(rc))
4129	return rc;
4130
4131	/*
4132	* Dump the ranges.
4133	*/
4134	PPGMMAPPING pCur;
4135	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4136	{
4137	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4138	"%08x - %08x %s\n",
4139	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4140	if (VBOX_FAILURE(rc))
4141	return rc;
4142	}
4143
4144	return VINF_SUCCESS;
4145	}
4146
4147
4148	/**
4149	* The '.pgmsync' command.
4150	*
4151	* @returns VBox status.
4152	* @param pCmd Pointer to the command descriptor (as registered).
4153	* @param pCmdHlp Pointer to command helper functions.
4154	* @param pVM Pointer to the current VM (if any).
4155	* @param paArgs Pointer to (readonly) array of arguments.
4156	* @param cArgs Number of arguments in the array.
4157	*/
4158	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4159	{
4160	/*
4161	* Validate input.
4162	*/
4163	if (!pVM)
4164	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4165
4166	/*
4167	* Force page directory sync.
4168	*/
4169	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4170
4171	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4172	if (VBOX_FAILURE(rc))
4173	return rc;
4174
4175	return VINF_SUCCESS;
4176	}
4177
4178
4179	#ifdef VBOX_STRICT
4180	/**
4181	* The '.pgmassertcr3' command.
4182	*
4183	* @returns VBox status.
4184	* @param pCmd Pointer to the command descriptor (as registered).
4185	* @param pCmdHlp Pointer to command helper functions.
4186	* @param pVM Pointer to the current VM (if any).
4187	* @param paArgs Pointer to (readonly) array of arguments.
4188	* @param cArgs Number of arguments in the array.
4189	*/
4190	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4191	{
4192	/*
4193	* Validate input.
4194	*/
4195	if (!pVM)
4196	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4197
4198	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4199	if (VBOX_FAILURE(rc))
4200	return rc;
4201
4202	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4203
4204	return VINF_SUCCESS;
4205	}
4206	#endif /* VBOX_STRICT */
4207
4208
4209	/**
4210	* The '.pgmsyncalways' command.
4211	*
4212	* @returns VBox status.
4213	* @param pCmd Pointer to the command descriptor (as registered).
4214	* @param pCmdHlp Pointer to command helper functions.
4215	* @param pVM Pointer to the current VM (if any).
4216	* @param paArgs Pointer to (readonly) array of arguments.
4217	* @param cArgs Number of arguments in the array.
4218	*/
4219	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4220	{
4221	/*
4222	* Validate input.
4223	*/
4224	if (!pVM)
4225	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4226
4227	/*
4228	* Force page directory sync.
4229	*/
4230	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4231	{
4232	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4233	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4234	}
4235	else
4236	{
4237	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4238	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4239	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4240	}
4241	}
4242
4243	#endif /* VBOX_WITH_DEBUGGER */
4244
4245	/**
4246	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4247	*/
4248	typedef struct PGMCHECKINTARGS
4249	{
4250	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4251	PPGMPHYSHANDLER pPrevPhys;
4252	PPGMVIRTHANDLER pPrevVirt;
4253	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4254	PVM pVM;
4255	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4256
4257	/**
4258	* Validate a node in the physical handler tree.
4259	*
4260	* @returns 0 on if ok, other wise 1.
4261	* @param pNode The handler node.
4262	* @param pvUser pVM.
4263	*/
4264	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4265	{
4266	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4267	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4268	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4269	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4270	AssertReleaseMsg( !pArgs->pPrevPhys
4271	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4272	("pPrevPhys=%p %VGp-%VGp %s\n"
4273	" pCur=%p %VGp-%VGp %s\n",
4274	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4275	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4276	pArgs->pPrevPhys = pCur;
4277	return 0;
4278	}
4279
4280
4281	/**
4282	* Validate a node in the virtual handler tree.
4283	*
4284	* @returns 0 on if ok, other wise 1.
4285	* @param pNode The handler node.
4286	* @param pvUser pVM.
4287	*/
4288	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4289	{
4290	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4291	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4292	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4293	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4294	AssertReleaseMsg( !pArgs->pPrevVirt
4295	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4296	("pPrevVirt=%p %VGv-%VGv %s\n"
4297	" pCur=%p %VGv-%VGv %s\n",
4298	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4299	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4300	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4301	{
4302	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4303	("pCur=%p %VGv-%VGv %s\n"
4304	"iPage=%d offVirtHandle=%#x expected %#x\n",
4305	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4306	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4307	}
4308	pArgs->pPrevVirt = pCur;
4309	return 0;
4310	}
4311
4312
4313	/**
4314	* Validate a node in the virtual handler tree.
4315	*
4316	* @returns 0 on if ok, other wise 1.
4317	* @param pNode The handler node.
4318	* @param pvUser pVM.
4319	*/
4320	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4321	{
4322	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4323	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4324	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4325	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4326	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4327	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4328	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4329	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4330	" pCur=%p %VGp-%VGp\n",
4331	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4332	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4333	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4334	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4335	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4336	" pCur=%p %VGp-%VGp\n",
4337	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4338	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4339	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4340	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4341	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4342	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4343	{
4344	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4345	for (;;)
4346	{
4347	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4348	AssertReleaseMsg(pCur2 != pCur,
4349	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4350	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4351	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4352	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4353	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4354	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4355	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4356	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4357	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4358	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4359	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4360	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4361	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4362	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4363	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4364	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4365	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4366	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4367	break;
4368	}
4369	}
4370
4371	pArgs->pPrevPhys2Virt = pCur;
4372	return 0;
4373	}
4374
4375
4376	/**
4377	* Perform an integrity check on the PGM component.
4378	*
4379	* @returns VINF_SUCCESS if everything is fine.
4380	* @returns VBox error status after asserting on integrity breach.
4381	* @param pVM The VM handle.
4382	*/
4383	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4384	{
4385	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4386
4387	/*
4388	* Check the trees.
4389	*/
4390	int cErrors = 0;
4391	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4392	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4393	PGMCHECKINTARGS Args = s_LeftToRight;
4394	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4395	Args = s_RightToLeft;
4396	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4397	Args = s_LeftToRight;
4398	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4399	Args = s_RightToLeft;
4400	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4401	Args = s_LeftToRight;
4402	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4403	Args = s_RightToLeft;
4404	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4405	Args = s_LeftToRight;
4406	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4407	Args = s_RightToLeft;
4408	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4409
4410	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4411	}
4412
4413
4414	/**
4415	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4416	*
4417	* @returns VBox status code.
4418	* @param pVM VM handle.
4419	* @param fEnable Enable or disable shadow mappings
4420	*/
4421	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4422	{
4423	pVM->pgm.s.fDisableMappings = !fEnable;
4424
4425	uint32_t cb;
4426	int rc = PGMR3MappingsSize(pVM, &cb);
4427	AssertRCReturn(rc, rc);
4428
4429	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4430	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4431	AssertRCReturn(rc, rc);
4432
4433	return VINF_SUCCESS;
4434	}
4435

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 13232

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