PGM.cpp@ 30495

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1	/* $Id: PGM.cpp 30488 2010-06-29 09:02:04Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @see grp_pgm,
22	* @ref pg_pgm_pool,
23	* @ref pg_pgm_phys.
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be refered to
30	* as "host paging", and GC refered to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successfull this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgm_phys PGM Physical Guest Memory Management
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery assoicated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attemted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separeate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the otherway around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
484	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
485	* memory context for the HWACCM execution.
486	*
487	*
488	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
489	*
490	* We've considered implementing the ring-3 mapping cache page based but found
491	* that this was bother some when one had to take into account TLBs+SMP and
492	* portability (missing the necessary APIs on several platforms). There were
493	* also some performance concerns with this approach which hadn't quite been
494	* worked out.
495	*
496	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
497	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
498	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
499	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
500	* costly than a single page, although how much more costly is uncertain. We'll
501	* try address this by using a very big cache, preferably bigger than the actual
502	* VM RAM size if possible. The current VM RAM sizes should give some idea for
503	* 32-bit boxes, while on 64-bit we can probably get away with employing an
504	* unlimited cache.
505	*
506	* The cache have to parts, as already indicated, the ring-3 side and the
507	* ring-0 side.
508	*
509	* The ring-0 will be tied to the page allocator since it will operate on the
510	* memory objects it contains. It will therefore require the first ring-0 mutex
511	* discussed in @ref subsec_pgmPhys_Serializing. We
512	* some double house keeping wrt to who has mapped what I think, since both
513	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
514	*
515	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
516	* require anyone that desires to do changes to the mapping cache to do that
517	* from within this critsect. Alternatively, we could employ a separate critsect
518	* for serializing changes to the mapping cache as this would reduce potential
519	* contention with other threads accessing mappings unrelated to the changes
520	* that are in process. We can see about this later, contention will show
521	* up in the statistics anyway, so it'll be simple to tell.
522	*
523	* The organization of the ring-3 part will be very much like how the allocation
524	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
525	* having to walk the tree all the time, we'll have a couple of lookaside entries
526	* like in we do for I/O ports and MMIO in IOM.
527	*
528	* The simplified flow of a PGMPhysRead/Write function:
529	* -# Enter the PGM critsect.
530	* -# Lookup GCPhys in the ram ranges and get the Page ID.
531	* -# Calc the Allocation Chunk ID from the Page ID.
532	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
533	* If not found in cache:
534	* -# Call ring-0 and request it to be mapped and supply
535	* a chunk to be unmapped if the cache is maxed out already.
536	* -# Insert the new mapping into the AVL tree (id + R3 address).
537	* -# Update the relevant lookaside entry and return the mapping address.
538	* -# Do the read/write according to monitoring flags and everything.
539	* -# Leave the critsect.
540	*
541	*
542	* @section sec_pgmPhys_Fallback Fallback
543	*
544	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
545	* API and thus require a fallback.
546	*
547	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
548	* will return to the ring-3 caller (and later ring-0) and asking it to seed
549	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
550	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
551	* "SeededAllocPages" call to ring-0.
552	*
553	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
554	* all page sharing (zero page detection will continue). It will also force
555	* all allocations to come from the VM which seeded the page. Both these
556	* measures are taken to make sure that there will never be any need for
557	* mapping anything into ring-3 - everything will be mapped already.
558	*
559	* Whether we'll continue to use the current MM locked memory management
560	* for this I don't quite know (I'd prefer not to and just ditch that all
561	* togther), we'll see what's simplest to do.
562	*
563	*
564	*
565	* @section sec_pgmPhys_Changes Changes
566	*
567	* Breakdown of the changes involved?
568	*/
569
570	/*******************************************************************************
571	* Header Files *
572	*******************************************************************************/
573	#define LOG_GROUP LOG_GROUP_PGM
574	#include <VBox/dbgf.h>
575	#include <VBox/pgm.h>
576	#include <VBox/cpum.h>
577	#include <VBox/iom.h>
578	#include <VBox/sup.h>
579	#include <VBox/mm.h>
580	#include <VBox/em.h>
581	#include <VBox/stam.h>
582	#include <VBox/rem.h>
583	#include <VBox/selm.h>
584	#include <VBox/ssm.h>
585	#include <VBox/hwaccm.h>
586	#include "PGMInternal.h"
587	#include <VBox/vm.h>
588	#include "PGMInline.h"
589
590	#include <VBox/dbg.h>
591	#include <VBox/param.h>
592	#include <VBox/err.h>
593
594	#include <iprt/asm.h>
595	#include <iprt/assert.h>
596	#include <iprt/env.h>
597	#include <iprt/mem.h>
598	#include <iprt/file.h>
599	#include <iprt/string.h>
600	#include <iprt/thread.h>
601
602
603	/*******************************************************************************
604	* Defined Constants And Macros *
605	*******************************************************************************/
606	/** Saved state data unit version for 2.5.x and later. */
607	#define PGM_SAVED_STATE_VERSION 9
608	/** Saved state data unit version for 2.2.2 and later. */
609	#define PGM_SAVED_STATE_VERSION_2_2_2 8
610	/** Saved state data unit version for 2.2.0. */
611	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
612	/** Saved state data unit version. */
613	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
614
615
616	/*******************************************************************************
617	* Internal Functions *
618	*******************************************************************************/
619	static int pgmR3InitPaging(PVM pVM);
620	static void pgmR3InitStats(PVM pVM);
621	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
622	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
623	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
624	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
625	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
626	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
627	#ifdef VBOX_STRICT
628	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
629	#endif
630	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
631	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
632	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
633
634	#ifdef VBOX_WITH_DEBUGGER
635	/** @todo Convert the first two commands to 'info' items. */
636	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
637	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	# ifdef VBOX_STRICT
641	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	# endif
643	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
644	static DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
645	# endif
646	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
647	#endif
648
649
650	/*******************************************************************************
651	* Global Variables *
652	*******************************************************************************/
653	#ifdef VBOX_WITH_DEBUGGER
654	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
655	static const DBGCVARDESC g_aPgmErrorArgs[] =
656	{
657	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
658	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
659	};
660
661	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
662	{
663	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
664	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
665	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
666	};
667
668	/** Command descriptors. */
669	static const DBGCCMD g_aCmds[] =
670	{
671	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
672	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
673	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
674	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
675	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
676	#ifdef VBOX_STRICT
677	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
678	#endif
679	#if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
680	{ "pgmcheckduppages", 0, 0, NULL, 0, NULL, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
681	#endif
682	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
683	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
684	};
685	#endif
686
687
688
689
690	/*
691	* Shadow - 32-bit mode
692	*/
693	#define PGM_SHW_TYPE PGM_TYPE_32BIT
694	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
695	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
696	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
697	#include "PGMShw.h"
698
699	/* Guest - real mode */
700	#define PGM_GST_TYPE PGM_TYPE_REAL
701	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
702	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
703	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
704	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
705	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
706	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
707	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
708	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
709	#include "PGMBth.h"
710	#include "PGMGstDefs.h"
711	#include "PGMGst.h"
712	#undef BTH_PGMPOOLKIND_PT_FOR_PT
713	#undef BTH_PGMPOOLKIND_ROOT
714	#undef PGM_BTH_NAME
715	#undef PGM_BTH_NAME_RC_STR
716	#undef PGM_BTH_NAME_R0_STR
717	#undef PGM_GST_TYPE
718	#undef PGM_GST_NAME
719	#undef PGM_GST_NAME_RC_STR
720	#undef PGM_GST_NAME_R0_STR
721
722	/* Guest - protected mode */
723	#define PGM_GST_TYPE PGM_TYPE_PROT
724	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
725	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
726	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
727	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
728	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
729	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
730	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
731	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
732	#include "PGMBth.h"
733	#include "PGMGstDefs.h"
734	#include "PGMGst.h"
735	#undef BTH_PGMPOOLKIND_PT_FOR_PT
736	#undef BTH_PGMPOOLKIND_ROOT
737	#undef PGM_BTH_NAME
738	#undef PGM_BTH_NAME_RC_STR
739	#undef PGM_BTH_NAME_R0_STR
740	#undef PGM_GST_TYPE
741	#undef PGM_GST_NAME
742	#undef PGM_GST_NAME_RC_STR
743	#undef PGM_GST_NAME_R0_STR
744
745	/* Guest - 32-bit mode */
746	#define PGM_GST_TYPE PGM_TYPE_32BIT
747	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
748	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
749	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
750	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
751	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
752	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
753	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
754	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
755	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
756	#include "PGMBth.h"
757	#include "PGMGstDefs.h"
758	#include "PGMGst.h"
759	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
760	#undef BTH_PGMPOOLKIND_PT_FOR_PT
761	#undef BTH_PGMPOOLKIND_ROOT
762	#undef PGM_BTH_NAME
763	#undef PGM_BTH_NAME_RC_STR
764	#undef PGM_BTH_NAME_R0_STR
765	#undef PGM_GST_TYPE
766	#undef PGM_GST_NAME
767	#undef PGM_GST_NAME_RC_STR
768	#undef PGM_GST_NAME_R0_STR
769
770	#undef PGM_SHW_TYPE
771	#undef PGM_SHW_NAME
772	#undef PGM_SHW_NAME_RC_STR
773	#undef PGM_SHW_NAME_R0_STR
774
775
776	/*
777	* Shadow - PAE mode
778	*/
779	#define PGM_SHW_TYPE PGM_TYPE_PAE
780	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
781	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
782	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
783	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
784	#include "PGMShw.h"
785
786	/* Guest - real mode */
787	#define PGM_GST_TYPE PGM_TYPE_REAL
788	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
789	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
790	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
791	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
792	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
793	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
794	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
795	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
796	#include "PGMGstDefs.h"
797	#include "PGMBth.h"
798	#undef BTH_PGMPOOLKIND_PT_FOR_PT
799	#undef BTH_PGMPOOLKIND_ROOT
800	#undef PGM_BTH_NAME
801	#undef PGM_BTH_NAME_RC_STR
802	#undef PGM_BTH_NAME_R0_STR
803	#undef PGM_GST_TYPE
804	#undef PGM_GST_NAME
805	#undef PGM_GST_NAME_RC_STR
806	#undef PGM_GST_NAME_R0_STR
807
808	/* Guest - protected mode */
809	#define PGM_GST_TYPE PGM_TYPE_PROT
810	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
811	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
812	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
813	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
814	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
815	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
816	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
817	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
818	#include "PGMGstDefs.h"
819	#include "PGMBth.h"
820	#undef BTH_PGMPOOLKIND_PT_FOR_PT
821	#undef BTH_PGMPOOLKIND_ROOT
822	#undef PGM_BTH_NAME
823	#undef PGM_BTH_NAME_RC_STR
824	#undef PGM_BTH_NAME_R0_STR
825	#undef PGM_GST_TYPE
826	#undef PGM_GST_NAME
827	#undef PGM_GST_NAME_RC_STR
828	#undef PGM_GST_NAME_R0_STR
829
830	/* Guest - 32-bit mode */
831	#define PGM_GST_TYPE PGM_TYPE_32BIT
832	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
833	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
834	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
835	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
836	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
837	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
838	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
839	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
840	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
841	#include "PGMGstDefs.h"
842	#include "PGMBth.h"
843	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
844	#undef BTH_PGMPOOLKIND_PT_FOR_PT
845	#undef BTH_PGMPOOLKIND_ROOT
846	#undef PGM_BTH_NAME
847	#undef PGM_BTH_NAME_RC_STR
848	#undef PGM_BTH_NAME_R0_STR
849	#undef PGM_GST_TYPE
850	#undef PGM_GST_NAME
851	#undef PGM_GST_NAME_RC_STR
852	#undef PGM_GST_NAME_R0_STR
853
854	/* Guest - PAE mode */
855	#define PGM_GST_TYPE PGM_TYPE_PAE
856	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
857	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
858	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
859	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
860	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
861	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
862	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
863	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
864	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
865	#include "PGMBth.h"
866	#include "PGMGstDefs.h"
867	#include "PGMGst.h"
868	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
869	#undef BTH_PGMPOOLKIND_PT_FOR_PT
870	#undef BTH_PGMPOOLKIND_ROOT
871	#undef PGM_BTH_NAME
872	#undef PGM_BTH_NAME_RC_STR
873	#undef PGM_BTH_NAME_R0_STR
874	#undef PGM_GST_TYPE
875	#undef PGM_GST_NAME
876	#undef PGM_GST_NAME_RC_STR
877	#undef PGM_GST_NAME_R0_STR
878
879	#undef PGM_SHW_TYPE
880	#undef PGM_SHW_NAME
881	#undef PGM_SHW_NAME_RC_STR
882	#undef PGM_SHW_NAME_R0_STR
883
884
885	/*
886	* Shadow - AMD64 mode
887	*/
888	#define PGM_SHW_TYPE PGM_TYPE_AMD64
889	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
890	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
891	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
892	#include "PGMShw.h"
893
894	#ifdef VBOX_WITH_64_BITS_GUESTS
895	/* Guest - AMD64 mode */
896	# define PGM_GST_TYPE PGM_TYPE_AMD64
897	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
898	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
899	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
900	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
901	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
902	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
903	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
904	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
905	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
906	# include "PGMBth.h"
907	# include "PGMGstDefs.h"
908	# include "PGMGst.h"
909	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
910	# undef BTH_PGMPOOLKIND_PT_FOR_PT
911	# undef BTH_PGMPOOLKIND_ROOT
912	# undef PGM_BTH_NAME
913	# undef PGM_BTH_NAME_RC_STR
914	# undef PGM_BTH_NAME_R0_STR
915	# undef PGM_GST_TYPE
916	# undef PGM_GST_NAME
917	# undef PGM_GST_NAME_RC_STR
918	# undef PGM_GST_NAME_R0_STR
919	#endif /* VBOX_WITH_64_BITS_GUESTS */
920
921	#undef PGM_SHW_TYPE
922	#undef PGM_SHW_NAME
923	#undef PGM_SHW_NAME_RC_STR
924	#undef PGM_SHW_NAME_R0_STR
925
926
927	/*
928	* Shadow - Nested paging mode
929	*/
930	#define PGM_SHW_TYPE PGM_TYPE_NESTED
931	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
932	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
933	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
934	#include "PGMShw.h"
935
936	/* Guest - real mode */
937	#define PGM_GST_TYPE PGM_TYPE_REAL
938	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
939	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
940	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
941	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
942	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
943	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
944	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
945	#include "PGMGstDefs.h"
946	#include "PGMBth.h"
947	#undef BTH_PGMPOOLKIND_PT_FOR_PT
948	#undef PGM_BTH_NAME
949	#undef PGM_BTH_NAME_RC_STR
950	#undef PGM_BTH_NAME_R0_STR
951	#undef PGM_GST_TYPE
952	#undef PGM_GST_NAME
953	#undef PGM_GST_NAME_RC_STR
954	#undef PGM_GST_NAME_R0_STR
955
956	/* Guest - protected mode */
957	#define PGM_GST_TYPE PGM_TYPE_PROT
958	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
959	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
960	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
961	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
962	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
963	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
964	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
965	#include "PGMGstDefs.h"
966	#include "PGMBth.h"
967	#undef BTH_PGMPOOLKIND_PT_FOR_PT
968	#undef PGM_BTH_NAME
969	#undef PGM_BTH_NAME_RC_STR
970	#undef PGM_BTH_NAME_R0_STR
971	#undef PGM_GST_TYPE
972	#undef PGM_GST_NAME
973	#undef PGM_GST_NAME_RC_STR
974	#undef PGM_GST_NAME_R0_STR
975
976	/* Guest - 32-bit mode */
977	#define PGM_GST_TYPE PGM_TYPE_32BIT
978	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
979	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
980	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
981	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
982	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
983	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
984	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
985	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
986	#include "PGMGstDefs.h"
987	#include "PGMBth.h"
988	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
989	#undef BTH_PGMPOOLKIND_PT_FOR_PT
990	#undef PGM_BTH_NAME
991	#undef PGM_BTH_NAME_RC_STR
992	#undef PGM_BTH_NAME_R0_STR
993	#undef PGM_GST_TYPE
994	#undef PGM_GST_NAME
995	#undef PGM_GST_NAME_RC_STR
996	#undef PGM_GST_NAME_R0_STR
997
998	/* Guest - PAE mode */
999	#define PGM_GST_TYPE PGM_TYPE_PAE
1000	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1001	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1002	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1003	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1004	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1005	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1006	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1007	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1008	#include "PGMGstDefs.h"
1009	#include "PGMBth.h"
1010	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1011	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1012	#undef PGM_BTH_NAME
1013	#undef PGM_BTH_NAME_RC_STR
1014	#undef PGM_BTH_NAME_R0_STR
1015	#undef PGM_GST_TYPE
1016	#undef PGM_GST_NAME
1017	#undef PGM_GST_NAME_RC_STR
1018	#undef PGM_GST_NAME_R0_STR
1019
1020	#ifdef VBOX_WITH_64_BITS_GUESTS
1021	/* Guest - AMD64 mode */
1022	# define PGM_GST_TYPE PGM_TYPE_AMD64
1023	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1024	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1025	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1026	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1027	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1028	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1029	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1030	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1031	# include "PGMGstDefs.h"
1032	# include "PGMBth.h"
1033	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1034	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1035	# undef PGM_BTH_NAME
1036	# undef PGM_BTH_NAME_RC_STR
1037	# undef PGM_BTH_NAME_R0_STR
1038	# undef PGM_GST_TYPE
1039	# undef PGM_GST_NAME
1040	# undef PGM_GST_NAME_RC_STR
1041	# undef PGM_GST_NAME_R0_STR
1042	#endif /* VBOX_WITH_64_BITS_GUESTS */
1043
1044	#undef PGM_SHW_TYPE
1045	#undef PGM_SHW_NAME
1046	#undef PGM_SHW_NAME_RC_STR
1047	#undef PGM_SHW_NAME_R0_STR
1048
1049
1050	/*
1051	* Shadow - EPT
1052	*/
1053	#define PGM_SHW_TYPE PGM_TYPE_EPT
1054	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1055	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1056	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1057	#include "PGMShw.h"
1058
1059	/* Guest - real mode */
1060	#define PGM_GST_TYPE PGM_TYPE_REAL
1061	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1062	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1063	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1064	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1065	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1066	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1067	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1068	#include "PGMGstDefs.h"
1069	#include "PGMBth.h"
1070	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1071	#undef PGM_BTH_NAME
1072	#undef PGM_BTH_NAME_RC_STR
1073	#undef PGM_BTH_NAME_R0_STR
1074	#undef PGM_GST_TYPE
1075	#undef PGM_GST_NAME
1076	#undef PGM_GST_NAME_RC_STR
1077	#undef PGM_GST_NAME_R0_STR
1078
1079	/* Guest - protected mode */
1080	#define PGM_GST_TYPE PGM_TYPE_PROT
1081	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1082	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1083	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1084	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1085	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1086	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1087	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1088	#include "PGMGstDefs.h"
1089	#include "PGMBth.h"
1090	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1091	#undef PGM_BTH_NAME
1092	#undef PGM_BTH_NAME_RC_STR
1093	#undef PGM_BTH_NAME_R0_STR
1094	#undef PGM_GST_TYPE
1095	#undef PGM_GST_NAME
1096	#undef PGM_GST_NAME_RC_STR
1097	#undef PGM_GST_NAME_R0_STR
1098
1099	/* Guest - 32-bit mode */
1100	#define PGM_GST_TYPE PGM_TYPE_32BIT
1101	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1102	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1103	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1104	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1105	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1106	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1107	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1108	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1109	#include "PGMGstDefs.h"
1110	#include "PGMBth.h"
1111	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1112	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1113	#undef PGM_BTH_NAME
1114	#undef PGM_BTH_NAME_RC_STR
1115	#undef PGM_BTH_NAME_R0_STR
1116	#undef PGM_GST_TYPE
1117	#undef PGM_GST_NAME
1118	#undef PGM_GST_NAME_RC_STR
1119	#undef PGM_GST_NAME_R0_STR
1120
1121	/* Guest - PAE mode */
1122	#define PGM_GST_TYPE PGM_TYPE_PAE
1123	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1124	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1125	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1126	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1127	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1128	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1129	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1130	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1131	#include "PGMGstDefs.h"
1132	#include "PGMBth.h"
1133	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1134	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1135	#undef PGM_BTH_NAME
1136	#undef PGM_BTH_NAME_RC_STR
1137	#undef PGM_BTH_NAME_R0_STR
1138	#undef PGM_GST_TYPE
1139	#undef PGM_GST_NAME
1140	#undef PGM_GST_NAME_RC_STR
1141	#undef PGM_GST_NAME_R0_STR
1142
1143	#ifdef VBOX_WITH_64_BITS_GUESTS
1144	/* Guest - AMD64 mode */
1145	# define PGM_GST_TYPE PGM_TYPE_AMD64
1146	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1147	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1148	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1149	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1150	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1151	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1152	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1153	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1154	# include "PGMGstDefs.h"
1155	# include "PGMBth.h"
1156	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1157	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1158	# undef PGM_BTH_NAME
1159	# undef PGM_BTH_NAME_RC_STR
1160	# undef PGM_BTH_NAME_R0_STR
1161	# undef PGM_GST_TYPE
1162	# undef PGM_GST_NAME
1163	# undef PGM_GST_NAME_RC_STR
1164	# undef PGM_GST_NAME_R0_STR
1165	#endif /* VBOX_WITH_64_BITS_GUESTS */
1166
1167	#undef PGM_SHW_TYPE
1168	#undef PGM_SHW_NAME
1169	#undef PGM_SHW_NAME_RC_STR
1170	#undef PGM_SHW_NAME_R0_STR
1171
1172
1173
1174	/**
1175	* Initiates the paging of VM.
1176	*
1177	* @returns VBox status code.
1178	* @param pVM Pointer to VM structure.
1179	*/
1180	VMMR3DECL(int) PGMR3Init(PVM pVM)
1181	{
1182	LogFlow(("PGMR3Init:\n"));
1183	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1184	int rc;
1185
1186	/*
1187	* Assert alignment and sizes.
1188	*/
1189	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1190	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1191	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1192
1193	/*
1194	* Init the structure.
1195	*/
1196	#ifdef PGM_WITHOUT_MAPPINGS
1197	pVM->pgm.s.fMappingsDisabled = true;
1198	#endif
1199	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1200	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1201
1202	/* Init the per-CPU part. */
1203	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1204	{
1205	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1206	PPGMCPU pPGM = &pVCpu->pgm.s;
1207
1208	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1209	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1210	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1211
1212	pPGM->enmShadowMode = PGMMODE_INVALID;
1213	pPGM->enmGuestMode = PGMMODE_INVALID;
1214
1215	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1216
1217	pPGM->pGstPaePdptR3 = NULL;
1218	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1219	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1220	#endif
1221	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1222	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1223	{
1224	pPGM->apGstPaePDsR3[i] = NULL;
1225	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1226	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1227	#endif
1228	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1229	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1230	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1231	}
1232
1233	pPGM->fA20Enabled = true;
1234	}
1235
1236	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1237	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1238	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1239
1240	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1241	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1242	true
1243	#else
1244	false
1245	#endif
1246	);
1247	AssertLogRelRCReturn(rc, rc);
1248
1249	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1250	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1251	#else
1252	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1253	#endif
1254	AssertLogRelRCReturn(rc, rc);
1255	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1256	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1257
1258	/*
1259	* Get the configured RAM size - to estimate saved state size.
1260	*/
1261	uint64_t cbRam;
1262	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1263	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1264	cbRam = 0;
1265	else if (RT_SUCCESS(rc))
1266	{
1267	if (cbRam < PAGE_SIZE)
1268	cbRam = 0;
1269	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1270	}
1271	else
1272	{
1273	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1274	return rc;
1275	}
1276
1277	/*
1278	* Register callbacks, string formatters and the saved state data unit.
1279	*/
1280	#ifdef VBOX_STRICT
1281	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1282	#endif
1283	PGMRegisterStringFormatTypes();
1284
1285	rc = pgmR3InitSavedState(pVM, cbRam);
1286	if (RT_FAILURE(rc))
1287	return rc;
1288
1289	/*
1290	* Initialize the PGM critical section and flush the phys TLBs
1291	*/
1292	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, RT_SRC_POS, "PGM");
1293	AssertRCReturn(rc, rc);
1294
1295	PGMR3PhysChunkInvalidateTLB(pVM);
1296	PGMPhysInvalidatePageMapTLB(pVM);
1297
1298	/*
1299	* For the time being we sport a full set of handy pages in addition to the base
1300	* memory to simplify things.
1301	*/
1302	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1303	AssertRCReturn(rc, rc);
1304
1305	/*
1306	* Trees
1307	*/
1308	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1309	if (RT_SUCCESS(rc))
1310	{
1311	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1312	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1313
1314	/*
1315	* Alocate the zero page.
1316	*/
1317	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1318	}
1319	if (RT_SUCCESS(rc))
1320	{
1321	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1322	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1323	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1324	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1325
1326	/*
1327	* Init the paging.
1328	*/
1329	rc = pgmR3InitPaging(pVM);
1330	}
1331	if (RT_SUCCESS(rc))
1332	{
1333	/*
1334	* Init the page pool.
1335	*/
1336	rc = pgmR3PoolInit(pVM);
1337	}
1338	if (RT_SUCCESS(rc))
1339	{
1340	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1341	{
1342	PVMCPU pVCpu = &pVM->aCpus[i];
1343	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1344	if (RT_FAILURE(rc))
1345	break;
1346	}
1347	}
1348
1349	if (RT_SUCCESS(rc))
1350	{
1351	/*
1352	* Info & statistics
1353	*/
1354	DBGFR3InfoRegisterInternal(pVM, "mode",
1355	"Shows the current paging mode. "
1356	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1357	pgmR3InfoMode);
1358	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1359	"Dumps all the entries in the top level paging table. No arguments.",
1360	pgmR3InfoCr3);
1361	DBGFR3InfoRegisterInternal(pVM, "phys",
1362	"Dumps all the physical address ranges. No arguments.",
1363	pgmR3PhysInfo);
1364	DBGFR3InfoRegisterInternal(pVM, "handlers",
1365	"Dumps physical, virtual and hyper virtual handlers. "
1366	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1367	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1368	pgmR3InfoHandlers);
1369	DBGFR3InfoRegisterInternal(pVM, "mappings",
1370	"Dumps guest mappings.",
1371	pgmR3MapInfo);
1372
1373	pgmR3InitStats(pVM);
1374
1375	#ifdef VBOX_WITH_DEBUGGER
1376	/*
1377	* Debugger commands.
1378	*/
1379	static bool s_fRegisteredCmds = false;
1380	if (!s_fRegisteredCmds)
1381	{
1382	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1383	if (RT_SUCCESS(rc2))
1384	s_fRegisteredCmds = true;
1385	}
1386	#endif
1387	return VINF_SUCCESS;
1388	}
1389
1390	/* Almost no cleanup necessary, MM frees all memory. */
1391	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1392
1393	return rc;
1394	}
1395
1396
1397	/**
1398	* Initializes the per-VCPU PGM.
1399	*
1400	* @returns VBox status code.
1401	* @param pVM The VM to operate on.
1402	*/
1403	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1404	{
1405	LogFlow(("PGMR3InitCPU\n"));
1406	return VINF_SUCCESS;
1407	}
1408
1409
1410	/**
1411	* Init paging.
1412	*
1413	* Since we need to check what mode the host is operating in before we can choose
1414	* the right paging functions for the host we have to delay this until R0 has
1415	* been initialized.
1416	*
1417	* @returns VBox status code.
1418	* @param pVM VM handle.
1419	*/
1420	static int pgmR3InitPaging(PVM pVM)
1421	{
1422	/*
1423	* Force a recalculation of modes and switcher so everyone gets notified.
1424	*/
1425	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1426	{
1427	PVMCPU pVCpu = &pVM->aCpus[i];
1428
1429	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1430	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1431	}
1432
1433	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1434
1435	/*
1436	* Allocate static mapping space for whatever the cr3 register
1437	* points to and in the case of PAE mode to the 4 PDs.
1438	*/
1439	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1440	if (RT_FAILURE(rc))
1441	{
1442	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1443	return rc;
1444	}
1445	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1446
1447	/*
1448	* Allocate pages for the three possible intermediate contexts
1449	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1450	* for the sake of simplicity. The AMD64 uses the PAE for the
1451	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1452	*
1453	* We assume that two page tables will be enought for the core code
1454	* mappings (HC virtual and identity).
1455	*/
1456	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1457	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1458	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1459	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1460	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1461	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1462	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1463	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1464	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1465	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1466	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1467	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1468
1469	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1470	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1471	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1472	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1473	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1474	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1475
1476	/*
1477	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1478	*/
1479	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1480	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1481	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1482
1483	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1484	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1485
1486	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1487	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1488	{
1489	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1490	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1491	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1492	}
1493
1494	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1495	{
1496	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1497	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1498	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1499	}
1500
1501	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1502	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1503	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1504	\| HCPhysInterPaePDPT64;
1505
1506	/*
1507	* Initialize paging workers and mode from current host mode
1508	* and the guest running in real mode.
1509	*/
1510	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1511	switch (pVM->pgm.s.enmHostMode)
1512	{
1513	case SUPPAGINGMODE_32_BIT:
1514	case SUPPAGINGMODE_32_BIT_GLOBAL:
1515	case SUPPAGINGMODE_PAE:
1516	case SUPPAGINGMODE_PAE_GLOBAL:
1517	case SUPPAGINGMODE_PAE_NX:
1518	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1519	break;
1520
1521	case SUPPAGINGMODE_AMD64:
1522	case SUPPAGINGMODE_AMD64_GLOBAL:
1523	case SUPPAGINGMODE_AMD64_NX:
1524	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1525	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1526	if (ARCH_BITS != 64)
1527	{
1528	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1529	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1530	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1531	}
1532	#endif
1533	break;
1534	default:
1535	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1536	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1537	}
1538	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1539	if (RT_SUCCESS(rc))
1540	{
1541	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1542	#if HC_ARCH_BITS == 64
1543	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1544	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1545	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1546	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1547	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1548	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1549	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1550	#endif
1551
1552	return VINF_SUCCESS;
1553	}
1554
1555	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1556	return rc;
1557	}
1558
1559
1560	/**
1561	* Init statistics
1562	*/
1563	static void pgmR3InitStats(PVM pVM)
1564	{
1565	PPGM pPGM = &pVM->pgm.s;
1566	int rc;
1567
1568	/* Common - misc variables */
1569	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1570	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1571	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1572	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1573	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1574	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1575	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1576	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1577	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1578	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1579	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1580	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1581	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1582	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1583	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1584
1585	STAM_REL_REG(pVM, &pPGM->StatLargePageAlloc, STAMTYPE_COUNTER, "/PGM/LargePage/Alloc", STAMUNIT_OCCURENCES, "The number of large pages we've used.");
1586	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1587	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1588	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1589
1590	/* Live save */
1591	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1592	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1593	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1594	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1595	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1596	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1597	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1598	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1599	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1600	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1601	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1602	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1603	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1604	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1605	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1606	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1607	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1608	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1609
1610	#ifdef VBOX_WITH_STATISTICS
1611
1612	# define PGM_REG_COUNTER(a, b, c) \
1613	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1614	AssertRC(rc);
1615
1616	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1617	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1618	AssertRC(rc);
1619
1620	# define PGM_REG_PROFILE(a, b, c) \
1621	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1622	AssertRC(rc);
1623
1624	PGM_REG_PROFILE(&pPGM->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1625	PGM_REG_PROFILE(&pPGM->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1626	PGM_REG_PROFILE(&pPGM->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1627	PGM_REG_PROFILE(&pPGM->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1628
1629	PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1630	PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1631	PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1632	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1633	PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1634	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1635	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1636	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1637	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1638	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1639
1640	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1641	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1642	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1643	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1644	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1645	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1646	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1647	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1648	PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1649	PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1650
1651	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1652	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1653	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1654	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1655
1656	PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1657	PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1658	PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1659	PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1660
1661	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1662	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1663	/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1664	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1665	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1666	/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1667
1668	PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1669	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1670	PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1671	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1672	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1673	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1674	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1675	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1676
1677	/* GC only: */
1678	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1679	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1680	PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1681	PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1682
1683	PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1684	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1685	PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1686	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1687	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1688	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1689	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1690	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1691
1692	PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1693	PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1694	PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1695	PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1696	PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1697	PGM_REG_COUNTER(&pPGM->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1698	PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1699
1700	# undef PGM_REG_COUNTER
1701	# undef PGM_REG_PROFILE
1702	#endif
1703
1704	/*
1705	* Note! The layout below matches the member layout exactly!
1706	*/
1707
1708	/*
1709	* Common - stats
1710	*/
1711	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1712	{
1713	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1714
1715	#define PGM_REG_COUNTER(a, b, c) \
1716	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1717	AssertRC(rc);
1718	#define PGM_REG_PROFILE(a, b, c) \
1719	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1720	AssertRC(rc);
1721
1722	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1723
1724	#ifdef VBOX_WITH_STATISTICS
1725
1726	# if 0 /* rarely useful; leave for debugging. */
1727	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1728	STAMR3RegisterF(pVM, &pPgmCpu->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1729	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1730	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPagePD); j++)
1731	STAMR3RegisterF(pVM, &pPgmCpu->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1732	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1733	# endif
1734	/* R0 only: */
1735	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapMigrateInvlPg, "/PGM/CPU%u/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1736	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapGCPageInl, "/PGM/CPU%u/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1737	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1738	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1739	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1740	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1741	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapHCPageInl, "/PGM/CPU%u/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1742	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapHCPageInlHits, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1743	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapHCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1744	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPage, "/PGM/CPU%u/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1745	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetOptimize, "/PGM/CPU%u/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1746	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchFlushes, "/PGM/CPU%u/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1747	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchHits, "/PGM/CPU%u/R0/DynMapPage/SetSearchHits", "Set search hits.");
1748	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchMisses, "/PGM/CPU%u/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1749	PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapHCPage, "/PGM/CPU%u/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1750	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits0, "/PGM/CPU%u/R0/DynMapPage/Hits0", "Hits at iPage+0");
1751	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits1, "/PGM/CPU%u/R0/DynMapPage/Hits1", "Hits at iPage+1");
1752	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits2, "/PGM/CPU%u/R0/DynMapPage/Hits2", "Hits at iPage+2");
1753	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageInvlPg, "/PGM/CPU%u/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1754	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlow, "/PGM/CPU%u/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1755	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%u/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1756	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%u/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1757	//PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMapPage/SlowLostHits", "Lost hits.");
1758	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSubsets, "/PGM/CPU%u/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1759	PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPopFlushes, "/PGM/CPU%u/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1760	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[0], "/PGM/CPU%u/R0/SetSize000..09", "00-09% filled");
1761	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[1], "/PGM/CPU%u/R0/SetSize010..19", "10-19% filled");
1762	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[2], "/PGM/CPU%u/R0/SetSize020..29", "20-29% filled");
1763	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[3], "/PGM/CPU%u/R0/SetSize030..39", "30-39% filled");
1764	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[4], "/PGM/CPU%u/R0/SetSize040..49", "40-49% filled");
1765	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[5], "/PGM/CPU%u/R0/SetSize050..59", "50-59% filled");
1766	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[6], "/PGM/CPU%u/R0/SetSize060..69", "60-69% filled");
1767	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[7], "/PGM/CPU%u/R0/SetSize070..79", "70-79% filled");
1768	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[8], "/PGM/CPU%u/R0/SetSize080..89", "80-89% filled");
1769	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[9], "/PGM/CPU%u/R0/SetSize090..99", "90-99% filled");
1770	PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[10], "/PGM/CPU%u/R0/SetSize100", "100% filled");
1771
1772	/* RZ only: */
1773	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1774	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%u/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1775	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeSyncPT, "/PGM/CPU%u/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1776	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeMapping, "/PGM/CPU%u/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1777	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1778	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeHandlers, "/PGM/CPU%u/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1779	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1780	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1781	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1782	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1783	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1784	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1785	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1786	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1787	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1788	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1789	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1790	PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1791	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1792	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1793	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1794	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersPhysical, "/PGM/CPU%u/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1795	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1796	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1797	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1798	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1799	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1800	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1801	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1802	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1803	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1804	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1805	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1806	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1807	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1808	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1809	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1810	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1811	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1812	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPFUnh, "/PGM/CPU%u/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1813	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1814	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1815	PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1816	#if 0 /* rarely useful; leave for debugging. */
1817	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatRZTrap0ePD); j++)
1818	STAMR3RegisterF(pVM, &pPgmCpu->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1819	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1820	#endif
1821	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1822	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1823	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1824	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1825	PGM_REG_COUNTER(&pPgmCpu->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1826
1827	/* HC only: */
1828
1829	/* RZ & R3: */
1830	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1831	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1832	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1833	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1834	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1835	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1836	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1837	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1838	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1839	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1840	PGM_REG_PROFILE(&pPgmCpu->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1841	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1842	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1843	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1844	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1845	PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1846	PGM_REG_COUNTER(&pPgmCpu->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1847	PGM_REG_PROFILE(&pPgmCpu->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1848	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1849	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1850	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1851	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1852	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1853	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1854	PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1855	PGM_REG_COUNTER(&pPgmCpu->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1856	PGM_REG_PROFILE(&pPgmCpu->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1857	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1858	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1859	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1860	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1861	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1862	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1863	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1864	PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1865	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1866	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1867	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1868	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1869	PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1870	PGM_REG_PROFILE(&pPgmCpu->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1871	PGM_REG_PROFILE(&pPgmCpu->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1872	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1873	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1874	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1875	PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1876	PGM_REG_PROFILE(&pPgmCpu->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1877
1878	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1879	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1880	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1881	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1882	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1883	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1884	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1885	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1886	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1887	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1888	PGM_REG_PROFILE(&pPgmCpu->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1889	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1890	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1891	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1892	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1893	PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1894	PGM_REG_COUNTER(&pPgmCpu->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1895	PGM_REG_PROFILE(&pPgmCpu->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1896	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1897	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1898	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1899	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1900	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1901	PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1902	PGM_REG_COUNTER(&pPgmCpu->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1903	PGM_REG_PROFILE(&pPgmCpu->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1904	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1905	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1906	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1907	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1908	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1909	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1910	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1911	PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1912	PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1913	PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1914	PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1915	PGM_REG_PROFILE(&pPgmCpu->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1916	PGM_REG_PROFILE(&pPgmCpu->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1917	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1918	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1919	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1920	PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1921	PGM_REG_PROFILE(&pPgmCpu->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1922	#endif /* VBOX_WITH_STATISTICS */
1923
1924	#undef PGM_REG_PROFILE
1925	#undef PGM_REG_COUNTER
1926
1927	}
1928	}
1929
1930
1931	/**
1932	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1933	*
1934	* The dynamic mapping area will also be allocated and initialized at this
1935	* time. We could allocate it during PGMR3Init of course, but the mapping
1936	* wouldn't be allocated at that time preventing us from setting up the
1937	* page table entries with the dummy page.
1938	*
1939	* @returns VBox status code.
1940	* @param pVM VM handle.
1941	*/
1942	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1943	{
1944	RTGCPTR GCPtr;
1945	int rc;
1946
1947	/*
1948	* Reserve space for the dynamic mappings.
1949	*/
1950	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1951	if (RT_SUCCESS(rc))
1952	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1953
1954	if ( RT_SUCCESS(rc)
1955	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1956	{
1957	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1958	if (RT_SUCCESS(rc))
1959	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1960	}
1961	if (RT_SUCCESS(rc))
1962	{
1963	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1964	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1965	}
1966	return rc;
1967	}
1968
1969
1970	/**
1971	* Ring-3 init finalizing.
1972	*
1973	* @returns VBox status code.
1974	* @param pVM The VM handle.
1975	*/
1976	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1977	{
1978	int rc;
1979
1980	/*
1981	* Reserve space for the dynamic mappings.
1982	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1983	*/
1984	/* get the pointer to the page table entries. */
1985	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1986	AssertRelease(pMapping);
1987	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1988	const unsigned iPT = off >> X86_PD_SHIFT;
1989	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1990	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1991	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1992
1993	/* init cache */
1994	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1995	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1996	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1997
1998	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1999	{
2000	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
2001	AssertRCReturn(rc, rc);
2002	}
2003
2004	/*
2005	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2006	* Intel only goes up to 36 bits, so we stick to 36 as well.
2007	*/
2008	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
2009	uint32_t u32Dummy, u32Features;
2010	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2011
2012	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2013	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
2014	else
2015	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2016
2017	/*
2018	* Allocate memory if we're supposed to do that.
2019	*/
2020	if (pVM->pgm.s.fRamPreAlloc)
2021	rc = pgmR3PhysRamPreAllocate(pVM);
2022
2023	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2024	return rc;
2025	}
2026
2027
2028	/**
2029	* Applies relocations to data and code managed by this component.
2030	*
2031	* This function will be called at init and whenever the VMM need to relocate it
2032	* self inside the GC.
2033	*
2034	* @param pVM The VM.
2035	* @param offDelta Relocation delta relative to old location.
2036	*/
2037	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2038	{
2039	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2040
2041	/*
2042	* Paging stuff.
2043	*/
2044	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2045
2046	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2047
2048	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2049	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2050	{
2051	PVMCPU pVCpu = &pVM->aCpus[i];
2052
2053	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2054
2055	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2056	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2057	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2058	}
2059
2060	/*
2061	* Trees.
2062	*/
2063	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2064
2065	/*
2066	* Ram ranges.
2067	*/
2068	if (pVM->pgm.s.pRamRangesR3)
2069	{
2070	/* Update the pSelfRC pointers and relink them. */
2071	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2072	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2073	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2074	pgmR3PhysRelinkRamRanges(pVM);
2075	}
2076
2077	/*
2078	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2079	* be mapped and thus not included in the above exercise.
2080	*/
2081	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2082	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2083	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2084
2085	/*
2086	* Update the two page directories with all page table mappings.
2087	* (One or more of them have changed, that's why we're here.)
2088	*/
2089	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2090	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2091	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2092
2093	/* Relocate GC addresses of Page Tables. */
2094	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2095	{
2096	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2097	{
2098	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2099	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2100	}
2101	}
2102
2103	/*
2104	* Dynamic page mapping area.
2105	*/
2106	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2107	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2108	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2109
2110	/*
2111	* The Zero page.
2112	*/
2113	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2114	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2115	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2116	#else
2117	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2118	#endif
2119
2120	/*
2121	* Physical and virtual handlers.
2122	*/
2123	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2124	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2125	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2126
2127	/*
2128	* The page pool.
2129	*/
2130	pgmR3PoolRelocate(pVM);
2131	}
2132
2133
2134	/**
2135	* Callback function for relocating a physical access handler.
2136	*
2137	* @returns 0 (continue enum)
2138	* @param pNode Pointer to a PGMPHYSHANDLER node.
2139	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2140	* not certain the delta will fit in a void pointer for all possible configs.
2141	*/
2142	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2143	{
2144	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2145	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2146	if (pHandler->pfnHandlerRC)
2147	pHandler->pfnHandlerRC += offDelta;
2148	if (pHandler->pvUserRC >= 0x10000)
2149	pHandler->pvUserRC += offDelta;
2150	return 0;
2151	}
2152
2153
2154	/**
2155	* Callback function for relocating a virtual access handler.
2156	*
2157	* @returns 0 (continue enum)
2158	* @param pNode Pointer to a PGMVIRTHANDLER node.
2159	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2160	* not certain the delta will fit in a void pointer for all possible configs.
2161	*/
2162	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2163	{
2164	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2165	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2166	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2167	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2168	Assert(pHandler->pfnHandlerRC);
2169	pHandler->pfnHandlerRC += offDelta;
2170	return 0;
2171	}
2172
2173
2174	/**
2175	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2176	*
2177	* @returns 0 (continue enum)
2178	* @param pNode Pointer to a PGMVIRTHANDLER node.
2179	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2180	* not certain the delta will fit in a void pointer for all possible configs.
2181	*/
2182	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2183	{
2184	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2185	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2186	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2187	Assert(pHandler->pfnHandlerRC);
2188	pHandler->pfnHandlerRC += offDelta;
2189	return 0;
2190	}
2191
2192
2193	/**
2194	* Resets a virtual CPU when unplugged.
2195	*
2196	* @param pVM The VM handle.
2197	* @param pVCpu The virtual CPU handle.
2198	*/
2199	VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2200	{
2201	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2202	AssertRC(rc);
2203
2204	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2205	AssertRC(rc);
2206
2207	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2208
2209	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2210
2211	/*
2212	* Re-init other members.
2213	*/
2214	pVCpu->pgm.s.fA20Enabled = true;
2215
2216	/*
2217	* Clear the FFs PGM owns.
2218	*/
2219	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2220	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2221	}
2222
2223
2224	/**
2225	* The VM is being reset.
2226	*
2227	* For the PGM component this means that any PD write monitors
2228	* needs to be removed.
2229	*
2230	* @param pVM VM handle.
2231	*/
2232	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2233	{
2234	int rc;
2235
2236	LogFlow(("PGMR3Reset:\n"));
2237	VM_ASSERT_EMT(pVM);
2238
2239	pgmLock(pVM);
2240
2241	/*
2242	* Unfix any fixed mappings and disable CR3 monitoring.
2243	*/
2244	pVM->pgm.s.fMappingsFixed = false;
2245	pVM->pgm.s.fMappingsFixedRestored = false;
2246	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2247	pVM->pgm.s.cbMappingFixed = 0;
2248
2249	/*
2250	* Exit the guest paging mode before the pgm pool gets reset.
2251	* Important to clean up the amd64 case.
2252	*/
2253	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2254	{
2255	PVMCPU pVCpu = &pVM->aCpus[i];
2256	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2257	AssertRC(rc);
2258	}
2259
2260	#ifdef DEBUG
2261	DBGFR3InfoLog(pVM, "mappings", NULL);
2262	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2263	#endif
2264
2265	/*
2266	* Switch mode back to real mode. (before resetting the pgm pool!)
2267	*/
2268	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2269	{
2270	PVMCPU pVCpu = &pVM->aCpus[i];
2271
2272	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2273	AssertRC(rc);
2274
2275	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2276	}
2277
2278	/*
2279	* Reset the shadow page pool.
2280	*/
2281	pgmR3PoolReset(pVM);
2282
2283	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2284	{
2285	PVMCPU pVCpu = &pVM->aCpus[i];
2286
2287	/*
2288	* Re-init other members.
2289	*/
2290	pVCpu->pgm.s.fA20Enabled = true;
2291
2292	/*
2293	* Clear the FFs PGM owns.
2294	*/
2295	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2296	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2297	}
2298
2299	/*
2300	* Reset (zero) RAM pages.
2301	*/
2302	rc = pgmR3PhysRamReset(pVM);
2303	if (RT_SUCCESS(rc))
2304	{
2305	/*
2306	* Reset (zero) shadow ROM pages.
2307	*/
2308	rc = pgmR3PhysRomReset(pVM);
2309	}
2310
2311	pgmUnlock(pVM);
2312	AssertReleaseRC(rc);
2313	}
2314
2315
2316	#ifdef VBOX_STRICT
2317	/**
2318	* VM state change callback for clearing fNoMorePhysWrites after
2319	* a snapshot has been created.
2320	*/
2321	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2322	{
2323	if ( enmState == VMSTATE_RUNNING
2324	\|\| enmState == VMSTATE_RESUMING)
2325	pVM->pgm.s.fNoMorePhysWrites = false;
2326	}
2327	#endif
2328
2329
2330	/**
2331	* Terminates the PGM.
2332	*
2333	* @returns VBox status code.
2334	* @param pVM Pointer to VM structure.
2335	*/
2336	VMMR3DECL(int) PGMR3Term(PVM pVM)
2337	{
2338	/* Must free shared pages here. */
2339	pgmLock(pVM);
2340	pgmR3PhysRamTerm(pVM);
2341	pgmUnlock(pVM);
2342
2343	PGMDeregisterStringFormatTypes();
2344	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2345	}
2346
2347
2348	/**
2349	* Terminates the per-VCPU PGM.
2350	*
2351	* Termination means cleaning up and freeing all resources,
2352	* the VM it self is at this point powered off or suspended.
2353	*
2354	* @returns VBox status code.
2355	* @param pVM The VM to operate on.
2356	*/
2357	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2358	{
2359	return 0;
2360	}
2361
2362
2363	/**
2364	* Show paging mode.
2365	*
2366	* @param pVM VM Handle.
2367	* @param pHlp The info helpers.
2368	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2369	*/
2370	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2371	{
2372	/* digest argument. */
2373	bool fGuest, fShadow, fHost;
2374	if (pszArgs)
2375	pszArgs = RTStrStripL(pszArgs);
2376	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2377	fShadow = fHost = fGuest = true;
2378	else
2379	{
2380	fShadow = fHost = fGuest = false;
2381	if (strstr(pszArgs, "guest"))
2382	fGuest = true;
2383	if (strstr(pszArgs, "shadow"))
2384	fShadow = true;
2385	if (strstr(pszArgs, "host"))
2386	fHost = true;
2387	}
2388
2389	/** @todo SMP support! */
2390	/* print info. */
2391	if (fGuest)
2392	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2393	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2394	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
2395	if (fShadow)
2396	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2397	if (fHost)
2398	{
2399	const char *psz;
2400	switch (pVM->pgm.s.enmHostMode)
2401	{
2402	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2403	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2404	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2405	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2406	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2407	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2408	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2409	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2410	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2411	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2412	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2413	default: psz = "unknown"; break;
2414	}
2415	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2416	}
2417	}
2418
2419
2420	/**
2421	* Dump registered MMIO ranges to the log.
2422	*
2423	* @param pVM VM Handle.
2424	* @param pHlp The info helpers.
2425	* @param pszArgs Arguments, ignored.
2426	*/
2427	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2428	{
2429	NOREF(pszArgs);
2430	pHlp->pfnPrintf(pHlp,
2431	"RAM ranges (pVM=%p)\n"
2432	"%.s %.s\n",
2433	pVM,
2434	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2435	sizeof(RTHCPTR) * 2, "pvHC ");
2436
2437	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2438	pHlp->pfnPrintf(pHlp,
2439	"%RGp-%RGp %RHv %s\n",
2440	pCur->GCPhys,
2441	pCur->GCPhysLast,
2442	pCur->pvR3,
2443	pCur->pszDesc);
2444	}
2445
2446	/**
2447	* Dump the page directory to the log.
2448	*
2449	* @param pVM VM Handle.
2450	* @param pHlp The info helpers.
2451	* @param pszArgs Arguments, ignored.
2452	*/
2453	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2454	{
2455	/** @todo SMP support!! */
2456	PVMCPU pVCpu = &pVM->aCpus[0];
2457
2458	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2459	/* Big pages supported? */
2460	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2461
2462	/* Global pages supported? */
2463	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2464
2465	NOREF(pszArgs);
2466
2467	/*
2468	* Get page directory addresses.
2469	*/
2470	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
2471	Assert(pPDSrc);
2472	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2473
2474	/*
2475	* Iterate the page directory.
2476	*/
2477	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2478	{
2479	X86PDE PdeSrc = pPDSrc->a[iPD];
2480	if (PdeSrc.n.u1Present)
2481	{
2482	if (PdeSrc.b.u1Size && fPSE)
2483	pHlp->pfnPrintf(pHlp,
2484	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2485	iPD,
2486	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2487	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2488	else
2489	pHlp->pfnPrintf(pHlp,
2490	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2491	iPD,
2492	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2493	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2494	}
2495	}
2496	}
2497
2498
2499	/**
2500	* Service a VMMCALLRING3_PGM_LOCK call.
2501	*
2502	* @returns VBox status code.
2503	* @param pVM The VM handle.
2504	*/
2505	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2506	{
2507	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2508	AssertRC(rc);
2509	return rc;
2510	}
2511
2512
2513	/**
2514	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2515	*
2516	* @returns PGM_TYPE_*.
2517	* @param pgmMode The mode value to convert.
2518	*/
2519	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2520	{
2521	switch (pgmMode)
2522	{
2523	case PGMMODE_REAL: return PGM_TYPE_REAL;
2524	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2525	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2526	case PGMMODE_PAE:
2527	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2528	case PGMMODE_AMD64:
2529	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2530	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2531	case PGMMODE_EPT: return PGM_TYPE_EPT;
2532	default:
2533	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2534	}
2535	}
2536
2537
2538	/**
2539	* Gets the index into the paging mode data array of a SHW+GST mode.
2540	*
2541	* @returns PGM::paPagingData index.
2542	* @param uShwType The shadow paging mode type.
2543	* @param uGstType The guest paging mode type.
2544	*/
2545	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2546	{
2547	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2548	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2549	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2550	+ (uGstType - PGM_TYPE_REAL);
2551	}
2552
2553
2554	/**
2555	* Gets the index into the paging mode data array of a SHW+GST mode.
2556	*
2557	* @returns PGM::paPagingData index.
2558	* @param enmShw The shadow paging mode.
2559	* @param enmGst The guest paging mode.
2560	*/
2561	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2562	{
2563	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2564	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2565	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2566	}
2567
2568
2569	/**
2570	* Calculates the max data index.
2571	* @returns The number of entries in the paging data array.
2572	*/
2573	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2574	{
2575	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2576	}
2577
2578
2579	/**
2580	* Initializes the paging mode data kept in PGM::paModeData.
2581	*
2582	* @param pVM The VM handle.
2583	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2584	* This is used early in the init process to avoid trouble with PDM
2585	* not being initialized yet.
2586	*/
2587	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2588	{
2589	PPGMMODEDATA pModeData;
2590	int rc;
2591
2592	/*
2593	* Allocate the array on the first call.
2594	*/
2595	if (!pVM->pgm.s.paModeData)
2596	{
2597	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2598	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2599	}
2600
2601	/*
2602	* Initialize the array entries.
2603	*/
2604	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2605	pModeData->uShwType = PGM_TYPE_32BIT;
2606	pModeData->uGstType = PGM_TYPE_REAL;
2607	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2608	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2609	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2610
2611	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2612	pModeData->uShwType = PGM_TYPE_32BIT;
2613	pModeData->uGstType = PGM_TYPE_PROT;
2614	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2615	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2616	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2617
2618	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2619	pModeData->uShwType = PGM_TYPE_32BIT;
2620	pModeData->uGstType = PGM_TYPE_32BIT;
2621	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2622	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2623	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2624
2625	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2626	pModeData->uShwType = PGM_TYPE_PAE;
2627	pModeData->uGstType = PGM_TYPE_REAL;
2628	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2629	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2630	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2631
2632	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2633	pModeData->uShwType = PGM_TYPE_PAE;
2634	pModeData->uGstType = PGM_TYPE_PROT;
2635	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2636	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2637	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2638
2639	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2640	pModeData->uShwType = PGM_TYPE_PAE;
2641	pModeData->uGstType = PGM_TYPE_32BIT;
2642	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2643	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2644	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2645
2646	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2647	pModeData->uShwType = PGM_TYPE_PAE;
2648	pModeData->uGstType = PGM_TYPE_PAE;
2649	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2650	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2651	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2652
2653	#ifdef VBOX_WITH_64_BITS_GUESTS
2654	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2655	pModeData->uShwType = PGM_TYPE_AMD64;
2656	pModeData->uGstType = PGM_TYPE_AMD64;
2657	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2658	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2659	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2660	#endif
2661
2662	/* The nested paging mode. */
2663	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2664	pModeData->uShwType = PGM_TYPE_NESTED;
2665	pModeData->uGstType = PGM_TYPE_REAL;
2666	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2667	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2668
2669	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2670	pModeData->uShwType = PGM_TYPE_NESTED;
2671	pModeData->uGstType = PGM_TYPE_PROT;
2672	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2673	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2674
2675	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2676	pModeData->uShwType = PGM_TYPE_NESTED;
2677	pModeData->uGstType = PGM_TYPE_32BIT;
2678	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2679	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2680
2681	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2682	pModeData->uShwType = PGM_TYPE_NESTED;
2683	pModeData->uGstType = PGM_TYPE_PAE;
2684	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2685	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2686
2687	#ifdef VBOX_WITH_64_BITS_GUESTS
2688	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2689	pModeData->uShwType = PGM_TYPE_NESTED;
2690	pModeData->uGstType = PGM_TYPE_AMD64;
2691	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2692	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2693	#endif
2694
2695	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2696	switch (pVM->pgm.s.enmHostMode)
2697	{
2698	#if HC_ARCH_BITS == 32
2699	case SUPPAGINGMODE_32_BIT:
2700	case SUPPAGINGMODE_32_BIT_GLOBAL:
2701	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2702	{
2703	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2704	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2705	}
2706	# ifdef VBOX_WITH_64_BITS_GUESTS
2707	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2708	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2709	# endif
2710	break;
2711
2712	case SUPPAGINGMODE_PAE:
2713	case SUPPAGINGMODE_PAE_NX:
2714	case SUPPAGINGMODE_PAE_GLOBAL:
2715	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2716	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2717	{
2718	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2719	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2720	}
2721	# ifdef VBOX_WITH_64_BITS_GUESTS
2722	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2723	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2724	# endif
2725	break;
2726	#endif /* HC_ARCH_BITS == 32 */
2727
2728	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2729	case SUPPAGINGMODE_AMD64:
2730	case SUPPAGINGMODE_AMD64_GLOBAL:
2731	case SUPPAGINGMODE_AMD64_NX:
2732	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2733	# ifdef VBOX_WITH_64_BITS_GUESTS
2734	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2735	# else
2736	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2737	# endif
2738	{
2739	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2740	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2741	}
2742	break;
2743	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2744
2745	default:
2746	AssertFailed();
2747	break;
2748	}
2749
2750	/* Extended paging (EPT) / Intel VT-x */
2751	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2752	pModeData->uShwType = PGM_TYPE_EPT;
2753	pModeData->uGstType = PGM_TYPE_REAL;
2754	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2755	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2756	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2757
2758	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2759	pModeData->uShwType = PGM_TYPE_EPT;
2760	pModeData->uGstType = PGM_TYPE_PROT;
2761	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2762	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2763	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2764
2765	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2766	pModeData->uShwType = PGM_TYPE_EPT;
2767	pModeData->uGstType = PGM_TYPE_32BIT;
2768	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2769	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2770	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2771
2772	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2773	pModeData->uShwType = PGM_TYPE_EPT;
2774	pModeData->uGstType = PGM_TYPE_PAE;
2775	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2776	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2777	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2778
2779	#ifdef VBOX_WITH_64_BITS_GUESTS
2780	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2781	pModeData->uShwType = PGM_TYPE_EPT;
2782	pModeData->uGstType = PGM_TYPE_AMD64;
2783	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2784	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2785	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2786	#endif
2787	return VINF_SUCCESS;
2788	}
2789
2790
2791	/**
2792	* Switch to different (or relocated in the relocate case) mode data.
2793	*
2794	* @param pVM The VM handle.
2795	* @param pVCpu The VMCPU to operate on.
2796	* @param enmShw The the shadow paging mode.
2797	* @param enmGst The the guest paging mode.
2798	*/
2799	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
2800	{
2801	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2802
2803	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2804	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2805
2806	/* shadow */
2807	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2808	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2809	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2810	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
2811	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2812
2813	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2814	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2815
2816	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2817	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2818
2819
2820	/* guest */
2821	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2822	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2823	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2824	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
2825	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2826	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2827	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2828	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2829	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2830	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2831	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2832	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2833
2834	/* both */
2835	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2836	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2837	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2838	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
2839	pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2840	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2841	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2842	#ifdef VBOX_STRICT
2843	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2844	#endif
2845	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
2846	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
2847
2848	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2849	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2850	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2851	pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2852	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2853	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2854	#ifdef VBOX_STRICT
2855	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2856	#endif
2857	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
2858	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
2859
2860	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2861	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2862	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2863	pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2864	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2865	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2866	#ifdef VBOX_STRICT
2867	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2868	#endif
2869	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
2870	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
2871	}
2872
2873
2874	/**
2875	* Calculates the shadow paging mode.
2876	*
2877	* @returns The shadow paging mode.
2878	* @param pVM VM handle.
2879	* @param enmGuestMode The guest mode.
2880	* @param enmHostMode The host mode.
2881	* @param enmShadowMode The current shadow mode.
2882	* @param penmSwitcher Where to store the switcher to use.
2883	* VMMSWITCHER_INVALID means no change.
2884	*/
2885	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2886	{
2887	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2888	switch (enmGuestMode)
2889	{
2890	/*
2891	* When switching to real or protected mode we don't change
2892	* anything since it's likely that we'll switch back pretty soon.
2893	*
2894	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2895	* and is supposed to determine which shadow paging and switcher to
2896	* use during init.
2897	*/
2898	case PGMMODE_REAL:
2899	case PGMMODE_PROTECTED:
2900	if ( enmShadowMode != PGMMODE_INVALID
2901	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2902	break; /* (no change) */
2903
2904	switch (enmHostMode)
2905	{
2906	case SUPPAGINGMODE_32_BIT:
2907	case SUPPAGINGMODE_32_BIT_GLOBAL:
2908	enmShadowMode = PGMMODE_32_BIT;
2909	enmSwitcher = VMMSWITCHER_32_TO_32;
2910	break;
2911
2912	case SUPPAGINGMODE_PAE:
2913	case SUPPAGINGMODE_PAE_NX:
2914	case SUPPAGINGMODE_PAE_GLOBAL:
2915	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2916	enmShadowMode = PGMMODE_PAE;
2917	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2918	#ifdef DEBUG_bird
2919	if (RTEnvExist("VBOX_32BIT"))
2920	{
2921	enmShadowMode = PGMMODE_32_BIT;
2922	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2923	}
2924	#endif
2925	break;
2926
2927	case SUPPAGINGMODE_AMD64:
2928	case SUPPAGINGMODE_AMD64_GLOBAL:
2929	case SUPPAGINGMODE_AMD64_NX:
2930	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2931	enmShadowMode = PGMMODE_PAE;
2932	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2933	#ifdef DEBUG_bird
2934	if (RTEnvExist("VBOX_32BIT"))
2935	{
2936	enmShadowMode = PGMMODE_32_BIT;
2937	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2938	}
2939	#endif
2940	break;
2941
2942	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2943	}
2944	break;
2945
2946	case PGMMODE_32_BIT:
2947	switch (enmHostMode)
2948	{
2949	case SUPPAGINGMODE_32_BIT:
2950	case SUPPAGINGMODE_32_BIT_GLOBAL:
2951	enmShadowMode = PGMMODE_32_BIT;
2952	enmSwitcher = VMMSWITCHER_32_TO_32;
2953	break;
2954
2955	case SUPPAGINGMODE_PAE:
2956	case SUPPAGINGMODE_PAE_NX:
2957	case SUPPAGINGMODE_PAE_GLOBAL:
2958	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2959	enmShadowMode = PGMMODE_PAE;
2960	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2961	#ifdef DEBUG_bird
2962	if (RTEnvExist("VBOX_32BIT"))
2963	{
2964	enmShadowMode = PGMMODE_32_BIT;
2965	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2966	}
2967	#endif
2968	break;
2969
2970	case SUPPAGINGMODE_AMD64:
2971	case SUPPAGINGMODE_AMD64_GLOBAL:
2972	case SUPPAGINGMODE_AMD64_NX:
2973	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2974	enmShadowMode = PGMMODE_PAE;
2975	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2976	#ifdef DEBUG_bird
2977	if (RTEnvExist("VBOX_32BIT"))
2978	{
2979	enmShadowMode = PGMMODE_32_BIT;
2980	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2981	}
2982	#endif
2983	break;
2984
2985	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2986	}
2987	break;
2988
2989	case PGMMODE_PAE:
2990	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2991	switch (enmHostMode)
2992	{
2993	case SUPPAGINGMODE_32_BIT:
2994	case SUPPAGINGMODE_32_BIT_GLOBAL:
2995	enmShadowMode = PGMMODE_PAE;
2996	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2997	break;
2998
2999	case SUPPAGINGMODE_PAE:
3000	case SUPPAGINGMODE_PAE_NX:
3001	case SUPPAGINGMODE_PAE_GLOBAL:
3002	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3003	enmShadowMode = PGMMODE_PAE;
3004	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3005	break;
3006
3007	case SUPPAGINGMODE_AMD64:
3008	case SUPPAGINGMODE_AMD64_GLOBAL:
3009	case SUPPAGINGMODE_AMD64_NX:
3010	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3011	enmShadowMode = PGMMODE_PAE;
3012	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3013	break;
3014
3015	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3016	}
3017	break;
3018
3019	case PGMMODE_AMD64:
3020	case PGMMODE_AMD64_NX:
3021	switch (enmHostMode)
3022	{
3023	case SUPPAGINGMODE_32_BIT:
3024	case SUPPAGINGMODE_32_BIT_GLOBAL:
3025	enmShadowMode = PGMMODE_AMD64;
3026	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3027	break;
3028
3029	case SUPPAGINGMODE_PAE:
3030	case SUPPAGINGMODE_PAE_NX:
3031	case SUPPAGINGMODE_PAE_GLOBAL:
3032	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3033	enmShadowMode = PGMMODE_AMD64;
3034	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3035	break;
3036
3037	case SUPPAGINGMODE_AMD64:
3038	case SUPPAGINGMODE_AMD64_GLOBAL:
3039	case SUPPAGINGMODE_AMD64_NX:
3040	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3041	enmShadowMode = PGMMODE_AMD64;
3042	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3043	break;
3044
3045	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3046	}
3047	break;
3048
3049
3050	default:
3051	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3052	*penmSwitcher = VMMSWITCHER_INVALID;
3053	return PGMMODE_INVALID;
3054	}
3055	/* Override the shadow mode is nested paging is active. */
3056	if (HWACCMIsNestedPagingActive(pVM))
3057	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3058
3059	*penmSwitcher = enmSwitcher;
3060	return enmShadowMode;
3061	}
3062
3063
3064	/**
3065	* Performs the actual mode change.
3066	* This is called by PGMChangeMode and pgmR3InitPaging().
3067	*
3068	* @returns VBox status code. May suspend or power off the VM on error, but this
3069	* will trigger using FFs and not status codes.
3070	*
3071	* @param pVM VM handle.
3072	* @param pVCpu The VMCPU to operate on.
3073	* @param enmGuestMode The new guest mode. This is assumed to be different from
3074	* the current mode.
3075	*/
3076	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3077	{
3078	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3079	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3080
3081	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3082	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3083
3084	/*
3085	* Calc the shadow mode and switcher.
3086	*/
3087	VMMSWITCHER enmSwitcher;
3088	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3089
3090	#ifdef VBOX_WITH_RAW_MODE
3091	if (enmSwitcher != VMMSWITCHER_INVALID)
3092	{
3093	/*
3094	* Select new switcher.
3095	*/
3096	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3097	if (RT_FAILURE(rc))
3098	{
3099	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3100	return rc;
3101	}
3102	}
3103	#endif
3104
3105	/*
3106	* Exit old mode(s).
3107	*/
3108	#if HC_ARCH_BITS == 32
3109	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3110	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3111	&& enmShadowMode == PGMMODE_NESTED);
3112	#else
3113	const bool fForceShwEnterExit = false;
3114	#endif
3115	/* shadow */
3116	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3117	\|\| fForceShwEnterExit)
3118	{
3119	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3120	if (PGM_SHW_PFN(Exit, pVCpu))
3121	{
3122	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3123	if (RT_FAILURE(rc))
3124	{
3125	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3126	return rc;
3127	}
3128	}
3129
3130	}
3131	else
3132	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3133
3134	/* guest */
3135	if (PGM_GST_PFN(Exit, pVCpu))
3136	{
3137	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3138	if (RT_FAILURE(rc))
3139	{
3140	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3141	return rc;
3142	}
3143	}
3144
3145	/*
3146	* Load new paging mode data.
3147	*/
3148	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3149
3150	/*
3151	* Enter new shadow mode (if changed).
3152	*/
3153	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3154	\|\| fForceShwEnterExit)
3155	{
3156	int rc;
3157	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3158	switch (enmShadowMode)
3159	{
3160	case PGMMODE_32_BIT:
3161	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3162	break;
3163	case PGMMODE_PAE:
3164	case PGMMODE_PAE_NX:
3165	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3166	break;
3167	case PGMMODE_AMD64:
3168	case PGMMODE_AMD64_NX:
3169	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3170	break;
3171	case PGMMODE_NESTED:
3172	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3173	break;
3174	case PGMMODE_EPT:
3175	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3176	break;
3177	case PGMMODE_REAL:
3178	case PGMMODE_PROTECTED:
3179	default:
3180	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3181	return VERR_INTERNAL_ERROR;
3182	}
3183	if (RT_FAILURE(rc))
3184	{
3185	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3186	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3187	return rc;
3188	}
3189	}
3190
3191	/*
3192	* Always flag the necessary updates
3193	*/
3194	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3195
3196	/*
3197	* Enter the new guest and shadow+guest modes.
3198	*/
3199	int rc = -1;
3200	int rc2 = -1;
3201	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3202	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3203	switch (enmGuestMode)
3204	{
3205	case PGMMODE_REAL:
3206	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3207	switch (pVCpu->pgm.s.enmShadowMode)
3208	{
3209	case PGMMODE_32_BIT:
3210	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3211	break;
3212	case PGMMODE_PAE:
3213	case PGMMODE_PAE_NX:
3214	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3215	break;
3216	case PGMMODE_NESTED:
3217	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3218	break;
3219	case PGMMODE_EPT:
3220	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3221	break;
3222	case PGMMODE_AMD64:
3223	case PGMMODE_AMD64_NX:
3224	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3225	default: AssertFailed(); break;
3226	}
3227	break;
3228
3229	case PGMMODE_PROTECTED:
3230	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3231	switch (pVCpu->pgm.s.enmShadowMode)
3232	{
3233	case PGMMODE_32_BIT:
3234	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3235	break;
3236	case PGMMODE_PAE:
3237	case PGMMODE_PAE_NX:
3238	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3239	break;
3240	case PGMMODE_NESTED:
3241	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3242	break;
3243	case PGMMODE_EPT:
3244	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3245	break;
3246	case PGMMODE_AMD64:
3247	case PGMMODE_AMD64_NX:
3248	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3249	default: AssertFailed(); break;
3250	}
3251	break;
3252
3253	case PGMMODE_32_BIT:
3254	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3255	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3256	switch (pVCpu->pgm.s.enmShadowMode)
3257	{
3258	case PGMMODE_32_BIT:
3259	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3260	break;
3261	case PGMMODE_PAE:
3262	case PGMMODE_PAE_NX:
3263	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3264	break;
3265	case PGMMODE_NESTED:
3266	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3267	break;
3268	case PGMMODE_EPT:
3269	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3270	break;
3271	case PGMMODE_AMD64:
3272	case PGMMODE_AMD64_NX:
3273	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3274	default: AssertFailed(); break;
3275	}
3276	break;
3277
3278	case PGMMODE_PAE_NX:
3279	case PGMMODE_PAE:
3280	{
3281	uint32_t u32Dummy, u32Features;
3282
3283	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3284	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3285	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3286	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3287
3288	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3289	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3290	switch (pVCpu->pgm.s.enmShadowMode)
3291	{
3292	case PGMMODE_PAE:
3293	case PGMMODE_PAE_NX:
3294	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3295	break;
3296	case PGMMODE_NESTED:
3297	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3298	break;
3299	case PGMMODE_EPT:
3300	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3301	break;
3302	case PGMMODE_32_BIT:
3303	case PGMMODE_AMD64:
3304	case PGMMODE_AMD64_NX:
3305	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3306	default: AssertFailed(); break;
3307	}
3308	break;
3309	}
3310
3311	#ifdef VBOX_WITH_64_BITS_GUESTS
3312	case PGMMODE_AMD64_NX:
3313	case PGMMODE_AMD64:
3314	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3315	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3316	switch (pVCpu->pgm.s.enmShadowMode)
3317	{
3318	case PGMMODE_AMD64:
3319	case PGMMODE_AMD64_NX:
3320	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3321	break;
3322	case PGMMODE_NESTED:
3323	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3324	break;
3325	case PGMMODE_EPT:
3326	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3327	break;
3328	case PGMMODE_32_BIT:
3329	case PGMMODE_PAE:
3330	case PGMMODE_PAE_NX:
3331	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3332	default: AssertFailed(); break;
3333	}
3334	break;
3335	#endif
3336
3337	default:
3338	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3339	rc = VERR_NOT_IMPLEMENTED;
3340	break;
3341	}
3342
3343	/* status codes. */
3344	AssertRC(rc);
3345	AssertRC(rc2);
3346	if (RT_SUCCESS(rc))
3347	{
3348	rc = rc2;
3349	if (RT_SUCCESS(rc)) /* no informational status codes. */
3350	rc = VINF_SUCCESS;
3351	}
3352
3353	/* Notify HWACCM as well. */
3354	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3355	return rc;
3356	}
3357
3358
3359	/**
3360	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3361	*
3362	* @returns VBox status code, fully asserted.
3363	* @param pVM The VM handle.
3364	* @param pVCpu The VMCPU to operate on.
3365	*/
3366	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
3367	{
3368	/* Unmap the old CR3 value before flushing everything. */
3369	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3370	AssertRC(rc);
3371
3372	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3373	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3374	AssertRC(rc);
3375	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3376	return rc;
3377	}
3378
3379
3380	/**
3381	* Called by pgmPoolFlushAllInt after flushing the pool.
3382	*
3383	* @returns VBox status code, fully asserted.
3384	* @param pVM The VM handle.
3385	* @param pVCpu The VMCPU to operate on.
3386	*/
3387	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3388	{
3389	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3390	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3391	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3392	AssertRCReturn(rc, rc);
3393	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3394
3395	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3396	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3397	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3398	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3399	return rc;
3400	}
3401
3402
3403	/**
3404	* Dumps a PAE shadow page table.
3405	*
3406	* @returns VBox status code (VINF_SUCCESS).
3407	* @param pVM The VM handle.
3408	* @param pPT Pointer to the page table.
3409	* @param u64Address The virtual address of the page table starts.
3410	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3411	* @param cMaxDepth The maxium depth.
3412	* @param pHlp Pointer to the output functions.
3413	*/
3414	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3415	{
3416	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3417	{
3418	X86PTEPAE Pte = pPT->a[i];
3419	if (Pte.n.u1Present)
3420	{
3421	pHlp->pfnPrintf(pHlp,
3422	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3423	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3424	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3425	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3426	Pte.n.u1Write ? 'W' : 'R',
3427	Pte.n.u1User ? 'U' : 'S',
3428	Pte.n.u1Accessed ? 'A' : '-',
3429	Pte.n.u1Dirty ? 'D' : '-',
3430	Pte.n.u1Global ? 'G' : '-',
3431	Pte.n.u1WriteThru ? "WT" : "--",
3432	Pte.n.u1CacheDisable? "CD" : "--",
3433	Pte.n.u1PAT ? "AT" : "--",
3434	Pte.n.u1NoExecute ? "NX" : "--",
3435	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3436	Pte.u & RT_BIT(10) ? '1' : '0',
3437	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3438	Pte.u & X86_PTE_PAE_PG_MASK);
3439	}
3440	}
3441	return VINF_SUCCESS;
3442	}
3443
3444
3445	/**
3446	* Dumps a PAE shadow page directory table.
3447	*
3448	* @returns VBox status code (VINF_SUCCESS).
3449	* @param pVM The VM handle.
3450	* @param HCPhys The physical address of the page directory table.
3451	* @param u64Address The virtual address of the page table starts.
3452	* @param cr4 The CR4, PSE is currently used.
3453	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3454	* @param cMaxDepth The maxium depth.
3455	* @param pHlp Pointer to the output functions.
3456	*/
3457	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3458	{
3459	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3460	if (!pPD)
3461	{
3462	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3463	fLongMode ? 16 : 8, u64Address, HCPhys);
3464	return VERR_INVALID_PARAMETER;
3465	}
3466	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3467
3468	int rc = VINF_SUCCESS;
3469	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3470	{
3471	X86PDEPAE Pde = pPD->a[i];
3472	if (Pde.n.u1Present)
3473	{
3474	if (fBigPagesSupported && Pde.b.u1Size)
3475	pHlp->pfnPrintf(pHlp,
3476	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3477	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3478	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3479	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3480	Pde.b.u1Write ? 'W' : 'R',
3481	Pde.b.u1User ? 'U' : 'S',
3482	Pde.b.u1Accessed ? 'A' : '-',
3483	Pde.b.u1Dirty ? 'D' : '-',
3484	Pde.b.u1Global ? 'G' : '-',
3485	Pde.b.u1WriteThru ? "WT" : "--",
3486	Pde.b.u1CacheDisable? "CD" : "--",
3487	Pde.b.u1PAT ? "AT" : "--",
3488	Pde.b.u1NoExecute ? "NX" : "--",
3489	Pde.u & RT_BIT_64(9) ? '1' : '0',
3490	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3491	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3492	Pde.u & X86_PDE_PAE_PG_MASK);
3493	else
3494	{
3495	pHlp->pfnPrintf(pHlp,
3496	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3497	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3498	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3499	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3500	Pde.n.u1Write ? 'W' : 'R',
3501	Pde.n.u1User ? 'U' : 'S',
3502	Pde.n.u1Accessed ? 'A' : '-',
3503	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3504	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3505	Pde.n.u1WriteThru ? "WT" : "--",
3506	Pde.n.u1CacheDisable? "CD" : "--",
3507	Pde.n.u1NoExecute ? "NX" : "--",
3508	Pde.u & RT_BIT_64(9) ? '1' : '0',
3509	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3510	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3511	Pde.u & X86_PDE_PAE_PG_MASK);
3512	if (cMaxDepth >= 1)
3513	{
3514	/** @todo what about using the page pool for mapping PTs? */
3515	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3516	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3517	PX86PTPAE pPT = NULL;
3518	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3519	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3520	else
3521	{
3522	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3523	{
3524	uint64_t off = u64AddressPT - pMap->GCPtr;
3525	if (off < pMap->cb)
3526	{
3527	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3528	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3529	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3530	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3531	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3532	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3533	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3534	}
3535	}
3536	}
3537	int rc2 = VERR_INVALID_PARAMETER;
3538	if (pPT)
3539	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3540	else
3541	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3542	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3543	if (rc2 < rc && RT_SUCCESS(rc))
3544	rc = rc2;
3545	}
3546	}
3547	}
3548	}
3549	return rc;
3550	}
3551
3552
3553	/**
3554	* Dumps a PAE shadow page directory pointer table.
3555	*
3556	* @returns VBox status code (VINF_SUCCESS).
3557	* @param pVM The VM handle.
3558	* @param HCPhys The physical address of the page directory pointer table.
3559	* @param u64Address The virtual address of the page table starts.
3560	* @param cr4 The CR4, PSE is currently used.
3561	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3562	* @param cMaxDepth The maxium depth.
3563	* @param pHlp Pointer to the output functions.
3564	*/
3565	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3566	{
3567	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3568	if (!pPDPT)
3569	{
3570	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3571	fLongMode ? 16 : 8, u64Address, HCPhys);
3572	return VERR_INVALID_PARAMETER;
3573	}
3574
3575	int rc = VINF_SUCCESS;
3576	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3577	for (unsigned i = 0; i < c; i++)
3578	{
3579	X86PDPE Pdpe = pPDPT->a[i];
3580	if (Pdpe.n.u1Present)
3581	{
3582	if (fLongMode)
3583	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3584	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3585	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3586	Pdpe.lm.u1Write ? 'W' : 'R',
3587	Pdpe.lm.u1User ? 'U' : 'S',
3588	Pdpe.lm.u1Accessed ? 'A' : '-',
3589	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3590	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3591	Pdpe.lm.u1WriteThru ? "WT" : "--",
3592	Pdpe.lm.u1CacheDisable? "CD" : "--",
3593	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3594	Pdpe.lm.u1NoExecute ? "NX" : "--",
3595	Pdpe.u & RT_BIT(9) ? '1' : '0',
3596	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3597	Pdpe.u & RT_BIT(11) ? '1' : '0',
3598	Pdpe.u & X86_PDPE_PG_MASK);
3599	else
3600	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3601	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3602	i << X86_PDPT_SHIFT,
3603	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3604	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3605	Pdpe.n.u1WriteThru ? "WT" : "--",
3606	Pdpe.n.u1CacheDisable? "CD" : "--",
3607	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3608	Pdpe.u & RT_BIT(9) ? '1' : '0',
3609	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3610	Pdpe.u & RT_BIT(11) ? '1' : '0',
3611	Pdpe.u & X86_PDPE_PG_MASK);
3612	if (cMaxDepth >= 1)
3613	{
3614	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3615	cr4, fLongMode, cMaxDepth - 1, pHlp);
3616	if (rc2 < rc && RT_SUCCESS(rc))
3617	rc = rc2;
3618	}
3619	}
3620	}
3621	return rc;
3622	}
3623
3624
3625	/**
3626	* Dumps a 32-bit shadow page table.
3627	*
3628	* @returns VBox status code (VINF_SUCCESS).
3629	* @param pVM The VM handle.
3630	* @param HCPhys The physical address of the table.
3631	* @param cr4 The CR4, PSE is currently used.
3632	* @param cMaxDepth The maxium depth.
3633	* @param pHlp Pointer to the output functions.
3634	*/
3635	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3636	{
3637	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3638	if (!pPML4)
3639	{
3640	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3641	return VERR_INVALID_PARAMETER;
3642	}
3643
3644	int rc = VINF_SUCCESS;
3645	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3646	{
3647	X86PML4E Pml4e = pPML4->a[i];
3648	if (Pml4e.n.u1Present)
3649	{
3650	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3651	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3652	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3653	u64Address,
3654	Pml4e.n.u1Write ? 'W' : 'R',
3655	Pml4e.n.u1User ? 'U' : 'S',
3656	Pml4e.n.u1Accessed ? 'A' : '-',
3657	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3658	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3659	Pml4e.n.u1WriteThru ? "WT" : "--",
3660	Pml4e.n.u1CacheDisable? "CD" : "--",
3661	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3662	Pml4e.n.u1NoExecute ? "NX" : "--",
3663	Pml4e.u & RT_BIT(9) ? '1' : '0',
3664	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3665	Pml4e.u & RT_BIT(11) ? '1' : '0',
3666	Pml4e.u & X86_PML4E_PG_MASK);
3667
3668	if (cMaxDepth >= 1)
3669	{
3670	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3671	if (rc2 < rc && RT_SUCCESS(rc))
3672	rc = rc2;
3673	}
3674	}
3675	}
3676	return rc;
3677	}
3678
3679
3680	/**
3681	* Dumps a 32-bit shadow page table.
3682	*
3683	* @returns VBox status code (VINF_SUCCESS).
3684	* @param pVM The VM handle.
3685	* @param pPT Pointer to the page table.
3686	* @param u32Address The virtual address this table starts at.
3687	* @param pHlp Pointer to the output functions.
3688	*/
3689	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3690	{
3691	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3692	{
3693	X86PTE Pte = pPT->a[i];
3694	if (Pte.n.u1Present)
3695	{
3696	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3697	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3698	u32Address + (i << X86_PT_SHIFT),
3699	Pte.n.u1Write ? 'W' : 'R',
3700	Pte.n.u1User ? 'U' : 'S',
3701	Pte.n.u1Accessed ? 'A' : '-',
3702	Pte.n.u1Dirty ? 'D' : '-',
3703	Pte.n.u1Global ? 'G' : '-',
3704	Pte.n.u1WriteThru ? "WT" : "--",
3705	Pte.n.u1CacheDisable? "CD" : "--",
3706	Pte.n.u1PAT ? "AT" : "--",
3707	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3708	Pte.u & RT_BIT(10) ? '1' : '0',
3709	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3710	Pte.u & X86_PDE_PG_MASK);
3711	}
3712	}
3713	return VINF_SUCCESS;
3714	}
3715
3716
3717	/**
3718	* Dumps a 32-bit shadow page directory and page tables.
3719	*
3720	* @returns VBox status code (VINF_SUCCESS).
3721	* @param pVM The VM handle.
3722	* @param cr3 The root of the hierarchy.
3723	* @param cr4 The CR4, PSE is currently used.
3724	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3725	* @param pHlp Pointer to the output functions.
3726	*/
3727	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3728	{
3729	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3730	if (!pPD)
3731	{
3732	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3733	return VERR_INVALID_PARAMETER;
3734	}
3735
3736	int rc = VINF_SUCCESS;
3737	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3738	{
3739	X86PDE Pde = pPD->a[i];
3740	if (Pde.n.u1Present)
3741	{
3742	const uint32_t u32Address = i << X86_PD_SHIFT;
3743	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3744	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3745	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3746	u32Address,
3747	Pde.b.u1Write ? 'W' : 'R',
3748	Pde.b.u1User ? 'U' : 'S',
3749	Pde.b.u1Accessed ? 'A' : '-',
3750	Pde.b.u1Dirty ? 'D' : '-',
3751	Pde.b.u1Global ? 'G' : '-',
3752	Pde.b.u1WriteThru ? "WT" : "--",
3753	Pde.b.u1CacheDisable? "CD" : "--",
3754	Pde.b.u1PAT ? "AT" : "--",
3755	Pde.u & RT_BIT_64(9) ? '1' : '0',
3756	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3757	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3758	Pde.u & X86_PDE4M_PG_MASK);
3759	else
3760	{
3761	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3762	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3763	u32Address,
3764	Pde.n.u1Write ? 'W' : 'R',
3765	Pde.n.u1User ? 'U' : 'S',
3766	Pde.n.u1Accessed ? 'A' : '-',
3767	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3768	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3769	Pde.n.u1WriteThru ? "WT" : "--",
3770	Pde.n.u1CacheDisable? "CD" : "--",
3771	Pde.u & RT_BIT_64(9) ? '1' : '0',
3772	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3773	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3774	Pde.u & X86_PDE_PG_MASK);
3775	if (cMaxDepth >= 1)
3776	{
3777	/** @todo what about using the page pool for mapping PTs? */
3778	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3779	PX86PT pPT = NULL;
3780	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3781	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3782	else
3783	{
3784	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3785	if (u32Address - pMap->GCPtr < pMap->cb)
3786	{
3787	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3788	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3789	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3790	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3791	pPT = pMap->aPTs[iPDE].pPTR3;
3792	}
3793	}
3794	int rc2 = VERR_INVALID_PARAMETER;
3795	if (pPT)
3796	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3797	else
3798	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3799	if (rc2 < rc && RT_SUCCESS(rc))
3800	rc = rc2;
3801	}
3802	}
3803	}
3804	}
3805
3806	return rc;
3807	}
3808
3809
3810	/**
3811	* Dumps a 32-bit shadow page table.
3812	*
3813	* @returns VBox status code (VINF_SUCCESS).
3814	* @param pVM The VM handle.
3815	* @param pPT Pointer to the page table.
3816	* @param u32Address The virtual address this table starts at.
3817	* @param PhysSearch Address to search for.
3818	*/
3819	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3820	{
3821	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3822	{
3823	X86PTE Pte = pPT->a[i];
3824	if (Pte.n.u1Present)
3825	{
3826	Log(( /P R S A D G WT CD AT NX 4M a m d /
3827	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3828	u32Address + (i << X86_PT_SHIFT),
3829	Pte.n.u1Write ? 'W' : 'R',
3830	Pte.n.u1User ? 'U' : 'S',
3831	Pte.n.u1Accessed ? 'A' : '-',
3832	Pte.n.u1Dirty ? 'D' : '-',
3833	Pte.n.u1Global ? 'G' : '-',
3834	Pte.n.u1WriteThru ? "WT" : "--",
3835	Pte.n.u1CacheDisable? "CD" : "--",
3836	Pte.n.u1PAT ? "AT" : "--",
3837	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3838	Pte.u & RT_BIT(10) ? '1' : '0',
3839	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3840	Pte.u & X86_PDE_PG_MASK));
3841
3842	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3843	{
3844	uint64_t fPageShw = 0;
3845	RTHCPHYS pPhysHC = 0;
3846
3847	/** @todo SMP support!! */
3848	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3849	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3850	}
3851	}
3852	}
3853	return VINF_SUCCESS;
3854	}
3855
3856
3857	/**
3858	* Dumps a 32-bit guest page directory and page tables.
3859	*
3860	* @returns VBox status code (VINF_SUCCESS).
3861	* @param pVM The VM handle.
3862	* @param cr3 The root of the hierarchy.
3863	* @param cr4 The CR4, PSE is currently used.
3864	* @param PhysSearch Address to search for.
3865	*/
3866	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3867	{
3868	bool fLongMode = false;
3869	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3870	PX86PD pPD = 0;
3871
3872	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3873	if (RT_FAILURE(rc) \|\| !pPD)
3874	{
3875	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3876	return VERR_INVALID_PARAMETER;
3877	}
3878
3879	Log(("cr3=%08x cr4=%08x%s\n"
3880	"%-*s P - Present\n"
3881	"%-*s \| R/W - Read (0) / Write (1)\n"
3882	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3883	"%-*s \| \| \| A - Accessed\n"
3884	"%-*s \| \| \| \| D - Dirty\n"
3885	"%-*s \| \| \| \| \| G - Global\n"
3886	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3887	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3888	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3889	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3890	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3891	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3892	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3893	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3894	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3895	- W U - - - -- -- -- -- -- 010 */
3896	, cr3, cr4, fLongMode ? " Long Mode" : "",
3897	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3898	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3899
3900	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3901	{
3902	X86PDE Pde = pPD->a[i];
3903	if (Pde.n.u1Present)
3904	{
3905	const uint32_t u32Address = i << X86_PD_SHIFT;
3906
3907	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3908	Log(( /P R S A D G WT CD AT NX 4M a m d /
3909	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3910	u32Address,
3911	Pde.b.u1Write ? 'W' : 'R',
3912	Pde.b.u1User ? 'U' : 'S',
3913	Pde.b.u1Accessed ? 'A' : '-',
3914	Pde.b.u1Dirty ? 'D' : '-',
3915	Pde.b.u1Global ? 'G' : '-',
3916	Pde.b.u1WriteThru ? "WT" : "--",
3917	Pde.b.u1CacheDisable? "CD" : "--",
3918	Pde.b.u1PAT ? "AT" : "--",
3919	Pde.u & RT_BIT(9) ? '1' : '0',
3920	Pde.u & RT_BIT(10) ? '1' : '0',
3921	Pde.u & RT_BIT(11) ? '1' : '0',
3922	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3923	/** @todo PhysSearch */
3924	else
3925	{
3926	Log(( /P R S A D G WT CD AT NX 4M a m d /
3927	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3928	u32Address,
3929	Pde.n.u1Write ? 'W' : 'R',
3930	Pde.n.u1User ? 'U' : 'S',
3931	Pde.n.u1Accessed ? 'A' : '-',
3932	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3933	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3934	Pde.n.u1WriteThru ? "WT" : "--",
3935	Pde.n.u1CacheDisable? "CD" : "--",
3936	Pde.u & RT_BIT(9) ? '1' : '0',
3937	Pde.u & RT_BIT(10) ? '1' : '0',
3938	Pde.u & RT_BIT(11) ? '1' : '0',
3939	Pde.u & X86_PDE_PG_MASK));
3940	////if (cMaxDepth >= 1)
3941	{
3942	/** @todo what about using the page pool for mapping PTs? */
3943	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3944	PX86PT pPT = NULL;
3945
3946	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3947
3948	int rc2 = VERR_INVALID_PARAMETER;
3949	if (pPT)
3950	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3951	else
3952	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3953	if (rc2 < rc && RT_SUCCESS(rc))
3954	rc = rc2;
3955	}
3956	}
3957	}
3958	}
3959
3960	return rc;
3961	}
3962
3963
3964	/**
3965	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3966	*
3967	* @returns VBox status code (VINF_SUCCESS).
3968	* @param pVM The VM handle.
3969	* @param cr3 The root of the hierarchy.
3970	* @param cr4 The cr4, only PAE and PSE is currently used.
3971	* @param fLongMode Set if long mode, false if not long mode.
3972	* @param cMaxDepth Number of levels to dump.
3973	* @param pHlp Pointer to the output functions.
3974	*/
3975	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3976	{
3977	if (!pHlp)
3978	pHlp = DBGFR3InfoLogHlp();
3979	if (!cMaxDepth)
3980	return VINF_SUCCESS;
3981	const unsigned cch = fLongMode ? 16 : 8;
3982	pHlp->pfnPrintf(pHlp,
3983	"cr3=%08x cr4=%08x%s\n"
3984	"%-*s P - Present\n"
3985	"%-*s \| R/W - Read (0) / Write (1)\n"
3986	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3987	"%-*s \| \| \| A - Accessed\n"
3988	"%-*s \| \| \| \| D - Dirty\n"
3989	"%-*s \| \| \| \| \| G - Global\n"
3990	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3991	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3992	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3993	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3994	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3995	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3996	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3997	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3998	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3999	- W U - - - -- -- -- -- -- 010 */
4000	, cr3, cr4, fLongMode ? " Long Mode" : "",
4001	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4002	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4003	if (cr4 & X86_CR4_PAE)
4004	{
4005	if (fLongMode)
4006	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4007	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4008	}
4009	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4010	}
4011
4012	#ifdef VBOX_WITH_DEBUGGER
4013
4014	/**
4015	* The '.pgmram' command.
4016	*
4017	* @returns VBox status.
4018	* @param pCmd Pointer to the command descriptor (as registered).
4019	* @param pCmdHlp Pointer to command helper functions.
4020	* @param pVM Pointer to the current VM (if any).
4021	* @param paArgs Pointer to (readonly) array of arguments.
4022	* @param cArgs Number of arguments in the array.
4023	*/
4024	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4025	{
4026	/*
4027	* Validate input.
4028	*/
4029	if (!pVM)
4030	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4031	if (!pVM->pgm.s.pRamRangesRC)
4032	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4033
4034	/*
4035	* Dump the ranges.
4036	*/
4037	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4038	PPGMRAMRANGE pRam;
4039	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4040	{
4041	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4042	"%RGp - %RGp %p\n",
4043	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4044	if (RT_FAILURE(rc))
4045	return rc;
4046	}
4047
4048	return VINF_SUCCESS;
4049	}
4050
4051
4052	/**
4053	* The '.pgmerror' and '.pgmerroroff' commands.
4054	*
4055	* @returns VBox status.
4056	* @param pCmd Pointer to the command descriptor (as registered).
4057	* @param pCmdHlp Pointer to command helper functions.
4058	* @param pVM Pointer to the current VM (if any).
4059	* @param paArgs Pointer to (readonly) array of arguments.
4060	* @param cArgs Number of arguments in the array.
4061	*/
4062	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4063	{
4064	/*
4065	* Validate input.
4066	*/
4067	if (!pVM)
4068	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4069	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4070	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4071
4072	if (!cArgs)
4073	{
4074	/*
4075	* Print the list of error injection locations with status.
4076	*/
4077	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4078	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4079	}
4080	else
4081	{
4082
4083	/*
4084	* String switch on where to inject the error.
4085	*/
4086	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4087	const char *pszWhere = paArgs[0].u.pszString;
4088	if (!strcmp(pszWhere, "handy"))
4089	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4090	else
4091	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4092	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4093	}
4094	return VINF_SUCCESS;
4095	}
4096
4097
4098	/**
4099	* The '.pgmsync' command.
4100	*
4101	* @returns VBox status.
4102	* @param pCmd Pointer to the command descriptor (as registered).
4103	* @param pCmdHlp Pointer to command helper functions.
4104	* @param pVM Pointer to the current VM (if any).
4105	* @param paArgs Pointer to (readonly) array of arguments.
4106	* @param cArgs Number of arguments in the array.
4107	*/
4108	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4109	{
4110	/** @todo SMP support */
4111	PVMCPU pVCpu = &pVM->aCpus[0];
4112
4113	/*
4114	* Validate input.
4115	*/
4116	if (!pVM)
4117	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4118
4119	/*
4120	* Force page directory sync.
4121	*/
4122	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4123
4124	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4125	if (RT_FAILURE(rc))
4126	return rc;
4127
4128	return VINF_SUCCESS;
4129	}
4130
4131
4132	#ifdef VBOX_STRICT
4133	/**
4134	* The '.pgmassertcr3' command.
4135	*
4136	* @returns VBox status.
4137	* @param pCmd Pointer to the command descriptor (as registered).
4138	* @param pCmdHlp Pointer to command helper functions.
4139	* @param pVM Pointer to the current VM (if any).
4140	* @param paArgs Pointer to (readonly) array of arguments.
4141	* @param cArgs Number of arguments in the array.
4142	*/
4143	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4144	{
4145	/** @todo SMP support!! */
4146	PVMCPU pVCpu = &pVM->aCpus[0];
4147
4148	/*
4149	* Validate input.
4150	*/
4151	if (!pVM)
4152	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4153
4154	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4155	if (RT_FAILURE(rc))
4156	return rc;
4157
4158	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4159
4160	return VINF_SUCCESS;
4161	}
4162	#endif /* VBOX_STRICT */
4163
4164	#if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
4165	/**
4166	* The '.pgmcheckduppages' command.
4167	*
4168	* @returns VBox status.
4169	* @param pCmd Pointer to the command descriptor (as registered).
4170	* @param pCmdHlp Pointer to command helper functions.
4171	* @param pVM Pointer to the current VM (if any).
4172	* @param paArgs Pointer to (readonly) array of arguments.
4173	* @param cArgs Number of arguments in the array.
4174	*/
4175	static DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4176	{
4177	unsigned cBallooned = 0;
4178	unsigned cShared = 0;
4179	unsigned cZero = 0;
4180	unsigned cUnique = 0;
4181	unsigned cDuplicate = 0;
4182
4183	pgmLock(pVM);
4184
4185	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4186	{
4187	PPGMPAGE pPage = &pRam->aPages[0];
4188	RTGCPHYS GCPhys = pRam->GCPhys;
4189	uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
4190	while (cLeft-- > 0)
4191	{
4192	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
4193	{
4194	switch (PGM_PAGE_GET_STATE(pPage))
4195	{
4196	case PGM_PAGE_STATE_ZERO:
4197	cZero++;
4198	break;
4199
4200	case PGM_PAGE_STATE_BALLOONED:
4201	cBallooned++;
4202	break;
4203
4204	case PGM_PAGE_STATE_SHARED:
4205	cShared++;
4206	break;
4207
4208	case PGM_PAGE_STATE_ALLOCATED:
4209	case PGM_PAGE_STATE_WRITE_MONITORED:
4210	if (GMMR3IsDuplicatePage(pVM, PGM_PAGE_GET_PAGEID(pPage)))
4211	cDuplicate++;
4212	else
4213	cUnique++;
4214
4215	break;
4216
4217	default:
4218	AssertFailed();
4219	break;
4220	}
4221	}
4222
4223	/* next */
4224	pPage++;
4225	GCPhys += PAGE_SIZE;
4226	}
4227	}
4228	pgmUnlock(pVM);
4229
4230	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Number of zero pages %x\n", cZero);
4231	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Number of ballooned pages %x\n", cBallooned);
4232	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Number of shared pages %x\n", cShared);
4233	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Number of unique pages %x\n", cUnique);
4234	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Number of duplicate pages %x\n", cDuplicate);
4235	return VINF_SUCCESS;
4236	}
4237
4238	#endif /* VBOX_STRICT && HC_ARCH_BITS == 64*/
4239
4240
4241	/**
4242	* The '.pgmsyncalways' command.
4243	*
4244	* @returns VBox status.
4245	* @param pCmd Pointer to the command descriptor (as registered).
4246	* @param pCmdHlp Pointer to command helper functions.
4247	* @param pVM Pointer to the current VM (if any).
4248	* @param paArgs Pointer to (readonly) array of arguments.
4249	* @param cArgs Number of arguments in the array.
4250	*/
4251	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4252	{
4253	/** @todo SMP support!! */
4254	PVMCPU pVCpu = &pVM->aCpus[0];
4255
4256	/*
4257	* Validate input.
4258	*/
4259	if (!pVM)
4260	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4261
4262	/*
4263	* Force page directory sync.
4264	*/
4265	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4266	{
4267	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4268	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4269	}
4270	else
4271	{
4272	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4273	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4274	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4275	}
4276	}
4277
4278
4279	/**
4280	* The '.pgmsyncalways' command.
4281	*
4282	* @returns VBox status.
4283	* @param pCmd Pointer to the command descriptor (as registered).
4284	* @param pCmdHlp Pointer to command helper functions.
4285	* @param pVM Pointer to the current VM (if any).
4286	* @param paArgs Pointer to (readonly) array of arguments.
4287	* @param cArgs Number of arguments in the array.
4288	*/
4289	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4290	{
4291	/*
4292	* Validate input.
4293	*/
4294	if (!pVM)
4295	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4296	if ( cArgs < 1
4297	\|\| cArgs > 2
4298	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
4299	\|\| ( cArgs > 1
4300	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
4301	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4302	if ( cArgs >= 2
4303	&& strcmp(paArgs[1].u.pszString, "nozero"))
4304	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4305	bool fIncZeroPgs = cArgs < 2;
4306
4307	/*
4308	* Open the output file and get the ram parameters.
4309	*/
4310	RTFILE hFile;
4311	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
4312	if (RT_FAILURE(rc))
4313	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
4314
4315	uint32_t cbRamHole = 0;
4316	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
4317	uint64_t cbRam = 0;
4318	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
4319	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
4320
4321	/*
4322	* Dump the physical memory, page by page.
4323	*/
4324	RTGCPHYS GCPhys = 0;
4325	char abZeroPg[PAGE_SIZE];
4326	RT_ZERO(abZeroPg);
4327
4328	pgmLock(pVM);
4329	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
4330	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
4331	pRam = pRam->pNextR3)
4332	{
4333	/* fill the gap */
4334	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
4335	{
4336	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
4337	{
4338	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4339	GCPhys += PAGE_SIZE;
4340	}
4341	}
4342
4343	PCPGMPAGE pPage = &pRam->aPages[0];
4344	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
4345	{
4346	if ( PGM_PAGE_IS_ZERO(pPage)
4347	\|\| PGM_PAGE_IS_BALLOONED(pPage))
4348	{
4349	if (fIncZeroPgs)
4350	{
4351	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4352	if (RT_FAILURE(rc))
4353	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4354	}
4355	}
4356	else
4357	{
4358	switch (PGM_PAGE_GET_TYPE(pPage))
4359	{
4360	case PGMPAGETYPE_RAM:
4361	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
4362	case PGMPAGETYPE_ROM:
4363	case PGMPAGETYPE_MMIO2:
4364	{
4365	void const *pvPage;
4366	PGMPAGEMAPLOCK Lock;
4367	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
4368	if (RT_SUCCESS(rc))
4369	{
4370	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
4371	PGMPhysReleasePageMappingLock(pVM, &Lock);
4372	if (RT_FAILURE(rc))
4373	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4374	}
4375	else
4376	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4377	break;
4378	}
4379
4380	default:
4381	AssertFailed();
4382	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4383	case PGMPAGETYPE_MMIO:
4384	if (fIncZeroPgs)
4385	{
4386	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4387	if (RT_FAILURE(rc))
4388	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4389	}
4390	break;
4391	}
4392	}
4393
4394
4395	/* advance */
4396	GCPhys += PAGE_SIZE;
4397	pPage++;
4398	}
4399	}
4400	pgmUnlock(pVM);
4401
4402	RTFileClose(hFile);
4403	if (RT_SUCCESS(rc))
4404	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4405	return VINF_SUCCESS;
4406	}
4407
4408	#endif /* VBOX_WITH_DEBUGGER */
4409
4410	/**
4411	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4412	*/
4413	typedef struct PGMCHECKINTARGS
4414	{
4415	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4416	PPGMPHYSHANDLER pPrevPhys;
4417	PPGMVIRTHANDLER pPrevVirt;
4418	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4419	PVM pVM;
4420	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4421
4422	/**
4423	* Validate a node in the physical handler tree.
4424	*
4425	* @returns 0 on if ok, other wise 1.
4426	* @param pNode The handler node.
4427	* @param pvUser pVM.
4428	*/
4429	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4430	{
4431	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4432	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4433	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4434	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4435	AssertReleaseMsg( !pArgs->pPrevPhys
4436	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4437	("pPrevPhys=%p %RGp-%RGp %s\n"
4438	" pCur=%p %RGp-%RGp %s\n",
4439	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4440	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4441	pArgs->pPrevPhys = pCur;
4442	return 0;
4443	}
4444
4445
4446	/**
4447	* Validate a node in the virtual handler tree.
4448	*
4449	* @returns 0 on if ok, other wise 1.
4450	* @param pNode The handler node.
4451	* @param pvUser pVM.
4452	*/
4453	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4454	{
4455	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4456	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4457	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4458	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4459	AssertReleaseMsg( !pArgs->pPrevVirt
4460	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4461	("pPrevVirt=%p %RGv-%RGv %s\n"
4462	" pCur=%p %RGv-%RGv %s\n",
4463	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4464	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4465	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4466	{
4467	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4468	("pCur=%p %RGv-%RGv %s\n"
4469	"iPage=%d offVirtHandle=%#x expected %#x\n",
4470	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4471	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4472	}
4473	pArgs->pPrevVirt = pCur;
4474	return 0;
4475	}
4476
4477
4478	/**
4479	* Validate a node in the virtual handler tree.
4480	*
4481	* @returns 0 on if ok, other wise 1.
4482	* @param pNode The handler node.
4483	* @param pvUser pVM.
4484	*/
4485	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4486	{
4487	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4488	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4489	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4490	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4491	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4492	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4493	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4494	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4495	" pCur=%p %RGp-%RGp\n",
4496	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4497	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4498	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4499	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4500	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4501	" pCur=%p %RGp-%RGp\n",
4502	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4503	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4504	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4505	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4506	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4507	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4508	{
4509	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4510	for (;;)
4511	{
4512	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4513	AssertReleaseMsg(pCur2 != pCur,
4514	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4515	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4516	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4517	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4518	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4519	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4520	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4521	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4522	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4523	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4524	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4525	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4526	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4527	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4528	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4529	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4530	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4531	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4532	break;
4533	}
4534	}
4535
4536	pArgs->pPrevPhys2Virt = pCur;
4537	return 0;
4538	}
4539
4540
4541	/**
4542	* Perform an integrity check on the PGM component.
4543	*
4544	* @returns VINF_SUCCESS if everything is fine.
4545	* @returns VBox error status after asserting on integrity breach.
4546	* @param pVM The VM handle.
4547	*/
4548	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4549	{
4550	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4551
4552	/*
4553	* Check the trees.
4554	*/
4555	int cErrors = 0;
4556	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4557	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4558	PGMCHECKINTARGS Args = s_LeftToRight;
4559	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4560	Args = s_RightToLeft;
4561	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4562	Args = s_LeftToRight;
4563	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4564	Args = s_RightToLeft;
4565	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4566	Args = s_LeftToRight;
4567	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4568	Args = s_RightToLeft;
4569	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4570	Args = s_LeftToRight;
4571	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4572	Args = s_RightToLeft;
4573	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4574
4575	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4576	}
4577

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 30495

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