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source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 8454

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1/* $Id: PGMInternal.h 8454 2008-04-29 11:31:44Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___PGMInternal_h
23#define ___PGMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/err.h>
28#include <VBox/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm.h>
31#include <VBox/mm.h>
32#include <VBox/pdmcritsect.h>
33#include <VBox/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/gmm.h>
38#include <iprt/avl.h>
39#include <iprt/assert.h>
40#include <iprt/critsect.h>
41
42#if !defined(IN_PGM_R3) && !defined(IN_PGM_R0) && !defined(IN_PGM_GC)
43# error "Not in PGM! This is an internal header!"
44#endif
45
46
47/** @defgroup grp_pgm_int Internals
48 * @ingroup grp_pgm
49 * @internal
50 * @{
51 */
52
53
54/** @name PGM Compile Time Config
55 * @{
56 */
57
58/**
59 * Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
60 * Comment it if it will break something.
61 */
62#define PGM_OUT_OF_SYNC_IN_GC
63
64/**
65 * Virtualize the dirty bit
66 * This also makes a half-hearted attempt at the accessed bit. For full
67 * accessed bit virtualization define PGM_SYNC_ACCESSED_BIT.
68 */
69#define PGM_SYNC_DIRTY_BIT
70
71/**
72 * Fully virtualize the accessed bit.
73 * @remark This requires SYNC_DIRTY_ACCESSED_BITS to be defined!
74 */
75#define PGM_SYNC_ACCESSED_BIT
76
77/**
78 * Check and skip global PDEs for non-global flushes
79 */
80#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
81
82/**
83 * Sync N pages instead of a whole page table
84 */
85#define PGM_SYNC_N_PAGES
86
87/**
88 * Number of pages to sync during a page fault
89 *
90 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
91 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
92 */
93#define PGM_SYNC_NR_PAGES 8
94
95/**
96 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
97 */
98#define PGM_MAX_PHYSCACHE_ENTRIES 64
99#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
100
101/**
102 * Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
103 */
104#define PGM_PHYSMEMACCESS_CACHING
105
106/*
107 * Assert Sanity.
108 */
109#if defined(PGM_SYNC_ACCESSED_BIT) && !defined(PGM_SYNC_DIRTY_BIT)
110# error "PGM_SYNC_ACCESSED_BIT requires PGM_SYNC_DIRTY_BIT!"
111#endif
112
113/** @def PGMPOOL_WITH_CACHE
114 * Enable agressive caching using the page pool.
115 *
116 * This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
117 */
118#define PGMPOOL_WITH_CACHE
119
120/** @def PGMPOOL_WITH_MIXED_PT_CR3
121 * When defined, we'll deal with 'uncachable' pages.
122 */
123#ifdef PGMPOOL_WITH_CACHE
124# define PGMPOOL_WITH_MIXED_PT_CR3
125#endif
126
127/** @def PGMPOOL_WITH_MONITORING
128 * Monitor the guest pages which are shadowed.
129 * When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
130 * be enabled as well.
131 * @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
132 */
133#ifdef PGMPOOL_WITH_CACHE
134# define PGMPOOL_WITH_MONITORING
135#endif
136
137/** @def PGMPOOL_WITH_GCPHYS_TRACKING
138 * Tracking the of shadow pages mapping guest physical pages.
139 *
140 * This is very expensive, the current cache prototype is trying to figure out
141 * whether it will be acceptable with an agressive caching policy.
142 */
143#if defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
144# define PGMPOOL_WITH_GCPHYS_TRACKING
145#endif
146
147/** @def PGMPOOL_WITH_USER_TRACKNG
148 * Tracking users of shadow pages. This is required for the linking of shadow page
149 * tables and physical guest addresses.
150 */
151#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) || defined(PGMPOOL_WITH_CACHE) || defined(PGMPOOL_WITH_MONITORING)
152# define PGMPOOL_WITH_USER_TRACKING
153#endif
154
155/** @def PGMPOOL_CFG_MAX_GROW
156 * The maximum number of pages to add to the pool in one go.
157 */
158#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
159
160/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
161 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
162 */
163#ifdef VBOX_STRICT
164# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
165#endif
166/** @} */
167
168
169/** @name PDPT and PML4 flags.
170 * These are placed in the three bits available for system programs in
171 * the PDPT and PML4 entries.
172 * @{ */
173/** The entry is a permanent one and it's must always be present.
174 * Never free such an entry. */
175#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
176/** Mapping (hypervisor allocated pagetable). */
177#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
178/** @} */
179
180/** @name Page directory flags.
181 * These are placed in the three bits available for system programs in
182 * the page directory entries.
183 * @{ */
184/** Mapping (hypervisor allocated pagetable). */
185#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
186/** Made read-only to facilitate dirty bit tracking. */
187#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
188/** @} */
189
190/** @name Page flags.
191 * These are placed in the three bits available for system programs in
192 * the page entries.
193 * @{ */
194/** Made read-only to facilitate dirty bit tracking. */
195#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
196
197#ifndef PGM_PTFLAGS_CSAM_VALIDATED
198/** Scanned and approved by CSAM (tm).
199 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
200 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
201#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
202#endif
203/** @} */
204
205/** @name Defines used to indicate the shadow and guest paging in the templates.
206 * @{ */
207#define PGM_TYPE_REAL 1
208#define PGM_TYPE_PROT 2
209#define PGM_TYPE_32BIT 3
210#define PGM_TYPE_PAE 4
211#define PGM_TYPE_AMD64 5
212/** @} */
213
214/** Macro for checking if the guest is using paging.
215 * @param uType PGM_TYPE_*
216 * @remark ASSUMES certain order of the PGM_TYPE_* values.
217 */
218#define PGM_WITH_PAGING(uType) ((uType) >= PGM_TYPE_32BIT)
219
220/** Macro for checking if the guest supports the NX bit.
221 * @param uType PGM_TYPE_*
222 * @remark ASSUMES certain order of the PGM_TYPE_* values.
223 */
224#define PGM_WITH_NX(uType) ((uType) >= PGM_TYPE_PAE)
225
226
227/** @def PGM_HCPHYS_2_PTR
228 * Maps a HC physical page pool address to a virtual address.
229 *
230 * @returns VBox status code.
231 * @param pVM The VM handle.
232 * @param HCPhys The HC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast this.
234 *
235 * @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
236 * small page window employeed by that function. Be careful.
237 * @remark There is no need to assert on the result.
238 */
239#ifdef IN_GC
240# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) PGMGCDynMapHCPage(pVM, HCPhys, (void **)(ppv))
241#else
242# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
243#endif
244
245/** @def PGM_GCPHYS_2_PTR
246 * Maps a GC physical page address to a virtual address.
247 *
248 * @returns VBox status code.
249 * @param pVM The VM handle.
250 * @param GCPhys The GC physical address to map to a virtual one.
251 * @param ppv Where to store the virtual address. No need to cast this.
252 *
253 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
254 * small page window employeed by that function. Be careful.
255 * @remark There is no need to assert on the result.
256 */
257#ifdef IN_GC
258# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMGCDynMapGCPage(pVM, GCPhys, (void **)(ppv))
259#else
260# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
261#endif
262
263/** @def PGM_GCPHYS_2_PTR_EX
264 * Maps a unaligned GC physical page address to a virtual address.
265 *
266 * @returns VBox status code.
267 * @param pVM The VM handle.
268 * @param GCPhys The GC physical address to map to a virtual one.
269 * @param ppv Where to store the virtual address. No need to cast this.
270 *
271 * @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
272 * small page window employeed by that function. Be careful.
273 * @remark There is no need to assert on the result.
274 */
275#ifdef IN_GC
276# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMGCDynMapGCPageEx(pVM, GCPhys, (void **)(ppv))
277#else
278# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1 /* one page only */, (void **)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
279#endif
280
281/** @def PGM_INVL_PG
282 * Invalidates a page when in GC does nothing in HC.
283 *
284 * @param GCVirt The virtual address of the page to invalidate.
285 */
286#ifdef IN_GC
287# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
288#else
289# define PGM_INVL_PG(GCVirt) ((void)0)
290#endif
291
292/** @def PGM_INVL_BIG_PG
293 * Invalidates a 4MB page directory entry when in GC does nothing in HC.
294 *
295 * @param GCVirt The virtual address within the page directory to invalidate.
296 */
297#ifdef IN_GC
298# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
299#else
300# define PGM_INVL_BIG_PG(GCVirt) ((void)0)
301#endif
302
303/** @def PGM_INVL_GUEST_TLBS()
304 * Invalidates all guest TLBs.
305 */
306#ifdef IN_GC
307# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
308#else
309# define PGM_INVL_GUEST_TLBS() ((void)0)
310#endif
311
312
313/**
314 * Structure for tracking GC Mappings.
315 *
316 * This structure is used by linked list in both GC and HC.
317 */
318typedef struct PGMMAPPING
319{
320 /** Pointer to next entry. */
321 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
322 /** Pointer to next entry. */
323 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
324 /** Pointer to next entry. */
325 GCPTRTYPE(struct PGMMAPPING *) pNextGC;
326 /** Start Virtual address. */
327 RTGCUINTPTR GCPtr;
328 /** Last Virtual address (inclusive). */
329 RTGCUINTPTR GCPtrLast;
330 /** Range size (bytes). */
331 RTGCUINTPTR cb;
332 /** Pointer to relocation callback function. */
333 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
334 /** User argument to the callback. */
335 R3PTRTYPE(void *) pvUser;
336 /** Mapping description / name. For easing debugging. */
337 R3PTRTYPE(const char *) pszDesc;
338 /** Number of page tables. */
339 RTUINT cPTs;
340#if HC_ARCH_BITS != GC_ARCH_BITS
341 RTUINT uPadding0; /**< Alignment padding. */
342#endif
343 /** Array of page table mapping data. Each entry
344 * describes one page table. The array can be longer
345 * than the declared length.
346 */
347 struct
348 {
349 /** The HC physical address of the page table. */
350 RTHCPHYS HCPhysPT;
351 /** The HC physical address of the first PAE page table. */
352 RTHCPHYS HCPhysPaePT0;
353 /** The HC physical address of the second PAE page table. */
354 RTHCPHYS HCPhysPaePT1;
355 /** The HC virtual address of the 32-bit page table. */
356 R3PTRTYPE(PX86PT) pPTR3;
357 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
358 R3PTRTYPE(PX86PTPAE) paPaePTsR3;
359 /** The GC virtual address of the 32-bit page table. */
360 GCPTRTYPE(PX86PT) pPTGC;
361 /** The GC virtual address of the two PAE page table. */
362 GCPTRTYPE(PX86PTPAE) paPaePTsGC;
363 /** The GC virtual address of the 32-bit page table. */
364 R0PTRTYPE(PX86PT) pPTR0;
365 /** The GC virtual address of the two PAE page table. */
366 R0PTRTYPE(PX86PTPAE) paPaePTsR0;
367 } aPTs[1];
368} PGMMAPPING;
369/** Pointer to structure for tracking GC Mappings. */
370typedef struct PGMMAPPING *PPGMMAPPING;
371
372
373/**
374 * Physical page access handler structure.
375 *
376 * This is used to keep track of physical address ranges
377 * which are being monitored in some kind of way.
378 */
379typedef struct PGMPHYSHANDLER
380{
381 AVLROGCPHYSNODECORE Core;
382 /** Access type. */
383 PGMPHYSHANDLERTYPE enmType;
384 /** Number of pages to update. */
385 uint32_t cPages;
386 /** Pointer to R3 callback function. */
387 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
388 /** User argument for R3 handlers. */
389 R3PTRTYPE(void *) pvUserR3;
390 /** Pointer to R0 callback function. */
391 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
392 /** User argument for R0 handlers. */
393 R0PTRTYPE(void *) pvUserR0;
394 /** Pointer to GC callback function. */
395 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnHandlerGC;
396 /** User argument for GC handlers. */
397 GCPTRTYPE(void *) pvUserGC;
398 /** Description / Name. For easing debugging. */
399 R3PTRTYPE(const char *) pszDesc;
400#ifdef VBOX_WITH_STATISTICS
401 /** Profiling of this handler. */
402 STAMPROFILE Stat;
403#endif
404} PGMPHYSHANDLER;
405/** Pointer to a physical page access handler structure. */
406typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
407
408
409/**
410 * Cache node for the physical addresses covered by a virtual handler.
411 */
412typedef struct PGMPHYS2VIRTHANDLER
413{
414 /** Core node for the tree based on physical ranges. */
415 AVLROGCPHYSNODECORE Core;
416 /** Offset from this struct to the PGMVIRTHANDLER structure. */
417 int32_t offVirtHandler;
418 /** Offset of the next alias relative to this one.
419 * Bit 0 is used for indicating whether we're in the tree.
420 * Bit 1 is used for indicating that we're the head node.
421 */
422 int32_t offNextAlias;
423} PGMPHYS2VIRTHANDLER;
424/** Pointer to a phys to virtual handler structure. */
425typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
426
427/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
428 * node is in the tree. */
429#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
430/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
431 * node is in the head of an alias chain.
432 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
433#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
434/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
435#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
436
437
438/**
439 * Virtual page access handler structure.
440 *
441 * This is used to keep track of virtual address ranges
442 * which are being monitored in some kind of way.
443 */
444typedef struct PGMVIRTHANDLER
445{
446 /** Core node for the tree based on virtual ranges. */
447 AVLROGCPTRNODECORE Core;
448 /** Number of cache pages. */
449 uint32_t u32Padding;
450 /** Access type. */
451 PGMVIRTHANDLERTYPE enmType;
452 /** Number of cache pages. */
453 uint32_t cPages;
454
455/** @todo The next two members are redundant. It adds some readability though. */
456 /** Start of the range. */
457 RTGCPTR GCPtr;
458 /** End of the range (exclusive). */
459 RTGCPTR GCPtrLast;
460 /** Size of the range (in bytes). */
461 RTGCUINTPTR cb;
462 /** Pointer to the GC callback function. */
463 GCPTRTYPE(PFNPGMGCVIRTHANDLER) pfnHandlerGC;
464 /** Pointer to the HC callback function for invalidation. */
465 R3PTRTYPE(PFNPGMHCVIRTINVALIDATE) pfnInvalidateHC;
466 /** Pointer to the HC callback function. */
467 R3PTRTYPE(PFNPGMHCVIRTHANDLER) pfnHandlerHC;
468 /** Description / Name. For easing debugging. */
469 R3PTRTYPE(const char *) pszDesc;
470#ifdef VBOX_WITH_STATISTICS
471 /** Profiling of this handler. */
472 STAMPROFILE Stat;
473#endif
474 /** Array of cached physical addresses for the monitored ranged. */
475 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
476} PGMVIRTHANDLER;
477/** Pointer to a virtual page access handler structure. */
478typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
479
480
481/**
482 * Page type.
483 * @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
484 * @todo convert to \#defines.
485 */
486typedef enum PGMPAGETYPE
487{
488 /** The usual invalid zero entry. */
489 PGMPAGETYPE_INVALID = 0,
490 /** RAM page. (RWX) */
491 PGMPAGETYPE_RAM,
492 /** MMIO2 page. (RWX) */
493 PGMPAGETYPE_MMIO2,
494 /** Shadowed ROM. (RWX) */
495 PGMPAGETYPE_ROM_SHADOW,
496 /** ROM page. (R-X) */
497 PGMPAGETYPE_ROM,
498 /** MMIO page. (---) */
499 PGMPAGETYPE_MMIO,
500 /** End of valid entries. */
501 PGMPAGETYPE_END
502} PGMPAGETYPE;
503AssertCompile(PGMPAGETYPE_END < 7);
504
505/** @name Page type predicates.
506 * @{ */
507#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
508#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
509#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
510#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
511#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
512/** @} */
513
514
515/**
516 * A Physical Guest Page tracking structure.
517 *
518 * The format of this structure is complicated because we have to fit a lot
519 * of information into as few bits as possible. The format is also subject
520 * to change (there is one comming up soon). Which means that for we'll be
521 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
522 * accessess to the structure.
523 */
524typedef struct PGMPAGE
525{
526 /** The physical address and a whole lot of other stuff. All bits are used! */
527 RTHCPHYS HCPhys;
528 /** The page state. */
529 uint32_t u2StateX : 2;
530 /** Flag indicating that a write monitored page was written to when set. */
531 uint32_t fWrittenToX : 1;
532 /** For later. */
533 uint32_t fSomethingElse : 1;
534 /** The Page ID.
535 * @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
536 * The HCPhys will be 100% static. */
537 uint32_t idPageX : 28;
538 /** The page type (PGMPAGETYPE). */
539 uint32_t u3Type : 3;
540 /** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE*) */
541 uint32_t u2HandlerPhysStateX : 2;
542 /** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE*) */
543 uint32_t u2HandlerVirtStateX : 2;
544 uint32_t u29B : 25;
545} PGMPAGE;
546AssertCompileSize(PGMPAGE, 16);
547/** Pointer to a physical guest page. */
548typedef PGMPAGE *PPGMPAGE;
549/** Pointer to a const physical guest page. */
550typedef const PGMPAGE *PCPGMPAGE;
551/** Pointer to a physical guest page pointer. */
552typedef PPGMPAGE *PPPGMPAGE;
553
554
555/**
556 * Clears the page structure.
557 * @param pPage Pointer to the physical guest page tracking structure.
558 */
559#define PGM_PAGE_CLEAR(pPage) \
560 do { \
561 (pPage)->HCPhys = 0; \
562 (pPage)->u2StateX = 0; \
563 (pPage)->fWrittenToX = 0; \
564 (pPage)->fSomethingElse = 0; \
565 (pPage)->idPageX = 0; \
566 (pPage)->u3Type = 0; \
567 (pPage)->u29B = 0; \
568 } while (0)
569
570/**
571 * Initializes the page structure.
572 * @param pPage Pointer to the physical guest page tracking structure.
573 */
574#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
575 do { \
576 (pPage)->HCPhys = (_HCPhys); \
577 (pPage)->u2StateX = (_uState); \
578 (pPage)->fWrittenToX = 0; \
579 (pPage)->fSomethingElse = 0; \
580 (pPage)->idPageX = (_idPage); \
581 /*(pPage)->u3Type = (_uType); - later */ \
582 PGM_PAGE_SET_TYPE(pPage, _uType); \
583 (pPage)->u29B = 0; \
584 } while (0)
585
586/**
587 * Initializes the page structure of a ZERO page.
588 * @param pPage Pointer to the physical guest page tracking structure.
589 */
590#ifdef VBOX_WITH_NEW_PHYS_CODE
591# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
592 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
593#else
594# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
595 PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
596#endif
597/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
598# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
599 PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
600
601
602/** @name The Page state, PGMPAGE::u2StateX.
603 * @{ */
604/** The zero page.
605 * This is a per-VM page that's never ever mapped writable. */
606#define PGM_PAGE_STATE_ZERO 0
607/** A allocated page.
608 * This is a per-VM page allocated from the page pool (or wherever
609 * we get MMIO2 pages from if the type is MMIO2).
610 */
611#define PGM_PAGE_STATE_ALLOCATED 1
612/** A allocated page that's being monitored for writes.
613 * The shadow page table mappings are read-only. When a write occurs, the
614 * fWrittenTo member is set, the page remapped as read-write and the state
615 * moved back to allocated. */
616#define PGM_PAGE_STATE_WRITE_MONITORED 2
617/** The page is shared, aka. copy-on-write.
618 * This is a page that's shared with other VMs. */
619#define PGM_PAGE_STATE_SHARED 3
620/** @} */
621
622
623/**
624 * Gets the page state.
625 * @returns page state (PGM_PAGE_STATE_*).
626 * @param pPage Pointer to the physical guest page tracking structure.
627 */
628#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
629
630/**
631 * Sets the page state.
632 * @param pPage Pointer to the physical guest page tracking structure.
633 * @param _uState The new page state.
634 */
635#define PGM_PAGE_SET_STATE(pPage, _uState) \
636 do { (pPage)->u2StateX = (_uState); } while (0)
637
638
639/**
640 * Gets the host physical address of the guest page.
641 * @returns host physical address (RTHCPHYS).
642 * @param pPage Pointer to the physical guest page tracking structure.
643 */
644#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
645
646/**
647 * Sets the host physical address of the guest page.
648 * @param pPage Pointer to the physical guest page tracking structure.
649 * @param _HCPhys The new host physical address.
650 */
651#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
652 do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
653 | ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
654
655/**
656 * Get the Page ID.
657 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
658 * @param pPage Pointer to the physical guest page tracking structure.
659 */
660#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
661/* later:
662#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
663 | ((uint32_t)(pPage)->HCPhys & 0xfff) )
664*/
665/**
666 * Sets the Page ID.
667 * @param pPage Pointer to the physical guest page tracking structure.
668 */
669#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
670/* later:
671#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
672 | ((_idPage) & 0xfff) \
673 | (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
674*/
675
676/**
677 * Get the Chunk ID.
678 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
679 * @param pPage Pointer to the physical guest page tracking structure.
680 */
681#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
682/* later:
683#if GMM_CHUNKID_SHIFT == 12
684# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
685#elif GMM_CHUNKID_SHIFT > 12
686# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
687#elif GMM_CHUNKID_SHIFT < 12
688# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
689 | ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
690#else
691# error "GMM_CHUNKID_SHIFT isn't defined or something."
692#endif
693*/
694
695/**
696 * Get the index of the page within the allocaiton chunk.
697 * @returns The page index.
698 * @param pPage Pointer to the physical guest page tracking structure.
699 */
700#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
701/* later:
702#if GMM_CHUNKID_SHIFT <= 12
703# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
704#else
705# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
706 | ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
707#endif
708*/
709
710
711/**
712 * Gets the page type.
713 * @returns The page type.
714 * @param pPage Pointer to the physical guest page tracking structure.
715 */
716#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
717
718/**
719 * Sets the page type.
720 * @param pPage Pointer to the physical guest page tracking structure.
721 * @param _enmType The new page type (PGMPAGETYPE).
722 */
723#ifdef VBOX_WITH_NEW_PHYS_CODE
724#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
725 do { (pPage)->u3Type = (_enmType); } while (0)
726#else
727#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
728 do { \
729 (pPage)->u3Type = (_enmType); \
730 if ((_enmType) == PGMPAGETYPE_ROM) \
731 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM; \
732 else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
733 (pPage)->HCPhys |= MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO2; \
734 else if ((_enmType) == PGMPAGETYPE_MMIO2) \
735 (pPage)->HCPhys |= MM_RAM_FLAGS_MMIO2; \
736 } while (0)
737#endif
738
739
740/**
741 * Checks if the page is 'reserved'.
742 * @returns true/false.
743 * @param pPage Pointer to the physical guest page tracking structure.
744 */
745#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
746
747/**
748 * Checks if the page is marked for MMIO.
749 * @returns true/false.
750 * @param pPage Pointer to the physical guest page tracking structure.
751 */
752#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
753
754/**
755 * Checks if the page is backed by the ZERO page.
756 * @returns true/false.
757 * @param pPage Pointer to the physical guest page tracking structure.
758 */
759#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
760
761/**
762 * Checks if the page is backed by a SHARED page.
763 * @returns true/false.
764 * @param pPage Pointer to the physical guest page tracking structure.
765 */
766#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
767
768
769/**
770 * Marks the paget as written to (for GMM change monitoring).
771 * @param pPage Pointer to the physical guest page tracking structure.
772 */
773#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
774
775/**
776 * Clears the written-to indicator.
777 * @param pPage Pointer to the physical guest page tracking structure.
778 */
779#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
780
781/**
782 * Checks if the page was marked as written-to.
783 * @returns true/false.
784 * @param pPage Pointer to the physical guest page tracking structure.
785 */
786#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
787
788
789/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
790 *
791 * @remarks The values are assigned in order of priority, so we can calculate
792 * the correct state for a page with different handlers installed.
793 * @{ */
794/** No handler installed. */
795#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
796/** Monitoring is temporarily disabled. */
797#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
798/** Write access is monitored. */
799#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
800/** All access is monitored. */
801#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
802/** @} */
803
804/**
805 * Gets the physical access handler state of a page.
806 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
807 * @param pPage Pointer to the physical guest page tracking structure.
808 */
809#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
810
811/**
812 * Sets the physical access handler state of a page.
813 * @param pPage Pointer to the physical guest page tracking structure.
814 * @param _uState The new state value.
815 */
816#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
817 do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
818
819/**
820 * Checks if the page has any physical access handlers, including temporariliy disabled ones.
821 * @returns true/false
822 * @param pPage Pointer to the physical guest page tracking structure.
823 */
824#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
825
826/**
827 * Checks if the page has any active physical access handlers.
828 * @returns true/false
829 * @param pPage Pointer to the physical guest page tracking structure.
830 */
831#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
832
833
834/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
835 *
836 * @remarks The values are assigned in order of priority, so we can calculate
837 * the correct state for a page with different handlers installed.
838 * @{ */
839/** No handler installed. */
840#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
841/* 1 is reserved so the lineup is identical with the physical ones. */
842/** Write access is monitored. */
843#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
844/** All access is monitored. */
845#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
846/** @} */
847
848/**
849 * Gets the virtual access handler state of a page.
850 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
851 * @param pPage Pointer to the physical guest page tracking structure.
852 */
853#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
854
855/**
856 * Sets the virtual access handler state of a page.
857 * @param pPage Pointer to the physical guest page tracking structure.
858 * @param _uState The new state value.
859 */
860#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
861 do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
862
863/**
864 * Checks if the page has any virtual access handlers.
865 * @returns true/false
866 * @param pPage Pointer to the physical guest page tracking structure.
867 */
868#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
869
870/**
871 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
872 * virtual handlers.
873 * @returns true/false
874 * @param pPage Pointer to the physical guest page tracking structure.
875 */
876#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
877
878
879
880/**
881 * Checks if the page has any access handlers, including temporarily disabled ones.
882 * @returns true/false
883 * @param pPage Pointer to the physical guest page tracking structure.
884 */
885#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
886 ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
887 || (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
888
889/**
890 * Checks if the page has any active access handlers.
891 * @returns true/false
892 * @param pPage Pointer to the physical guest page tracking structure.
893 */
894#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
895 ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
896 || (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
897
898/**
899 * Checks if the page has any active access handlers catching all accesses.
900 * @returns true/false
901 * @param pPage Pointer to the physical guest page tracking structure.
902 */
903#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
904 ( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
905 || (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
906
907
908/**
909 * Ram range for GC Phys to HC Phys conversion.
910 *
911 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
912 * conversions too, but we'll let MM handle that for now.
913 *
914 * This structure is used by linked lists in both GC and HC.
915 */
916typedef struct PGMRAMRANGE
917{
918 /** Pointer to the next RAM range - for R3. */
919 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
920 /** Pointer to the next RAM range - for R0. */
921 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
922 /** Pointer to the next RAM range - for GC. */
923 GCPTRTYPE(struct PGMRAMRANGE *) pNextGC;
924#if GC_ARCH_BITS == 32
925 /** Pointer alignment. */
926 RTGCPTR GCPtrAlignment;
927#endif
928 /** Start of the range. Page aligned. */
929 RTGCPHYS GCPhys;
930 /** Last address in the range (inclusive). Page aligned (-1). */
931 RTGCPHYS GCPhysLast;
932 /** Size of the range. (Page aligned of course). */
933 RTGCPHYS cb;
934 /** MM_RAM_* flags */
935 uint32_t fFlags;
936#ifdef VBOX_WITH_NEW_PHYS_CODE
937 uint32_t u32Alignment; /**< alignment. */
938#else
939 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
940 GCPTRTYPE(PRTHCPTR) pavHCChunkGC;
941 /** HC virtual lookup ranges for chunks. Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges. */
942 R3R0PTRTYPE(PRTHCPTR) pavHCChunkHC;
943#endif
944 /** Start of the HC mapping of the range. This is only used for MMIO2. */
945 R3PTRTYPE(void *) pvHC;
946 /** The range description. */
947 R3PTRTYPE(const char *) pszDesc;
948
949 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
950#ifdef VBOX_WITH_NEW_PHYS_CODE
951 uint32_t au32Reserved[2];
952#elif HC_ARCH_BITS == 32
953 uint32_t au32Reserved[1];
954#endif
955
956 /** Array of physical guest page tracking structures. */
957 PGMPAGE aPages[1];
958} PGMRAMRANGE;
959/** Pointer to Ram range for GC Phys to HC Phys conversion. */
960typedef PGMRAMRANGE *PPGMRAMRANGE;
961
962/** Return hc ptr corresponding to the ram range and physical offset */
963#define PGMRAMRANGE_GETHCPTR(pRam, off) \
964 (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[(off >> PGM_DYNAMIC_CHUNK_SHIFT)] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
965 : (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
966
967/**
968 * Per page tracking structure for ROM image.
969 *
970 * A ROM image may have a shadow page, in which case we may have
971 * two pages backing it. This structure contains the PGMPAGE for
972 * both while PGMRAMRANGE have a copy of the active one. It is
973 * important that these aren't out of sync in any regard other
974 * than page pool tracking data.
975 */
976typedef struct PGMROMPAGE
977{
978 /** The page structure for the virgin ROM page. */
979 PGMPAGE Virgin;
980 /** The page structure for the shadow RAM page. */
981 PGMPAGE Shadow;
982 /** The current protection setting. */
983 PGMROMPROT enmProt;
984 /** Pad the structure size to a multiple of 8. */
985 uint32_t u32Padding;
986} PGMROMPAGE;
987/** Pointer to a ROM page tracking structure. */
988typedef PGMROMPAGE *PPGMROMPAGE;
989
990
991/**
992 * A registered ROM image.
993 *
994 * This is needed to keep track of ROM image since they generally
995 * intrude into a PGMRAMRANGE. It also keeps track of additional
996 * info like the two page sets (read-only virgin and read-write shadow),
997 * the current state of each page.
998 *
999 * Because access handlers cannot easily be executed in a different
1000 * context, the ROM ranges needs to be accessible and in all contexts.
1001 */
1002typedef struct PGMROMRANGE
1003{
1004 /** Pointer to the next range - R3. */
1005 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1006 /** Pointer to the next range - R0. */
1007 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1008 /** Pointer to the next range - GC. */
1009 GCPTRTYPE(struct PGMROMRANGE *) pNextGC;
1010#if GC_ARCH_BITS == 32
1011 RTGCPTR GCPtrAlignment; /**< Pointer alignment. */
1012#endif
1013 /** Address of the range. */
1014 RTGCPHYS GCPhys;
1015 /** Address of the last byte in the range. */
1016 RTGCPHYS GCPhysLast;
1017 /** Size of the range. */
1018 RTGCPHYS cb;
1019 /** The flags (PGMPHYS_ROM_FLAG_*). */
1020 uint32_t fFlags;
1021 /**< Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1022 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1023 /** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1024 * This is used for strictness checks. */
1025 R3PTRTYPE(const void *) pvOriginal;
1026 /** The ROM description. */
1027 R3PTRTYPE(const char *) pszDesc;
1028 /** The per page tracking structures. */
1029 PGMROMPAGE aPages[1];
1030} PGMROMRANGE;
1031/** Pointer to a ROM range. */
1032typedef PGMROMRANGE *PPGMROMRANGE;
1033
1034
1035/**
1036 * A registered MMIO2 (= Device RAM) range.
1037 *
1038 * There are a few reason why we need to keep track of these
1039 * registrations. One of them is the deregistration & cleanup
1040 * stuff, while another is that the PGMRAMRANGE associated with
1041 * such a region may have to be removed from the ram range list.
1042 *
1043 * Overlapping with a RAM range has to be 100% or none at all. The
1044 * pages in the existing RAM range must not be ROM nor MMIO. A guru
1045 * meditation will be raised if a partial overlap or an overlap of
1046 * ROM pages is encountered. On an overlap we will free all the
1047 * existing RAM pages and put in the ram range pages instead.
1048 */
1049typedef struct PGMMMIO2RANGE
1050{
1051 /** The owner of the range. (a device) */
1052 PPDMDEVINSR3 pDevInsR3;
1053 /** Pointer to the ring-3 mapping of the allocation. */
1054 RTR3PTR pvR3;
1055 /** Pointer to the next range - R3. */
1056 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1057 /** Whether it's mapped or not. */
1058 bool fMapped;
1059 /** Whether it's overlapping or not. */
1060 bool fOverlapping;
1061 /** The PCI region number.
1062 * @remarks This ASSUMES that nobody will ever really need to have multiple
1063 * PCI devices with matching MMIO region numbers on a single device. */
1064 uint8_t iRegion;
1065 /**< Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1066 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1067 /** The associated RAM range. */
1068 PGMRAMRANGE RamRange;
1069} PGMMMIO2RANGE;
1070/** Pointer to a MMIO2 range. */
1071typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1072
1073
1074
1075
1076/** @todo r=bird: fix typename. */
1077/**
1078 * PGMPhysRead/Write cache entry
1079 */
1080typedef struct PGMPHYSCACHE_ENTRY
1081{
1082 /** HC pointer to physical page */
1083 R3PTRTYPE(uint8_t *) pbHC;
1084 /** GC Physical address for cache entry */
1085 RTGCPHYS GCPhys;
1086#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1087 RTGCPHYS u32Padding0; /**< alignment padding. */
1088#endif
1089} PGMPHYSCACHE_ENTRY;
1090
1091/**
1092 * PGMPhysRead/Write cache to reduce REM memory access overhead
1093 */
1094typedef struct PGMPHYSCACHE
1095{
1096 /** Bitmap of valid cache entries */
1097 uint64_t aEntries;
1098 /** Cache entries */
1099 PGMPHYSCACHE_ENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1100} PGMPHYSCACHE;
1101
1102
1103/** Pointer to an allocation chunk ring-3 mapping. */
1104typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1105/** Pointer to an allocation chunk ring-3 mapping pointer. */
1106typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1107
1108/**
1109 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1110 *
1111 * The primary tree (Core) uses the chunk id as key.
1112 * The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1113 */
1114typedef struct PGMCHUNKR3MAP
1115{
1116 /** The key is the chunk id. */
1117 AVLU32NODECORE Core;
1118 /** The key is the ageing sequence number. */
1119 AVLLU32NODECORE AgeCore;
1120 /** The current age thingy. */
1121 uint32_t iAge;
1122 /** The current reference count. */
1123 uint32_t volatile cRefs;
1124 /** The current permanent reference count. */
1125 uint32_t volatile cPermRefs;
1126 /** The mapping address. */
1127 void *pv;
1128} PGMCHUNKR3MAP;
1129
1130/**
1131 * Allocation chunk ring-3 mapping TLB entry.
1132 */
1133typedef struct PGMCHUNKR3MAPTLBE
1134{
1135 /** The chunk id. */
1136 uint32_t volatile idChunk;
1137#if HC_ARCH_BITS == 64
1138 uint32_t u32Padding; /**< alignment padding. */
1139#endif
1140 /** The chunk map. */
1141 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1142} PGMCHUNKR3MAPTLBE;
1143/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1144typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1145
1146/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1147 * @remark Must be a power of two value. */
1148#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1149
1150/**
1151 * Allocation chunk ring-3 mapping TLB.
1152 *
1153 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1154 * At first glance this might look kinda odd since AVL trees are
1155 * supposed to give the most optimial lookup times of all trees
1156 * due to their balancing. However, take a tree with 1023 nodes
1157 * in it, that's 10 levels, meaning that most searches has to go
1158 * down 9 levels before they find what they want. This isn't fast
1159 * compared to a TLB hit. There is the factor of cache misses,
1160 * and of course the problem with trees and branch prediction.
1161 * This is why we use TLBs in front of most of the trees.
1162 *
1163 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1164 * difficult when we switch to inlined AVL trees (from kStuff).
1165 */
1166typedef struct PGMCHUNKR3MAPTLB
1167{
1168 /** The TLB entries. */
1169 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1170} PGMCHUNKR3MAPTLB;
1171
1172/**
1173 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1174 * @returns Chunk TLB index.
1175 * @param idChunk The Chunk ID.
1176 */
1177#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1178
1179
1180/**
1181 * Ring-3 guest page mapping TLB entry.
1182 * @remarks used in ring-0 as well at the moment.
1183 */
1184typedef struct PGMPAGER3MAPTLBE
1185{
1186 /** Address of the page. */
1187 RTGCPHYS volatile GCPhys;
1188 /** The guest page. */
1189 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1190 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1191 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1192 /** The address */
1193 R3R0PTRTYPE(void *) volatile pv;
1194#if HC_ARCH_BITS == 32
1195 uint32_t u32Padding; /**< alignment padding. */
1196#endif
1197} PGMPAGER3MAPTLBE;
1198/** Pointer to an entry in the HC physical TLB. */
1199typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1200
1201
1202/** The number of entries in the ring-3 guest page mapping TLB.
1203 * @remarks The value must be a power of two. */
1204#define PGM_PAGER3MAPTLB_ENTRIES 64
1205
1206/**
1207 * Ring-3 guest page mapping TLB.
1208 * @remarks used in ring-0 as well at the moment.
1209 */
1210typedef struct PGMPAGER3MAPTLB
1211{
1212 /** The TLB entries. */
1213 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1214} PGMPAGER3MAPTLB;
1215/** Pointer to the ring-3 guest page mapping TLB. */
1216typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1217
1218/**
1219 * Calculates the index of the TLB entry for the specified guest page.
1220 * @returns Physical TLB index.
1221 * @param GCPhys The guest physical address.
1222 */
1223#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1224
1225
1226/** @name Context neutrual page mapper TLB.
1227 *
1228 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1229 * code is writting in a kind of context neutrual way. Time will show whether
1230 * this actually makes sense or not...
1231 *
1232 * @{ */
1233/** @typedef PPGMPAGEMAPTLB
1234 * The page mapper TLB pointer type for the current context. */
1235/** @typedef PPGMPAGEMAPTLB
1236 * The page mapper TLB entry pointer type for the current context. */
1237/** @typedef PPGMPAGEMAPTLB
1238 * The page mapper TLB entry pointer pointer type for the current context. */
1239/** @def PGMPAGEMAPTLB_ENTRIES
1240 * The number of TLB entries in the page mapper TLB for the current context. */
1241/** @def PGM_PAGEMAPTLB_IDX
1242 * Calculate the TLB index for a guest physical address.
1243 * @returns The TLB index.
1244 * @param GCPhys The guest physical address. */
1245/** @typedef PPGMPAGEMAP
1246 * Pointer to a page mapper unit for current context. */
1247/** @typedef PPPGMPAGEMAP
1248 * Pointer to a page mapper unit pointer for current context. */
1249#ifdef IN_GC
1250// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1251// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1252// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1253# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1254# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1255 typedef void * PPGMPAGEMAP;
1256 typedef void ** PPPGMPAGEMAP;
1257//#elif IN_RING0
1258// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1259// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1260// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1261//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1262//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1263// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1264// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1265#else
1266 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1267 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1268 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1269# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1270# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1271 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1272 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1273#endif
1274/** @} */
1275
1276
1277/** @name PGM Pool Indexes.
1278 * Aka. the unique shadow page identifier.
1279 * @{ */
1280/** NIL page pool IDX. */
1281#define NIL_PGMPOOL_IDX 0
1282/** The first normal index. */
1283#define PGMPOOL_IDX_FIRST_SPECIAL 1
1284/** Page directory (32-bit root). */
1285#define PGMPOOL_IDX_PD 1
1286/** The extended PAE page directory (2048 entries, works as root currently). */
1287#define PGMPOOL_IDX_PAE_PD 2
1288 /** PAE Page Directory Table 0. */
1289#define PGMPOOL_IDX_PAE_PD_0 3
1290 /** PAE Page Directory Table 1. */
1291#define PGMPOOL_IDX_PAE_PD_1 4
1292 /** PAE Page Directory Table 2. */
1293#define PGMPOOL_IDX_PAE_PD_2 5
1294 /** PAE Page Directory Table 3. */
1295#define PGMPOOL_IDX_PAE_PD_3 6
1296/** Page Directory Pointer Table (PAE root, not currently used). */
1297#define PGMPOOL_IDX_PDPT 7
1298/** Page Map Level-4 (64-bit root). */
1299#define PGMPOOL_IDX_PML4 8
1300/** The first normal index. */
1301#define PGMPOOL_IDX_FIRST 9
1302/** The last valid index. (inclusive, 14 bits) */
1303#define PGMPOOL_IDX_LAST 0x3fff
1304/** @} */
1305
1306/** The NIL index for the parent chain. */
1307#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1308
1309/**
1310 * Node in the chain linking a shadowed page to it's parent (user).
1311 */
1312#pragma pack(1)
1313typedef struct PGMPOOLUSER
1314{
1315 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1316 uint16_t iNext;
1317 /** The user page index. */
1318 uint16_t iUser;
1319 /** Index into the user table. */
1320 uint16_t iUserTable;
1321} PGMPOOLUSER, *PPGMPOOLUSER;
1322typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1323#pragma pack()
1324
1325
1326/** The NIL index for the phys ext chain. */
1327#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1328
1329/**
1330 * Node in the chain of physical cross reference extents.
1331 */
1332#pragma pack(1)
1333typedef struct PGMPOOLPHYSEXT
1334{
1335 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1336 uint16_t iNext;
1337 /** The user page index. */
1338 uint16_t aidx[3];
1339} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1340typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1341#pragma pack()
1342
1343
1344/**
1345 * The kind of page that's being shadowed.
1346 */
1347typedef enum PGMPOOLKIND
1348{
1349 /** The virtual invalid 0 entry. */
1350 PGMPOOLKIND_INVALID = 0,
1351 /** The entry is free (=unused). */
1352 PGMPOOLKIND_FREE,
1353
1354 /** Shw: 32-bit page table; Gst: no paging */
1355 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1356 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1357 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1358 /** Shw: 32-bit page table; Gst: 4MB page. */
1359 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1360 /** Shw: PAE page table; Gst: no paging */
1361 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1362 /** Shw: PAE page table; Gst: 32-bit page table. */
1363 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1364 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1365 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1366 /** Shw: PAE page table; Gst: PAE page table. */
1367 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1368 /** Shw: PAE page table; Gst: 2MB page. */
1369 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1370
1371 /** Shw: PAE page directory; Gst: 32-bit page directory. */
1372 PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1373 /** Shw: PAE page directory; Gst: PAE page directory. */
1374 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1375
1376 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1377 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1378
1379 /** Shw: Root 32-bit page directory. */
1380 PGMPOOLKIND_ROOT_32BIT_PD,
1381 /** Shw: Root PAE page directory */
1382 PGMPOOLKIND_ROOT_PAE_PD,
1383 /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1384 PGMPOOLKIND_ROOT_PDPT,
1385 /** Shw: Root page map level-4 table. */
1386 PGMPOOLKIND_ROOT_PML4,
1387
1388 /** The last valid entry. */
1389 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_PML4
1390} PGMPOOLKIND;
1391
1392
1393/**
1394 * The tracking data for a page in the pool.
1395 */
1396typedef struct PGMPOOLPAGE
1397{
1398 /** AVL node code with the (HC) physical address of this page. */
1399 AVLOHCPHYSNODECORE Core;
1400 /** Pointer to the HC mapping of the page. */
1401 R3R0PTRTYPE(void *) pvPageHC;
1402 /** The guest physical address. */
1403 RTGCPHYS GCPhys;
1404 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1405 uint8_t enmKind;
1406 uint8_t bPadding;
1407 /** The index of this page. */
1408 uint16_t idx;
1409 /** The next entry in the list this page currently resides in.
1410 * It's either in the free list or in the GCPhys hash. */
1411 uint16_t iNext;
1412#ifdef PGMPOOL_WITH_USER_TRACKING
1413 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1414 uint16_t iUserHead;
1415 /** The number of present entries. */
1416 uint16_t cPresent;
1417 /** The first entry in the table which is present. */
1418 uint16_t iFirstPresent;
1419#endif
1420#ifdef PGMPOOL_WITH_MONITORING
1421 /** The number of modifications to the monitored page. */
1422 uint16_t cModifications;
1423 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1424 uint16_t iModifiedNext;
1425 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1426 uint16_t iModifiedPrev;
1427 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1428 uint16_t iMonitoredNext;
1429 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1430 uint16_t iMonitoredPrev;
1431#endif
1432#ifdef PGMPOOL_WITH_CACHE
1433 /** The next page in the age list. */
1434 uint16_t iAgeNext;
1435 /** The previous page in the age list. */
1436 uint16_t iAgePrev;
1437#endif /* PGMPOOL_WITH_CACHE */
1438 /** Used to indicate that the page is zeroed. */
1439 bool fZeroed;
1440 /** Used to indicate that a PT has non-global entries. */
1441 bool fSeenNonGlobal;
1442 /** Used to indicate that we're monitoring writes to the guest page. */
1443 bool fMonitored;
1444 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1445 * (All pages are in the age list.) */
1446 bool fCached;
1447 /** This is used by the R3 access handlers when invoked by an async thread.
1448 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1449 bool volatile fReusedFlushPending;
1450 /** Used to indicate that the guest is mapping the page is also used as a CR3.
1451 * In these cases the access handler acts differently and will check
1452 * for mapping conflicts like the normal CR3 handler.
1453 * @todo When we change the CR3 shadowing to use pool pages, this flag can be
1454 * replaced by a list of pages which share access handler.
1455 */
1456 bool fCR3Mix;
1457} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
1458
1459
1460#ifdef PGMPOOL_WITH_CACHE
1461/** The hash table size. */
1462# define PGMPOOL_HASH_SIZE 0x40
1463/** The hash function. */
1464# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1465#endif
1466
1467
1468/**
1469 * The shadow page pool instance data.
1470 *
1471 * It's all one big allocation made at init time, except for the
1472 * pages that is. The user nodes follows immediatly after the
1473 * page structures.
1474 */
1475typedef struct PGMPOOL
1476{
1477 /** The VM handle - HC Ptr. */
1478 R3R0PTRTYPE(PVM) pVMHC;
1479 /** The VM handle - GC Ptr. */
1480 GCPTRTYPE(PVM) pVMGC;
1481 /** The max pool size. This includes the special IDs. */
1482 uint16_t cMaxPages;
1483 /** The current pool size. */
1484 uint16_t cCurPages;
1485 /** The head of the free page list. */
1486 uint16_t iFreeHead;
1487 /* Padding. */
1488 uint16_t u16Padding;
1489#ifdef PGMPOOL_WITH_USER_TRACKING
1490 /** Head of the chain of free user nodes. */
1491 uint16_t iUserFreeHead;
1492 /** The number of user nodes we've allocated. */
1493 uint16_t cMaxUsers;
1494 /** The number of present page table entries in the entire pool. */
1495 uint32_t cPresent;
1496 /** Pointer to the array of user nodes - GC pointer. */
1497 GCPTRTYPE(PPGMPOOLUSER) paUsersGC;
1498 /** Pointer to the array of user nodes - HC pointer. */
1499 R3R0PTRTYPE(PPGMPOOLUSER) paUsersHC;
1500#endif /* PGMPOOL_WITH_USER_TRACKING */
1501#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1502 /** Head of the chain of free phys ext nodes. */
1503 uint16_t iPhysExtFreeHead;
1504 /** The number of user nodes we've allocated. */
1505 uint16_t cMaxPhysExts;
1506 /** Pointer to the array of physical xref extent - GC pointer. */
1507 GCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsGC;
1508 /** Pointer to the array of physical xref extent nodes - HC pointer. */
1509 R3R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsHC;
1510#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1511#ifdef PGMPOOL_WITH_CACHE
1512 /** Hash table for GCPhys addresses. */
1513 uint16_t aiHash[PGMPOOL_HASH_SIZE];
1514 /** The head of the age list. */
1515 uint16_t iAgeHead;
1516 /** The tail of the age list. */
1517 uint16_t iAgeTail;
1518 /** Set if the cache is enabled. */
1519 bool fCacheEnabled;
1520#endif /* PGMPOOL_WITH_CACHE */
1521#ifdef PGMPOOL_WITH_MONITORING
1522 /** Head of the list of modified pages. */
1523 uint16_t iModifiedHead;
1524 /** The current number of modified pages. */
1525 uint16_t cModifiedPages;
1526 /** Access handler, GC. */
1527 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnAccessHandlerGC;
1528 /** Access handler, R0. */
1529 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1530 /** Access handler, R3. */
1531 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1532 /** The access handler description (HC ptr). */
1533 R3PTRTYPE(const char *) pszAccessHandler;
1534#endif /* PGMPOOL_WITH_MONITORING */
1535 /** The number of pages currently in use. */
1536 uint16_t cUsedPages;
1537#ifdef VBOX_WITH_STATISTICS
1538 /** The high wather mark for cUsedPages. */
1539 uint16_t cUsedPagesHigh;
1540 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1541 /** Profiling pgmPoolAlloc(). */
1542 STAMPROFILEADV StatAlloc;
1543 /** Profiling pgmPoolClearAll(). */
1544 STAMPROFILE StatClearAll;
1545 /** Profiling pgmPoolFlushAllInt(). */
1546 STAMPROFILE StatFlushAllInt;
1547 /** Profiling pgmPoolFlushPage(). */
1548 STAMPROFILE StatFlushPage;
1549 /** Profiling pgmPoolFree(). */
1550 STAMPROFILE StatFree;
1551 /** Profiling time spent zeroing pages. */
1552 STAMPROFILE StatZeroPage;
1553# ifdef PGMPOOL_WITH_USER_TRACKING
1554 /** Profiling of pgmPoolTrackDeref. */
1555 STAMPROFILE StatTrackDeref;
1556 /** Profiling pgmTrackFlushGCPhysPT. */
1557 STAMPROFILE StatTrackFlushGCPhysPT;
1558 /** Profiling pgmTrackFlushGCPhysPTs. */
1559 STAMPROFILE StatTrackFlushGCPhysPTs;
1560 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
1561 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1562 /** Number of times we've been out of user records. */
1563 STAMCOUNTER StatTrackFreeUpOneUser;
1564# endif
1565# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1566 /** Profiling deref activity related tracking GC physical pages. */
1567 STAMPROFILE StatTrackDerefGCPhys;
1568 /** Number of linear searches for a HCPhys in the ram ranges. */
1569 STAMCOUNTER StatTrackLinearRamSearches;
1570 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1571 STAMCOUNTER StamTrackPhysExtAllocFailures;
1572# endif
1573# ifdef PGMPOOL_WITH_MONITORING
1574 /** Profiling the GC PT access handler. */
1575 STAMPROFILE StatMonitorGC;
1576 /** Times we've failed interpreting the instruction. */
1577 STAMCOUNTER StatMonitorGCEmulateInstr;
1578 /** Profiling the pgmPoolFlushPage calls made from the GC PT access handler. */
1579 STAMPROFILE StatMonitorGCFlushPage;
1580 /** Times we've detected fork(). */
1581 STAMCOUNTER StatMonitorGCFork;
1582 /** Profiling the GC access we've handled (except REP STOSD). */
1583 STAMPROFILE StatMonitorGCHandled;
1584 /** Times we've failed interpreting a patch code instruction. */
1585 STAMCOUNTER StatMonitorGCIntrFailPatch1;
1586 /** Times we've failed interpreting a patch code instruction during flushing. */
1587 STAMCOUNTER StatMonitorGCIntrFailPatch2;
1588 /** The number of times we've seen rep prefixes we can't handle. */
1589 STAMCOUNTER StatMonitorGCRepPrefix;
1590 /** Profiling the REP STOSD cases we've handled. */
1591 STAMPROFILE StatMonitorGCRepStosd;
1592
1593 /** Profiling the HC PT access handler. */
1594 STAMPROFILE StatMonitorHC;
1595 /** Times we've failed interpreting the instruction. */
1596 STAMCOUNTER StatMonitorHCEmulateInstr;
1597 /** Profiling the pgmPoolFlushPage calls made from the HC PT access handler. */
1598 STAMPROFILE StatMonitorHCFlushPage;
1599 /** Times we've detected fork(). */
1600 STAMCOUNTER StatMonitorHCFork;
1601 /** Profiling the HC access we've handled (except REP STOSD). */
1602 STAMPROFILE StatMonitorHCHandled;
1603 /** The number of times we've seen rep prefixes we can't handle. */
1604 STAMCOUNTER StatMonitorHCRepPrefix;
1605 /** Profiling the REP STOSD cases we've handled. */
1606 STAMPROFILE StatMonitorHCRepStosd;
1607 /** The number of times we're called in an async thread an need to flush. */
1608 STAMCOUNTER StatMonitorHCAsync;
1609 /** The high wather mark for cModifiedPages. */
1610 uint16_t cModifiedPagesHigh;
1611 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundrary. */
1612# endif
1613# ifdef PGMPOOL_WITH_CACHE
1614 /** The number of cache hits. */
1615 STAMCOUNTER StatCacheHits;
1616 /** The number of cache misses. */
1617 STAMCOUNTER StatCacheMisses;
1618 /** The number of times we've got a conflict of 'kind' in the cache. */
1619 STAMCOUNTER StatCacheKindMismatches;
1620 /** Number of times we've been out of pages. */
1621 STAMCOUNTER StatCacheFreeUpOne;
1622 /** The number of cacheable allocations. */
1623 STAMCOUNTER StatCacheCacheable;
1624 /** The number of uncacheable allocations. */
1625 STAMCOUNTER StatCacheUncacheable;
1626# endif
1627#elif HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1628 uint32_t Alignment1; /**< Align the next member on a 64-bit boundrary. */
1629#endif
1630 /** The AVL tree for looking up a page by its HC physical address. */
1631 AVLOHCPHYSTREE HCPhysTree;
1632 uint32_t Alignment3; /**< Align the next member on a 64-bit boundrary. */
1633 /** Array of pages. (cMaxPages in length)
1634 * The Id is the index into thist array.
1635 */
1636 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1637} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
1638
1639
1640/** @def PGMPOOL_PAGE_2_PTR
1641 * Maps a pool page pool into the current context.
1642 *
1643 * @returns VBox status code.
1644 * @param pVM The VM handle.
1645 * @param pPage The pool page.
1646 *
1647 * @remark In HC this uses PGMGCDynMapHCPage(), so it will consume of the
1648 * small page window employeed by that function. Be careful.
1649 * @remark There is no need to assert on the result.
1650 */
1651#ifdef IN_GC
1652# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmGCPoolMapPage((pVM), (pPage))
1653#else
1654# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageHC)
1655#endif
1656
1657
1658/**
1659 * Trees are using self relative offsets as pointers.
1660 * So, all its data, including the root pointer, must be in the heap for HC and GC
1661 * to have the same layout.
1662 */
1663typedef struct PGMTREES
1664{
1665 /** Physical access handlers (AVL range+offsetptr tree). */
1666 AVLROGCPHYSTREE PhysHandlers;
1667 /** Virtual access handlers (AVL range + GC ptr tree). */
1668 AVLROGCPTRTREE VirtHandlers;
1669 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1670 AVLROGCPHYSTREE PhysToVirtHandlers;
1671 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1672 AVLROGCPTRTREE HyperVirtHandlers;
1673} PGMTREES;
1674/** Pointer to PGM trees. */
1675typedef PGMTREES *PPGMTREES;
1676
1677
1678/** @name Paging mode macros
1679 * @{ */
1680#ifdef IN_GC
1681# define PGM_CTX(a,b) a##GC##b
1682# define PGM_CTX_STR(a,b) a "GC" b
1683# define PGM_CTX_DECL(type) PGMGCDECL(type)
1684#else
1685# ifdef IN_RING3
1686# define PGM_CTX(a,b) a##R3##b
1687# define PGM_CTX_STR(a,b) a "R3" b
1688# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1689# else
1690# define PGM_CTX(a,b) a##R0##b
1691# define PGM_CTX_STR(a,b) a "R0" b
1692# define PGM_CTX_DECL(type) PGMDECL(type)
1693# endif
1694#endif
1695
1696#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1697#define PGM_GST_NAME_GC_REAL_STR(name) "pgmGCGstReal" #name
1698#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1699#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1700#define PGM_GST_NAME_GC_PROT_STR(name) "pgmGCGstProt" #name
1701#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1702#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1703#define PGM_GST_NAME_GC_32BIT_STR(name) "pgmGCGst32Bit" #name
1704#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1705#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1706#define PGM_GST_NAME_GC_PAE_STR(name) "pgmGCGstPAE" #name
1707#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1708#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1709#define PGM_GST_NAME_GC_AMD64_STR(name) "pgmGCGstAMD64" #name
1710#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1711#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1712#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1713
1714#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1715#define PGM_SHW_NAME_GC_32BIT_STR(name) "pgmGCShw32Bit" #name
1716#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1717#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1718#define PGM_SHW_NAME_GC_PAE_STR(name) "pgmGCShwPAE" #name
1719#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1720#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1721#define PGM_SHW_NAME_GC_AMD64_STR(name) "pgmGCShwAMD64" #name
1722#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1723#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1724#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1725
1726/* Shw_Gst */
1727#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1728#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1729#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1730#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1731#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1732#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1733#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1734#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1735#define PGM_BTH_NAME_GC_32BIT_REAL_STR(name) "pgmGCBth32BitReal" #name
1736#define PGM_BTH_NAME_GC_32BIT_PROT_STR(name) "pgmGCBth32BitProt" #name
1737#define PGM_BTH_NAME_GC_32BIT_32BIT_STR(name) "pgmGCBth32Bit32Bit" #name
1738#define PGM_BTH_NAME_GC_PAE_REAL_STR(name) "pgmGCBthPAEReal" #name
1739#define PGM_BTH_NAME_GC_PAE_PROT_STR(name) "pgmGCBthPAEProt" #name
1740#define PGM_BTH_NAME_GC_PAE_32BIT_STR(name) "pgmGCBthPAE32Bit" #name
1741#define PGM_BTH_NAME_GC_PAE_PAE_STR(name) "pgmGCBthPAEPAE" #name
1742#define PGM_BTH_NAME_GC_AMD64_AMD64_STR(name) "pgmGCBthAMD64AMD64" #name
1743#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1744#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1745#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1746#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1747#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1748#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1749#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1750#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1751#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
1752#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
1753/** @} */
1754
1755/**
1756 * Data for each paging mode.
1757 */
1758typedef struct PGMMODEDATA
1759{
1760 /** The guest mode type. */
1761 uint32_t uGstType;
1762 /** The shadow mode type. */
1763 uint32_t uShwType;
1764
1765 /** @name Function pointers for Shadow paging.
1766 * @{
1767 */
1768 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1769 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1770 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1771 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1772 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1773 DECLR3CALLBACKMEMBER(int, pfnR3ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1774 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1775
1776 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1777 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1778 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1779 DECLGCCALLBACKMEMBER(int, pfnGCShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1780 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1781
1782 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1783 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1784 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1785 DECLR0CALLBACKMEMBER(int, pfnR0ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1786 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1787 /** @} */
1788
1789 /** @name Function pointers for Guest paging.
1790 * @{
1791 */
1792 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1793 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
1794 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1795 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1796 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1797 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1798 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
1799 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1800 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
1801 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
1802 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
1803 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
1804 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
1805
1806 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1807 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1808 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1809 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1810 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
1811 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1812 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
1813 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
1814 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
1815
1816 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
1817 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1818 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
1819 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1820 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
1821 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
1822 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
1823 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
1824 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
1825 /** @} */
1826
1827 /** @name Function pointers for Both Shadow and Guest paging.
1828 * @{
1829 */
1830 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1831 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1832 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1833 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1834 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1835 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1836 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1837#ifdef VBOX_STRICT
1838 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1839#endif
1840
1841 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1842 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1843 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1844 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1845 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1846 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1847#ifdef VBOX_STRICT
1848 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1849#endif
1850
1851 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
1852 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
1853 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
1854 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
1855 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
1856 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
1857#ifdef VBOX_STRICT
1858 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
1859#endif
1860 /** @} */
1861} PGMMODEDATA, *PPGMMODEDATA;
1862
1863
1864
1865/**
1866 * Converts a PGM pointer into a VM pointer.
1867 * @returns Pointer to the VM structure the PGM is part of.
1868 * @param pPGM Pointer to PGM instance data.
1869 */
1870#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
1871
1872/**
1873 * PGM Data (part of VM)
1874 */
1875typedef struct PGM
1876{
1877 /** Offset to the VM structure. */
1878 RTINT offVM;
1879
1880 /*
1881 * This will be redefined at least two more times before we're done, I'm sure.
1882 * The current code is only to get on with the coding.
1883 * - 2004-06-10: initial version, bird.
1884 * - 2004-07-02: 1st time, bird.
1885 * - 2004-10-18: 2nd time, bird.
1886 * - 2005-07-xx: 3rd time, bird.
1887 */
1888
1889 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1890 GCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
1891 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
1892 GCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
1893
1894 /** The host paging mode. (This is what SUPLib reports.) */
1895 SUPPAGINGMODE enmHostMode;
1896 /** The shadow paging mode. */
1897 PGMMODE enmShadowMode;
1898 /** The guest paging mode. */
1899 PGMMODE enmGuestMode;
1900
1901 /** The current physical address representing in the guest CR3 register. */
1902 RTGCPHYS GCPhysCR3;
1903 /** Pointer to the 5 page CR3 content mapping.
1904 * The first page is always the CR3 (in some form) while the 4 other pages
1905 * are used of the PDs in PAE mode. */
1906 RTGCPTR GCPtrCR3Mapping;
1907#if HC_ARCH_BITS == 64
1908 uint32_t u32Alignment;
1909#endif
1910 /** The physical address of the currently monitored guest CR3 page.
1911 * When this value is NIL_RTGCPHYS no page is being monitored. */
1912 RTGCPHYS GCPhysGstCR3Monitored;
1913
1914 /** @name 32-bit Guest Paging.
1915 * @{ */
1916 /** The guest's page directory, HC pointer. */
1917 R3R0PTRTYPE(PX86PD) pGuestPDHC;
1918 /** The guest's page directory, static GC mapping. */
1919 GCPTRTYPE(PX86PD) pGuestPDGC;
1920 /** @} */
1921
1922 /** @name PAE Guest Paging.
1923 * @{ */
1924 /** The guest's page directory pointer table, static GC mapping. */
1925 GCPTRTYPE(PX86PDPT) pGstPaePDPTGC;
1926 /** The guest's page directory pointer table, HC pointer. */
1927 R3R0PTRTYPE(PX86PDPT) pGstPaePDPTHC;
1928 /** The guest's page directories, HC pointers.
1929 * These are individual pointers and don't have to be adjecent.
1930 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1931 R3R0PTRTYPE(PX86PDPAE) apGstPaePDsHC[4];
1932 /** The guest's page directories, static GC mapping.
1933 * Unlike the HC array the first entry can be accessed as a 2048 entry PD.
1934 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
1935 GCPTRTYPE(PX86PDPAE) apGstPaePDsGC[4];
1936 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
1937 RTGCPHYS aGCPhysGstPaePDs[4];
1938 /** The physical addresses of the monitored guest page directories (PAE). */
1939 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
1940 /** @} */
1941
1942
1943 /** @name 32-bit Shadow Paging
1944 * @{ */
1945 /** The 32-Bit PD - HC Ptr. */
1946 R3R0PTRTYPE(PX86PD) pHC32BitPD;
1947 /** The 32-Bit PD - GC Ptr. */
1948 GCPTRTYPE(PX86PD) pGC32BitPD;
1949#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1950 uint32_t u32Padding1; /**< alignment padding. */
1951#endif
1952 /** The Physical Address (HC) of the 32-Bit PD. */
1953 RTHCPHYS HCPhys32BitPD;
1954 /** @} */
1955
1956 /** @name PAE Shadow Paging
1957 * @{ */
1958 /** The four PDs for the low 4GB - HC Ptr.
1959 * Even though these are 4 pointers, what they point at is a single table.
1960 * Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
1961 R3R0PTRTYPE(PX86PDPAE) apHCPaePDs[4];
1962 /** The four PDs for the low 4GB - GC Ptr.
1963 * Same kind of mapping as apHCPaePDs. */
1964 GCPTRTYPE(PX86PDPAE) apGCPaePDs[4];
1965 /** The Physical Address (HC) of the four PDs for the low 4GB.
1966 * These are *NOT* 4 contiguous pages. */
1967 RTHCPHYS aHCPhysPaePDs[4];
1968 /** The PAE PDP - HC Ptr. */
1969 R3R0PTRTYPE(PX86PDPT) pHCPaePDPT;
1970 /** The Physical Address (HC) of the PAE PDPT. */
1971 RTHCPHYS HCPhysPaePDPT;
1972 /** The PAE PDPT - GC Ptr. */
1973 GCPTRTYPE(PX86PDPT) pGCPaePDPT;
1974 /** @} */
1975
1976 /** @name AMD64 Shadow Paging
1977 * Extends PAE Paging.
1978 * @{ */
1979 /** The Page Map Level 4 table - HC Ptr. */
1980 R3R0PTRTYPE(PX86PML4) pHCPaePML4;
1981 /** The Physical Address (HC) of the Page Map Level 4 table. */
1982 RTHCPHYS HCPhysPaePML4;
1983 /** @}*/
1984
1985 /** @name Function pointers for Shadow paging.
1986 * @{
1987 */
1988 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCUINTPTR offDelta));
1989 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
1990 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1991 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1992 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1993 DECLR3CALLBACKMEMBER(int, pfnR3ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
1994 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
1995
1996 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
1997 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
1998 DECLGCCALLBACKMEMBER(int, pfnGCShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
1999 DECLGCCALLBACKMEMBER(int, pfnGCShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
2000 DECLGCCALLBACKMEMBER(int, pfnGCShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
2001#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2002 RTGCPTR alignment0; /**< structure size alignment. */
2003#endif
2004
2005 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2006 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2007 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPDEByIndex,(PVM pVM, uint32_t iPD, PX86PDEPAE pPde));
2008 DECLR0CALLBACKMEMBER(int, pfnR0ShwSetPDEByIndex,(PVM pVM, uint32_t iPD, X86PDEPAE Pde));
2009 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPDEByIndex,(PVM pVM, uint32_t iPD, uint64_t fFlags, uint64_t fMask));
2010
2011 /** @} */
2012
2013 /** @name Function pointers for Guest paging.
2014 * @{
2015 */
2016 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2017 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2018 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2019 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2020 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2021 DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2022 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2023 DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2024 DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2025 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2026 R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2027 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2028 R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2029
2030 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2031 DECLGCCALLBACKMEMBER(int, pfnGCGstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2032 DECLGCCALLBACKMEMBER(int, pfnGCGstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2033 DECLGCCALLBACKMEMBER(int, pfnGCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2034 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmonitorCR3,(PVM pVM));
2035 DECLGCCALLBACKMEMBER(int, pfnGCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2036 DECLGCCALLBACKMEMBER(int, pfnGCGstUnmapCR3,(PVM pVM));
2037 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstWriteHandlerCR3;
2038 GCPTRTYPE(PFNPGMGCPHYSHANDLER) pfnGCGstPAEWriteHandlerCR3;
2039#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2040 RTGCPTR alignment3; /**< structure size alignment. */
2041#endif
2042
2043 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2044 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2045 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPde));
2046 DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2047 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2048 DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2049 DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2050 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2051 R0PTRTYPE(PFNPGMGCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2052 /** @} */
2053
2054 /** @name Function pointers for Both Shadow and Guest paging.
2055 * @{
2056 */
2057 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCUINTPTR offDelta));
2058 DECLR3CALLBACKMEMBER(int, pfnR3BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2059 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2060 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2061 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2062 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2063 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2064 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2065
2066 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2067 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2068 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2069 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2070 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2071 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2072 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2073
2074 DECLGCCALLBACKMEMBER(int, pfnGCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2075 DECLGCCALLBACKMEMBER(int, pfnGCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2076 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2077 DECLGCCALLBACKMEMBER(int, pfnGCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uError));
2078 DECLGCCALLBACKMEMBER(int, pfnGCBthPrefetchPage,(PVM pVM, RTGCUINTPTR GCPtrPage));
2079 DECLGCCALLBACKMEMBER(int, pfnGCBthVerifyAccessSyncPage,(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fFlags, unsigned uError));
2080 DECLGCCALLBACKMEMBER(unsigned, pfnGCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb));
2081#if GC_ARCH_BITS == 32 && HC_ARCH_BITS == 64
2082 RTGCPTR alignment2; /**< structure size alignment. */
2083#endif
2084 /** @} */
2085
2086 /** Pointer to SHW+GST mode data (function pointers).
2087 * The index into this table is made up from */
2088 R3PTRTYPE(PPGMMODEDATA) paModeData;
2089
2090 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2091 * This is sorted by physical address and contains no overlapping ranges. */
2092 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2093 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2094 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2095 /** GC pointer corresponding to PGM::pRamRangesR3. */
2096 GCPTRTYPE(PPGMRAMRANGE) pRamRangesGC;
2097 /** The configured RAM size. */
2098 RTUINT cbRamSize;
2099
2100 /** Pointer to the list of ROM ranges - for R3.
2101 * This is sorted by physical address and contains no overlapping ranges. */
2102 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2103 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2104 R0PTRTYPE(PPGMRAMRANGE) pRomRangesR0;
2105 /** GC pointer corresponding to PGM::pRomRangesR3. */
2106 GCPTRTYPE(PPGMRAMRANGE) pRomRangesGC;
2107 /** Alignment padding. */
2108 RTGCPTR GCPtrPadding2;
2109
2110 /** Pointer to the list of MMIO2 ranges - for R3.
2111 * Registration order. */
2112 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2113
2114 /** PGM offset based trees - HC Ptr. */
2115 R3R0PTRTYPE(PPGMTREES) pTreesHC;
2116 /** PGM offset based trees - GC Ptr. */
2117 GCPTRTYPE(PPGMTREES) pTreesGC;
2118
2119 /** Linked list of GC mappings - for GC.
2120 * The list is sorted ascending on address.
2121 */
2122 GCPTRTYPE(PPGMMAPPING) pMappingsGC;
2123 /** Linked list of GC mappings - for HC.
2124 * The list is sorted ascending on address.
2125 */
2126 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2127 /** Linked list of GC mappings - for R0.
2128 * The list is sorted ascending on address.
2129 */
2130 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2131
2132 /** If set no conflict checks are required. (boolean) */
2133 bool fMappingsFixed;
2134 /** If set, then no mappings are put into the shadow page table. (boolean) */
2135 bool fDisableMappings;
2136 /** Size of fixed mapping */
2137 uint32_t cbMappingFixed;
2138 /** Base address (GC) of fixed mapping */
2139 RTGCPTR GCPtrMappingFixed;
2140#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2141 uint32_t u32Padding0; /**< alignment padding. */
2142#endif
2143
2144
2145 /** @name Intermediate Context
2146 * @{ */
2147 /** Pointer to the intermediate page directory - Normal. */
2148 R3PTRTYPE(PX86PD) pInterPD;
2149 /** Pointer to the intermedate page tables - Normal.
2150 * There are two page tables, one for the identity mapping and one for
2151 * the host context mapping (of the core code). */
2152 R3PTRTYPE(PX86PT) apInterPTs[2];
2153 /** Pointer to the intermedate page tables - PAE. */
2154 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2155 /** Pointer to the intermedate page directory - PAE. */
2156 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2157 /** Pointer to the intermedate page directory - PAE. */
2158 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2159 /** Pointer to the intermedate page-map level 4 - AMD64. */
2160 R3PTRTYPE(PX86PML4) pInterPaePML4;
2161 /** Pointer to the intermedate page directory - AMD64. */
2162 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2163 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2164 RTHCPHYS HCPhysInterPD;
2165 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2166 RTHCPHYS HCPhysInterPaePDPT;
2167 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2168 RTHCPHYS HCPhysInterPaePML4;
2169 /** @} */
2170
2171 /** Base address of the dynamic page mapping area.
2172 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2173 */
2174 GCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2175 /** The index of the last entry used in the dynamic page mapping area. */
2176 RTUINT iDynPageMapLast;
2177 /** Cache containing the last entries in the dynamic page mapping area.
2178 * The cache size is covering half of the mapping area. */
2179 RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2180
2181 /** A20 gate mask.
2182 * Our current approach to A20 emulation is to let REM do it and don't bother
2183 * anywhere else. The interesting Guests will be operating with it enabled anyway.
2184 * But whould need arrise, we'll subject physical addresses to this mask. */
2185 RTGCPHYS GCPhysA20Mask;
2186 /** A20 gate state - boolean! */
2187 RTUINT fA20Enabled;
2188
2189 /** What needs syncing (PGM_SYNC_*).
2190 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2191 * PGMFlushTLB, and PGMR3Load. */
2192 RTUINT fSyncFlags;
2193
2194 /** PGM critical section.
2195 * This protects the physical & virtual access handlers, ram ranges,
2196 * and the page flag updating (some of it anyway).
2197 */
2198 PDMCRITSECT CritSect;
2199
2200 /** Shadow Page Pool - HC Ptr. */
2201 R3R0PTRTYPE(PPGMPOOL) pPoolHC;
2202 /** Shadow Page Pool - GC Ptr. */
2203 GCPTRTYPE(PPGMPOOL) pPoolGC;
2204
2205 /** We're not in a state which permits writes to guest memory.
2206 * (Only used in strict builds.) */
2207 bool fNoMorePhysWrites;
2208
2209 /** Flush the cache on the next access. */
2210 bool fPhysCacheFlushPending;
2211/** @todo r=bird: Fix member names!*/
2212 /** PGMPhysRead cache */
2213 PGMPHYSCACHE pgmphysreadcache;
2214 /** PGMPhysWrite cache */
2215 PGMPHYSCACHE pgmphyswritecache;
2216
2217 /**
2218 * Data associated with managing the ring-3 mappings of the allocation chunks.
2219 */
2220 struct
2221 {
2222 /** The chunk tree, ordered by chunk id. */
2223 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2224 /** The chunk mapping TLB. */
2225 PGMCHUNKR3MAPTLB Tlb;
2226 /** The number of mapped chunks. */
2227 uint32_t c;
2228 /** The maximum number of mapped chunks.
2229 * @cfgm PGM/MaxRing3Chunks */
2230 uint32_t cMax;
2231 /** The chunk age tree, ordered by ageing sequence number. */
2232 R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2233 /** The current time. */
2234 uint32_t iNow;
2235 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2236 uint32_t AgeingCountdown;
2237 } ChunkR3Map;
2238
2239 /**
2240 * The page mapping TLB for ring-3 and (for the time being) ring-0.
2241 */
2242 PGMPAGER3MAPTLB PhysTlbHC;
2243
2244 /** @name The zero page.
2245 * @{ */
2246 /** The host physical address of the zero page. */
2247 RTHCPHYS HCPhysZeroPg;
2248 /** The ring-3 mapping of the zero page. */
2249 RTR3PTR pvZeroPgR3;
2250 /** The ring-0 mapping of the zero page. */
2251 RTR0PTR pvZeroPgR0;
2252 /** The GC mapping of the zero page. */
2253 RTGCPTR pvZeroPgGC;
2254#if GC_ARCH_BITS != 32
2255 uint32_t u32ZeroAlignment; /**< Alignment padding. */
2256#endif
2257 /** @}*/
2258
2259 /** The number of handy pages. */
2260 uint32_t cHandyPages;
2261 /**
2262 * Array of handy pages.
2263 *
2264 * This array is used in a two way communication between pgmPhysAllocPage
2265 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2266 * an intermediary.
2267 *
2268 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
2269 * (The current size of 32 pages, means 128 KB of handy memory.)
2270 */
2271 GMMPAGEDESC aHandyPages[32];
2272
2273 /** @name Release Statistics
2274 * @{ */
2275 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero.) */
2276 uint32_t cPrivatePages; /**< The number of private pages. */
2277 uint32_t cSharedPages; /**< The number of shared pages. */
2278 uint32_t cZeroPages; /**< The number of zero backed pages. */
2279 /** The number of times the guest has switched mode since last reset or statistics reset. */
2280 STAMCOUNTER cGuestModeChanges;
2281 /** @} */
2282
2283#ifdef VBOX_WITH_STATISTICS
2284 /** GC: Which statistic this \#PF should be attributed to. */
2285 GCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionGC;
2286 RTGCPTR padding0;
2287 /** HC: Which statistic this \#PF should be attributed to. */
2288 R3R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionHC;
2289 RTHCPTR padding1;
2290 STAMPROFILE StatGCTrap0e; /**< GC: PGMGCTrap0eHandler() profiling. */
2291 STAMPROFILE StatTrap0eCSAM; /**< Profiling of the Trap0eHandler body when the cause is CSAM. */
2292 STAMPROFILE StatTrap0eDirtyAndAccessedBits; /**< Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
2293 STAMPROFILE StatTrap0eGuestTrap; /**< Profiling of the Trap0eHandler body when the cause is a guest trap. */
2294 STAMPROFILE StatTrap0eHndPhys; /**< Profiling of the Trap0eHandler body when the cause is a physical handler. */
2295 STAMPROFILE StatTrap0eHndVirt; /**< Profiling of the Trap0eHandler body when the cause is a virtual handler. */
2296 STAMPROFILE StatTrap0eHndUnhandled; /**< Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
2297 STAMPROFILE StatTrap0eMisc; /**< Profiling of the Trap0eHandler body when the cause is not known. */
2298 STAMPROFILE StatTrap0eOutOfSync; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
2299 STAMPROFILE StatTrap0eOutOfSyncHndPhys; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
2300 STAMPROFILE StatTrap0eOutOfSyncHndVirt; /**< Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
2301 STAMPROFILE StatTrap0eOutOfSyncObsHnd; /**< Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
2302 STAMPROFILE StatTrap0eSyncPT; /**< Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
2303
2304 STAMCOUNTER StatTrap0eMapHandler; /**< Number of traps due to access handlers in mappings. */
2305 STAMCOUNTER StatGCTrap0eConflicts; /**< GC: The number of times \#PF was caused by an undetected conflict. */
2306
2307 STAMCOUNTER StatGCTrap0eUSNotPresentRead;
2308 STAMCOUNTER StatGCTrap0eUSNotPresentWrite;
2309 STAMCOUNTER StatGCTrap0eUSWrite;
2310 STAMCOUNTER StatGCTrap0eUSReserved;
2311 STAMCOUNTER StatGCTrap0eUSNXE;
2312 STAMCOUNTER StatGCTrap0eUSRead;
2313
2314 STAMCOUNTER StatGCTrap0eSVNotPresentRead;
2315 STAMCOUNTER StatGCTrap0eSVNotPresentWrite;
2316 STAMCOUNTER StatGCTrap0eSVWrite;
2317 STAMCOUNTER StatGCTrap0eSVReserved;
2318 STAMCOUNTER StatGCTrap0eSNXE;
2319
2320 STAMCOUNTER StatTrap0eWPEmulGC;
2321 STAMCOUNTER StatTrap0eWPEmulR3;
2322
2323 STAMCOUNTER StatGCTrap0eUnhandled;
2324 STAMCOUNTER StatGCTrap0eMap;
2325
2326 /** GC: PGMSyncPT() profiling. */
2327 STAMPROFILE StatGCSyncPT;
2328 /** GC: The number of times PGMSyncPT() needed to allocate page tables. */
2329 STAMCOUNTER StatGCSyncPTAlloc;
2330 /** GC: The number of times PGMSyncPT() detected conflicts. */
2331 STAMCOUNTER StatGCSyncPTConflict;
2332 /** GC: The number of times PGMSyncPT() failed. */
2333 STAMCOUNTER StatGCSyncPTFailed;
2334 /** GC: PGMGCInvalidatePage() profiling. */
2335 STAMPROFILE StatGCInvalidatePage;
2336 /** GC: The number of times PGMGCInvalidatePage() was called for a 4KB page. */
2337 STAMCOUNTER StatGCInvalidatePage4KBPages;
2338 /** GC: The number of times PGMGCInvalidatePage() was called for a 4MB page. */
2339 STAMCOUNTER StatGCInvalidatePage4MBPages;
2340 /** GC: The number of times PGMGCInvalidatePage() skipped a 4MB page. */
2341 STAMCOUNTER StatGCInvalidatePage4MBPagesSkip;
2342 /** GC: The number of times PGMGCInvalidatePage() was called for a not accessed page directory. */
2343 STAMCOUNTER StatGCInvalidatePagePDNAs;
2344 /** GC: The number of times PGMGCInvalidatePage() was called for a not present page directory. */
2345 STAMCOUNTER StatGCInvalidatePagePDNPs;
2346 /** GC: The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict). */
2347 STAMCOUNTER StatGCInvalidatePagePDMappings;
2348 /** GC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2349 STAMCOUNTER StatGCInvalidatePagePDOutOfSync;
2350 /** HC: The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2351 STAMCOUNTER StatGCInvalidatePageSkipped;
2352 /** GC: The number of times user page is out of sync was detected in GC. */
2353 STAMCOUNTER StatGCPageOutOfSyncUser;
2354 /** GC: The number of times supervisor page is out of sync was detected in GC. */
2355 STAMCOUNTER StatGCPageOutOfSyncSupervisor;
2356 /** GC: The number of dynamic page mapping cache hits */
2357 STAMCOUNTER StatDynMapCacheMisses;
2358 /** GC: The number of dynamic page mapping cache misses */
2359 STAMCOUNTER StatDynMapCacheHits;
2360 /** GC: The number of times pgmGCGuestPDWriteHandler() was successfully called. */
2361 STAMCOUNTER StatGCGuestCR3WriteHandled;
2362 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and we had to fall back to the recompiler. */
2363 STAMCOUNTER StatGCGuestCR3WriteUnhandled;
2364 /** GC: The number of times pgmGCGuestPDWriteHandler() was called and a conflict was detected. */
2365 STAMCOUNTER StatGCGuestCR3WriteConflict;
2366 /** GC: Number of out-of-sync handled pages. */
2367 STAMCOUNTER StatHandlersOutOfSync;
2368 /** GC: Number of traps due to physical access handlers. */
2369 STAMCOUNTER StatHandlersPhysical;
2370 /** GC: Number of traps due to virtual access handlers. */
2371 STAMCOUNTER StatHandlersVirtual;
2372 /** GC: Number of traps due to virtual access handlers found by physical address. */
2373 STAMCOUNTER StatHandlersVirtualByPhys;
2374 /** GC: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
2375 STAMCOUNTER StatHandlersVirtualUnmarked;
2376 /** GC: Number of traps due to access outside range of monitored page(s). */
2377 STAMCOUNTER StatHandlersUnhandled;
2378
2379 /** GC: The number of times pgmGCGuestROMWriteHandler() was successfully called. */
2380 STAMCOUNTER StatGCGuestROMWriteHandled;
2381 /** GC: The number of times pgmGCGuestROMWriteHandler() was called and we had to fall back to the recompiler */
2382 STAMCOUNTER StatGCGuestROMWriteUnhandled;
2383
2384 /** HC: PGMR3InvalidatePage() profiling. */
2385 STAMPROFILE StatHCInvalidatePage;
2386 /** HC: The number of times PGMR3InvalidatePage() was called for a 4KB page. */
2387 STAMCOUNTER StatHCInvalidatePage4KBPages;
2388 /** HC: The number of times PGMR3InvalidatePage() was called for a 4MB page. */
2389 STAMCOUNTER StatHCInvalidatePage4MBPages;
2390 /** HC: The number of times PGMR3InvalidatePage() skipped a 4MB page. */
2391 STAMCOUNTER StatHCInvalidatePage4MBPagesSkip;
2392 /** HC: The number of times PGMR3InvalidatePage() was called for a not accessed page directory. */
2393 STAMCOUNTER StatHCInvalidatePagePDNAs;
2394 /** HC: The number of times PGMR3InvalidatePage() was called for a not present page directory. */
2395 STAMCOUNTER StatHCInvalidatePagePDNPs;
2396 /** HC: The number of times PGMR3InvalidatePage() was called for a page directory containing mappings (no conflict). */
2397 STAMCOUNTER StatHCInvalidatePagePDMappings;
2398 /** HC: The number of times PGMGCInvalidatePage() was called for an out of sync page directory. */
2399 STAMCOUNTER StatHCInvalidatePagePDOutOfSync;
2400 /** HC: The number of times PGMR3InvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
2401 STAMCOUNTER StatHCInvalidatePageSkipped;
2402 /** HC: PGMR3SyncPT() profiling. */
2403 STAMPROFILE StatHCSyncPT;
2404 /** HC: pgmr3SyncPTResolveConflict() profiling (includes the entire relocation). */
2405 STAMPROFILE StatHCResolveConflict;
2406 /** HC: Number of times PGMR3CheckMappingConflicts() detected a conflict. */
2407 STAMCOUNTER StatHCDetectedConflicts;
2408 /** HC: The total number of times pgmHCGuestPDWriteHandler() was called. */
2409 STAMCOUNTER StatHCGuestPDWrite;
2410 /** HC: The number of times pgmHCGuestPDWriteHandler() detected a conflict */
2411 STAMCOUNTER StatHCGuestPDWriteConflict;
2412
2413 /** HC: The number of pages marked not present for accessed bit emulation. */
2414 STAMCOUNTER StatHCAccessedPage;
2415 /** HC: The number of pages marked read-only for dirty bit tracking. */
2416 STAMCOUNTER StatHCDirtyPage;
2417 /** HC: The number of pages marked read-only for dirty bit tracking. */
2418 STAMCOUNTER StatHCDirtyPageBig;
2419 /** HC: The number of traps generated for dirty bit tracking. */
2420 STAMCOUNTER StatHCDirtyPageTrap;
2421 /** HC: The number of pages already dirty or readonly. */
2422 STAMCOUNTER StatHCDirtyPageSkipped;
2423
2424 /** GC: The number of pages marked not present for accessed bit emulation. */
2425 STAMCOUNTER StatGCAccessedPage;
2426 /** GC: The number of pages marked read-only for dirty bit tracking. */
2427 STAMCOUNTER StatGCDirtyPage;
2428 /** GC: The number of pages marked read-only for dirty bit tracking. */
2429 STAMCOUNTER StatGCDirtyPageBig;
2430 /** GC: The number of traps generated for dirty bit tracking. */
2431 STAMCOUNTER StatGCDirtyPageTrap;
2432 /** GC: The number of pages already dirty or readonly. */
2433 STAMCOUNTER StatGCDirtyPageSkipped;
2434 /** GC: The number of pages marked dirty because of write accesses. */
2435 STAMCOUNTER StatGCDirtiedPage;
2436 /** GC: The number of pages already marked dirty because of write accesses. */
2437 STAMCOUNTER StatGCPageAlreadyDirty;
2438 /** GC: The number of real pages faults during dirty bit tracking. */
2439 STAMCOUNTER StatGCDirtyTrackRealPF;
2440
2441 /** GC: Profiling of the PGMTrackDirtyBit() body */
2442 STAMPROFILE StatGCDirtyBitTracking;
2443 /** HC: Profiling of the PGMTrackDirtyBit() body */
2444 STAMPROFILE StatHCDirtyBitTracking;
2445
2446 /** GC: Profiling of the PGMGstModifyPage() body */
2447 STAMPROFILE StatGCGstModifyPage;
2448 /** HC: Profiling of the PGMGstModifyPage() body */
2449 STAMPROFILE StatHCGstModifyPage;
2450
2451 /** GC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2452 STAMCOUNTER StatGCSyncPagePDNAs;
2453 /** GC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2454 STAMCOUNTER StatGCSyncPagePDOutOfSync;
2455 /** HC: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
2456 STAMCOUNTER StatHCSyncPagePDNAs;
2457 /** HC: The number of time we've encountered an out-of-sync PD in SyncPage. */
2458 STAMCOUNTER StatHCSyncPagePDOutOfSync;
2459
2460 STAMCOUNTER StatSynPT4kGC;
2461 STAMCOUNTER StatSynPT4kHC;
2462 STAMCOUNTER StatSynPT4MGC;
2463 STAMCOUNTER StatSynPT4MHC;
2464
2465 /** Profiling of the PGMFlushTLB() body. */
2466 STAMPROFILE StatFlushTLB;
2467 /** The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
2468 STAMCOUNTER StatFlushTLBNewCR3;
2469 /** The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
2470 STAMCOUNTER StatFlushTLBNewCR3Global;
2471 /** The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
2472 STAMCOUNTER StatFlushTLBSameCR3;
2473 /** The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
2474 STAMCOUNTER StatFlushTLBSameCR3Global;
2475
2476 STAMPROFILE StatGCSyncCR3; /**< GC: PGMSyncCR3() profiling. */
2477 STAMPROFILE StatGCSyncCR3Handlers; /**< GC: Profiling of the PGMSyncCR3() update handler section. */
2478 STAMPROFILE StatGCSyncCR3HandlerVirtualReset; /**< GC: Profiling of the virtual handler resets. */
2479 STAMPROFILE StatGCSyncCR3HandlerVirtualUpdate; /**< GC: Profiling of the virtual handler updates. */
2480 STAMCOUNTER StatGCSyncCR3Global; /**< GC: The number of global CR3 syncs. */
2481 STAMCOUNTER StatGCSyncCR3NotGlobal; /**< GC: The number of non-global CR3 syncs. */
2482 STAMCOUNTER StatGCSyncCR3DstFreed; /**< GC: The number of times we've had to free a shadow entry. */
2483 STAMCOUNTER StatGCSyncCR3DstFreedSrcNP; /**< GC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2484 STAMCOUNTER StatGCSyncCR3DstNotPresent; /**< GC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2485 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPD; /**< GC: The number of times a global page directory wasn't flushed. */
2486 STAMCOUNTER StatGCSyncCR3DstSkippedGlobalPT; /**< GC: The number of times a page table with only global entries wasn't flushed. */
2487 STAMCOUNTER StatGCSyncCR3DstCacheHit; /**< GC: The number of times we got some kind of cache hit on a page table. */
2488
2489 STAMPROFILE StatHCSyncCR3; /**< HC: PGMSyncCR3() profiling. */
2490 STAMPROFILE StatHCSyncCR3Handlers; /**< HC: Profiling of the PGMSyncCR3() update handler section. */
2491 STAMPROFILE StatHCSyncCR3HandlerVirtualReset; /**< HC: Profiling of the virtual handler resets. */
2492 STAMPROFILE StatHCSyncCR3HandlerVirtualUpdate; /**< HC: Profiling of the virtual handler updates. */
2493 STAMCOUNTER StatHCSyncCR3Global; /**< HC: The number of global CR3 syncs. */
2494 STAMCOUNTER StatHCSyncCR3NotGlobal; /**< HC: The number of non-global CR3 syncs. */
2495 STAMCOUNTER StatHCSyncCR3DstFreed; /**< HC: The number of times we've had to free a shadow entry. */
2496 STAMCOUNTER StatHCSyncCR3DstFreedSrcNP; /**< HC: The number of times we've had to free a shadow entry for which the source entry was not present. */
2497 STAMCOUNTER StatHCSyncCR3DstNotPresent; /**< HC: The number of times we've encountered a not present shadow entry for a present guest entry. */
2498 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPD; /**< HC: The number of times a global page directory wasn't flushed. */
2499 STAMCOUNTER StatHCSyncCR3DstSkippedGlobalPT; /**< HC: The number of times a page table with only global entries wasn't flushed. */
2500 STAMCOUNTER StatHCSyncCR3DstCacheHit; /**< HC: The number of times we got some kind of cache hit on a page table. */
2501
2502 /** GC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2503 STAMPROFILE StatVirtHandleSearchByPhysGC;
2504 /** HC: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2505 STAMPROFILE StatVirtHandleSearchByPhysHC;
2506 /** HC: The number of times PGMR3HandlerPhysicalReset is called. */
2507 STAMCOUNTER StatHandlePhysicalReset;
2508
2509 STAMPROFILE StatCheckPageFault;
2510 STAMPROFILE StatLazySyncPT;
2511 STAMPROFILE StatMapping;
2512 STAMPROFILE StatOutOfSync;
2513 STAMPROFILE StatHandlers;
2514 STAMPROFILE StatEIPHandlers;
2515 STAMPROFILE StatHCPrefetch;
2516
2517# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2518 /** The number of first time shadowings. */
2519 STAMCOUNTER StatTrackVirgin;
2520 /** The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2521 STAMCOUNTER StatTrackAliased;
2522 /** The number of times we're tracking using cRef2. */
2523 STAMCOUNTER StatTrackAliasedMany;
2524 /** The number of times we're hitting pages which has overflowed cRef2. */
2525 STAMCOUNTER StatTrackAliasedLots;
2526 /** The number of times the extent list grows to long. */
2527 STAMCOUNTER StatTrackOverflows;
2528 /** Profiling of SyncPageWorkerTrackDeref (expensive). */
2529 STAMPROFILE StatTrackDeref;
2530# endif
2531
2532 /** Ring-3/0 page mapper TLB hits. */
2533 STAMCOUNTER StatPageHCMapTlbHits;
2534 /** Ring-3/0 page mapper TLB misses. */
2535 STAMCOUNTER StatPageHCMapTlbMisses;
2536 /** Ring-3/0 chunk mapper TLB hits. */
2537 STAMCOUNTER StatChunkR3MapTlbHits;
2538 /** Ring-3/0 chunk mapper TLB misses. */
2539 STAMCOUNTER StatChunkR3MapTlbMisses;
2540 /** Times a shared page has been replaced by a private one. */
2541 STAMCOUNTER StatPageReplaceShared;
2542 /** Times the zero page has been replaced by a private one. */
2543 STAMCOUNTER StatPageReplaceZero;
2544 /** The number of times we've executed GMMR3AllocateHandyPages. */
2545 STAMCOUNTER StatPageHandyAllocs;
2546
2547 /** Allocated mbs of guest ram */
2548 STAMCOUNTER StatDynRamTotal;
2549 /** Nr of pgmr3PhysGrowRange calls. */
2550 STAMCOUNTER StatDynRamGrow;
2551
2552 STAMCOUNTER StatGCTrap0ePD[X86_PG_ENTRIES];
2553 STAMCOUNTER StatGCSyncPtPD[X86_PG_ENTRIES];
2554 STAMCOUNTER StatGCSyncPagePD[X86_PG_ENTRIES];
2555#endif
2556} PGM, *PPGM;
2557
2558
2559/** @name PGM::fSyncFlags Flags
2560 * @{
2561 */
2562/** Updates the virtual access handler state bit in PGMPAGE. */
2563#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2564/** Always sync CR3. */
2565#define PGM_SYNC_ALWAYS RT_BIT(1)
2566/** Check monitoring on next CR3 (re)load and invalidate page. */
2567#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2568/** Clear the page pool (a light weight flush). */
2569#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2570/** @} */
2571
2572
2573__BEGIN_DECLS
2574
2575int pgmLock(PVM pVM);
2576void pgmUnlock(PVM pVM);
2577
2578PGMGCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2579PGMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void *pvFault, RTGCPHYS GCPhysFault, void *pvUser);
2580int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode);
2581
2582int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2583int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2584PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2585void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2586DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2587
2588void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2589int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
2590DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2591#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
2592void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2593#else
2594# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2595#endif
2596DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2597
2598
2599void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2600int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2601int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2602int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2603#ifdef IN_RING3
2604int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2605int pgmR3PhysRamReset(PVM pVM);
2606int pgmR3PhysRomReset(PVM pVM);
2607#ifndef VBOX_WITH_NEW_PHYS_CODE
2608int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2609#endif
2610
2611int pgmR3PoolInit(PVM pVM);
2612void pgmR3PoolRelocate(PVM pVM);
2613void pgmR3PoolReset(PVM pVM);
2614
2615#endif /* IN_RING3 */
2616#ifdef IN_GC
2617void *pgmGCPoolMapPage(PVM pVM, PPGMPOOLPAGE pPage);
2618#endif
2619int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint16_t iUserTable, PPPGMPOOLPAGE ppPage);
2620PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2621void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint16_t iUserTable);
2622void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint16_t iUserTable);
2623int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2624void pgmPoolFlushAll(PVM pVM);
2625void pgmPoolClearAll(PVM pVM);
2626void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2627void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2628int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2629PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2630void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2631void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2632uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2633void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2634#ifdef PGMPOOL_WITH_MONITORING
2635# ifdef IN_RING3
2636void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2637# else
2638void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2639# endif
2640int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2641void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2642void pgmPoolMonitorModifiedClearAll(PVM pVM);
2643int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2644int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2645#endif
2646
2647__END_DECLS
2648
2649
2650/**
2651 * Gets the PGMRAMRANGE structure for a guest page.
2652 *
2653 * @returns Pointer to the RAM range on success.
2654 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2655 *
2656 * @param pPGM PGM handle.
2657 * @param GCPhys The GC physical address.
2658 */
2659DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2660{
2661 /*
2662 * Optimize for the first range.
2663 */
2664 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2665 RTGCPHYS off = GCPhys - pRam->GCPhys;
2666 if (RT_UNLIKELY(off >= pRam->cb))
2667 {
2668 do
2669 {
2670 pRam = CTXALLSUFF(pRam->pNext);
2671 if (RT_UNLIKELY(!pRam))
2672 break;
2673 off = GCPhys - pRam->GCPhys;
2674 } while (off >= pRam->cb);
2675 }
2676 return pRam;
2677}
2678
2679
2680/**
2681 * Gets the PGMPAGE structure for a guest page.
2682 *
2683 * @returns Pointer to the page on success.
2684 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2685 *
2686 * @param pPGM PGM handle.
2687 * @param GCPhys The GC physical address.
2688 */
2689DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
2690{
2691 /*
2692 * Optimize for the first range.
2693 */
2694 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2695 RTGCPHYS off = GCPhys - pRam->GCPhys;
2696 if (RT_UNLIKELY(off >= pRam->cb))
2697 {
2698 do
2699 {
2700 pRam = CTXALLSUFF(pRam->pNext);
2701 if (RT_UNLIKELY(!pRam))
2702 return NULL;
2703 off = GCPhys - pRam->GCPhys;
2704 } while (off >= pRam->cb);
2705 }
2706 return &pRam->aPages[off >> PAGE_SHIFT];
2707}
2708
2709
2710/**
2711 * Gets the PGMPAGE structure for a guest page.
2712 *
2713 * Old Phys code: Will make sure the page is present.
2714 *
2715 * @returns VBox status code.
2716 * @retval VINF_SUCCESS and a valid *ppPage on success.
2717 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2718 *
2719 * @param pPGM PGM handle.
2720 * @param GCPhys The GC physical address.
2721 * @param ppPage Where to store the page poitner on success.
2722 */
2723DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
2724{
2725 /*
2726 * Optimize for the first range.
2727 */
2728 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2729 RTGCPHYS off = GCPhys - pRam->GCPhys;
2730 if (RT_UNLIKELY(off >= pRam->cb))
2731 {
2732 do
2733 {
2734 pRam = CTXALLSUFF(pRam->pNext);
2735 if (RT_UNLIKELY(!pRam))
2736 {
2737 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2738 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2739 }
2740 off = GCPhys - pRam->GCPhys;
2741 } while (off >= pRam->cb);
2742 }
2743 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2744#ifndef VBOX_WITH_NEW_PHYS_CODE
2745
2746 /*
2747 * Make sure it's present.
2748 */
2749 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2750 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2751 {
2752#ifdef IN_RING3
2753 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2754#else
2755 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2756#endif
2757 if (VBOX_FAILURE(rc))
2758 {
2759 *ppPage = NULL; /* avoid incorrect and very annoying GCC warnings */
2760 return rc;
2761 }
2762 Assert(rc == VINF_SUCCESS);
2763 }
2764#endif
2765 return VINF_SUCCESS;
2766}
2767
2768
2769
2770
2771/**
2772 * Gets the PGMPAGE structure for a guest page.
2773 *
2774 * Old Phys code: Will make sure the page is present.
2775 *
2776 * @returns VBox status code.
2777 * @retval VINF_SUCCESS and a valid *ppPage on success.
2778 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
2779 *
2780 * @param pPGM PGM handle.
2781 * @param GCPhys The GC physical address.
2782 * @param ppPage Where to store the page poitner on success.
2783 * @param ppRamHint Where to read and store the ram list hint.
2784 * The caller initializes this to NULL before the call.
2785 */
2786DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
2787{
2788 RTGCPHYS off;
2789 PPGMRAMRANGE pRam = *ppRamHint;
2790 if ( !pRam
2791 || RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
2792 {
2793 pRam = CTXALLSUFF(pPGM->pRamRanges);
2794 off = GCPhys - pRam->GCPhys;
2795 if (RT_UNLIKELY(off >= pRam->cb))
2796 {
2797 do
2798 {
2799 pRam = CTXALLSUFF(pRam->pNext);
2800 if (RT_UNLIKELY(!pRam))
2801 {
2802 *ppPage = NULL; /* Kill the incorrect and extremely annoying GCC warnings. */
2803 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2804 }
2805 off = GCPhys - pRam->GCPhys;
2806 } while (off >= pRam->cb);
2807 }
2808 *ppRamHint = pRam;
2809 }
2810 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2811#ifndef VBOX_WITH_NEW_PHYS_CODE
2812
2813 /*
2814 * Make sure it's present.
2815 */
2816 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2817 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2818 {
2819#ifdef IN_RING3
2820 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2821#else
2822 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2823#endif
2824 if (VBOX_FAILURE(rc))
2825 {
2826 *ppPage = NULL; /* Shut up annoying smart ass. */
2827 return rc;
2828 }
2829 Assert(rc == VINF_SUCCESS);
2830 }
2831#endif
2832 return VINF_SUCCESS;
2833}
2834
2835
2836/**
2837 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2838 *
2839 * @returns Pointer to the page on success.
2840 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2841 *
2842 * @param pPGM PGM handle.
2843 * @param GCPhys The GC physical address.
2844 * @param ppRam Where to store the pointer to the PGMRAMRANGE.
2845 */
2846DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
2847{
2848 /*
2849 * Optimize for the first range.
2850 */
2851 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2852 RTGCPHYS off = GCPhys - pRam->GCPhys;
2853 if (RT_UNLIKELY(off >= pRam->cb))
2854 {
2855 do
2856 {
2857 pRam = CTXALLSUFF(pRam->pNext);
2858 if (RT_UNLIKELY(!pRam))
2859 return NULL;
2860 off = GCPhys - pRam->GCPhys;
2861 } while (off >= pRam->cb);
2862 }
2863 *ppRam = pRam;
2864 return &pRam->aPages[off >> PAGE_SHIFT];
2865}
2866
2867
2868
2869
2870/**
2871 * Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
2872 *
2873 * @returns Pointer to the page on success.
2874 * @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2875 *
2876 * @param pPGM PGM handle.
2877 * @param GCPhys The GC physical address.
2878 * @param ppPage Where to store the pointer to the PGMPAGE structure.
2879 * @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
2880 */
2881DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
2882{
2883 /*
2884 * Optimize for the first range.
2885 */
2886 PPGMRAMRANGE pRam = CTXALLSUFF(pPGM->pRamRanges);
2887 RTGCPHYS off = GCPhys - pRam->GCPhys;
2888 if (RT_UNLIKELY(off >= pRam->cb))
2889 {
2890 do
2891 {
2892 pRam = CTXALLSUFF(pRam->pNext);
2893 if (RT_UNLIKELY(!pRam))
2894 {
2895 *ppRam = NULL; /* Shut up silly GCC warnings. */
2896 *ppPage = NULL; /* ditto */
2897 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2898 }
2899 off = GCPhys - pRam->GCPhys;
2900 } while (off >= pRam->cb);
2901 }
2902 *ppRam = pRam;
2903 *ppPage = &pRam->aPages[off >> PAGE_SHIFT];
2904#ifndef VBOX_WITH_NEW_PHYS_CODE
2905
2906 /*
2907 * Make sure it's present.
2908 */
2909 if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
2910 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
2911 {
2912#ifdef IN_RING3
2913 int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
2914#else
2915 int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2916#endif
2917 if (VBOX_FAILURE(rc))
2918 {
2919 *ppPage = NULL; /* Shut up silly GCC warnings. */
2920 *ppPage = NULL; /* ditto */
2921 return rc;
2922 }
2923 Assert(rc == VINF_SUCCESS);
2924
2925 }
2926#endif
2927 return VINF_SUCCESS;
2928}
2929
2930
2931/**
2932 * Convert GC Phys to HC Phys.
2933 *
2934 * @returns VBox status.
2935 * @param pPGM PGM handle.
2936 * @param GCPhys The GC physical address.
2937 * @param pHCPhys Where to store the corresponding HC physical address.
2938 *
2939 * @deprecated Doesn't deal with zero, shared or write monitored pages.
2940 * Avoid when writing new code!
2941 */
2942DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
2943{
2944 PPGMPAGE pPage;
2945 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
2946 if (VBOX_FAILURE(rc))
2947 return rc;
2948 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) | (GCPhys & PAGE_OFFSET_MASK);
2949 return VINF_SUCCESS;
2950}
2951
2952
2953#ifndef IN_GC
2954/**
2955 * Queries the Physical TLB entry for a physical guest page,
2956 * attemting to load the TLB entry if necessary.
2957 *
2958 * @returns VBox status code.
2959 * @retval VINF_SUCCESS on success
2960 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
2961 * @param pPGM The PGM instance handle.
2962 * @param GCPhys The address of the guest page.
2963 * @param ppTlbe Where to store the pointer to the TLB entry.
2964 */
2965
2966DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
2967{
2968 int rc;
2969 PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
2970 if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
2971 {
2972 STAM_COUNTER_INC(&pPGM->CTXMID(StatPage,MapTlbHits));
2973 rc = VINF_SUCCESS;
2974 }
2975 else
2976 rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
2977 *ppTlbe = pTlbe;
2978 return rc;
2979}
2980#endif /* !IN_GC */
2981
2982
2983#ifndef VBOX_WITH_NEW_PHYS_CODE
2984/**
2985 * Convert GC Phys to HC Virt.
2986 *
2987 * @returns VBox status.
2988 * @param pPGM PGM handle.
2989 * @param GCPhys The GC physical address.
2990 * @param pHCPtr Where to store the corresponding HC virtual address.
2991 *
2992 * @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr.
2993 */
2994DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
2995{
2996 PPGMRAMRANGE pRam;
2997 PPGMPAGE pPage;
2998 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
2999 if (VBOX_FAILURE(rc))
3000 {
3001 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3002 return rc;
3003 }
3004 RTGCPHYS off = GCPhys - pRam->GCPhys;
3005
3006 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3007 {
3008 unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3009 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3010 return VINF_SUCCESS;
3011 }
3012 if (pRam->pvHC)
3013 {
3014 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3015 return VINF_SUCCESS;
3016 }
3017 *pHCPtr = 0; /* Shut up silly GCC warnings. */
3018 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3019}
3020#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3021
3022
3023/**
3024 * Convert GC Phys to HC Virt.
3025 *
3026 * @returns VBox status.
3027 * @param PVM VM handle.
3028 * @param pRam Ram range
3029 * @param GCPhys The GC physical address.
3030 * @param pHCPtr Where to store the corresponding HC virtual address.
3031 *
3032 * @deprecated This will be eliminated. Don't use it.
3033 */
3034DECLINLINE(int) pgmRamGCPhys2HCPtrWithRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3035{
3036 RTGCPHYS off = GCPhys - pRam->GCPhys;
3037 Assert(off < pRam->cb);
3038
3039 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3040 {
3041 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3042 /* Physical chunk in dynamically allocated range not present? */
3043 if (RT_UNLIKELY(!CTXSUFF(pRam->pavHCChunk)[idx]))
3044 {
3045#ifdef IN_RING3
3046 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
3047#else
3048 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3049#endif
3050 if (rc != VINF_SUCCESS)
3051 {
3052 *pHCPtr = 0; /* GCC crap */
3053 return rc;
3054 }
3055 }
3056 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3057 return VINF_SUCCESS;
3058 }
3059 if (pRam->pvHC)
3060 {
3061 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3062 return VINF_SUCCESS;
3063 }
3064 *pHCPtr = 0; /* GCC crap */
3065 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3066}
3067
3068
3069/**
3070 * Convert GC Phys to HC Virt and HC Phys.
3071 *
3072 * @returns VBox status.
3073 * @param pPGM PGM handle.
3074 * @param GCPhys The GC physical address.
3075 * @param pHCPtr Where to store the corresponding HC virtual address.
3076 * @param pHCPhys Where to store the HC Physical address and its flags.
3077 *
3078 * @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3079 * and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3080 */
3081DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3082{
3083 PPGMRAMRANGE pRam;
3084 PPGMPAGE pPage;
3085 int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3086 if (VBOX_FAILURE(rc))
3087 {
3088 *pHCPtr = 0; /* Shut up crappy GCC warnings */
3089 *pHCPhys = 0; /* ditto */
3090 return rc;
3091 }
3092 RTGCPHYS off = GCPhys - pRam->GCPhys;
3093
3094 *pHCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
3095 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3096 {
3097 unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3098 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3099 return VINF_SUCCESS;
3100 }
3101 if (pRam->pvHC)
3102 {
3103 *pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
3104 return VINF_SUCCESS;
3105 }
3106 *pHCPtr = 0;
3107 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3108}
3109
3110
3111/**
3112 * Clears flags associated with a RAM address.
3113 *
3114 * @returns VBox status code.
3115 * @param pPGM PGM handle.
3116 * @param GCPhys Guest context physical address.
3117 * @param fFlags fFlags to clear. (Bits 0-11.)
3118 */
3119DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3120{
3121 PPGMPAGE pPage;
3122 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3123 if (VBOX_FAILURE(rc))
3124 return rc;
3125
3126 fFlags &= ~X86_PTE_PAE_PG_MASK;
3127 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3128 return VINF_SUCCESS;
3129}
3130
3131
3132/**
3133 * Clears flags associated with a RAM address.
3134 *
3135 * @returns VBox status code.
3136 * @param pPGM PGM handle.
3137 * @param GCPhys Guest context physical address.
3138 * @param fFlags fFlags to clear. (Bits 0-11.)
3139 * @param ppRamHint Where to read and store the ram list hint.
3140 * The caller initializes this to NULL before the call.
3141 */
3142DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3143{
3144 PPGMPAGE pPage;
3145 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3146 if (VBOX_FAILURE(rc))
3147 return rc;
3148
3149 fFlags &= ~X86_PTE_PAE_PG_MASK;
3150 pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3151 return VINF_SUCCESS;
3152}
3153
3154/**
3155 * Sets (bitwise OR) flags associated with a RAM address.
3156 *
3157 * @returns VBox status code.
3158 * @param pPGM PGM handle.
3159 * @param GCPhys Guest context physical address.
3160 * @param fFlags fFlags to set clear. (Bits 0-11.)
3161 */
3162DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3163{
3164 PPGMPAGE pPage;
3165 int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3166 if (VBOX_FAILURE(rc))
3167 return rc;
3168
3169 fFlags &= ~X86_PTE_PAE_PG_MASK;
3170 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3171 return VINF_SUCCESS;
3172}
3173
3174
3175/**
3176 * Sets (bitwise OR) flags associated with a RAM address.
3177 *
3178 * @returns VBox status code.
3179 * @param pPGM PGM handle.
3180 * @param GCPhys Guest context physical address.
3181 * @param fFlags fFlags to set clear. (Bits 0-11.)
3182 * @param ppRamHint Where to read and store the ram list hint.
3183 * The caller initializes this to NULL before the call.
3184 */
3185DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3186{
3187 PPGMPAGE pPage;
3188 int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3189 if (VBOX_FAILURE(rc))
3190 return rc;
3191
3192 fFlags &= ~X86_PTE_PAE_PG_MASK;
3193 pPage->HCPhys |= fFlags; /** @todo PAGE FLAGS */
3194 return VINF_SUCCESS;
3195}
3196
3197
3198/**
3199 * Gets the page directory for the specified address.
3200 *
3201 * @returns Pointer to the page directory in question.
3202 * @returns NULL if the page directory is not present or on an invalid page.
3203 * @param pPGM Pointer to the PGM instance data.
3204 * @param GCPtr The address.
3205 */
3206DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCUINTPTR GCPtr)
3207{
3208 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3209 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3210 {
3211 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3212 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3213
3214 /* cache is out-of-sync. */
3215 PX86PDPAE pPD;
3216 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3217 if (VBOX_SUCCESS(rc))
3218 return pPD;
3219 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3220 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3221 }
3222 return NULL;
3223}
3224
3225
3226/**
3227 * Gets the page directory entry for the specified address.
3228 *
3229 * @returns Pointer to the page directory entry in question.
3230 * @returns NULL if the page directory is not present or on an invalid page.
3231 * @param pPGM Pointer to the PGM instance data.
3232 * @param GCPtr The address.
3233 */
3234DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCUINTPTR GCPtr)
3235{
3236 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3237 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3238 {
3239 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3240 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3241 return &CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD];
3242
3243 /* The cache is out-of-sync. */
3244 PX86PDPAE pPD;
3245 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3246 if (VBOX_SUCCESS(rc))
3247 return &pPD->a[iPD];
3248 AssertMsgFailed(("Impossible! rc=%Vrc PDPE=%RX64\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3249 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. */
3250 }
3251 return NULL;
3252}
3253
3254
3255/**
3256 * Gets the page directory entry for the specified address.
3257 *
3258 * @returns The page directory entry in question.
3259 * @returns A non-present entry if the page directory is not present or on an invalid page.
3260 * @param pPGM Pointer to the PGM instance data.
3261 * @param GCPtr The address.
3262 */
3263DECLINLINE(uint64_t) pgmGstGetPaePDE(PPGM pPGM, RTGCUINTPTR GCPtr)
3264{
3265 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3266 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3267 {
3268 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3269 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3270 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt]->a[iPD].u;
3271
3272 /* cache is out-of-sync. */
3273 PX86PDPAE pPD;
3274 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3275 if (VBOX_SUCCESS(rc))
3276 return pPD->a[iPD].u;
3277 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3278 }
3279 return 0ULL;
3280}
3281
3282
3283/**
3284 * Gets the page directory pointer table entry for the specified address
3285 * and returns the index into the page directory
3286 *
3287 * @returns Pointer to the page directory in question.
3288 * @returns NULL if the page directory is not present or on an invalid page.
3289 * @param pPGM Pointer to the PGM instance data.
3290 * @param GCPtr The address.
3291 * @param piPD Receives the index into the returned page directory
3292 */
3293DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCUINTPTR GCPtr, unsigned *piPD)
3294{
3295 const unsigned iPdPt = GCPtr >> X86_PDPT_SHIFT;
3296 if (CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].n.u1Present)
3297 {
3298 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3299 if ((CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3300 {
3301 *piPD = iPD;
3302 return CTXSUFF(pPGM->apGstPaePDs)[iPdPt];
3303 }
3304
3305 /* cache is out-of-sync. */
3306 PX86PDPAE pPD;
3307 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3308 if (VBOX_SUCCESS(rc))
3309 {
3310 *piPD = iPD;
3311 return pPD;
3312 }
3313 AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, CTXSUFF(pPGM->pGstPaePDPT)->a[iPdPt].u));
3314 /* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3315 }
3316 return NULL;
3317}
3318
3319#ifndef IN_GC
3320/**
3321 * Gets the page directory entry for the specified address.
3322 *
3323 * @returns The page directory entry in question.
3324 * @returns A non-present entry if the page directory is not present or on an invalid page.
3325 * @param pPGM Pointer to the PGM instance data.
3326 * @param GCPtr The address.
3327 * @param ppPml4e Page Map Level-4 Entry (out)
3328 * @param pPdpe Page directory pointer table entry (out)
3329 */
3330DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3331{
3332 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3333
3334 *ppPml4e = &pPGM->pHCPaePML4->a[iPml4e];
3335 if ((*ppPml4e)->n.u1Present)
3336 {
3337 PX86PDPT pPdptTemp;
3338 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), (*ppPml4e)->u & X86_PML4E_PG_MASK, &pPdptTemp);
3339 if (VBOX_FAILURE(rc))
3340 {
3341 AssertFailed();
3342 return 0ULL;
3343 }
3344
3345 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3346 *pPdpe = pPdptTemp->a[iPdPt];
3347 if (pPdpe->n.u1Present)
3348 {
3349 PX86PDPAE pPD;
3350
3351 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdpe->u & X86_PDPE_PG_MASK, &pPD);
3352 if (VBOX_FAILURE(rc))
3353 {
3354 AssertFailed();
3355 return 0ULL;
3356 }
3357 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3358 return pPD->a[iPD].u;
3359 }
3360 }
3361 return 0ULL;
3362}
3363
3364/**
3365 * Gets the page directory entry for the specified address.
3366 *
3367 * @returns The page directory entry in question.
3368 * @returns A non-present entry if the page directory is not present or on an invalid page.
3369 * @param pPGM Pointer to the PGM instance data.
3370 * @param GCPtr The address.
3371 */
3372DECLINLINE(uint64_t) pgmGstGetLongModePDE(PPGM pPGM, RTGCUINTPTR64 GCPtr)
3373{
3374 const unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3375
3376 if (pPGM->pHCPaePML4->a[iPml4e].n.u1Present)
3377 {
3378 PX86PDPT pPdptTemp;
3379 int rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPGM->pHCPaePML4->a[iPml4e].u & X86_PML4E_PG_MASK, &pPdptTemp);
3380 if (VBOX_FAILURE(rc))
3381 {
3382 AssertFailed();
3383 return 0ULL;
3384 }
3385
3386 const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3387 if (pPdptTemp->a[iPdPt].n.u1Present)
3388 {
3389 PX86PDPAE pPD;
3390
3391 rc = PGM_GCPHYS_2_PTR(PGM2VM(pPGM), pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3392 if (VBOX_FAILURE(rc))
3393 {
3394 AssertFailed();
3395 return 0ULL;
3396 }
3397 const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3398 return pPD->a[iPD].u;
3399 }
3400 }
3401 return 0ULL;
3402}
3403#endif /* !IN_GC */
3404
3405/**
3406 * Checks if any of the specified page flags are set for the given page.
3407 *
3408 * @returns true if any of the flags are set.
3409 * @returns false if all the flags are clear.
3410 * @param pPGM PGM handle.
3411 * @param GCPhys The GC physical address.
3412 * @param fFlags The flags to check for.
3413 */
3414DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
3415{
3416 PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
3417 return pPage
3418 && (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
3419}
3420
3421
3422/**
3423 * Gets the page state for a physical handler.
3424 *
3425 * @returns The physical handler page state.
3426 * @param pCur The physical handler in question.
3427 */
3428DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
3429{
3430 switch (pCur->enmType)
3431 {
3432 case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
3433 return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
3434
3435 case PGMPHYSHANDLERTYPE_MMIO:
3436 case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
3437 return PGM_PAGE_HNDL_PHYS_STATE_ALL;
3438
3439 default:
3440 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3441 }
3442}
3443
3444
3445/**
3446 * Gets the page state for a virtual handler.
3447 *
3448 * @returns The virtual handler page state.
3449 * @param pCur The virtual handler in question.
3450 * @remarks This should never be used on a hypervisor access handler.
3451 */
3452DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
3453{
3454 switch (pCur->enmType)
3455 {
3456 case PGMVIRTHANDLERTYPE_WRITE:
3457 return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
3458 case PGMVIRTHANDLERTYPE_ALL:
3459 return PGM_PAGE_HNDL_VIRT_STATE_ALL;
3460 default:
3461 AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
3462 }
3463}
3464
3465
3466/**
3467 * Clears one physical page of a virtual handler
3468 *
3469 * @param pPGM Pointer to the PGM instance.
3470 * @param pCur Virtual handler structure
3471 * @param iPage Physical page index
3472 *
3473 * @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
3474 * need to care about other handlers in the same page.
3475 */
3476DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
3477{
3478 const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
3479
3480 /*
3481 * Remove the node from the tree (it's supposed to be in the tree if we get here!).
3482 */
3483#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3484 AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3485 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3486 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3487#endif
3488 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
3489 {
3490 /* We're the head of the alias chain. */
3491 PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
3492#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3493 AssertReleaseMsg(pRemove != NULL,
3494 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3495 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
3496 AssertReleaseMsg(pRemove == pPhys2Virt,
3497 ("wanted: pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3498 " got: pRemove=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3499 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
3500 pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
3501#endif
3502 if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3503 {
3504 /* Insert the next list in the alias chain into the tree. */
3505 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3506#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3507 AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
3508 ("pNext=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3509 pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
3510#endif
3511 pNext->offNextAlias |= PGMPHYS2VIRTHANDLER_IS_HEAD;
3512 bool fRc = RTAvlroGCPhysInsert(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
3513 AssertRelease(fRc);
3514 }
3515 }
3516 else
3517 {
3518 /* Locate the previous node in the alias chain. */
3519 PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTXSUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
3520#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3521 AssertReleaseMsg(pPrev != pPhys2Virt,
3522 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3523 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3524#endif
3525 for (;;)
3526 {
3527 PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3528 if (pNext == pPhys2Virt)
3529 {
3530 /* unlink. */
3531 LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%VGp-%VGp]\n",
3532 pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
3533 if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3534 pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
3535 else
3536 {
3537 PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3538 pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
3539 | (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
3540 }
3541 break;
3542 }
3543
3544 /* next */
3545 if (pNext == pPrev)
3546 {
3547#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
3548 AssertReleaseMsg(pNext != pPrev,
3549 ("pPhys2Virt=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
3550 pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
3551#endif
3552 break;
3553 }
3554 pPrev = pNext;
3555 }
3556 }
3557 Log2(("PHYS2VIRT: Removing %VGp-%VGp %#RX32 %s\n",
3558 pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, HCSTRING(pCur->pszDesc)));
3559 pPhys2Virt->offNextAlias = 0;
3560 pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
3561
3562 /*
3563 * Clear the ram flags for this page.
3564 */
3565 PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
3566 AssertReturnVoid(pPage);
3567 PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
3568}
3569
3570
3571/**
3572 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3573 *
3574 * @returns Pointer to the shadow page structure.
3575 * @param pPool The pool.
3576 * @param HCPhys The HC physical address of the shadow page.
3577 */
3578DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
3579{
3580 /*
3581 * Look up the page.
3582 */
3583 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
3584 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%VHp pPage=%p type=%d\n", HCPhys, pPage, (pPage) ? pPage->enmKind : 0));
3585 return pPage;
3586}
3587
3588
3589/**
3590 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
3591 *
3592 * @returns Pointer to the shadow page structure.
3593 * @param pPool The pool.
3594 * @param idx The pool page index.
3595 */
3596DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
3597{
3598 AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
3599 return &pPool->aPages[idx];
3600}
3601
3602
3603#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3604/**
3605 * Clear references to guest physical memory.
3606 *
3607 * @param pPool The pool.
3608 * @param pPoolPage The pool page.
3609 * @param pPhysPage The physical guest page tracking structure.
3610 */
3611DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
3612{
3613 /*
3614 * Just deal with the simple case here.
3615 */
3616#ifdef LOG_ENABLED
3617 const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
3618#endif
3619 const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3620 if (cRefs == 1)
3621 {
3622 Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
3623 pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
3624 }
3625 else
3626 pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
3627 LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
3628}
3629#endif
3630
3631
3632#ifdef PGMPOOL_WITH_CACHE
3633/**
3634 * Moves the page to the head of the age list.
3635 *
3636 * This is done when the cached page is used in one way or another.
3637 *
3638 * @param pPool The pool.
3639 * @param pPage The cached page.
3640 * @todo inline in PGMInternal.h!
3641 */
3642DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3643{
3644 /*
3645 * Move to the head of the age list.
3646 */
3647 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
3648 {
3649 /* unlink */
3650 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
3651 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
3652 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
3653 else
3654 pPool->iAgeTail = pPage->iAgePrev;
3655
3656 /* insert at head */
3657 pPage->iAgePrev = NIL_PGMPOOL_IDX;
3658 pPage->iAgeNext = pPool->iAgeHead;
3659 Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
3660 pPool->iAgeHead = pPage->idx;
3661 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
3662 }
3663}
3664#endif /* PGMPOOL_WITH_CACHE */
3665
3666/**
3667 * Tells if mappings are to be put into the shadow page table or not
3668 *
3669 * @returns boolean result
3670 * @param pVM VM handle.
3671 */
3672
3673DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
3674{
3675#ifdef IN_RING0
3676 /* There are no mappings in VT-x and AMD-V mode. */
3677 Assert(pPGM->fDisableMappings);
3678 return false;
3679#else
3680 return !pPGM->fDisableMappings;
3681#endif
3682}
3683
3684/** @} */
3685
3686#endif
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