PGMPhys.cpp@ 18291

Last change on this file since 18291 was 18291, checked in by vboxsync, 16 years ago
PGM: Map PGMRAMRANGES above 4GB outside HMA (see defect). Changed PGMR3MapPT to take a flag indicating whether PGMR3UnmapPT will be used; this way we can select a more optimal allocation function for the ram ranges. PGMMapResolveConflicts: Walk the list correctly after reloc. pgmMapClearShadowPDEs: Don't clear PGM_PLXFLAGS_MAPPING when we shouldn't (odd PAE cases).
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1	/* $Id: PGMPhys.cpp 18291 2009-03-26 05:11:07Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_PHYS
27	#include <VBox/pgm.h>
28	#include <VBox/cpum.h>
29	#include <VBox/iom.h>
30	#include <VBox/sup.h>
31	#include <VBox/mm.h>
32	#include <VBox/stam.h>
33	#include <VBox/rem.h>
34	#include <VBox/csam.h>
35	#include "PGMInternal.h"
36	#include <VBox/vm.h>
37	#include <VBox/dbg.h>
38	#include <VBox/param.h>
39	#include <VBox/err.h>
40	#include <iprt/assert.h>
41	#include <iprt/alloc.h>
42	#include <iprt/asm.h>
43	#include <VBox/log.h>
44	#include <iprt/thread.h>
45	#include <iprt/string.h>
46
47
48	/*******************************************************************************
49	* Defined Constants And Macros *
50	*******************************************************************************/
51	/** The number of pages to free in one batch. */
52	#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
53
54
55	/*******************************************************************************
56	* Internal Functions *
57	*******************************************************************************/
58	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
59	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
60
61
62	/*
63	* PGMR3PhysReadU8-64
64	* PGMR3PhysWriteU8-64
65	*/
66	#define PGMPHYSFN_READNAME PGMR3PhysReadU8
67	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
68	#define PGMPHYS_DATASIZE 1
69	#define PGMPHYS_DATATYPE uint8_t
70	#include "PGMPhysRWTmpl.h"
71
72	#define PGMPHYSFN_READNAME PGMR3PhysReadU16
73	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
74	#define PGMPHYS_DATASIZE 2
75	#define PGMPHYS_DATATYPE uint16_t
76	#include "PGMPhysRWTmpl.h"
77
78	#define PGMPHYSFN_READNAME PGMR3PhysReadU32
79	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
80	#define PGMPHYS_DATASIZE 4
81	#define PGMPHYS_DATATYPE uint32_t
82	#include "PGMPhysRWTmpl.h"
83
84	#define PGMPHYSFN_READNAME PGMR3PhysReadU64
85	#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
86	#define PGMPHYS_DATASIZE 8
87	#define PGMPHYS_DATATYPE uint64_t
88	#include "PGMPhysRWTmpl.h"
89
90
91	/**
92	* EMT worker for PGMR3PhysReadExternal.
93	*/
94	static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
95	{
96	PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
97	return VINF_SUCCESS;
98	}
99
100
101	/**
102	* Write to physical memory, external users.
103	*
104	* @returns VBox status code.
105	* @retval VINF_SUCCESS.
106	*
107	* @param pVM VM Handle.
108	* @param GCPhys Physical address to write to.
109	* @param pvBuf What to write.
110	* @param cbWrite How many bytes to write.
111	*
112	* @thread Any but EMTs.
113	*/
114	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
115	{
116	VM_ASSERT_OTHER_THREAD(pVM);
117
118	AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
119	LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
120
121	pgmLock(pVM);
122
123	/*
124	* Copy loop on ram ranges.
125	*/
126	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
127	for (;;)
128	{
129	/* Find range. */
130	while (pRam && GCPhys > pRam->GCPhysLast)
131	pRam = pRam->CTX_SUFF(pNext);
132	/* Inside range or not? */
133	if (pRam && GCPhys >= pRam->GCPhys)
134	{
135	/*
136	* Must work our way thru this page by page.
137	*/
138	RTGCPHYS off = GCPhys - pRam->GCPhys;
139	while (off < pRam->cb)
140	{
141	unsigned iPage = off >> PAGE_SHIFT;
142	PPGMPAGE pPage = &pRam->aPages[iPage];
143
144	/*
145	* If the page has an ALL access handler, we'll have to
146	* delegate the job to EMT.
147	*/
148	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
149	{
150	pgmUnlock(pVM);
151
152	PVMREQ pReq = NULL;
153	int rc = VMR3ReqCall(pVM, VMREQDEST_ANY, &pReq, RT_INDEFINITE_WAIT,
154	(PFNRT)pgmR3PhysReadExternalEMT, 4, pVM, &GCPhys, pvBuf, cbRead);
155	if (RT_SUCCESS(rc))
156	{
157	rc = pReq->iStatus;
158	VMR3ReqFree(pReq);
159	}
160	return rc;
161	}
162	Assert(!PGM_PAGE_IS_MMIO(pPage));
163
164	/*
165	* Simple stuff, go ahead.
166	*/
167	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
168	if (cb > cbRead)
169	cb = cbRead;
170	const void *pvSrc;
171	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
172	if (RT_SUCCESS(rc))
173	memcpy(pvBuf, pvSrc, cb);
174	else
175	{
176	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
177	pRam->GCPhys + off, pPage, rc));
178	memset(pvBuf, 0xff, cb);
179	}
180
181	/* next page */
182	if (cb >= cbRead)
183	{
184	pgmUnlock(pVM);
185	return VINF_SUCCESS;
186	}
187	cbRead -= cb;
188	off += cb;
189	GCPhys += cb;
190	pvBuf = (char *)pvBuf + cb;
191	} /* walk pages in ram range. */
192	}
193	else
194	{
195	LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
196
197	/*
198	* Unassigned address space.
199	*/
200	if (!pRam)
201	break;
202	size_t cb = pRam->GCPhys - GCPhys;
203	if (cb >= cbRead)
204	{
205	memset(pvBuf, 0xff, cbRead);
206	break;
207	}
208	memset(pvBuf, 0xff, cb);
209
210	cbRead -= cb;
211	pvBuf = (char *)pvBuf + cb;
212	GCPhys += cb;
213	}
214	} /* Ram range walk */
215
216	pgmUnlock(pVM);
217
218	return VINF_SUCCESS;
219	}
220
221
222	/**
223	* EMT worker for PGMR3PhysWriteExternal.
224	*/
225	static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
226	{
227	/** @todo VERR_EM_NO_MEMORY */
228	PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
229	return VINF_SUCCESS;
230	}
231
232
233	/**
234	* Write to physical memory, external users.
235	*
236	* @returns VBox status code.
237	* @retval VINF_SUCCESS.
238	* @retval VERR_EM_NO_MEMORY.
239	*
240	* @param pVM VM Handle.
241	* @param GCPhys Physical address to write to.
242	* @param pvBuf What to write.
243	* @param cbWrite How many bytes to write.
244	*
245	* @thread Any but EMTs.
246	*/
247	VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
248	{
249	VM_ASSERT_OTHER_THREAD(pVM);
250
251	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites, ("Calling PGMR3PhysWriteExternal after pgmR3Save()!\n"));
252	AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
253	LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
254
255	pgmLock(pVM);
256
257	/*
258	* Copy loop on ram ranges, stop when we hit something difficult.
259	*/
260	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
261	for (;;)
262	{
263	/* Find range. */
264	while (pRam && GCPhys > pRam->GCPhysLast)
265	pRam = pRam->CTX_SUFF(pNext);
266	/* Inside range or not? */
267	if (pRam && GCPhys >= pRam->GCPhys)
268	{
269	/*
270	* Must work our way thru this page by page.
271	*/
272	RTGCPTR off = GCPhys - pRam->GCPhys;
273	while (off < pRam->cb)
274	{
275	RTGCPTR iPage = off >> PAGE_SHIFT;
276	PPGMPAGE pPage = &pRam->aPages[iPage];
277
278	/*
279	* It the page is in any way problematic, we have to
280	* do the work on the EMT. Anything that needs to be made
281	* writable or involves access handlers is problematic.
282	*/
283	if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
284	\|\| PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
285	{
286	pgmUnlock(pVM);
287
288	PVMREQ pReq = NULL;
289	int rc = VMR3ReqCall(pVM, VMREQDEST_ANY, &pReq, RT_INDEFINITE_WAIT,
290	(PFNRT)pgmR3PhysWriteExternalEMT, 4, pVM, &GCPhys, pvBuf, cbWrite);
291	if (RT_SUCCESS(rc))
292	{
293	rc = pReq->iStatus;
294	VMR3ReqFree(pReq);
295	}
296	return rc;
297	}
298	Assert(!PGM_PAGE_IS_MMIO(pPage));
299
300	/*
301	* Simple stuff, go ahead.
302	*/
303	size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
304	if (cb > cbWrite)
305	cb = cbWrite;
306	void *pvDst;
307	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
308	if (RT_SUCCESS(rc))
309	memcpy(pvDst, pvBuf, cb);
310	else
311	AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
312	pRam->GCPhys + off, pPage, rc));
313
314	/* next page */
315	if (cb >= cbWrite)
316	{
317	pgmUnlock(pVM);
318	return VINF_SUCCESS;
319	}
320
321	cbWrite -= cb;
322	off += cb;
323	GCPhys += cb;
324	pvBuf = (const char *)pvBuf + cb;
325	} /* walk pages in ram range */
326	}
327	else
328	{
329	/*
330	* Unassigned address space, skip it.
331	*/
332	if (!pRam)
333	break;
334	size_t cb = pRam->GCPhys - GCPhys;
335	if (cb >= cbWrite)
336	break;
337	cbWrite -= cb;
338	pvBuf = (const char *)pvBuf + cb;
339	GCPhys += cb;
340	}
341	} /* Ram range walk */
342
343	pgmUnlock(pVM);
344	return VINF_SUCCESS;
345	}
346
347
348	#ifdef VBOX_WITH_NEW_PHYS_CODE
349	/**
350	* VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
351	*
352	* @returns see PGMR3PhysGCPhys2CCPtrExternal
353	* @param pVM The VM handle.
354	* @param pGCPhys Pointer to the guest physical address.
355	* @param ppv Where to store the mapping address.
356	* @param pLock Where to store the lock.
357	*/
358	static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
359	{
360	/*
361	* Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
362	* an access handler after it succeeds.
363	*/
364	int rc = pgmLock(pVM);
365	AssertRCReturn(rc, rc);
366
367	rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
368	if (RT_SUCCESS(rc))
369	{
370	PPGMPAGEMAPTLBE pTlbe;
371	int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
372	AssertFatalRC(rc2);
373	PPGMPAGE pPage = pTlbe->pPage;
374	#if 1
375	if (PGM_PAGE_IS_MMIO(pPage))
376	#else
377	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
378	#endif
379	{
380	PGMPhysReleasePageMappingLock(pVM, pLock);
381	rc = VERR_PGM_PHYS_PAGE_RESERVED;
382	}
383	}
384
385	pgmUnlock(pVM);
386	return rc;
387	}
388	#endif /* VBOX_WITH_NEW_PHYS_CODE */
389
390
391	/**
392	* Requests the mapping of a guest page into ring-3, external threads.
393	*
394	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
395	* release it.
396	*
397	* This API will assume your intention is to write to the page, and will
398	* therefore replace shared and zero pages. If you do not intend to modify the
399	* page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
400	*
401	* @returns VBox status code.
402	* @retval VINF_SUCCESS on success.
403	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
404	* backing or if the page has any active access handlers. The caller
405	* must fall back on using PGMR3PhysWriteExternal.
406	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
407	*
408	* @param pVM The VM handle.
409	* @param GCPhys The guest physical address of the page that should be mapped.
410	* @param ppv Where to store the address corresponding to GCPhys.
411	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
412	*
413	* @remark Avoid calling this API from within critical sections (other than the
414	* PGM one) because of the deadlock risk when we have to delegating the
415	* task to an EMT.
416	* @thread Any.
417	*/
418	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
419	{
420	VM_ASSERT_OTHER_THREAD(pVM);
421	AssertPtr(ppv);
422	AssertPtr(pLock);
423
424	#ifdef VBOX_WITH_NEW_PHYS_CODE
425	int rc = pgmLock(pVM);
426	AssertRCReturn(rc, rc);
427
428	/*
429	* Query the Physical TLB entry for the page (may fail).
430	*/
431	PPGMPAGEMAPTLBE pTlbe;
432	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
433	if (RT_SUCCESS(rc))
434	{
435	PPGMPAGE pPage = pTlbe->pPage;
436	#if 1
437	if (PGM_PAGE_IS_MMIO(pPage))
438	rc = VERR_PGM_PHYS_PAGE_RESERVED;
439	#else
440	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
441	rc = VERR_PGM_PHYS_PAGE_RESERVED;
442	#endif
443	else
444	{
445	/*
446	* If the page is shared, the zero page, or being write monitored
447	* it must be converted to an page that's writable if possible.
448	* This has to be done on an EMT.
449	*/
450	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED))
451	{
452	pgmUnlock(pVM);
453
454	PVMREQ pReq = NULL;
455	rc = VMR3ReqCall(pVM, VMREQDEST_ANY, &pReq, RT_INDEFINITE_WAIT,
456	(PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4, pVM, &GCPhys, ppv, pLock);
457	if (RT_SUCCESS(rc))
458	{
459	rc = pReq->iStatus;
460	VMR3ReqFree(pReq);
461	}
462	return rc;
463	}
464
465	/*
466	* Now, just perform the locking and calculate the return address.
467	*/
468	PPGMPAGEMAP pMap = pTlbe->pMap;
469	pMap->cRefs++;
470	#if 0 /** @todo implement locking properly */
471	if (RT_LIKELY(pPage->cLocks != PGM_PAGE_MAX_LOCKS))
472	if (RT_UNLIKELY(++pPage->cLocks == PGM_PAGE_MAX_LOCKS))
473	{
474	AssertMsgFailed(("%RGp is entering permanent locked state!\n", GCPhys));
475	pMap->cRefs++; /* Extra ref to prevent it from going away. */
476	}
477	#endif
478	ppv = (void )((uintptr_t)pTlbe->pv \| (GCPhys & PAGE_OFFSET_MASK));
479	pLock->pvPage = pPage;
480	pLock->pvMap = pMap;
481	}
482	}
483
484	pgmUnlock(pVM);
485	return rc;
486
487	#else /* !VBOX_WITH_NEW_PHYS_CODE */
488	/*
489	* Fallback code.
490	*/
491	return PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1, (PRTR3PTR)ppv);
492	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
493	}
494
495
496	/**
497	* Requests the mapping of a guest page into ring-3, external threads.
498	*
499	* When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
500	* release it.
501	*
502	* @returns VBox status code.
503	* @retval VINF_SUCCESS on success.
504	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
505	* backing or if the page as an active ALL access handler. The caller
506	* must fall back on using PGMPhysRead.
507	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
508	*
509	* @param pVM The VM handle.
510	* @param GCPhys The guest physical address of the page that should be mapped.
511	* @param ppv Where to store the address corresponding to GCPhys.
512	* @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
513	*
514	* @remark Avoid calling this API from within critical sections (other than
515	* the PGM one) because of the deadlock risk.
516	* @thread Any.
517	*/
518	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
519	{
520	#ifdef VBOX_WITH_NEW_PHYS_CODE
521	int rc = pgmLock(pVM);
522	AssertRCReturn(rc, rc);
523
524	/*
525	* Query the Physical TLB entry for the page (may fail).
526	*/
527	PPGMPAGEMAPTLBE pTlbe;
528	rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
529	if (RT_SUCCESS(rc))
530	{
531	PPGMPAGE pPage = pTlbe->pPage;
532	#if 1
533	/* MMIO pages doesn't have any readable backing. */
534	if (PGM_PAGE_IS_MMIO(pPage))
535	rc = VERR_PGM_PHYS_PAGE_RESERVED;
536	#else
537	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
538	rc = VERR_PGM_PHYS_PAGE_RESERVED;
539	#endif
540	else
541	{
542	/*
543	* Now, just perform the locking and calculate the return address.
544	*/
545	PPGMPAGEMAP pMap = pTlbe->pMap;
546	pMap->cRefs++;
547	#if 0 /** @todo implement locking properly */
548	if (RT_LIKELY(pPage->cLocks != PGM_PAGE_MAX_LOCKS))
549	if (RT_UNLIKELY(++pPage->cLocks == PGM_PAGE_MAX_LOCKS))
550	{
551	AssertMsgFailed(("%RGp is entering permanent locked state!\n", GCPhys));
552	pMap->cRefs++; /* Extra ref to prevent it from going away. */
553	}
554	#endif
555	ppv = (void )((uintptr_t)pTlbe->pv \| (GCPhys & PAGE_OFFSET_MASK));
556	pLock->pvPage = pPage;
557	pLock->pvMap = pMap;
558	}
559	}
560
561	pgmUnlock(pVM);
562	return rc;
563
564	#else /* !VBOX_WITH_NEW_PHYS_CODE */
565	/*
566	* Fallback code.
567	*/
568	return PGMPhysGCPhys2CCPtr(pVM, GCPhys, (void **)ppv, pLock);
569	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
570	}
571
572
573	/**
574	* Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
575	*
576	* Called when anything was relocated.
577	*
578	* @param pVM Pointer to the shared VM structure.
579	*/
580	void pgmR3PhysRelinkRamRanges(PVM pVM)
581	{
582	PPGMRAMRANGE pCur;
583
584	#ifdef VBOX_STRICT
585	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
586	{
587	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
588	Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
589	Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
590	Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
591	Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
592	Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
593	for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
594	Assert( pCur2 == pCur
595	\|\| strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
596	}
597	#endif
598
599	pCur = pVM->pgm.s.pRamRangesR3;
600	if (pCur)
601	{
602	pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
603	pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
604
605	for (; pCur->pNextR3; pCur = pCur->pNextR3)
606	{
607	pCur->pNextR0 = pCur->pNextR3->pSelfR0;
608	pCur->pNextRC = pCur->pNextR3->pSelfRC;
609	}
610
611	Assert(pCur->pNextR0 == NIL_RTR0PTR);
612	Assert(pCur->pNextRC == NIL_RTRCPTR);
613	}
614	else
615	{
616	Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
617	Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
618	}
619	}
620
621
622	/**
623	* Links a new RAM range into the list.
624	*
625	* @param pVM Pointer to the shared VM structure.
626	* @param pNew Pointer to the new list entry.
627	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
628	*/
629	static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
630	{
631	AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
632	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
633	Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
634
635	pgmLock(pVM);
636
637	PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
638	pNew->pNextR3 = pRam;
639	pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
640	pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
641
642	if (pPrev)
643	{
644	pPrev->pNextR3 = pNew;
645	pPrev->pNextR0 = pNew->pSelfR0;
646	pPrev->pNextRC = pNew->pSelfRC;
647	}
648	else
649	{
650	pVM->pgm.s.pRamRangesR3 = pNew;
651	pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
652	pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
653	}
654
655	pgmUnlock(pVM);
656	}
657
658
659	/**
660	* Unlink an existing RAM range from the list.
661	*
662	* @param pVM Pointer to the shared VM structure.
663	* @param pRam Pointer to the new list entry.
664	* @param pPrev Pointer to the previous list entry. If NULL, insert as head.
665	*/
666	static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
667	{
668	Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
669	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
670	Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) \|\| pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
671
672	pgmLock(pVM);
673
674	PPGMRAMRANGE pNext = pRam->pNextR3;
675	if (pPrev)
676	{
677	pPrev->pNextR3 = pNext;
678	pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
679	pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
680	}
681	else
682	{
683	Assert(pVM->pgm.s.pRamRangesR3 == pRam);
684	pVM->pgm.s.pRamRangesR3 = pNext;
685	pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
686	pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
687	}
688
689	pgmUnlock(pVM);
690	}
691
692
693	/**
694	* Unlink an existing RAM range from the list.
695	*
696	* @param pVM Pointer to the shared VM structure.
697	* @param pRam Pointer to the new list entry.
698	*/
699	static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
700	{
701	pgmLock(pVM);
702
703	/* find prev. */
704	PPGMRAMRANGE pPrev = NULL;
705	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
706	while (pCur != pRam)
707	{
708	pPrev = pCur;
709	pCur = pCur->pNextR3;
710	}
711	AssertFatal(pCur);
712
713	pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
714
715	pgmUnlock(pVM);
716	}
717
718
719	#ifdef VBOX_WITH_NEW_PHYS_CODE
720	/**
721	* Frees a range of pages, replacing them with ZERO pages of the specified type.
722	*
723	* @returns VBox status code.
724	* @param pVM The VM handle.
725	* @param pRam The RAM range in which the pages resides.
726	* @param GCPhys The address of the first page.
727	* @param GCPhysLast The address of the last page.
728	* @param uType The page type to replace then with.
729	*/
730	static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
731	{
732	uint32_t cPendingPages = 0;
733	PGMMFREEPAGESREQ pReq;
734	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
735	AssertLogRelRCReturn(rc, rc);
736
737	/* Itegerate the pages. */
738	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
739	uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
740	while (cPagesLeft-- > 0)
741	{
742	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
743	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
744
745	PGM_PAGE_SET_TYPE(pPageDst, uType);
746
747	GCPhys += PAGE_SIZE;
748	pPageDst++;
749	}
750
751	if (cPendingPages)
752	{
753	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
754	AssertLogRelRCReturn(rc, rc);
755	}
756	GMMR3FreePagesCleanup(pReq);
757
758	return rc;
759	}
760	#endif /* VBOX_WITH_NEW_PHYS_CODE */
761
762
763	/**
764	* PGMR3PhysRegisterRam worker that initializes and links a RAM range.
765	*
766	* @param pVM The VM handle.
767	* @param pNew The new RAM range.
768	* @param GCPhys The address of the RAM range.
769	* @param GCPhysLast The last address of the RAM range.
770	* @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
771	* if in HMA.
772	* @param R0PtrNew Ditto for R0.
773	* @param pszDesc The description.
774	* @param pPrev The previous RAM range (for linking).
775	*/
776	static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
777	RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
778	{
779	/*
780	* Initialize the range.
781	*/
782	pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
783	pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
784	pNew->GCPhys = GCPhys;
785	pNew->GCPhysLast = GCPhysLast;
786	pNew->cb = GCPhysLast - GCPhys + 1;
787	pNew->pszDesc = pszDesc;
788	pNew->fFlags = RCPtrNew != NIL_RTR0PTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
789	pNew->pvR3 = NULL;
790
791	uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
792	RTGCPHYS iPage = cPages;
793	while (iPage-- > 0)
794	PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
795
796	/* Update the page count stats. */
797	pVM->pgm.s.cZeroPages += cPages;
798	pVM->pgm.s.cAllPages += cPages;
799
800	/*
801	* Link it.
802	*/
803	pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
804	}
805
806
807	/**
808	* Relocate a floating RAM range.
809	*
810	* @copydoc FNPGMRELOCATE.
811	*/
812	static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
813	{
814	PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
815	Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
816	Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
817
818	switch (enmMode)
819	{
820	case PGMRELOCATECALL_SUGGEST:
821	return true;
822	case PGMRELOCATECALL_RELOCATE:
823	{
824	/* Update myself and then relink all the ranges. */
825	pgmLock(pVM);
826	pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
827	pgmR3PhysRelinkRamRanges(pVM);
828	pgmUnlock(pVM);
829	return true;
830	}
831
832	default:
833	AssertFailedReturn(false);
834	}
835	}
836
837
838	/**
839	* PGMR3PhysRegisterRam worker that registers a high chunk.
840	*
841	* @returns VBox status code.
842	* @param pVM The VM handle.
843	* @param GCPhys The address of the RAM.
844	* @param cRamPages The number of RAM pages to register.
845	* @param cbChunk The size of the PGMRAMRANGE guest mapping.
846	* @param iChunk The chunk number.
847	* @param pszDesc The RAM range description.
848	* @param ppPrev Previous RAM range pointer. In/Out.
849	*/
850	static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
851	uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
852	PPGMRAMRANGE *ppPrev)
853	{
854	const char *pszDescChunk = iChunk == 0
855	? pszDesc
856	: MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
857	AssertReturn(pszDescChunk, VERR_NO_MEMORY);
858
859	/*
860	* Allocate memory for the new chunk.
861	*/
862	size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
863	PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
864	AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
865	RTR0PTR R0PtrChunk = NIL_RTR0PTR;
866	void *pvChunk = NULL;
867	int rc = SUPR3PageAllocEx(cChunkPages, 0 /fFlags/, &pvChunk,
868	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
869	VMMIsHwVirtExtForced(pVM) ? &pvR0 : NULL,
870	#else
871	NULL,
872	#endif
873	paChunkPages);
874	if (RT_SUCCESS(rc))
875	{
876	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
877	if (!VMMIsHwVirtExtForced(pVM))
878	R0PtrChunk = NIL_RTR0PTR;
879	#else
880	R0PtrChunk = (uintptr_t)pvChunk;
881	#endif
882	memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
883
884	PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
885
886	/*
887	* Create a mapping and map the pages into it.
888	* We push these in below the HMA.
889	*/
890	RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
891	rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /fFlags/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
892	if (RT_SUCCESS(rc))
893	{
894	pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
895
896	RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
897	RTGCPTR GCPtrPage = GCPtrChunk;
898	for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
899	rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
900	if (RT_SUCCESS(rc))
901	{
902	/*
903	* Ok, init and link the range.
904	*/
905	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
906	(RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
907	*ppPrev = pNew;
908	}
909	}
910
911	if (RT_FAILURE(rc))
912	SUPR3PageFreeEx(pvChunk, cChunkPages);
913	}
914
915	RTMemTmpFree(paChunkPages);
916	return rc;
917	}
918
919
920	/**
921	* Sets up a range RAM.
922	*
923	* This will check for conflicting registrations, make a resource
924	* reservation for the memory (with GMM), and setup the per-page
925	* tracking structures (PGMPAGE).
926	*
927	* @returns VBox stutus code.
928	* @param pVM Pointer to the shared VM structure.
929	* @param GCPhys The physical address of the RAM.
930	* @param cb The size of the RAM.
931	* @param pszDesc The description - not copied, so, don't free or change it.
932	*/
933	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
934	{
935	/*
936	* Validate input.
937	*/
938	Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
939	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
940	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
941	AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
942	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
943	AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
944	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
945	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
946
947	/*
948	* Find range location and check for conflicts.
949	* (We don't lock here because the locking by EMT is only required on update.)
950	*/
951	PPGMRAMRANGE pPrev = NULL;
952	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
953	while (pRam && GCPhysLast >= pRam->GCPhys)
954	{
955	if ( GCPhysLast >= pRam->GCPhys
956	&& GCPhys <= pRam->GCPhysLast)
957	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
958	GCPhys, GCPhysLast, pszDesc,
959	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
960	VERR_PGM_RAM_CONFLICT);
961
962	/* next */
963	pPrev = pRam;
964	pRam = pRam->pNextR3;
965	}
966
967	/*
968	* Register it with GMM (the API bitches).
969	*/
970	const RTGCPHYS cPages = cb >> PAGE_SHIFT;
971	int rc = MMR3IncreaseBaseReservation(pVM, cPages);
972	if (RT_FAILURE(rc))
973	return rc;
974
975	#ifdef VBOX_WITH_NEW_PHYS_CODE
976	if ( GCPhys >= _4G
977	&& cPages > 256)
978	{
979	/*
980	* The PGMRAMRANGE structures for the high memory can get very big.
981	* In order to avoid SUPR3PageAllocEx allocation failures due to the
982	* allocation size limit there and also to avoid being unable to find
983	* guest mapping space for them, we split this memory up into 4MB in
984	* (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
985	* mode.
986	*
987	* The first and last page of each mapping are guard pages and marked
988	* not-present. So, we've got 4186112 and 16769024 bytes available for
989	* the PGMRAMRANGE structure.
990	*
991	* Note! The sizes used here will influence the saved state.
992	*/
993	uint32_t cbChunk;
994	uint32_t cPagesPerChunk;
995	if (VMMIsHwVirtExtForced(pVM))
996	{
997	cbChunk = 16U*_1M;
998	cPagesPerChunk = 1048048; /* max ~1048059 */
999	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U_1M - PAGE_SIZE 2);
1000	}
1001	else
1002	{
1003	cbChunk = 4U*_1M;
1004	cPagesPerChunk = 261616; /* max ~261627 */
1005	AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U_1M - PAGE_SIZE 2);
1006	}
1007	AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1008
1009	RTGCPHYS cPagesLeft = cPages;
1010	RTGCPHYS GCPhysChunk = GCPhys;
1011	uint32_t iChunk = 0;
1012	while (cPagesLeft > 0)
1013	{
1014	uint32_t cPagesInChunk = cPagesLeft;
1015	if (cPagesInChunk > cPagesPerChunk)
1016	cPagesInChunk = cPagesPerChunk;
1017
1018	rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1019	AssertRCReturn(rc, rc);
1020
1021	/* advance */
1022	GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1023	cPagesLeft -= cPagesInChunk;
1024	iChunk++;
1025	}
1026	}
1027	else
1028	#endif
1029	{
1030	/*
1031	* Allocate, initialize and link the new RAM range.
1032	*/
1033	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1034	PPGMRAMRANGE pNew;
1035	rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1036	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1037
1038	#ifndef VBOX_WITH_NEW_PHYS_CODE
1039	/* Allocate memory for chunk to HC ptr lookup array. */
1040	pNew->paChunkR3Ptrs = NULL;
1041	rc = MMHyperAlloc(pVM, (cb >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(void ), 16, MM_TAG_PGM, (void *)&pNew->paChunkR3Ptrs);
1042	AssertRCReturn(rc, rc);
1043	pNew->fFlags \|= MM_RAM_FLAGS_DYNAMIC_ALLOC;
1044	#endif
1045
1046	pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1047	}
1048
1049	/*
1050	* Notify REM.
1051	*/
1052	#ifdef VBOX_WITH_NEW_PHYS_CODE
1053	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1054	#else
1055	REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, MM_RAM_FLAGS_DYNAMIC_ALLOC);
1056	#endif
1057
1058	return VINF_SUCCESS;
1059	}
1060
1061
1062	/**
1063	* Resets (zeros) the RAM.
1064	*
1065	* ASSUMES that the caller owns the PGM lock.
1066	*
1067	* @returns VBox status code.
1068	* @param pVM Pointer to the shared VM structure.
1069	*/
1070	int pgmR3PhysRamReset(PVM pVM)
1071	{
1072	#ifdef VBOX_WITH_NEW_PHYS_CODE
1073	/*
1074	* We batch up pages before freeing them.
1075	*/
1076	uint32_t cPendingPages = 0;
1077	PGMMFREEPAGESREQ pReq;
1078	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1079	AssertLogRelRCReturn(rc, rc);
1080	#endif
1081
1082	/*
1083	* Walk the ram ranges.
1084	*/
1085	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1086	{
1087	uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1088	AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1089
1090	#ifdef VBOX_WITH_NEW_PHYS_CODE
1091	if (!pVM->pgm.s.fRamPreAlloc)
1092	{
1093	/* Replace all RAM pages by ZERO pages. */
1094	while (iPage-- > 0)
1095	{
1096	PPGMPAGE pPage = &pRam->aPages[iPage];
1097	switch (PGM_PAGE_GET_TYPE(pPage))
1098	{
1099	case PGMPAGETYPE_RAM:
1100	if (!PGM_PAGE_IS_ZERO(pPage))
1101	{
1102	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1103	AssertLogRelRCReturn(rc, rc);
1104	}
1105	break;
1106
1107	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1108	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1109	break;
1110
1111	case PGMPAGETYPE_MMIO2:
1112	case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1113	case PGMPAGETYPE_ROM:
1114	case PGMPAGETYPE_MMIO:
1115	break;
1116	default:
1117	AssertFailed();
1118	}
1119	} /* for each page */
1120	}
1121	else
1122	#endif
1123	{
1124	/* Zero the memory. */
1125	while (iPage-- > 0)
1126	{
1127	PPGMPAGE pPage = &pRam->aPages[iPage];
1128	switch (PGM_PAGE_GET_TYPE(pPage))
1129	{
1130	#ifndef VBOX_WITH_NEW_PHYS_CODE
1131	case PGMPAGETYPE_INVALID:
1132	case PGMPAGETYPE_RAM:
1133	if (pRam->aPages[iPage].HCPhys & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2)) /** @todo PAGE FLAGS */
1134	{
1135	/* shadow ram is reloaded elsewhere. */
1136	Log4(("PGMR3Reset: not clearing phys page %RGp due to flags %RHp\n", pRam->GCPhys + (iPage << PAGE_SHIFT), pRam->aPages[iPage].HCPhys & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO))); /** @todo PAGE FLAGS */
1137	continue;
1138	}
1139	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1140	{
1141	unsigned iChunk = iPage >> (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
1142	if (pRam->paChunkR3Ptrs[iChunk])
1143	ASMMemZero32((char *)pRam->paChunkR3Ptrs[iChunk] + ((iPage << PAGE_SHIFT) & PGM_DYNAMIC_CHUNK_OFFSET_MASK), PAGE_SIZE);
1144	}
1145	else
1146	ASMMemZero32((char *)pRam->pvR3 + (iPage << PAGE_SHIFT), PAGE_SIZE);
1147	break;
1148	#else /* VBOX_WITH_NEW_PHYS_CODE */
1149	case PGMPAGETYPE_RAM:
1150	switch (PGM_PAGE_GET_STATE(pPage))
1151	{
1152	case PGM_PAGE_STATE_ZERO:
1153	break;
1154	case PGM_PAGE_STATE_SHARED:
1155	case PGM_PAGE_STATE_WRITE_MONITORED:
1156	rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1157	AssertLogRelRCReturn(rc, rc);
1158	case PGM_PAGE_STATE_ALLOCATED:
1159	{
1160	void *pvPage;
1161	PPGMPAGEMAP pMapIgnored;
1162	rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pMapIgnored, &pvPage);
1163	AssertLogRelRCReturn(rc, rc);
1164	ASMMemZeroPage(pvPage);
1165	break;
1166	}
1167	}
1168	break;
1169	#endif /* VBOX_WITH_NEW_PHYS_CODE */
1170
1171	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1172	pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1173	break;
1174
1175	case PGMPAGETYPE_MMIO2:
1176	case PGMPAGETYPE_ROM_SHADOW:
1177	case PGMPAGETYPE_ROM:
1178	case PGMPAGETYPE_MMIO:
1179	break;
1180	default:
1181	AssertFailed();
1182
1183	}
1184	} /* for each page */
1185	}
1186
1187	}
1188
1189	#ifdef VBOX_WITH_NEW_PHYS_CODE
1190	/*
1191	* Finish off any pages pending freeing.
1192	*/
1193	if (cPendingPages)
1194	{
1195	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1196	AssertLogRelRCReturn(rc, rc);
1197	}
1198	GMMR3FreePagesCleanup(pReq);
1199	#endif
1200
1201
1202	return VINF_SUCCESS;
1203	}
1204
1205
1206	/**
1207	* This is the interface IOM is using to register an MMIO region.
1208	*
1209	* It will check for conflicts and ensure that a RAM range structure
1210	* is present before calling the PGMR3HandlerPhysicalRegister API to
1211	* register the callbacks.
1212	*
1213	* @returns VBox status code.
1214	*
1215	* @param pVM Pointer to the shared VM structure.
1216	* @param GCPhys The start of the MMIO region.
1217	* @param cb The size of the MMIO region.
1218	* @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1219	* @param pvUserR3 The user argument for R3.
1220	* @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1221	* @param pvUserR0 The user argument for R0.
1222	* @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1223	* @param pvUserRC The user argument for RC.
1224	* @param pszDesc The description of the MMIO region.
1225	*/
1226	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1227	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1228	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1229	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1230	R3PTRTYPE(const char *) pszDesc)
1231	{
1232	/*
1233	* Assert on some assumption.
1234	*/
1235	VM_ASSERT_EMT(pVM);
1236	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1237	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1238	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1239	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1240
1241	/*
1242	* Make sure there's a RAM range structure for the region.
1243	*/
1244	int rc;
1245	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1246	bool fRamExists = false;
1247	PPGMRAMRANGE pRamPrev = NULL;
1248	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1249	while (pRam && GCPhysLast >= pRam->GCPhys)
1250	{
1251	if ( GCPhysLast >= pRam->GCPhys
1252	&& GCPhys <= pRam->GCPhysLast)
1253	{
1254	/* Simplification: all within the same range. */
1255	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1256	&& GCPhysLast <= pRam->GCPhysLast,
1257	("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1258	GCPhys, GCPhysLast, pszDesc,
1259	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1260	VERR_PGM_RAM_CONFLICT);
1261
1262	/* Check that it's all RAM or MMIO pages. */
1263	PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1264	uint32_t cLeft = cb >> PAGE_SHIFT;
1265	while (cLeft-- > 0)
1266	{
1267	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1268	\|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1269	("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1270	GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1271	VERR_PGM_RAM_CONFLICT);
1272	pPage++;
1273	}
1274
1275	/* Looks good. */
1276	fRamExists = true;
1277	break;
1278	}
1279
1280	/* next */
1281	pRamPrev = pRam;
1282	pRam = pRam->pNextR3;
1283	}
1284	PPGMRAMRANGE pNew;
1285	if (fRamExists)
1286	{
1287	pNew = NULL;
1288	#ifdef VBOX_WITH_NEW_PHYS_CODE
1289	/*
1290	* Make all the pages in the range MMIO/ZERO pages, freeing any
1291	* RAM pages currently mapped here. This might not be 100% correct
1292	* for PCI memory, but we're doing the same thing for MMIO2 pages.
1293	*/
1294	rc = pgmLock(pVM);
1295	if (RT_SUCCESS(rc))
1296	{
1297	rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1298	pgmUnlock(pVM);
1299	}
1300	AssertRCReturn(rc, rc);
1301	#endif
1302	}
1303	else
1304	{
1305	/*
1306	* No RAM range, insert an ad-hoc one.
1307	*
1308	* Note that we don't have to tell REM about this range because
1309	* PGMHandlerPhysicalRegisterEx will do that for us.
1310	*/
1311	Log(("PGMR3PhysMMIORegister: Adding ad-hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1312
1313	const uint32_t cPages = cb >> PAGE_SHIFT;
1314	const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1315	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1316	AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1317
1318	/* Initialize the range. */
1319	pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1320	pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1321	pNew->GCPhys = GCPhys;
1322	pNew->GCPhysLast = GCPhysLast;
1323	pNew->cb = cb;
1324	pNew->pszDesc = pszDesc;
1325	pNew->fFlags = 0; /** @todo add some kind of ad-hoc flag? */
1326
1327	pNew->pvR3 = NULL;
1328	#ifndef VBOX_WITH_NEW_PHYS_CODE
1329	pNew->paChunkR3Ptrs = NULL;
1330	#endif
1331
1332	uint32_t iPage = cPages;
1333	while (iPage-- > 0)
1334	PGM_PAGE_INIT_ZERO_REAL(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1335	Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1336
1337	/* update the page count stats. */
1338	pVM->pgm.s.cZeroPages += cPages;
1339	pVM->pgm.s.cAllPages += cPages;
1340
1341	/* link it */
1342	pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1343	}
1344
1345	/*
1346	* Register the access handler.
1347	*/
1348	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1349	pfnHandlerR3, pvUserR3,
1350	pfnHandlerR0, pvUserR0,
1351	pfnHandlerRC, pvUserRC, pszDesc);
1352	if ( RT_FAILURE(rc)
1353	&& !fRamExists)
1354	{
1355	pVM->pgm.s.cZeroPages -= cb >> PAGE_SHIFT;
1356	pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1357
1358	/* remove the ad-hoc range. */
1359	pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1360	pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1361	MMHyperFree(pVM, pRam);
1362	}
1363
1364	return rc;
1365	}
1366
1367
1368	/**
1369	* This is the interface IOM is using to register an MMIO region.
1370	*
1371	* It will take care of calling PGMHandlerPhysicalDeregister and clean up
1372	* any ad-hoc PGMRAMRANGE left behind.
1373	*
1374	* @returns VBox status code.
1375	* @param pVM Pointer to the shared VM structure.
1376	* @param GCPhys The start of the MMIO region.
1377	* @param cb The size of the MMIO region.
1378	*/
1379	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1380	{
1381	VM_ASSERT_EMT(pVM);
1382
1383	/*
1384	* First deregister the handler, then check if we should remove the ram range.
1385	*/
1386	int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1387	if (RT_SUCCESS(rc))
1388	{
1389	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1390	PPGMRAMRANGE pRamPrev = NULL;
1391	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1392	while (pRam && GCPhysLast >= pRam->GCPhys)
1393	{
1394	/** @todo We're being a bit too careful here. rewrite. */
1395	if ( GCPhysLast == pRam->GCPhysLast
1396	&& GCPhys == pRam->GCPhys)
1397	{
1398	Assert(pRam->cb == cb);
1399
1400	/*
1401	* See if all the pages are dead MMIO pages.
1402	*/
1403	uint32_t const cPages = cb >> PAGE_SHIFT;
1404	bool fAllMMIO = true;
1405	uint32_t iPage = 0;
1406	uint32_t cLeft = cPages;
1407	while (cLeft-- > 0)
1408	{
1409	PPGMPAGE pPage = &pRam->aPages[iPage];
1410	if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1411	/\|\| not-out-of-action later /)
1412	{
1413	fAllMMIO = false;
1414	#ifdef VBOX_WITH_NEW_PHYS_CODE
1415	Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1416	AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1417	#endif
1418	break;
1419	}
1420	Assert(PGM_PAGE_IS_ZERO(pPage));
1421	pPage++;
1422	}
1423	if (fAllMMIO)
1424	{
1425	/*
1426	* Ad-hoc range, unlink and free it.
1427	*/
1428	Log(("PGMR3PhysMMIODeregister: Freeing ad-hoc MMIO range for %RGp-%RGp %s\n",
1429	GCPhys, GCPhysLast, pRam->pszDesc));
1430
1431	pVM->pgm.s.cAllPages -= cPages;
1432	pVM->pgm.s.cZeroPages -= cPages;
1433
1434	pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1435	pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1436	MMHyperFree(pVM, pRam);
1437	break;
1438	}
1439	}
1440
1441	#ifdef VBOX_WITH_NEW_PHYS_CODE
1442	/*
1443	* Range match? It will all be within one range (see PGMAllHandler.cpp).
1444	*/
1445	if ( GCPhysLast >= pRam->GCPhys
1446	&& GCPhys <= pRam->GCPhysLast)
1447	{
1448	Assert(GCPhys >= pRam->GCPhys);
1449	Assert(GCPhysLast <= pRam->GCPhysLast);
1450
1451	/*
1452	* Turn the pages back into RAM pages.
1453	*/
1454	uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1455	uint32_t cLeft = cb >> PAGE_SHIFT;
1456	while (cLeft--)
1457	{
1458	PPGMPAGE pPage = &pRam->aPages[iPage];
1459	AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1460	AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1461	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
1462	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
1463	}
1464	break;
1465	}
1466	#endif
1467
1468	/* next */
1469	pRamPrev = pRam;
1470	pRam = pRam->pNextR3;
1471	}
1472	}
1473
1474	return rc;
1475	}
1476
1477
1478	/**
1479	* Locate a MMIO2 range.
1480	*
1481	* @returns Pointer to the MMIO2 range.
1482	* @param pVM Pointer to the shared VM structure.
1483	* @param pDevIns The device instance owning the region.
1484	* @param iRegion The region.
1485	*/
1486	DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1487	{
1488	/*
1489	* Search the list.
1490	*/
1491	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1492	if ( pCur->pDevInsR3 == pDevIns
1493	&& pCur->iRegion == iRegion)
1494	return pCur;
1495	return NULL;
1496	}
1497
1498
1499	/**
1500	* Allocate and register an MMIO2 region.
1501	*
1502	* As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
1503	* RAM associated with a device. It is also non-shared memory with a
1504	* permanent ring-3 mapping and page backing (presently).
1505	*
1506	* A MMIO2 range may overlap with base memory if a lot of RAM
1507	* is configured for the VM, in which case we'll drop the base
1508	* memory pages. Presently we will make no attempt to preserve
1509	* anything that happens to be present in the base memory that
1510	* is replaced, this is of course incorrectly but it's too much
1511	* effort.
1512	*
1513	* @returns VBox status code.
1514	* @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
1515	* @retval VERR_ALREADY_EXISTS if the region already exists.
1516	*
1517	* @param pVM Pointer to the shared VM structure.
1518	* @param pDevIns The device instance owning the region.
1519	* @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
1520	* this number has to be the number of that region. Otherwise
1521	* it can be any number safe UINT8_MAX.
1522	* @param cb The size of the region. Must be page aligned.
1523	* @param fFlags Reserved for future use, must be zero.
1524	* @param ppv Where to store the pointer to the ring-3 mapping of the memory.
1525	* @param pszDesc The description.
1526	*/
1527	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc)
1528	{
1529	/*
1530	* Validate input.
1531	*/
1532	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1533	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1534	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1535	AssertPtrReturn(ppv, VERR_INVALID_POINTER);
1536	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1537	AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1538	AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
1539	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1540	AssertReturn(cb, VERR_INVALID_PARAMETER);
1541	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1542
1543	const uint32_t cPages = cb >> PAGE_SHIFT;
1544	AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
1545	AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
1546
1547	/*
1548	* Try reserve and allocate the backing memory first as this is what is
1549	* most likely to fail.
1550	*/
1551	int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
1552	if (RT_FAILURE(rc))
1553	return rc;
1554
1555	void *pvPages;
1556	PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
1557	if (RT_SUCCESS(rc))
1558	rc = SUPR3PageAllocEx(cPages, 0 /fFlags/, &pvPages, NULL /pR0Ptr/, paPages);
1559	if (RT_SUCCESS(rc))
1560	{
1561	memset(pvPages, 0, cPages * PAGE_SIZE);
1562
1563	/*
1564	* Create the MMIO2 range record for it.
1565	*/
1566	const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
1567	PPGMMMIO2RANGE pNew;
1568	rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1569	AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
1570	if (RT_SUCCESS(rc))
1571	{
1572	pNew->pDevInsR3 = pDevIns;
1573	pNew->pvR3 = pvPages;
1574	//pNew->pNext = NULL;
1575	//pNew->fMapped = false;
1576	//pNew->fOverlapping = false;
1577	pNew->iRegion = iRegion;
1578	pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
1579	pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
1580	pNew->RamRange.GCPhys = NIL_RTGCPHYS;
1581	pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
1582	pNew->RamRange.pszDesc = pszDesc;
1583	pNew->RamRange.cb = cb;
1584	//pNew->RamRange.fFlags = 0; /// @todo MMIO2 flag?
1585
1586	pNew->RamRange.pvR3 = pvPages;
1587	#ifndef VBOX_WITH_NEW_PHYS_CODE
1588	pNew->RamRange.paChunkR3Ptrs = NULL;
1589	#endif
1590
1591	uint32_t iPage = cPages;
1592	while (iPage-- > 0)
1593	{
1594	PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1595	paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
1596	PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1597	}
1598
1599	/* update page count stats */
1600	pVM->pgm.s.cAllPages += cPages;
1601	pVM->pgm.s.cPrivatePages += cPages;
1602
1603	/*
1604	* Link it into the list.
1605	* Since there is no particular order, just push it.
1606	*/
1607	pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1608	pVM->pgm.s.pMmio2RangesR3 = pNew;
1609
1610	*ppv = pvPages;
1611	RTMemTmpFree(paPages);
1612	return VINF_SUCCESS;
1613	}
1614
1615	SUPR3PageFreeEx(pvPages, cPages);
1616	}
1617	RTMemTmpFree(paPages);
1618	MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1619	return rc;
1620	}
1621
1622
1623	/**
1624	* Deregisters and frees an MMIO2 region.
1625	*
1626	* Any physical (and virtual) access handlers registered for the region must
1627	* be deregistered before calling this function.
1628	*
1629	* @returns VBox status code.
1630	* @param pVM Pointer to the shared VM structure.
1631	* @param pDevIns The device instance owning the region.
1632	* @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1633	*/
1634	VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1635	{
1636	/*
1637	* Validate input.
1638	*/
1639	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1640	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1641	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1642
1643	int rc = VINF_SUCCESS;
1644	unsigned cFound = 0;
1645	PPGMMMIO2RANGE pPrev = NULL;
1646	PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1647	while (pCur)
1648	{
1649	if ( pCur->pDevInsR3 == pDevIns
1650	&& ( iRegion == UINT32_MAX
1651	\|\| pCur->iRegion == iRegion))
1652	{
1653	cFound++;
1654
1655	/*
1656	* Unmap it if it's mapped.
1657	*/
1658	if (pCur->fMapped)
1659	{
1660	int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1661	AssertRC(rc2);
1662	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1663	rc = rc2;
1664	}
1665
1666	/*
1667	* Unlink it
1668	*/
1669	PPGMMMIO2RANGE pNext = pCur->pNextR3;
1670	if (pPrev)
1671	pPrev->pNextR3 = pNext;
1672	else
1673	pVM->pgm.s.pMmio2RangesR3 = pNext;
1674	pCur->pNextR3 = NULL;
1675
1676	/*
1677	* Free the memory.
1678	*/
1679	int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1680	AssertRC(rc2);
1681	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1682	rc = rc2;
1683
1684	uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
1685	rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
1686	AssertRC(rc2);
1687	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1688	rc = rc2;
1689
1690	/* we're leaking hyper memory here if done at runtime. */
1691	Assert( VMR3GetState(pVM) == VMSTATE_OFF
1692	\|\| VMR3GetState(pVM) == VMSTATE_DESTROYING
1693	\|\| VMR3GetState(pVM) == VMSTATE_TERMINATED
1694	\|\| VMR3GetState(pVM) == VMSTATE_CREATING);
1695	/*rc = MMHyperFree(pVM, pCur);
1696	AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1697
1698
1699	/* update page count stats */
1700	pVM->pgm.s.cAllPages -= cPages;
1701	pVM->pgm.s.cPrivatePages -= cPages;
1702
1703	/* next */
1704	pCur = pNext;
1705	}
1706	else
1707	{
1708	pPrev = pCur;
1709	pCur = pCur->pNextR3;
1710	}
1711	}
1712
1713	return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
1714	}
1715
1716
1717	/**
1718	* Maps a MMIO2 region.
1719	*
1720	* This is done when a guest / the bios / state loading changes the
1721	* PCI config. The replacing of base memory has the same restrictions
1722	* as during registration, of course.
1723	*
1724	* @returns VBox status code.
1725	*
1726	* @param pVM Pointer to the shared VM structure.
1727	* @param pDevIns The
1728	*/
1729	VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1730	{
1731	/*
1732	* Validate input
1733	*/
1734	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1735	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1736	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1737	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1738	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1739	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1740
1741	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1742	AssertReturn(pCur, VERR_NOT_FOUND);
1743	AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
1744	Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
1745	Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
1746
1747	const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
1748	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1749
1750	/*
1751	* Find our location in the ram range list, checking for
1752	* restriction we don't bother implementing yet (partially overlapping).
1753	*/
1754	bool fRamExists = false;
1755	PPGMRAMRANGE pRamPrev = NULL;
1756	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1757	while (pRam && GCPhysLast >= pRam->GCPhys)
1758	{
1759	if ( GCPhys <= pRam->GCPhysLast
1760	&& GCPhysLast >= pRam->GCPhys)
1761	{
1762	/* completely within? */
1763	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1764	&& GCPhysLast <= pRam->GCPhysLast,
1765	("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
1766	GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
1767	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1768	VERR_PGM_RAM_CONFLICT);
1769	fRamExists = true;
1770	break;
1771	}
1772
1773	/* next */
1774	pRamPrev = pRam;
1775	pRam = pRam->pNextR3;
1776	}
1777	if (fRamExists)
1778	{
1779	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1780	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1781	while (cPagesLeft-- > 0)
1782	{
1783	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
1784	("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
1785	GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
1786	VERR_PGM_RAM_CONFLICT);
1787	pPage++;
1788	}
1789	}
1790	Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
1791	GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
1792
1793	/*
1794	* Make the changes.
1795	*/
1796	pgmLock(pVM);
1797
1798	pCur->RamRange.GCPhys = GCPhys;
1799	pCur->RamRange.GCPhysLast = GCPhysLast;
1800	pCur->fMapped = true;
1801	pCur->fOverlapping = fRamExists;
1802
1803	if (fRamExists)
1804	{
1805	/** @todo use pgmR3PhysFreePageRange here. */
1806	uint32_t cPendingPages = 0;
1807	PGMMFREEPAGESREQ pReq;
1808	int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1809	AssertLogRelRCReturn(rc, rc);
1810
1811	/* replace the pages, freeing all present RAM pages. */
1812	PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
1813	PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1814	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1815	while (cPagesLeft-- > 0)
1816	{
1817	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
1818	AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1819
1820	RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
1821	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
1822	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
1823	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
1824
1825	pVM->pgm.s.cZeroPages--;
1826	GCPhys += PAGE_SIZE;
1827	pPageSrc++;
1828	pPageDst++;
1829	}
1830
1831	if (cPendingPages)
1832	{
1833	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1834	AssertLogRelRCReturn(rc, rc);
1835	}
1836	GMMR3FreePagesCleanup(pReq);
1837	}
1838	else
1839	{
1840	/* link in the ram range */
1841	pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
1842	REMR3NotifyPhysRamRegister(pVM, GCPhys, pCur->RamRange.cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
1843	}
1844
1845	pgmUnlock(pVM);
1846
1847	return VINF_SUCCESS;
1848	}
1849
1850
1851	/**
1852	* Unmaps a MMIO2 region.
1853	*
1854	* This is done when a guest / the bios / state loading changes the
1855	* PCI config. The replacing of base memory has the same restrictions
1856	* as during registration, of course.
1857	*/
1858	VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1859	{
1860	/*
1861	* Validate input
1862	*/
1863	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1864	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1865	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1866	AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1867	AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1868	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1869
1870	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1871	AssertReturn(pCur, VERR_NOT_FOUND);
1872	AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
1873	AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
1874	Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
1875
1876	Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
1877	pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
1878
1879	/*
1880	* Unmap it.
1881	*/
1882	pgmLock(pVM);
1883
1884	if (pCur->fOverlapping)
1885	{
1886	/* Restore the RAM pages we've replaced. */
1887	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1888	while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
1889	pRam = pRam->pNextR3;
1890
1891	RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
1892	Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
1893	PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1894	uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1895	while (cPagesLeft-- > 0)
1896	{
1897	PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
1898	PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
1899	PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
1900	PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
1901
1902	pVM->pgm.s.cZeroPages++;
1903	pPageDst++;
1904	}
1905	}
1906	else
1907	{
1908	REMR3NotifyPhysRamDeregister(pVM, pCur->RamRange.GCPhys, pCur->RamRange.cb);
1909	pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
1910	}
1911
1912	pCur->RamRange.GCPhys = NIL_RTGCPHYS;
1913	pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
1914	pCur->fOverlapping = false;
1915	pCur->fMapped = false;
1916
1917	pgmUnlock(pVM);
1918
1919	return VINF_SUCCESS;
1920	}
1921
1922
1923	/**
1924	* Checks if the given address is an MMIO2 base address or not.
1925	*
1926	* @returns true/false accordingly.
1927	* @param pVM Pointer to the shared VM structure.
1928	* @param pDevIns The owner of the memory, optional.
1929	* @param GCPhys The address to check.
1930	*/
1931	VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
1932	{
1933	/*
1934	* Validate input
1935	*/
1936	VM_ASSERT_EMT_RETURN(pVM, false);
1937	AssertPtrReturn(pDevIns, false);
1938	AssertReturn(GCPhys != NIL_RTGCPHYS, false);
1939	AssertReturn(GCPhys != 0, false);
1940	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
1941
1942	/*
1943	* Search the list.
1944	*/
1945	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1946	if (pCur->RamRange.GCPhys == GCPhys)
1947	{
1948	Assert(pCur->fMapped);
1949	return true;
1950	}
1951	return false;
1952	}
1953
1954
1955	/**
1956	* Gets the HC physical address of a page in the MMIO2 region.
1957	*
1958	* This is API is intended for MMHyper and shouldn't be called
1959	* by anyone else...
1960	*
1961	* @returns VBox status code.
1962	* @param pVM Pointer to the shared VM structure.
1963	* @param pDevIns The owner of the memory, optional.
1964	* @param iRegion The region.
1965	* @param off The page expressed an offset into the MMIO2 region.
1966	* @param pHCPhys Where to store the result.
1967	*/
1968	VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
1969	{
1970	/*
1971	* Validate input
1972	*/
1973	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1974	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1975	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1976
1977	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1978	AssertReturn(pCur, VERR_NOT_FOUND);
1979	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1980
1981	PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
1982	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
1983	return VINF_SUCCESS;
1984	}
1985
1986
1987	/**
1988	* Maps a portion of an MMIO2 region into kernel space (host).
1989	*
1990	* The kernel mapping will become invalid when the MMIO2 memory is deregistered
1991	* or the VM is terminated.
1992	*
1993	* @return VBox status code.
1994	*
1995	* @param pVM Pointer to the shared VM structure.
1996	* @param pDevIns The device owning the MMIO2 memory.
1997	* @param iRegion The region.
1998	* @param off The offset into the region. Must be page aligned.
1999	* @param cb The number of bytes to map. Must be page aligned.
2000	* @param pszDesc Mapping description.
2001	* @param pR0Ptr Where to store the R0 address.
2002	*/
2003	VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2004	const char *pszDesc, PRTR0PTR pR0Ptr)
2005	{
2006	/*
2007	* Validate input.
2008	*/
2009	VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2010	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2011	AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2012
2013	PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2014	AssertReturn(pCur, VERR_NOT_FOUND);
2015	AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2016	AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2017	AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2018
2019	/*
2020	* Pass the request on to the support library/driver.
2021	*/
2022	int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2023
2024	return rc;
2025	}
2026
2027
2028	/**
2029	* Registers a ROM image.
2030	*
2031	* Shadowed ROM images requires double the amount of backing memory, so,
2032	* don't use that unless you have to. Shadowing of ROM images is process
2033	* where we can select where the reads go and where the writes go. On real
2034	* hardware the chipset provides means to configure this. We provide
2035	* PGMR3PhysProtectROM() for this purpose.
2036	*
2037	* A read-only copy of the ROM image will always be kept around while we
2038	* will allocate RAM pages for the changes on demand (unless all memory
2039	* is configured to be preallocated).
2040	*
2041	* @returns VBox status.
2042	* @param pVM VM Handle.
2043	* @param pDevIns The device instance owning the ROM.
2044	* @param GCPhys First physical address in the range.
2045	* Must be page aligned!
2046	* @param cbRange The size of the range (in bytes).
2047	* Must be page aligned!
2048	* @param pvBinary Pointer to the binary data backing the ROM image.
2049	* This must be exactly \a cbRange in size.
2050	* @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2051	* and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2052	* @param pszDesc Pointer to description string. This must not be freed.
2053	*
2054	* @remark There is no way to remove the rom, automatically on device cleanup or
2055	* manually from the device yet. This isn't difficult in any way, it's
2056	* just not something we expect to be necessary for a while.
2057	*/
2058	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2059	const void pvBinary, uint32_t fFlags, const char pszDesc)
2060	{
2061	Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2062	pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2063
2064	/*
2065	* Validate input.
2066	*/
2067	AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2068	AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2069	AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2070	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2071	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2072	AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2073	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2074	AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED \| PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2075	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2076
2077	const uint32_t cPages = cb >> PAGE_SHIFT;
2078
2079	/*
2080	* Find the ROM location in the ROM list first.
2081	*/
2082	PPGMROMRANGE pRomPrev = NULL;
2083	PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2084	while (pRom && GCPhysLast >= pRom->GCPhys)
2085	{
2086	if ( GCPhys <= pRom->GCPhysLast
2087	&& GCPhysLast >= pRom->GCPhys)
2088	AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2089	GCPhys, GCPhysLast, pszDesc,
2090	pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2091	VERR_PGM_RAM_CONFLICT);
2092	/* next */
2093	pRomPrev = pRom;
2094	pRom = pRom->pNextR3;
2095	}
2096
2097	/*
2098	* Find the RAM location and check for conflicts.
2099	*
2100	* Conflict detection is a bit different than for RAM
2101	* registration since a ROM can be located within a RAM
2102	* range. So, what we have to check for is other memory
2103	* types (other than RAM that is) and that we don't span
2104	* more than one RAM range (layz).
2105	*/
2106	bool fRamExists = false;
2107	PPGMRAMRANGE pRamPrev = NULL;
2108	PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2109	while (pRam && GCPhysLast >= pRam->GCPhys)
2110	{
2111	if ( GCPhys <= pRam->GCPhysLast
2112	&& GCPhysLast >= pRam->GCPhys)
2113	{
2114	/* completely within? */
2115	AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2116	&& GCPhysLast <= pRam->GCPhysLast,
2117	("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2118	GCPhys, GCPhysLast, pszDesc,
2119	pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2120	VERR_PGM_RAM_CONFLICT);
2121	fRamExists = true;
2122	break;
2123	}
2124
2125	/* next */
2126	pRamPrev = pRam;
2127	pRam = pRam->pNextR3;
2128	}
2129	if (fRamExists)
2130	{
2131	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2132	uint32_t cPagesLeft = cPages;
2133	while (cPagesLeft-- > 0)
2134	{
2135	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2136	("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2137	pRam->GCPhys + (RTGCPTR)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT,
2138	pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2139	Assert(PGM_PAGE_IS_ZERO(pPage));
2140	pPage++;
2141	}
2142	}
2143
2144	/*
2145	* Update the base memory reservation if necessary.
2146	*/
2147	uint32_t cExtraBaseCost = fRamExists ? cPages : 0;
2148	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2149	cExtraBaseCost += cPages;
2150	if (cExtraBaseCost)
2151	{
2152	int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2153	if (RT_FAILURE(rc))
2154	return rc;
2155	}
2156
2157	/*
2158	* Allocate memory for the virgin copy of the RAM.
2159	*/
2160	PGMMALLOCATEPAGESREQ pReq;
2161	int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2162	AssertRCReturn(rc, rc);
2163
2164	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2165	{
2166	pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2167	pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2168	pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2169	}
2170
2171	pgmLock(pVM);
2172	rc = GMMR3AllocatePagesPerform(pVM, pReq);
2173	pgmUnlock(pVM);
2174	if (RT_FAILURE(rc))
2175	{
2176	GMMR3AllocatePagesCleanup(pReq);
2177	return rc;
2178	}
2179
2180	/*
2181	* Allocate the new ROM range and RAM range (if necessary).
2182	*/
2183	PPGMROMRANGE pRomNew;
2184	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2185	if (RT_SUCCESS(rc))
2186	{
2187	PPGMRAMRANGE pRamNew = NULL;
2188	if (!fRamExists)
2189	rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2190	if (RT_SUCCESS(rc))
2191	{
2192	pgmLock(pVM);
2193
2194	/*
2195	* Initialize and insert the RAM range (if required).
2196	*/
2197	PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2198	if (!fRamExists)
2199	{
2200	pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2201	pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2202	pRamNew->GCPhys = GCPhys;
2203	pRamNew->GCPhysLast = GCPhysLast;
2204	pRamNew->cb = cb;
2205	pRamNew->pszDesc = pszDesc;
2206	pRamNew->fFlags = 0;
2207	pRamNew->pvR3 = NULL;
2208
2209	PPGMPAGE pPage = &pRamNew->aPages[0];
2210	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2211	{
2212	PGM_PAGE_INIT(pPage,
2213	pReq->aPages[iPage].HCPhysGCPhys,
2214	pReq->aPages[iPage].idPage,
2215	PGMPAGETYPE_ROM,
2216	PGM_PAGE_STATE_ALLOCATED);
2217
2218	pRomPage->Virgin = *pPage;
2219	}
2220
2221	pVM->pgm.s.cAllPages += cPages;
2222	pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2223	}
2224	else
2225	{
2226	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2227	for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2228	{
2229	PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2230	PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2231	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2232	PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2233
2234	pRomPage->Virgin = *pPage;
2235	}
2236
2237	pRamNew = pRam;
2238
2239	pVM->pgm.s.cZeroPages -= cPages;
2240	}
2241	pVM->pgm.s.cPrivatePages += cPages;
2242
2243	pgmUnlock(pVM);
2244
2245
2246	/*
2247	* !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2248	*
2249	* If it's shadowed we'll register the handler after the ROM notification
2250	* so we get the access handler callbacks that we should. If it isn't
2251	* shadowed we'll do it the other way around to make REM use the built-in
2252	* ROM behavior and not the handler behavior (which is to route all access
2253	* to PGM atm).
2254	*/
2255	if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2256	{
2257	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2258	rc = PGMR3HandlerPhysicalRegister(pVM,
2259	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2260	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2261	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2262	GCPhys, GCPhysLast,
2263	pgmR3PhysRomWriteHandler, pRomNew,
2264	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2265	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2266	}
2267	else
2268	{
2269	rc = PGMR3HandlerPhysicalRegister(pVM,
2270	fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2271	? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2272	: PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2273	GCPhys, GCPhysLast,
2274	pgmR3PhysRomWriteHandler, pRomNew,
2275	NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2276	NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2277	REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2278	}
2279	if (RT_SUCCESS(rc))
2280	{
2281	pgmLock(pVM);
2282
2283	/*
2284	* Copy the image over to the virgin pages.
2285	* This must be done after linking in the RAM range.
2286	*/
2287	PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2288	for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2289	{
2290	void *pvDstPage;
2291	PPGMPAGEMAP pMapIgnored;
2292	rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pMapIgnored, &pvDstPage);
2293	if (RT_FAILURE(rc))
2294	{
2295	VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2296	break;
2297	}
2298	memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2299	}
2300	if (RT_SUCCESS(rc))
2301	{
2302	/*
2303	* Initialize the ROM range.
2304	* Note that the Virgin member of the pages has already been initialized above.
2305	*/
2306	pRomNew->GCPhys = GCPhys;
2307	pRomNew->GCPhysLast = GCPhysLast;
2308	pRomNew->cb = cb;
2309	pRomNew->fFlags = fFlags;
2310	pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2311	pRomNew->pszDesc = pszDesc;
2312
2313	for (unsigned iPage = 0; iPage < cPages; iPage++)
2314	{
2315	PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2316	pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2317	PGM_PAGE_INIT_ZERO_REAL(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2318	}
2319
2320	/* update the page count stats */
2321	pVM->pgm.s.cZeroPages += cPages;
2322	pVM->pgm.s.cAllPages += cPages;
2323
2324	/*
2325	* Insert the ROM range, tell REM and return successfully.
2326	*/
2327	pRomNew->pNextR3 = pRom;
2328	pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2329	pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2330
2331	if (pRomPrev)
2332	{
2333	pRomPrev->pNextR3 = pRomNew;
2334	pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2335	pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2336	}
2337	else
2338	{
2339	pVM->pgm.s.pRomRangesR3 = pRomNew;
2340	pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2341	pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2342	}
2343
2344	GMMR3AllocatePagesCleanup(pReq);
2345	pgmUnlock(pVM);
2346	return VINF_SUCCESS;
2347	}
2348
2349	/* bail out */
2350
2351	pgmUnlock(pVM);
2352	int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2353	AssertRC(rc2);
2354	pgmLock(pVM);
2355	}
2356
2357	if (!fRamExists)
2358	{
2359	pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
2360	MMHyperFree(pVM, pRamNew);
2361	}
2362	}
2363	MMHyperFree(pVM, pRomNew);
2364	}
2365
2366	/** @todo Purge the mapping cache or something... */
2367	GMMR3FreeAllocatedPages(pVM, pReq);
2368	GMMR3AllocatePagesCleanup(pReq);
2369	pgmUnlock(pVM);
2370	return rc;
2371	}
2372
2373
2374	/**
2375	* \#PF Handler callback for ROM write accesses.
2376	*
2377	* @returns VINF_SUCCESS if the handler have carried out the operation.
2378	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2379	* @param pVM VM Handle.
2380	* @param GCPhys The physical address the guest is writing to.
2381	* @param pvPhys The HC mapping of that address.
2382	* @param pvBuf What the guest is reading/writing.
2383	* @param cbBuf How much it's reading/writing.
2384	* @param enmAccessType The access type.
2385	* @param pvUser User argument.
2386	*/
2387	static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
2388	{
2389	PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
2390	const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2391	Assert(iPage < (pRom->cb >> PAGE_SHIFT));
2392	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2393	Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
2394
2395	if (enmAccessType == PGMACCESSTYPE_READ)
2396	{
2397	switch (pRomPage->enmProt)
2398	{
2399	/*
2400	* Take the default action.
2401	*/
2402	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2403	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2404	case PGMROMPROT_READ_ROM_WRITE_RAM:
2405	case PGMROMPROT_READ_RAM_WRITE_RAM:
2406	return VINF_PGM_HANDLER_DO_DEFAULT;
2407
2408	default:
2409	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2410	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2411	VERR_INTERNAL_ERROR);
2412	}
2413	}
2414	else
2415	{
2416	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2417	switch (pRomPage->enmProt)
2418	{
2419	/*
2420	* Ignore writes.
2421	*/
2422	case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2423	case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2424	return VINF_SUCCESS;
2425
2426	/*
2427	* Write to the ram page.
2428	*/
2429	case PGMROMPROT_READ_ROM_WRITE_RAM:
2430	case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's way simpler that way. */
2431	{
2432	/* This should be impossible now, pvPhys doesn't work cross page anylonger. */
2433	Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
2434
2435	/*
2436	* Take the lock, do lazy allocation, map the page and copy the data.
2437	*
2438	* Note that we have to bypass the mapping TLB since it works on
2439	* guest physical addresses and entering the shadow page would
2440	* kind of screw things up...
2441	*/
2442	int rc = pgmLock(pVM);
2443	AssertRC(rc);
2444	PPGMPAGE pShadowPage = &pRomPage->Shadow;
2445	if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
2446	{
2447	pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2448	AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
2449	}
2450
2451	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(pShadowPage) != PGM_PAGE_STATE_ALLOCATED))
2452	{
2453	rc = pgmPhysPageMakeWritable(pVM, pShadowPage, GCPhys);
2454	if (RT_FAILURE(rc))
2455	{
2456	pgmUnlock(pVM);
2457	return rc;
2458	}
2459	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3 /* returned */, ("%Rrc\n", rc));
2460	}
2461
2462	void *pvDstPage;
2463	PPGMPAGEMAP pMapIgnored;
2464	int rc2 = pgmPhysPageMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pMapIgnored, &pvDstPage);
2465	if (RT_SUCCESS(rc2))
2466	memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
2467	else
2468	rc = rc2;
2469
2470	pgmUnlock(pVM);
2471	return rc;
2472	}
2473
2474	default:
2475	AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2476	pRom->aPages[iPage].enmProt, iPage, GCPhys),
2477	VERR_INTERNAL_ERROR);
2478	}
2479	}
2480	}
2481
2482
2483	/**
2484	* Called by PGMR3Reset to reset the shadow, switch to the virgin,
2485	* and verify that the virgin part is untouched.
2486	*
2487	* This is done after the normal memory has been cleared.
2488	*
2489	* ASSUMES that the caller owns the PGM lock.
2490	*
2491	* @param pVM The VM handle.
2492	*/
2493	int pgmR3PhysRomReset(PVM pVM)
2494	{
2495	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2496	{
2497	const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
2498
2499	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2500	{
2501	/*
2502	* Reset the physical handler.
2503	*/
2504	int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
2505	AssertRCReturn(rc, rc);
2506
2507	/*
2508	* What we do with the shadow pages depends on the memory
2509	* preallocation option. If not enabled, we'll just throw
2510	* out all the dirty pages and replace them by the zero page.
2511	*/
2512	if (!pVM->pgm.s.fRamPreAlloc)
2513	{
2514	/* Free the dirty pages. */
2515	uint32_t cPendingPages = 0;
2516	PGMMFREEPAGESREQ pReq;
2517	rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2518	AssertRCReturn(rc, rc);
2519
2520	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2521	if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
2522	{
2523	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
2524	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
2525	AssertLogRelRCReturn(rc, rc);
2526	}
2527
2528	if (cPendingPages)
2529	{
2530	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2531	AssertLogRelRCReturn(rc, rc);
2532	}
2533	GMMR3FreePagesCleanup(pReq);
2534	}
2535	else
2536	{
2537	/* clear all the shadow pages. */
2538	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2539	{
2540	Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO);
2541
2542	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2543	rc = pgmPhysPageMakeWritable(pVM, &pRom->aPages[iPage].Shadow, GCPhys);
2544	if (RT_FAILURE(rc))
2545	break;
2546
2547	void *pvDstPage;
2548	PPGMPAGEMAP pMapIgnored;
2549	rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pMapIgnored, &pvDstPage);
2550	if (RT_FAILURE(rc))
2551	break;
2552	ASMMemZeroPage(pvDstPage);
2553	}
2554	AssertRCReturn(rc, rc);
2555	}
2556	}
2557
2558	#ifdef VBOX_STRICT
2559	/*
2560	* Verify that the virgin page is unchanged if possible.
2561	*/
2562	if (pRom->pvOriginal)
2563	{
2564	uint8_t const pbSrcPage = (uint8_t const )pRom->pvOriginal;
2565	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
2566	{
2567	const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2568	PPGMPAGEMAP pMapIgnored;
2569	void *pvDstPage;
2570	int rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pMapIgnored, &pvDstPage);
2571	if (RT_FAILURE(rc))
2572	break;
2573	if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
2574	LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
2575	GCPhys, pRom->pszDesc));
2576	}
2577	}
2578	#endif
2579	}
2580
2581	return VINF_SUCCESS;
2582	}
2583
2584
2585	/**
2586	* Change the shadowing of a range of ROM pages.
2587	*
2588	* This is intended for implementing chipset specific memory registers
2589	* and will not be very strict about the input. It will silently ignore
2590	* any pages that are not the part of a shadowed ROM.
2591	*
2592	* @returns VBox status code.
2593	* @retval VINF_PGM_SYNC_CR3
2594	*
2595	* @param pVM Pointer to the shared VM structure.
2596	* @param GCPhys Where to start. Page aligned.
2597	* @param cb How much to change. Page aligned.
2598	* @param enmProt The new ROM protection.
2599	*/
2600	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
2601	{
2602	/*
2603	* Check input
2604	*/
2605	if (!cb)
2606	return VINF_SUCCESS;
2607	AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2608	AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2609	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2610	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2611	AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
2612
2613	/*
2614	* Process the request.
2615	*/
2616	int rc = VINF_SUCCESS;
2617	bool fFlushTLB = false;
2618	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2619	if ( GCPhys <= pRom->GCPhysLast
2620	&& GCPhysLast >= pRom->GCPhys
2621	&& (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
2622	{
2623	/*
2624	* Iterate the relevant pages and make necessary the changes.
2625	*/
2626	bool fChanges = false;
2627	uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
2628	? pRom->cb >> PAGE_SHIFT
2629	: (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
2630	for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2631	iPage < cPages;
2632	iPage++)
2633	{
2634	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2635	if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
2636	{
2637	fChanges = true;
2638
2639	/* flush references to the page. */
2640	PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2641	int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRamPage, &fFlushTLB);
2642	if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS \|\| RT_FAILURE(rc2)))
2643	rc = rc2;
2644
2645	PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2646	PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2647
2648	pOld = pRamPage;
2649	pRamPage = pNew;
2650	/** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2651	}
2652	pRomPage->enmProt = enmProt;
2653	}
2654
2655	/*
2656	* Reset the access handler if we made changes, no need
2657	* to optimize this.
2658	*/
2659	if (fChanges)
2660	{
2661	int rc = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2662	AssertRCReturn(rc, rc);
2663	}
2664
2665	/* Advance - cb isn't updated. */
2666	GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
2667	}
2668
2669	if (fFlushTLB)
2670	PGM_INVL_GUEST_TLBS();
2671	return rc;
2672	}
2673
2674	#ifndef VBOX_WITH_NEW_PHYS_CODE
2675
2676	/**
2677	* Interface that the MMR3RamRegister(), MMR3RomRegister() and MMIO handler
2678	* registration APIs calls to inform PGM about memory registrations.
2679	*
2680	* It registers the physical memory range with PGM. MM is responsible
2681	* for the toplevel things - allocation and locking - while PGM is taking
2682	* care of all the details and implements the physical address space virtualization.
2683	*
2684	* @returns VBox status.
2685	* @param pVM The VM handle.
2686	* @param pvRam HC virtual address of the RAM range. (page aligned)
2687	* @param GCPhys GC physical address of the RAM range. (page aligned)
2688	* @param cb Size of the RAM range. (page aligned)
2689	* @param fFlags Flags, MM_RAM_*.
2690	* @param paPages Pointer an array of physical page descriptors.
2691	* @param pszDesc Description string.
2692	*/
2693	VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE paPages, const char *pszDesc)
2694	{
2695	/*
2696	* Validate input.
2697	* (Not so important because callers are only MMR3PhysRegister()
2698	* and PGMR3HandlerPhysicalRegisterEx(), but anyway...)
2699	*/
2700	Log(("PGMR3PhysRegister %08X %x bytes flags %x %s\n", GCPhys, cb, fFlags, pszDesc));
2701
2702	Assert((fFlags & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_DYNAMIC_ALLOC)) \|\| paPages);
2703	/Assert(!(fFlags & MM_RAM_FLAGS_RESERVED) \|\| !paPages);/
2704	Assert((fFlags == (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_MMIO)) \|\| (fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) \|\| pvRam);
2705	/Assert(!(fFlags & MM_RAM_FLAGS_RESERVED) \|\| !pvRam);/
2706	Assert(!(fFlags & ~0xfff));
2707	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
2708	Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
2709	Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2 \| MM_RAM_FLAGS_DYNAMIC_ALLOC)));
2710	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2711	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2712	if (GCPhysLast < GCPhys)
2713	{
2714	AssertMsgFailed(("The range wraps! GCPhys=%RGp cb=%#x\n", GCPhys, cb));
2715	return VERR_INVALID_PARAMETER;
2716	}
2717
2718	/*
2719	* Find range location and check for conflicts.
2720	*/
2721	PPGMRAMRANGE pPrev = NULL;
2722	PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
2723	while (pCur)
2724	{
2725	if (GCPhys <= pCur->GCPhysLast && GCPhysLast >= pCur->GCPhys)
2726	{
2727	AssertMsgFailed(("Conflict! This cannot happen!\n"));
2728	return VERR_PGM_RAM_CONFLICT;
2729	}
2730	if (GCPhysLast < pCur->GCPhys)
2731	break;
2732
2733	/* next */
2734	pPrev = pCur;
2735	pCur = pCur->pNextR3;
2736	}
2737
2738	/*
2739	* Allocate RAM range.
2740	* Small ranges are allocated from the heap, big ones have separate mappings.
2741	*/
2742	size_t cbRam = RT_OFFSETOF(PGMRAMRANGE, aPages[cb >> PAGE_SHIFT]);
2743	PPGMRAMRANGE pNew;
2744	int rc = VERR_NO_MEMORY;
2745	if (cbRam > PAGE_SIZE / 2)
2746	{ /* large */
2747	cbRam = RT_ALIGN_Z(cbRam, PAGE_SIZE);
2748	rc = MMR3HyperAllocOnceNoRel(pVM, cbRam, PAGE_SIZE, MM_TAG_PGM_PHYS, (void **)&pNew);
2749	AssertMsgRC(rc, ("MMR3HyperAllocOnceNoRel(,%#x,,) -> %Rrc\n", cbRam, rc));
2750	}
2751	else
2752	{ /* small */
2753	rc = MMHyperAlloc(pVM, cbRam, 16, MM_TAG_PGM, (void **)&pNew);
2754	AssertMsgRC(rc, ("MMHyperAlloc(,%#x,,,) -> %Rrc\n", cbRam, rc));
2755	}
2756	if (RT_SUCCESS(rc))
2757	{
2758	/*
2759	* Initialize the range.
2760	*/
2761	pNew->pvR3 = pvRam;
2762	pNew->GCPhys = GCPhys;
2763	pNew->GCPhysLast = GCPhysLast;
2764	pNew->cb = cb;
2765	pNew->fFlags = fFlags;
2766	pNew->paChunkR3Ptrs = NULL;
2767
2768	unsigned iPage = (unsigned)(cb >> PAGE_SHIFT);
2769	if (paPages)
2770	{
2771	while (iPage-- > 0)
2772	{
2773	PGM_PAGE_INIT(&pNew->aPages[iPage], paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
2774	fFlags & MM_RAM_FLAGS_MMIO2 ? PGMPAGETYPE_MMIO2 : PGMPAGETYPE_RAM,
2775	PGM_PAGE_STATE_ALLOCATED);
2776	pNew->aPages[iPage].HCPhys \|= fFlags; /** @todo PAGE FLAGS*/
2777	}
2778	}
2779	else if (fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2780	{
2781	/* Allocate memory for chunk to HC ptr lookup array. */
2782	rc = MMHyperAlloc(pVM, (cb >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(void ), 16, MM_TAG_PGM, (void *)&pNew->paChunkR3Ptrs);
2783	AssertMsgReturn(rc == VINF_SUCCESS, ("MMHyperAlloc(,%#x,,,) -> %Rrc\n", cbRam, cb), rc);
2784
2785	/* Physical memory will be allocated on demand. */
2786	while (iPage-- > 0)
2787	{
2788	PGM_PAGE_INIT(&pNew->aPages[iPage], 0, NIL_GMM_PAGEID, PGMPAGETYPE_RAM, PGM_PAGE_STATE_ZERO);
2789	pNew->aPages[iPage].HCPhys = fFlags; /** @todo PAGE FLAGS */
2790	}
2791	}
2792	else
2793	{
2794	Assert(fFlags == (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_MMIO));
2795	RTHCPHYS HCPhysDummyPage = MMR3PageDummyHCPhys(pVM);
2796	while (iPage-- > 0)
2797	{
2798	PGM_PAGE_INIT(&pNew->aPages[iPage], HCPhysDummyPage, NIL_GMM_PAGEID, PGMPAGETYPE_MMIO, PGM_PAGE_STATE_ZERO);
2799	pNew->aPages[iPage].HCPhys \|= fFlags; /** @todo PAGE FLAGS*/
2800	}
2801	}
2802
2803	/*
2804	* Insert the new RAM range.
2805	*/
2806	pgmLock(pVM);
2807	pNew->pNextR3 = pCur;
2808	pNew->pNextR0 = pCur ? MMHyperCCToR0(pVM, pCur) : NIL_RTR0PTR;
2809	pNew->pNextRC = pCur ? MMHyperCCToRC(pVM, pCur) : NIL_RTRCPTR;
2810	if (pPrev)
2811	{
2812	pPrev->pNextR3 = pNew;
2813	pPrev->pNextR0 = MMHyperCCToR0(pVM, pNew);
2814	pPrev->pNextRC = MMHyperCCToRC(pVM, pNew);
2815	}
2816	else
2817	{
2818	pVM->pgm.s.pRamRangesR3 = pNew;
2819	pVM->pgm.s.pRamRangesR0 = MMHyperCCToR0(pVM, pNew);
2820	pVM->pgm.s.pRamRangesRC = MMHyperCCToRC(pVM, pNew);
2821	}
2822	pgmUnlock(pVM);
2823	}
2824	return rc;
2825	}
2826
2827
2828	/**
2829	* Register a chunk of a the physical memory range with PGM. MM is responsible
2830	* for the toplevel things - allocation and locking - while PGM is taking
2831	* care of all the details and implements the physical address space virtualization.
2832	*
2833	*
2834	* @returns VBox status.
2835	* @param pVM The VM handle.
2836	* @param pvRam HC virtual address of the RAM range. (page aligned)
2837	* @param GCPhys GC physical address of the RAM range. (page aligned)
2838	* @param cb Size of the RAM range. (page aligned)
2839	* @param fFlags Flags, MM_RAM_*.
2840	* @param paPages Pointer an array of physical page descriptors.
2841	* @param pszDesc Description string.
2842	*/
2843	VMMR3DECL(int) PGMR3PhysRegisterChunk(PVM pVM, void pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE paPages, const char *pszDesc)
2844	{
2845	NOREF(pszDesc);
2846
2847	/*
2848	* Validate input.
2849	* (Not so important because callers are only MMR3PhysRegister()
2850	* and PGMR3HandlerPhysicalRegisterEx(), but anyway...)
2851	*/
2852	Log(("PGMR3PhysRegisterChunk %08X %x bytes flags %x %s\n", GCPhys, cb, fFlags, pszDesc));
2853
2854	Assert(paPages);
2855	Assert(pvRam);
2856	Assert(!(fFlags & ~0xfff));
2857	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
2858	Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
2859	Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2 \| MM_RAM_FLAGS_DYNAMIC_ALLOC)));
2860	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2861	Assert(VM_IS_EMT(pVM));
2862	Assert(!(GCPhys & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2863	Assert(cb == PGM_DYNAMIC_CHUNK_SIZE);
2864
2865	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2866	if (GCPhysLast < GCPhys)
2867	{
2868	AssertMsgFailed(("The range wraps! GCPhys=%RGp cb=%#x\n", GCPhys, cb));
2869	return VERR_INVALID_PARAMETER;
2870	}
2871
2872	/*
2873	* Find existing range location.
2874	*/
2875	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2876	while (pRam)
2877	{
2878	RTGCPHYS off = GCPhys - pRam->GCPhys;
2879	if ( off < pRam->cb
2880	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC))
2881	break;
2882
2883	pRam = pRam->CTX_SUFF(pNext);
2884	}
2885	AssertReturn(pRam, VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS);
2886
2887	unsigned off = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2888	unsigned iPage = (unsigned)(cb >> PAGE_SHIFT);
2889	if (paPages)
2890	{
2891	while (iPage-- > 0)
2892	pRam->aPages[off + iPage].HCPhys = (paPages[iPage].Phys & X86_PTE_PAE_PG_MASK) \| fFlags; /** @todo PAGE FLAGS */
2893	}
2894	off >>= (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
2895	pRam->paChunkR3Ptrs[off] = (uintptr_t)pvRam;
2896
2897	/* Notify the recompiler. */
2898	REMR3NotifyPhysRamChunkRegister(pVM, GCPhys, PGM_DYNAMIC_CHUNK_SIZE, (RTHCUINTPTR)pvRam, fFlags);
2899
2900	return VINF_SUCCESS;
2901	}
2902
2903
2904	/**
2905	* Allocate missing physical pages for an existing guest RAM range.
2906	*
2907	* @returns VBox status.
2908	* @param pVM The VM handle.
2909	* @param GCPhys GC physical address of the RAM range. (page aligned)
2910	*/
2911	VMMR3DECL(int) PGM3PhysGrowRange(PVM pVM, PCRTGCPHYS pGCPhys)
2912	{
2913	RTGCPHYS GCPhys = *pGCPhys;
2914
2915	/*
2916	* Walk range list.
2917	*/
2918	pgmLock(pVM);
2919
2920	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2921	while (pRam)
2922	{
2923	RTGCPHYS off = GCPhys - pRam->GCPhys;
2924	if ( off < pRam->cb
2925	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC))
2926	{
2927	bool fRangeExists = false;
2928	unsigned off = (GCPhys - pRam->GCPhys) >> PGM_DYNAMIC_CHUNK_SHIFT;
2929
2930	/* Note: A request made from another thread may end up in EMT after somebody else has already allocated the range. */
2931	if (pRam->paChunkR3Ptrs[off])
2932	fRangeExists = true;
2933
2934	pgmUnlock(pVM);
2935	if (fRangeExists)
2936	return VINF_SUCCESS;
2937	return pgmr3PhysGrowRange(pVM, GCPhys);
2938	}
2939
2940	pRam = pRam->CTX_SUFF(pNext);
2941	}
2942	pgmUnlock(pVM);
2943	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2944	}
2945
2946
2947	/**
2948	* Allocate missing physical pages for an existing guest RAM range.
2949	*
2950	* @returns VBox status.
2951	* @param pVM The VM handle.
2952	* @param pRamRange RAM range
2953	* @param GCPhys GC physical address of the RAM range. (page aligned)
2954	*/
2955	int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys)
2956	{
2957	void *pvRam;
2958	int rc;
2959
2960	/* We must execute this function in the EMT thread, otherwise we'll run into problems. */
2961	if (!VM_IS_EMT(pVM))
2962	{
2963	PVMREQ pReq;
2964	const RTGCPHYS GCPhysParam = GCPhys;
2965
2966	AssertMsg(!PDMCritSectIsOwner(&pVM->pgm.s.CritSect), ("We own the PGM lock -> deadlock danger!!\n"));
2967
2968	rc = VMR3ReqCall(pVM, VMREQDEST_ANY, &pReq, RT_INDEFINITE_WAIT, (PFNRT)PGM3PhysGrowRange, 2, pVM, &GCPhysParam);
2969	if (RT_SUCCESS(rc))
2970	{
2971	rc = pReq->iStatus;
2972	VMR3ReqFree(pReq);
2973	}
2974	return rc;
2975	}
2976
2977	/* Round down to chunk boundary */
2978	GCPhys = GCPhys & PGM_DYNAMIC_CHUNK_BASE_MASK;
2979
2980	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DynRamGrow);
2981	STAM_COUNTER_ADD(&pVM->pgm.s.StatR3DynRamTotal, PGM_DYNAMIC_CHUNK_SIZE/(1024*1024));
2982
2983	Log(("pgmr3PhysGrowRange: allocate chunk of size 0x%X at %RGp\n", PGM_DYNAMIC_CHUNK_SIZE, GCPhys));
2984
2985	unsigned cPages = PGM_DYNAMIC_CHUNK_SIZE >> PAGE_SHIFT;
2986
2987	for (;;)
2988	{
2989	rc = SUPPageAlloc(cPages, &pvRam);
2990	if (RT_SUCCESS(rc))
2991	{
2992	rc = MMR3PhysRegisterEx(pVM, pvRam, GCPhys, PGM_DYNAMIC_CHUNK_SIZE, 0, MM_PHYS_TYPE_DYNALLOC_CHUNK, "Main Memory");
2993	if (RT_SUCCESS(rc))
2994	return rc;
2995
2996	SUPPageFree(pvRam, cPages);
2997	}
2998
2999	VMSTATE enmVMState = VMR3GetState(pVM);
3000	if (enmVMState != VMSTATE_RUNNING)
3001	{
3002	AssertMsgFailed(("Out of memory while trying to allocate a guest RAM chunk at %RGp!\n", GCPhys));
3003	LogRel(("PGM: Out of memory while trying to allocate a guest RAM chunk at %RGp (VMstate=%s)!\n", GCPhys, VMR3GetStateName(enmVMState)));
3004	return rc;
3005	}
3006
3007	LogRel(("pgmr3PhysGrowRange: out of memory. pause until the user resumes execution.\n"));
3008
3009	/* Pause first, then inform Main. */
3010	rc = VMR3SuspendNoSave(pVM);
3011	AssertRC(rc);
3012
3013	VMSetRuntimeError(pVM, false, "HostMemoryLow", "Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM");
3014
3015	/* Wait for resume event; will only return in that case. If the VM is stopped, the EMT thread will be destroyed. */
3016	rc = VMR3WaitForResume(pVM);
3017
3018	/* Retry */
3019	LogRel(("pgmr3PhysGrowRange: VM execution resumed -> retry.\n"));
3020	}
3021	}
3022
3023
3024	/**
3025	* Interface MMR3RomRegister() and MMR3PhysReserve calls to update the
3026	* flags of existing RAM ranges.
3027	*
3028	* @returns VBox status.
3029	* @param pVM The VM handle.
3030	* @param GCPhys GC physical address of the RAM range. (page aligned)
3031	* @param cb Size of the RAM range. (page aligned)
3032	* @param fFlags The Or flags, MM_RAM_* \#defines.
3033	* @param fMask The and mask for the flags.
3034	*/
3035	VMMR3DECL(int) PGMR3PhysSetFlags(PVM pVM, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, unsigned fMask)
3036	{
3037	Log(("PGMR3PhysSetFlags %08X %x %x %x\n", GCPhys, cb, fFlags, fMask));
3038
3039	/*
3040	* Validate input.
3041	* (Not so important because caller is always MMR3RomRegister() and MMR3PhysReserve(), but anyway...)
3042	*/
3043	Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2)));
3044	Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
3045	Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
3046	RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
3047	AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
3048
3049	/*
3050	* Lookup the range.
3051	*/
3052	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
3053	while (pRam && GCPhys > pRam->GCPhysLast)
3054	pRam = pRam->CTX_SUFF(pNext);
3055	if ( !pRam
3056	\|\| GCPhys > pRam->GCPhysLast
3057	\|\| GCPhysLast < pRam->GCPhys)
3058	{
3059	AssertMsgFailed(("No RAM range for %RGp-%RGp\n", GCPhys, GCPhysLast));
3060	return VERR_INVALID_PARAMETER;
3061	}
3062
3063	/*
3064	* Update the requested flags.
3065	*/
3066	RTHCPHYS fFullMask = ~(RTHCPHYS)(MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2)
3067	\| fMask;
3068	unsigned iPageEnd = (GCPhysLast - pRam->GCPhys + 1) >> PAGE_SHIFT;
3069	unsigned iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
3070	for ( ; iPage < iPageEnd; iPage++)
3071	pRam->aPages[iPage].HCPhys = (pRam->aPages[iPage].HCPhys & fFullMask) \| fFlags; /** @todo PAGE FLAGS */
3072
3073	return VINF_SUCCESS;
3074	}
3075
3076	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3077
3078	/**
3079	* Sets the Address Gate 20 state.
3080	*
3081	* @param pVM VM handle.
3082	* @param fEnable True if the gate should be enabled.
3083	* False if the gate should be disabled.
3084	*/
3085	VMMDECL(void) PGMR3PhysSetA20(PVM pVM, bool fEnable)
3086	{
3087	LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVM->pgm.s.fA20Enabled));
3088	if (pVM->pgm.s.fA20Enabled != fEnable)
3089	{
3090	pVM->pgm.s.fA20Enabled = fEnable;
3091	pVM->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
3092	REMR3A20Set(pVM, fEnable);
3093	/** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
3094	}
3095	}
3096
3097
3098	/**
3099	* Tree enumeration callback for dealing with age rollover.
3100	* It will perform a simple compression of the current age.
3101	*/
3102	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
3103	{
3104	/* Age compression - ASSUMES iNow == 4. */
3105	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3106	if (pChunk->iAge >= UINT32_C(0xffffff00))
3107	pChunk->iAge = 3;
3108	else if (pChunk->iAge >= UINT32_C(0xfffff000))
3109	pChunk->iAge = 2;
3110	else if (pChunk->iAge)
3111	pChunk->iAge = 1;
3112	else /* iAge = 0 */
3113	pChunk->iAge = 4;
3114
3115	/* reinsert */
3116	PVM pVM = (PVM)pvUser;
3117	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
3118	pChunk->AgeCore.Key = pChunk->iAge;
3119	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3120	return 0;
3121	}
3122
3123
3124	/**
3125	* Tree enumeration callback that updates the chunks that have
3126	* been used since the last
3127	*/
3128	static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
3129	{
3130	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
3131	if (!pChunk->iAge)
3132	{
3133	PVM pVM = (PVM)pvUser;
3134	RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
3135	pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
3136	RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3137	}
3138
3139	return 0;
3140	}
3141
3142
3143	/**
3144	* Performs ageing of the ring-3 chunk mappings.
3145	*
3146	* @param pVM The VM handle.
3147	*/
3148	VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
3149	{
3150	pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
3151	pVM->pgm.s.ChunkR3Map.iNow++;
3152	if (pVM->pgm.s.ChunkR3Map.iNow == 0)
3153	{
3154	pVM->pgm.s.ChunkR3Map.iNow = 4;
3155	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
3156	}
3157	else
3158	RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingCallback, pVM);
3159	}
3160
3161
3162	/**
3163	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
3164	*/
3165	typedef struct PGMR3PHYSCHUNKUNMAPCB
3166	{
3167	PVM pVM; /*< The VM handle. /
3168	PPGMCHUNKR3MAP pChunk; /*< The chunk to unmap. /
3169	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
3170
3171
3172	/**
3173	* Callback used to find the mapping that's been unused for
3174	* the longest time.
3175	*/
3176	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
3177	{
3178	do
3179	{
3180	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
3181	if ( pChunk->iAge
3182	&& !pChunk->cRefs)
3183	{
3184	/*
3185	* Check that it's not in any of the TLBs.
3186	*/
3187	PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
3188	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3189	if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
3190	{
3191	pChunk = NULL;
3192	break;
3193	}
3194	if (pChunk)
3195	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
3196	if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
3197	{
3198	pChunk = NULL;
3199	break;
3200	}
3201	if (pChunk)
3202	{
3203	((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
3204	return 1; /* done */
3205	}
3206	}
3207
3208	/* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
3209	pNode = pNode->pList;
3210	} while (pNode);
3211	return 0;
3212	}
3213
3214
3215	/**
3216	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
3217	*
3218	* The candidate will not be part of any TLBs, so no need to flush
3219	* anything afterwards.
3220	*
3221	* @returns Chunk id.
3222	* @param pVM The VM handle.
3223	*/
3224	static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
3225	{
3226	/*
3227	* Do tree ageing first?
3228	*/
3229	if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
3230	PGMR3PhysChunkAgeing(pVM);
3231
3232	/*
3233	* Enumerate the age tree starting with the left most node.
3234	*/
3235	PGMR3PHYSCHUNKUNMAPCB Args;
3236	Args.pVM = pVM;
3237	Args.pChunk = NULL;
3238	if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
3239	return Args.pChunk->Core.Key;
3240	return INT32_MAX;
3241	}
3242
3243
3244	/**
3245	* Maps the given chunk into the ring-3 mapping cache.
3246	*
3247	* This will call ring-0.
3248	*
3249	* @returns VBox status code.
3250	* @param pVM The VM handle.
3251	* @param idChunk The chunk in question.
3252	* @param ppChunk Where to store the chunk tracking structure.
3253	*
3254	* @remarks Called from within the PGM critical section.
3255	*/
3256	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
3257	{
3258	int rc;
3259	/*
3260	* Allocate a new tracking structure first.
3261	*/
3262	#if 0 /* for later when we've got a separate mapping method for ring-0. */
3263	PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
3264	AssertReturn(pChunk, VERR_NO_MEMORY);
3265	#else
3266	PPGMCHUNKR3MAP pChunk;
3267	rc = MMHyperAlloc(pVM, sizeof(pChunk), 0, MM_TAG_PGM_CHUNK_MAPPING, (void *)&pChunk);
3268	AssertRCReturn(rc, rc);
3269	#endif
3270	pChunk->Core.Key = idChunk;
3271	pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
3272	pChunk->iAge = 0;
3273	pChunk->cRefs = 0;
3274	pChunk->cPermRefs = 0;
3275	pChunk->pv = NULL;
3276
3277	/*
3278	* Request the ring-0 part to map the chunk in question and if
3279	* necessary unmap another one to make space in the mapping cache.
3280	*/
3281	GMMMAPUNMAPCHUNKREQ Req;
3282	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
3283	Req.Hdr.cbReq = sizeof(Req);
3284	Req.pvR3 = NULL;
3285	Req.idChunkMap = idChunk;
3286	Req.idChunkUnmap = NIL_GMM_CHUNKID;
3287	if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
3288	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
3289	rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
3290	if (RT_SUCCESS(rc))
3291	{
3292	/*
3293	* Update the tree.
3294	*/
3295	/* insert the new one. */
3296	AssertPtr(Req.pvR3);
3297	pChunk->pv = Req.pvR3;
3298	bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
3299	AssertRelease(fRc);
3300	pVM->pgm.s.ChunkR3Map.c++;
3301
3302	fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
3303	AssertRelease(fRc);
3304
3305	/* remove the unmapped one. */
3306	if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
3307	{
3308	PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
3309	AssertRelease(pUnmappedChunk);
3310	pUnmappedChunk->pv = NULL;
3311	pUnmappedChunk->Core.Key = UINT32_MAX;
3312	#if 0 /* for later when we've got a separate mapping method for ring-0. */
3313	MMR3HeapFree(pUnmappedChunk);
3314	#else
3315	MMHyperFree(pVM, pUnmappedChunk);
3316	#endif
3317	pVM->pgm.s.ChunkR3Map.c--;
3318	}
3319	}
3320	else
3321	{
3322	AssertRC(rc);
3323	#if 0 /* for later when we've got a separate mapping method for ring-0. */
3324	MMR3HeapFree(pChunk);
3325	#else
3326	MMHyperFree(pVM, pChunk);
3327	#endif
3328	pChunk = NULL;
3329	}
3330
3331	*ppChunk = pChunk;
3332	return rc;
3333	}
3334
3335
3336	/**
3337	* For VMMCALLHOST_PGM_MAP_CHUNK, considered internal.
3338	*
3339	* @returns see pgmR3PhysChunkMap.
3340	* @param pVM The VM handle.
3341	* @param idChunk The chunk to map.
3342	*/
3343	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
3344	{
3345	PPGMCHUNKR3MAP pChunk;
3346	return pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
3347	}
3348
3349
3350	/**
3351	* Invalidates the TLB for the ring-3 mapping cache.
3352	*
3353	* @param pVM The VM handle.
3354	*/
3355	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3356	{
3357	pgmLock(pVM);
3358	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3359	{
3360	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3361	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3362	}
3363	pgmUnlock(pVM);
3364	}
3365
3366
3367	/**
3368	* Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES.
3369	*
3370	* @returns The following VBox status codes.
3371	* @retval VINF_SUCCESS on success. FF cleared.
3372	* @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in this case.
3373	*
3374	* @param pVM The VM handle.
3375	*/
3376	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3377	{
3378	pgmLock(pVM);
3379
3380	/*
3381	* Allocate more pages, noting down the index of the first new page.
3382	*/
3383	uint32_t iClear = pVM->pgm.s.cHandyPages;
3384	AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3385	Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3386	int rcAlloc = VINF_SUCCESS;
3387	int rcSeed = VINF_SUCCESS;
3388	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3389	while (rc == VERR_GMM_SEED_ME)
3390	{
3391	void *pvChunk;
3392	rcAlloc = rc = SUPPageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3393	if (RT_SUCCESS(rc))
3394	{
3395	rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3396	if (RT_FAILURE(rc))
3397	SUPPageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3398	}
3399	if (RT_SUCCESS(rc))
3400	rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3401	}
3402
3403	/*
3404	* Clear the pages.
3405	*/
3406	if (RT_SUCCESS(rc))
3407	{
3408	while (iClear < pVM->pgm.s.cHandyPages)
3409	{
3410	PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3411	void *pv;
3412	rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3413	AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
3414	ASMMemZeroPage(pv);
3415	iClear++;
3416	Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3417	}
3418
3419	VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3420	}
3421	else
3422	{
3423	LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3424	" cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3425	rc, rcSeed, rcAlloc,
3426	pVM->pgm.s.cHandyPages,
3427	pVM->pgm.s.cAllPages,
3428	pVM->pgm.s.cPrivatePages,
3429	pVM->pgm.s.cSharedPages,
3430	pVM->pgm.s.cZeroPages));
3431	#if 1
3432	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3433	{
3434	LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3435	i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3436	pVM->pgm.s.aHandyPages[i].idSharedPage));
3437	uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3438	if (idPage != NIL_GMM_PAGEID)
3439	{
3440	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3441	pRam;
3442	pRam = pRam->pNextR3)
3443	{
3444	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3445	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3446	if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3447	LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3448	pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3449	}
3450	}
3451	}
3452	#endif
3453	rc = VERR_EM_NO_MEMORY;
3454	//rc = VINF_EM_NO_MEMORY;
3455	//VM_FF_SET(pVM, VM_FF_PGM_WE_ARE_SCREWED?);
3456	}
3457
3458	/** @todo Do proper VERR_EM_NO_MEMORY reporting. */
3459	AssertMsg( pVM->pgm.s.cHandyPages == RT_ELEMENTS(pVM->pgm.s.aHandyPages)
3460	\|\| rc != VINF_SUCCESS, ("%d rc=%Rrc\n", pVM->pgm.s.cHandyPages, rc));
3461
3462	pgmUnlock(pVM);
3463	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_NO_MEMORY \|\| rc == VERR_EM_NO_MEMORY);
3464	return rc;
3465	}
3466
3467
3468	/**
3469	* Frees the specified RAM page and replaces it with the ZERO page.
3470	*
3471	* This is used by ballooning, remapping MMIO2 and RAM reset.
3472	*
3473	* @param pVM Pointer to the shared VM structure.
3474	* @param pReq Pointer to the request.
3475	* @param pPage Pointer to the page structure.
3476	* @param GCPhys The guest physical address of the page, if applicable.
3477	*
3478	* @remarks The caller must own the PGM lock.
3479	*/
3480	static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3481	{
3482	/*
3483	* Assert sanity.
3484	*/
3485	Assert(PDMCritSectIsOwner(&pVM->pgm.s.CritSect));
3486	if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3487	&& PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3488	{
3489	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3490	return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3491	}
3492
3493	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO)
3494	return VINF_SUCCESS;
3495
3496	const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
3497	Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
3498	if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
3499	\|\| idPage > GMM_PAGEID_LAST
3500	\|\| PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
3501	{
3502	AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3503	return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
3504	}
3505
3506	/* update page count stats. */
3507	if (PGM_PAGE_IS_SHARED(pPage))
3508	pVM->pgm.s.cSharedPages--;
3509	else
3510	pVM->pgm.s.cPrivatePages--;
3511	pVM->pgm.s.cZeroPages++;
3512
3513	/*
3514	* pPage = ZERO page.
3515	*/
3516	PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
3517	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
3518	PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
3519
3520	/*
3521	* Make sure it's not in the handy page array.
3522	*/
3523	uint32_t i = pVM->pgm.s.cHandyPages;
3524	while (i < RT_ELEMENTS(pVM->pgm.s.aHandyPages))
3525	{
3526	if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
3527	{
3528	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
3529	break;
3530	}
3531	if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
3532	{
3533	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
3534	break;
3535	}
3536	i++;
3537	}
3538
3539	/*
3540	* Push it onto the page array.
3541	*/
3542	uint32_t iPage = *pcPendingPages;
3543	Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
3544	*pcPendingPages += 1;
3545
3546	pReq->aPages[iPage].idPage = idPage;
3547
3548	if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
3549	return VINF_SUCCESS;
3550
3551	/*
3552	* Flush the pages.
3553	*/
3554	int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
3555	if (RT_SUCCESS(rc))
3556	{
3557	GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3558	*pcPendingPages = 0;
3559	}
3560	return rc;
3561	}
3562
3563
3564	/**
3565	* Converts a GC physical address to a HC ring-3 pointer, with some
3566	* additional checks.
3567	*
3568	* @returns VBox status code.
3569	* @retval VINF_SUCCESS on success.
3570	* @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
3571	* access handler of some kind.
3572	* @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
3573	* accesses or is odd in any way.
3574	* @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
3575	*
3576	* @param pVM The VM handle.
3577	* @param GCPhys The GC physical address to convert.
3578	* @param fWritable Whether write access is required.
3579	* @param ppv Where to store the pointer corresponding to GCPhys on
3580	* success.
3581	*/
3582	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
3583	{
3584	pgmLock(pVM);
3585
3586	PPGMRAMRANGE pRam;
3587	PPGMPAGE pPage;
3588	int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
3589	if (RT_SUCCESS(rc))
3590	{
3591	#ifdef VBOX_WITH_NEW_PHYS_CODE
3592	if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3593	rc = VINF_SUCCESS;
3594	else
3595	{
3596	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3597	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3598	else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3599	{
3600	/** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
3601	* in -norawr0 mode. */
3602	if (fWritable)
3603	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3604	}
3605	else
3606	{
3607	/* Temporariliy disabled phycial handler(s), since the recompiler
3608	doesn't get notified when it's reset we'll have to pretend its
3609	operating normally. */
3610	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3611	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3612	else
3613	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3614	}
3615	}
3616	if (RT_SUCCESS(rc))
3617	{
3618	int rc2;
3619
3620	/* Make sure what we return is writable. */
3621	if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
3622	switch (PGM_PAGE_GET_STATE(pPage))
3623	{
3624	case PGM_PAGE_STATE_ALLOCATED:
3625	break;
3626	case PGM_PAGE_STATE_ZERO:
3627	case PGM_PAGE_STATE_SHARED:
3628	case PGM_PAGE_STATE_WRITE_MONITORED:
3629	rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
3630	AssertLogRelRCReturn(rc2, rc2);
3631	break;
3632	}
3633
3634	/* Get a ring-3 mapping of the address. */
3635	PPGMPAGER3MAPTLBE pTlbe;
3636	rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
3637	AssertLogRelRCReturn(rc2, rc2);
3638	ppv = (void )((uintptr_t)pTlbe->pv \| (GCPhys & PAGE_OFFSET_MASK));
3639	/** @todo mapping/locking hell; this isn't horribly efficient since
3640	* pgmPhysPageLoadIntoTlb will repeate the lookup we've done here. */
3641
3642	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] ppv=%p\n", GCPhys, rc, pPage, ppv));
3643	}
3644	else
3645	Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
3646
3647	/* else: handler catching all access, no pointer returned. */
3648
3649	#else
3650	if (0)
3651	/* nothing */;
3652	else if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3653	{
3654	if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3655	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3656	else if (fWritable && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3657	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3658	else
3659	{
3660	/* Temporariliy disabled phycial handler(s), since the recompiler
3661	doesn't get notified when it's reset we'll have to pretend its
3662	operating normally. */
3663	if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3664	rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3665	else
3666	rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3667	}
3668	}
3669	else
3670	rc = VINF_SUCCESS;
3671	if (RT_SUCCESS(rc))
3672	{
3673	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3674	{
3675	AssertMsg(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM, ("GCPhys=%RGp type=%d\n", GCPhys, PGM_PAGE_GET_TYPE(pPage)));
3676	RTGCPHYS off = GCPhys - pRam->GCPhys;
3677	unsigned iChunk = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3678	ppv = (void )(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3679	}
3680	else if (RT_LIKELY(pRam->pvR3))
3681	{
3682	AssertMsg(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM \|\| PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2, ("GCPhys=%RGp type=%d\n", GCPhys, PGM_PAGE_GET_TYPE(pPage)));
3683	RTGCPHYS off = GCPhys - pRam->GCPhys;
3684	ppv = (uint8_t )pRam->pvR3 + off;
3685	}
3686	else
3687	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3688	}
3689	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
3690	}
3691	else
3692	rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3693
3694	pgmUnlock(pVM);
3695	return rc;
3696	}
3697
3698
3699

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source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 18291

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