VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 17383

Last change on this file since 17383 was 17371, checked in by vboxsync, 16 years ago

PGM,GMM: Hacking on the new phys code.
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1/* $Id: PGMPhys.cpp 17371 2009-03-05 01:37:58Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, Physical Memory Addressing.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM
27#include <VBox/pgm.h>
28#include <VBox/cpum.h>
29#include <VBox/iom.h>
30#include <VBox/sup.h>
31#include <VBox/mm.h>
32#include <VBox/stam.h>
33#include <VBox/rem.h>
34#include <VBox/csam.h>
35#include "PGMInternal.h"
36#include <VBox/vm.h>
37#include <VBox/dbg.h>
38#include <VBox/param.h>
39#include <VBox/err.h>
40#include <iprt/assert.h>
41#include <iprt/alloc.h>
42#include <iprt/asm.h>
43#include <VBox/log.h>
44#include <iprt/thread.h>
45#include <iprt/string.h>
46
47
48/*******************************************************************************
49* Internal Functions *
50*******************************************************************************/
51static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
52
53
54
55/*
56 * PGMR3PhysReadU8-64
57 * PGMR3PhysWriteU8-64
58 */
59#define PGMPHYSFN_READNAME PGMR3PhysReadU8
60#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
61#define PGMPHYS_DATASIZE 1
62#define PGMPHYS_DATATYPE uint8_t
63#include "PGMPhysRWTmpl.h"
64
65#define PGMPHYSFN_READNAME PGMR3PhysReadU16
66#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
67#define PGMPHYS_DATASIZE 2
68#define PGMPHYS_DATATYPE uint16_t
69#include "PGMPhysRWTmpl.h"
70
71#define PGMPHYSFN_READNAME PGMR3PhysReadU32
72#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
73#define PGMPHYS_DATASIZE 4
74#define PGMPHYS_DATATYPE uint32_t
75#include "PGMPhysRWTmpl.h"
76
77#define PGMPHYSFN_READNAME PGMR3PhysReadU64
78#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
79#define PGMPHYS_DATASIZE 8
80#define PGMPHYS_DATATYPE uint64_t
81#include "PGMPhysRWTmpl.h"
82
83
84
85/**
86 * Links a new RAM range into the list.
87 *
88 * @param pVM Pointer to the shared VM structure.
89 * @param pNew Pointer to the new list entry.
90 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
91 */
92static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
93{
94 pgmLock(pVM);
95
96 PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
97 pNew->pNextR3 = pRam;
98 pNew->pNextR0 = pRam ? MMHyperCCToR0(pVM, pRam) : NIL_RTR0PTR;
99 pNew->pNextRC = pRam ? MMHyperCCToRC(pVM, pRam) : NIL_RTRCPTR;
100
101 if (pPrev)
102 {
103 pPrev->pNextR3 = pNew;
104 pPrev->pNextR0 = MMHyperCCToR0(pVM, pNew);
105 pPrev->pNextRC = MMHyperCCToRC(pVM, pNew);
106 }
107 else
108 {
109 pVM->pgm.s.pRamRangesR3 = pNew;
110 pVM->pgm.s.pRamRangesR0 = MMHyperCCToR0(pVM, pNew);
111 pVM->pgm.s.pRamRangesRC = MMHyperCCToRC(pVM, pNew);
112 }
113
114 pgmUnlock(pVM);
115}
116
117
118/**
119 * Unlink an existing RAM range from the list.
120 *
121 * @param pVM Pointer to the shared VM structure.
122 * @param pRam Pointer to the new list entry.
123 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
124 */
125static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
126{
127 Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
128
129 pgmLock(pVM);
130
131 PPGMRAMRANGE pNext = pRam->pNextR3;
132 if (pPrev)
133 {
134 pPrev->pNextR3 = pNext;
135 pPrev->pNextR0 = pNext ? MMHyperCCToR0(pVM, pNext) : NIL_RTR0PTR;
136 pPrev->pNextRC = pNext ? MMHyperCCToRC(pVM, pNext) : NIL_RTRCPTR;
137 }
138 else
139 {
140 Assert(pVM->pgm.s.pRamRangesR3 == pRam);
141 pVM->pgm.s.pRamRangesR3 = pNext;
142 pVM->pgm.s.pRamRangesR0 = pNext ? MMHyperCCToR0(pVM, pNext) : NIL_RTR0PTR;
143 pVM->pgm.s.pRamRangesRC = pNext ? MMHyperCCToRC(pVM, pNext) : NIL_RTRCPTR;
144 }
145
146 pgmUnlock(pVM);
147}
148
149
150/**
151 * Unlink an existing RAM range from the list.
152 *
153 * @param pVM Pointer to the shared VM structure.
154 * @param pRam Pointer to the new list entry.
155 */
156static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
157{
158 /* find prev. */
159 PPGMRAMRANGE pPrev = NULL;
160 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
161 while (pCur != pRam)
162 {
163 pPrev = pCur;
164 pCur = pCur->pNextR3;
165 }
166 AssertFatal(pCur);
167
168 pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
169}
170
171
172/**
173 * Sets up a range RAM.
174 *
175 * This will check for conflicting registrations, make a resource
176 * reservation for the memory (with GMM), and setup the per-page
177 * tracking structures (PGMPAGE).
178 *
179 * @returns VBox stutus code.
180 * @param pVM Pointer to the shared VM structure.
181 * @param GCPhys The physical address of the RAM.
182 * @param cb The size of the RAM.
183 * @param pszDesc The description - not copied, so, don't free or change it.
184 */
185VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
186{
187 /*
188 * Validate input.
189 */
190 Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
191 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
192 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
193 AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
194 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
195 AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
196 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
197 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
198
199 /*
200 * Find range location and check for conflicts.
201 * (We don't lock here because the locking by EMT is only required on update.)
202 */
203 PPGMRAMRANGE pPrev = NULL;
204 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
205 while (pRam && GCPhysLast >= pRam->GCPhys)
206 {
207 if ( GCPhysLast >= pRam->GCPhys
208 && GCPhys <= pRam->GCPhysLast)
209 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
210 GCPhys, GCPhysLast, pszDesc,
211 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
212 VERR_PGM_RAM_CONFLICT);
213
214 /* next */
215 pPrev = pRam;
216 pRam = pRam->pNextR3;
217 }
218
219 /*
220 * Register it with GMM (the API bitches).
221 */
222 const RTGCPHYS cPages = cb >> PAGE_SHIFT;
223 int rc = MMR3IncreaseBaseReservation(pVM, cPages);
224 if (RT_FAILURE(rc))
225 return rc;
226
227 /*
228 * Allocate RAM range.
229 */
230 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
231 PPGMRAMRANGE pNew;
232 rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
233 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
234
235 /*
236 * Initialize the range.
237 */
238 pNew->GCPhys = GCPhys;
239 pNew->GCPhysLast = GCPhysLast;
240 pNew->pszDesc = pszDesc;
241 pNew->cb = cb;
242 pNew->fFlags = 0;
243
244 pNew->pvR3 = NULL;
245#ifndef VBOX_WITH_NEW_PHYS_CODE
246 pNew->paChunkR3Ptrs = NULL;
247
248 /* Allocate memory for chunk to HC ptr lookup array. */
249 rc = MMHyperAlloc(pVM, (cb >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(void *), 16, MM_TAG_PGM, (void **)&pNew->paChunkR3Ptrs);
250 AssertRCReturn(rc, rc);
251 pNew->fFlags |= MM_RAM_FLAGS_DYNAMIC_ALLOC;
252
253#endif
254 RTGCPHYS iPage = cPages;
255 while (iPage-- > 0)
256 PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
257
258 /*
259 * Insert the new RAM range.
260 */
261 pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
262
263 /*
264 * Notify REM.
265 */
266#ifdef VBOX_WITH_NEW_PHYS_CODE
267 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, 0);
268#else
269 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, MM_RAM_FLAGS_DYNAMIC_ALLOC);
270#endif
271
272 return VINF_SUCCESS;
273}
274
275
276/**
277 * Resets (zeros) the RAM.
278 *
279 * ASSUMES that the caller owns the PGM lock.
280 *
281 * @returns VBox status code.
282 * @param pVM Pointer to the shared VM structure.
283 */
284int pgmR3PhysRamReset(PVM pVM)
285{
286 /*
287 * Walk the ram ranges.
288 */
289 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
290 {
291 uint32_t iPage = pRam->cb >> PAGE_SHIFT; Assert((RTGCPHYS)iPage << PAGE_SHIFT == pRam->cb);
292#ifdef VBOX_WITH_NEW_PHYS_CODE
293 int rc;
294 if (!pVM->pgm.s.fRamPreAlloc)
295 {
296 /* Replace all RAM pages by ZERO pages. */
297 while (iPage-- > 0)
298 {
299 PPGMPAGE pPage = &pRam->aPages[iPage];
300 switch (PGM_PAGE_GET_TYPE(pPage))
301 {
302 case PGMPAGETYPE_RAM:
303 if (!PGM_PAGE_IS_ZERO(pPage))
304 pgmPhysFreePage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
305 break;
306
307 case PGMPAGETYPE_MMIO2:
308 case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
309 case PGMPAGETYPE_ROM:
310 case PGMPAGETYPE_MMIO:
311 break;
312 default:
313 AssertFailed();
314 }
315 } /* for each page */
316 }
317 else
318#endif
319 {
320 /* Zero the memory. */
321 while (iPage-- > 0)
322 {
323 PPGMPAGE pPage = &pRam->aPages[iPage];
324 switch (PGM_PAGE_GET_TYPE(pPage))
325 {
326#ifndef VBOX_WITH_NEW_PHYS_CODE
327 case PGMPAGETYPE_INVALID:
328 case PGMPAGETYPE_RAM:
329 if (pRam->aPages[iPage].HCPhys & (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2)) /** @todo PAGE FLAGS */
330 {
331 /* shadow ram is reloaded elsewhere. */
332 Log4(("PGMR3Reset: not clearing phys page %RGp due to flags %RHp\n", pRam->GCPhys + (iPage << PAGE_SHIFT), pRam->aPages[iPage].HCPhys & (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO))); /** @todo PAGE FLAGS */
333 continue;
334 }
335 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
336 {
337 unsigned iChunk = iPage >> (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
338 if (pRam->paChunkR3Ptrs[iChunk])
339 ASMMemZero32((char *)pRam->paChunkR3Ptrs[iChunk] + ((iPage << PAGE_SHIFT) & PGM_DYNAMIC_CHUNK_OFFSET_MASK), PAGE_SIZE);
340 }
341 else
342 ASMMemZero32((char *)pRam->pvR3 + (iPage << PAGE_SHIFT), PAGE_SIZE);
343 break;
344#else /* VBOX_WITH_NEW_PHYS_CODE */
345 case PGMPAGETYPE_RAM:
346 switch (PGM_PAGE_GET_STATE(pPage))
347 {
348 case PGM_PAGE_STATE_ZERO:
349 break;
350 case PGM_PAGE_STATE_SHARED:
351 case PGM_PAGE_STATE_WRITE_MONITORED:
352 rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
353 AssertLogRelRCReturn(rc, rc);
354 case PGM_PAGE_STATE_ALLOCATED:
355 {
356 void *pvPage;
357 PPGMPAGEMAP pMapIgnored;
358 rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pMapIgnored, &pvPage);
359 AssertLogRelRCReturn(rc, rc);
360 ASMMemZeroPage(pvPage);
361 break;
362 }
363 }
364 break;
365#endif /* VBOX_WITH_NEW_PHYS_CODE */
366
367 case PGMPAGETYPE_MMIO2:
368 case PGMPAGETYPE_ROM_SHADOW:
369 case PGMPAGETYPE_ROM:
370 case PGMPAGETYPE_MMIO:
371 break;
372 default:
373 AssertFailed();
374
375 }
376 } /* for each page */
377 }
378
379 }
380
381 return VINF_SUCCESS;
382}
383
384
385/**
386 * This is the interface IOM is using to register an MMIO region.
387 *
388 * It will check for conflicts and ensure that a RAM range structure
389 * is present before calling the PGMR3HandlerPhysicalRegister API to
390 * register the callbacks.
391 *
392 * @returns VBox status code.
393 *
394 * @param pVM Pointer to the shared VM structure.
395 * @param GCPhys The start of the MMIO region.
396 * @param cb The size of the MMIO region.
397 * @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
398 * @param pvUserR3 The user argument for R3.
399 * @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
400 * @param pvUserR0 The user argument for R0.
401 * @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
402 * @param pvUserRC The user argument for RC.
403 * @param pszDesc The description of the MMIO region.
404 */
405VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
406 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
407 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
408 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
409 R3PTRTYPE(const char *) pszDesc)
410{
411 /*
412 * Assert on some assumption.
413 */
414 VM_ASSERT_EMT(pVM);
415 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
416 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
417 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
418 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
419
420 /*
421 * Make sure there's a RAM range structure for the region.
422 */
423 int rc;
424 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
425 bool fRamExists = false;
426 PPGMRAMRANGE pRamPrev = NULL;
427 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
428 while (pRam && GCPhysLast >= pRam->GCPhys)
429 {
430 if ( GCPhysLast >= pRam->GCPhys
431 && GCPhys <= pRam->GCPhysLast)
432 {
433 /* Simplification: all within the same range. */
434 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
435 && GCPhysLast <= pRam->GCPhysLast,
436 ("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
437 GCPhys, GCPhysLast, pszDesc,
438 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
439 VERR_PGM_RAM_CONFLICT);
440
441 /* Check that it's all RAM or MMIO pages. */
442 PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
443 uint32_t cLeft = cb >> PAGE_SHIFT;
444 while (cLeft-- > 0)
445 {
446 AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
447 || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
448 ("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
449 GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
450 VERR_PGM_RAM_CONFLICT);
451 pPage++;
452 }
453
454 /* Looks good. */
455 fRamExists = true;
456 break;
457 }
458
459 /* next */
460 pRamPrev = pRam;
461 pRam = pRam->pNextR3;
462 }
463 PPGMRAMRANGE pNew;
464 if (fRamExists)
465 pNew = NULL;
466 else
467 {
468 /*
469 * No RAM range, insert an ad-hoc one.
470 *
471 * Note that we don't have to tell REM about this range because
472 * PGMHandlerPhysicalRegisterEx will do that for us.
473 */
474 Log(("PGMR3PhysMMIORegister: Adding ad-hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
475
476 const uint32_t cPages = cb >> PAGE_SHIFT;
477 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
478 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
479 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
480
481 /* Initialize the range. */
482 pNew->GCPhys = GCPhys;
483 pNew->GCPhysLast = GCPhysLast;
484 pNew->pszDesc = pszDesc;
485 pNew->cb = cb;
486 pNew->fFlags = 0; /* Some MMIO flag here? */
487
488 pNew->pvR3 = NULL;
489#ifndef VBOX_WITH_NEW_PHYS_CODE
490 pNew->paChunkR3Ptrs = NULL;
491#endif
492
493 uint32_t iPage = cPages;
494 while (iPage-- > 0)
495 PGM_PAGE_INIT_ZERO_REAL(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
496 Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
497
498 /* link it */
499 pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
500 }
501
502 /*
503 * Register the access handler.
504 */
505 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
506 pfnHandlerR3, pvUserR3,
507 pfnHandlerR0, pvUserR0,
508 pfnHandlerRC, pvUserRC, pszDesc);
509 if ( RT_FAILURE(rc)
510 && !fRamExists)
511 {
512 /* remove the ad-hoc range. */
513 pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
514 pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
515 MMHyperFree(pVM, pRam);
516 }
517
518 return rc;
519}
520
521
522/**
523 * This is the interface IOM is using to register an MMIO region.
524 *
525 * It will take care of calling PGMHandlerPhysicalDeregister and clean up
526 * any ad-hoc PGMRAMRANGE left behind.
527 *
528 * @returns VBox status code.
529 * @param pVM Pointer to the shared VM structure.
530 * @param GCPhys The start of the MMIO region.
531 * @param cb The size of the MMIO region.
532 */
533VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
534{
535 VM_ASSERT_EMT(pVM);
536
537 /*
538 * First deregister the handler, then check if we should remove the ram range.
539 */
540 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
541 if (RT_SUCCESS(rc))
542 {
543 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
544 PPGMRAMRANGE pRamPrev = NULL;
545 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
546 while (pRam && GCPhysLast >= pRam->GCPhys)
547 {
548 /*if ( GCPhysLast >= pRam->GCPhys
549 && GCPhys <= pRam->GCPhysLast) - later */
550 if ( GCPhysLast == pRam->GCPhysLast
551 && GCPhys == pRam->GCPhys)
552 {
553 Assert(pRam->cb == cb);
554
555 /*
556 * See if all the pages are dead MMIO pages.
557 */
558 bool fAllMMIO = true;
559 PPGMPAGE pPage = &pRam->aPages[0];
560 uint32_t cLeft = cb >> PAGE_SHIFT;
561 while (cLeft-- > 0)
562 {
563 if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
564 /*|| not-out-of-action later */)
565 {
566 fAllMMIO = false;
567 break;
568 }
569 pPage++;
570 }
571
572 /*
573 * Unlink it and free if it's all MMIO.
574 */
575 if (fAllMMIO)
576 {
577 Log(("PGMR3PhysMMIODeregister: Freeing ad-hoc MMIO range for %RGp-%RGp %s\n",
578 GCPhys, GCPhysLast, pRam->pszDesc));
579
580 pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
581 pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
582 MMHyperFree(pVM, pRam);
583 }
584 break;
585 }
586
587 /* next */
588 pRamPrev = pRam;
589 pRam = pRam->pNextR3;
590 }
591 }
592
593 return rc;
594}
595
596
597/**
598 * Locate a MMIO2 range.
599 *
600 * @returns Pointer to the MMIO2 range.
601 * @param pVM Pointer to the shared VM structure.
602 * @param pDevIns The device instance owning the region.
603 * @param iRegion The region.
604 */
605DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
606{
607 /*
608 * Search the list.
609 */
610 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
611 if ( pCur->pDevInsR3 == pDevIns
612 && pCur->iRegion == iRegion)
613 return pCur;
614 return NULL;
615}
616
617
618/**
619 * Allocate and register an MMIO2 region.
620 *
621 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
622 * RAM associated with a device. It is also non-shared memory with a
623 * permanent ring-3 mapping and page backing (presently).
624 *
625 * A MMIO2 range may overlap with base memory if a lot of RAM
626 * is configured for the VM, in which case we'll drop the base
627 * memory pages. Presently we will make no attempt to preserve
628 * anything that happens to be present in the base memory that
629 * is replaced, this is of course incorrectly but it's too much
630 * effort.
631 *
632 * @returns VBox status code.
633 * @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
634 * @retval VERR_ALREADY_EXISTS if the region already exists.
635 *
636 * @param pVM Pointer to the shared VM structure.
637 * @param pDevIns The device instance owning the region.
638 * @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
639 * this number has to be the number of that region. Otherwise
640 * it can be any number safe UINT8_MAX.
641 * @param cb The size of the region. Must be page aligned.
642 * @param fFlags Reserved for future use, must be zero.
643 * @param ppv Where to store the pointer to the ring-3 mapping of the memory.
644 * @param pszDesc The description.
645 */
646VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc)
647{
648 /*
649 * Validate input.
650 */
651 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
652 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
653 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
654 AssertPtrReturn(ppv, VERR_INVALID_POINTER);
655 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
656 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
657 AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
658 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
659 AssertReturn(cb, VERR_INVALID_PARAMETER);
660 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
661
662 const uint32_t cPages = cb >> PAGE_SHIFT;
663 AssertLogRelReturn((RTGCPHYS)cPages << PAGE_SHIFT == cb, VERR_INVALID_PARAMETER);
664 AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
665
666 /*
667 * Try reserve and allocate the backing memory first as this is what is
668 * most likely to fail.
669 */
670 int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
671 if (RT_FAILURE(rc))
672 return rc;
673
674 void *pvPages;
675 PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
676 if (RT_SUCCESS(rc))
677 rc = SUPR3PageAllocEx(cPages, 0 /*fFlags*/, &pvPages, NULL /*pR0Ptr*/, paPages);
678 if (RT_SUCCESS(rc))
679 {
680 memset(pvPages, 0, cPages * PAGE_SIZE);
681
682 /*
683 * Create the MMIO2 range record for it.
684 */
685 const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
686 PPGMMMIO2RANGE pNew;
687 rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
688 AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
689 if (RT_SUCCESS(rc))
690 {
691 pNew->pDevInsR3 = pDevIns;
692 pNew->pvR3 = pvPages;
693 //pNew->pNext = NULL;
694 //pNew->fMapped = false;
695 //pNew->fOverlapping = false;
696 pNew->iRegion = iRegion;
697 pNew->RamRange.GCPhys = NIL_RTGCPHYS;
698 pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
699 pNew->RamRange.pszDesc = pszDesc;
700 pNew->RamRange.cb = cb;
701 //pNew->RamRange.fFlags = 0;
702
703 pNew->RamRange.pvR3 = pvPages; ///@todo remove this [new phys code]
704#ifndef VBOX_WITH_NEW_PHYS_CODE
705 pNew->RamRange.paChunkR3Ptrs = NULL; ///@todo remove this [new phys code]
706#endif
707
708 uint32_t iPage = cPages;
709 while (iPage-- > 0)
710 {
711 PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
712 paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
713 PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
714 }
715
716 /*
717 * Link it into the list.
718 * Since there is no particular order, just push it.
719 */
720 pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
721 pVM->pgm.s.pMmio2RangesR3 = pNew;
722
723 *ppv = pvPages;
724 RTMemTmpFree(paPages);
725 return VINF_SUCCESS;
726 }
727
728 SUPR3PageFreeEx(pvPages, cPages);
729 }
730 RTMemTmpFree(paPages);
731 MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
732 return rc;
733}
734
735
736/**
737 * Deregisters and frees an MMIO2 region.
738 *
739 * Any physical (and virtual) access handlers registered for the region must
740 * be deregistered before calling this function.
741 *
742 * @returns VBox status code.
743 * @param pVM Pointer to the shared VM structure.
744 * @param pDevIns The device instance owning the region.
745 * @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
746 */
747VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
748{
749 /*
750 * Validate input.
751 */
752 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
753 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
754 AssertReturn(iRegion <= UINT8_MAX || iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
755
756 int rc = VINF_SUCCESS;
757 unsigned cFound = 0;
758 PPGMMMIO2RANGE pPrev = NULL;
759 PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
760 while (pCur)
761 {
762 if ( pCur->pDevInsR3 == pDevIns
763 && ( iRegion == UINT32_MAX
764 || pCur->iRegion == iRegion))
765 {
766 cFound++;
767
768 /*
769 * Unmap it if it's mapped.
770 */
771 if (pCur->fMapped)
772 {
773 int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
774 AssertRC(rc2);
775 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
776 rc = rc2;
777 }
778
779 /*
780 * Unlink it
781 */
782 PPGMMMIO2RANGE pNext = pCur->pNextR3;
783 if (pPrev)
784 pPrev->pNextR3 = pNext;
785 else
786 pVM->pgm.s.pMmio2RangesR3 = pNext;
787 pCur->pNextR3 = NULL;
788
789 /*
790 * Free the memory.
791 */
792 int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
793 AssertRC(rc2);
794 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
795 rc = rc2;
796
797 rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)(pCur->RamRange.cb >> PAGE_SHIFT), pCur->RamRange.pszDesc);
798 AssertRC(rc2);
799 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
800 rc = rc2;
801
802 /* we're leaking hyper memory here if done at runtime. */
803 Assert( VMR3GetState(pVM) == VMSTATE_OFF
804 || VMR3GetState(pVM) == VMSTATE_DESTROYING
805 || VMR3GetState(pVM) == VMSTATE_TERMINATED
806 || VMR3GetState(pVM) == VMSTATE_CREATING);
807 /*rc = MMHyperFree(pVM, pCur);
808 AssertRCReturn(rc, rc); - not safe, see the alloc call. */
809
810 /* next */
811 pCur = pNext;
812 }
813 else
814 {
815 pPrev = pCur;
816 pCur = pCur->pNextR3;
817 }
818 }
819
820 return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
821}
822
823
824/**
825 * Maps a MMIO2 region.
826 *
827 * This is done when a guest / the bios / state loading changes the
828 * PCI config. The replacing of base memory has the same restrictions
829 * as during registration, of course.
830 *
831 * @returns VBox status code.
832 *
833 * @param pVM Pointer to the shared VM structure.
834 * @param pDevIns The
835 */
836VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
837{
838 /*
839 * Validate input
840 */
841 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
842 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
843 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
844 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
845 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
846 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
847
848 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
849 AssertReturn(pCur, VERR_NOT_FOUND);
850 AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
851 Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
852 Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
853
854 const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
855 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
856
857 /*
858 * Find our location in the ram range list, checking for
859 * restriction we don't bother implementing yet (partially overlapping).
860 */
861 bool fRamExists = false;
862 PPGMRAMRANGE pRamPrev = NULL;
863 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
864 while (pRam && GCPhysLast >= pRam->GCPhys)
865 {
866 if ( GCPhys <= pRam->GCPhysLast
867 && GCPhysLast >= pRam->GCPhys)
868 {
869 /* completely within? */
870 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
871 && GCPhysLast <= pRam->GCPhysLast,
872 ("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
873 GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
874 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
875 VERR_PGM_RAM_CONFLICT);
876 fRamExists = true;
877 break;
878 }
879
880 /* next */
881 pRamPrev = pRam;
882 pRam = pRam->pNextR3;
883 }
884 if (fRamExists)
885 {
886 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
887 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
888 while (cPagesLeft-- > 0)
889 {
890 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
891 ("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
892 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
893 VERR_PGM_RAM_CONFLICT);
894 pPage++;
895 }
896 }
897 Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
898 GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
899
900 /*
901 * Make the changes.
902 */
903 pgmLock(pVM);
904
905 pCur->RamRange.GCPhys = GCPhys;
906 pCur->RamRange.GCPhysLast = GCPhysLast;
907 pCur->fMapped = true;
908 pCur->fOverlapping = fRamExists;
909
910 if (fRamExists)
911 {
912 /* replace the pages, freeing all present RAM pages. */
913 PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
914 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
915 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
916 while (cPagesLeft-- > 0)
917 {
918 pgmPhysFreePage(pVM, pPageDst, GCPhys);
919
920 RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
921 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
922 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
923 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
924
925 GCPhys += PAGE_SIZE;
926 pPageSrc++;
927 pPageDst++;
928 }
929 }
930 else
931 {
932 /* link in the ram range */
933 pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
934 REMR3NotifyPhysRamRegister(pVM, GCPhys, pCur->RamRange.cb, 0);
935 }
936
937 pgmUnlock(pVM);
938
939 return VINF_SUCCESS;
940}
941
942
943/**
944 * Unmaps a MMIO2 region.
945 *
946 * This is done when a guest / the bios / state loading changes the
947 * PCI config. The replacing of base memory has the same restrictions
948 * as during registration, of course.
949 */
950VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
951{
952 /*
953 * Validate input
954 */
955 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
956 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
957 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
958 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
959 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
960 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
961
962 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
963 AssertReturn(pCur, VERR_NOT_FOUND);
964 AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
965 AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
966 Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
967
968 Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
969 pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
970
971 /*
972 * Unmap it.
973 */
974 pgmLock(pVM);
975
976 if (pCur->fOverlapping)
977 {
978 /* Restore the RAM pages we've replaced. */
979 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
980 while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
981 pRam = pRam->pNextR3;
982
983#ifdef RT_STRICT
984 RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
985#endif
986 Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
987 PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
988 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
989 while (cPagesLeft-- > 0)
990 {
991 PGM_PAGE_SET_HCPHYS(pPageDst, pVM->pgm.s.HCPhysZeroPg);
992 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
993 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
994
995 pPageDst++;
996 }
997 }
998 else
999 {
1000 REMR3NotifyPhysRamDeregister(pVM, pCur->RamRange.GCPhys, pCur->RamRange.cb);
1001 pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
1002 }
1003
1004 pCur->RamRange.GCPhys = NIL_RTGCPHYS;
1005 pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
1006 pCur->fOverlapping = false;
1007 pCur->fMapped = false;
1008
1009 pgmUnlock(pVM);
1010
1011 return VINF_SUCCESS;
1012}
1013
1014
1015/**
1016 * Checks if the given address is an MMIO2 base address or not.
1017 *
1018 * @returns true/false accordingly.
1019 * @param pVM Pointer to the shared VM structure.
1020 * @param pDevIns The owner of the memory, optional.
1021 * @param GCPhys The address to check.
1022 */
1023VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
1024{
1025 /*
1026 * Validate input
1027 */
1028 VM_ASSERT_EMT_RETURN(pVM, false);
1029 AssertPtrReturn(pDevIns, false);
1030 AssertReturn(GCPhys != NIL_RTGCPHYS, false);
1031 AssertReturn(GCPhys != 0, false);
1032 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
1033
1034 /*
1035 * Search the list.
1036 */
1037 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1038 if (pCur->RamRange.GCPhys == GCPhys)
1039 {
1040 Assert(pCur->fMapped);
1041 return true;
1042 }
1043 return false;
1044}
1045
1046
1047/**
1048 * Gets the HC physical address of a page in the MMIO2 region.
1049 *
1050 * This is API is intended for MMHyper and shouldn't be called
1051 * by anyone else...
1052 *
1053 * @returns VBox status code.
1054 * @param pVM Pointer to the shared VM structure.
1055 * @param pDevIns The owner of the memory, optional.
1056 * @param iRegion The region.
1057 * @param off The page expressed an offset into the MMIO2 region.
1058 * @param pHCPhys Where to store the result.
1059 */
1060VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
1061{
1062 /*
1063 * Validate input
1064 */
1065 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1066 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1067 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1068
1069 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1070 AssertReturn(pCur, VERR_NOT_FOUND);
1071 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1072
1073 PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
1074 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
1075 return VINF_SUCCESS;
1076}
1077
1078
1079/**
1080 * Maps a portion of an MMIO2 region into kernel space (host).
1081 *
1082 * The kernel mapping will become invalid when the MMIO2 memory is deregistered
1083 * or the VM is terminated.
1084 *
1085 * @return VBox status code.
1086 *
1087 * @param pVM Pointer to the shared VM structure.
1088 * @param pDevIns The device owning the MMIO2 memory.
1089 * @param iRegion The region.
1090 * @param off The offset into the region. Must be page aligned.
1091 * @param cb The number of bytes to map. Must be page aligned.
1092 * @param pszDesc Mapping description.
1093 * @param pR0Ptr Where to store the R0 address.
1094 */
1095VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
1096 const char *pszDesc, PRTR0PTR pR0Ptr)
1097{
1098 /*
1099 * Validate input.
1100 */
1101 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1102 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1103 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1104
1105 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1106 AssertReturn(pCur, VERR_NOT_FOUND);
1107 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1108 AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1109 AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
1110
1111 /*
1112 * Pass the request on to the support library/driver.
1113 */
1114 int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
1115
1116 return rc;
1117}
1118
1119
1120/**
1121 * Registers a ROM image.
1122 *
1123 * Shadowed ROM images requires double the amount of backing memory, so,
1124 * don't use that unless you have to. Shadowing of ROM images is process
1125 * where we can select where the reads go and where the writes go. On real
1126 * hardware the chipset provides means to configure this. We provide
1127 * PGMR3PhysProtectROM() for this purpose.
1128 *
1129 * A read-only copy of the ROM image will always be kept around while we
1130 * will allocate RAM pages for the changes on demand (unless all memory
1131 * is configured to be preallocated).
1132 *
1133 * @returns VBox status.
1134 * @param pVM VM Handle.
1135 * @param pDevIns The device instance owning the ROM.
1136 * @param GCPhys First physical address in the range.
1137 * Must be page aligned!
1138 * @param cbRange The size of the range (in bytes).
1139 * Must be page aligned!
1140 * @param pvBinary Pointer to the binary data backing the ROM image.
1141 * This must be exactly \a cbRange in size.
1142 * @param fFlags Mask of flags. PGMPHYS_ROM_FLAG_SHADOWED
1143 * and/or PGMPHYS_ROM_FLAG_PERMANENT_BINARY.
1144 * @param pszDesc Pointer to description string. This must not be freed.
1145 *
1146 * @remark There is no way to remove the rom, automatically on device cleanup or
1147 * manually from the device yet. This isn't difficult in any way, it's
1148 * just not something we expect to be necessary for a while.
1149 */
1150VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
1151 const void *pvBinary, uint32_t fFlags, const char *pszDesc)
1152{
1153 Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
1154 pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
1155
1156 /*
1157 * Validate input.
1158 */
1159 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1160 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
1161 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
1162 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1163 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1164 AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
1165 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1166 AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAG_SHADOWED | PGMPHYS_ROM_FLAG_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
1167 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
1168
1169 const uint32_t cPages = cb >> PAGE_SHIFT;
1170
1171 /*
1172 * Find the ROM location in the ROM list first.
1173 */
1174 PPGMROMRANGE pRomPrev = NULL;
1175 PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
1176 while (pRom && GCPhysLast >= pRom->GCPhys)
1177 {
1178 if ( GCPhys <= pRom->GCPhysLast
1179 && GCPhysLast >= pRom->GCPhys)
1180 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
1181 GCPhys, GCPhysLast, pszDesc,
1182 pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
1183 VERR_PGM_RAM_CONFLICT);
1184 /* next */
1185 pRomPrev = pRom;
1186 pRom = pRom->pNextR3;
1187 }
1188
1189 /*
1190 * Find the RAM location and check for conflicts.
1191 *
1192 * Conflict detection is a bit different than for RAM
1193 * registration since a ROM can be located within a RAM
1194 * range. So, what we have to check for is other memory
1195 * types (other than RAM that is) and that we don't span
1196 * more than one RAM range (layz).
1197 */
1198 bool fRamExists = false;
1199 PPGMRAMRANGE pRamPrev = NULL;
1200 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1201 while (pRam && GCPhysLast >= pRam->GCPhys)
1202 {
1203 if ( GCPhys <= pRam->GCPhysLast
1204 && GCPhysLast >= pRam->GCPhys)
1205 {
1206 /* completely within? */
1207 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1208 && GCPhysLast <= pRam->GCPhysLast,
1209 ("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
1210 GCPhys, GCPhysLast, pszDesc,
1211 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1212 VERR_PGM_RAM_CONFLICT);
1213 fRamExists = true;
1214 break;
1215 }
1216
1217 /* next */
1218 pRamPrev = pRam;
1219 pRam = pRam->pNextR3;
1220 }
1221 if (fRamExists)
1222 {
1223 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1224 uint32_t cPagesLeft = cPages;
1225 while (cPagesLeft-- > 0)
1226 {
1227 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
1228 ("%RGp isn't a RAM page (%d) - registering %RGp-%RGp (%s).\n",
1229 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pszDesc),
1230 VERR_PGM_RAM_CONFLICT);
1231 Assert(PGM_PAGE_IS_ZERO(pPage));
1232 pPage++;
1233 }
1234 }
1235
1236 /*
1237 * Update the base memory reservation if necessary.
1238 */
1239 uint32_t cExtraBaseCost = fRamExists ? cPages : 0;
1240 if (fFlags & PGMPHYS_ROM_FLAG_SHADOWED)
1241 cExtraBaseCost += cPages;
1242 if (cExtraBaseCost)
1243 {
1244 int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
1245 if (RT_FAILURE(rc))
1246 return rc;
1247 }
1248
1249 /*
1250 * Allocate memory for the virgin copy of the RAM.
1251 */
1252 PGMMALLOCATEPAGESREQ pReq;
1253 int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
1254 AssertRCReturn(rc, rc);
1255
1256 for (uint32_t iPage = 0; iPage < cPages; iPage++)
1257 {
1258 pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
1259 pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
1260 pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
1261 }
1262
1263 pgmLock(pVM);
1264 rc = GMMR3AllocatePagesPerform(pVM, pReq);
1265 pgmUnlock(pVM);
1266 if (RT_FAILURE(rc))
1267 {
1268 GMMR3AllocatePagesCleanup(pReq);
1269 return rc;
1270 }
1271
1272 /*
1273 * Allocate the new ROM range and RAM range (if necessary).
1274 */
1275 PPGMROMRANGE pRomNew;
1276 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
1277 if (RT_SUCCESS(rc))
1278 {
1279 PPGMRAMRANGE pRamNew = NULL;
1280 if (!fRamExists)
1281 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
1282 if (RT_SUCCESS(rc))
1283 {
1284 pgmLock(pVM);
1285
1286 /*
1287 * Initialize and insert the RAM range (if required).
1288 */
1289 PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
1290 if (!fRamExists)
1291 {
1292 pRamNew->GCPhys = GCPhys;
1293 pRamNew->GCPhysLast = GCPhysLast;
1294 pRamNew->pszDesc = pszDesc;
1295 pRamNew->cb = cb;
1296 pRamNew->fFlags = 0;
1297 pRamNew->pvR3 = NULL;
1298
1299 PPGMPAGE pPage = &pRamNew->aPages[0];
1300 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
1301 {
1302 PGM_PAGE_INIT(pPage,
1303 pReq->aPages[iPage].HCPhysGCPhys,
1304 pReq->aPages[iPage].idPage,
1305 PGMPAGETYPE_ROM,
1306 PGM_PAGE_STATE_ALLOCATED);
1307
1308 pRomPage->Virgin = *pPage;
1309 }
1310
1311 pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
1312 }
1313 else
1314 {
1315 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1316 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
1317 {
1318 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
1319 PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
1320 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1321 PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
1322
1323 pRomPage->Virgin = *pPage;
1324 }
1325
1326 pRamNew = pRam;
1327 }
1328 pgmUnlock(pVM);
1329
1330
1331 /*
1332 * Before registering the handler, notify REM, it'll get
1333 * confused about shadowed ROM otherwise.
1334 */
1335 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL,
1336 !!(fFlags & PGMPHYS_ROM_FLAG_SHADOWED));
1337 /** @todo fix shadowing and REM. */
1338
1339 /*
1340 * Register the write access handler for the range (PGMROMPROT_READ_ROM_WRITE_IGNORE).
1341 */
1342 rc = PGMR3HandlerPhysicalRegister(pVM,
1343 fFlags & PGMPHYS_ROM_FLAG_SHADOWED
1344 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
1345 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1346 GCPhys, GCPhysLast,
1347 pgmR3PhysRomWriteHandler, pRomNew,
1348 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
1349 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
1350 if (RT_SUCCESS(rc))
1351 {
1352 pgmLock(pVM);
1353
1354 /*
1355 * Copy the image over to the virgin pages.
1356 * This must be done after linking in the RAM range.
1357 */
1358 PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
1359 for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
1360 {
1361 void *pvDstPage;
1362 PPGMPAGEMAP pMapIgnored;
1363 rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pMapIgnored, &pvDstPage);
1364 if (RT_FAILURE(rc))
1365 {
1366 VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
1367 break;
1368 }
1369 memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
1370 }
1371 if (RT_SUCCESS(rc))
1372 {
1373 /*
1374 * Initialize the ROM range.
1375 * Note that the Virgin member of the pages has already been initialized above.
1376 */
1377 pRomNew->GCPhys = GCPhys;
1378 pRomNew->GCPhysLast = GCPhysLast;
1379 pRomNew->cb = cb;
1380 pRomNew->fFlags = fFlags;
1381 pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAG_PERMANENT_BINARY ? pvBinary : NULL;
1382 pRomNew->pszDesc = pszDesc;
1383
1384 for (unsigned iPage = 0; iPage < cPages; iPage++)
1385 {
1386 PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
1387 pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
1388 PGM_PAGE_INIT_ZERO_REAL(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
1389 }
1390
1391 /*
1392 * Insert the ROM range, tell REM and return successfully.
1393 */
1394 pRomNew->pNextR3 = pRom;
1395 pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
1396 pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
1397
1398 if (pRomPrev)
1399 {
1400 pRomPrev->pNextR3 = pRomNew;
1401 pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
1402 pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
1403 }
1404 else
1405 {
1406 pVM->pgm.s.pRomRangesR3 = pRomNew;
1407 pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
1408 pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
1409 }
1410
1411 GMMR3AllocatePagesCleanup(pReq);
1412 pgmUnlock(pVM);
1413 return VINF_SUCCESS;
1414 }
1415
1416 /* bail out */
1417
1418 pgmUnlock(pVM);
1419 int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1420 AssertRC(rc2);
1421 pgmLock(pVM);
1422 }
1423
1424 if (!fRamExists)
1425 {
1426 pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
1427 MMHyperFree(pVM, pRamNew);
1428 }
1429 }
1430 MMHyperFree(pVM, pRomNew);
1431 }
1432
1433 /** @todo Purge the mapping cache or something... */
1434 GMMR3FreeAllocatedPages(pVM, pReq);
1435 GMMR3AllocatePagesCleanup(pReq);
1436 pgmUnlock(pVM);
1437 return rc;
1438}
1439
1440
1441/**
1442 * \#PF Handler callback for ROM write accesses.
1443 *
1444 * @returns VINF_SUCCESS if the handler have carried out the operation.
1445 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1446 * @param pVM VM Handle.
1447 * @param GCPhys The physical address the guest is writing to.
1448 * @param pvPhys The HC mapping of that address.
1449 * @param pvBuf What the guest is reading/writing.
1450 * @param cbBuf How much it's reading/writing.
1451 * @param enmAccessType The access type.
1452 * @param pvUser User argument.
1453 */
1454static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1455{
1456 PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
1457 const uint32_t iPage = GCPhys - pRom->GCPhys;
1458 Assert(iPage < (pRom->cb >> PAGE_SHIFT));
1459 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
1460 switch (pRomPage->enmProt)
1461 {
1462 /*
1463 * Ignore.
1464 */
1465 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
1466 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
1467 return VINF_SUCCESS;
1468
1469 /*
1470 * Write to the ram page.
1471 */
1472 case PGMROMPROT_READ_ROM_WRITE_RAM:
1473 case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's *way* simpler that way. */
1474 {
1475 /* This should be impossible now, pvPhys doesn't work cross page anylonger. */
1476 Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
1477
1478 /*
1479 * Take the lock, do lazy allocation, map the page and copy the data.
1480 *
1481 * Note that we have to bypass the mapping TLB since it works on
1482 * guest physical addresses and entering the shadow page would
1483 * kind of screw things up...
1484 */
1485 int rc = pgmLock(pVM);
1486 AssertRC(rc);
1487
1488 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pRomPage->Shadow) != PGM_PAGE_STATE_ALLOCATED))
1489 {
1490 rc = pgmPhysPageMakeWritable(pVM, &pRomPage->Shadow, GCPhys);
1491 if (RT_FAILURE(rc))
1492 {
1493 pgmUnlock(pVM);
1494 return rc;
1495 }
1496 }
1497
1498 void *pvDstPage;
1499 PPGMPAGEMAP pMapIgnored;
1500 rc = pgmPhysPageMap(pVM, &pRomPage->Shadow, GCPhys & X86_PTE_PG_MASK, &pMapIgnored, &pvDstPage);
1501 if (RT_SUCCESS(rc))
1502 memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
1503
1504 pgmUnlock(pVM);
1505 return rc;
1506 }
1507
1508 default:
1509 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
1510 pRom->aPages[iPage].enmProt, iPage, GCPhys),
1511 VERR_INTERNAL_ERROR);
1512 }
1513}
1514
1515
1516/**
1517 * Called by PGMR3Reset to reset the shadow, switch to the virgin,
1518 * and verify that the virgin part is untouched.
1519 *
1520 * This is done after the normal memory has been cleared.
1521 *
1522 * ASSUMES that the caller owns the PGM lock.
1523 *
1524 * @param pVM The VM handle.
1525 */
1526int pgmR3PhysRomReset(PVM pVM)
1527{
1528 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
1529 {
1530 const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
1531
1532 if (pRom->fFlags & PGMPHYS_ROM_FLAG_SHADOWED)
1533 {
1534 /*
1535 * Reset the physical handler.
1536 */
1537 int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
1538 AssertRCReturn(rc, rc);
1539
1540 /*
1541 * What we do with the shadow pages depends on the memory
1542 * preallocation option. If not enabled, we'll just throw
1543 * out all the dirty pages and replace them by the zero page.
1544 */
1545 if (1)///@todo !pVM->pgm.f.fRamPreAlloc)
1546 {
1547 /* Count dirty shadow pages. */
1548 uint32_t cDirty = 0;
1549 uint32_t iPage = cPages;
1550 while (iPage-- > 0)
1551 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
1552 cDirty++;
1553 if (cDirty)
1554 {
1555 /* Free the dirty pages. */
1556 PGMMFREEPAGESREQ pReq;
1557 rc = GMMR3FreePagesPrepare(pVM, &pReq, cDirty, GMMACCOUNT_BASE);
1558 AssertRCReturn(rc, rc);
1559
1560 uint32_t iReqPage = 0;
1561 for (iPage = 0; iPage < cPages; iPage++)
1562 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
1563 {
1564 pReq->aPages[iReqPage].idPage = PGM_PAGE_GET_PAGEID(&pRom->aPages[iPage].Shadow);
1565 iReqPage++;
1566 }
1567
1568 rc = GMMR3FreePagesPerform(pVM, pReq);
1569 GMMR3FreePagesCleanup(pReq);
1570 AssertRCReturn(rc, rc);
1571
1572 /* setup the zero page. */
1573 for (iPage = 0; iPage < cPages; iPage++)
1574 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
1575 PGM_PAGE_INIT_ZERO_REAL(&pRom->aPages[iPage].Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
1576 }
1577 }
1578 else
1579 {
1580 /* clear all the pages. */
1581 for (uint32_t iPage = 0; iPage < cPages; iPage++)
1582 {
1583 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
1584 rc = pgmPhysPageMakeWritable(pVM, &pRom->aPages[iPage].Shadow, GCPhys);
1585 if (RT_FAILURE(rc))
1586 break;
1587
1588 void *pvDstPage;
1589 PPGMPAGEMAP pMapIgnored;
1590 rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pMapIgnored, &pvDstPage);
1591 if (RT_FAILURE(rc))
1592 break;
1593 ASMMemZeroPage(pvDstPage);
1594 }
1595 AssertRCReturn(rc, rc);
1596 }
1597 }
1598
1599#ifdef VBOX_STRICT
1600 /*
1601 * Verify that the virgin page is unchanged if possible.
1602 */
1603 if (pRom->pvOriginal)
1604 {
1605 uint8_t const *pbSrcPage = (uint8_t const *)pRom->pvOriginal;
1606 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
1607 {
1608 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
1609 PPGMPAGEMAP pMapIgnored;
1610 void *pvDstPage;
1611 int rc = pgmPhysPageMap(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pMapIgnored, &pvDstPage);
1612 if (RT_FAILURE(rc))
1613 break;
1614 if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
1615 LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
1616 GCPhys, pRom->pszDesc));
1617 }
1618 }
1619#endif
1620 }
1621
1622 return VINF_SUCCESS;
1623}
1624
1625
1626/**
1627 * Change the shadowing of a range of ROM pages.
1628 *
1629 * This is intended for implementing chipset specific memory registers
1630 * and will not be very strict about the input. It will silently ignore
1631 * any pages that are not the part of a shadowed ROM.
1632 *
1633 * @returns VBox status code.
1634 * @param pVM Pointer to the shared VM structure.
1635 * @param GCPhys Where to start. Page aligned.
1636 * @param cb How much to change. Page aligned.
1637 * @param enmProt The new ROM protection.
1638 */
1639VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
1640{
1641 /*
1642 * Check input
1643 */
1644 if (!cb)
1645 return VINF_SUCCESS;
1646 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1647 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1648 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1649 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1650 AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
1651
1652 /*
1653 * Process the request.
1654 */
1655 bool fFlushedPool = false;
1656 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
1657 if ( GCPhys <= pRom->GCPhysLast
1658 && GCPhysLast >= pRom->GCPhys)
1659 {
1660 /*
1661 * Iterate the relevant pages and the ncessary make changes.
1662 */
1663 bool fChanges = false;
1664 uint32_t const cPages = pRom->GCPhysLast > GCPhysLast
1665 ? pRom->cb >> PAGE_SHIFT
1666 : (GCPhysLast - pRom->GCPhys) >> PAGE_SHIFT;
1667 for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
1668 iPage < cPages;
1669 iPage++)
1670 {
1671 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
1672 if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
1673 {
1674 fChanges = true;
1675
1676 /* flush the page pool first so we don't leave any usage references dangling. */
1677 if (!fFlushedPool)
1678 {
1679 pgmPoolFlushAll(pVM);
1680 fFlushedPool = true;
1681 }
1682
1683 PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
1684 PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
1685 PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
1686
1687 *pOld = *pRamPage;
1688 *pRamPage = *pNew;
1689 /** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
1690 }
1691 }
1692
1693 /*
1694 * Reset the access handler if we made changes, no need
1695 * to optimize this.
1696 */
1697 if (fChanges)
1698 {
1699 int rc = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
1700 AssertRCReturn(rc, rc);
1701 }
1702
1703 /* Advance - cb isn't updated. */
1704 GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
1705 }
1706
1707 return VINF_SUCCESS;
1708}
1709
1710#ifndef VBOX_WITH_NEW_PHYS_CODE
1711
1712/**
1713 * Interface that the MMR3RamRegister(), MMR3RomRegister() and MMIO handler
1714 * registration APIs calls to inform PGM about memory registrations.
1715 *
1716 * It registers the physical memory range with PGM. MM is responsible
1717 * for the toplevel things - allocation and locking - while PGM is taking
1718 * care of all the details and implements the physical address space virtualization.
1719 *
1720 * @returns VBox status.
1721 * @param pVM The VM handle.
1722 * @param pvRam HC virtual address of the RAM range. (page aligned)
1723 * @param GCPhys GC physical address of the RAM range. (page aligned)
1724 * @param cb Size of the RAM range. (page aligned)
1725 * @param fFlags Flags, MM_RAM_*.
1726 * @param paPages Pointer an array of physical page descriptors.
1727 * @param pszDesc Description string.
1728 */
1729VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc)
1730{
1731 /*
1732 * Validate input.
1733 * (Not so important because callers are only MMR3PhysRegister()
1734 * and PGMR3HandlerPhysicalRegisterEx(), but anyway...)
1735 */
1736 Log(("PGMR3PhysRegister %08X %x bytes flags %x %s\n", GCPhys, cb, fFlags, pszDesc));
1737
1738 Assert((fFlags & (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_DYNAMIC_ALLOC)) || paPages);
1739 /*Assert(!(fFlags & MM_RAM_FLAGS_RESERVED) || !paPages);*/
1740 Assert((fFlags == (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_MMIO)) || (fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) || pvRam);
1741 /*Assert(!(fFlags & MM_RAM_FLAGS_RESERVED) || !pvRam);*/
1742 Assert(!(fFlags & ~0xfff));
1743 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
1744 Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
1745 Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2 | MM_RAM_FLAGS_DYNAMIC_ALLOC)));
1746 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
1747 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1748 if (GCPhysLast < GCPhys)
1749 {
1750 AssertMsgFailed(("The range wraps! GCPhys=%RGp cb=%#x\n", GCPhys, cb));
1751 return VERR_INVALID_PARAMETER;
1752 }
1753
1754 /*
1755 * Find range location and check for conflicts.
1756 */
1757 PPGMRAMRANGE pPrev = NULL;
1758 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
1759 while (pCur)
1760 {
1761 if (GCPhys <= pCur->GCPhysLast && GCPhysLast >= pCur->GCPhys)
1762 {
1763 AssertMsgFailed(("Conflict! This cannot happen!\n"));
1764 return VERR_PGM_RAM_CONFLICT;
1765 }
1766 if (GCPhysLast < pCur->GCPhys)
1767 break;
1768
1769 /* next */
1770 pPrev = pCur;
1771 pCur = pCur->pNextR3;
1772 }
1773
1774 /*
1775 * Allocate RAM range.
1776 * Small ranges are allocated from the heap, big ones have separate mappings.
1777 */
1778 size_t cbRam = RT_OFFSETOF(PGMRAMRANGE, aPages[cb >> PAGE_SHIFT]);
1779 PPGMRAMRANGE pNew;
1780 int rc = VERR_NO_MEMORY;
1781 if (cbRam > PAGE_SIZE / 2)
1782 { /* large */
1783 cbRam = RT_ALIGN_Z(cbRam, PAGE_SIZE);
1784 rc = MMR3HyperAllocOnceNoRel(pVM, cbRam, PAGE_SIZE, MM_TAG_PGM_PHYS, (void **)&pNew);
1785 AssertMsgRC(rc, ("MMR3HyperAllocOnceNoRel(,%#x,,) -> %Rrc\n", cbRam, rc));
1786 }
1787 else
1788 { /* small */
1789 rc = MMHyperAlloc(pVM, cbRam, 16, MM_TAG_PGM, (void **)&pNew);
1790 AssertMsgRC(rc, ("MMHyperAlloc(,%#x,,,) -> %Rrc\n", cbRam, rc));
1791 }
1792 if (RT_SUCCESS(rc))
1793 {
1794 /*
1795 * Initialize the range.
1796 */
1797 pNew->pvR3 = pvRam;
1798 pNew->GCPhys = GCPhys;
1799 pNew->GCPhysLast = GCPhysLast;
1800 pNew->cb = cb;
1801 pNew->fFlags = fFlags;
1802 pNew->paChunkR3Ptrs = NULL;
1803
1804 unsigned iPage = (unsigned)(cb >> PAGE_SHIFT);
1805 if (paPages)
1806 {
1807 while (iPage-- > 0)
1808 {
1809 PGM_PAGE_INIT(&pNew->aPages[iPage], paPages[iPage].Phys & X86_PTE_PAE_PG_MASK, NIL_GMM_PAGEID,
1810 fFlags & MM_RAM_FLAGS_MMIO2 ? PGMPAGETYPE_MMIO2 : PGMPAGETYPE_RAM,
1811 PGM_PAGE_STATE_ALLOCATED);
1812 pNew->aPages[iPage].HCPhys |= fFlags; /** @todo PAGE FLAGS*/
1813 }
1814 }
1815 else if (fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1816 {
1817 /* Allocate memory for chunk to HC ptr lookup array. */
1818 rc = MMHyperAlloc(pVM, (cb >> PGM_DYNAMIC_CHUNK_SHIFT) * sizeof(void *), 16, MM_TAG_PGM, (void **)&pNew->paChunkR3Ptrs);
1819 AssertMsgReturn(rc == VINF_SUCCESS, ("MMHyperAlloc(,%#x,,,) -> %Rrc\n", cbRam, cb), rc);
1820
1821 /* Physical memory will be allocated on demand. */
1822 while (iPage-- > 0)
1823 {
1824 PGM_PAGE_INIT(&pNew->aPages[iPage], 0, NIL_GMM_PAGEID, PGMPAGETYPE_RAM, PGM_PAGE_STATE_ZERO);
1825 pNew->aPages[iPage].HCPhys = fFlags; /** @todo PAGE FLAGS */
1826 }
1827 }
1828 else
1829 {
1830 Assert(fFlags == (MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_MMIO));
1831 RTHCPHYS HCPhysDummyPage = MMR3PageDummyHCPhys(pVM);
1832 while (iPage-- > 0)
1833 {
1834 PGM_PAGE_INIT(&pNew->aPages[iPage], HCPhysDummyPage, NIL_GMM_PAGEID, PGMPAGETYPE_MMIO, PGM_PAGE_STATE_ZERO);
1835 pNew->aPages[iPage].HCPhys |= fFlags; /** @todo PAGE FLAGS*/
1836 }
1837 }
1838
1839 /*
1840 * Insert the new RAM range.
1841 */
1842 pgmLock(pVM);
1843 pNew->pNextR3 = pCur;
1844 pNew->pNextR0 = pCur ? MMHyperCCToR0(pVM, pCur) : NIL_RTR0PTR;
1845 pNew->pNextRC = pCur ? MMHyperCCToRC(pVM, pCur) : NIL_RTRCPTR;
1846 if (pPrev)
1847 {
1848 pPrev->pNextR3 = pNew;
1849 pPrev->pNextR0 = MMHyperCCToR0(pVM, pNew);
1850 pPrev->pNextRC = MMHyperCCToRC(pVM, pNew);
1851 }
1852 else
1853 {
1854 pVM->pgm.s.pRamRangesR3 = pNew;
1855 pVM->pgm.s.pRamRangesR0 = MMHyperCCToR0(pVM, pNew);
1856 pVM->pgm.s.pRamRangesRC = MMHyperCCToRC(pVM, pNew);
1857 }
1858 pgmUnlock(pVM);
1859 }
1860 return rc;
1861}
1862
1863
1864/**
1865 * Register a chunk of a the physical memory range with PGM. MM is responsible
1866 * for the toplevel things - allocation and locking - while PGM is taking
1867 * care of all the details and implements the physical address space virtualization.
1868 *
1869 *
1870 * @returns VBox status.
1871 * @param pVM The VM handle.
1872 * @param pvRam HC virtual address of the RAM range. (page aligned)
1873 * @param GCPhys GC physical address of the RAM range. (page aligned)
1874 * @param cb Size of the RAM range. (page aligned)
1875 * @param fFlags Flags, MM_RAM_*.
1876 * @param paPages Pointer an array of physical page descriptors.
1877 * @param pszDesc Description string.
1878 */
1879VMMR3DECL(int) PGMR3PhysRegisterChunk(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc)
1880{
1881 NOREF(pszDesc);
1882
1883 /*
1884 * Validate input.
1885 * (Not so important because callers are only MMR3PhysRegister()
1886 * and PGMR3HandlerPhysicalRegisterEx(), but anyway...)
1887 */
1888 Log(("PGMR3PhysRegisterChunk %08X %x bytes flags %x %s\n", GCPhys, cb, fFlags, pszDesc));
1889
1890 Assert(paPages);
1891 Assert(pvRam);
1892 Assert(!(fFlags & ~0xfff));
1893 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
1894 Assert(RT_ALIGN_P(pvRam, PAGE_SIZE) == pvRam);
1895 Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2 | MM_RAM_FLAGS_DYNAMIC_ALLOC)));
1896 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
1897 Assert(VM_IS_EMT(pVM));
1898 Assert(!(GCPhys & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
1899 Assert(cb == PGM_DYNAMIC_CHUNK_SIZE);
1900
1901 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1902 if (GCPhysLast < GCPhys)
1903 {
1904 AssertMsgFailed(("The range wraps! GCPhys=%RGp cb=%#x\n", GCPhys, cb));
1905 return VERR_INVALID_PARAMETER;
1906 }
1907
1908 /*
1909 * Find existing range location.
1910 */
1911 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1912 while (pRam)
1913 {
1914 RTGCPHYS off = GCPhys - pRam->GCPhys;
1915 if ( off < pRam->cb
1916 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC))
1917 break;
1918
1919 pRam = pRam->CTX_SUFF(pNext);
1920 }
1921 AssertReturn(pRam, VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS);
1922
1923 unsigned off = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1924 unsigned iPage = (unsigned)(cb >> PAGE_SHIFT);
1925 if (paPages)
1926 {
1927 while (iPage-- > 0)
1928 pRam->aPages[off + iPage].HCPhys = (paPages[iPage].Phys & X86_PTE_PAE_PG_MASK) | fFlags; /** @todo PAGE FLAGS */
1929 }
1930 off >>= (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
1931 pRam->paChunkR3Ptrs[off] = (uintptr_t)pvRam;
1932
1933 /* Notify the recompiler. */
1934 REMR3NotifyPhysRamChunkRegister(pVM, GCPhys, PGM_DYNAMIC_CHUNK_SIZE, (RTHCUINTPTR)pvRam, fFlags);
1935
1936 return VINF_SUCCESS;
1937}
1938
1939
1940/**
1941 * Allocate missing physical pages for an existing guest RAM range.
1942 *
1943 * @returns VBox status.
1944 * @param pVM The VM handle.
1945 * @param GCPhys GC physical address of the RAM range. (page aligned)
1946 */
1947VMMR3DECL(int) PGM3PhysGrowRange(PVM pVM, PCRTGCPHYS pGCPhys)
1948{
1949 RTGCPHYS GCPhys = *pGCPhys;
1950
1951 /*
1952 * Walk range list.
1953 */
1954 pgmLock(pVM);
1955
1956 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1957 while (pRam)
1958 {
1959 RTGCPHYS off = GCPhys - pRam->GCPhys;
1960 if ( off < pRam->cb
1961 && (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC))
1962 {
1963 bool fRangeExists = false;
1964 unsigned off = (GCPhys - pRam->GCPhys) >> PGM_DYNAMIC_CHUNK_SHIFT;
1965
1966 /* Note: A request made from another thread may end up in EMT after somebody else has already allocated the range. */
1967 if (pRam->paChunkR3Ptrs[off])
1968 fRangeExists = true;
1969
1970 pgmUnlock(pVM);
1971 if (fRangeExists)
1972 return VINF_SUCCESS;
1973 return pgmr3PhysGrowRange(pVM, GCPhys);
1974 }
1975
1976 pRam = pRam->CTX_SUFF(pNext);
1977 }
1978 pgmUnlock(pVM);
1979 return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
1980}
1981
1982
1983/**
1984 * Allocate missing physical pages for an existing guest RAM range.
1985 *
1986 * @returns VBox status.
1987 * @param pVM The VM handle.
1988 * @param pRamRange RAM range
1989 * @param GCPhys GC physical address of the RAM range. (page aligned)
1990 */
1991int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys)
1992{
1993 void *pvRam;
1994 int rc;
1995
1996 /* We must execute this function in the EMT thread, otherwise we'll run into problems. */
1997 if (!VM_IS_EMT(pVM))
1998 {
1999 PVMREQ pReq;
2000 const RTGCPHYS GCPhysParam = GCPhys;
2001
2002 AssertMsg(!PDMCritSectIsOwner(&pVM->pgm.s.CritSect), ("We own the PGM lock -> deadlock danger!!\n"));
2003
2004 rc = VMR3ReqCall(pVM, VMREQDEST_ANY, &pReq, RT_INDEFINITE_WAIT, (PFNRT)PGM3PhysGrowRange, 2, pVM, &GCPhysParam);
2005 if (RT_SUCCESS(rc))
2006 {
2007 rc = pReq->iStatus;
2008 VMR3ReqFree(pReq);
2009 }
2010 return rc;
2011 }
2012
2013 /* Round down to chunk boundary */
2014 GCPhys = GCPhys & PGM_DYNAMIC_CHUNK_BASE_MASK;
2015
2016 STAM_COUNTER_INC(&pVM->pgm.s.StatR3DynRamGrow);
2017 STAM_COUNTER_ADD(&pVM->pgm.s.StatR3DynRamTotal, PGM_DYNAMIC_CHUNK_SIZE/(1024*1024));
2018
2019 Log(("pgmr3PhysGrowRange: allocate chunk of size 0x%X at %RGp\n", PGM_DYNAMIC_CHUNK_SIZE, GCPhys));
2020
2021 unsigned cPages = PGM_DYNAMIC_CHUNK_SIZE >> PAGE_SHIFT;
2022
2023 for (;;)
2024 {
2025 rc = SUPPageAlloc(cPages, &pvRam);
2026 if (RT_SUCCESS(rc))
2027 {
2028 rc = MMR3PhysRegisterEx(pVM, pvRam, GCPhys, PGM_DYNAMIC_CHUNK_SIZE, 0, MM_PHYS_TYPE_DYNALLOC_CHUNK, "Main Memory");
2029 if (RT_SUCCESS(rc))
2030 return rc;
2031
2032 SUPPageFree(pvRam, cPages);
2033 }
2034
2035 VMSTATE enmVMState = VMR3GetState(pVM);
2036 if (enmVMState != VMSTATE_RUNNING)
2037 {
2038 AssertMsgFailed(("Out of memory while trying to allocate a guest RAM chunk at %RGp!\n", GCPhys));
2039 LogRel(("PGM: Out of memory while trying to allocate a guest RAM chunk at %RGp (VMstate=%s)!\n", GCPhys, VMR3GetStateName(enmVMState)));
2040 return rc;
2041 }
2042
2043 LogRel(("pgmr3PhysGrowRange: out of memory. pause until the user resumes execution.\n"));
2044
2045 /* Pause first, then inform Main. */
2046 rc = VMR3SuspendNoSave(pVM);
2047 AssertRC(rc);
2048
2049 VMSetRuntimeError(pVM, false, "HostMemoryLow", "Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM");
2050
2051 /* Wait for resume event; will only return in that case. If the VM is stopped, the EMT thread will be destroyed. */
2052 rc = VMR3WaitForResume(pVM);
2053
2054 /* Retry */
2055 LogRel(("pgmr3PhysGrowRange: VM execution resumed -> retry.\n"));
2056 }
2057}
2058
2059
2060/**
2061 * Interface MMR3RomRegister() and MMR3PhysReserve calls to update the
2062 * flags of existing RAM ranges.
2063 *
2064 * @returns VBox status.
2065 * @param pVM The VM handle.
2066 * @param GCPhys GC physical address of the RAM range. (page aligned)
2067 * @param cb Size of the RAM range. (page aligned)
2068 * @param fFlags The Or flags, MM_RAM_* \#defines.
2069 * @param fMask The and mask for the flags.
2070 */
2071VMMR3DECL(int) PGMR3PhysSetFlags(PVM pVM, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, unsigned fMask)
2072{
2073 Log(("PGMR3PhysSetFlags %08X %x %x %x\n", GCPhys, cb, fFlags, fMask));
2074
2075 /*
2076 * Validate input.
2077 * (Not so important because caller is always MMR3RomRegister() and MMR3PhysReserve(), but anyway...)
2078 */
2079 Assert(!(fFlags & ~(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2)));
2080 Assert(RT_ALIGN_Z(cb, PAGE_SIZE) == cb && cb);
2081 Assert(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys);
2082 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2083 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2084
2085 /*
2086 * Lookup the range.
2087 */
2088 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2089 while (pRam && GCPhys > pRam->GCPhysLast)
2090 pRam = pRam->CTX_SUFF(pNext);
2091 if ( !pRam
2092 || GCPhys > pRam->GCPhysLast
2093 || GCPhysLast < pRam->GCPhys)
2094 {
2095 AssertMsgFailed(("No RAM range for %RGp-%RGp\n", GCPhys, GCPhysLast));
2096 return VERR_INVALID_PARAMETER;
2097 }
2098
2099 /*
2100 * Update the requested flags.
2101 */
2102 RTHCPHYS fFullMask = ~(RTHCPHYS)(MM_RAM_FLAGS_RESERVED | MM_RAM_FLAGS_ROM | MM_RAM_FLAGS_MMIO | MM_RAM_FLAGS_MMIO2)
2103 | fMask;
2104 unsigned iPageEnd = (GCPhysLast - pRam->GCPhys + 1) >> PAGE_SHIFT;
2105 unsigned iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2106 for ( ; iPage < iPageEnd; iPage++)
2107 pRam->aPages[iPage].HCPhys = (pRam->aPages[iPage].HCPhys & fFullMask) | fFlags; /** @todo PAGE FLAGS */
2108
2109 return VINF_SUCCESS;
2110}
2111
2112#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2113
2114/**
2115 * Sets the Address Gate 20 state.
2116 *
2117 * @param pVM VM handle.
2118 * @param fEnable True if the gate should be enabled.
2119 * False if the gate should be disabled.
2120 */
2121VMMDECL(void) PGMR3PhysSetA20(PVM pVM, bool fEnable)
2122{
2123 LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVM->pgm.s.fA20Enabled));
2124 if (pVM->pgm.s.fA20Enabled != (RTUINT)fEnable)
2125 {
2126 pVM->pgm.s.fA20Enabled = fEnable;
2127 pVM->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2128 REMR3A20Set(pVM, fEnable);
2129 /** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
2130 }
2131}
2132
2133
2134/**
2135 * Tree enumeration callback for dealing with age rollover.
2136 * It will perform a simple compression of the current age.
2137 */
2138static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
2139{
2140 /* Age compression - ASSUMES iNow == 4. */
2141 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2142 if (pChunk->iAge >= UINT32_C(0xffffff00))
2143 pChunk->iAge = 3;
2144 else if (pChunk->iAge >= UINT32_C(0xfffff000))
2145 pChunk->iAge = 2;
2146 else if (pChunk->iAge)
2147 pChunk->iAge = 1;
2148 else /* iAge = 0 */
2149 pChunk->iAge = 4;
2150
2151 /* reinsert */
2152 PVM pVM = (PVM)pvUser;
2153 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2154 pChunk->AgeCore.Key = pChunk->iAge;
2155 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2156 return 0;
2157}
2158
2159
2160/**
2161 * Tree enumeration callback that updates the chunks that have
2162 * been used since the last
2163 */
2164static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
2165{
2166 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2167 if (!pChunk->iAge)
2168 {
2169 PVM pVM = (PVM)pvUser;
2170 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2171 pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
2172 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2173 }
2174
2175 return 0;
2176}
2177
2178
2179/**
2180 * Performs ageing of the ring-3 chunk mappings.
2181 *
2182 * @param pVM The VM handle.
2183 */
2184VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
2185{
2186 pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
2187 pVM->pgm.s.ChunkR3Map.iNow++;
2188 if (pVM->pgm.s.ChunkR3Map.iNow == 0)
2189 {
2190 pVM->pgm.s.ChunkR3Map.iNow = 4;
2191 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
2192 }
2193 else
2194 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingCallback, pVM);
2195}
2196
2197
2198/**
2199 * The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
2200 */
2201typedef struct PGMR3PHYSCHUNKUNMAPCB
2202{
2203 PVM pVM; /**< The VM handle. */
2204 PPGMCHUNKR3MAP pChunk; /**< The chunk to unmap. */
2205} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
2206
2207
2208/**
2209 * Callback used to find the mapping that's been unused for
2210 * the longest time.
2211 */
2212static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
2213{
2214 do
2215 {
2216 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
2217 if ( pChunk->iAge
2218 && !pChunk->cRefs)
2219 {
2220 /*
2221 * Check that it's not in any of the TLBs.
2222 */
2223 PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
2224 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2225 if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
2226 {
2227 pChunk = NULL;
2228 break;
2229 }
2230 if (pChunk)
2231 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
2232 if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
2233 {
2234 pChunk = NULL;
2235 break;
2236 }
2237 if (pChunk)
2238 {
2239 ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
2240 return 1; /* done */
2241 }
2242 }
2243
2244 /* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
2245 pNode = pNode->pList;
2246 } while (pNode);
2247 return 0;
2248}
2249
2250
2251/**
2252 * Finds a good candidate for unmapping when the ring-3 mapping cache is full.
2253 *
2254 * The candidate will not be part of any TLBs, so no need to flush
2255 * anything afterwards.
2256 *
2257 * @returns Chunk id.
2258 * @param pVM The VM handle.
2259 */
2260static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
2261{
2262 /*
2263 * Do tree ageing first?
2264 */
2265 if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
2266 PGMR3PhysChunkAgeing(pVM);
2267
2268 /*
2269 * Enumerate the age tree starting with the left most node.
2270 */
2271 PGMR3PHYSCHUNKUNMAPCB Args;
2272 Args.pVM = pVM;
2273 Args.pChunk = NULL;
2274 if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /*fFromLeft*/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
2275 return Args.pChunk->Core.Key;
2276 return INT32_MAX;
2277}
2278
2279
2280/**
2281 * Maps the given chunk into the ring-3 mapping cache.
2282 *
2283 * This will call ring-0.
2284 *
2285 * @returns VBox status code.
2286 * @param pVM The VM handle.
2287 * @param idChunk The chunk in question.
2288 * @param ppChunk Where to store the chunk tracking structure.
2289 *
2290 * @remarks Called from within the PGM critical section.
2291 */
2292int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
2293{
2294 int rc;
2295 /*
2296 * Allocate a new tracking structure first.
2297 */
2298#if 0 /* for later when we've got a separate mapping method for ring-0. */
2299 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
2300 AssertReturn(pChunk, VERR_NO_MEMORY);
2301#else
2302 PPGMCHUNKR3MAP pChunk;
2303 rc = MMHyperAlloc(pVM, sizeof(*pChunk), 0, MM_TAG_PGM_CHUNK_MAPPING, (void **)&pChunk);
2304 AssertRCReturn(rc, rc);
2305#endif
2306 pChunk->Core.Key = idChunk;
2307 pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
2308 pChunk->iAge = 0;
2309 pChunk->cRefs = 0;
2310 pChunk->cPermRefs = 0;
2311 pChunk->pv = NULL;
2312
2313 /*
2314 * Request the ring-0 part to map the chunk in question and if
2315 * necessary unmap another one to make space in the mapping cache.
2316 */
2317 GMMMAPUNMAPCHUNKREQ Req;
2318 Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
2319 Req.Hdr.cbReq = sizeof(Req);
2320 Req.pvR3 = NULL;
2321 Req.idChunkMap = idChunk;
2322 Req.idChunkUnmap = NIL_GMM_CHUNKID;
2323 if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
2324 Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
2325 rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
2326 if (RT_SUCCESS(rc))
2327 {
2328 /*
2329 * Update the tree.
2330 */
2331 /* insert the new one. */
2332 AssertPtr(Req.pvR3);
2333 pChunk->pv = Req.pvR3;
2334 bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
2335 AssertRelease(fRc);
2336 pVM->pgm.s.ChunkR3Map.c++;
2337
2338 fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2339 AssertRelease(fRc);
2340
2341 /* remove the unmapped one. */
2342 if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
2343 {
2344 PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
2345 AssertRelease(pUnmappedChunk);
2346 pUnmappedChunk->pv = NULL;
2347 pUnmappedChunk->Core.Key = UINT32_MAX;
2348#if 0 /* for later when we've got a separate mapping method for ring-0. */
2349 MMR3HeapFree(pUnmappedChunk);
2350#else
2351 MMHyperFree(pVM, pUnmappedChunk);
2352#endif
2353 pVM->pgm.s.ChunkR3Map.c--;
2354 }
2355 }
2356 else
2357 {
2358 AssertRC(rc);
2359#if 0 /* for later when we've got a separate mapping method for ring-0. */
2360 MMR3HeapFree(pChunk);
2361#else
2362 MMHyperFree(pVM, pChunk);
2363#endif
2364 pChunk = NULL;
2365 }
2366
2367 *ppChunk = pChunk;
2368 return rc;
2369}
2370
2371
2372/**
2373 * For VMMCALLHOST_PGM_MAP_CHUNK, considered internal.
2374 *
2375 * @returns see pgmR3PhysChunkMap.
2376 * @param pVM The VM handle.
2377 * @param idChunk The chunk to map.
2378 */
2379VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
2380{
2381 PPGMCHUNKR3MAP pChunk;
2382 return pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
2383}
2384
2385
2386/**
2387 * Invalidates the TLB for the ring-3 mapping cache.
2388 *
2389 * @param pVM The VM handle.
2390 */
2391VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
2392{
2393 pgmLock(pVM);
2394 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2395 {
2396 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
2397 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
2398 }
2399 pgmUnlock(pVM);
2400}
2401
2402
2403/**
2404 * Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES.
2405 *
2406 * @returns The following VBox status codes.
2407 * @retval VINF_SUCCESS on success. FF cleared.
2408 * @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in this case.
2409 *
2410 * @param pVM The VM handle.
2411 */
2412VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
2413{
2414 pgmLock(pVM);
2415 int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
2416 if (rc == VERR_GMM_SEED_ME)
2417 {
2418 void *pvChunk;
2419 rc = SUPPageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
2420 if (RT_SUCCESS(rc))
2421 rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
2422 if (RT_FAILURE(rc))
2423 {
2424 LogRel(("PGM: GMM Seeding failed, rc=%Rrc\n", rc));
2425 rc = VINF_EM_NO_MEMORY;
2426 }
2427 }
2428 pgmUnlock(pVM);
2429 Assert(rc == VINF_SUCCESS || rc == VINF_EM_NO_MEMORY);
2430 return rc;
2431}
2432
2433
2434/**
2435 * Converts a GC physical address to a HC ring-3 pointer, with some
2436 * additional checks.
2437 *
2438 * @returns VBox status code.
2439 * @retval VINF_SUCCESS on success.
2440 * @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
2441 * access handler of some kind.
2442 * @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
2443 * accesses or is odd in any way.
2444 * @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
2445 *
2446 * @param pVM The VM handle.
2447 * @param GCPhys The GC physical address to convert.
2448 * @param fWritable Whether write access is required.
2449 * @param ppv Where to store the pointer corresponding to GCPhys on
2450 * success.
2451 */
2452VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
2453{
2454 pgmLock(pVM);
2455
2456 PPGMRAMRANGE pRam;
2457 PPGMPAGE pPage;
2458 int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
2459 if (RT_SUCCESS(rc))
2460 {
2461#ifdef VBOX_WITH_NEW_PHYS_CODE
2462 if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
2463 rc = VINF_SUCCESS;
2464 else
2465 {
2466 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
2467 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
2468 else if (fWritable && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2469 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
2470 else
2471 {
2472 /* Temporariliy disabled phycial handler(s), since the recompiler
2473 doesn't get notified when it's reset we'll have to pretend its
2474 operating normally. */
2475 if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
2476 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
2477 else
2478 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
2479 }
2480 }
2481 if (RT_SUCCESS(rc))
2482 {
2483 /* Make sure what we return is writable. */
2484 if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
2485 switch (PGM_PAGE_GET_STATE(pPage))
2486 {
2487 case PGM_PAGE_STATE_ALLOCATED:
2488 case PGM_PAGE_STATE_ZERO:
2489 break;
2490 case PGM_PAGE_STATE_SHARED:
2491 case PGM_PAGE_STATE_WRITE_MONITORED:
2492 rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
2493 AssertLogRelRCReturn(rc, rc);
2494 break;
2495 }
2496
2497 /* Get a ring-3 mapping of the address. */
2498 PPGMPAGER3MAPTLBE pTlbe;
2499 int rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
2500 AssertLogRelRCReturn(rc, rc);
2501 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
2502 /** @todo mapping/locking hell; this isn't horribly efficient since
2503 * pgmPhysPageLoadIntoTlb will repeate the lookup we've done here. */
2504 }
2505 /* else: handler catching all access, no pointer returned. */
2506
2507#else
2508 if (0)
2509 /* nothing */;
2510 else if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
2511 {
2512 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
2513 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
2514 else if (fWritable && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2515 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
2516 else
2517 {
2518 /* Temporariliy disabled phycial handler(s), since the recompiler
2519 doesn't get notified when it's reset we'll have to pretend its
2520 operating normally. */
2521 if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
2522 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
2523 else
2524 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
2525 }
2526 }
2527 else
2528 rc = VINF_SUCCESS;
2529 if (RT_SUCCESS(rc))
2530 {
2531 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2532 {
2533 AssertMsg(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM, ("GCPhys=%RGp type=%d\n", GCPhys, PGM_PAGE_GET_TYPE(pPage)));
2534 RTGCPHYS off = GCPhys - pRam->GCPhys;
2535 unsigned iChunk = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
2536 *ppv = (void *)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
2537 }
2538 else if (RT_LIKELY(pRam->pvR3))
2539 {
2540 AssertMsg(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO2, ("GCPhys=%RGp type=%d\n", GCPhys, PGM_PAGE_GET_TYPE(pPage)));
2541 RTGCPHYS off = GCPhys - pRam->GCPhys;
2542 *ppv = (uint8_t *)pRam->pvR3 + off;
2543 }
2544 else
2545 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
2546 }
2547#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2548 }
2549 else
2550 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
2551
2552 pgmUnlock(pVM);
2553 return rc;
2554}
2555
2556
2557
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