PGMSavedState.cpp@ 31080

Last change on this file since 31080 was 31080, checked in by vboxsync, 14 years ago
PGM: Micro optimizations.
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1	/* $Id: PGMSavedState.cpp 31080 2010-07-24 17:25:32Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM
23	#include <VBox/pgm.h>
24	#include <VBox/stam.h>
25	#include <VBox/ssm.h>
26	#include <VBox/pdmdrv.h>
27	#include <VBox/pdmdev.h>
28	#include "PGMInternal.h"
29	#include <VBox/vm.h>
30	#include "PGMInline.h"
31
32	#include <VBox/param.h>
33	#include <VBox/err.h>
34
35	#include <iprt/asm.h>
36	#include <iprt/assert.h>
37	#include <iprt/crc32.h>
38	#include <iprt/mem.h>
39	#include <iprt/sha.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42
43
44	/*******************************************************************************
45	* Defined Constants And Macros *
46	*******************************************************************************/
47	/** Saved state data unit version.
48	* @todo remove the guest mappings from the saved state at next version change! */
49	#define PGM_SAVED_STATE_VERSION 12
50	/** Saved state before the balloon change. */
51	#define PGM_SAVED_STATE_VERSION_PRE_BALLOON 11
52	/** Saved state data unit version used during 3.1 development, misses the RAM
53	* config. */
54	#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
55	/** Saved state data unit version for 3.0 (pre teleportation). */
56	#define PGM_SAVED_STATE_VERSION_3_0_0 9
57	/** Saved state data unit version for 2.2.2 and later. */
58	#define PGM_SAVED_STATE_VERSION_2_2_2 8
59	/** Saved state data unit version for 2.2.0. */
60	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
61	/** Saved state data unit version. */
62	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
63
64
65	/** @name Sparse state record types
66	* @{ */
67	/** Zero page. No data. */
68	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
69	/** Raw page. */
70	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
71	/** Raw MMIO2 page. */
72	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
73	/** Zero MMIO2 page. */
74	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
75	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
76	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
77	/** Raw shadowed ROM page. The protection (8-bit) preceeds the raw bits. */
78	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
79	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
80	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
81	/** ROM protection (8-bit). */
82	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
83	/** The last record type. */
84	#define PGM_STATE_REC_LAST PGM_STATE_REC_ROM_PROT
85	/** End marker. */
86	#define PGM_STATE_REC_END UINT8_C(0xff)
87	/** Flag indicating that the data is preceeded by the page address.
88	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
89	* range ID and a 32-bit page index.
90	*/
91	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
92	/** @} */
93
94	/** The CRC-32 for a zero page. */
95	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
96	/** The CRC-32 for a zero half page. */
97	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
98
99
100	/*******************************************************************************
101	* Structures and Typedefs *
102	*******************************************************************************/
103	/** For loading old saved states. (pre-smp) */
104	typedef struct
105	{
106	/** If set no conflict checks are required. (boolean) */
107	bool fMappingsFixed;
108	/** Size of fixed mapping */
109	uint32_t cbMappingFixed;
110	/** Base address (GC) of fixed mapping */
111	RTGCPTR GCPtrMappingFixed;
112	/** A20 gate mask.
113	* Our current approach to A20 emulation is to let REM do it and don't bother
114	* anywhere else. The interesting guests will be operating with it enabled anyway.
115	* But should the need arise, we'll subject physical addresses to this mask. */
116	RTGCPHYS GCPhysA20Mask;
117	/** A20 gate state - boolean! */
118	bool fA20Enabled;
119	/** The guest paging mode. */
120	PGMMODE enmGuestMode;
121	} PGMOLD;
122
123
124	/*******************************************************************************
125	* Global Variables *
126	*******************************************************************************/
127	/** PGM fields to save/load. */
128
129	static const SSMFIELD s_aPGMFields[] =
130	{
131	SSMFIELD_ENTRY( PGM, fMappingsFixed),
132	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
133	SSMFIELD_ENTRY( PGM, cbMappingFixed),
134	SSMFIELD_ENTRY( PGM, cBalloonedPages),
135	SSMFIELD_ENTRY_TERM()
136	};
137
138	static const SSMFIELD s_aPGMFieldsPreBalloon[] =
139	{
140	SSMFIELD_ENTRY( PGM, fMappingsFixed),
141	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
142	SSMFIELD_ENTRY( PGM, cbMappingFixed),
143	SSMFIELD_ENTRY_TERM()
144	};
145
146	static const SSMFIELD s_aPGMCpuFields[] =
147	{
148	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
149	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
150	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
151	SSMFIELD_ENTRY_TERM()
152	};
153
154	static const SSMFIELD s_aPGMFields_Old[] =
155	{
156	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
157	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
158	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
159	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
160	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
161	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
162	SSMFIELD_ENTRY_TERM()
163	};
164
165
166	/**
167	* Find the ROM tracking structure for the given page.
168	*
169	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
170	* that it's a ROM page.
171	* @param pVM The VM handle.
172	* @param GCPhys The address of the ROM page.
173	*/
174	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
175	{
176	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
177	pRomRange;
178	pRomRange = pRomRange->CTX_SUFF(pNext))
179	{
180	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
181	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
182	return &pRomRange->aPages[off >> PAGE_SHIFT];
183	}
184	return NULL;
185	}
186
187
188	/**
189	* Prepares the ROM pages for a live save.
190	*
191	* @returns VBox status code.
192	* @param pVM The VM handle.
193	*/
194	static int pgmR3PrepRomPages(PVM pVM)
195	{
196	/*
197	* Initialize the live save tracking in the ROM page descriptors.
198	*/
199	pgmLock(pVM);
200	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
201	{
202	PPGMRAMRANGE pRamHint = NULL;;
203	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
204
205	for (uint32_t iPage = 0; iPage < cPages; iPage++)
206	{
207	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
208	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
209	pRom->aPages[iPage].LiveSave.fDirty = true;
210	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
211	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
212	{
213	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
214	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
215	else
216	{
217	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
218	PPGMPAGE pPage;
219	int rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
220	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
221	if (RT_SUCCESS(rc))
222	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage) && !PGM_PAGE_IS_BALLOONED(pPage);
223	else
224	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
225	}
226	}
227	}
228
229	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
230	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
231	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
232	}
233	pgmUnlock(pVM);
234
235	return VINF_SUCCESS;
236	}
237
238
239	/**
240	* Assigns IDs to the ROM ranges and saves them.
241	*
242	* @returns VBox status code.
243	* @param pVM The VM handle.
244	* @param pSSM Saved state handle.
245	*/
246	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
247	{
248	pgmLock(pVM);
249	uint8_t id = 1;
250	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
251	{
252	pRom->idSavedState = id;
253	SSMR3PutU8(pSSM, id);
254	SSMR3PutStrZ(pSSM, ""); /* device name */
255	SSMR3PutU32(pSSM, 0); /* device instance */
256	SSMR3PutU8(pSSM, 0); /* region */
257	SSMR3PutStrZ(pSSM, pRom->pszDesc);
258	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
259	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
260	if (RT_FAILURE(rc))
261	break;
262	}
263	pgmUnlock(pVM);
264	return SSMR3PutU8(pSSM, UINT8_MAX);
265	}
266
267
268	/**
269	* Loads the ROM range ID assignments.
270	*
271	* @returns VBox status code.
272	*
273	* @param pVM The VM handle.
274	* @param pSSM The saved state handle.
275	*/
276	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
277	{
278	Assert(PGMIsLockOwner(pVM));
279
280	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
281	pRom->idSavedState = UINT8_MAX;
282
283	for (;;)
284	{
285	/*
286	* Read the data.
287	*/
288	uint8_t id;
289	int rc = SSMR3GetU8(pSSM, &id);
290	if (RT_FAILURE(rc))
291	return rc;
292	if (id == UINT8_MAX)
293	{
294	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
295	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX,
296	("The \"%s\" ROM was not found in the saved state. Probably due to some misconfiguration\n",
297	pRom->pszDesc));
298	return VINF_SUCCESS; /* the end */
299	}
300	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
301
302	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
303	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
304	AssertLogRelRCReturn(rc, rc);
305
306	uint32_t uInstance;
307	SSMR3GetU32(pSSM, &uInstance);
308	uint8_t iRegion;
309	SSMR3GetU8(pSSM, &iRegion);
310
311	char szDesc[64];
312	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
313	AssertLogRelRCReturn(rc, rc);
314
315	RTGCPHYS GCPhys;
316	SSMR3GetGCPhys(pSSM, &GCPhys);
317	RTGCPHYS cb;
318	rc = SSMR3GetGCPhys(pSSM, &cb);
319	if (RT_FAILURE(rc))
320	return rc;
321	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
322	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
323
324	/*
325	* Locate a matching ROM range.
326	*/
327	AssertLogRelMsgReturn( uInstance == 0
328	&& iRegion == 0
329	&& szDevName[0] == '\0',
330	("GCPhys=%RGp %s\n", GCPhys, szDesc),
331	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
332	PPGMROMRANGE pRom;
333	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
334	{
335	if ( pRom->idSavedState == UINT8_MAX
336	&& !strcmp(pRom->pszDesc, szDesc))
337	{
338	pRom->idSavedState = id;
339	break;
340	}
341	}
342	if (!pRom)
343	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
344	} /* forever */
345	}
346
347
348	/**
349	* Scan ROM pages.
350	*
351	* @param pVM The VM handle.
352	*/
353	static void pgmR3ScanRomPages(PVM pVM)
354	{
355	/*
356	* The shadow ROMs.
357	*/
358	pgmLock(pVM);
359	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
360	{
361	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
362	{
363	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
364	for (uint32_t iPage = 0; iPage < cPages; iPage++)
365	{
366	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
367	if (pRomPage->LiveSave.fWrittenTo)
368	{
369	pRomPage->LiveSave.fWrittenTo = false;
370	if (!pRomPage->LiveSave.fDirty)
371	{
372	pRomPage->LiveSave.fDirty = true;
373	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
374	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
375	}
376	pRomPage->LiveSave.fDirtiedRecently = true;
377	}
378	else
379	pRomPage->LiveSave.fDirtiedRecently = false;
380	}
381	}
382	}
383	pgmUnlock(pVM);
384	}
385
386
387	/**
388	* Takes care of the virgin ROM pages in the first pass.
389	*
390	* This is an attempt at simplifying the handling of ROM pages a little bit.
391	* This ASSUMES that no new ROM ranges will be added and that they won't be
392	* relinked in any way.
393	*
394	* @param pVM The VM handle.
395	* @param pSSM The SSM handle.
396	* @param fLiveSave Whether we're in a live save or not.
397	*/
398	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
399	{
400	pgmLock(pVM);
401	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
402	{
403	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
404	for (uint32_t iPage = 0; iPage < cPages; iPage++)
405	{
406	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
407	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
408
409	/* Get the virgin page descriptor. */
410	PPGMPAGE pPage;
411	if (PGMROMPROT_IS_ROM(enmProt))
412	pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
413	else
414	pPage = &pRom->aPages[iPage].Virgin;
415
416	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
417	int rc = VINF_SUCCESS;
418	char abPage[PAGE_SIZE];
419	if ( !PGM_PAGE_IS_ZERO(pPage)
420	&& !PGM_PAGE_IS_BALLOONED(pPage))
421	{
422	void const *pvPage;
423	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
424	if (RT_SUCCESS(rc))
425	memcpy(abPage, pvPage, PAGE_SIZE);
426	}
427	else
428	ASMMemZeroPage(abPage);
429	pgmUnlock(pVM);
430	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
431
432	/* Save it. */
433	if (iPage > 0)
434	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
435	else
436	{
437	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
438	SSMR3PutU8(pSSM, pRom->idSavedState);
439	SSMR3PutU32(pSSM, iPage);
440	}
441	SSMR3PutU8(pSSM, (uint8_t)enmProt);
442	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
443	if (RT_FAILURE(rc))
444	return rc;
445
446	/* Update state. */
447	pgmLock(pVM);
448	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
449	if (fLiveSave)
450	{
451	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
452	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
453	pVM->pgm.s.LiveSave.cSavedPages++;
454	}
455	}
456	}
457	pgmUnlock(pVM);
458	return VINF_SUCCESS;
459	}
460
461
462	/**
463	* Saves dirty pages in the shadowed ROM ranges.
464	*
465	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
466	*
467	* @returns VBox status code.
468	* @param pVM The VM handle.
469	* @param pSSM The SSM handle.
470	* @param fLiveSave Whether it's a live save or not.
471	* @param fFinalPass Whether this is the final pass or not.
472	*/
473	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
474	{
475	/*
476	* The Shadowed ROMs.
477	*
478	* ASSUMES that the ROM ranges are fixed.
479	* ASSUMES that all the ROM ranges are mapped.
480	*/
481	pgmLock(pVM);
482	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
483	{
484	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
485	{
486	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
487	uint32_t iPrevPage = cPages;
488	for (uint32_t iPage = 0; iPage < cPages; iPage++)
489	{
490	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
491	if ( !fLiveSave
492	\|\| ( pRomPage->LiveSave.fDirty
493	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
494	&& !pRomPage->LiveSave.fWrittenTo)
495	\|\| fFinalPass
496	)
497	)
498	)
499	{
500	uint8_t abPage[PAGE_SIZE];
501	PGMROMPROT enmProt = pRomPage->enmProt;
502	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
503	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(&pVM->pgm.s, GCPhys);
504	bool fZero = PGM_PAGE_IS_ZERO(pPage) \|\| PGM_PAGE_IS_BALLOONED(pPage);
505	int rc = VINF_SUCCESS;
506	if (!fZero)
507	{
508	void const *pvPage;
509	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
510	if (RT_SUCCESS(rc))
511	memcpy(abPage, pvPage, PAGE_SIZE);
512	}
513	if (fLiveSave && RT_SUCCESS(rc))
514	{
515	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
516	pRomPage->LiveSave.fDirty = false;
517	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
518	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
519	pVM->pgm.s.LiveSave.cSavedPages++;
520	}
521	pgmUnlock(pVM);
522	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
523
524	if (iPage - 1U == iPrevPage && iPage > 0)
525	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
526	else
527	{
528	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
529	SSMR3PutU8(pSSM, pRom->idSavedState);
530	SSMR3PutU32(pSSM, iPage);
531	}
532	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
533	if (!fZero)
534	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
535	if (RT_FAILURE(rc))
536	return rc;
537
538	pgmLock(pVM);
539	iPrevPage = iPage;
540	}
541	/*
542	* In the final pass, make sure the protection is in sync.
543	*/
544	else if ( fFinalPass
545	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
546	{
547	PGMROMPROT enmProt = pRomPage->enmProt;
548	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
549	pgmUnlock(pVM);
550
551	if (iPage - 1U == iPrevPage && iPage > 0)
552	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
553	else
554	{
555	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
556	SSMR3PutU8(pSSM, pRom->idSavedState);
557	SSMR3PutU32(pSSM, iPage);
558	}
559	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
560	if (RT_FAILURE(rc))
561	return rc;
562
563	pgmLock(pVM);
564	iPrevPage = iPage;
565	}
566	}
567	}
568	}
569	pgmUnlock(pVM);
570	return VINF_SUCCESS;
571	}
572
573
574	/**
575	* Cleans up ROM pages after a live save.
576	*
577	* @param pVM The VM handle.
578	*/
579	static void pgmR3DoneRomPages(PVM pVM)
580	{
581	NOREF(pVM);
582	}
583
584
585	/**
586	* Prepares the MMIO2 pages for a live save.
587	*
588	* @returns VBox status code.
589	* @param pVM The VM handle.
590	*/
591	static int pgmR3PrepMmio2Pages(PVM pVM)
592	{
593	/*
594	* Initialize the live save tracking in the MMIO2 ranges.
595	* ASSUME nothing changes here.
596	*/
597	pgmLock(pVM);
598	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
599	{
600	uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
601	pgmUnlock(pVM);
602
603	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
604	if (!paLSPages)
605	return VERR_NO_MEMORY;
606	for (uint32_t iPage = 0; iPage < cPages; iPage++)
607	{
608	/* Initialize it as a dirty zero page. */
609	paLSPages[iPage].fDirty = true;
610	paLSPages[iPage].cUnchangedScans = 0;
611	paLSPages[iPage].fZero = true;
612	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
613	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
614	}
615
616	pgmLock(pVM);
617	pMmio2->paLSPages = paLSPages;
618	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
619	}
620	pgmUnlock(pVM);
621	return VINF_SUCCESS;
622	}
623
624
625	/**
626	* Assigns IDs to the MMIO2 ranges and saves them.
627	*
628	* @returns VBox status code.
629	* @param pVM The VM handle.
630	* @param pSSM Saved state handle.
631	*/
632	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
633	{
634	pgmLock(pVM);
635	uint8_t id = 1;
636	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
637	{
638	pMmio2->idSavedState = id;
639	SSMR3PutU8(pSSM, id);
640	SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pReg->szName);
641	SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
642	SSMR3PutU8(pSSM, pMmio2->iRegion);
643	SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
644	int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
645	if (RT_FAILURE(rc))
646	break;
647	}
648	pgmUnlock(pVM);
649	return SSMR3PutU8(pSSM, UINT8_MAX);
650	}
651
652
653	/**
654	* Loads the MMIO2 range ID assignments.
655	*
656	* @returns VBox status code.
657	*
658	* @param pVM The VM handle.
659	* @param pSSM The saved state handle.
660	*/
661	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
662	{
663	Assert(PGMIsLockOwner(pVM));
664
665	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
666	pMmio2->idSavedState = UINT8_MAX;
667
668	for (;;)
669	{
670	/*
671	* Read the data.
672	*/
673	uint8_t id;
674	int rc = SSMR3GetU8(pSSM, &id);
675	if (RT_FAILURE(rc))
676	return rc;
677	if (id == UINT8_MAX)
678	{
679	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
680	AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
681	return VINF_SUCCESS; /* the end */
682	}
683	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
684
685	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
686	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
687	AssertLogRelRCReturn(rc, rc);
688
689	uint32_t uInstance;
690	SSMR3GetU32(pSSM, &uInstance);
691	uint8_t iRegion;
692	SSMR3GetU8(pSSM, &iRegion);
693
694	char szDesc[64];
695	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
696	AssertLogRelRCReturn(rc, rc);
697
698	RTGCPHYS cb;
699	rc = SSMR3GetGCPhys(pSSM, &cb);
700	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
701
702	/*
703	* Locate a matching MMIO2 range.
704	*/
705	PPGMMMIO2RANGE pMmio2;
706	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
707	{
708	if ( pMmio2->idSavedState == UINT8_MAX
709	&& pMmio2->iRegion == iRegion
710	&& pMmio2->pDevInsR3->iInstance == uInstance
711	&& !strcmp(pMmio2->pDevInsR3->pReg->szName, szDevName))
712	{
713	pMmio2->idSavedState = id;
714	break;
715	}
716	}
717	if (!pMmio2)
718	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
719	szDesc, szDevName, uInstance, iRegion);
720
721	/*
722	* Validate the configuration, the size of the MMIO2 region should be
723	* the same.
724	*/
725	if (cb != pMmio2->RamRange.cb)
726	{
727	LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
728	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb));
729	if (cb > pMmio2->RamRange.cb) /* bad idea? */
730	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
731	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb);
732	}
733	} /* forever */
734	}
735
736
737	/**
738	* Scans one MMIO2 page.
739	*
740	* @returns True if changed, false if unchanged.
741	*
742	* @param pVM The VM handle
743	* @param pbPage The page bits.
744	* @param pLSPage The live save tracking structure for the page.
745	*
746	*/
747	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
748	{
749	/*
750	* Special handling of zero pages.
751	*/
752	bool const fZero = pLSPage->fZero;
753	if (fZero)
754	{
755	if (ASMMemIsZeroPage(pbPage))
756	{
757	/* Not modified. */
758	if (pLSPage->fDirty)
759	pLSPage->cUnchangedScans++;
760	return false;
761	}
762
763	pLSPage->fZero = false;
764	pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
765	}
766	else
767	{
768	/*
769	* CRC the first half, if it doesn't match the page is dirty and
770	* we won't check the 2nd half (we'll do that next time).
771	*/
772	uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
773	if (u32CrcH1 == pLSPage->u32CrcH1)
774	{
775	uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
776	if (u32CrcH2 == pLSPage->u32CrcH2)
777	{
778	/* Probably not modified. */
779	if (pLSPage->fDirty)
780	pLSPage->cUnchangedScans++;
781	return false;
782	}
783
784	pLSPage->u32CrcH2 = u32CrcH2;
785	}
786	else
787	{
788	pLSPage->u32CrcH1 = u32CrcH1;
789	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
790	&& ASMMemIsZeroPage(pbPage))
791	{
792	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
793	pLSPage->fZero = true;
794	}
795	}
796	}
797
798	/* dirty page path */
799	pLSPage->cUnchangedScans = 0;
800	if (!pLSPage->fDirty)
801	{
802	pLSPage->fDirty = true;
803	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
804	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
805	if (fZero)
806	pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
807	}
808	return true;
809	}
810
811
812	/**
813	* Scan for MMIO2 page modifications.
814	*
815	* @param pVM The VM handle.
816	* @param uPass The pass number.
817	*/
818	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
819	{
820	/*
821	* Since this is a bit expensive we lower the scan rate after a little while.
822	*/
823	if ( ( (uPass & 3) != 0
824	&& uPass > 10)
825	\|\| uPass == SSM_PASS_FINAL)
826	return;
827
828	pgmLock(pVM); /* paranoia */
829	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
830	{
831	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
832	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
833	pgmUnlock(pVM);
834
835	for (uint32_t iPage = 0; iPage < cPages; iPage++)
836	{
837	uint8_t const pbPage = (uint8_t const )pMmio2->pvR3 + iPage * PAGE_SIZE;
838	pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]);
839	}
840
841	pgmLock(pVM);
842	}
843	pgmUnlock(pVM);
844
845	}
846
847
848	/**
849	* Save quiescent MMIO2 pages.
850	*
851	* @returns VBox status code.
852	* @param pVM The VM handle.
853	* @param pSSM The SSM handle.
854	* @param fLiveSave Whether it's a live save or not.
855	* @param uPass The pass number.
856	*/
857	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
858	{
859	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
860	* device that we wish to know about changes.) */
861
862	int rc = VINF_SUCCESS;
863	if (uPass == SSM_PASS_FINAL)
864	{
865	/*
866	* The mop up round.
867	*/
868	pgmLock(pVM);
869	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
870	pMmio2 && RT_SUCCESS(rc);
871	pMmio2 = pMmio2->pNextR3)
872	{
873	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
874	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
875	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
876	uint32_t iPageLast = cPages;
877	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
878	{
879	uint8_t u8Type;
880	if (!fLiveSave)
881	u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
882	else
883	{
884	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
885	if ( !paLSPages[iPage].fDirty
886	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
887	{
888	if (paLSPages[iPage].fZero)
889	continue;
890
891	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
892	RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
893	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
894	continue;
895	}
896	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
897	pVM->pgm.s.LiveSave.cSavedPages++;
898	}
899
900	if (iPage != 0 && iPage == iPageLast + 1)
901	rc = SSMR3PutU8(pSSM, u8Type);
902	else
903	{
904	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
905	SSMR3PutU8(pSSM, pMmio2->idSavedState);
906	rc = SSMR3PutU32(pSSM, iPage);
907	}
908	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
909	rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
910	if (RT_FAILURE(rc))
911	break;
912	iPageLast = iPage;
913	}
914	}
915	pgmUnlock(pVM);
916	}
917	/*
918	* Reduce the rate after a little while since the current MMIO2 approach is
919	* a bit expensive.
920	* We position it two passes after the scan pass to avoid saving busy pages.
921	*/
922	else if ( uPass <= 10
923	\|\| (uPass & 3) == 2)
924	{
925	pgmLock(pVM);
926	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
927	pMmio2 && RT_SUCCESS(rc);
928	pMmio2 = pMmio2->pNextR3)
929	{
930	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
931	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
932	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
933	uint32_t iPageLast = cPages;
934	pgmUnlock(pVM);
935
936	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
937	{
938	/* Skip clean pages and pages which hasn't quiesced. */
939	if (!paLSPages[iPage].fDirty)
940	continue;
941	if (paLSPages[iPage].cUnchangedScans < 3)
942	continue;
943	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
944	continue;
945
946	/* Save it. */
947	bool const fZero = paLSPages[iPage].fZero;
948	uint8_t abPage[PAGE_SIZE];
949	if (!fZero)
950	{
951	memcpy(abPage, pbPage, PAGE_SIZE);
952	RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
953	}
954
955	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
956	if (iPage != 0 && iPage == iPageLast + 1)
957	rc = SSMR3PutU8(pSSM, u8Type);
958	else
959	{
960	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
961	SSMR3PutU8(pSSM, pMmio2->idSavedState);
962	rc = SSMR3PutU32(pSSM, iPage);
963	}
964	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
965	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
966	if (RT_FAILURE(rc))
967	break;
968
969	/* Housekeeping. */
970	paLSPages[iPage].fDirty = false;
971	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
972	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
973	if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
974	pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
975	pVM->pgm.s.LiveSave.cSavedPages++;
976	iPageLast = iPage;
977	}
978
979	pgmLock(pVM);
980	}
981	pgmUnlock(pVM);
982	}
983
984	return rc;
985	}
986
987
988	/**
989	* Cleans up MMIO2 pages after a live save.
990	*
991	* @param pVM The VM handle.
992	*/
993	static void pgmR3DoneMmio2Pages(PVM pVM)
994	{
995	/*
996	* Free the tracking structures for the MMIO2 pages.
997	* We do the freeing outside the lock in case the VM is running.
998	*/
999	pgmLock(pVM);
1000	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
1001	{
1002	void *pvMmio2ToFree = pMmio2->paLSPages;
1003	if (pvMmio2ToFree)
1004	{
1005	pMmio2->paLSPages = NULL;
1006	pgmUnlock(pVM);
1007	MMR3HeapFree(pvMmio2ToFree);
1008	pgmLock(pVM);
1009	}
1010	}
1011	pgmUnlock(pVM);
1012	}
1013
1014
1015	/**
1016	* Prepares the RAM pages for a live save.
1017	*
1018	* @returns VBox status code.
1019	* @param pVM The VM handle.
1020	*/
1021	static int pgmR3PrepRamPages(PVM pVM)
1022	{
1023
1024	/*
1025	* Try allocating tracking structures for the ram ranges.
1026	*
1027	* To avoid lock contention, we leave the lock every time we're allocating
1028	* a new array. This means we'll have to ditch the allocation and start
1029	* all over again if the RAM range list changes in-between.
1030	*
1031	* Note! pgmR3SaveDone will always be called and it is therefore responsible
1032	* for cleaning up.
1033	*/
1034	PPGMRAMRANGE pCur;
1035	pgmLock(pVM);
1036	do
1037	{
1038	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1039	{
1040	if ( !pCur->paLSPages
1041	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1042	{
1043	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1044	uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1045	pgmUnlock(pVM);
1046	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1047	if (!paLSPages)
1048	return VERR_NO_MEMORY;
1049	pgmLock(pVM);
1050	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1051	{
1052	pgmUnlock(pVM);
1053	MMR3HeapFree(paLSPages);
1054	pgmLock(pVM);
1055	break; /* try again */
1056	}
1057	pCur->paLSPages = paLSPages;
1058
1059	/*
1060	* Initialize the array.
1061	*/
1062	uint32_t iPage = cPages;
1063	while (iPage-- > 0)
1064	{
1065	/** @todo yield critsect! (after moving this away from EMT0) */
1066	PCPGMPAGE pPage = &pCur->aPages[iPage];
1067	paLSPages[iPage].cDirtied = 0;
1068	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1069	paLSPages[iPage].fWriteMonitored = 0;
1070	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1071	paLSPages[iPage].u2Reserved = 0;
1072	switch (PGM_PAGE_GET_TYPE(pPage))
1073	{
1074	case PGMPAGETYPE_RAM:
1075	if ( PGM_PAGE_IS_ZERO(pPage)
1076	\|\| PGM_PAGE_IS_BALLOONED(pPage))
1077	{
1078	paLSPages[iPage].fZero = 1;
1079	paLSPages[iPage].fShared = 0;
1080	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1081	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1082	#endif
1083	}
1084	else if (PGM_PAGE_IS_SHARED(pPage))
1085	{
1086	paLSPages[iPage].fZero = 0;
1087	paLSPages[iPage].fShared = 1;
1088	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1089	paLSPages[iPage].u32Crc = UINT32_MAX;
1090	#endif
1091	}
1092	else
1093	{
1094	paLSPages[iPage].fZero = 0;
1095	paLSPages[iPage].fShared = 0;
1096	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1097	paLSPages[iPage].u32Crc = UINT32_MAX;
1098	#endif
1099	}
1100	paLSPages[iPage].fIgnore = 0;
1101	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1102	break;
1103
1104	case PGMPAGETYPE_ROM_SHADOW:
1105	case PGMPAGETYPE_ROM:
1106	{
1107	paLSPages[iPage].fZero = 0;
1108	paLSPages[iPage].fShared = 0;
1109	paLSPages[iPage].fDirty = 0;
1110	paLSPages[iPage].fIgnore = 1;
1111	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1112	paLSPages[iPage].u32Crc = UINT32_MAX;
1113	#endif
1114	pVM->pgm.s.LiveSave.cIgnoredPages++;
1115	break;
1116	}
1117
1118	default:
1119	AssertMsgFailed(("%R[pgmpage]", pPage));
1120	case PGMPAGETYPE_MMIO2:
1121	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1122	paLSPages[iPage].fZero = 0;
1123	paLSPages[iPage].fShared = 0;
1124	paLSPages[iPage].fDirty = 0;
1125	paLSPages[iPage].fIgnore = 1;
1126	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1127	paLSPages[iPage].u32Crc = UINT32_MAX;
1128	#endif
1129	pVM->pgm.s.LiveSave.cIgnoredPages++;
1130	break;
1131
1132	case PGMPAGETYPE_MMIO:
1133	paLSPages[iPage].fZero = 0;
1134	paLSPages[iPage].fShared = 0;
1135	paLSPages[iPage].fDirty = 0;
1136	paLSPages[iPage].fIgnore = 1;
1137	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1138	paLSPages[iPage].u32Crc = UINT32_MAX;
1139	#endif
1140	pVM->pgm.s.LiveSave.cIgnoredPages++;
1141	break;
1142	}
1143	}
1144	}
1145	}
1146	} while (pCur);
1147	pgmUnlock(pVM);
1148
1149	return VINF_SUCCESS;
1150	}
1151
1152
1153	/**
1154	* Saves the RAM configuration.
1155	*
1156	* @returns VBox status code.
1157	* @param pVM The VM handle.
1158	* @param pSSM The saved state handle.
1159	*/
1160	static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1161	{
1162	uint32_t cbRamHole = 0;
1163	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1164	AssertRCReturn(rc, rc);
1165
1166	uint64_t cbRam = 0;
1167	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1168	AssertRCReturn(rc, rc);
1169
1170	SSMR3PutU32(pSSM, cbRamHole);
1171	return SSMR3PutU64(pSSM, cbRam);
1172	}
1173
1174
1175	/**
1176	* Loads and verifies the RAM configuration.
1177	*
1178	* @returns VBox status code.
1179	* @param pVM The VM handle.
1180	* @param pSSM The saved state handle.
1181	*/
1182	static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1183	{
1184	uint32_t cbRamHoleCfg = 0;
1185	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1186	AssertRCReturn(rc, rc);
1187
1188	uint64_t cbRamCfg = 0;
1189	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1190	AssertRCReturn(rc, rc);
1191
1192	uint32_t cbRamHoleSaved;
1193	SSMR3GetU32(pSSM, &cbRamHoleSaved);
1194
1195	uint64_t cbRamSaved;
1196	rc = SSMR3GetU64(pSSM, &cbRamSaved);
1197	AssertRCReturn(rc, rc);
1198
1199	if ( cbRamHoleCfg != cbRamHoleSaved
1200	\|\| cbRamCfg != cbRamSaved)
1201	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1202	cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1203	return VINF_SUCCESS;
1204	}
1205
1206	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1207
1208	/**
1209	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1210	* info with it.
1211	*
1212	* @param pVM The VM handle.
1213	* @param pCur The current RAM range.
1214	* @param paLSPages The current array of live save page tracking
1215	* structures.
1216	* @param iPage The page index.
1217	*/
1218	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1219	{
1220	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1221	void const *pvPage;
1222	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1223	if (RT_SUCCESS(rc))
1224	paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1225	else
1226	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1227	}
1228
1229
1230	/**
1231	* Verifies the CRC-32 for a page given it's raw bits.
1232	*
1233	* @param pvPage The page bits.
1234	* @param pCur The current RAM range.
1235	* @param paLSPages The current array of live save page tracking
1236	* structures.
1237	* @param iPage The page index.
1238	*/
1239	static void pgmR3StateVerifyCrc32ForPage(void const pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char pszWhere)
1240	{
1241	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1242	{
1243	uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1244	Assert( ( !PGM_PAGE_IS_ZERO(&pCur->aPages[iPage])
1245	&& !PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage]))
1246	\|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1247	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1248	("%08x != %08x for %RGp %R[pgmpage] %s\n", paLSPages[iPage].u32Crc, u32Crc,
1249	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage], pszWhere));
1250	}
1251	}
1252
1253
1254	/**
1255	* Verfies the CRC-32 for a RAM page.
1256	*
1257	* @param pVM The VM handle.
1258	* @param pCur The current RAM range.
1259	* @param paLSPages The current array of live save page tracking
1260	* structures.
1261	* @param iPage The page index.
1262	*/
1263	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char *pszWhere)
1264	{
1265	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1266	{
1267	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1268	void const *pvPage;
1269	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1270	if (RT_SUCCESS(rc))
1271	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage, pszWhere);
1272	}
1273	}
1274
1275	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1276
1277	/**
1278	* Scan for RAM page modifications and reprotect them.
1279	*
1280	* @param pVM The VM handle.
1281	* @param fFinalPass Whether this is the final pass or not.
1282	*/
1283	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1284	{
1285	/*
1286	* The RAM.
1287	*/
1288	RTGCPHYS GCPhysCur = 0;
1289	PPGMRAMRANGE pCur;
1290	pgmLock(pVM);
1291	do
1292	{
1293	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1294	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1295	{
1296	if ( pCur->GCPhysLast > GCPhysCur
1297	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1298	{
1299	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1300	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1301	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1302	GCPhysCur = 0;
1303	for (; iPage < cPages; iPage++)
1304	{
1305	/* Do yield first. */
1306	if ( !fFinalPass
1307	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1308	&& (iPage & 0x7ff) == 0x100
1309	#endif
1310	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1311	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1312	{
1313	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1314	break; /* restart */
1315	}
1316
1317	/* Skip already ignored pages. */
1318	if (paLSPages[iPage].fIgnore)
1319	continue;
1320
1321	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1322	{
1323	/*
1324	* A RAM page.
1325	*/
1326	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1327	{
1328	case PGM_PAGE_STATE_ALLOCATED:
1329	/** @todo Optimize this: Don't always re-enable write
1330	* monitoring if the page is known to be very busy. */
1331	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1332	{
1333	Assert(paLSPages[iPage].fWriteMonitored);
1334	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1335	Assert(pVM->pgm.s.cWrittenToPages > 0);
1336	pVM->pgm.s.cWrittenToPages--;
1337	}
1338	else
1339	{
1340	Assert(!paLSPages[iPage].fWriteMonitored);
1341	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1342	}
1343
1344	if (!paLSPages[iPage].fDirty)
1345	{
1346	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1347	if (paLSPages[iPage].fZero)
1348	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1349	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1350	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1351	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1352	}
1353
1354	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_WRITE_MONITORED);
1355	pVM->pgm.s.cMonitoredPages++;
1356	paLSPages[iPage].fWriteMonitored = 1;
1357	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1358	paLSPages[iPage].fDirty = 1;
1359	paLSPages[iPage].fZero = 0;
1360	paLSPages[iPage].fShared = 0;
1361	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1362	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1363	#endif
1364	break;
1365
1366	case PGM_PAGE_STATE_WRITE_MONITORED:
1367	Assert(paLSPages[iPage].fWriteMonitored);
1368	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1369	{
1370	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1371	if (paLSPages[iPage].fWriteMonitoredJustNow)
1372	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1373	else
1374	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "scan");
1375	#endif
1376	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1377	}
1378	else
1379	{
1380	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1381	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1382	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1383	#endif
1384	if (!paLSPages[iPage].fDirty)
1385	{
1386	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1387	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1388	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1389	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1390	}
1391	}
1392	break;
1393
1394	case PGM_PAGE_STATE_ZERO:
1395	if (!paLSPages[iPage].fZero)
1396	{
1397	if (!paLSPages[iPage].fDirty)
1398	{
1399	paLSPages[iPage].fDirty = 1;
1400	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1401	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1402	}
1403	paLSPages[iPage].fZero = 1;
1404	paLSPages[iPage].fShared = 0;
1405	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1406	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1407	#endif
1408	}
1409	break;
1410
1411	case PGM_PAGE_STATE_BALLOONED:
1412	if (!paLSPages[iPage].fZero)
1413	{
1414	if (!paLSPages[iPage].fDirty)
1415	{
1416	paLSPages[iPage].fDirty = 1;
1417	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1418	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1419	}
1420	paLSPages[iPage].fZero = 1;
1421	paLSPages[iPage].fShared = 0;
1422	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1423	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1424	#endif
1425	}
1426	break;
1427
1428	case PGM_PAGE_STATE_SHARED:
1429	if (!paLSPages[iPage].fShared)
1430	{
1431	if (!paLSPages[iPage].fDirty)
1432	{
1433	paLSPages[iPage].fDirty = 1;
1434	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1435	if (paLSPages[iPage].fZero)
1436	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1437	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1438	}
1439	paLSPages[iPage].fZero = 0;
1440	paLSPages[iPage].fShared = 1;
1441	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1442	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1443	#endif
1444	}
1445	break;
1446	}
1447	}
1448	else
1449	{
1450	/*
1451	* All other types => Ignore the page.
1452	*/
1453	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1454	paLSPages[iPage].fIgnore = 1;
1455	if (paLSPages[iPage].fWriteMonitored)
1456	{
1457	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1458	* pages! */
1459	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1460	{
1461	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1462	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1463	Assert(pVM->pgm.s.cMonitoredPages > 0);
1464	pVM->pgm.s.cMonitoredPages--;
1465	}
1466	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1467	{
1468	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1469	Assert(pVM->pgm.s.cWrittenToPages > 0);
1470	pVM->pgm.s.cWrittenToPages--;
1471	}
1472	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1473	}
1474
1475	/** @todo the counting doesn't quite work out here. fix later? */
1476	if (paLSPages[iPage].fDirty)
1477	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1478	else
1479	{
1480	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1481	if (paLSPages[iPage].fZero)
1482	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1483	}
1484	pVM->pgm.s.LiveSave.cIgnoredPages++;
1485	}
1486	} /* for each page in range */
1487
1488	if (GCPhysCur != 0)
1489	break; /* Yield + ramrange change */
1490	GCPhysCur = pCur->GCPhysLast;
1491	}
1492	} /* for each range */
1493	} while (pCur);
1494	pgmUnlock(pVM);
1495	}
1496
1497
1498	/**
1499	* Save quiescent RAM pages.
1500	*
1501	* @returns VBox status code.
1502	* @param pVM The VM handle.
1503	* @param pSSM The SSM handle.
1504	* @param fLiveSave Whether it's a live save or not.
1505	* @param uPass The pass number.
1506	*/
1507	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1508	{
1509	/*
1510	* The RAM.
1511	*/
1512	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1513	RTGCPHYS GCPhysCur = 0;
1514	PPGMRAMRANGE pCur;
1515	pgmLock(pVM);
1516	do
1517	{
1518	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1519	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1520	{
1521	if ( pCur->GCPhysLast > GCPhysCur
1522	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1523	{
1524	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1525	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1526	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1527	GCPhysCur = 0;
1528	for (; iPage < cPages; iPage++)
1529	{
1530	/* Do yield first. */
1531	if ( uPass != SSM_PASS_FINAL
1532	&& (iPage & 0x7ff) == 0x100
1533	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1534	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1535	{
1536	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1537	break; /* restart */
1538	}
1539
1540	/*
1541	* Only save pages that haven't changed since last scan and are dirty.
1542	*/
1543	if ( uPass != SSM_PASS_FINAL
1544	&& paLSPages)
1545	{
1546	if (!paLSPages[iPage].fDirty)
1547	continue;
1548	if (paLSPages[iPage].fWriteMonitoredJustNow)
1549	continue;
1550	if (paLSPages[iPage].fIgnore)
1551	continue;
1552	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM) /* in case of recent remappings */
1553	continue;
1554	if ( PGM_PAGE_GET_STATE(&pCur->aPages[iPage])
1555	!= ( paLSPages[iPage].fZero
1556	? PGM_PAGE_STATE_ZERO
1557	: paLSPages[iPage].fShared
1558	? PGM_PAGE_STATE_SHARED
1559	: PGM_PAGE_STATE_WRITE_MONITORED))
1560	continue;
1561	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1562	continue;
1563	}
1564	else
1565	{
1566	if ( paLSPages
1567	&& !paLSPages[iPage].fDirty
1568	&& !paLSPages[iPage].fIgnore)
1569	{
1570	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1571	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1572	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#1");
1573	#endif
1574	continue;
1575	}
1576	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1577	continue;
1578	}
1579
1580	/*
1581	* Do the saving outside the PGM critsect since SSM may block on I/O.
1582	*/
1583	int rc;
1584	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1585	bool fZero = PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]) \|\| PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage]);
1586
1587	if (!fZero)
1588	{
1589	/*
1590	* Copy the page and then save it outside the lock (since any
1591	* SSM call may block).
1592	*/
1593	uint8_t abPage[PAGE_SIZE];
1594	void const *pvPage;
1595	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1596	if (RT_SUCCESS(rc))
1597	{
1598	memcpy(abPage, pvPage, PAGE_SIZE);
1599	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1600	if (paLSPages)
1601	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage, "save#3");
1602	#endif
1603	}
1604	pgmUnlock(pVM);
1605	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1606
1607	/* Try save some memory when restoring. */
1608	if (!ASMMemIsZeroPage(pvPage))
1609	{
1610	if (GCPhys == GCPhysLast + PAGE_SIZE)
1611	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1612	else
1613	{
1614	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1615	SSMR3PutGCPhys(pSSM, GCPhys);
1616	}
1617	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1618	}
1619	else
1620	{
1621	if (GCPhys == GCPhysLast + PAGE_SIZE)
1622	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1623	else
1624	{
1625	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1626	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1627	}
1628	}
1629	}
1630	else
1631	{
1632	/*
1633	* Dirty zero page.
1634	*/
1635	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1636	if (paLSPages)
1637	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#2");
1638	#endif
1639	pgmUnlock(pVM);
1640
1641	if (GCPhys == GCPhysLast + PAGE_SIZE)
1642	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1643	else
1644	{
1645	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1646	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1647	}
1648	}
1649	if (RT_FAILURE(rc))
1650	return rc;
1651
1652	pgmLock(pVM);
1653	GCPhysLast = GCPhys;
1654	if (paLSPages)
1655	{
1656	paLSPages[iPage].fDirty = 0;
1657	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1658	if (fZero)
1659	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1660	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1661	pVM->pgm.s.LiveSave.cSavedPages++;
1662	}
1663	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1664	{
1665	GCPhysCur = GCPhys \| PAGE_OFFSET_MASK;
1666	break; /* restart */
1667	}
1668
1669	} /* for each page in range */
1670
1671	if (GCPhysCur != 0)
1672	break; /* Yield + ramrange change */
1673	GCPhysCur = pCur->GCPhysLast;
1674	}
1675	} /* for each range */
1676	} while (pCur);
1677	pgmUnlock(pVM);
1678
1679	return VINF_SUCCESS;
1680	}
1681
1682
1683	/**
1684	* Cleans up RAM pages after a live save.
1685	*
1686	* @param pVM The VM handle.
1687	*/
1688	static void pgmR3DoneRamPages(PVM pVM)
1689	{
1690	/*
1691	* Free the tracking arrays and disable write monitoring.
1692	*
1693	* Play nice with the PGM lock in case we're called while the VM is still
1694	* running. This means we have to delay the freeing since we wish to use
1695	* paLSPages as an indicator of which RAM ranges which we need to scan for
1696	* write monitored pages.
1697	*/
1698	void *pvToFree = NULL;
1699	PPGMRAMRANGE pCur;
1700	uint32_t cMonitoredPages = 0;
1701	pgmLock(pVM);
1702	do
1703	{
1704	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1705	{
1706	if (pCur->paLSPages)
1707	{
1708	if (pvToFree)
1709	{
1710	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1711	pgmUnlock(pVM);
1712	MMR3HeapFree(pvToFree);
1713	pvToFree = NULL;
1714	pgmLock(pVM);
1715	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1716	break; /* start over again. */
1717	}
1718
1719	pvToFree = pCur->paLSPages;
1720	pCur->paLSPages = NULL;
1721
1722	uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1723	while (iPage--)
1724	{
1725	PPGMPAGE pPage = &pCur->aPages[iPage];
1726	PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1727	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1728	{
1729	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1730	cMonitoredPages++;
1731	}
1732	}
1733	}
1734	}
1735	} while (pCur);
1736
1737	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1738	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1739	pVM->pgm.s.cMonitoredPages = 0;
1740	else
1741	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1742
1743	pgmUnlock(pVM);
1744
1745	MMR3HeapFree(pvToFree);
1746	pvToFree = NULL;
1747	}
1748
1749
1750	/**
1751	* Execute a live save pass.
1752	*
1753	* @returns VBox status code.
1754	*
1755	* @param pVM The VM handle.
1756	* @param pSSM The SSM handle.
1757	*/
1758	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1759	{
1760	int rc;
1761
1762	/*
1763	* Save the MMIO2 and ROM range IDs in pass 0.
1764	*/
1765	if (uPass == 0)
1766	{
1767	rc = pgmR3SaveRamConfig(pVM, pSSM);
1768	if (RT_FAILURE(rc))
1769	return rc;
1770	rc = pgmR3SaveRomRanges(pVM, pSSM);
1771	if (RT_FAILURE(rc))
1772	return rc;
1773	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1774	if (RT_FAILURE(rc))
1775	return rc;
1776	}
1777	/*
1778	* Reset the page-per-second estimate to avoid inflation by the initial
1779	* load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1780	*/
1781	else if (uPass == 7)
1782	{
1783	pVM->pgm.s.LiveSave.cSavedPages = 0;
1784	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1785	}
1786
1787	/*
1788	* Do the scanning.
1789	*/
1790	pgmR3ScanRomPages(pVM);
1791	pgmR3ScanMmio2Pages(pVM, uPass);
1792	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1793	pgmR3PoolClearAll(pVM, true /fFlushRemTlb/); /** @todo this could perhaps be optimized a bit. */
1794
1795	/*
1796	* Save the pages.
1797	*/
1798	if (uPass == 0)
1799	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1800	else
1801	rc = VINF_SUCCESS;
1802	if (RT_SUCCESS(rc))
1803	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1804	if (RT_SUCCESS(rc))
1805	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1806	if (RT_SUCCESS(rc))
1807	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1808	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes care of it.) */
1809
1810	return rc;
1811	}
1812
1813
1814	/**
1815	* Votes on whether the live save phase is done or not.
1816	*
1817	* @returns VBox status code.
1818	*
1819	* @param pVM The VM handle.
1820	* @param pSSM The SSM handle.
1821	* @param uPass The data pass.
1822	*/
1823	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1824	{
1825	/*
1826	* Update and calculate parameters used in the decision making.
1827	*/
1828	const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1829
1830	/* update history. */
1831	pgmLock(pVM);
1832	uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1833	pgmUnlock(pVM);
1834	uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1835	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1836	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages
1837	+ cWrittenToPages;
1838	uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1839	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1840	pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1841
1842	/* calc shortterm average (4 passes). */
1843	AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1844	uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1845	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1846	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1847	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1848	uint32_t const cDirtyPagesShort = cTotal / 4;
1849	pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1850
1851	/* calc longterm average. */
1852	cTotal = 0;
1853	if (uPass < cHistoryEntries)
1854	for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1855	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1856	else
1857	for (i = 0; i < cHistoryEntries; i++)
1858	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1859	uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1860	pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1861
1862	/* estimate the speed */
1863	uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1864	uint32_t cPagesPerSecond = (uint32_t)( pVM->pgm.s.LiveSave.cSavedPages
1865	/ ((long double)cNsElapsed / 1000000000.0) );
1866	pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1867
1868	/*
1869	* Try make a decision.
1870	*/
1871	if ( cDirtyPagesShort <= cDirtyPagesLong
1872	&& ( cDirtyNow <= cDirtyPagesShort
1873	\|\| cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1874	)
1875	)
1876	{
1877	if (uPass > 10)
1878	{
1879	uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1880	uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1881	uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1882	if (cMsMaxDowntime < 32)
1883	cMsMaxDowntime = 32;
1884	if ( ( cMsLeftLong <= cMsMaxDowntime
1885	&& cMsLeftShort < cMsMaxDowntime)
1886	\|\| cMsLeftShort < cMsMaxDowntime / 2
1887	)
1888	{
1889	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u\|%ums cDirtyPagesLong=%u\|%ums cMsMaxDowntime=%u\n",
1890	uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1891	return VINF_SUCCESS;
1892	}
1893	}
1894	else
1895	{
1896	if ( ( cDirtyPagesShort <= 128
1897	&& cDirtyPagesLong <= 1024)
1898	\|\| cDirtyPagesLong <= 256
1899	)
1900	{
1901	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1902	return VINF_SUCCESS;
1903	}
1904	}
1905	}
1906
1907	/*
1908	* Come up with a completion percentage. Currently this is a simple
1909	* dirty page (long term) vs. total pages ratio + some pass trickery.
1910	*/
1911	unsigned uPctDirty = (unsigned)( (long double)cDirtyPagesLong
1912	/ (pVM->pgm.s.cAllPages - pVM->pgm.s.LiveSave.cIgnoredPages - pVM->pgm.s.cZeroPages) );
1913	if (uPctDirty <= 100)
1914	SSMR3HandleReportLivePercent(pSSM, RT_MIN(100 - uPctDirty, uPass * 2));
1915	else
1916	AssertMsgFailed(("uPctDirty=%u cDirtyPagesLong=%#x cAllPages=%#x cIgnoredPages=%#x cZeroPages=%#x\n",
1917	uPctDirty, cDirtyPagesLong, pVM->pgm.s.cAllPages, pVM->pgm.s.LiveSave.cIgnoredPages, pVM->pgm.s.cZeroPages));
1918
1919	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1920	}
1921
1922
1923	/**
1924	* Prepare for a live save operation.
1925	*
1926	* This will attempt to allocate and initialize the tracking structures. It
1927	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1928	* pgmR3SaveDone will do the cleanups.
1929	*
1930	* @returns VBox status code.
1931	*
1932	* @param pVM The VM handle.
1933	* @param pSSM The SSM handle.
1934	*/
1935	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1936	{
1937	/*
1938	* Indicate that we will be using the write monitoring.
1939	*/
1940	pgmLock(pVM);
1941	/** @todo find a way of mediating this when more users are added. */
1942	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1943	{
1944	pgmUnlock(pVM);
1945	AssertLogRelFailedReturn(VERR_INTERNAL_ERROR_2);
1946	}
1947	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
1948	pgmUnlock(pVM);
1949
1950	/*
1951	* Initialize the statistics.
1952	*/
1953	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
1954	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
1955	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
1956	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
1957	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
1958	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
1959	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
1960	pVM->pgm.s.LiveSave.fActive = true;
1961	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
1962	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
1963	pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
1964	pVM->pgm.s.LiveSave.cSavedPages = 0;
1965	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1966	pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
1967
1968	/*
1969	* Per page type.
1970	*/
1971	int rc = pgmR3PrepRomPages(pVM);
1972	if (RT_SUCCESS(rc))
1973	rc = pgmR3PrepMmio2Pages(pVM);
1974	if (RT_SUCCESS(rc))
1975	rc = pgmR3PrepRamPages(pVM);
1976	return rc;
1977	}
1978
1979
1980	/**
1981	* Execute state save operation.
1982	*
1983	* @returns VBox status code.
1984	* @param pVM VM Handle.
1985	* @param pSSM SSM operation handle.
1986	*/
1987	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1988	{
1989	int rc;
1990	unsigned i;
1991	PPGM pPGM = &pVM->pgm.s;
1992
1993	/*
1994	* Lock PGM and set the no-more-writes indicator.
1995	*/
1996	pgmLock(pVM);
1997	pVM->pgm.s.fNoMorePhysWrites = true;
1998
1999	/*
2000	* Save basic data (required / unaffected by relocation).
2001	*/
2002	bool const fMappingsFixed = pVM->pgm.s.fMappingsFixed;
2003	pVM->pgm.s.fMappingsFixed \|= pVM->pgm.s.fMappingsFixedRestored;
2004	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2005	pVM->pgm.s.fMappingsFixed = fMappingsFixed;
2006
2007	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2008	SSMR3PutStruct(pSSM, &pVM->aCpus[idCpu].pgm.s, &s_aPGMCpuFields[0]);
2009
2010	/*
2011	* The guest mappings.
2012	*/
2013	i = 0;
2014	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2015	{
2016	SSMR3PutU32( pSSM, i);
2017	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2018	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
2019	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2020	}
2021	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
2022
2023	/*
2024	* Save the (remainder of the) memory.
2025	*/
2026	if (RT_SUCCESS(rc))
2027	{
2028	if (pVM->pgm.s.LiveSave.fActive)
2029	{
2030	pgmR3ScanRomPages(pVM);
2031	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
2032	pgmR3ScanRamPages(pVM, true /fFinalPass/);
2033
2034	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
2035	if (RT_SUCCESS(rc))
2036	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2037	if (RT_SUCCESS(rc))
2038	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
2039	}
2040	else
2041	{
2042	rc = pgmR3SaveRamConfig(pVM, pSSM);
2043	if (RT_SUCCESS(rc))
2044	rc = pgmR3SaveRomRanges(pVM, pSSM);
2045	if (RT_SUCCESS(rc))
2046	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
2047	if (RT_SUCCESS(rc))
2048	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
2049	if (RT_SUCCESS(rc))
2050	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
2051	if (RT_SUCCESS(rc))
2052	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2053	if (RT_SUCCESS(rc))
2054	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
2055	}
2056	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
2057	}
2058
2059	pgmUnlock(pVM);
2060	return rc;
2061	}
2062
2063
2064	/**
2065	* Cleans up after an save state operation.
2066	*
2067	* @returns VBox status code.
2068	* @param pVM VM Handle.
2069	* @param pSSM SSM operation handle.
2070	*/
2071	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2072	{
2073	/*
2074	* Do per page type cleanups first.
2075	*/
2076	if (pVM->pgm.s.LiveSave.fActive)
2077	{
2078	pgmR3DoneRomPages(pVM);
2079	pgmR3DoneMmio2Pages(pVM);
2080	pgmR3DoneRamPages(pVM);
2081	}
2082
2083	/*
2084	* Clear the live save indicator and disengage write monitoring.
2085	*/
2086	pgmLock(pVM);
2087	pVM->pgm.s.LiveSave.fActive = false;
2088	/** @todo this is blindly assuming that we're the only user of write
2089	* monitoring. Fix this when more users are added. */
2090	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2091	pgmUnlock(pVM);
2092
2093	return VINF_SUCCESS;
2094	}
2095
2096
2097	/**
2098	* Prepare state load operation.
2099	*
2100	* @returns VBox status code.
2101	* @param pVM VM Handle.
2102	* @param pSSM SSM operation handle.
2103	*/
2104	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2105	{
2106	/*
2107	* Call the reset function to make sure all the memory is cleared.
2108	*/
2109	PGMR3Reset(pVM);
2110	pVM->pgm.s.LiveSave.fActive = false;
2111	NOREF(pSSM);
2112	return VINF_SUCCESS;
2113	}
2114
2115
2116	/**
2117	* Load an ignored page.
2118	*
2119	* @returns VBox status code.
2120	* @param pSSM The saved state handle.
2121	*/
2122	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2123	{
2124	uint8_t abPage[PAGE_SIZE];
2125	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2126	}
2127
2128
2129	/**
2130	* Loads a page without any bits in the saved state, i.e. making sure it's
2131	* really zero.
2132	*
2133	* @returns VBox status code.
2134	* @param pVM The VM handle.
2135	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2136	* state).
2137	* @param pPage The guest page tracking structure.
2138	* @param GCPhys The page address.
2139	* @param pRam The ram range (logging).
2140	*/
2141	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2142	{
2143	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2144	&& uType != PGMPAGETYPE_INVALID)
2145	return VERR_SSM_UNEXPECTED_DATA;
2146
2147	/* I think this should be sufficient. */
2148	if ( !PGM_PAGE_IS_ZERO(pPage)
2149	&& !PGM_PAGE_IS_BALLOONED(pPage))
2150	return VERR_SSM_UNEXPECTED_DATA;
2151
2152	NOREF(pVM);
2153	NOREF(GCPhys);
2154	NOREF(pRam);
2155	return VINF_SUCCESS;
2156	}
2157
2158
2159	/**
2160	* Loads a page from the saved state.
2161	*
2162	* @returns VBox status code.
2163	* @param pVM The VM handle.
2164	* @param pSSM The SSM handle.
2165	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2166	* state).
2167	* @param pPage The guest page tracking structure.
2168	* @param GCPhys The page address.
2169	* @param pRam The ram range (logging).
2170	*/
2171	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2172	{
2173	/*
2174	* Match up the type, dealing with MMIO2 aliases (dropped).
2175	*/
2176	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2177	\|\| uType == PGMPAGETYPE_INVALID,
2178	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2179	VERR_SSM_UNEXPECTED_DATA);
2180
2181	/*
2182	* Load the page.
2183	*/
2184	void *pvPage;
2185	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2186	if (RT_SUCCESS(rc))
2187	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2188
2189	return rc;
2190	}
2191
2192
2193	/**
2194	* Loads a page (counter part to pgmR3SavePage).
2195	*
2196	* @returns VBox status code, fully bitched errors.
2197	* @param pVM The VM handle.
2198	* @param pSSM The SSM handle.
2199	* @param uType The page type.
2200	* @param pPage The page.
2201	* @param GCPhys The page address.
2202	* @param pRam The RAM range (for error messages).
2203	*/
2204	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2205	{
2206	uint8_t uState;
2207	int rc = SSMR3GetU8(pSSM, &uState);
2208	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2209	if (uState == 0 /* zero */)
2210	rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2211	else if (uState == 1)
2212	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2213	else
2214	rc = VERR_INTERNAL_ERROR;
2215	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2216	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2217	rc);
2218	return VINF_SUCCESS;
2219	}
2220
2221
2222	/**
2223	* Loads a shadowed ROM page.
2224	*
2225	* @returns VBox status code, errors are fully bitched.
2226	* @param pVM The VM handle.
2227	* @param pSSM The saved state handle.
2228	* @param pPage The page.
2229	* @param GCPhys The page address.
2230	* @param pRam The RAM range (for error messages).
2231	*/
2232	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2233	{
2234	/*
2235	* Load and set the protection first, then load the two pages, the first
2236	* one is the active the other is the passive.
2237	*/
2238	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2239	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2240
2241	uint8_t uProt;
2242	int rc = SSMR3GetU8(pSSM, &uProt);
2243	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2244	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2245	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2246	&& enmProt < PGMROMPROT_END,
2247	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2248	VERR_SSM_UNEXPECTED_DATA);
2249
2250	if (pRomPage->enmProt != enmProt)
2251	{
2252	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2253	AssertLogRelRCReturn(rc, rc);
2254	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2255	}
2256
2257	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2258	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2259	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2260	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2261
2262	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2263	* used down the line (will the 2nd page will be written to the first
2264	* one because of a false TLB hit since the TLB is using GCPhys and
2265	* doesn't check the HCPhys of the desired page). */
2266	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2267	if (RT_SUCCESS(rc))
2268	{
2269	pPageActive = pPage;
2270	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2271	}
2272	return rc;
2273	}
2274
2275	/**
2276	* Ram range flags and bits for older versions of the saved state.
2277	*
2278	* @returns VBox status code.
2279	*
2280	* @param pVM The VM handle
2281	* @param pSSM The SSM handle.
2282	* @param uVersion The saved state version.
2283	*/
2284	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2285	{
2286	PPGM pPGM = &pVM->pgm.s;
2287
2288	/*
2289	* Ram range flags and bits.
2290	*/
2291	uint32_t i = 0;
2292	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2293	{
2294	/* Check the seqence number / separator. */
2295	uint32_t u32Sep;
2296	int rc = SSMR3GetU32(pSSM, &u32Sep);
2297	if (RT_FAILURE(rc))
2298	return rc;
2299	if (u32Sep == ~0U)
2300	break;
2301	if (u32Sep != i)
2302	{
2303	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2304	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2305	}
2306	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2307
2308	/* Get the range details. */
2309	RTGCPHYS GCPhys;
2310	SSMR3GetGCPhys(pSSM, &GCPhys);
2311	RTGCPHYS GCPhysLast;
2312	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2313	RTGCPHYS cb;
2314	SSMR3GetGCPhys(pSSM, &cb);
2315	uint8_t fHaveBits;
2316	rc = SSMR3GetU8(pSSM, &fHaveBits);
2317	if (RT_FAILURE(rc))
2318	return rc;
2319	if (fHaveBits & ~1)
2320	{
2321	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2322	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2323	}
2324	size_t cchDesc = 0;
2325	char szDesc[256];
2326	szDesc[0] = '\0';
2327	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2328	{
2329	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2330	if (RT_FAILURE(rc))
2331	return rc;
2332	/* Since we've modified the description strings in r45878, only compare
2333	them if the saved state is more recent. */
2334	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2335	cchDesc = strlen(szDesc);
2336	}
2337
2338	/*
2339	* Match it up with the current range.
2340	*
2341	* Note there is a hack for dealing with the high BIOS mapping
2342	* in the old saved state format, this means we might not have
2343	* a 1:1 match on success.
2344	*/
2345	if ( ( GCPhys != pRam->GCPhys
2346	\|\| GCPhysLast != pRam->GCPhysLast
2347	\|\| cb != pRam->cb
2348	\|\| ( cchDesc
2349	&& strcmp(szDesc, pRam->pszDesc)) )
2350	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2351	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2352	\|\| GCPhys != UINT32_C(0xfff80000)
2353	\|\| GCPhysLast != UINT32_C(0xffffffff)
2354	\|\| pRam->GCPhysLast != GCPhysLast
2355	\|\| pRam->GCPhys < GCPhys
2356	\|\| !fHaveBits)
2357	)
2358	{
2359	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2360	"State : %RGp-%RGp %RGp bytes %s %s\n",
2361	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2362	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2363	/*
2364	* If we're loading a state for debugging purpose, don't make a fuss if
2365	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2366	*/
2367	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2368	\|\| GCPhys < 8 * _1M)
2369	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2370	N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2371	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2372	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2373
2374	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2375	continue;
2376	}
2377
2378	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2379	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2380	{
2381	/*
2382	* Load the pages one by one.
2383	*/
2384	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2385	{
2386	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2387	PPGMPAGE pPage = &pRam->aPages[iPage];
2388	uint8_t uType;
2389	rc = SSMR3GetU8(pSSM, &uType);
2390	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2391	if (uType == PGMPAGETYPE_ROM_SHADOW)
2392	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2393	else
2394	rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2395	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2396	}
2397	}
2398	else
2399	{
2400	/*
2401	* Old format.
2402	*/
2403
2404	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2405	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2406	uint32_t fFlags = 0;
2407	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2408	{
2409	uint16_t u16Flags;
2410	rc = SSMR3GetU16(pSSM, &u16Flags);
2411	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2412	fFlags \|= u16Flags;
2413	}
2414
2415	/* Load the bits */
2416	if ( !fHaveBits
2417	&& GCPhysLast < UINT32_C(0xe0000000))
2418	{
2419	/*
2420	* Dynamic chunks.
2421	*/
2422	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2423	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2424	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2425	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2426
2427	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2428	{
2429	uint8_t fPresent;
2430	rc = SSMR3GetU8(pSSM, &fPresent);
2431	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2432	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2433	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2434	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2435
2436	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2437	{
2438	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2439	PPGMPAGE pPage = &pRam->aPages[iPage];
2440	if (fPresent)
2441	{
2442	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2443	rc = pgmR3LoadPageToDevNullOld(pSSM);
2444	else
2445	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2446	}
2447	else
2448	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2449	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2450	}
2451	}
2452	}
2453	else if (pRam->pvR3)
2454	{
2455	/*
2456	* MMIO2.
2457	*/
2458	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2459	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2460	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2461	AssertLogRelMsgReturn(pRam->pvR3,
2462	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2463	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2464
2465	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2466	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2467	}
2468	else if (GCPhysLast < UINT32_C(0xfff80000))
2469	{
2470	/*
2471	* PCI MMIO, no pages saved.
2472	*/
2473	}
2474	else
2475	{
2476	/*
2477	* Load the 0xfff80000..0xffffffff BIOS range.
2478	* It starts with X reserved pages that we have to skip over since
2479	* the RAMRANGE create by the new code won't include those.
2480	*/
2481	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2482	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2483	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2484	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2485	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2486	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2487	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2488
2489	/* Skip wasted reserved pages before the ROM. */
2490	while (GCPhys < pRam->GCPhys)
2491	{
2492	rc = pgmR3LoadPageToDevNullOld(pSSM);
2493	GCPhys += PAGE_SIZE;
2494	}
2495
2496	/* Load the bios pages. */
2497	cPages = pRam->cb >> PAGE_SHIFT;
2498	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2499	{
2500	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2501	PPGMPAGE pPage = &pRam->aPages[iPage];
2502
2503	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2504	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2505	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2506	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2507	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2508	}
2509	}
2510	}
2511	}
2512
2513	return VINF_SUCCESS;
2514	}
2515
2516
2517	/**
2518	* Worker for pgmR3Load and pgmR3LoadLocked.
2519	*
2520	* @returns VBox status code.
2521	*
2522	* @param pVM The VM handle.
2523	* @param pSSM The SSM handle.
2524	* @param uVersion The saved state version.
2525	*
2526	* @todo This needs splitting up if more record types or code twists are
2527	* added...
2528	*/
2529	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2530	{
2531	/*
2532	* Process page records until we hit the terminator.
2533	*/
2534	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2535	PPGMRAMRANGE pRamHint = NULL;
2536	uint8_t id = UINT8_MAX;
2537	uint32_t iPage = UINT32_MAX - 10;
2538	PPGMROMRANGE pRom = NULL;
2539	PPGMMMIO2RANGE pMmio2 = NULL;
2540
2541	/*
2542	* We batch up pages that should be freed instead of calling GMM for
2543	* each and every one of them.
2544	*/
2545	uint32_t cPendingPages = 0;
2546	PGMMFREEPAGESREQ pReq;
2547	int rc = GMMR3FreePagesPrepare(pVM, &pReq, 128 /* batch size */, GMMACCOUNT_BASE);
2548	AssertLogRelRCReturn(rc, rc);
2549
2550	for (;;)
2551	{
2552	/*
2553	* Get the record type and flags.
2554	*/
2555	uint8_t u8;
2556	rc = SSMR3GetU8(pSSM, &u8);
2557	if (RT_FAILURE(rc))
2558	return rc;
2559	if (u8 == PGM_STATE_REC_END)
2560	{
2561	/*
2562	* Finish off any pages pending freeing.
2563	*/
2564	if (cPendingPages)
2565	{
2566	rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2567	AssertLogRelRCReturn(rc, rc);
2568	}
2569	GMMR3FreePagesCleanup(pReq);
2570	return VINF_SUCCESS;
2571	}
2572	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2573	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2574	{
2575	/*
2576	* RAM page.
2577	*/
2578	case PGM_STATE_REC_RAM_ZERO:
2579	case PGM_STATE_REC_RAM_RAW:
2580	{
2581	/*
2582	* Get the address and resolve it into a page descriptor.
2583	*/
2584	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2585	GCPhys += PAGE_SIZE;
2586	else
2587	{
2588	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2589	if (RT_FAILURE(rc))
2590	return rc;
2591	}
2592	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2593
2594	PPGMPAGE pPage;
2595	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
2596	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2597
2598	/*
2599	* Take action according to the record type.
2600	*/
2601	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2602	{
2603	case PGM_STATE_REC_RAM_ZERO:
2604	{
2605	if ( PGM_PAGE_IS_ZERO(pPage)
2606	\|\| PGM_PAGE_IS_BALLOONED(pPage))
2607	break;
2608	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2609	/* Allocated before (prealloc), so free it now. */
2610	rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, GCPhys);
2611	AssertRC(rc);
2612	break;
2613	}
2614
2615	case PGM_STATE_REC_RAM_RAW:
2616	{
2617	void *pvDstPage;
2618	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2619	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2620	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2621	if (RT_FAILURE(rc))
2622	return rc;
2623	break;
2624	}
2625
2626	default:
2627	AssertMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2628	}
2629	id = UINT8_MAX;
2630	break;
2631	}
2632
2633	/*
2634	* MMIO2 page.
2635	*/
2636	case PGM_STATE_REC_MMIO2_RAW:
2637	case PGM_STATE_REC_MMIO2_ZERO:
2638	{
2639	/*
2640	* Get the ID + page number and resolved that into a MMIO2 page.
2641	*/
2642	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2643	iPage++;
2644	else
2645	{
2646	SSMR3GetU8(pSSM, &id);
2647	rc = SSMR3GetU32(pSSM, &iPage);
2648	if (RT_FAILURE(rc))
2649	return rc;
2650	}
2651	if ( !pMmio2
2652	\|\| pMmio2->idSavedState != id)
2653	{
2654	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2655	if (pMmio2->idSavedState == id)
2656	break;
2657	AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2658	}
2659	AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_INTERNAL_ERROR);
2660	void pvDstPage = (uint8_t )pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2661
2662	/*
2663	* Load the page bits.
2664	*/
2665	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2666	ASMMemZeroPage(pvDstPage);
2667	else
2668	{
2669	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2670	if (RT_FAILURE(rc))
2671	return rc;
2672	}
2673	GCPhys = NIL_RTGCPHYS;
2674	break;
2675	}
2676
2677	/*
2678	* ROM pages.
2679	*/
2680	case PGM_STATE_REC_ROM_VIRGIN:
2681	case PGM_STATE_REC_ROM_SHW_RAW:
2682	case PGM_STATE_REC_ROM_SHW_ZERO:
2683	case PGM_STATE_REC_ROM_PROT:
2684	{
2685	/*
2686	* Get the ID + page number and resolved that into a ROM page descriptor.
2687	*/
2688	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2689	iPage++;
2690	else
2691	{
2692	SSMR3GetU8(pSSM, &id);
2693	rc = SSMR3GetU32(pSSM, &iPage);
2694	if (RT_FAILURE(rc))
2695	return rc;
2696	}
2697	if ( !pRom
2698	\|\| pRom->idSavedState != id)
2699	{
2700	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2701	if (pRom->idSavedState == id)
2702	break;
2703	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2704	}
2705	AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_INTERNAL_ERROR);
2706	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2707	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2708
2709	/*
2710	* Get and set the protection.
2711	*/
2712	uint8_t u8Prot;
2713	rc = SSMR3GetU8(pSSM, &u8Prot);
2714	if (RT_FAILURE(rc))
2715	return rc;
2716	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2717	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_INTERNAL_ERROR);
2718
2719	if (enmProt != pRomPage->enmProt)
2720	{
2721	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2722	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2723	N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2724	GCPhys, enmProt, pRom->pszDesc);
2725	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2726	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2727	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2728	}
2729	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2730	break; /* done */
2731
2732	/*
2733	* Get the right page descriptor.
2734	*/
2735	PPGMPAGE pRealPage;
2736	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2737	{
2738	case PGM_STATE_REC_ROM_VIRGIN:
2739	if (!PGMROMPROT_IS_ROM(enmProt))
2740	pRealPage = &pRomPage->Virgin;
2741	else
2742	pRealPage = NULL;
2743	break;
2744
2745	case PGM_STATE_REC_ROM_SHW_RAW:
2746	case PGM_STATE_REC_ROM_SHW_ZERO:
2747	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2748	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2749	N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2750	GCPhys, enmProt, pRom->pszDesc);
2751	if (PGMROMPROT_IS_ROM(enmProt))
2752	pRealPage = &pRomPage->Shadow;
2753	else
2754	pRealPage = NULL;
2755	break;
2756
2757	default: AssertLogRelFailedReturn(VERR_INTERNAL_ERROR); /* shut up gcc */
2758	}
2759	if (!pRealPage)
2760	{
2761	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pRealPage, &pRamHint);
2762	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2763	}
2764
2765	/*
2766	* Make it writable and map it (if necessary).
2767	*/
2768	void *pvDstPage = NULL;
2769	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2770	{
2771	case PGM_STATE_REC_ROM_SHW_ZERO:
2772	if ( PGM_PAGE_IS_ZERO(pRealPage)
2773	\|\| PGM_PAGE_IS_BALLOONED(pRealPage))
2774	break;
2775	/** @todo implement zero page replacing. */
2776	/* fall thru */
2777	case PGM_STATE_REC_ROM_VIRGIN:
2778	case PGM_STATE_REC_ROM_SHW_RAW:
2779	{
2780	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2781	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2782	break;
2783	}
2784	}
2785
2786	/*
2787	* Load the bits.
2788	*/
2789	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2790	{
2791	case PGM_STATE_REC_ROM_SHW_ZERO:
2792	if (pvDstPage)
2793	ASMMemZeroPage(pvDstPage);
2794	break;
2795
2796	case PGM_STATE_REC_ROM_VIRGIN:
2797	case PGM_STATE_REC_ROM_SHW_RAW:
2798	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2799	if (RT_FAILURE(rc))
2800	return rc;
2801	break;
2802	}
2803	GCPhys = NIL_RTGCPHYS;
2804	break;
2805	}
2806
2807	/*
2808	* Unknown type.
2809	*/
2810	default:
2811	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2812	}
2813	} /* forever */
2814	}
2815
2816
2817	/**
2818	* Worker for pgmR3Load.
2819	*
2820	* @returns VBox status code.
2821	*
2822	* @param pVM The VM handle.
2823	* @param pSSM The SSM handle.
2824	* @param uVersion The saved state version.
2825	*/
2826	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2827	{
2828	PPGM pPGM = &pVM->pgm.s;
2829	int rc;
2830	uint32_t u32Sep;
2831
2832	/*
2833	* Load basic data (required / unaffected by relocation).
2834	*/
2835	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2836	{
2837	if (uVersion > PGM_SAVED_STATE_VERSION_PRE_BALLOON)
2838	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2839	else
2840	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFieldsPreBalloon[0]);
2841
2842	AssertLogRelRCReturn(rc, rc);
2843
2844	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2845	{
2846	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2847	AssertLogRelRCReturn(rc, rc);
2848	}
2849	}
2850	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2851	{
2852	AssertRelease(pVM->cCpus == 1);
2853
2854	PGMOLD pgmOld;
2855	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2856	AssertLogRelRCReturn(rc, rc);
2857
2858	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2859	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2860	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2861
2862	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2863	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2864	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2865	}
2866	else
2867	{
2868	AssertRelease(pVM->cCpus == 1);
2869
2870	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2871	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2872	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2873
2874	uint32_t cbRamSizeIgnored;
2875	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2876	if (RT_FAILURE(rc))
2877	return rc;
2878	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2879
2880	uint32_t u32 = 0;
2881	SSMR3GetUInt(pSSM, &u32);
2882	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2883	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2884	RTUINT uGuestMode;
2885	SSMR3GetUInt(pSSM, &uGuestMode);
2886	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2887
2888	/* check separator. */
2889	SSMR3GetU32(pSSM, &u32Sep);
2890	if (RT_FAILURE(rc))
2891	return rc;
2892	if (u32Sep != (uint32_t)~0)
2893	{
2894	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2895	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2896	}
2897	}
2898
2899	/*
2900	* The guest mappings - skipped now, see re-fixation in the caller.
2901	*/
2902	uint32_t i = 0;
2903	for (;; i++)
2904	{
2905	rc = SSMR3GetU32(pSSM, &u32Sep); /* seqence number */
2906	if (RT_FAILURE(rc))
2907	return rc;
2908	if (u32Sep == ~0U)
2909	break;
2910	AssertMsgReturn(u32Sep == i, ("u32Sep=%#x i=%#x\n", u32Sep, i), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2911
2912	char szDesc[256];
2913	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2914	if (RT_FAILURE(rc))
2915	return rc;
2916	RTGCPTR GCPtrIgnore;
2917	SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* GCPtr */
2918	rc = SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* cPTs */
2919	if (RT_FAILURE(rc))
2920	return rc;
2921	}
2922
2923	/*
2924	* Load the RAM contents.
2925	*/
2926	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
2927	{
2928	if (!pVM->pgm.s.LiveSave.fActive)
2929	{
2930	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2931	{
2932	rc = pgmR3LoadRamConfig(pVM, pSSM);
2933	if (RT_FAILURE(rc))
2934	return rc;
2935	}
2936	rc = pgmR3LoadRomRanges(pVM, pSSM);
2937	if (RT_FAILURE(rc))
2938	return rc;
2939	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2940	if (RT_FAILURE(rc))
2941	return rc;
2942	}
2943
2944	rc = pgmR3LoadMemory(pVM, pSSM, SSM_PASS_FINAL);
2945	}
2946	else
2947	rc = pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
2948
2949	/* Refresh balloon accounting. */
2950	if (pVM->pgm.s.cBalloonedPages)
2951	{
2952	rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_INFLATE, pVM->pgm.s.cBalloonedPages);
2953	AssertRC(rc);
2954	}
2955	return rc;
2956	}
2957
2958
2959	/**
2960	* Execute state load operation.
2961	*
2962	* @returns VBox status code.
2963	* @param pVM VM Handle.
2964	* @param pSSM SSM operation handle.
2965	* @param uVersion Data layout version.
2966	* @param uPass The data pass.
2967	*/
2968	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2969	{
2970	int rc;
2971	PPGM pPGM = &pVM->pgm.s;
2972
2973	/*
2974	* Validate version.
2975	*/
2976	if ( ( uPass != SSM_PASS_FINAL
2977	&& uVersion != PGM_SAVED_STATE_VERSION
2978	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
2979	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2980	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
2981	&& uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
2982	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
2983	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
2984	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
2985	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
2986	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
2987	)
2988	{
2989	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
2990	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2991	}
2992
2993	/*
2994	* Do the loading while owning the lock because a bunch of the functions
2995	* we're using requires this.
2996	*/
2997	if (uPass != SSM_PASS_FINAL)
2998	{
2999	pgmLock(pVM);
3000	if (uPass != 0)
3001	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
3002	else
3003	{
3004	pVM->pgm.s.LiveSave.fActive = true;
3005	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3006	rc = pgmR3LoadRamConfig(pVM, pSSM);
3007	else
3008	rc = VINF_SUCCESS;
3009	if (RT_SUCCESS(rc))
3010	rc = pgmR3LoadRomRanges(pVM, pSSM);
3011	if (RT_SUCCESS(rc))
3012	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
3013	if (RT_SUCCESS(rc))
3014	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
3015	}
3016	pgmUnlock(pVM);
3017	}
3018	else
3019	{
3020	pgmLock(pVM);
3021	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
3022	pVM->pgm.s.LiveSave.fActive = false;
3023	pgmUnlock(pVM);
3024	if (RT_SUCCESS(rc))
3025	{
3026	/*
3027	* We require a full resync now.
3028	*/
3029	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3030	{
3031	PVMCPU pVCpu = &pVM->aCpus[i];
3032	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3033	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3034	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3035	}
3036
3037	pgmR3HandlerPhysicalUpdateAll(pVM);
3038
3039	/*
3040	* Change the paging mode and restore PGMCPU::GCPhysCR3.
3041	* (The latter requires the CPUM state to be restored already.)
3042	*/
3043	if (CPUMR3IsStateRestorePending(pVM))
3044	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3045	N_("PGM was unexpectedly restored before CPUM"));
3046
3047	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3048	{
3049	PVMCPU pVCpu = &pVM->aCpus[i];
3050
3051	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3052	AssertLogRelRCReturn(rc, rc);
3053
3054	/* Update pVM->pgm.s.GCPhysCR3. */
3055	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3056	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3057	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3058	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3059	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3060	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3061	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3062	else
3063	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3064	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3065
3066	/* Update the PSE, NX flags and validity masks. */
3067	pVCpu->pgm.s.fGst32BitPageSizeExtension = CPUMIsGuestPageSizeExtEnabled(pVCpu);
3068	PGMNotifyNxeChanged(pVCpu, CPUMIsGuestNXEnabled(pVCpu));
3069	}
3070
3071	/*
3072	* Try re-fixate the guest mappings.
3073	*/
3074	pVM->pgm.s.fMappingsFixedRestored = false;
3075	if ( pVM->pgm.s.fMappingsFixed
3076	&& pgmMapAreMappingsEnabled(&pVM->pgm.s))
3077	{
3078	RTGCPTR GCPtrFixed = pVM->pgm.s.GCPtrMappingFixed;
3079	uint32_t cbFixed = pVM->pgm.s.cbMappingFixed;
3080	pVM->pgm.s.fMappingsFixed = false;
3081
3082	uint32_t cbRequired;
3083	int rc2 = PGMR3MappingsSize(pVM, &cbRequired); AssertRC(rc2);
3084	if ( RT_SUCCESS(rc2)
3085	&& cbRequired > cbFixed)
3086	rc2 = VERR_OUT_OF_RANGE;
3087	if (RT_SUCCESS(rc2))
3088	rc2 = pgmR3MappingsFixInternal(pVM, GCPtrFixed, cbFixed);
3089	if (RT_FAILURE(rc2))
3090	{
3091	LogRel(("PGM: Unable to re-fixate the guest mappings at %RGv-%RGv: rc=%Rrc (cbRequired=%#x)\n",
3092	GCPtrFixed, GCPtrFixed + cbFixed, rc2, cbRequired));
3093	pVM->pgm.s.fMappingsFixed = false;
3094	pVM->pgm.s.fMappingsFixedRestored = true;
3095	pVM->pgm.s.GCPtrMappingFixed = GCPtrFixed;
3096	pVM->pgm.s.cbMappingFixed = cbFixed;
3097	}
3098	}
3099	else
3100	{
3101	/* We used to set fixed + disabled while we only use disabled now,
3102	so wipe the state to avoid any confusion. */
3103	pVM->pgm.s.fMappingsFixed = false;
3104	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
3105	pVM->pgm.s.cbMappingFixed = 0;
3106	}
3107
3108	/*
3109	* If we have floating mappings, do a CR3 sync now to make sure the HMA
3110	* doesn't conflict with guest code / data and thereby cause trouble
3111	* when restoring other components like PATM.
3112	*/
3113	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3114	{
3115	PVMCPU pVCpu = &pVM->aCpus[0];
3116	rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), true);
3117	if (RT_FAILURE(rc))
3118	return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3119	N_("PGMSyncCR3 failed unexpectedly with rc=%Rrc"), rc);
3120
3121	/* Make sure to re-sync before executing code. */
3122	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3123	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3124	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3125	}
3126	}
3127	}
3128
3129	return rc;
3130	}
3131
3132
3133	/**
3134	* Registers the saved state callbacks with SSM.
3135	*
3136	* @returns VBox status code.
3137	* @param pVM Pointer to VM structure.
3138	* @param cbRam The RAM size.
3139	*/
3140	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3141	{
3142	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3143	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3144	NULL, pgmR3SaveExec, pgmR3SaveDone,
3145	pgmR3LoadPrep, pgmR3Load, NULL);
3146	}
3147

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source: vbox/trunk/src/VBox/VMM/PGMSavedState.cpp@ 31080

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