Changeset 31080 in vbox

Timestamp:

Jul 24, 2010 5:25:32 PM (15 years ago)

Author:

vboxsync

Message:

PGM: Micro optimizations.

Location:

trunk/src/VBox/VMM

Files:

• PGM.cpp (modified) (2 diffs)
• PGMGstDefs.h (modified) (1 diff)
• PGMInline.h (modified) (3 diffs)
• PGMInternal.h (modified) (1 diff)
• PGMSavedState.cpp (modified) (2 diffs)
• VMMAll/PGMAll.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/PGM.cpp

@@ -2345 +2345 @@
     pgmR3PoolReset(pVM);
 
+    /*
+     * Re-init various other members and clear the FFs that PGM owns.
+     */
     for (VMCPUID i = 0; i < pVM->cCpus; i++)
     {
-        PVMCPU  pVCpu = &pVM->aCpus[i];
-
-        /*
-         * Re-init other members.
-         */
+        PVMCPU pVCpu = &pVM->aCpus[i];
+
         pVCpu->pgm.s.fA20Enabled = true;
-
-        /*
-         * Clear the FFs PGM owns.
-         */
+        pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
+        PGMNotifyNxeChanged(pVCpu, false);
+
         VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
         VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
@@ -2362 +2361 @@
 
     /*
-     * Reset (zero) RAM pages.
+     * Reset (zero) RAM and shadow ROM pages.
      */
     rc = pgmR3PhysRamReset(pVM);
     if (RT_SUCCESS(rc))
-    {
-        /*
-         * Reset (zero) shadow ROM pages.
-         */
         rc = pgmR3PhysRomReset(pVM);
-    }
+
 
     pgmUnlock(pVM);

trunk/src/VBox/VMM/PGMGstDefs.h

@@ -127 +127 @@
 //# define GST_IS_BIG_PDPE_VALID(pVCpu, Pdpe)     (false)
 //# define GST_IS_PML4E_VALID(pVCpu, Pml4e)       (false)
-# define GST_IS_PSE_ACTIVE(pVCpu)               pgmGstIsPageSizeExtActive(pVCpu)
+# define GST_IS_PSE_ACTIVE(pVCpu)               pgmGst32BitIsPageSizeExtActive(pVCpu)
 # define GST_IS_NX_ACTIVE(pVCpu)                (false)
 # define BTH_IS_NP_ACTIVE(pVM)                  (false)

trunk/src/VBox/VMM/PGMInline.h

@@ -558 +558 @@
  * Checks if the no-execute (NX) feature is active (EFER.NXE=1).
  *
- * This is inlined so that we can perform consistency checks in debug builds.
+ * Only used when the guest is in PAE or long mode.  This is inlined so that we
+ * can perform consistency checks in debug builds.
  *
  * @returns true if it is, false if it isn't.
@@ -565 +566 @@
 DECL_FORCE_INLINE(bool) pgmGstIsNoExecuteActive(PVMCPU pVCpu)
 {
-    /** @todo shadow this variable */
-    return CPUMIsGuestNXEnabled(pVCpu);
+    Assert(pVCpu->pgm.s.fNoExecuteEnabled == CPUMIsGuestNXEnabled(pVCpu));
+    Assert(CPUMIsGuestInPAEMode(pVCpu) || CPUMIsGuestInLongMode(pVCpu));
+    return pVCpu->pgm.s.fNoExecuteEnabled;
 }
 
@@ -573 +575 @@
  * Checks if the page size extension (PSE) is currently enabled (CR4.PSE=1).
  *
- * This is inlined so that we can perform consistency checks in debug builds.
+ * Only used when the guest is in paged 32-bit mode.  This is inlined so that
+ * we can perform consistency checks in debug builds.
  *
  * @returns true if it is, false if it isn't.
  * @param   pVCpu       The current CPU.
  */
-DECL_FORCE_INLINE(bool) pgmGstIsPageSizeExtActive(PVMCPU pVCpu)
-{
-    /** @todo ( (pVCpu)->pgm.s.fGst32BitPageSizeExtension ) */
-    return CPUMIsGuestPageSizeExtEnabled(pVCpu);
+DECL_FORCE_INLINE(bool) pgmGst32BitIsPageSizeExtActive(PVMCPU pVCpu)
+{
+    Assert(pVCpu->pgm.s.fGst32BitPageSizeExtension == CPUMIsGuestPageSizeExtEnabled(pVCpu));
+    Assert(!CPUMIsGuestInPAEMode(pVCpu));
+    Assert(!CPUMIsGuestInLongMode(pVCpu));
+    return pVCpu->pgm.s.fGst32BitPageSizeExtension;
 }
 

trunk/src/VBox/VMM/PGMInternal.h

@@ -3119 +3119 @@
     /** A20 gate state - boolean! */
     bool                            fA20Enabled;
-    /** Mirror of the EFER.NXE bit. */
+    /** Mirror of the EFER.NXE bit.  Managed by PGMNotifyNxeChanged. */
     bool                            fNoExecuteEnabled;
     /** Unused bits. */

trunk/src/VBox/VMM/PGMSavedState.cpp

@@ -3052 +3052 @@
                 AssertLogRelRCReturn(rc, rc);
 
-                /* Restore pVM->pgm.s.GCPhysCR3. */
+                /* Update pVM->pgm.s.GCPhysCR3. */
                 Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
                 RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
@@ -3063 +3063 @@
                     GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
                 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
+
+                /* Update the PSE, NX flags and validity masks. */
+                pVCpu->pgm.s.fGst32BitPageSizeExtension = CPUMIsGuestPageSizeExtEnabled(pVCpu);
+                PGMNotifyNxeChanged(pVCpu, CPUMIsGuestNXEnabled(pVCpu));
             }
 

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -2006 +2006 @@
 
 /**
- * Called whenever CR0 or CR4 in a way which may change
- * the paging mode.
+ * Called whenever CR0 or CR4 in a way which may affect the paging mode.
  *
  * @returns VBox status code, with the following informational code for
@@ -2034 +2033 @@
         enmGuestMode = PGMMODE_PROTECTED;
     else if (!(cr4 & X86_CR4_PAE))
+    {
+        bool const fPse = !!(cr4 & X86_CR4_PSE);
+        if (pVCpu->pgm.s.fGst32BitPageSizeExtension != fPse)
+            Log(("PGMChangeMode: CR4.PSE %d -> %d\n", pVCpu->pgm.s.fGst32BitPageSizeExtension, fPse));
+        pVCpu->pgm.s.fGst32BitPageSizeExtension = fPse;
         enmGuestMode = PGMMODE_32_BIT;
+    }
     else if (!(efer & MSR_K6_EFER_LME))
     {