VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp@ 51208

Last change on this file since 51208 was 50617, checked in by vboxsync, 11 years ago

Implemented MSR 0x00000035 on i7, it reports threads and core counts on intel.
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1/* $Id: CPUMAllMsrs.cpp 50617 2014-02-26 19:34:46Z vboxsync $ */
2/** @file
3 * CPUM - CPU MSR Registers.
4 */
5
6/*
7 * Copyright (C) 2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/pdmapi.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/tm.h>
26#include "CPUMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/err.h>
29
30
31/*******************************************************************************
32* Defined Constants And Macros *
33*******************************************************************************/
34/**
35 * Validates the CPUMMSRRANGE::offCpumCpu value and declares a local variable
36 * pointing to it.
37 *
38 * ASSUMES sizeof(a_Type) is a power of two and that the member is aligned
39 * correctly.
40 */
41#define CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(a_pVCpu, a_pRange, a_Type, a_VarName) \
42 AssertMsgReturn( (a_pRange)->offCpumCpu >= 8 \
43 && (a_pRange)->offCpumCpu < sizeof(CPUMCPU) \
44 && !((a_pRange)->offCpumCpu & (RT_MIN(sizeof(a_Type), 8) - 1)) \
45 , ("offCpumCpu=%#x %s\n", (a_pRange)->offCpumCpu, (a_pRange)->szName), \
46 VERR_CPUM_MSR_BAD_CPUMCPU_OFFSET); \
47 a_Type *a_VarName = (a_Type *)((uintptr_t)&(a_pVCpu)->cpum.s + (a_pRange)->offCpumCpu)
48
49
50/*******************************************************************************
51* Structures and Typedefs *
52*******************************************************************************/
53
54/**
55 * Implements reading one or more MSRs.
56 *
57 * @returns VBox status code.
58 * @retval VINF_SUCCESS on success.
59 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR).
60 *
61 * @param pVCpu Pointer to the VMCPU.
62 * @param idMsr The MSR we're reading.
63 * @param pRange The MSR range descriptor.
64 * @param puValue Where to return the value.
65 */
66typedef DECLCALLBACK(int) FNCPUMRDMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
67/** Pointer to a RDMSR worker for a specific MSR or range of MSRs. */
68typedef FNCPUMRDMSR *PFNCPUMRDMSR;
69
70
71/**
72 * Implements writing one or more MSRs.
73 *
74 * @retval VINF_SUCCESS on success.
75 * @retval VERR_CPUM_RAISE_GP_0 on failure.
76 *
77 * @param pVCpu Pointer to the VMCPU.
78 * @param idMsr The MSR we're writing.
79 * @param pRange The MSR range descriptor.
80 * @param uValue The value to set, ignored bits masked.
81 * @param uRawValue The raw value with the ignored bits not masked.
82 */
83typedef DECLCALLBACK(int) FNCPUMWRMSR(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
84/** Pointer to a WRMSR worker for a specific MSR or range of MSRs. */
85typedef FNCPUMWRMSR *PFNCPUMWRMSR;
86
87
88
89/*
90 * Generic functions.
91 * Generic functions.
92 * Generic functions.
93 */
94
95
96/** @callback_method_impl{FNCPUMRDMSR} */
97static DECLCALLBACK(int) cpumMsrRd_FixedValue(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
98{
99 *puValue = pRange->uValue;
100 return VINF_SUCCESS;
101}
102
103
104/** @callback_method_impl{FNCPUMWRMSR} */
105static DECLCALLBACK(int) cpumMsrWr_IgnoreWrite(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
106{
107 Log(("CPUM: Ignoring WRMSR %#x (%s), %#llx\n", idMsr, pRange->szName, uValue));
108 return VINF_SUCCESS;
109}
110
111
112/** @callback_method_impl{FNCPUMRDMSR} */
113static DECLCALLBACK(int) cpumMsrRd_WriteOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
114{
115 return VERR_CPUM_RAISE_GP_0;
116}
117
118
119/** @callback_method_impl{FNCPUMWRMSR} */
120static DECLCALLBACK(int) cpumMsrWr_ReadOnly(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
121{
122 Assert(pRange->fWrGpMask == UINT64_MAX);
123 return VERR_CPUM_RAISE_GP_0;
124}
125
126
127
128
129/*
130 * IA32
131 * IA32
132 * IA32
133 */
134
135/** @callback_method_impl{FNCPUMRDMSR} */
136static DECLCALLBACK(int) cpumMsrRd_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
137{
138 *puValue = 0; /** @todo implement machine check injection. */
139 return VINF_SUCCESS;
140}
141
142
143/** @callback_method_impl{FNCPUMWRMSR} */
144static DECLCALLBACK(int) cpumMsrWr_Ia32P5McAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
145{
146 /** @todo implement machine check injection. */
147 return VINF_SUCCESS;
148}
149
150
151/** @callback_method_impl{FNCPUMRDMSR} */
152static DECLCALLBACK(int) cpumMsrRd_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
153{
154 *puValue = 0; /** @todo implement machine check injection. */
155 return VINF_SUCCESS;
156}
157
158
159/** @callback_method_impl{FNCPUMWRMSR} */
160static DECLCALLBACK(int) cpumMsrWr_Ia32P5McType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
161{
162 /** @todo implement machine check injection. */
163 return VINF_SUCCESS;
164}
165
166
167/** @callback_method_impl{FNCPUMRDMSR} */
168static DECLCALLBACK(int) cpumMsrRd_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
169{
170 *puValue = TMCpuTickGet(pVCpu);
171 return VINF_SUCCESS;
172}
173
174
175/** @callback_method_impl{FNCPUMWRMSR} */
176static DECLCALLBACK(int) cpumMsrWr_Ia32TimestampCounter(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
177{
178 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
179 return VINF_SUCCESS;
180}
181
182
183/** @callback_method_impl{FNCPUMRDMSR} */
184static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
185{
186 uint64_t uValue = pRange->uValue;
187 if (uValue & 0x1f00)
188 {
189 /* Max allowed bus ratio present. */
190 /** @todo Implement scaled BUS frequency. */
191 }
192
193 *puValue = uValue;
194 return VINF_SUCCESS;
195}
196
197
198/** @callback_method_impl{FNCPUMRDMSR} */
199static DECLCALLBACK(int) cpumMsrRd_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
200{
201 PVM pVM = pVCpu->CTX_SUFF(pVM);
202 if ( !pVM->cpum.s.GuestFeatures.fApic
203 && !pVM->cpum.s.GuestFeatures.fX2Apic)
204 {
205 Log(("CPUM: %s, apic not present -> GP\n", pRange->szName));
206 return VERR_CPUM_RAISE_GP_0;
207 }
208
209 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
210 return VINF_SUCCESS;
211}
212
213
214/** @callback_method_impl{FNCPUMWRMSR} */
215static DECLCALLBACK(int) cpumMsrWr_Ia32ApicBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
216{
217 int rc = PDMApicSetBase(pVCpu, uValue);
218 if (rc != VINF_SUCCESS)
219 rc = VERR_CPUM_RAISE_GP_0;
220 return VINF_SUCCESS;
221}
222
223
224/** @callback_method_impl{FNCPUMRDMSR} */
225static DECLCALLBACK(int) cpumMsrRd_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
226{
227 *puValue = 1; /* Locked, no VT-X, no SYSENTER micromanagement. */
228 return VINF_SUCCESS;
229}
230
231
232/** @callback_method_impl{FNCPUMWRMSR} */
233static DECLCALLBACK(int) cpumMsrWr_Ia32FeatureControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
234{
235 return VERR_CPUM_RAISE_GP_0;
236}
237
238
239/** @callback_method_impl{FNCPUMRDMSR} */
240static DECLCALLBACK(int) cpumMsrRd_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
241{
242 /** @todo fake microcode update. */
243 *puValue = pRange->uValue;
244 return VINF_SUCCESS;
245}
246
247
248/** @callback_method_impl{FNCPUMWRMSR} */
249static DECLCALLBACK(int) cpumMsrWr_Ia32BiosSignId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
250{
251 /* Normally, zero is written to Ia32BiosSignId before reading it in order
252 to select the signature instead of the BBL_CR_D3 behaviour. The GP mask
253 of the database entry should take care of most illegal writes for now, so
254 just ignore all writes atm. */
255 return VINF_SUCCESS;
256}
257
258
259/** @callback_method_impl{FNCPUMWRMSR} */
260static DECLCALLBACK(int) cpumMsrWr_Ia32BiosUpdateTrigger(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
261{
262 /** @todo Fake bios update trigger better. The value is the address to an
263 * update package, I think. We should probably GP if it's invalid. */
264 return VINF_SUCCESS;
265}
266
267
268/** @callback_method_impl{FNCPUMRDMSR} */
269static DECLCALLBACK(int) cpumMsrRd_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
270{
271 /** @todo SMM. */
272 *puValue = 0;
273 return VINF_SUCCESS;
274}
275
276
277/** @callback_method_impl{FNCPUMWRMSR} */
278static DECLCALLBACK(int) cpumMsrWr_Ia32SmmMonitorCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
279{
280 /** @todo SMM. */
281 return VINF_SUCCESS;
282}
283
284
285/** @callback_method_impl{FNCPUMRDMSR} */
286static DECLCALLBACK(int) cpumMsrRd_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
287{
288 /** @todo check CPUID leaf 0ah. */
289 *puValue = 0;
290 return VINF_SUCCESS;
291}
292
293
294/** @callback_method_impl{FNCPUMWRMSR} */
295static DECLCALLBACK(int) cpumMsrWr_Ia32PmcN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
296{
297 /** @todo check CPUID leaf 0ah. */
298 return VINF_SUCCESS;
299}
300
301
302/** @callback_method_impl{FNCPUMRDMSR} */
303static DECLCALLBACK(int) cpumMsrRd_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
304{
305 /** @todo return 0x1000 if we try emulate mwait 100% correctly. */
306 *puValue = 0x40; /** @todo Change to CPU cache line size. */
307 return VINF_SUCCESS;
308}
309
310
311/** @callback_method_impl{FNCPUMWRMSR} */
312static DECLCALLBACK(int) cpumMsrWr_Ia32MonitorFilterLineSize(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
313{
314 /** @todo should remember writes, though it's supposedly something only a BIOS
315 * would write so, it's not extremely important. */
316 return VINF_SUCCESS;
317}
318
319/** @callback_method_impl{FNCPUMRDMSR} */
320static DECLCALLBACK(int) cpumMsrRd_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
321{
322 /** @todo Read MPERF: Adjust against previously written MPERF value. Is TSC
323 * what we want? */
324 *puValue = TMCpuTickGet(pVCpu);
325 return VINF_SUCCESS;
326}
327
328
329/** @callback_method_impl{FNCPUMWRMSR} */
330static DECLCALLBACK(int) cpumMsrWr_Ia32MPerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
331{
332 /** @todo Write MPERF: Calc adjustment. */
333 return VINF_SUCCESS;
334}
335
336
337/** @callback_method_impl{FNCPUMRDMSR} */
338static DECLCALLBACK(int) cpumMsrRd_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
339{
340 /** @todo Read APERF: Adjust against previously written MPERF value. Is TSC
341 * what we want? */
342 *puValue = TMCpuTickGet(pVCpu);
343 return VINF_SUCCESS;
344}
345
346
347/** @callback_method_impl{FNCPUMWRMSR} */
348static DECLCALLBACK(int) cpumMsrWr_Ia32APerf(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
349{
350 /** @todo Write APERF: Calc adjustment. */
351 return VINF_SUCCESS;
352}
353
354
355/** @callback_method_impl{FNCPUMWRMSR} */
356static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
357{
358 /* This is currently a bit weird. :-) */
359 uint8_t const cVariableRangeRegs = 0;
360 bool const fSystemManagementRangeRegisters = false;
361 bool const fFixedRangeRegisters = false;
362 bool const fWriteCombiningType = false;
363 *puValue = cVariableRangeRegs
364 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
365 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
366 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
367 return VINF_SUCCESS;
368}
369
370
371/** @callback_method_impl{FNCPUMRDMSR} */
372static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
373{
374 /** @todo Implement variable MTRR storage. */
375 Assert(pRange->uValue == (idMsr - 0x200) / 2);
376 *puValue = 0;
377 return VINF_SUCCESS;
378}
379
380
381/** @callback_method_impl{FNCPUMWRMSR} */
382static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
383{
384 /*
385 * Validate the value.
386 */
387 Assert(pRange->uValue == (idMsr - 0x200) / 2);
388
389 if ((uValue & 0xff) >= 7)
390 {
391 Log(("CPUM: Invalid type set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n", idMsr, uValue, uValue & 0xff));
392 return VERR_CPUM_RAISE_GP_0;
393 }
394
395 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
396 if (fInvPhysMask & uValue)
397 {
398 Log(("CPUM: Invalid physical address bits set writing MTRR PhysBase MSR %#x: %#llx (%#llx)\n",
399 idMsr, uValue, uValue & fInvPhysMask));
400 return VERR_CPUM_RAISE_GP_0;
401 }
402
403 /*
404 * Store it.
405 */
406 /** @todo Implement variable MTRR storage. */
407 return VINF_SUCCESS;
408}
409
410
411/** @callback_method_impl{FNCPUMRDMSR} */
412static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
413{
414 /** @todo Implement variable MTRR storage. */
415 Assert(pRange->uValue == (idMsr - 0x200) / 2);
416 *puValue = 0;
417 return VINF_SUCCESS;
418}
419
420
421/** @callback_method_impl{FNCPUMWRMSR} */
422static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrPhysMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
423{
424 /*
425 * Validate the value.
426 */
427 Assert(pRange->uValue == (idMsr - 0x200) / 2);
428
429 uint64_t fInvPhysMask = ~(RT_BIT_64(pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
430 if (fInvPhysMask & uValue)
431 {
432 Log(("CPUM: Invalid physical address bits set writing MTRR PhysMask MSR %#x: %#llx (%#llx)\n",
433 idMsr, uValue, uValue & fInvPhysMask));
434 return VERR_CPUM_RAISE_GP_0;
435 }
436
437 /*
438 * Store it.
439 */
440 /** @todo Implement variable MTRR storage. */
441 return VINF_SUCCESS;
442}
443
444
445/** @callback_method_impl{FNCPUMRDMSR} */
446static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
447{
448 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
449 *puValue = *puFixedMtrr;
450 return VINF_SUCCESS;
451}
452
453
454/** @callback_method_impl{FNCPUMWRMSR} */
455static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrFixed(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
456{
457 CPUM_MSR_ASSERT_CPUMCPU_OFFSET_RETURN(pVCpu, pRange, uint64_t, puFixedMtrr);
458 for (uint32_t cShift = 0; cShift < 63; cShift += 8)
459 {
460 uint8_t uType = (uint8_t)(uValue >> cShift);
461 if (uType >= 7)
462 {
463 Log(("CPUM: Invalid MTRR type at %u:%u in fixed range (%#x/%s): %#llx (%#llx)\n",
464 cShift + 7, cShift, idMsr, pRange->szName, uValue, uType));
465 return VERR_CPUM_RAISE_GP_0;
466 }
467 }
468 *puFixedMtrr = uValue;
469 return VINF_SUCCESS;
470}
471
472
473/** @callback_method_impl{FNCPUMRDMSR} */
474static DECLCALLBACK(int) cpumMsrRd_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
475{
476 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
477 return VINF_SUCCESS;
478}
479
480
481/** @callback_method_impl{FNCPUMWRMSR} */
482static DECLCALLBACK(int) cpumMsrWr_Ia32MtrrDefType(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
483{
484 if ((uValue & 0xff) >= 7)
485 {
486 Log(("CPUM: Invalid MTRR default type value: %#llx (%#llx)\n", pRange->szName, uValue, uValue & 0xff));
487 return VERR_CPUM_RAISE_GP_0;
488 }
489
490 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
491 return VINF_SUCCESS;
492}
493
494
495/** @callback_method_impl{FNCPUMRDMSR} */
496static DECLCALLBACK(int) cpumMsrRd_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
497{
498 *puValue = pVCpu->cpum.s.Guest.msrPAT;
499 return VINF_SUCCESS;
500}
501
502
503/** @callback_method_impl{FNCPUMWRMSR} */
504static DECLCALLBACK(int) cpumMsrWr_Ia32Pat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
505{
506 pVCpu->cpum.s.Guest.msrPAT = uValue;
507 return VINF_SUCCESS;
508}
509
510
511/** @callback_method_impl{FNCPUMRDMSR} */
512static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
513{
514 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
515 return VINF_SUCCESS;
516}
517
518
519/** @callback_method_impl{FNCPUMWRMSR} */
520static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterCs(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
521{
522 /* Note! We used to mask this by 0xffff, but turns out real HW doesn't and
523 there are generally 32-bit working bits backing this register. */
524 pVCpu->cpum.s.Guest.SysEnter.cs = uValue;
525 return VINF_SUCCESS;
526}
527
528
529/** @callback_method_impl{FNCPUMRDMSR} */
530static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
531{
532 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
533 return VINF_SUCCESS;
534}
535
536
537/** @callback_method_impl{FNCPUMWRMSR} */
538static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEsp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
539{
540 if (X86_IS_CANONICAL(uValue))
541 {
542 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
543 return VINF_SUCCESS;
544 }
545 Log(("CPUM: IA32_SYSENTER_ESP not canonical! %#llx\n", uValue));
546 return VERR_CPUM_RAISE_GP_0;
547}
548
549
550/** @callback_method_impl{FNCPUMRDMSR} */
551static DECLCALLBACK(int) cpumMsrRd_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
552{
553 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
554 return VINF_SUCCESS;
555}
556
557
558/** @callback_method_impl{FNCPUMWRMSR} */
559static DECLCALLBACK(int) cpumMsrWr_Ia32SysEnterEip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
560{
561 if (X86_IS_CANONICAL(uValue))
562 {
563 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
564 return VINF_SUCCESS;
565 }
566 Log(("CPUM: IA32_SYSENTER_EIP not canonical! %#llx\n", uValue));
567 return VERR_CPUM_RAISE_GP_0;
568}
569
570
571/** @callback_method_impl{FNCPUMRDMSR} */
572static DECLCALLBACK(int) cpumMsrRd_Ia32McgCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
573{
574#if 0 /** @todo implement machine checks. */
575 *puValue = pRange->uValue & (RT_BIT_64(8) | 0);
576#else
577 *puValue = 0;
578#endif
579 return VINF_SUCCESS;
580}
581
582
583/** @callback_method_impl{FNCPUMRDMSR} */
584static DECLCALLBACK(int) cpumMsrRd_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
585{
586 /** @todo implement machine checks. */
587 *puValue = 0;
588 return VINF_SUCCESS;
589}
590
591
592/** @callback_method_impl{FNCPUMWRMSR} */
593static DECLCALLBACK(int) cpumMsrWr_Ia32McgStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
594{
595 /** @todo implement machine checks. */
596 return VINF_SUCCESS;
597}
598
599
600/** @callback_method_impl{FNCPUMRDMSR} */
601static DECLCALLBACK(int) cpumMsrRd_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
602{
603 /** @todo implement machine checks. */
604 *puValue = 0;
605 return VINF_SUCCESS;
606}
607
608
609/** @callback_method_impl{FNCPUMWRMSR} */
610static DECLCALLBACK(int) cpumMsrWr_Ia32McgCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
611{
612 /** @todo implement machine checks. */
613 return VINF_SUCCESS;
614}
615
616
617/** @callback_method_impl{FNCPUMRDMSR} */
618static DECLCALLBACK(int) cpumMsrRd_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
619{
620 /** @todo implement IA32_DEBUGCTL. */
621 *puValue = 0;
622 return VINF_SUCCESS;
623}
624
625
626/** @callback_method_impl{FNCPUMWRMSR} */
627static DECLCALLBACK(int) cpumMsrWr_Ia32DebugCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
628{
629 /** @todo implement IA32_DEBUGCTL. */
630 return VINF_SUCCESS;
631}
632
633
634/** @callback_method_impl{FNCPUMRDMSR} */
635static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
636{
637 /** @todo implement intel SMM. */
638 *puValue = 0;
639 return VINF_SUCCESS;
640}
641
642
643/** @callback_method_impl{FNCPUMWRMSR} */
644static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
645{
646 /** @todo implement intel SMM. */
647 return VERR_CPUM_RAISE_GP_0;
648}
649
650
651/** @callback_method_impl{FNCPUMRDMSR} */
652static DECLCALLBACK(int) cpumMsrRd_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
653{
654 /** @todo implement intel SMM. */
655 *puValue = 0;
656 return VINF_SUCCESS;
657}
658
659
660/** @callback_method_impl{FNCPUMWRMSR} */
661static DECLCALLBACK(int) cpumMsrWr_Ia32SmrrPhysMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
662{
663 /** @todo implement intel SMM. */
664 return VERR_CPUM_RAISE_GP_0;
665}
666
667
668/** @callback_method_impl{FNCPUMRDMSR} */
669static DECLCALLBACK(int) cpumMsrRd_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
670{
671 /** @todo implement intel direct cache access (DCA)?? */
672 *puValue = 0;
673 return VINF_SUCCESS;
674}
675
676
677/** @callback_method_impl{FNCPUMWRMSR} */
678static DECLCALLBACK(int) cpumMsrWr_Ia32PlatformDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
679{
680 /** @todo implement intel direct cache access (DCA)?? */
681 return VINF_SUCCESS;
682}
683
684
685/** @callback_method_impl{FNCPUMRDMSR} */
686static DECLCALLBACK(int) cpumMsrRd_Ia32CpuDcaCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
687{
688 /** @todo implement intel direct cache access (DCA)?? */
689 *puValue = 0;
690 return VINF_SUCCESS;
691}
692
693
694/** @callback_method_impl{FNCPUMRDMSR} */
695static DECLCALLBACK(int) cpumMsrRd_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
696{
697 /** @todo implement intel direct cache access (DCA)?? */
698 *puValue = 0;
699 return VINF_SUCCESS;
700}
701
702
703/** @callback_method_impl{FNCPUMWRMSR} */
704static DECLCALLBACK(int) cpumMsrWr_Ia32Dca0Cap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
705{
706 /** @todo implement intel direct cache access (DCA)?? */
707 return VINF_SUCCESS;
708}
709
710
711/** @callback_method_impl{FNCPUMRDMSR} */
712static DECLCALLBACK(int) cpumMsrRd_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
713{
714 /** @todo implement IA32_PERFEVTSEL0+. */
715 *puValue = 0;
716 return VINF_SUCCESS;
717}
718
719
720/** @callback_method_impl{FNCPUMWRMSR} */
721static DECLCALLBACK(int) cpumMsrWr_Ia32PerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
722{
723 /** @todo implement IA32_PERFEVTSEL0+. */
724 return VINF_SUCCESS;
725}
726
727
728/** @callback_method_impl{FNCPUMRDMSR} */
729static DECLCALLBACK(int) cpumMsrRd_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
730{
731 uint64_t uValue = pRange->uValue;
732
733 /* Always provide the max bus ratio for now. XNU expects it. */
734 uValue &= ~((UINT64_C(0x1f) << 40) | RT_BIT_64(46));
735
736 PVM pVM = pVCpu->CTX_SUFF(pVM);
737 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
738 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
739 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
740 if (uTscRatio > 0x1f)
741 uTscRatio = 0x1f;
742 uValue |= (uint64_t)uTscRatio << 40;
743
744 *puValue = uValue;
745 return VINF_SUCCESS;
746}
747
748
749/** @callback_method_impl{FNCPUMWRMSR} */
750static DECLCALLBACK(int) cpumMsrWr_Ia32PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
751{
752 /* Pentium4 allows writing, but all bits are ignored. */
753 return VINF_SUCCESS;
754}
755
756
757/** @callback_method_impl{FNCPUMRDMSR} */
758static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
759{
760 /** @todo implement IA32_PERFCTL. */
761 *puValue = 0;
762 return VINF_SUCCESS;
763}
764
765
766/** @callback_method_impl{FNCPUMWRMSR} */
767static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
768{
769 /** @todo implement IA32_PERFCTL. */
770 return VINF_SUCCESS;
771}
772
773
774/** @callback_method_impl{FNCPUMRDMSR} */
775static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
776{
777 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
778 *puValue = 0;
779 return VINF_SUCCESS;
780}
781
782
783/** @callback_method_impl{FNCPUMWRMSR} */
784static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
785{
786 /** @todo implement IA32_FIXED_CTRn (fixed performance counters). */
787 return VINF_SUCCESS;
788}
789
790
791/** @callback_method_impl{FNCPUMRDMSR} */
792static DECLCALLBACK(int) cpumMsrRd_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
793{
794 /** @todo implement performance counters. */
795 *puValue = 0;
796 return VINF_SUCCESS;
797}
798
799
800/** @callback_method_impl{FNCPUMWRMSR} */
801static DECLCALLBACK(int) cpumMsrWr_Ia32PerfCapabilities(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
802{
803 /** @todo implement performance counters. */
804 return VINF_SUCCESS;
805}
806
807
808/** @callback_method_impl{FNCPUMRDMSR} */
809static DECLCALLBACK(int) cpumMsrRd_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
810{
811 /** @todo implement performance counters. */
812 *puValue = 0;
813 return VINF_SUCCESS;
814}
815
816
817/** @callback_method_impl{FNCPUMWRMSR} */
818static DECLCALLBACK(int) cpumMsrWr_Ia32FixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
819{
820 /** @todo implement performance counters. */
821 return VINF_SUCCESS;
822}
823
824
825/** @callback_method_impl{FNCPUMRDMSR} */
826static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
827{
828 /** @todo implement performance counters. */
829 *puValue = 0;
830 return VINF_SUCCESS;
831}
832
833
834/** @callback_method_impl{FNCPUMWRMSR} */
835static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
836{
837 /** @todo implement performance counters. */
838 return VINF_SUCCESS;
839}
840
841
842/** @callback_method_impl{FNCPUMRDMSR} */
843static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
844{
845 /** @todo implement performance counters. */
846 *puValue = 0;
847 return VINF_SUCCESS;
848}
849
850
851/** @callback_method_impl{FNCPUMWRMSR} */
852static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
853{
854 /** @todo implement performance counters. */
855 return VINF_SUCCESS;
856}
857
858
859/** @callback_method_impl{FNCPUMRDMSR} */
860static DECLCALLBACK(int) cpumMsrRd_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
861{
862 /** @todo implement performance counters. */
863 *puValue = 0;
864 return VINF_SUCCESS;
865}
866
867
868/** @callback_method_impl{FNCPUMWRMSR} */
869static DECLCALLBACK(int) cpumMsrWr_Ia32PerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
870{
871 /** @todo implement performance counters. */
872 return VINF_SUCCESS;
873}
874
875
876/** @callback_method_impl{FNCPUMRDMSR} */
877static DECLCALLBACK(int) cpumMsrRd_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
878{
879 /** @todo implement performance counters. */
880 *puValue = 0;
881 return VINF_SUCCESS;
882}
883
884
885/** @callback_method_impl{FNCPUMWRMSR} */
886static DECLCALLBACK(int) cpumMsrWr_Ia32PebsEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
887{
888 /** @todo implement performance counters. */
889 return VINF_SUCCESS;
890}
891
892
893/** @callback_method_impl{FNCPUMRDMSR} */
894static DECLCALLBACK(int) cpumMsrRd_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
895{
896 /** @todo implement IA32_CLOCK_MODULATION. */
897 *puValue = 0;
898 return VINF_SUCCESS;
899}
900
901
902/** @callback_method_impl{FNCPUMWRMSR} */
903static DECLCALLBACK(int) cpumMsrWr_Ia32ClockModulation(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
904{
905 /** @todo implement IA32_CLOCK_MODULATION. */
906 return VINF_SUCCESS;
907}
908
909
910/** @callback_method_impl{FNCPUMRDMSR} */
911static DECLCALLBACK(int) cpumMsrRd_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
912{
913 /** @todo implement IA32_THERM_INTERRUPT. */
914 *puValue = 0;
915 return VINF_SUCCESS;
916}
917
918
919/** @callback_method_impl{FNCPUMWRMSR} */
920static DECLCALLBACK(int) cpumMsrWr_Ia32ThermInterrupt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
921{
922 /** @todo implement IA32_THERM_STATUS. */
923 return VINF_SUCCESS;
924}
925
926
927/** @callback_method_impl{FNCPUMRDMSR} */
928static DECLCALLBACK(int) cpumMsrRd_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
929{
930 /** @todo implement IA32_THERM_STATUS. */
931 *puValue = 0;
932 return VINF_SUCCESS;
933}
934
935
936/** @callback_method_impl{FNCPUMWRMSR} */
937static DECLCALLBACK(int) cpumMsrWr_Ia32ThermStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
938{
939 /** @todo implement IA32_THERM_INTERRUPT. */
940 return VINF_SUCCESS;
941}
942
943
944/** @callback_method_impl{FNCPUMRDMSR} */
945static DECLCALLBACK(int) cpumMsrRd_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
946{
947 /** @todo implement IA32_THERM2_CTL. */
948 *puValue = 0;
949 return VINF_SUCCESS;
950}
951
952
953/** @callback_method_impl{FNCPUMWRMSR} */
954static DECLCALLBACK(int) cpumMsrWr_Ia32Therm2Ctl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
955{
956 /** @todo implement IA32_THERM2_CTL. */
957 return VINF_SUCCESS;
958}
959
960
961/** @callback_method_impl{FNCPUMRDMSR} */
962static DECLCALLBACK(int) cpumMsrRd_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
963{
964 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
965 return VINF_SUCCESS;
966}
967
968
969/** @callback_method_impl{FNCPUMWRMSR} */
970static DECLCALLBACK(int) cpumMsrWr_Ia32MiscEnable(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
971{
972#ifdef LOG_ENABLED
973 uint64_t const uOld = pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
974#endif
975
976 /* Unsupported bits are generally ignored and stripped by the MSR range
977 entry that got us here. So, we just need to preserve fixed bits. */
978 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue
979 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
980 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
981
982 Log(("CPUM: IA32_MISC_ENABLE; old=%#llx written=%#llx => %#llx\n",
983 uOld, uValue, pVCpu->cpum.s.GuestMsrs.msr.MiscEnable));
984
985 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
986 /** @todo Wire up MSR_IA32_MISC_ENABLE_XD_DISABLE. */
987 return VINF_SUCCESS;
988}
989
990
991/** @callback_method_impl{FNCPUMRDMSR} */
992static DECLCALLBACK(int) cpumMsrRd_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
993{
994 /** @todo Implement machine check exception injection. */
995 switch (idMsr & 3)
996 {
997 case 0:
998 case 1:
999 *puValue = 0;
1000 break;
1001
1002 /* The ADDR and MISC registers aren't accessible since the
1003 corresponding STATUS bits are zero. */
1004 case 2:
1005 Log(("CPUM: Reading IA32_MCi_ADDR %#x -> #GP\n", idMsr));
1006 return VERR_CPUM_RAISE_GP_0;
1007 case 3:
1008 Log(("CPUM: Reading IA32_MCi_MISC %#x -> #GP\n", idMsr));
1009 return VERR_CPUM_RAISE_GP_0;
1010 }
1011 return VINF_SUCCESS;
1012}
1013
1014
1015/** @callback_method_impl{FNCPUMWRMSR} */
1016static DECLCALLBACK(int) cpumMsrWr_Ia32McCtlStatusAddrMiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1017{
1018 switch (idMsr & 3)
1019 {
1020 case 0:
1021 /* Ignore writes to the CTL register. */
1022 break;
1023
1024 case 1:
1025 /* According to specs, the STATUS register can only be written to
1026 with the value 0. VBoxCpuReport thinks different for a
1027 Pentium M Dothan, but implementing according to specs now. */
1028 if (uValue != 0)
1029 {
1030 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_STATUS %#x -> #GP\n", uValue, idMsr));
1031 return VERR_CPUM_RAISE_GP_0;
1032 }
1033 break;
1034
1035 /* Specs states that ADDR and MISC can be cleared by writing zeros.
1036 Writing 1s will GP. Need to figure out how this relates to the
1037 ADDRV and MISCV status flags. If writing is independent of those
1038 bits, we need to know whether the CPU really implements them since
1039 that is exposed by writing 0 to them.
1040 Implementing the solution with the fewer GPs for now. */
1041 case 2:
1042 if (uValue != 0)
1043 {
1044 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_ADDR %#x -> #GP\n", uValue, idMsr));
1045 return VERR_CPUM_RAISE_GP_0;
1046 }
1047 break;
1048 case 3:
1049 if (uValue != 0)
1050 {
1051 Log(("CPUM: Writing non-zero value (%#llx) to IA32_MCi_MISC %#x -> #GP\n", uValue, idMsr));
1052 return VERR_CPUM_RAISE_GP_0;
1053 }
1054 break;
1055 }
1056 return VINF_SUCCESS;
1057}
1058
1059
1060/** @callback_method_impl{FNCPUMRDMSR} */
1061static DECLCALLBACK(int) cpumMsrRd_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1062{
1063 /** @todo Implement machine check exception injection. */
1064 *puValue = 0;
1065 return VINF_SUCCESS;
1066}
1067
1068
1069/** @callback_method_impl{FNCPUMWRMSR} */
1070static DECLCALLBACK(int) cpumMsrWr_Ia32McNCtl2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1071{
1072 /** @todo Implement machine check exception injection. */
1073 return VINF_SUCCESS;
1074}
1075
1076
1077/** @callback_method_impl{FNCPUMRDMSR} */
1078static DECLCALLBACK(int) cpumMsrRd_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1079{
1080 /** @todo implement IA32_DS_AREA. */
1081 *puValue = 0;
1082 return VINF_SUCCESS;
1083}
1084
1085
1086/** @callback_method_impl{FNCPUMWRMSR} */
1087static DECLCALLBACK(int) cpumMsrWr_Ia32DsArea(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1088{
1089 return VINF_SUCCESS;
1090}
1091
1092
1093/** @callback_method_impl{FNCPUMRDMSR} */
1094static DECLCALLBACK(int) cpumMsrRd_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1095{
1096 /** @todo implement TSC deadline timer. */
1097 *puValue = 0;
1098 return VINF_SUCCESS;
1099}
1100
1101
1102/** @callback_method_impl{FNCPUMWRMSR} */
1103static DECLCALLBACK(int) cpumMsrWr_Ia32TscDeadline(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1104{
1105 /** @todo implement TSC deadline timer. */
1106 return VINF_SUCCESS;
1107}
1108
1109
1110/** @callback_method_impl{FNCPUMRDMSR} */
1111static DECLCALLBACK(int) cpumMsrRd_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1112{
1113 int rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1114 if (rc != VINF_SUCCESS)
1115 {
1116 Log(("CPUM: X2APIC %#x read => %Rrc => #GP\n", idMsr, rc));
1117 return VERR_CPUM_RAISE_GP_0;
1118 }
1119 return VINF_SUCCESS;
1120}
1121
1122
1123/** @callback_method_impl{FNCPUMWRMSR} */
1124static DECLCALLBACK(int) cpumMsrWr_Ia32X2ApicN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1125{
1126 int rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1127 if (rc != VINF_SUCCESS)
1128 {
1129 Log(("CPUM: X2APIC %#x write %#llx => %Rrc => #GP\n", idMsr, rc, uValue));
1130 return VERR_CPUM_RAISE_GP_0;
1131 }
1132 return VINF_SUCCESS;
1133}
1134
1135
1136/** @callback_method_impl{FNCPUMRDMSR} */
1137static DECLCALLBACK(int) cpumMsrRd_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1138{
1139 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1140 *puValue = 0;
1141 return VINF_SUCCESS;
1142}
1143
1144
1145/** @callback_method_impl{FNCPUMWRMSR} */
1146static DECLCALLBACK(int) cpumMsrWr_Ia32DebugInterface(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1147{
1148 /** @todo IA32_DEBUG_INTERFACE (no docs) */
1149 return VINF_SUCCESS;
1150}
1151
1152
1153/** @callback_method_impl{FNCPUMRDMSR} */
1154static DECLCALLBACK(int) cpumMsrRd_Ia32VmxBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1155{
1156 *puValue = 0;
1157 return VINF_SUCCESS;
1158}
1159
1160
1161/** @callback_method_impl{FNCPUMRDMSR} */
1162static DECLCALLBACK(int) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1163{
1164 *puValue = 0;
1165 return VINF_SUCCESS;
1166}
1167
1168
1169/** @callback_method_impl{FNCPUMRDMSR} */
1170static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1171{
1172 *puValue = 0;
1173 return VINF_SUCCESS;
1174}
1175
1176
1177/** @callback_method_impl{FNCPUMRDMSR} */
1178static DECLCALLBACK(int) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1179{
1180 *puValue = 0;
1181 return VINF_SUCCESS;
1182}
1183
1184
1185/** @callback_method_impl{FNCPUMRDMSR} */
1186static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1187{
1188 *puValue = 0;
1189 return VINF_SUCCESS;
1190}
1191
1192
1193/** @callback_method_impl{FNCPUMRDMSR} */
1194static DECLCALLBACK(int) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1195{
1196 *puValue = 0;
1197 return VINF_SUCCESS;
1198}
1199
1200
1201/** @callback_method_impl{FNCPUMRDMSR} */
1202static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1203{
1204 *puValue = 0;
1205 return VINF_SUCCESS;
1206}
1207
1208
1209/** @callback_method_impl{FNCPUMRDMSR} */
1210static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr0Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1211{
1212 *puValue = 0;
1213 return VINF_SUCCESS;
1214}
1215
1216
1217/** @callback_method_impl{FNCPUMRDMSR} */
1218static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed0(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1219{
1220 *puValue = 0;
1221 return VINF_SUCCESS;
1222}
1223
1224
1225/** @callback_method_impl{FNCPUMRDMSR} */
1226static DECLCALLBACK(int) cpumMsrRd_Ia32VmxCr4Fixed1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1227{
1228 *puValue = 0;
1229 return VINF_SUCCESS;
1230}
1231
1232
1233/** @callback_method_impl{FNCPUMRDMSR} */
1234static DECLCALLBACK(int) cpumMsrRd_Ia32VmxVmcsEnum(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1235{
1236 *puValue = 0;
1237 return VINF_SUCCESS;
1238}
1239
1240
1241/** @callback_method_impl{FNCPUMRDMSR} */
1242static DECLCALLBACK(int) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1243{
1244 *puValue = 0;
1245 return VINF_SUCCESS;
1246}
1247
1248
1249/** @callback_method_impl{FNCPUMRDMSR} */
1250static DECLCALLBACK(int) cpumMsrRd_Ia32VmxEptVpidCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1251{
1252 *puValue = 0;
1253 return VINF_SUCCESS;
1254}
1255
1256
1257/** @callback_method_impl{FNCPUMRDMSR} */
1258static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTruePinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1259{
1260 *puValue = 0;
1261 return VINF_SUCCESS;
1262}
1263
1264
1265/** @callback_method_impl{FNCPUMRDMSR} */
1266static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1267{
1268 *puValue = 0;
1269 return VINF_SUCCESS;
1270}
1271
1272
1273/** @callback_method_impl{FNCPUMRDMSR} */
1274static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1275{
1276 *puValue = 0;
1277 return VINF_SUCCESS;
1278}
1279
1280
1281/** @callback_method_impl{FNCPUMRDMSR} */
1282static DECLCALLBACK(int) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1283{
1284 *puValue = 0;
1285 return VINF_SUCCESS;
1286}
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297/*
1298 * AMD64
1299 * AMD64
1300 * AMD64
1301 */
1302
1303
1304/** @callback_method_impl{FNCPUMRDMSR} */
1305static DECLCALLBACK(int) cpumMsrRd_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1306{
1307 *puValue = pVCpu->cpum.s.Guest.msrEFER;
1308 return VINF_SUCCESS;
1309}
1310
1311
1312/** @callback_method_impl{FNCPUMWRMSR} */
1313static DECLCALLBACK(int) cpumMsrWr_Amd64Efer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1314{
1315 PVM pVM = pVCpu->CTX_SUFF(pVM);
1316 uint64_t const uOldEfer = pVCpu->cpum.s.Guest.msrEFER;
1317 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1318 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1319 : 0;
1320 uint64_t fMask = 0;
1321
1322 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1323 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1324 fMask |= MSR_K6_EFER_NXE;
1325 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1326 fMask |= MSR_K6_EFER_LME;
1327 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1328 fMask |= MSR_K6_EFER_SCE;
1329 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1330 fMask |= MSR_K6_EFER_FFXSR;
1331
1332 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1333 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1334 if ( (uOldEfer & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1335 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1336 {
1337 Log(("CPUM: Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1338 return VERR_CPUM_RAISE_GP_0;
1339 }
1340
1341 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1342 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1343 ("Unexpected value %RX64\n", uValue));
1344 pVCpu->cpum.s.Guest.msrEFER = (uOldEfer & ~fMask) | (uValue & fMask);
1345
1346 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1347 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1348 if ( (uOldEfer & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1349 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1350 {
1351 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1352 HMFlushTLB(pVCpu);
1353
1354 /* Notify PGM about NXE changes. */
1355 if ( (uOldEfer & MSR_K6_EFER_NXE)
1356 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1357 PGMNotifyNxeChanged(pVCpu, !(uOldEfer & MSR_K6_EFER_NXE));
1358 }
1359 return VINF_SUCCESS;
1360}
1361
1362
1363/** @callback_method_impl{FNCPUMRDMSR} */
1364static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1365{
1366 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
1367 return VINF_SUCCESS;
1368}
1369
1370
1371/** @callback_method_impl{FNCPUMWRMSR} */
1372static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1373{
1374 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1375 return VINF_SUCCESS;
1376}
1377
1378
1379/** @callback_method_impl{FNCPUMRDMSR} */
1380static DECLCALLBACK(int) cpumMsrRd_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1381{
1382 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
1383 return VINF_SUCCESS;
1384}
1385
1386
1387/** @callback_method_impl{FNCPUMWRMSR} */
1388static DECLCALLBACK(int) cpumMsrWr_Amd64LongSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1389{
1390 if (!X86_IS_CANONICAL(uValue))
1391 {
1392 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1393 return VERR_CPUM_RAISE_GP_0;
1394 }
1395 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1396 return VINF_SUCCESS;
1397}
1398
1399
1400/** @callback_method_impl{FNCPUMRDMSR} */
1401static DECLCALLBACK(int) cpumMsrRd_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1402{
1403 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
1404 return VINF_SUCCESS;
1405}
1406
1407
1408/** @callback_method_impl{FNCPUMWRMSR} */
1409static DECLCALLBACK(int) cpumMsrWr_Amd64CompSyscallTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1410{
1411 if (!X86_IS_CANONICAL(uValue))
1412 {
1413 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1414 return VERR_CPUM_RAISE_GP_0;
1415 }
1416 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1417 return VINF_SUCCESS;
1418}
1419
1420
1421/** @callback_method_impl{FNCPUMRDMSR} */
1422static DECLCALLBACK(int) cpumMsrRd_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1423{
1424 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
1425 return VINF_SUCCESS;
1426}
1427
1428
1429/** @callback_method_impl{FNCPUMWRMSR} */
1430static DECLCALLBACK(int) cpumMsrWr_Amd64SyscallFlagMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1431{
1432 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1433 return VINF_SUCCESS;
1434}
1435
1436
1437/** @callback_method_impl{FNCPUMRDMSR} */
1438static DECLCALLBACK(int) cpumMsrRd_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1439{
1440 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
1441 return VINF_SUCCESS;
1442}
1443
1444
1445/** @callback_method_impl{FNCPUMWRMSR} */
1446static DECLCALLBACK(int) cpumMsrWr_Amd64FsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1447{
1448 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1449 return VINF_SUCCESS;
1450}
1451
1452
1453/** @callback_method_impl{FNCPUMRDMSR} */
1454static DECLCALLBACK(int) cpumMsrRd_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1455{
1456 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
1457 return VINF_SUCCESS;
1458}
1459
1460/** @callback_method_impl{FNCPUMWRMSR} */
1461static DECLCALLBACK(int) cpumMsrWr_Amd64GsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1462{
1463 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1464 return VINF_SUCCESS;
1465}
1466
1467
1468
1469/** @callback_method_impl{FNCPUMRDMSR} */
1470static DECLCALLBACK(int) cpumMsrRd_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1471{
1472 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
1473 return VINF_SUCCESS;
1474}
1475
1476/** @callback_method_impl{FNCPUMWRMSR} */
1477static DECLCALLBACK(int) cpumMsrWr_Amd64KernelGsBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1478{
1479 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1480 return VINF_SUCCESS;
1481}
1482
1483
1484/** @callback_method_impl{FNCPUMRDMSR} */
1485static DECLCALLBACK(int) cpumMsrRd_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1486{
1487 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
1488 return VINF_SUCCESS;
1489}
1490
1491/** @callback_method_impl{FNCPUMWRMSR} */
1492static DECLCALLBACK(int) cpumMsrWr_Amd64TscAux(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1493{
1494 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1495 return VINF_SUCCESS;
1496}
1497
1498
1499/*
1500 * Intel specific
1501 * Intel specific
1502 * Intel specific
1503 */
1504
1505/** @callback_method_impl{FNCPUMRDMSR} */
1506static DECLCALLBACK(int) cpumMsrRd_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1507{
1508 /** @todo recalc clock frequency ratio? */
1509 *puValue = pRange->uValue;
1510 return VINF_SUCCESS;
1511}
1512
1513
1514/** @callback_method_impl{FNCPUMWRMSR} */
1515static DECLCALLBACK(int) cpumMsrWr_IntelEblCrPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1516{
1517 /** @todo Write EBL_CR_POWERON: Remember written bits. */
1518 return VINF_SUCCESS;
1519}
1520
1521
1522/** @callback_method_impl{FNCPUMRDMSR} */
1523static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreThreadCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1524{
1525 /* Note! According to cpuid_set_info in XNU (10.7.0), Westmere CPU only
1526 have a 4-bit core count. */
1527 uint16_t cCores = pVCpu->CTX_SUFF(pVM)->cCpus;
1528 uint16_t cThreads = cCores; /** @todo hyper-threading. */
1529 *puValue = RT_MAKE_U32(cThreads, cCores);
1530 return VINF_SUCCESS;
1531}
1532
1533
1534/** @callback_method_impl{FNCPUMRDMSR} */
1535static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1536{
1537 /** @todo P4 hard power on config */
1538 *puValue = pRange->uValue;
1539 return VINF_SUCCESS;
1540}
1541
1542
1543/** @callback_method_impl{FNCPUMWRMSR} */
1544static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcHardPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1545{
1546 /** @todo P4 hard power on config */
1547 return VINF_SUCCESS;
1548}
1549
1550
1551/** @callback_method_impl{FNCPUMRDMSR} */
1552static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1553{
1554 /** @todo P4 soft power on config */
1555 *puValue = pRange->uValue;
1556 return VINF_SUCCESS;
1557}
1558
1559
1560/** @callback_method_impl{FNCPUMWRMSR} */
1561static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcSoftPowerOn(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1562{
1563 /** @todo P4 soft power on config */
1564 return VINF_SUCCESS;
1565}
1566
1567
1568/** @callback_method_impl{FNCPUMRDMSR} */
1569static DECLCALLBACK(int) cpumMsrRd_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1570{
1571 uint64_t uValue;
1572 PVM pVM = pVCpu->CTX_SUFF(pVM);
1573 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1574 if (pVM->cpum.s.GuestFeatures.uModel >= 2)
1575 {
1576 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ && pVM->cpum.s.GuestFeatures.uModel <= 2)
1577 {
1578 uScalableBusHz = CPUM_SBUSFREQ_100MHZ;
1579 uValue = 0;
1580 }
1581 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1582 {
1583 uScalableBusHz = CPUM_SBUSFREQ_133MHZ;
1584 uValue = 1;
1585 }
1586 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1587 {
1588 uScalableBusHz = CPUM_SBUSFREQ_167MHZ;
1589 uValue = 3;
1590 }
1591 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1592 {
1593 uScalableBusHz = CPUM_SBUSFREQ_200MHZ;
1594 uValue = 2;
1595 }
1596 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ && pVM->cpum.s.GuestFeatures.uModel > 2)
1597 {
1598 uScalableBusHz = CPUM_SBUSFREQ_267MHZ;
1599 uValue = 0;
1600 }
1601 else
1602 {
1603 uScalableBusHz = CPUM_SBUSFREQ_333MHZ;
1604 uValue = 6;
1605 }
1606 uValue <<= 16;
1607
1608 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1609 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1610 uValue |= (uint32_t)uTscRatio << 24;
1611
1612 uValue |= pRange->uValue & ~UINT64_C(0xff0f0000);
1613 }
1614 else
1615 {
1616 /* Probably more stuff here, but intel doesn't want to tell us. */
1617 uValue = pRange->uValue;
1618 uValue &= ~(RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23)); /* 100 MHz is only documented value */
1619 }
1620
1621 *puValue = uValue;
1622 return VINF_SUCCESS;
1623}
1624
1625
1626/** @callback_method_impl{FNCPUMWRMSR} */
1627static DECLCALLBACK(int) cpumMsrWr_IntelP4EbcFrequencyId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1628{
1629 /** @todo P4 bus frequency config */
1630 return VINF_SUCCESS;
1631}
1632
1633
1634/** @callback_method_impl{FNCPUMRDMSR} */
1635static DECLCALLBACK(int) cpumMsrRd_IntelP6FsbFrequency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1636{
1637 /* Convert the scalable bus frequency to the encoding in the intel manual (for core+). */
1638 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVCpu->CTX_SUFF(pVM));
1639 if (uScalableBusHz <= CPUM_SBUSFREQ_100MHZ)
1640 *puValue = 5;
1641 else if (uScalableBusHz <= CPUM_SBUSFREQ_133MHZ)
1642 *puValue = 1;
1643 else if (uScalableBusHz <= CPUM_SBUSFREQ_167MHZ)
1644 *puValue = 3;
1645 else if (uScalableBusHz <= CPUM_SBUSFREQ_200MHZ)
1646 *puValue = 2;
1647 else if (uScalableBusHz <= CPUM_SBUSFREQ_267MHZ)
1648 *puValue = 0;
1649 else if (uScalableBusHz <= CPUM_SBUSFREQ_333MHZ)
1650 *puValue = 4;
1651 else /*if (uScalableBusHz <= CPUM_SBUSFREQ_400MHZ)*/
1652 *puValue = 6;
1653
1654 *puValue |= pRange->uValue & ~UINT64_C(0x7);
1655
1656 return VINF_SUCCESS;
1657}
1658
1659
1660/** @callback_method_impl{FNCPUMRDMSR} */
1661static DECLCALLBACK(int) cpumMsrRd_IntelPlatformInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1662{
1663 /* Just indicate a fixed TSC, no turbo boost, no programmable anything. */
1664 PVM pVM = pVCpu->CTX_SUFF(pVM);
1665 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1666 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1667 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1668 uint64_t uValue = ((uint32_t)uTscRatio << 8) /* TSC invariant frequency. */
1669 | ((uint64_t)uTscRatio << 40); /* The max turbo frequency. */
1670
1671 /* Ivy bridge has a minimum operating ratio as well. */
1672 if (true) /** @todo detect sandy bridge. */
1673 uValue |= (uint64_t)uTscRatio << 48;
1674
1675 *puValue = uValue;
1676 return VINF_SUCCESS;
1677}
1678
1679
1680/** @callback_method_impl{FNCPUMRDMSR} */
1681static DECLCALLBACK(int) cpumMsrRd_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1682{
1683 uint64_t uValue = pRange->uValue & ~UINT64_C(0x1ff00);
1684
1685 PVM pVM = pVCpu->CTX_SUFF(pVM);
1686 uint64_t uScalableBusHz = CPUMGetGuestScalableBusFrequency(pVM);
1687 uint64_t uTscHz = TMCpuTicksPerSecond(pVM);
1688 uint8_t uTscRatio = (uint8_t)((uTscHz + uScalableBusHz / 2) / uScalableBusHz);
1689 uValue |= (uint32_t)uTscRatio << 8;
1690
1691 *puValue = uValue;
1692 return VINF_SUCCESS;
1693}
1694
1695
1696/** @callback_method_impl{FNCPUMWRMSR} */
1697static DECLCALLBACK(int) cpumMsrWr_IntelFlexRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1698{
1699 /** @todo implement writing MSR_FLEX_RATIO. */
1700 return VINF_SUCCESS;
1701}
1702
1703
1704/** @callback_method_impl{FNCPUMRDMSR} */
1705static DECLCALLBACK(int) cpumMsrRd_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1706{
1707 *puValue = pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl;
1708 return VINF_SUCCESS;
1709}
1710
1711
1712/** @callback_method_impl{FNCPUMWRMSR} */
1713static DECLCALLBACK(int) cpumMsrWr_IntelPkgCStConfigControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1714{
1715 if (pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl & RT_BIT_64(15))
1716 {
1717 Log(("CPUM: WRMDR %#x (%s), %#llx: Write protected -> #GP\n", idMsr, pRange->szName, uValue));
1718 return VERR_CPUM_RAISE_GP_0;
1719 }
1720#if 0 /** @todo check what real (old) hardware does. */
1721 if ((uValue & 7) >= 5)
1722 {
1723 Log(("CPUM: WRMDR %#x (%s), %#llx: Invalid limit (%d) -> #GP\n", idMsr, pRange->szName, uValue, (uint32_t)(uValue & 7)));
1724 return VERR_CPUM_RAISE_GP_0;
1725 }
1726#endif
1727 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = uValue;
1728 return VINF_SUCCESS;
1729}
1730
1731
1732/** @callback_method_impl{FNCPUMRDMSR} */
1733static DECLCALLBACK(int) cpumMsrRd_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1734{
1735 /** @todo implement I/O mwait wakeup. */
1736 *puValue = 0;
1737 return VINF_SUCCESS;
1738}
1739
1740
1741/** @callback_method_impl{FNCPUMWRMSR} */
1742static DECLCALLBACK(int) cpumMsrWr_IntelPmgIoCaptureBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1743{
1744 /** @todo implement I/O mwait wakeup. */
1745 return VINF_SUCCESS;
1746}
1747
1748
1749/** @callback_method_impl{FNCPUMRDMSR} */
1750static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1751{
1752 /** @todo implement last branch records. */
1753 *puValue = 0;
1754 return VINF_SUCCESS;
1755}
1756
1757
1758/** @callback_method_impl{FNCPUMWRMSR} */
1759static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1760{
1761 /** @todo implement last branch records. */
1762 return VINF_SUCCESS;
1763}
1764
1765
1766/** @callback_method_impl{FNCPUMRDMSR} */
1767static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1768{
1769 /** @todo implement last branch records. */
1770 *puValue = 0;
1771 return VINF_SUCCESS;
1772}
1773
1774
1775/** @callback_method_impl{FNCPUMWRMSR} */
1776static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchFromN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1777{
1778 /** @todo implement last branch records. */
1779 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1780 * if the rest of the bits are zero. Automatic sign extending?
1781 * Investigate! */
1782 if (!X86_IS_CANONICAL(uValue))
1783 {
1784 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1785 return VERR_CPUM_RAISE_GP_0;
1786 }
1787 return VINF_SUCCESS;
1788}
1789
1790
1791/** @callback_method_impl{FNCPUMRDMSR} */
1792static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1793{
1794 /** @todo implement last branch records. */
1795 *puValue = 0;
1796 return VINF_SUCCESS;
1797}
1798
1799
1800/** @callback_method_impl{FNCPUMWRMSR} */
1801static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchToN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1802{
1803 /** @todo implement last branch records. */
1804 /** @todo Probing indicates that bit 63 is settable on SandyBridge, at least
1805 * if the rest of the bits are zero. Automatic sign extending?
1806 * Investigate! */
1807 if (!X86_IS_CANONICAL(uValue))
1808 {
1809 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
1810 return VERR_CPUM_RAISE_GP_0;
1811 }
1812 return VINF_SUCCESS;
1813}
1814
1815
1816/** @callback_method_impl{FNCPUMRDMSR} */
1817static DECLCALLBACK(int) cpumMsrRd_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1818{
1819 /** @todo implement last branch records. */
1820 *puValue = 0;
1821 return VINF_SUCCESS;
1822}
1823
1824
1825/** @callback_method_impl{FNCPUMWRMSR} */
1826static DECLCALLBACK(int) cpumMsrWr_IntelLastBranchTos(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1827{
1828 /** @todo implement last branch records. */
1829 return VINF_SUCCESS;
1830}
1831
1832
1833/** @callback_method_impl{FNCPUMRDMSR} */
1834static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1835{
1836 *puValue = pRange->uValue;
1837 return VINF_SUCCESS;
1838}
1839
1840
1841/** @callback_method_impl{FNCPUMWRMSR} */
1842static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1843{
1844 return VINF_SUCCESS;
1845}
1846
1847
1848/** @callback_method_impl{FNCPUMRDMSR} */
1849static DECLCALLBACK(int) cpumMsrRd_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1850{
1851 *puValue = pRange->uValue;
1852 return VINF_SUCCESS;
1853}
1854
1855
1856/** @callback_method_impl{FNCPUMWRMSR} */
1857static DECLCALLBACK(int) cpumMsrWr_IntelBblCrCtl3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1858{
1859 return VINF_SUCCESS;
1860}
1861
1862
1863/** @callback_method_impl{FNCPUMRDMSR} */
1864static DECLCALLBACK(int) cpumMsrRd_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1865{
1866 *puValue = pRange->uValue;
1867 return VINF_SUCCESS;
1868}
1869
1870
1871/** @callback_method_impl{FNCPUMWRMSR} */
1872static DECLCALLBACK(int) cpumMsrWr_IntelI7TemperatureTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1873{
1874 return VINF_SUCCESS;
1875}
1876
1877
1878/** @callback_method_impl{FNCPUMRDMSR} */
1879static DECLCALLBACK(int) cpumMsrRd_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1880{
1881 /** @todo machine check. */
1882 *puValue = pRange->uValue;
1883 return VINF_SUCCESS;
1884}
1885
1886
1887/** @callback_method_impl{FNCPUMWRMSR} */
1888static DECLCALLBACK(int) cpumMsrWr_IntelI7MsrOffCoreResponseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1889{
1890 /** @todo machine check. */
1891 return VINF_SUCCESS;
1892}
1893
1894
1895/** @callback_method_impl{FNCPUMRDMSR} */
1896static DECLCALLBACK(int) cpumMsrRd_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1897{
1898 *puValue = 0;
1899 return VINF_SUCCESS;
1900}
1901
1902
1903/** @callback_method_impl{FNCPUMWRMSR} */
1904static DECLCALLBACK(int) cpumMsrWr_IntelI7MiscPwrMgmt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1905{
1906 return VINF_SUCCESS;
1907}
1908
1909
1910/** @callback_method_impl{FNCPUMRDMSR} */
1911static DECLCALLBACK(int) cpumMsrRd_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1912{
1913 int rc = CPUMGetGuestCRx(pVCpu, pRange->uValue, puValue);
1914 AssertRC(rc);
1915 return VINF_SUCCESS;
1916}
1917
1918
1919/** @callback_method_impl{FNCPUMWRMSR} */
1920static DECLCALLBACK(int) cpumMsrWr_IntelP6CrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1921{
1922 /* This CRx interface differs from the MOV CRx, GReg interface in that
1923 #GP(0) isn't raised if unsupported bits are written to. Instead they
1924 are simply ignored and masked off. (Pentium M Dothan) */
1925 /** @todo Implement MSR_P6_CRx writing. Too much effort for very little, if
1926 * any, gain. */
1927 return VINF_SUCCESS;
1928}
1929
1930
1931/** @callback_method_impl{FNCPUMRDMSR} */
1932static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1933{
1934 /** @todo implement CPUID masking. */
1935 *puValue = UINT64_MAX;
1936 return VINF_SUCCESS;
1937}
1938
1939
1940/** @callback_method_impl{FNCPUMWRMSR} */
1941static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1942{
1943 /** @todo implement CPUID masking. */
1944 return VINF_SUCCESS;
1945}
1946
1947
1948/** @callback_method_impl{FNCPUMRDMSR} */
1949static DECLCALLBACK(int) cpumMsrRd_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1950{
1951 /** @todo implement CPUID masking. */
1952 return VINF_SUCCESS;
1953}
1954
1955
1956/** @callback_method_impl{FNCPUMWRMSR} */
1957static DECLCALLBACK(int) cpumMsrWr_IntelCpuId1FeatureMaskEax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1958{
1959 /** @todo implement CPUID masking. */
1960 return VINF_SUCCESS;
1961}
1962
1963
1964
1965/** @callback_method_impl{FNCPUMRDMSR} */
1966static DECLCALLBACK(int) cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1967{
1968 /** @todo implement CPUID masking. */
1969 *puValue = UINT64_MAX;
1970 return VINF_SUCCESS;
1971}
1972
1973
1974/** @callback_method_impl{FNCPUMWRMSR} */
1975static DECLCALLBACK(int) cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1976{
1977 /** @todo implement CPUID masking. */
1978 return VINF_SUCCESS;
1979}
1980
1981
1982
1983/** @callback_method_impl{FNCPUMRDMSR} */
1984static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
1985{
1986 /** @todo implement AES-NI. */
1987 *puValue = 3; /* Bit 0 is lock bit, bit 1 disables AES-NI. That's what they say. */
1988 return VINF_SUCCESS;
1989}
1990
1991
1992/** @callback_method_impl{FNCPUMWRMSR} */
1993static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyAesNiCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
1994{
1995 /** @todo implement AES-NI. */
1996 return VERR_CPUM_RAISE_GP_0;
1997}
1998
1999
2000/** @callback_method_impl{FNCPUMRDMSR} */
2001static DECLCALLBACK(int) cpumMsrRd_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2002{
2003 /** @todo implement intel C states. */
2004 *puValue = pRange->uValue;
2005 return VINF_SUCCESS;
2006}
2007
2008
2009/** @callback_method_impl{FNCPUMWRMSR} */
2010static DECLCALLBACK(int) cpumMsrWr_IntelI7TurboRatioLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2011{
2012 /** @todo implement intel C states. */
2013 return VINF_SUCCESS;
2014}
2015
2016
2017/** @callback_method_impl{FNCPUMRDMSR} */
2018static DECLCALLBACK(int) cpumMsrRd_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2019{
2020 /** @todo implement last-branch-records. */
2021 *puValue = 0;
2022 return VINF_SUCCESS;
2023}
2024
2025
2026/** @callback_method_impl{FNCPUMWRMSR} */
2027static DECLCALLBACK(int) cpumMsrWr_IntelI7LbrSelect(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2028{
2029 /** @todo implement last-branch-records. */
2030 return VINF_SUCCESS;
2031}
2032
2033
2034/** @callback_method_impl{FNCPUMRDMSR} */
2035static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2036{
2037 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2038 *puValue = 0;
2039 return VINF_SUCCESS;
2040}
2041
2042
2043/** @callback_method_impl{FNCPUMWRMSR} */
2044static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyErrorControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2045{
2046 /** @todo implement memory error injection (MSR_ERROR_CONTROL). */
2047 return VINF_SUCCESS;
2048}
2049
2050
2051/** @callback_method_impl{FNCPUMRDMSR} */
2052static DECLCALLBACK(int) cpumMsrRd_IntelI7VirtualLegacyWireCap(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2053{
2054 /** @todo implement memory VLW? */
2055 *puValue = pRange->uValue;
2056 /* Note: A20M is known to be bit 1 as this was disclosed in spec update
2057 AAJ49/AAK51/????, which documents the inversion of this bit. The
2058 Sandy bridge CPU here has value 0x74, so it probably doesn't have a BIOS
2059 that correct things. Some guesses at the other bits:
2060 bit 2 = INTR
2061 bit 4 = SMI
2062 bit 5 = INIT
2063 bit 6 = NMI */
2064 return VINF_SUCCESS;
2065}
2066
2067
2068/** @callback_method_impl{FNCPUMRDMSR} */
2069static DECLCALLBACK(int) cpumMsrRd_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2070{
2071 /** @todo intel power management */
2072 *puValue = 0;
2073 return VINF_SUCCESS;
2074}
2075
2076
2077/** @callback_method_impl{FNCPUMWRMSR} */
2078static DECLCALLBACK(int) cpumMsrWr_IntelI7PowerCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2079{
2080 /** @todo intel power management */
2081 return VINF_SUCCESS;
2082}
2083
2084
2085/** @callback_method_impl{FNCPUMRDMSR} */
2086static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2087{
2088 /** @todo intel performance counters. */
2089 *puValue = 0;
2090 return VINF_SUCCESS;
2091}
2092
2093
2094/** @callback_method_impl{FNCPUMWRMSR} */
2095static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPebsNumAlt(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2096{
2097 /** @todo intel performance counters. */
2098 return VINF_SUCCESS;
2099}
2100
2101
2102/** @callback_method_impl{FNCPUMRDMSR} */
2103static DECLCALLBACK(int) cpumMsrRd_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2104{
2105 /** @todo intel performance counters. */
2106 *puValue = 0;
2107 return VINF_SUCCESS;
2108}
2109
2110
2111/** @callback_method_impl{FNCPUMWRMSR} */
2112static DECLCALLBACK(int) cpumMsrWr_IntelI7PebsLdLat(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2113{
2114 /** @todo intel performance counters. */
2115 return VINF_SUCCESS;
2116}
2117
2118
2119/** @callback_method_impl{FNCPUMRDMSR} */
2120static DECLCALLBACK(int) cpumMsrRd_IntelI7PkgCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2121{
2122 /** @todo intel power management. */
2123 *puValue = 0;
2124 return VINF_SUCCESS;
2125}
2126
2127
2128/** @callback_method_impl{FNCPUMRDMSR} */
2129static DECLCALLBACK(int) cpumMsrRd_IntelI7CoreCnResidencyN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2130{
2131 /** @todo intel power management. */
2132 *puValue = 0;
2133 return VINF_SUCCESS;
2134}
2135
2136
2137/** @callback_method_impl{FNCPUMRDMSR} */
2138static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2139{
2140 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2141 *puValue = 0;
2142 return VINF_SUCCESS;
2143}
2144
2145
2146/** @callback_method_impl{FNCPUMWRMSR} */
2147static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrCurrentConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2148{
2149 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2150 return VINF_SUCCESS;
2151}
2152
2153
2154/** @callback_method_impl{FNCPUMRDMSR} */
2155static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2156{
2157 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2158 *puValue = 0;
2159 return VINF_SUCCESS;
2160}
2161
2162
2163/** @callback_method_impl{FNCPUMWRMSR} */
2164static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyVrMiscConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2165{
2166 /** @todo Figure out what MSR_VR_CURRENT_CONFIG & MSR_VR_MISC_CONFIG are. */
2167 return VINF_SUCCESS;
2168}
2169
2170
2171/** @callback_method_impl{FNCPUMRDMSR} */
2172static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2173{
2174 /** @todo intel RAPL. */
2175 *puValue = pRange->uValue;
2176 return VINF_SUCCESS;
2177}
2178
2179
2180/** @callback_method_impl{FNCPUMRDMSR} */
2181static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2182{
2183 /** @todo intel power management. */
2184 *puValue = 0;
2185 return VINF_SUCCESS;
2186}
2187
2188
2189/** @callback_method_impl{FNCPUMWRMSR} */
2190static DECLCALLBACK(int) cpumMsrWr_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2191{
2192 /** @todo intel power management. */
2193 return VINF_SUCCESS;
2194}
2195
2196
2197/** @callback_method_impl{FNCPUMRDMSR} */
2198static DECLCALLBACK(int) cpumMsrRd_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2199{
2200 /** @todo intel power management. */
2201 *puValue = 0;
2202 return VINF_SUCCESS;
2203}
2204
2205
2206/** @callback_method_impl{FNCPUMRDMSR} */
2207static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2208{
2209 /** @todo intel RAPL. */
2210 *puValue = 0;
2211 return VINF_SUCCESS;
2212}
2213
2214
2215/** @callback_method_impl{FNCPUMWRMSR} */
2216static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPkgPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2217{
2218 /** @todo intel RAPL. */
2219 return VINF_SUCCESS;
2220}
2221
2222
2223/** @callback_method_impl{FNCPUMRDMSR} */
2224static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2225{
2226 /** @todo intel power management. */
2227 *puValue = 0;
2228 return VINF_SUCCESS;
2229}
2230
2231
2232/** @callback_method_impl{FNCPUMRDMSR} */
2233static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2234{
2235 /** @todo intel power management. */
2236 *puValue = 0;
2237 return VINF_SUCCESS;
2238}
2239
2240
2241/** @callback_method_impl{FNCPUMRDMSR} */
2242static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPkgPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2243{
2244 /** @todo intel power management. */
2245 *puValue = 0;
2246 return VINF_SUCCESS;
2247}
2248
2249
2250/** @callback_method_impl{FNCPUMRDMSR} */
2251static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2252{
2253 /** @todo intel RAPL. */
2254 *puValue = 0;
2255 return VINF_SUCCESS;
2256}
2257
2258
2259/** @callback_method_impl{FNCPUMWRMSR} */
2260static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplDramPowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2261{
2262 /** @todo intel RAPL. */
2263 return VINF_SUCCESS;
2264}
2265
2266
2267/** @callback_method_impl{FNCPUMRDMSR} */
2268static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramEnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2269{
2270 /** @todo intel power management. */
2271 *puValue = 0;
2272 return VINF_SUCCESS;
2273}
2274
2275
2276/** @callback_method_impl{FNCPUMRDMSR} */
2277static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2278{
2279 /** @todo intel power management. */
2280 *puValue = 0;
2281 return VINF_SUCCESS;
2282}
2283
2284
2285/** @callback_method_impl{FNCPUMRDMSR} */
2286static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplDramPowerInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2287{
2288 /** @todo intel power management. */
2289 *puValue = 0;
2290 return VINF_SUCCESS;
2291}
2292
2293
2294/** @callback_method_impl{FNCPUMRDMSR} */
2295static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2296{
2297 /** @todo intel RAPL. */
2298 *puValue = 0;
2299 return VINF_SUCCESS;
2300}
2301
2302
2303/** @callback_method_impl{FNCPUMWRMSR} */
2304static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2305{
2306 /** @todo intel RAPL. */
2307 return VINF_SUCCESS;
2308}
2309
2310
2311/** @callback_method_impl{FNCPUMRDMSR} */
2312static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2313{
2314 /** @todo intel power management. */
2315 *puValue = 0;
2316 return VINF_SUCCESS;
2317}
2318
2319
2320/** @callback_method_impl{FNCPUMRDMSR} */
2321static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2322{
2323 /** @todo intel RAPL. */
2324 *puValue = 0;
2325 return VINF_SUCCESS;
2326}
2327
2328
2329/** @callback_method_impl{FNCPUMWRMSR} */
2330static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp0Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2331{
2332 /** @todo intel RAPL. */
2333 return VINF_SUCCESS;
2334}
2335
2336
2337/** @callback_method_impl{FNCPUMRDMSR} */
2338static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp0PerfStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2339{
2340 /** @todo intel power management. */
2341 *puValue = 0;
2342 return VINF_SUCCESS;
2343}
2344
2345
2346/** @callback_method_impl{FNCPUMRDMSR} */
2347static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2348{
2349 /** @todo intel RAPL. */
2350 *puValue = 0;
2351 return VINF_SUCCESS;
2352}
2353
2354
2355/** @callback_method_impl{FNCPUMWRMSR} */
2356static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1PowerLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2357{
2358 /** @todo intel RAPL. */
2359 return VINF_SUCCESS;
2360}
2361
2362
2363/** @callback_method_impl{FNCPUMRDMSR} */
2364static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1EnergyStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2365{
2366 /** @todo intel power management. */
2367 *puValue = 0;
2368 return VINF_SUCCESS;
2369}
2370
2371
2372/** @callback_method_impl{FNCPUMRDMSR} */
2373static DECLCALLBACK(int) cpumMsrRd_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2374{
2375 /** @todo intel RAPL. */
2376 *puValue = 0;
2377 return VINF_SUCCESS;
2378}
2379
2380
2381/** @callback_method_impl{FNCPUMWRMSR} */
2382static DECLCALLBACK(int) cpumMsrWr_IntelI7RaplPp1Policy(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2383{
2384 /** @todo intel RAPL. */
2385 return VINF_SUCCESS;
2386}
2387
2388
2389/** @callback_method_impl{FNCPUMRDMSR} */
2390static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpNominal(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2391{
2392 /** @todo intel power management. */
2393 *puValue = pRange->uValue;
2394 return VINF_SUCCESS;
2395}
2396
2397
2398/** @callback_method_impl{FNCPUMRDMSR} */
2399static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2400{
2401 /** @todo intel power management. */
2402 *puValue = pRange->uValue;
2403 return VINF_SUCCESS;
2404}
2405
2406
2407/** @callback_method_impl{FNCPUMRDMSR} */
2408static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpLevel2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2409{
2410 /** @todo intel power management. */
2411 *puValue = pRange->uValue;
2412 return VINF_SUCCESS;
2413}
2414
2415
2416/** @callback_method_impl{FNCPUMRDMSR} */
2417static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2418{
2419 /** @todo intel power management. */
2420 *puValue = 0;
2421 return VINF_SUCCESS;
2422}
2423
2424
2425/** @callback_method_impl{FNCPUMWRMSR} */
2426static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyConfigTdpControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2427{
2428 /** @todo intel power management. */
2429 return VINF_SUCCESS;
2430}
2431
2432
2433/** @callback_method_impl{FNCPUMRDMSR} */
2434static DECLCALLBACK(int) cpumMsrRd_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2435{
2436 /** @todo intel power management. */
2437 *puValue = 0;
2438 return VINF_SUCCESS;
2439}
2440
2441
2442/** @callback_method_impl{FNCPUMWRMSR} */
2443static DECLCALLBACK(int) cpumMsrWr_IntelI7IvyTurboActivationRatio(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2444{
2445 /** @todo intel power management. */
2446 return VINF_SUCCESS;
2447}
2448
2449
2450/** @callback_method_impl{FNCPUMRDMSR} */
2451static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2452{
2453 /** @todo uncore msrs. */
2454 *puValue = 0;
2455 return VINF_SUCCESS;
2456}
2457
2458
2459/** @callback_method_impl{FNCPUMWRMSR} */
2460static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2461{
2462 /** @todo uncore msrs. */
2463 return VINF_SUCCESS;
2464}
2465
2466
2467/** @callback_method_impl{FNCPUMRDMSR} */
2468static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2469{
2470 /** @todo uncore msrs. */
2471 *puValue = 0;
2472 return VINF_SUCCESS;
2473}
2474
2475
2476/** @callback_method_impl{FNCPUMWRMSR} */
2477static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2478{
2479 /** @todo uncore msrs. */
2480 return VINF_SUCCESS;
2481}
2482
2483
2484/** @callback_method_impl{FNCPUMRDMSR} */
2485static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2486{
2487 /** @todo uncore msrs. */
2488 *puValue = 0;
2489 return VINF_SUCCESS;
2490}
2491
2492
2493/** @callback_method_impl{FNCPUMWRMSR} */
2494static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2495{
2496 /** @todo uncore msrs. */
2497 return VINF_SUCCESS;
2498}
2499
2500
2501/** @callback_method_impl{FNCPUMRDMSR} */
2502static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2503{
2504 /** @todo uncore msrs. */
2505 *puValue = 0;
2506 return VINF_SUCCESS;
2507}
2508
2509
2510/** @callback_method_impl{FNCPUMWRMSR} */
2511static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtrCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2512{
2513 /** @todo uncore msrs. */
2514 return VINF_SUCCESS;
2515}
2516
2517
2518/** @callback_method_impl{FNCPUMRDMSR} */
2519static DECLCALLBACK(int) cpumMsrRd_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2520{
2521 /** @todo uncore msrs. */
2522 *puValue = 0;
2523 return VINF_SUCCESS;
2524}
2525
2526
2527/** @callback_method_impl{FNCPUMWRMSR} */
2528static DECLCALLBACK(int) cpumMsrWr_IntelI7UncPerfFixedCtr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2529{
2530 /** @todo uncore msrs. */
2531 return VINF_SUCCESS;
2532}
2533
2534
2535/** @callback_method_impl{FNCPUMRDMSR} */
2536static DECLCALLBACK(int) cpumMsrRd_IntelI7UncCBoxConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2537{
2538 /** @todo uncore msrs. */
2539 *puValue = 0;
2540 return VINF_SUCCESS;
2541}
2542
2543
2544/** @callback_method_impl{FNCPUMRDMSR} */
2545static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2546{
2547 /** @todo uncore msrs. */
2548 *puValue = 0;
2549 return VINF_SUCCESS;
2550}
2551
2552
2553/** @callback_method_impl{FNCPUMWRMSR} */
2554static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2555{
2556 /** @todo uncore msrs. */
2557 return VINF_SUCCESS;
2558}
2559
2560
2561/** @callback_method_impl{FNCPUMRDMSR} */
2562static DECLCALLBACK(int) cpumMsrRd_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2563{
2564 /** @todo uncore msrs. */
2565 *puValue = 0;
2566 return VINF_SUCCESS;
2567}
2568
2569
2570/** @callback_method_impl{FNCPUMWRMSR} */
2571static DECLCALLBACK(int) cpumMsrWr_IntelI7UncArbPerfEvtSelN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2572{
2573 /** @todo uncore msrs. */
2574 return VINF_SUCCESS;
2575}
2576
2577
2578/** @callback_method_impl{FNCPUMRDMSR} */
2579static DECLCALLBACK(int) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2580{
2581 /** @todo implement enhanced multi thread termal monitoring? */
2582 *puValue = pRange->uValue;
2583 return VINF_SUCCESS;
2584}
2585
2586
2587/** @callback_method_impl{FNCPUMWRMSR} */
2588static DECLCALLBACK(int) cpumMsrWr_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2589{
2590 /** @todo implement enhanced multi thread termal monitoring? */
2591 return VINF_SUCCESS;
2592}
2593
2594
2595/** @callback_method_impl{FNCPUMRDMSR} */
2596static DECLCALLBACK(int) cpumMsrRd_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2597{
2598 /** @todo SMM & C-states? */
2599 *puValue = 0;
2600 return VINF_SUCCESS;
2601}
2602
2603
2604/** @callback_method_impl{FNCPUMWRMSR} */
2605static DECLCALLBACK(int) cpumMsrWr_IntelCore2SmmCStMiscInfo(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2606{
2607 /** @todo SMM & C-states? */
2608 return VINF_SUCCESS;
2609}
2610
2611
2612/** @callback_method_impl{FNCPUMRDMSR} */
2613static DECLCALLBACK(int) cpumMsrRd_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2614{
2615 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2616 *puValue = 0;
2617 return VINF_SUCCESS;
2618}
2619
2620
2621/** @callback_method_impl{FNCPUMWRMSR} */
2622static DECLCALLBACK(int) cpumMsrWr_IntelCore1ExtConfig(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2623{
2624 /** @todo Core1&2 EXT_CONFIG (whatever that is)? */
2625 return VINF_SUCCESS;
2626}
2627
2628
2629/** @callback_method_impl{FNCPUMRDMSR} */
2630static DECLCALLBACK(int) cpumMsrRd_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2631{
2632 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2633 *puValue = 0;
2634 return VINF_SUCCESS;
2635}
2636
2637
2638/** @callback_method_impl{FNCPUMWRMSR} */
2639static DECLCALLBACK(int) cpumMsrWr_IntelCore1DtsCalControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2640{
2641 /** @todo Core1&2(?) DTS_CAL_CTRL (whatever that is)? */
2642 return VINF_SUCCESS;
2643}
2644
2645
2646/** @callback_method_impl{FNCPUMRDMSR} */
2647static DECLCALLBACK(int) cpumMsrRd_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2648{
2649 /** @todo Core2+ platform environment control interface control register? */
2650 *puValue = 0;
2651 return VINF_SUCCESS;
2652}
2653
2654
2655/** @callback_method_impl{FNCPUMWRMSR} */
2656static DECLCALLBACK(int) cpumMsrWr_IntelCore2PeciControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2657{
2658 /** @todo Core2+ platform environment control interface control register? */
2659 return VINF_SUCCESS;
2660}
2661
2662
2663
2664/*
2665 * Multiple vendor P6 MSRs.
2666 * Multiple vendor P6 MSRs.
2667 * Multiple vendor P6 MSRs.
2668 *
2669 * These MSRs were introduced with the P6 but not elevated to architectural
2670 * MSRs, despite other vendors implementing them.
2671 */
2672
2673
2674/** @callback_method_impl{FNCPUMRDMSR} */
2675static DECLCALLBACK(int) cpumMsrRd_P6LastBranchFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2676{
2677 /* AMD seems to just record RIP, while intel claims to record RIP+CS.BASE
2678 if I read the docs correctly, thus the need for separate functions. */
2679 /** @todo implement last branch records. */
2680 *puValue = 0;
2681 return VINF_SUCCESS;
2682}
2683
2684
2685/** @callback_method_impl{FNCPUMRDMSR} */
2686static DECLCALLBACK(int) cpumMsrRd_P6LastBranchToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2687{
2688 /** @todo implement last branch records. */
2689 *puValue = 0;
2690 return VINF_SUCCESS;
2691}
2692
2693
2694/** @callback_method_impl{FNCPUMRDMSR} */
2695static DECLCALLBACK(int) cpumMsrRd_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2696{
2697 /** @todo implement last exception records. */
2698 *puValue = 0;
2699 return VINF_SUCCESS;
2700}
2701
2702
2703/** @callback_method_impl{FNCPUMWRMSR} */
2704static DECLCALLBACK(int) cpumMsrWr_P6LastIntFromIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2705{
2706 /** @todo implement last exception records. */
2707 return VINF_SUCCESS;
2708}
2709
2710
2711/** @callback_method_impl{FNCPUMRDMSR} */
2712static DECLCALLBACK(int) cpumMsrRd_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2713{
2714 /** @todo implement last exception records. */
2715 *puValue = 0;
2716 return VINF_SUCCESS;
2717}
2718
2719
2720/** @callback_method_impl{FNCPUMWRMSR} */
2721static DECLCALLBACK(int) cpumMsrWr_P6LastIntToIp(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2722{
2723 /** @todo implement last exception records. */
2724 return VINF_SUCCESS;
2725}
2726
2727
2728
2729/*
2730 * AMD specific
2731 * AMD specific
2732 * AMD specific
2733 */
2734
2735
2736/** @callback_method_impl{FNCPUMRDMSR} */
2737static DECLCALLBACK(int) cpumMsrRd_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2738{
2739 /** @todo Implement TscRateMsr */
2740 *puValue = RT_MAKE_U64(0, 1); /* 1.0 = reset value. */
2741 return VINF_SUCCESS;
2742}
2743
2744
2745/** @callback_method_impl{FNCPUMWRMSR} */
2746static DECLCALLBACK(int) cpumMsrWr_AmdFam15hTscRate(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2747{
2748 /** @todo Implement TscRateMsr */
2749 return VINF_SUCCESS;
2750}
2751
2752
2753/** @callback_method_impl{FNCPUMRDMSR} */
2754static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2755{
2756 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2757 /* Note: Only listes in BKDG for Family 15H. */
2758 *puValue = 0;
2759 return VINF_SUCCESS;
2760}
2761
2762
2763/** @callback_method_impl{FNCPUMWRMSR} */
2764static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2765{
2766 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2767 return VINF_SUCCESS;
2768}
2769
2770
2771/** @callback_method_impl{FNCPUMRDMSR} */
2772static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2773{
2774 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2775 /* Note: Only listes in BKDG for Family 15H. */
2776 *puValue = 0;
2777 return VINF_SUCCESS;
2778}
2779
2780
2781/** @callback_method_impl{FNCPUMWRMSR} */
2782static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLwpCbAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2783{
2784 /** @todo Implement AMD LWP? (Instructions: LWPINS, LWPVAL, LLWPCB, SLWPCB) */
2785 return VINF_SUCCESS;
2786}
2787
2788
2789/** @callback_method_impl{FNCPUMRDMSR} */
2790static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2791{
2792 /** @todo machine check. */
2793 *puValue = 0;
2794 return VINF_SUCCESS;
2795}
2796
2797
2798/** @callback_method_impl{FNCPUMWRMSR} */
2799static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMc4MiscN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2800{
2801 /** @todo machine check. */
2802 return VINF_SUCCESS;
2803}
2804
2805
2806/** @callback_method_impl{FNCPUMRDMSR} */
2807static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2808{
2809 /** @todo AMD performance events. */
2810 *puValue = 0;
2811 return VINF_SUCCESS;
2812}
2813
2814
2815/** @callback_method_impl{FNCPUMWRMSR} */
2816static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2817{
2818 /** @todo AMD performance events. */
2819 return VINF_SUCCESS;
2820}
2821
2822
2823/** @callback_method_impl{FNCPUMRDMSR} */
2824static DECLCALLBACK(int) cpumMsrRd_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2825{
2826 /** @todo AMD performance events. */
2827 *puValue = 0;
2828 return VINF_SUCCESS;
2829}
2830
2831
2832/** @callback_method_impl{FNCPUMWRMSR} */
2833static DECLCALLBACK(int) cpumMsrWr_AmdK8PerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2834{
2835 /** @todo AMD performance events. */
2836 return VINF_SUCCESS;
2837}
2838
2839
2840/** @callback_method_impl{FNCPUMRDMSR} */
2841static DECLCALLBACK(int) cpumMsrRd_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2842{
2843 /** @todo AMD SYS_CFG */
2844 *puValue = pRange->uValue;
2845 return VINF_SUCCESS;
2846}
2847
2848
2849/** @callback_method_impl{FNCPUMWRMSR} */
2850static DECLCALLBACK(int) cpumMsrWr_AmdK8SysCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2851{
2852 /** @todo AMD SYS_CFG */
2853 return VINF_SUCCESS;
2854}
2855
2856
2857/** @callback_method_impl{FNCPUMRDMSR} */
2858static DECLCALLBACK(int) cpumMsrRd_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2859{
2860 /** @todo AMD HW_CFG */
2861 *puValue = 0;
2862 return VINF_SUCCESS;
2863}
2864
2865
2866/** @callback_method_impl{FNCPUMWRMSR} */
2867static DECLCALLBACK(int) cpumMsrWr_AmdK8HwCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2868{
2869 /** @todo AMD HW_CFG */
2870 return VINF_SUCCESS;
2871}
2872
2873
2874/** @callback_method_impl{FNCPUMRDMSR} */
2875static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2876{
2877 /** @todo AMD IorrMask/IorrBase */
2878 *puValue = 0;
2879 return VINF_SUCCESS;
2880}
2881
2882
2883/** @callback_method_impl{FNCPUMWRMSR} */
2884static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrBaseN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2885{
2886 /** @todo AMD IorrMask/IorrBase */
2887 return VINF_SUCCESS;
2888}
2889
2890
2891/** @callback_method_impl{FNCPUMRDMSR} */
2892static DECLCALLBACK(int) cpumMsrRd_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2893{
2894 /** @todo AMD IorrMask/IorrBase */
2895 *puValue = 0;
2896 return VINF_SUCCESS;
2897}
2898
2899
2900/** @callback_method_impl{FNCPUMWRMSR} */
2901static DECLCALLBACK(int) cpumMsrWr_AmdK8IorrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2902{
2903 /** @todo AMD IorrMask/IorrBase */
2904 return VINF_SUCCESS;
2905}
2906
2907
2908/** @callback_method_impl{FNCPUMRDMSR} */
2909static DECLCALLBACK(int) cpumMsrRd_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2910{
2911 *puValue = 0;
2912 /** @todo return 4GB - RamHoleSize here for TOPMEM. Figure out what to return
2913 * for TOPMEM2. */
2914 //if (pRange->uValue == 0)
2915 // *puValue = _4G - RamHoleSize;
2916 return VINF_SUCCESS;
2917}
2918
2919
2920/** @callback_method_impl{FNCPUMWRMSR} */
2921static DECLCALLBACK(int) cpumMsrWr_AmdK8TopOfMemN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2922{
2923 /** @todo AMD TOPMEM and TOPMEM2/TOM2. */
2924 return VINF_SUCCESS;
2925}
2926
2927
2928/** @callback_method_impl{FNCPUMRDMSR} */
2929static DECLCALLBACK(int) cpumMsrRd_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2930{
2931 /** @todo AMD NB_CFG1 */
2932 *puValue = 0;
2933 return VINF_SUCCESS;
2934}
2935
2936
2937/** @callback_method_impl{FNCPUMWRMSR} */
2938static DECLCALLBACK(int) cpumMsrWr_AmdK8NbCfg1(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2939{
2940 /** @todo AMD NB_CFG1 */
2941 return VINF_SUCCESS;
2942}
2943
2944
2945/** @callback_method_impl{FNCPUMRDMSR} */
2946static DECLCALLBACK(int) cpumMsrRd_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2947{
2948 /** @todo machine check. */
2949 *puValue = 0;
2950 return VINF_SUCCESS;
2951}
2952
2953
2954/** @callback_method_impl{FNCPUMWRMSR} */
2955static DECLCALLBACK(int) cpumMsrWr_AmdK8McXcptRedir(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2956{
2957 /** @todo machine check. */
2958 return VINF_SUCCESS;
2959}
2960
2961
2962/** @callback_method_impl{FNCPUMRDMSR} */
2963static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2964{
2965 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), pRange->uValue / 2 + 0x80000001, 0);
2966 if (pLeaf)
2967 {
2968 if (!(pRange->uValue & 1))
2969 *puValue = RT_MAKE_U64(pLeaf->uEax, pLeaf->uEbx);
2970 else
2971 *puValue = RT_MAKE_U64(pLeaf->uEcx, pLeaf->uEdx);
2972 }
2973 else
2974 *puValue = 0;
2975 return VINF_SUCCESS;
2976}
2977
2978
2979/** @callback_method_impl{FNCPUMWRMSR} */
2980static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuNameN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2981{
2982 /** @todo Remember guest programmed CPU name. */
2983 return VINF_SUCCESS;
2984}
2985
2986
2987/** @callback_method_impl{FNCPUMRDMSR} */
2988static DECLCALLBACK(int) cpumMsrRd_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
2989{
2990 /** @todo AMD HTC. */
2991 *puValue = pRange->uValue;
2992 return VINF_SUCCESS;
2993}
2994
2995
2996/** @callback_method_impl{FNCPUMWRMSR} */
2997static DECLCALLBACK(int) cpumMsrWr_AmdK8HwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
2998{
2999 /** @todo AMD HTC. */
3000 return VINF_SUCCESS;
3001}
3002
3003
3004/** @callback_method_impl{FNCPUMRDMSR} */
3005static DECLCALLBACK(int) cpumMsrRd_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3006{
3007 /** @todo AMD STC. */
3008 *puValue = 0;
3009 return VINF_SUCCESS;
3010}
3011
3012
3013/** @callback_method_impl{FNCPUMWRMSR} */
3014static DECLCALLBACK(int) cpumMsrWr_AmdK8SwThermalCtrl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3015{
3016 /** @todo AMD STC. */
3017 return VINF_SUCCESS;
3018}
3019
3020
3021/** @callback_method_impl{FNCPUMRDMSR} */
3022static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3023{
3024 /** @todo AMD FIDVID_CTL. */
3025 *puValue = pRange->uValue;
3026 return VINF_SUCCESS;
3027}
3028
3029
3030/** @callback_method_impl{FNCPUMWRMSR} */
3031static DECLCALLBACK(int) cpumMsrWr_AmdK8FidVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3032{
3033 /** @todo AMD FIDVID_CTL. */
3034 return VINF_SUCCESS;
3035}
3036
3037
3038/** @callback_method_impl{FNCPUMRDMSR} */
3039static DECLCALLBACK(int) cpumMsrRd_AmdK8FidVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3040{
3041 /** @todo AMD FIDVID_STATUS. */
3042 *puValue = pRange->uValue;
3043 return VINF_SUCCESS;
3044}
3045
3046
3047/** @callback_method_impl{FNCPUMRDMSR} */
3048static DECLCALLBACK(int) cpumMsrRd_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3049{
3050 /** @todo AMD MC. */
3051 *puValue = 0;
3052 return VINF_SUCCESS;
3053}
3054
3055
3056/** @callback_method_impl{FNCPUMWRMSR} */
3057static DECLCALLBACK(int) cpumMsrWr_AmdK8McCtlMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3058{
3059 /** @todo AMD MC. */
3060 return VINF_SUCCESS;
3061}
3062
3063
3064/** @callback_method_impl{FNCPUMRDMSR} */
3065static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3066{
3067 /** @todo AMD SMM/SMI and I/O trap. */
3068 *puValue = 0;
3069 return VINF_SUCCESS;
3070}
3071
3072
3073/** @callback_method_impl{FNCPUMWRMSR} */
3074static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3075{
3076 /** @todo AMD SMM/SMI and I/O trap. */
3077 return VINF_SUCCESS;
3078}
3079
3080
3081/** @callback_method_impl{FNCPUMRDMSR} */
3082static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3083{
3084 /** @todo AMD SMM/SMI and I/O trap. */
3085 *puValue = 0;
3086 return VINF_SUCCESS;
3087}
3088
3089
3090/** @callback_method_impl{FNCPUMWRMSR} */
3091static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiOnIoTrapCtlSts(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3092{
3093 /** @todo AMD SMM/SMI and I/O trap. */
3094 return VINF_SUCCESS;
3095}
3096
3097
3098/** @callback_method_impl{FNCPUMRDMSR} */
3099static DECLCALLBACK(int) cpumMsrRd_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3100{
3101 /** @todo Interrupt pending message. */
3102 *puValue = 0;
3103 return VINF_SUCCESS;
3104}
3105
3106
3107/** @callback_method_impl{FNCPUMWRMSR} */
3108static DECLCALLBACK(int) cpumMsrWr_AmdK8IntPendingMessage(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3109{
3110 /** @todo Interrupt pending message. */
3111 return VINF_SUCCESS;
3112}
3113
3114
3115/** @callback_method_impl{FNCPUMRDMSR} */
3116static DECLCALLBACK(int) cpumMsrRd_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3117{
3118 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3119 *puValue = 0;
3120 return VINF_SUCCESS;
3121}
3122
3123
3124/** @callback_method_impl{FNCPUMWRMSR} */
3125static DECLCALLBACK(int) cpumMsrWr_AmdK8SmiTriggerIoCycle(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3126{
3127 /** @todo AMD SMM/SMI and trigger I/O cycle. */
3128 return VINF_SUCCESS;
3129}
3130
3131
3132/** @callback_method_impl{FNCPUMRDMSR} */
3133static DECLCALLBACK(int) cpumMsrRd_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3134{
3135 /** @todo AMD MMIO Configuration base address. */
3136 *puValue = 0;
3137 return VINF_SUCCESS;
3138}
3139
3140
3141/** @callback_method_impl{FNCPUMWRMSR} */
3142static DECLCALLBACK(int) cpumMsrWr_AmdFam10hMmioCfgBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3143{
3144 /** @todo AMD MMIO Configuration base address. */
3145 return VINF_SUCCESS;
3146}
3147
3148
3149/** @callback_method_impl{FNCPUMRDMSR} */
3150static DECLCALLBACK(int) cpumMsrRd_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3151{
3152 /** @todo AMD 0xc0010059. */
3153 *puValue = 0;
3154 return VINF_SUCCESS;
3155}
3156
3157
3158/** @callback_method_impl{FNCPUMWRMSR} */
3159static DECLCALLBACK(int) cpumMsrWr_AmdFam10hTrapCtlMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3160{
3161 /** @todo AMD 0xc0010059. */
3162 return VINF_SUCCESS;
3163}
3164
3165
3166/** @callback_method_impl{FNCPUMRDMSR} */
3167static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateCurLimit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3168{
3169 /** @todo AMD P-states. */
3170 *puValue = pRange->uValue;
3171 return VINF_SUCCESS;
3172}
3173
3174
3175/** @callback_method_impl{FNCPUMRDMSR} */
3176static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3177{
3178 /** @todo AMD P-states. */
3179 *puValue = pRange->uValue;
3180 return VINF_SUCCESS;
3181}
3182
3183
3184/** @callback_method_impl{FNCPUMWRMSR} */
3185static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3186{
3187 /** @todo AMD P-states. */
3188 return VINF_SUCCESS;
3189}
3190
3191
3192/** @callback_method_impl{FNCPUMRDMSR} */
3193static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3194{
3195 /** @todo AMD P-states. */
3196 *puValue = pRange->uValue;
3197 return VINF_SUCCESS;
3198}
3199
3200
3201/** @callback_method_impl{FNCPUMWRMSR} */
3202static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3203{
3204 /** @todo AMD P-states. */
3205 return VINF_SUCCESS;
3206}
3207
3208
3209/** @callback_method_impl{FNCPUMRDMSR} */
3210static DECLCALLBACK(int) cpumMsrRd_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3211{
3212 /** @todo AMD P-states. */
3213 *puValue = pRange->uValue;
3214 return VINF_SUCCESS;
3215}
3216
3217
3218/** @callback_method_impl{FNCPUMWRMSR} */
3219static DECLCALLBACK(int) cpumMsrWr_AmdFam10hPStateN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3220{
3221 /** @todo AMD P-states. */
3222 return VINF_SUCCESS;
3223}
3224
3225
3226/** @callback_method_impl{FNCPUMRDMSR} */
3227static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3228{
3229 /** @todo AMD P-states. */
3230 *puValue = pRange->uValue;
3231 return VINF_SUCCESS;
3232}
3233
3234
3235/** @callback_method_impl{FNCPUMWRMSR} */
3236static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidControl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3237{
3238 /** @todo AMD P-states. */
3239 return VINF_SUCCESS;
3240}
3241
3242
3243/** @callback_method_impl{FNCPUMRDMSR} */
3244static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3245{
3246 /** @todo AMD P-states. */
3247 *puValue = pRange->uValue;
3248 return VINF_SUCCESS;
3249}
3250
3251
3252/** @callback_method_impl{FNCPUMWRMSR} */
3253static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCofVidStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3254{
3255 /* Note! Writing 0 seems to not GP, not sure if it does anything to the value... */
3256 /** @todo AMD P-states. */
3257 return VINF_SUCCESS;
3258}
3259
3260
3261/** @callback_method_impl{FNCPUMRDMSR} */
3262static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3263{
3264 /** @todo AMD C-states. */
3265 *puValue = 0;
3266 return VINF_SUCCESS;
3267}
3268
3269
3270/** @callback_method_impl{FNCPUMWRMSR} */
3271static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCStateIoBaseAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3272{
3273 /** @todo AMD C-states. */
3274 return VINF_SUCCESS;
3275}
3276
3277
3278/** @callback_method_impl{FNCPUMRDMSR} */
3279static DECLCALLBACK(int) cpumMsrRd_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3280{
3281 /** @todo AMD machine checks. */
3282 *puValue = 0;
3283 return VINF_SUCCESS;
3284}
3285
3286
3287/** @callback_method_impl{FNCPUMWRMSR} */
3288static DECLCALLBACK(int) cpumMsrWr_AmdFam10hCpuWatchdogTimer(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3289{
3290 /** @todo AMD machine checks. */
3291 return VINF_SUCCESS;
3292}
3293
3294
3295/** @callback_method_impl{FNCPUMRDMSR} */
3296static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3297{
3298 /** @todo AMD SMM. */
3299 *puValue = 0;
3300 return VINF_SUCCESS;
3301}
3302
3303
3304/** @callback_method_impl{FNCPUMWRMSR} */
3305static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmBase(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3306{
3307 /** @todo AMD SMM. */
3308 return VINF_SUCCESS;
3309}
3310
3311
3312/** @callback_method_impl{FNCPUMRDMSR} */
3313static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3314{
3315 /** @todo AMD SMM. */
3316 *puValue = 0;
3317 return VINF_SUCCESS;
3318}
3319
3320
3321/** @callback_method_impl{FNCPUMWRMSR} */
3322static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3323{
3324 /** @todo AMD SMM. */
3325 return VINF_SUCCESS;
3326}
3327
3328
3329
3330/** @callback_method_impl{FNCPUMRDMSR} */
3331static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3332{
3333 /** @todo AMD SMM. */
3334 *puValue = 0;
3335 return VINF_SUCCESS;
3336}
3337
3338
3339/** @callback_method_impl{FNCPUMWRMSR} */
3340static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmMask(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3341{
3342 /** @todo AMD SMM. */
3343 return VINF_SUCCESS;
3344}
3345
3346
3347/** @callback_method_impl{FNCPUMRDMSR} */
3348static DECLCALLBACK(int) cpumMsrRd_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3349{
3350 /** @todo AMD SVM. */
3351 *puValue = 0;
3352 return VINF_SUCCESS;
3353}
3354
3355
3356/** @callback_method_impl{FNCPUMWRMSR} */
3357static DECLCALLBACK(int) cpumMsrWr_AmdK8VmCr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3358{
3359 /** @todo AMD SVM. */
3360 return VINF_SUCCESS;
3361}
3362
3363
3364/** @callback_method_impl{FNCPUMRDMSR} */
3365static DECLCALLBACK(int) cpumMsrRd_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3366{
3367 /** @todo AMD IGNNE\# control. */
3368 *puValue = 0;
3369 return VINF_SUCCESS;
3370}
3371
3372
3373/** @callback_method_impl{FNCPUMWRMSR} */
3374static DECLCALLBACK(int) cpumMsrWr_AmdK8IgnNe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3375{
3376 /** @todo AMD IGNNE\# control. */
3377 return VINF_SUCCESS;
3378}
3379
3380
3381/** @callback_method_impl{FNCPUMRDMSR} */
3382static DECLCALLBACK(int) cpumMsrRd_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3383{
3384 /** @todo AMD SMM. */
3385 *puValue = 0;
3386 return VINF_SUCCESS;
3387}
3388
3389
3390/** @callback_method_impl{FNCPUMWRMSR} */
3391static DECLCALLBACK(int) cpumMsrWr_AmdK8SmmCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3392{
3393 /** @todo AMD SMM. */
3394 return VINF_SUCCESS;
3395}
3396
3397
3398/** @callback_method_impl{FNCPUMRDMSR} */
3399static DECLCALLBACK(int) cpumMsrRd_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3400{
3401 /** @todo AMD SVM. */
3402 *puValue = 0;
3403 return VINF_SUCCESS;
3404}
3405
3406
3407/** @callback_method_impl{FNCPUMWRMSR} */
3408static DECLCALLBACK(int) cpumMsrWr_AmdK8VmHSavePa(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3409{
3410 /** @todo AMD SVM. */
3411 return VINF_SUCCESS;
3412}
3413
3414
3415/** @callback_method_impl{FNCPUMRDMSR} */
3416static DECLCALLBACK(int) cpumMsrRd_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3417{
3418 /** @todo AMD SVM. */
3419 *puValue = 0; /* RAZ */
3420 return VINF_SUCCESS;
3421}
3422
3423
3424/** @callback_method_impl{FNCPUMWRMSR} */
3425static DECLCALLBACK(int) cpumMsrWr_AmdFam10hVmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3426{
3427 /** @todo AMD SVM. */
3428 return VINF_SUCCESS;
3429}
3430
3431
3432/** @callback_method_impl{FNCPUMRDMSR} */
3433static DECLCALLBACK(int) cpumMsrRd_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3434{
3435 /** @todo AMD SMM. */
3436 *puValue = 0; /* RAZ */
3437 return VINF_SUCCESS;
3438}
3439
3440
3441/** @callback_method_impl{FNCPUMWRMSR} */
3442static DECLCALLBACK(int) cpumMsrWr_AmdFam10hSmmLockKey(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3443{
3444 /** @todo AMD SMM. */
3445 return VINF_SUCCESS;
3446}
3447
3448
3449/** @callback_method_impl{FNCPUMRDMSR} */
3450static DECLCALLBACK(int) cpumMsrRd_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3451{
3452 /** @todo AMD SMM/SMI. */
3453 *puValue = 0;
3454 return VINF_SUCCESS;
3455}
3456
3457
3458/** @callback_method_impl{FNCPUMWRMSR} */
3459static DECLCALLBACK(int) cpumMsrWr_AmdFam10hLocalSmiStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3460{
3461 /** @todo AMD SMM/SMI. */
3462 return VINF_SUCCESS;
3463}
3464
3465
3466/** @callback_method_impl{FNCPUMRDMSR} */
3467static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3468{
3469 /** @todo AMD OS visible workaround. */
3470 *puValue = pRange->uValue;
3471 return VINF_SUCCESS;
3472}
3473
3474
3475/** @callback_method_impl{FNCPUMWRMSR} */
3476static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkIdLength(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3477{
3478 /** @todo AMD OS visible workaround. */
3479 return VINF_SUCCESS;
3480}
3481
3482
3483/** @callback_method_impl{FNCPUMRDMSR} */
3484static DECLCALLBACK(int) cpumMsrRd_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3485{
3486 /** @todo AMD OS visible workaround. */
3487 *puValue = 0;
3488 return VINF_SUCCESS;
3489}
3490
3491
3492/** @callback_method_impl{FNCPUMWRMSR} */
3493static DECLCALLBACK(int) cpumMsrWr_AmdFam10hOsVisWrkStatus(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3494{
3495 /** @todo AMD OS visible workaround. */
3496 return VINF_SUCCESS;
3497}
3498
3499
3500/** @callback_method_impl{FNCPUMRDMSR} */
3501static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3502{
3503 /** @todo AMD L2I performance counters. */
3504 *puValue = 0;
3505 return VINF_SUCCESS;
3506}
3507
3508
3509/** @callback_method_impl{FNCPUMWRMSR} */
3510static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3511{
3512 /** @todo AMD L2I performance counters. */
3513 return VINF_SUCCESS;
3514}
3515
3516
3517/** @callback_method_impl{FNCPUMRDMSR} */
3518static DECLCALLBACK(int) cpumMsrRd_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3519{
3520 /** @todo AMD L2I performance counters. */
3521 *puValue = 0;
3522 return VINF_SUCCESS;
3523}
3524
3525
3526/** @callback_method_impl{FNCPUMWRMSR} */
3527static DECLCALLBACK(int) cpumMsrWr_AmdFam16hL2IPerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3528{
3529 /** @todo AMD L2I performance counters. */
3530 return VINF_SUCCESS;
3531}
3532
3533
3534/** @callback_method_impl{FNCPUMRDMSR} */
3535static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3536{
3537 /** @todo AMD Northbridge performance counters. */
3538 *puValue = 0;
3539 return VINF_SUCCESS;
3540}
3541
3542
3543/** @callback_method_impl{FNCPUMWRMSR} */
3544static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3545{
3546 /** @todo AMD Northbridge performance counters. */
3547 return VINF_SUCCESS;
3548}
3549
3550
3551/** @callback_method_impl{FNCPUMRDMSR} */
3552static DECLCALLBACK(int) cpumMsrRd_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3553{
3554 /** @todo AMD Northbridge performance counters. */
3555 *puValue = 0;
3556 return VINF_SUCCESS;
3557}
3558
3559
3560/** @callback_method_impl{FNCPUMWRMSR} */
3561static DECLCALLBACK(int) cpumMsrWr_AmdFam15hNorthbridgePerfCtrN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3562{
3563 /** @todo AMD Northbridge performance counters. */
3564 return VINF_SUCCESS;
3565}
3566
3567
3568/** @callback_method_impl{FNCPUMRDMSR} */
3569static DECLCALLBACK(int) cpumMsrRd_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3570{
3571 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3572 * cpus. Need to be explored and verify K7 presence. */
3573 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3574 *puValue = pRange->uValue;
3575 return VINF_SUCCESS;
3576}
3577
3578
3579/** @callback_method_impl{FNCPUMWRMSR} */
3580static DECLCALLBACK(int) cpumMsrWr_AmdK7MicrocodeCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3581{
3582 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3583 * cpus. Need to be explored and verify K7 presence. */
3584 /** @todo Undocumented register only seen mentioned in fam15h erratum \#608. */
3585 return VINF_SUCCESS;
3586}
3587
3588
3589/** @callback_method_impl{FNCPUMRDMSR} */
3590static DECLCALLBACK(int) cpumMsrRd_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3591{
3592 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3593 * cpus. Need to be explored and verify K7 presence. */
3594 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3595 * describing EBL_CR_POWERON. */
3596 *puValue = pRange->uValue;
3597 return VINF_SUCCESS;
3598}
3599
3600
3601/** @callback_method_impl{FNCPUMWRMSR} */
3602static DECLCALLBACK(int) cpumMsrWr_AmdK7ClusterIdMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3603{
3604 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3605 * cpus. Need to be explored and verify K7 presence. */
3606 /** @todo Undocumented register only seen mentioned in fam16h BKDG r3.00 when
3607 * describing EBL_CR_POWERON. */
3608 return VINF_SUCCESS;
3609}
3610
3611
3612/** @callback_method_impl{FNCPUMRDMSR} */
3613static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3614{
3615 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000007, 0);
3616 if (pLeaf)
3617 *puValue = RT_MAKE_U64(pLeaf->uEbx, pLeaf->uEax);
3618 else
3619 *puValue = 0;
3620 return VINF_SUCCESS;
3621}
3622
3623
3624/** @callback_method_impl{FNCPUMWRMSR} */
3625static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd07hEbax(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3626{
3627 /** @todo Changing CPUID leaf 7/0. */
3628 return VINF_SUCCESS;
3629}
3630
3631
3632/** @callback_method_impl{FNCPUMRDMSR} */
3633static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3634{
3635 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000006, 0);
3636 if (pLeaf)
3637 *puValue = pLeaf->uEcx;
3638 else
3639 *puValue = 0;
3640 return VINF_SUCCESS;
3641}
3642
3643
3644/** @callback_method_impl{FNCPUMWRMSR} */
3645static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd06hEcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3646{
3647 /** @todo Changing CPUID leaf 6. */
3648 return VINF_SUCCESS;
3649}
3650
3651
3652/** @callback_method_impl{FNCPUMRDMSR} */
3653static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3654{
3655 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x00000001, 0);
3656 if (pLeaf)
3657 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3658 else
3659 *puValue = 0;
3660 return VINF_SUCCESS;
3661}
3662
3663
3664/** @callback_method_impl{FNCPUMWRMSR} */
3665static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3666{
3667 /** @todo Changing CPUID leaf 0x80000001. */
3668 return VINF_SUCCESS;
3669}
3670
3671
3672/** @callback_method_impl{FNCPUMRDMSR} */
3673static DECLCALLBACK(int) cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3674{
3675 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeaf(pVCpu->CTX_SUFF(pVM), 0x80000001, 0);
3676 if (pLeaf)
3677 *puValue = RT_MAKE_U64(pLeaf->uEdx, pLeaf->uEcx);
3678 else
3679 *puValue = 0;
3680 return VINF_SUCCESS;
3681}
3682
3683
3684/** @callback_method_impl{FNCPUMWRMSR} */
3685static DECLCALLBACK(int) cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3686{
3687 /** @todo Changing CPUID leaf 0x80000001. */
3688 return VINF_SUCCESS;
3689}
3690
3691
3692/** @callback_method_impl{FNCPUMRDMSR} */
3693static DECLCALLBACK(int) cpumMsrRd_AmdK8PatchLevel(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3694{
3695 /** @todo Fake AMD microcode patching. */
3696 *puValue = pRange->uValue;
3697 return VINF_SUCCESS;
3698}
3699
3700
3701/** @callback_method_impl{FNCPUMWRMSR} */
3702static DECLCALLBACK(int) cpumMsrWr_AmdK8PatchLoader(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3703{
3704 /** @todo Fake AMD microcode patching. */
3705 return VINF_SUCCESS;
3706}
3707
3708
3709/** @callback_method_impl{FNCPUMRDMSR} */
3710static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3711{
3712 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3713 * cpus. Need to be explored and verify K7 presence. */
3714 /** @todo undocumented */
3715 *puValue = 0;
3716 return VINF_SUCCESS;
3717}
3718
3719
3720/** @callback_method_impl{FNCPUMWRMSR} */
3721static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugStatusMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3722{
3723 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3724 * cpus. Need to be explored and verify K7 presence. */
3725 /** @todo undocumented */
3726 return VINF_SUCCESS;
3727}
3728
3729
3730/** @callback_method_impl{FNCPUMRDMSR} */
3731static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3732{
3733 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3734 * cpus. Need to be explored and verify K7 presence. */
3735 /** @todo undocumented */
3736 *puValue = 0;
3737 return VINF_SUCCESS;
3738}
3739
3740
3741/** @callback_method_impl{FNCPUMWRMSR} */
3742static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceBaseMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3743{
3744 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3745 * cpus. Need to be explored and verify K7 presence. */
3746 /** @todo undocumented */
3747 return VINF_SUCCESS;
3748}
3749
3750
3751/** @callback_method_impl{FNCPUMRDMSR} */
3752static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3753{
3754 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3755 * cpus. Need to be explored and verify K7 presence. */
3756 /** @todo undocumented */
3757 *puValue = 0;
3758 return VINF_SUCCESS;
3759}
3760
3761
3762/** @callback_method_impl{FNCPUMWRMSR} */
3763static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTracePtrMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3764{
3765 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3766 * cpus. Need to be explored and verify K7 presence. */
3767 /** @todo undocumented */
3768 return VINF_SUCCESS;
3769}
3770
3771
3772/** @callback_method_impl{FNCPUMRDMSR} */
3773static DECLCALLBACK(int) cpumMsrRd_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3774{
3775 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3776 * cpus. Need to be explored and verify K7 presence. */
3777 /** @todo undocumented */
3778 *puValue = 0;
3779 return VINF_SUCCESS;
3780}
3781
3782
3783/** @callback_method_impl{FNCPUMWRMSR} */
3784static DECLCALLBACK(int) cpumMsrWr_AmdK7BHTraceLimitMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3785{
3786 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3787 * cpus. Need to be explored and verify K7 presence. */
3788 /** @todo undocumented */
3789 return VINF_SUCCESS;
3790}
3791
3792
3793/** @callback_method_impl{FNCPUMRDMSR} */
3794static DECLCALLBACK(int) cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3795{
3796 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3797 * cpus. Need to be explored and verify K7 presence. */
3798 /** @todo undocumented */
3799 *puValue = 0;
3800 return VINF_SUCCESS;
3801}
3802
3803
3804/** @callback_method_impl{FNCPUMWRMSR} */
3805static DECLCALLBACK(int) cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3806{
3807 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3808 * cpus. Need to be explored and verify K7 presence. */
3809 /** @todo undocumented */
3810 return VINF_SUCCESS;
3811}
3812
3813
3814/** @callback_method_impl{FNCPUMRDMSR} */
3815static DECLCALLBACK(int) cpumMsrRd_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3816{
3817 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3818 * cpus. Need to be explored and verify K7 presence. */
3819 /** @todo undocumented */
3820 *puValue = 0;
3821 return VINF_SUCCESS;
3822}
3823
3824
3825/** @callback_method_impl{FNCPUMWRMSR} */
3826static DECLCALLBACK(int) cpumMsrWr_AmdK7FastFlushCountMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3827{
3828 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3829 * cpus. Need to be explored and verify K7 presence. */
3830 /** @todo undocumented */
3831 return VINF_SUCCESS;
3832}
3833
3834
3835/** @callback_method_impl{FNCPUMRDMSR} */
3836static DECLCALLBACK(int) cpumMsrRd_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3837{
3838 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3839 * cpus. Need to be explored and verify K7 presence. */
3840 /** @todo AMD node ID and bios scratch. */
3841 *puValue = 0; /* nodeid = 0; nodes-per-cpu = 1 */
3842 return VINF_SUCCESS;
3843}
3844
3845
3846/** @callback_method_impl{FNCPUMWRMSR} */
3847static DECLCALLBACK(int) cpumMsrWr_AmdK7NodeId(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3848{
3849 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3850 * cpus. Need to be explored and verify K7 presence. */
3851 /** @todo AMD node ID and bios scratch. */
3852 return VINF_SUCCESS;
3853}
3854
3855
3856/** @callback_method_impl{FNCPUMRDMSR} */
3857static DECLCALLBACK(int) cpumMsrRd_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3858{
3859 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3860 * cpus. Need to be explored and verify K7 presence. */
3861 /** @todo AMD DRx address masking (range breakpoints). */
3862 *puValue = 0;
3863 return VINF_SUCCESS;
3864}
3865
3866
3867/** @callback_method_impl{FNCPUMWRMSR} */
3868static DECLCALLBACK(int) cpumMsrWr_AmdK7DrXAddrMaskN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3869{
3870 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3871 * cpus. Need to be explored and verify K7 presence. */
3872 /** @todo AMD DRx address masking (range breakpoints). */
3873 return VINF_SUCCESS;
3874}
3875
3876
3877/** @callback_method_impl{FNCPUMRDMSR} */
3878static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3879{
3880 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3881 * cpus. Need to be explored and verify K7 presence. */
3882 /** @todo AMD undocument debugging features. */
3883 *puValue = 0;
3884 return VINF_SUCCESS;
3885}
3886
3887
3888/** @callback_method_impl{FNCPUMWRMSR} */
3889static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMatchMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3890{
3891 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3892 * cpus. Need to be explored and verify K7 presence. */
3893 /** @todo AMD undocument debugging features. */
3894 return VINF_SUCCESS;
3895}
3896
3897
3898/** @callback_method_impl{FNCPUMRDMSR} */
3899static DECLCALLBACK(int) cpumMsrRd_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3900{
3901 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3902 * cpus. Need to be explored and verify K7 presence. */
3903 /** @todo AMD undocument debugging features. */
3904 *puValue = 0;
3905 return VINF_SUCCESS;
3906}
3907
3908
3909/** @callback_method_impl{FNCPUMWRMSR} */
3910static DECLCALLBACK(int) cpumMsrWr_AmdK7Dr0DataMaskMaybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3911{
3912 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3913 * cpus. Need to be explored and verify K7 presence. */
3914 /** @todo AMD undocument debugging features. */
3915 return VINF_SUCCESS;
3916}
3917
3918
3919/** @callback_method_impl{FNCPUMRDMSR} */
3920static DECLCALLBACK(int) cpumMsrRd_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3921{
3922 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3923 * cpus. Need to be explored and verify K7 presence. */
3924 /** @todo AMD load-store config. */
3925 *puValue = 0;
3926 return VINF_SUCCESS;
3927}
3928
3929
3930/** @callback_method_impl{FNCPUMWRMSR} */
3931static DECLCALLBACK(int) cpumMsrWr_AmdK7LoadStoreCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3932{
3933 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3934 * cpus. Need to be explored and verify K7 presence. */
3935 /** @todo AMD load-store config. */
3936 return VINF_SUCCESS;
3937}
3938
3939
3940/** @callback_method_impl{FNCPUMRDMSR} */
3941static DECLCALLBACK(int) cpumMsrRd_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3942{
3943 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3944 * cpus. Need to be explored and verify K7 presence. */
3945 /** @todo AMD instruction cache config. */
3946 *puValue = 0;
3947 return VINF_SUCCESS;
3948}
3949
3950
3951/** @callback_method_impl{FNCPUMWRMSR} */
3952static DECLCALLBACK(int) cpumMsrWr_AmdK7InstrCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3953{
3954 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3955 * cpus. Need to be explored and verify K7 presence. */
3956 /** @todo AMD instruction cache config. */
3957 return VINF_SUCCESS;
3958}
3959
3960
3961/** @callback_method_impl{FNCPUMRDMSR} */
3962static DECLCALLBACK(int) cpumMsrRd_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3963{
3964 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3965 * cpus. Need to be explored and verify K7 presence. */
3966 /** @todo AMD data cache config. */
3967 *puValue = 0;
3968 return VINF_SUCCESS;
3969}
3970
3971
3972/** @callback_method_impl{FNCPUMWRMSR} */
3973static DECLCALLBACK(int) cpumMsrWr_AmdK7DataCacheCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3974{
3975 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3976 * cpus. Need to be explored and verify K7 presence. */
3977 /** @todo AMD data cache config. */
3978 return VINF_SUCCESS;
3979}
3980
3981
3982/** @callback_method_impl{FNCPUMRDMSR} */
3983static DECLCALLBACK(int) cpumMsrRd_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
3984{
3985 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3986 * cpus. Need to be explored and verify K7 presence. */
3987 /** @todo AMD bus unit config. */
3988 *puValue = 0;
3989 return VINF_SUCCESS;
3990}
3991
3992
3993/** @callback_method_impl{FNCPUMWRMSR} */
3994static DECLCALLBACK(int) cpumMsrWr_AmdK7BusUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
3995{
3996 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
3997 * cpus. Need to be explored and verify K7 presence. */
3998 /** @todo AMD bus unit config. */
3999 return VINF_SUCCESS;
4000}
4001
4002
4003/** @callback_method_impl{FNCPUMRDMSR} */
4004static DECLCALLBACK(int) cpumMsrRd_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4005{
4006 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4007 * cpus. Need to be explored and verify K7 presence. */
4008 /** @todo Undocument AMD debug control register \#2. */
4009 *puValue = 0;
4010 return VINF_SUCCESS;
4011}
4012
4013
4014/** @callback_method_impl{FNCPUMWRMSR} */
4015static DECLCALLBACK(int) cpumMsrWr_AmdK7DebugCtl2Maybe(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4016{
4017 /** @todo Allegedly requiring edi=0x9c5a203a when execuing rdmsr/wrmsr on older
4018 * cpus. Need to be explored and verify K7 presence. */
4019 /** @todo Undocument AMD debug control register \#2. */
4020 return VINF_SUCCESS;
4021}
4022
4023
4024/** @callback_method_impl{FNCPUMRDMSR} */
4025static DECLCALLBACK(int) cpumMsrRd_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4026{
4027 /** @todo AMD FPU config. */
4028 *puValue = 0;
4029 return VINF_SUCCESS;
4030}
4031
4032
4033/** @callback_method_impl{FNCPUMWRMSR} */
4034static DECLCALLBACK(int) cpumMsrWr_AmdFam15hFpuCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4035{
4036 /** @todo AMD FPU config. */
4037 return VINF_SUCCESS;
4038}
4039
4040
4041/** @callback_method_impl{FNCPUMRDMSR} */
4042static DECLCALLBACK(int) cpumMsrRd_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4043{
4044 /** @todo AMD decoder config. */
4045 *puValue = 0;
4046 return VINF_SUCCESS;
4047}
4048
4049
4050/** @callback_method_impl{FNCPUMWRMSR} */
4051static DECLCALLBACK(int) cpumMsrWr_AmdFam15hDecoderCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4052{
4053 /** @todo AMD decoder config. */
4054 return VINF_SUCCESS;
4055}
4056
4057
4058/** @callback_method_impl{FNCPUMRDMSR} */
4059static DECLCALLBACK(int) cpumMsrRd_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4060{
4061 /* Note! 10h and 16h */
4062 /** @todo AMD bus unit config. */
4063 *puValue = 0;
4064 return VINF_SUCCESS;
4065}
4066
4067
4068/** @callback_method_impl{FNCPUMWRMSR} */
4069static DECLCALLBACK(int) cpumMsrWr_AmdFam10hBusUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4070{
4071 /* Note! 10h and 16h */
4072 /** @todo AMD bus unit config. */
4073 return VINF_SUCCESS;
4074}
4075
4076
4077/** @callback_method_impl{FNCPUMRDMSR} */
4078static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4079{
4080 /** @todo AMD unit config. */
4081 *puValue = 0;
4082 return VINF_SUCCESS;
4083}
4084
4085
4086/** @callback_method_impl{FNCPUMWRMSR} */
4087static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4088{
4089 /** @todo AMD unit config. */
4090 return VINF_SUCCESS;
4091}
4092
4093
4094/** @callback_method_impl{FNCPUMRDMSR} */
4095static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4096{
4097 /** @todo AMD unit config 2. */
4098 *puValue = 0;
4099 return VINF_SUCCESS;
4100}
4101
4102
4103/** @callback_method_impl{FNCPUMWRMSR} */
4104static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4105{
4106 /** @todo AMD unit config 2. */
4107 return VINF_SUCCESS;
4108}
4109
4110
4111/** @callback_method_impl{FNCPUMRDMSR} */
4112static DECLCALLBACK(int) cpumMsrRd_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4113{
4114 /** @todo AMD combined unit config 3. */
4115 *puValue = 0;
4116 return VINF_SUCCESS;
4117}
4118
4119
4120/** @callback_method_impl{FNCPUMWRMSR} */
4121static DECLCALLBACK(int) cpumMsrWr_AmdFam15hCombUnitCfg3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4122{
4123 /** @todo AMD combined unit config 3. */
4124 return VINF_SUCCESS;
4125}
4126
4127
4128/** @callback_method_impl{FNCPUMRDMSR} */
4129static DECLCALLBACK(int) cpumMsrRd_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4130{
4131 /** @todo AMD execution unit config. */
4132 *puValue = 0;
4133 return VINF_SUCCESS;
4134}
4135
4136
4137/** @callback_method_impl{FNCPUMWRMSR} */
4138static DECLCALLBACK(int) cpumMsrWr_AmdFam15hExecUnitCfg(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4139{
4140 /** @todo AMD execution unit config. */
4141 return VINF_SUCCESS;
4142}
4143
4144
4145/** @callback_method_impl{FNCPUMRDMSR} */
4146static DECLCALLBACK(int) cpumMsrRd_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4147{
4148 /** @todo AMD load-store config 2. */
4149 *puValue = 0;
4150 return VINF_SUCCESS;
4151}
4152
4153
4154/** @callback_method_impl{FNCPUMWRMSR} */
4155static DECLCALLBACK(int) cpumMsrWr_AmdFam15hLoadStoreCfg2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4156{
4157 /** @todo AMD load-store config 2. */
4158 return VINF_SUCCESS;
4159}
4160
4161
4162/** @callback_method_impl{FNCPUMRDMSR} */
4163static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4164{
4165 /** @todo AMD IBS. */
4166 *puValue = 0;
4167 return VINF_SUCCESS;
4168}
4169
4170
4171/** @callback_method_impl{FNCPUMWRMSR} */
4172static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4173{
4174 /** @todo AMD IBS. */
4175 return VINF_SUCCESS;
4176}
4177
4178
4179/** @callback_method_impl{FNCPUMRDMSR} */
4180static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4181{
4182 /** @todo AMD IBS. */
4183 *puValue = 0;
4184 return VINF_SUCCESS;
4185}
4186
4187
4188/** @callback_method_impl{FNCPUMWRMSR} */
4189static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4190{
4191 /** @todo AMD IBS. */
4192 return VINF_SUCCESS;
4193}
4194
4195
4196/** @callback_method_impl{FNCPUMRDMSR} */
4197static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4198{
4199 /** @todo AMD IBS. */
4200 *puValue = 0;
4201 return VINF_SUCCESS;
4202}
4203
4204
4205/** @callback_method_impl{FNCPUMWRMSR} */
4206static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsFetchPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4207{
4208 /** @todo AMD IBS. */
4209 return VINF_SUCCESS;
4210}
4211
4212
4213/** @callback_method_impl{FNCPUMRDMSR} */
4214static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4215{
4216 /** @todo AMD IBS. */
4217 *puValue = 0;
4218 return VINF_SUCCESS;
4219}
4220
4221
4222/** @callback_method_impl{FNCPUMWRMSR} */
4223static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpExecCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4224{
4225 /** @todo AMD IBS. */
4226 return VINF_SUCCESS;
4227}
4228
4229
4230/** @callback_method_impl{FNCPUMRDMSR} */
4231static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4232{
4233 /** @todo AMD IBS. */
4234 *puValue = 0;
4235 return VINF_SUCCESS;
4236}
4237
4238
4239/** @callback_method_impl{FNCPUMWRMSR} */
4240static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpRip(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4241{
4242 /** @todo AMD IBS. */
4243 if (!X86_IS_CANONICAL(uValue))
4244 {
4245 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4246 return VERR_CPUM_RAISE_GP_0;
4247 }
4248 return VINF_SUCCESS;
4249}
4250
4251
4252/** @callback_method_impl{FNCPUMRDMSR} */
4253static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4254{
4255 /** @todo AMD IBS. */
4256 *puValue = 0;
4257 return VINF_SUCCESS;
4258}
4259
4260
4261/** @callback_method_impl{FNCPUMWRMSR} */
4262static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4263{
4264 /** @todo AMD IBS. */
4265 return VINF_SUCCESS;
4266}
4267
4268
4269/** @callback_method_impl{FNCPUMRDMSR} */
4270static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4271{
4272 /** @todo AMD IBS. */
4273 *puValue = 0;
4274 return VINF_SUCCESS;
4275}
4276
4277
4278/** @callback_method_impl{FNCPUMWRMSR} */
4279static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4280{
4281 /** @todo AMD IBS. */
4282 return VINF_SUCCESS;
4283}
4284
4285
4286/** @callback_method_impl{FNCPUMRDMSR} */
4287static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4288{
4289 /** @todo AMD IBS. */
4290 *puValue = 0;
4291 return VINF_SUCCESS;
4292}
4293
4294
4295/** @callback_method_impl{FNCPUMWRMSR} */
4296static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsOpData3(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4297{
4298 /** @todo AMD IBS. */
4299 return VINF_SUCCESS;
4300}
4301
4302
4303/** @callback_method_impl{FNCPUMRDMSR} */
4304static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4305{
4306 /** @todo AMD IBS. */
4307 *puValue = 0;
4308 return VINF_SUCCESS;
4309}
4310
4311
4312/** @callback_method_impl{FNCPUMWRMSR} */
4313static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcLinAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4314{
4315 /** @todo AMD IBS. */
4316 if (!X86_IS_CANONICAL(uValue))
4317 {
4318 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4319 return VERR_CPUM_RAISE_GP_0;
4320 }
4321 return VINF_SUCCESS;
4322}
4323
4324
4325/** @callback_method_impl{FNCPUMRDMSR} */
4326static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4327{
4328 /** @todo AMD IBS. */
4329 *puValue = 0;
4330 return VINF_SUCCESS;
4331}
4332
4333
4334/** @callback_method_impl{FNCPUMWRMSR} */
4335static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsDcPhysAddr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4336{
4337 /** @todo AMD IBS. */
4338 return VINF_SUCCESS;
4339}
4340
4341
4342/** @callback_method_impl{FNCPUMRDMSR} */
4343static DECLCALLBACK(int) cpumMsrRd_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4344{
4345 /** @todo AMD IBS. */
4346 *puValue = 0;
4347 return VINF_SUCCESS;
4348}
4349
4350
4351/** @callback_method_impl{FNCPUMWRMSR} */
4352static DECLCALLBACK(int) cpumMsrWr_AmdFam10hIbsCtl(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4353{
4354 /** @todo AMD IBS. */
4355 return VINF_SUCCESS;
4356}
4357
4358
4359/** @callback_method_impl{FNCPUMRDMSR} */
4360static DECLCALLBACK(int) cpumMsrRd_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
4361{
4362 /** @todo AMD IBS. */
4363 *puValue = 0;
4364 return VINF_SUCCESS;
4365}
4366
4367
4368/** @callback_method_impl{FNCPUMWRMSR} */
4369static DECLCALLBACK(int) cpumMsrWr_AmdFam14hIbsBrTarget(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue)
4370{
4371 /** @todo AMD IBS. */
4372 if (!X86_IS_CANONICAL(uValue))
4373 {
4374 Log(("CPUM: wrmsr %s(%#x), %#llx -> %#GP - not canonical\n", pRange->szName, idMsr, uValue));
4375 return VERR_CPUM_RAISE_GP_0;
4376 }
4377 return VINF_SUCCESS;
4378}
4379
4380
4381
4382/**
4383 * MSR read function table.
4384 */
4385static const PFNCPUMRDMSR g_aCpumRdMsrFns[kCpumMsrRdFn_End] =
4386{
4387 NULL, /* Invalid */
4388 cpumMsrRd_FixedValue,
4389 NULL, /* Alias */
4390 cpumMsrRd_WriteOnly,
4391 cpumMsrRd_Ia32P5McAddr,
4392 cpumMsrRd_Ia32P5McType,
4393 cpumMsrRd_Ia32TimestampCounter,
4394 cpumMsrRd_Ia32PlatformId,
4395 cpumMsrRd_Ia32ApicBase,
4396 cpumMsrRd_Ia32FeatureControl,
4397 cpumMsrRd_Ia32BiosSignId,
4398 cpumMsrRd_Ia32SmmMonitorCtl,
4399 cpumMsrRd_Ia32PmcN,
4400 cpumMsrRd_Ia32MonitorFilterLineSize,
4401 cpumMsrRd_Ia32MPerf,
4402 cpumMsrRd_Ia32APerf,
4403 cpumMsrRd_Ia32MtrrCap,
4404 cpumMsrRd_Ia32MtrrPhysBaseN,
4405 cpumMsrRd_Ia32MtrrPhysMaskN,
4406 cpumMsrRd_Ia32MtrrFixed,
4407 cpumMsrRd_Ia32MtrrDefType,
4408 cpumMsrRd_Ia32Pat,
4409 cpumMsrRd_Ia32SysEnterCs,
4410 cpumMsrRd_Ia32SysEnterEsp,
4411 cpumMsrRd_Ia32SysEnterEip,
4412 cpumMsrRd_Ia32McgCap,
4413 cpumMsrRd_Ia32McgStatus,
4414 cpumMsrRd_Ia32McgCtl,
4415 cpumMsrRd_Ia32DebugCtl,
4416 cpumMsrRd_Ia32SmrrPhysBase,
4417 cpumMsrRd_Ia32SmrrPhysMask,
4418 cpumMsrRd_Ia32PlatformDcaCap,
4419 cpumMsrRd_Ia32CpuDcaCap,
4420 cpumMsrRd_Ia32Dca0Cap,
4421 cpumMsrRd_Ia32PerfEvtSelN,
4422 cpumMsrRd_Ia32PerfStatus,
4423 cpumMsrRd_Ia32PerfCtl,
4424 cpumMsrRd_Ia32FixedCtrN,
4425 cpumMsrRd_Ia32PerfCapabilities,
4426 cpumMsrRd_Ia32FixedCtrCtrl,
4427 cpumMsrRd_Ia32PerfGlobalStatus,
4428 cpumMsrRd_Ia32PerfGlobalCtrl,
4429 cpumMsrRd_Ia32PerfGlobalOvfCtrl,
4430 cpumMsrRd_Ia32PebsEnable,
4431 cpumMsrRd_Ia32ClockModulation,
4432 cpumMsrRd_Ia32ThermInterrupt,
4433 cpumMsrRd_Ia32ThermStatus,
4434 cpumMsrRd_Ia32Therm2Ctl,
4435 cpumMsrRd_Ia32MiscEnable,
4436 cpumMsrRd_Ia32McCtlStatusAddrMiscN,
4437 cpumMsrRd_Ia32McNCtl2,
4438 cpumMsrRd_Ia32DsArea,
4439 cpumMsrRd_Ia32TscDeadline,
4440 cpumMsrRd_Ia32X2ApicN,
4441 cpumMsrRd_Ia32DebugInterface,
4442 cpumMsrRd_Ia32VmxBase,
4443 cpumMsrRd_Ia32VmxPinbasedCtls,
4444 cpumMsrRd_Ia32VmxProcbasedCtls,
4445 cpumMsrRd_Ia32VmxExitCtls,
4446 cpumMsrRd_Ia32VmxEntryCtls,
4447 cpumMsrRd_Ia32VmxMisc,
4448 cpumMsrRd_Ia32VmxCr0Fixed0,
4449 cpumMsrRd_Ia32VmxCr0Fixed1,
4450 cpumMsrRd_Ia32VmxCr4Fixed0,
4451 cpumMsrRd_Ia32VmxCr4Fixed1,
4452 cpumMsrRd_Ia32VmxVmcsEnum,
4453 cpumMsrRd_Ia32VmxProcBasedCtls2,
4454 cpumMsrRd_Ia32VmxEptVpidCap,
4455 cpumMsrRd_Ia32VmxTruePinbasedCtls,
4456 cpumMsrRd_Ia32VmxTrueProcbasedCtls,
4457 cpumMsrRd_Ia32VmxTrueExitCtls,
4458 cpumMsrRd_Ia32VmxTrueEntryCtls,
4459
4460 cpumMsrRd_Amd64Efer,
4461 cpumMsrRd_Amd64SyscallTarget,
4462 cpumMsrRd_Amd64LongSyscallTarget,
4463 cpumMsrRd_Amd64CompSyscallTarget,
4464 cpumMsrRd_Amd64SyscallFlagMask,
4465 cpumMsrRd_Amd64FsBase,
4466 cpumMsrRd_Amd64GsBase,
4467 cpumMsrRd_Amd64KernelGsBase,
4468 cpumMsrRd_Amd64TscAux,
4469
4470 cpumMsrRd_IntelEblCrPowerOn,
4471 cpumMsrRd_IntelI7CoreThreadCount,
4472 cpumMsrRd_IntelP4EbcHardPowerOn,
4473 cpumMsrRd_IntelP4EbcSoftPowerOn,
4474 cpumMsrRd_IntelP4EbcFrequencyId,
4475 cpumMsrRd_IntelP6FsbFrequency,
4476 cpumMsrRd_IntelPlatformInfo,
4477 cpumMsrRd_IntelFlexRatio,
4478 cpumMsrRd_IntelPkgCStConfigControl,
4479 cpumMsrRd_IntelPmgIoCaptureBase,
4480 cpumMsrRd_IntelLastBranchFromToN,
4481 cpumMsrRd_IntelLastBranchFromN,
4482 cpumMsrRd_IntelLastBranchToN,
4483 cpumMsrRd_IntelLastBranchTos,
4484 cpumMsrRd_IntelBblCrCtl,
4485 cpumMsrRd_IntelBblCrCtl3,
4486 cpumMsrRd_IntelI7TemperatureTarget,
4487 cpumMsrRd_IntelI7MsrOffCoreResponseN,
4488 cpumMsrRd_IntelI7MiscPwrMgmt,
4489 cpumMsrRd_IntelP6CrN,
4490 cpumMsrRd_IntelCpuId1FeatureMaskEcdx,
4491 cpumMsrRd_IntelCpuId1FeatureMaskEax,
4492 cpumMsrRd_IntelCpuId80000001FeatureMaskEcdx,
4493 cpumMsrRd_IntelI7SandyAesNiCtl,
4494 cpumMsrRd_IntelI7TurboRatioLimit,
4495 cpumMsrRd_IntelI7LbrSelect,
4496 cpumMsrRd_IntelI7SandyErrorControl,
4497 cpumMsrRd_IntelI7VirtualLegacyWireCap,
4498 cpumMsrRd_IntelI7PowerCtl,
4499 cpumMsrRd_IntelI7SandyPebsNumAlt,
4500 cpumMsrRd_IntelI7PebsLdLat,
4501 cpumMsrRd_IntelI7PkgCnResidencyN,
4502 cpumMsrRd_IntelI7CoreCnResidencyN,
4503 cpumMsrRd_IntelI7SandyVrCurrentConfig,
4504 cpumMsrRd_IntelI7SandyVrMiscConfig,
4505 cpumMsrRd_IntelI7SandyRaplPowerUnit,
4506 cpumMsrRd_IntelI7SandyPkgCnIrtlN,
4507 cpumMsrRd_IntelI7SandyPkgC2Residency,
4508 cpumMsrRd_IntelI7RaplPkgPowerLimit,
4509 cpumMsrRd_IntelI7RaplPkgEnergyStatus,
4510 cpumMsrRd_IntelI7RaplPkgPerfStatus,
4511 cpumMsrRd_IntelI7RaplPkgPowerInfo,
4512 cpumMsrRd_IntelI7RaplDramPowerLimit,
4513 cpumMsrRd_IntelI7RaplDramEnergyStatus,
4514 cpumMsrRd_IntelI7RaplDramPerfStatus,
4515 cpumMsrRd_IntelI7RaplDramPowerInfo,
4516 cpumMsrRd_IntelI7RaplPp0PowerLimit,
4517 cpumMsrRd_IntelI7RaplPp0EnergyStatus,
4518 cpumMsrRd_IntelI7RaplPp0Policy,
4519 cpumMsrRd_IntelI7RaplPp0PerfStatus,
4520 cpumMsrRd_IntelI7RaplPp1PowerLimit,
4521 cpumMsrRd_IntelI7RaplPp1EnergyStatus,
4522 cpumMsrRd_IntelI7RaplPp1Policy,
4523 cpumMsrRd_IntelI7IvyConfigTdpNominal,
4524 cpumMsrRd_IntelI7IvyConfigTdpLevel1,
4525 cpumMsrRd_IntelI7IvyConfigTdpLevel2,
4526 cpumMsrRd_IntelI7IvyConfigTdpControl,
4527 cpumMsrRd_IntelI7IvyTurboActivationRatio,
4528 cpumMsrRd_IntelI7UncPerfGlobalCtrl,
4529 cpumMsrRd_IntelI7UncPerfGlobalStatus,
4530 cpumMsrRd_IntelI7UncPerfGlobalOvfCtrl,
4531 cpumMsrRd_IntelI7UncPerfFixedCtrCtrl,
4532 cpumMsrRd_IntelI7UncPerfFixedCtr,
4533 cpumMsrRd_IntelI7UncCBoxConfig,
4534 cpumMsrRd_IntelI7UncArbPerfCtrN,
4535 cpumMsrRd_IntelI7UncArbPerfEvtSelN,
4536 cpumMsrRd_IntelCore2EmttmCrTablesN,
4537 cpumMsrRd_IntelCore2SmmCStMiscInfo,
4538 cpumMsrRd_IntelCore1ExtConfig,
4539 cpumMsrRd_IntelCore1DtsCalControl,
4540 cpumMsrRd_IntelCore2PeciControl,
4541
4542 cpumMsrRd_P6LastBranchFromIp,
4543 cpumMsrRd_P6LastBranchToIp,
4544 cpumMsrRd_P6LastIntFromIp,
4545 cpumMsrRd_P6LastIntToIp,
4546
4547 cpumMsrRd_AmdFam15hTscRate,
4548 cpumMsrRd_AmdFam15hLwpCfg,
4549 cpumMsrRd_AmdFam15hLwpCbAddr,
4550 cpumMsrRd_AmdFam10hMc4MiscN,
4551 cpumMsrRd_AmdK8PerfCtlN,
4552 cpumMsrRd_AmdK8PerfCtrN,
4553 cpumMsrRd_AmdK8SysCfg,
4554 cpumMsrRd_AmdK8HwCr,
4555 cpumMsrRd_AmdK8IorrBaseN,
4556 cpumMsrRd_AmdK8IorrMaskN,
4557 cpumMsrRd_AmdK8TopOfMemN,
4558 cpumMsrRd_AmdK8NbCfg1,
4559 cpumMsrRd_AmdK8McXcptRedir,
4560 cpumMsrRd_AmdK8CpuNameN,
4561 cpumMsrRd_AmdK8HwThermalCtrl,
4562 cpumMsrRd_AmdK8SwThermalCtrl,
4563 cpumMsrRd_AmdK8FidVidControl,
4564 cpumMsrRd_AmdK8FidVidStatus,
4565 cpumMsrRd_AmdK8McCtlMaskN,
4566 cpumMsrRd_AmdK8SmiOnIoTrapN,
4567 cpumMsrRd_AmdK8SmiOnIoTrapCtlSts,
4568 cpumMsrRd_AmdK8IntPendingMessage,
4569 cpumMsrRd_AmdK8SmiTriggerIoCycle,
4570 cpumMsrRd_AmdFam10hMmioCfgBaseAddr,
4571 cpumMsrRd_AmdFam10hTrapCtlMaybe,
4572 cpumMsrRd_AmdFam10hPStateCurLimit,
4573 cpumMsrRd_AmdFam10hPStateControl,
4574 cpumMsrRd_AmdFam10hPStateStatus,
4575 cpumMsrRd_AmdFam10hPStateN,
4576 cpumMsrRd_AmdFam10hCofVidControl,
4577 cpumMsrRd_AmdFam10hCofVidStatus,
4578 cpumMsrRd_AmdFam10hCStateIoBaseAddr,
4579 cpumMsrRd_AmdFam10hCpuWatchdogTimer,
4580 cpumMsrRd_AmdK8SmmBase,
4581 cpumMsrRd_AmdK8SmmAddr,
4582 cpumMsrRd_AmdK8SmmMask,
4583 cpumMsrRd_AmdK8VmCr,
4584 cpumMsrRd_AmdK8IgnNe,
4585 cpumMsrRd_AmdK8SmmCtl,
4586 cpumMsrRd_AmdK8VmHSavePa,
4587 cpumMsrRd_AmdFam10hVmLockKey,
4588 cpumMsrRd_AmdFam10hSmmLockKey,
4589 cpumMsrRd_AmdFam10hLocalSmiStatus,
4590 cpumMsrRd_AmdFam10hOsVisWrkIdLength,
4591 cpumMsrRd_AmdFam10hOsVisWrkStatus,
4592 cpumMsrRd_AmdFam16hL2IPerfCtlN,
4593 cpumMsrRd_AmdFam16hL2IPerfCtrN,
4594 cpumMsrRd_AmdFam15hNorthbridgePerfCtlN,
4595 cpumMsrRd_AmdFam15hNorthbridgePerfCtrN,
4596 cpumMsrRd_AmdK7MicrocodeCtl,
4597 cpumMsrRd_AmdK7ClusterIdMaybe,
4598 cpumMsrRd_AmdK8CpuIdCtlStd07hEbax,
4599 cpumMsrRd_AmdK8CpuIdCtlStd06hEcx,
4600 cpumMsrRd_AmdK8CpuIdCtlStd01hEdcx,
4601 cpumMsrRd_AmdK8CpuIdCtlExt01hEdcx,
4602 cpumMsrRd_AmdK8PatchLevel,
4603 cpumMsrRd_AmdK7DebugStatusMaybe,
4604 cpumMsrRd_AmdK7BHTraceBaseMaybe,
4605 cpumMsrRd_AmdK7BHTracePtrMaybe,
4606 cpumMsrRd_AmdK7BHTraceLimitMaybe,
4607 cpumMsrRd_AmdK7HardwareDebugToolCfgMaybe,
4608 cpumMsrRd_AmdK7FastFlushCountMaybe,
4609 cpumMsrRd_AmdK7NodeId,
4610 cpumMsrRd_AmdK7DrXAddrMaskN,
4611 cpumMsrRd_AmdK7Dr0DataMatchMaybe,
4612 cpumMsrRd_AmdK7Dr0DataMaskMaybe,
4613 cpumMsrRd_AmdK7LoadStoreCfg,
4614 cpumMsrRd_AmdK7InstrCacheCfg,
4615 cpumMsrRd_AmdK7DataCacheCfg,
4616 cpumMsrRd_AmdK7BusUnitCfg,
4617 cpumMsrRd_AmdK7DebugCtl2Maybe,
4618 cpumMsrRd_AmdFam15hFpuCfg,
4619 cpumMsrRd_AmdFam15hDecoderCfg,
4620 cpumMsrRd_AmdFam10hBusUnitCfg2,
4621 cpumMsrRd_AmdFam15hCombUnitCfg,
4622 cpumMsrRd_AmdFam15hCombUnitCfg2,
4623 cpumMsrRd_AmdFam15hCombUnitCfg3,
4624 cpumMsrRd_AmdFam15hExecUnitCfg,
4625 cpumMsrRd_AmdFam15hLoadStoreCfg2,
4626 cpumMsrRd_AmdFam10hIbsFetchCtl,
4627 cpumMsrRd_AmdFam10hIbsFetchLinAddr,
4628 cpumMsrRd_AmdFam10hIbsFetchPhysAddr,
4629 cpumMsrRd_AmdFam10hIbsOpExecCtl,
4630 cpumMsrRd_AmdFam10hIbsOpRip,
4631 cpumMsrRd_AmdFam10hIbsOpData,
4632 cpumMsrRd_AmdFam10hIbsOpData2,
4633 cpumMsrRd_AmdFam10hIbsOpData3,
4634 cpumMsrRd_AmdFam10hIbsDcLinAddr,
4635 cpumMsrRd_AmdFam10hIbsDcPhysAddr,
4636 cpumMsrRd_AmdFam10hIbsCtl,
4637 cpumMsrRd_AmdFam14hIbsBrTarget,
4638};
4639
4640
4641/**
4642 * MSR write function table.
4643 */
4644static const PFNCPUMWRMSR g_aCpumWrMsrFns[kCpumMsrWrFn_End] =
4645{
4646 NULL, /* Invalid */
4647 cpumMsrWr_IgnoreWrite,
4648 cpumMsrWr_ReadOnly,
4649 NULL, /* Alias */
4650 cpumMsrWr_Ia32P5McAddr,
4651 cpumMsrWr_Ia32P5McType,
4652 cpumMsrWr_Ia32TimestampCounter,
4653 cpumMsrWr_Ia32ApicBase,
4654 cpumMsrWr_Ia32FeatureControl,
4655 cpumMsrWr_Ia32BiosSignId,
4656 cpumMsrWr_Ia32BiosUpdateTrigger,
4657 cpumMsrWr_Ia32SmmMonitorCtl,
4658 cpumMsrWr_Ia32PmcN,
4659 cpumMsrWr_Ia32MonitorFilterLineSize,
4660 cpumMsrWr_Ia32MPerf,
4661 cpumMsrWr_Ia32APerf,
4662 cpumMsrWr_Ia32MtrrPhysBaseN,
4663 cpumMsrWr_Ia32MtrrPhysMaskN,
4664 cpumMsrWr_Ia32MtrrFixed,
4665 cpumMsrWr_Ia32MtrrDefType,
4666 cpumMsrWr_Ia32Pat,
4667 cpumMsrWr_Ia32SysEnterCs,
4668 cpumMsrWr_Ia32SysEnterEsp,
4669 cpumMsrWr_Ia32SysEnterEip,
4670 cpumMsrWr_Ia32McgStatus,
4671 cpumMsrWr_Ia32McgCtl,
4672 cpumMsrWr_Ia32DebugCtl,
4673 cpumMsrWr_Ia32SmrrPhysBase,
4674 cpumMsrWr_Ia32SmrrPhysMask,
4675 cpumMsrWr_Ia32PlatformDcaCap,
4676 cpumMsrWr_Ia32Dca0Cap,
4677 cpumMsrWr_Ia32PerfEvtSelN,
4678 cpumMsrWr_Ia32PerfStatus,
4679 cpumMsrWr_Ia32PerfCtl,
4680 cpumMsrWr_Ia32FixedCtrN,
4681 cpumMsrWr_Ia32PerfCapabilities,
4682 cpumMsrWr_Ia32FixedCtrCtrl,
4683 cpumMsrWr_Ia32PerfGlobalStatus,
4684 cpumMsrWr_Ia32PerfGlobalCtrl,
4685 cpumMsrWr_Ia32PerfGlobalOvfCtrl,
4686 cpumMsrWr_Ia32PebsEnable,
4687 cpumMsrWr_Ia32ClockModulation,
4688 cpumMsrWr_Ia32ThermInterrupt,
4689 cpumMsrWr_Ia32ThermStatus,
4690 cpumMsrWr_Ia32Therm2Ctl,
4691 cpumMsrWr_Ia32MiscEnable,
4692 cpumMsrWr_Ia32McCtlStatusAddrMiscN,
4693 cpumMsrWr_Ia32McNCtl2,
4694 cpumMsrWr_Ia32DsArea,
4695 cpumMsrWr_Ia32TscDeadline,
4696 cpumMsrWr_Ia32X2ApicN,
4697 cpumMsrWr_Ia32DebugInterface,
4698
4699 cpumMsrWr_Amd64Efer,
4700 cpumMsrWr_Amd64SyscallTarget,
4701 cpumMsrWr_Amd64LongSyscallTarget,
4702 cpumMsrWr_Amd64CompSyscallTarget,
4703 cpumMsrWr_Amd64SyscallFlagMask,
4704 cpumMsrWr_Amd64FsBase,
4705 cpumMsrWr_Amd64GsBase,
4706 cpumMsrWr_Amd64KernelGsBase,
4707 cpumMsrWr_Amd64TscAux,
4708
4709 cpumMsrWr_IntelEblCrPowerOn,
4710 cpumMsrWr_IntelP4EbcHardPowerOn,
4711 cpumMsrWr_IntelP4EbcSoftPowerOn,
4712 cpumMsrWr_IntelP4EbcFrequencyId,
4713 cpumMsrWr_IntelFlexRatio,
4714 cpumMsrWr_IntelPkgCStConfigControl,
4715 cpumMsrWr_IntelPmgIoCaptureBase,
4716 cpumMsrWr_IntelLastBranchFromToN,
4717 cpumMsrWr_IntelLastBranchFromN,
4718 cpumMsrWr_IntelLastBranchToN,
4719 cpumMsrWr_IntelLastBranchTos,
4720 cpumMsrWr_IntelBblCrCtl,
4721 cpumMsrWr_IntelBblCrCtl3,
4722 cpumMsrWr_IntelI7TemperatureTarget,
4723 cpumMsrWr_IntelI7MsrOffCoreResponseN,
4724 cpumMsrWr_IntelI7MiscPwrMgmt,
4725 cpumMsrWr_IntelP6CrN,
4726 cpumMsrWr_IntelCpuId1FeatureMaskEcdx,
4727 cpumMsrWr_IntelCpuId1FeatureMaskEax,
4728 cpumMsrWr_IntelCpuId80000001FeatureMaskEcdx,
4729 cpumMsrWr_IntelI7SandyAesNiCtl,
4730 cpumMsrWr_IntelI7TurboRatioLimit,
4731 cpumMsrWr_IntelI7LbrSelect,
4732 cpumMsrWr_IntelI7SandyErrorControl,
4733 cpumMsrWr_IntelI7PowerCtl,
4734 cpumMsrWr_IntelI7SandyPebsNumAlt,
4735 cpumMsrWr_IntelI7PebsLdLat,
4736 cpumMsrWr_IntelI7SandyVrCurrentConfig,
4737 cpumMsrWr_IntelI7SandyVrMiscConfig,
4738 cpumMsrWr_IntelI7SandyPkgCnIrtlN,
4739 cpumMsrWr_IntelI7RaplPkgPowerLimit,
4740 cpumMsrWr_IntelI7RaplDramPowerLimit,
4741 cpumMsrWr_IntelI7RaplPp0PowerLimit,
4742 cpumMsrWr_IntelI7RaplPp0Policy,
4743 cpumMsrWr_IntelI7RaplPp1PowerLimit,
4744 cpumMsrWr_IntelI7RaplPp1Policy,
4745 cpumMsrWr_IntelI7IvyConfigTdpControl,
4746 cpumMsrWr_IntelI7IvyTurboActivationRatio,
4747 cpumMsrWr_IntelI7UncPerfGlobalCtrl,
4748 cpumMsrWr_IntelI7UncPerfGlobalStatus,
4749 cpumMsrWr_IntelI7UncPerfGlobalOvfCtrl,
4750 cpumMsrWr_IntelI7UncPerfFixedCtrCtrl,
4751 cpumMsrWr_IntelI7UncPerfFixedCtr,
4752 cpumMsrWr_IntelI7UncArbPerfCtrN,
4753 cpumMsrWr_IntelI7UncArbPerfEvtSelN,
4754 cpumMsrWr_IntelCore2EmttmCrTablesN,
4755 cpumMsrWr_IntelCore2SmmCStMiscInfo,
4756 cpumMsrWr_IntelCore1ExtConfig,
4757 cpumMsrWr_IntelCore1DtsCalControl,
4758 cpumMsrWr_IntelCore2PeciControl,
4759
4760 cpumMsrWr_P6LastIntFromIp,
4761 cpumMsrWr_P6LastIntToIp,
4762
4763 cpumMsrWr_AmdFam15hTscRate,
4764 cpumMsrWr_AmdFam15hLwpCfg,
4765 cpumMsrWr_AmdFam15hLwpCbAddr,
4766 cpumMsrWr_AmdFam10hMc4MiscN,
4767 cpumMsrWr_AmdK8PerfCtlN,
4768 cpumMsrWr_AmdK8PerfCtrN,
4769 cpumMsrWr_AmdK8SysCfg,
4770 cpumMsrWr_AmdK8HwCr,
4771 cpumMsrWr_AmdK8IorrBaseN,
4772 cpumMsrWr_AmdK8IorrMaskN,
4773 cpumMsrWr_AmdK8TopOfMemN,
4774 cpumMsrWr_AmdK8NbCfg1,
4775 cpumMsrWr_AmdK8McXcptRedir,
4776 cpumMsrWr_AmdK8CpuNameN,
4777 cpumMsrWr_AmdK8HwThermalCtrl,
4778 cpumMsrWr_AmdK8SwThermalCtrl,
4779 cpumMsrWr_AmdK8FidVidControl,
4780 cpumMsrWr_AmdK8McCtlMaskN,
4781 cpumMsrWr_AmdK8SmiOnIoTrapN,
4782 cpumMsrWr_AmdK8SmiOnIoTrapCtlSts,
4783 cpumMsrWr_AmdK8IntPendingMessage,
4784 cpumMsrWr_AmdK8SmiTriggerIoCycle,
4785 cpumMsrWr_AmdFam10hMmioCfgBaseAddr,
4786 cpumMsrWr_AmdFam10hTrapCtlMaybe,
4787 cpumMsrWr_AmdFam10hPStateControl,
4788 cpumMsrWr_AmdFam10hPStateStatus,
4789 cpumMsrWr_AmdFam10hPStateN,
4790 cpumMsrWr_AmdFam10hCofVidControl,
4791 cpumMsrWr_AmdFam10hCofVidStatus,
4792 cpumMsrWr_AmdFam10hCStateIoBaseAddr,
4793 cpumMsrWr_AmdFam10hCpuWatchdogTimer,
4794 cpumMsrWr_AmdK8SmmBase,
4795 cpumMsrWr_AmdK8SmmAddr,
4796 cpumMsrWr_AmdK8SmmMask,
4797 cpumMsrWr_AmdK8VmCr,
4798 cpumMsrWr_AmdK8IgnNe,
4799 cpumMsrWr_AmdK8SmmCtl,
4800 cpumMsrWr_AmdK8VmHSavePa,
4801 cpumMsrWr_AmdFam10hVmLockKey,
4802 cpumMsrWr_AmdFam10hSmmLockKey,
4803 cpumMsrWr_AmdFam10hLocalSmiStatus,
4804 cpumMsrWr_AmdFam10hOsVisWrkIdLength,
4805 cpumMsrWr_AmdFam10hOsVisWrkStatus,
4806 cpumMsrWr_AmdFam16hL2IPerfCtlN,
4807 cpumMsrWr_AmdFam16hL2IPerfCtrN,
4808 cpumMsrWr_AmdFam15hNorthbridgePerfCtlN,
4809 cpumMsrWr_AmdFam15hNorthbridgePerfCtrN,
4810 cpumMsrWr_AmdK7MicrocodeCtl,
4811 cpumMsrWr_AmdK7ClusterIdMaybe,
4812 cpumMsrWr_AmdK8CpuIdCtlStd07hEbax,
4813 cpumMsrWr_AmdK8CpuIdCtlStd06hEcx,
4814 cpumMsrWr_AmdK8CpuIdCtlStd01hEdcx,
4815 cpumMsrWr_AmdK8CpuIdCtlExt01hEdcx,
4816 cpumMsrWr_AmdK8PatchLoader,
4817 cpumMsrWr_AmdK7DebugStatusMaybe,
4818 cpumMsrWr_AmdK7BHTraceBaseMaybe,
4819 cpumMsrWr_AmdK7BHTracePtrMaybe,
4820 cpumMsrWr_AmdK7BHTraceLimitMaybe,
4821 cpumMsrWr_AmdK7HardwareDebugToolCfgMaybe,
4822 cpumMsrWr_AmdK7FastFlushCountMaybe,
4823 cpumMsrWr_AmdK7NodeId,
4824 cpumMsrWr_AmdK7DrXAddrMaskN,
4825 cpumMsrWr_AmdK7Dr0DataMatchMaybe,
4826 cpumMsrWr_AmdK7Dr0DataMaskMaybe,
4827 cpumMsrWr_AmdK7LoadStoreCfg,
4828 cpumMsrWr_AmdK7InstrCacheCfg,
4829 cpumMsrWr_AmdK7DataCacheCfg,
4830 cpumMsrWr_AmdK7BusUnitCfg,
4831 cpumMsrWr_AmdK7DebugCtl2Maybe,
4832 cpumMsrWr_AmdFam15hFpuCfg,
4833 cpumMsrWr_AmdFam15hDecoderCfg,
4834 cpumMsrWr_AmdFam10hBusUnitCfg2,
4835 cpumMsrWr_AmdFam15hCombUnitCfg,
4836 cpumMsrWr_AmdFam15hCombUnitCfg2,
4837 cpumMsrWr_AmdFam15hCombUnitCfg3,
4838 cpumMsrWr_AmdFam15hExecUnitCfg,
4839 cpumMsrWr_AmdFam15hLoadStoreCfg2,
4840 cpumMsrWr_AmdFam10hIbsFetchCtl,
4841 cpumMsrWr_AmdFam10hIbsFetchLinAddr,
4842 cpumMsrWr_AmdFam10hIbsFetchPhysAddr,
4843 cpumMsrWr_AmdFam10hIbsOpExecCtl,
4844 cpumMsrWr_AmdFam10hIbsOpRip,
4845 cpumMsrWr_AmdFam10hIbsOpData,
4846 cpumMsrWr_AmdFam10hIbsOpData2,
4847 cpumMsrWr_AmdFam10hIbsOpData3,
4848 cpumMsrWr_AmdFam10hIbsDcLinAddr,
4849 cpumMsrWr_AmdFam10hIbsDcPhysAddr,
4850 cpumMsrWr_AmdFam10hIbsCtl,
4851 cpumMsrWr_AmdFam14hIbsBrTarget,
4852};
4853
4854
4855/**
4856 * Looks up the range for the given MSR.
4857 *
4858 * @returns Pointer to the range if found, NULL if not.
4859 * @param pVM The cross context VM structure.
4860 * @param idMsr The MSR to look up.
4861 */
4862# ifndef IN_RING3
4863static
4864# endif
4865PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr)
4866{
4867 /*
4868 * Binary lookup.
4869 */
4870 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
4871 if (!cRanges)
4872 return NULL;
4873 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4874 for (;;)
4875 {
4876 uint32_t i = cRanges / 2;
4877 if (idMsr < paRanges[i].uFirst)
4878 {
4879 if (i == 0)
4880 break;
4881 cRanges = i;
4882 }
4883 else if (idMsr > paRanges[i].uLast)
4884 {
4885 i++;
4886 if (i >= cRanges)
4887 break;
4888 cRanges -= i;
4889 paRanges = &paRanges[i];
4890 }
4891 else
4892 {
4893 if (paRanges[i].enmRdFn == kCpumMsrRdFn_MsrAlias)
4894 return cpumLookupMsrRange(pVM, paRanges[i].uValue);
4895 return &paRanges[i];
4896 }
4897 }
4898
4899# ifdef VBOX_STRICT
4900 /*
4901 * Linear lookup to verify the above binary search.
4902 */
4903 uint32_t cLeft = pVM->cpum.s.GuestInfo.cMsrRanges;
4904 PCPUMMSRRANGE pCur = pVM->cpum.s.GuestInfo.CTX_SUFF(paMsrRanges);
4905 while (cLeft-- > 0)
4906 {
4907 if (idMsr >= pCur->uFirst && idMsr <= pCur->uLast)
4908 {
4909 AssertFailed();
4910 if (pCur->enmRdFn == kCpumMsrRdFn_MsrAlias)
4911 return cpumLookupMsrRange(pVM, pCur->uValue);
4912 return pCur;
4913 }
4914 pCur++;
4915 }
4916# endif
4917 return NULL;
4918}
4919
4920#ifdef VBOX_WITH_NEW_MSR_CODE
4921
4922/**
4923 * Query a guest MSR.
4924 *
4925 * The caller is responsible for checking privilege if the call is the result of
4926 * a RDMSR instruction. We'll do the rest.
4927 *
4928 * @retval VINF_SUCCESS on success.
4929 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
4930 * expected to take the appropriate actions. @a *puValue is set to 0.
4931 * @param pVCpu Pointer to the VMCPU.
4932 * @param idMsr The MSR.
4933 * @param puValue Where to return the value.
4934 *
4935 * @remarks This will always return the right values, even when we're in the
4936 * recompiler.
4937 */
4938VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
4939{
4940 *puValue = 0;
4941
4942 int rc;
4943 PVM pVM = pVCpu->CTX_SUFF(pVM);
4944 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
4945 if (pRange)
4946 {
4947 CPUMMSRRDFN enmRdFn = (CPUMMSRRDFN)pRange->enmRdFn;
4948 AssertReturn(enmRdFn > kCpumMsrRdFn_Invalid && enmRdFn < kCpumMsrRdFn_End, VERR_CPUM_IPE_1);
4949
4950 PFNCPUMRDMSR pfnRdMsr = g_aCpumRdMsrFns[enmRdFn];
4951 AssertReturn(pfnRdMsr, VERR_CPUM_IPE_2);
4952
4953 STAM_COUNTER_INC(&pRange->cReads);
4954 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4955
4956 rc = pfnRdMsr(pVCpu, idMsr, pRange, puValue);
4957 if (RT_SUCCESS(rc))
4958 {
4959 Log2(("CPUM: RDMSR %#x (%s) -> %#llx\n", idMsr, pRange->szName, *puValue));
4960 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
4961 }
4962 else if (rc == VERR_CPUM_RAISE_GP_0)
4963 {
4964 Log(("CPUM: RDMSR %#x (%s) -> #GP(0)\n", idMsr, pRange->szName));
4965 STAM_COUNTER_INC(&pRange->cGps);
4966 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsRaiseGp);
4967 }
4968 else
4969 Log(("CPUM: RDMSR %#x (%s) -> rc=%Rrc\n", idMsr, pRange->szName, rc));
4970 }
4971 else
4972 {
4973 Log(("CPUM: Unknown RDMSR %#x -> #GP(0)\n", idMsr));
4974 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReads);
4975 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrReadsUnknown);
4976 rc = VERR_CPUM_RAISE_GP_0;
4977 }
4978 return rc;
4979}
4980
4981
4982/**
4983 * Writes to a guest MSR.
4984 *
4985 * The caller is responsible for checking privilege if the call is the result of
4986 * a WRMSR instruction. We'll do the rest.
4987 *
4988 * @retval VINF_SUCCESS on success.
4989 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
4990 * appropriate actions.
4991 *
4992 * @param pVCpu Pointer to the VMCPU.
4993 * @param idMsr The MSR id.
4994 * @param uValue The value to set.
4995 *
4996 * @remarks Everyone changing MSR values, including the recompiler, shall do it
4997 * by calling this method. This makes sure we have current values and
4998 * that we trigger all the right actions when something changes.
4999 *
5000 * For performance reasons, this actually isn't entirely true for some
5001 * MSRs when in HM mode. The code here and in HM must be aware of
5002 * this.
5003 */
5004VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
5005{
5006 int rc;
5007 PVM pVM = pVCpu->CTX_SUFF(pVM);
5008 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, idMsr);
5009 if (pRange)
5010 {
5011 STAM_COUNTER_INC(&pRange->cWrites);
5012 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5013
5014 if (!(uValue & pRange->fWrGpMask))
5015 {
5016 CPUMMSRWRFN enmWrFn = (CPUMMSRWRFN)pRange->enmWrFn;
5017 AssertReturn(enmWrFn > kCpumMsrWrFn_Invalid && enmWrFn < kCpumMsrWrFn_End, VERR_CPUM_IPE_1);
5018
5019 PFNCPUMWRMSR pfnWrMsr = g_aCpumWrMsrFns[enmWrFn];
5020 AssertReturn(pfnWrMsr, VERR_CPUM_IPE_2);
5021
5022 uint64_t uValueAdjusted = uValue & ~pRange->fWrIgnMask;
5023 if (uValueAdjusted != uValue)
5024 {
5025 STAM_COUNTER_INC(&pRange->cIgnoredBits);
5026 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesToIgnoredBits);
5027 }
5028
5029 rc = pfnWrMsr(pVCpu, idMsr, pRange, uValueAdjusted, uValue);
5030 if (RT_SUCCESS(rc))
5031 {
5032 Log2(("CPUM: WRMSR %#x (%s), %#llx [%#llx]\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5033 AssertMsg(rc == VINF_SUCCESS, ("%Rrc idMsr=%#x\n", rc, idMsr));
5034 }
5035 else if (rc == VERR_CPUM_RAISE_GP_0)
5036 {
5037 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> #GP(0)\n", idMsr, pRange->szName, uValueAdjusted, uValue));
5038 STAM_COUNTER_INC(&pRange->cGps);
5039 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5040 }
5041 else
5042 Log(("CPUM: WRMSR %#x (%s), %#llx [%#llx] -> rc=%Rrc\n", idMsr, pRange->szName, uValueAdjusted, uValue, rc));
5043 }
5044 else
5045 {
5046 Log(("CPUM: WRMSR %#x (%s), %#llx -> #GP(0) - invalid bits %#llx\n",
5047 idMsr, pRange->szName, uValue, uValue & pRange->fWrGpMask));
5048 STAM_COUNTER_INC(&pRange->cGps);
5049 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesRaiseGp);
5050 rc = VERR_CPUM_RAISE_GP_0;
5051 }
5052 }
5053 else
5054 {
5055 Log(("CPUM: Unknown WRMSR %#x, %#llx -> #GP(0)\n", idMsr, uValue));
5056 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWrites);
5057 STAM_REL_COUNTER_INC(&pVM->cpum.s.cMsrWritesUnknown);
5058 rc = VERR_CPUM_RAISE_GP_0;
5059 }
5060 return rc;
5061}
5062
5063#endif /* VBOX_WITH_NEW_MSR_CODE */
5064
5065
5066#if defined(VBOX_STRICT) && defined(IN_RING3)
5067/**
5068 * Performs some checks on the static data related to MSRs.
5069 *
5070 * @returns VINF_SUCCESS on success, error on failure.
5071 */
5072int cpumR3MsrStrictInitChecks(void)
5073{
5074#define CPUM_ASSERT_RD_MSR_FN(a_Register) \
5075 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_##a_Register] == cpumMsrRd_##a_Register, VERR_CPUM_IPE_2);
5076#define CPUM_ASSERT_WR_MSR_FN(a_Register) \
5077 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_##a_Register] == cpumMsrWr_##a_Register, VERR_CPUM_IPE_2);
5078
5079 AssertReturn(g_aCpumRdMsrFns[kCpumMsrRdFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5080 CPUM_ASSERT_RD_MSR_FN(FixedValue);
5081 CPUM_ASSERT_RD_MSR_FN(WriteOnly);
5082 CPUM_ASSERT_RD_MSR_FN(Ia32P5McAddr);
5083 CPUM_ASSERT_RD_MSR_FN(Ia32P5McType);
5084 CPUM_ASSERT_RD_MSR_FN(Ia32TimestampCounter);
5085 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformId);
5086 CPUM_ASSERT_RD_MSR_FN(Ia32ApicBase);
5087 CPUM_ASSERT_RD_MSR_FN(Ia32FeatureControl);
5088 CPUM_ASSERT_RD_MSR_FN(Ia32BiosSignId);
5089 CPUM_ASSERT_RD_MSR_FN(Ia32SmmMonitorCtl);
5090 CPUM_ASSERT_RD_MSR_FN(Ia32PmcN);
5091 CPUM_ASSERT_RD_MSR_FN(Ia32MonitorFilterLineSize);
5092 CPUM_ASSERT_RD_MSR_FN(Ia32MPerf);
5093 CPUM_ASSERT_RD_MSR_FN(Ia32APerf);
5094 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrCap);
5095 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysBaseN);
5096 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrPhysMaskN);
5097 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrFixed);
5098 CPUM_ASSERT_RD_MSR_FN(Ia32MtrrDefType);
5099 CPUM_ASSERT_RD_MSR_FN(Ia32Pat);
5100 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterCs);
5101 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEsp);
5102 CPUM_ASSERT_RD_MSR_FN(Ia32SysEnterEip);
5103 CPUM_ASSERT_RD_MSR_FN(Ia32McgCap);
5104 CPUM_ASSERT_RD_MSR_FN(Ia32McgStatus);
5105 CPUM_ASSERT_RD_MSR_FN(Ia32McgCtl);
5106 CPUM_ASSERT_RD_MSR_FN(Ia32DebugCtl);
5107 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysBase);
5108 CPUM_ASSERT_RD_MSR_FN(Ia32SmrrPhysMask);
5109 CPUM_ASSERT_RD_MSR_FN(Ia32PlatformDcaCap);
5110 CPUM_ASSERT_RD_MSR_FN(Ia32CpuDcaCap);
5111 CPUM_ASSERT_RD_MSR_FN(Ia32Dca0Cap);
5112 CPUM_ASSERT_RD_MSR_FN(Ia32PerfEvtSelN);
5113 CPUM_ASSERT_RD_MSR_FN(Ia32PerfStatus);
5114 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCtl);
5115 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrN);
5116 CPUM_ASSERT_RD_MSR_FN(Ia32PerfCapabilities);
5117 CPUM_ASSERT_RD_MSR_FN(Ia32FixedCtrCtrl);
5118 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalStatus);
5119 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalCtrl);
5120 CPUM_ASSERT_RD_MSR_FN(Ia32PerfGlobalOvfCtrl);
5121 CPUM_ASSERT_RD_MSR_FN(Ia32PebsEnable);
5122 CPUM_ASSERT_RD_MSR_FN(Ia32ClockModulation);
5123 CPUM_ASSERT_RD_MSR_FN(Ia32ThermInterrupt);
5124 CPUM_ASSERT_RD_MSR_FN(Ia32ThermStatus);
5125 CPUM_ASSERT_RD_MSR_FN(Ia32MiscEnable);
5126 CPUM_ASSERT_RD_MSR_FN(Ia32McCtlStatusAddrMiscN);
5127 CPUM_ASSERT_RD_MSR_FN(Ia32McNCtl2);
5128 CPUM_ASSERT_RD_MSR_FN(Ia32DsArea);
5129 CPUM_ASSERT_RD_MSR_FN(Ia32TscDeadline);
5130 CPUM_ASSERT_RD_MSR_FN(Ia32X2ApicN);
5131 CPUM_ASSERT_RD_MSR_FN(Ia32DebugInterface);
5132 CPUM_ASSERT_RD_MSR_FN(Ia32VmxBase);
5133 CPUM_ASSERT_RD_MSR_FN(Ia32VmxPinbasedCtls);
5134 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcbasedCtls);
5135 CPUM_ASSERT_RD_MSR_FN(Ia32VmxExitCtls);
5136 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEntryCtls);
5137 CPUM_ASSERT_RD_MSR_FN(Ia32VmxMisc);
5138 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed0);
5139 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr0Fixed1);
5140 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed0);
5141 CPUM_ASSERT_RD_MSR_FN(Ia32VmxCr4Fixed1);
5142 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmcsEnum);
5143 CPUM_ASSERT_RD_MSR_FN(Ia32VmxProcBasedCtls2);
5144 CPUM_ASSERT_RD_MSR_FN(Ia32VmxEptVpidCap);
5145 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTruePinbasedCtls);
5146 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueProcbasedCtls);
5147 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls);
5148 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls);
5149
5150 CPUM_ASSERT_RD_MSR_FN(Amd64Efer);
5151 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallTarget);
5152 CPUM_ASSERT_RD_MSR_FN(Amd64LongSyscallTarget);
5153 CPUM_ASSERT_RD_MSR_FN(Amd64CompSyscallTarget);
5154 CPUM_ASSERT_RD_MSR_FN(Amd64SyscallFlagMask);
5155 CPUM_ASSERT_RD_MSR_FN(Amd64FsBase);
5156 CPUM_ASSERT_RD_MSR_FN(Amd64GsBase);
5157 CPUM_ASSERT_RD_MSR_FN(Amd64KernelGsBase);
5158 CPUM_ASSERT_RD_MSR_FN(Amd64TscAux);
5159
5160 CPUM_ASSERT_RD_MSR_FN(IntelEblCrPowerOn);
5161 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreThreadCount);
5162 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcHardPowerOn);
5163 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcSoftPowerOn);
5164 CPUM_ASSERT_RD_MSR_FN(IntelP4EbcFrequencyId);
5165 CPUM_ASSERT_RD_MSR_FN(IntelP6FsbFrequency);
5166 CPUM_ASSERT_RD_MSR_FN(IntelPlatformInfo);
5167 CPUM_ASSERT_RD_MSR_FN(IntelFlexRatio);
5168 CPUM_ASSERT_RD_MSR_FN(IntelPkgCStConfigControl);
5169 CPUM_ASSERT_RD_MSR_FN(IntelPmgIoCaptureBase);
5170 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromToN);
5171 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchFromN);
5172 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchToN);
5173 CPUM_ASSERT_RD_MSR_FN(IntelLastBranchTos);
5174 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl);
5175 CPUM_ASSERT_RD_MSR_FN(IntelBblCrCtl3);
5176 CPUM_ASSERT_RD_MSR_FN(IntelI7TemperatureTarget);
5177 CPUM_ASSERT_RD_MSR_FN(IntelI7MsrOffCoreResponseN);
5178 CPUM_ASSERT_RD_MSR_FN(IntelI7MiscPwrMgmt);
5179 CPUM_ASSERT_RD_MSR_FN(IntelP6CrN);
5180 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5181 CPUM_ASSERT_RD_MSR_FN(IntelCpuId1FeatureMaskEax);
5182 CPUM_ASSERT_RD_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5183 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyAesNiCtl);
5184 CPUM_ASSERT_RD_MSR_FN(IntelI7TurboRatioLimit);
5185 CPUM_ASSERT_RD_MSR_FN(IntelI7LbrSelect);
5186 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyErrorControl);
5187 CPUM_ASSERT_RD_MSR_FN(IntelI7VirtualLegacyWireCap);
5188 CPUM_ASSERT_RD_MSR_FN(IntelI7PowerCtl);
5189 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPebsNumAlt);
5190 CPUM_ASSERT_RD_MSR_FN(IntelI7PebsLdLat);
5191 CPUM_ASSERT_RD_MSR_FN(IntelI7PkgCnResidencyN);
5192 CPUM_ASSERT_RD_MSR_FN(IntelI7CoreCnResidencyN);
5193 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrCurrentConfig);
5194 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyVrMiscConfig);
5195 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyRaplPowerUnit);
5196 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgCnIrtlN);
5197 CPUM_ASSERT_RD_MSR_FN(IntelI7SandyPkgC2Residency);
5198 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerLimit);
5199 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgEnergyStatus);
5200 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPerfStatus);
5201 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPkgPowerInfo);
5202 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerLimit);
5203 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramEnergyStatus);
5204 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPerfStatus);
5205 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplDramPowerInfo);
5206 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PowerLimit);
5207 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0EnergyStatus);
5208 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0Policy);
5209 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp0PerfStatus);
5210 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1PowerLimit);
5211 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1EnergyStatus);
5212 CPUM_ASSERT_RD_MSR_FN(IntelI7RaplPp1Policy);
5213 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpNominal);
5214 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel1);
5215 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpLevel2);
5216 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyConfigTdpControl);
5217 CPUM_ASSERT_RD_MSR_FN(IntelI7IvyTurboActivationRatio);
5218 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalCtrl);
5219 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalStatus);
5220 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5221 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5222 CPUM_ASSERT_RD_MSR_FN(IntelI7UncPerfFixedCtr);
5223 CPUM_ASSERT_RD_MSR_FN(IntelI7UncCBoxConfig);
5224 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN);
5225 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN);
5226 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN);
5227 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo);
5228 CPUM_ASSERT_RD_MSR_FN(IntelCore1ExtConfig);
5229 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl);
5230 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl);
5231
5232 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp);
5233 CPUM_ASSERT_RD_MSR_FN(P6LastBranchToIp);
5234 CPUM_ASSERT_RD_MSR_FN(P6LastIntFromIp);
5235 CPUM_ASSERT_RD_MSR_FN(P6LastIntToIp);
5236
5237 CPUM_ASSERT_RD_MSR_FN(AmdFam15hTscRate);
5238 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCfg);
5239 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLwpCbAddr);
5240 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMc4MiscN);
5241 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtlN);
5242 CPUM_ASSERT_RD_MSR_FN(AmdK8PerfCtrN);
5243 CPUM_ASSERT_RD_MSR_FN(AmdK8SysCfg);
5244 CPUM_ASSERT_RD_MSR_FN(AmdK8HwCr);
5245 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrBaseN);
5246 CPUM_ASSERT_RD_MSR_FN(AmdK8IorrMaskN);
5247 CPUM_ASSERT_RD_MSR_FN(AmdK8TopOfMemN);
5248 CPUM_ASSERT_RD_MSR_FN(AmdK8NbCfg1);
5249 CPUM_ASSERT_RD_MSR_FN(AmdK8McXcptRedir);
5250 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuNameN);
5251 CPUM_ASSERT_RD_MSR_FN(AmdK8HwThermalCtrl);
5252 CPUM_ASSERT_RD_MSR_FN(AmdK8SwThermalCtrl);
5253 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidControl);
5254 CPUM_ASSERT_RD_MSR_FN(AmdK8FidVidStatus);
5255 CPUM_ASSERT_RD_MSR_FN(AmdK8McCtlMaskN);
5256 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapN);
5257 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5258 CPUM_ASSERT_RD_MSR_FN(AmdK8IntPendingMessage);
5259 CPUM_ASSERT_RD_MSR_FN(AmdK8SmiTriggerIoCycle);
5260 CPUM_ASSERT_RD_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5261 CPUM_ASSERT_RD_MSR_FN(AmdFam10hTrapCtlMaybe);
5262 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateCurLimit);
5263 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateControl);
5264 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateStatus);
5265 CPUM_ASSERT_RD_MSR_FN(AmdFam10hPStateN);
5266 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidControl);
5267 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCofVidStatus);
5268 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCStateIoBaseAddr);
5269 CPUM_ASSERT_RD_MSR_FN(AmdFam10hCpuWatchdogTimer);
5270 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmBase);
5271 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmAddr);
5272 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmMask);
5273 CPUM_ASSERT_RD_MSR_FN(AmdK8VmCr);
5274 CPUM_ASSERT_RD_MSR_FN(AmdK8IgnNe);
5275 CPUM_ASSERT_RD_MSR_FN(AmdK8SmmCtl);
5276 CPUM_ASSERT_RD_MSR_FN(AmdK8VmHSavePa);
5277 CPUM_ASSERT_RD_MSR_FN(AmdFam10hVmLockKey);
5278 CPUM_ASSERT_RD_MSR_FN(AmdFam10hSmmLockKey);
5279 CPUM_ASSERT_RD_MSR_FN(AmdFam10hLocalSmiStatus);
5280 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkIdLength);
5281 CPUM_ASSERT_RD_MSR_FN(AmdFam10hOsVisWrkStatus);
5282 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtlN);
5283 CPUM_ASSERT_RD_MSR_FN(AmdFam16hL2IPerfCtrN);
5284 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5285 CPUM_ASSERT_RD_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5286 CPUM_ASSERT_RD_MSR_FN(AmdK7MicrocodeCtl);
5287 CPUM_ASSERT_RD_MSR_FN(AmdK7ClusterIdMaybe);
5288 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5289 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5290 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5291 CPUM_ASSERT_RD_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5292 CPUM_ASSERT_RD_MSR_FN(AmdK8PatchLevel);
5293 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugStatusMaybe);
5294 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceBaseMaybe);
5295 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTracePtrMaybe);
5296 CPUM_ASSERT_RD_MSR_FN(AmdK7BHTraceLimitMaybe);
5297 CPUM_ASSERT_RD_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5298 CPUM_ASSERT_RD_MSR_FN(AmdK7FastFlushCountMaybe);
5299 CPUM_ASSERT_RD_MSR_FN(AmdK7NodeId);
5300 CPUM_ASSERT_RD_MSR_FN(AmdK7DrXAddrMaskN);
5301 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMatchMaybe);
5302 CPUM_ASSERT_RD_MSR_FN(AmdK7Dr0DataMaskMaybe);
5303 CPUM_ASSERT_RD_MSR_FN(AmdK7LoadStoreCfg);
5304 CPUM_ASSERT_RD_MSR_FN(AmdK7InstrCacheCfg);
5305 CPUM_ASSERT_RD_MSR_FN(AmdK7DataCacheCfg);
5306 CPUM_ASSERT_RD_MSR_FN(AmdK7BusUnitCfg);
5307 CPUM_ASSERT_RD_MSR_FN(AmdK7DebugCtl2Maybe);
5308 CPUM_ASSERT_RD_MSR_FN(AmdFam15hFpuCfg);
5309 CPUM_ASSERT_RD_MSR_FN(AmdFam15hDecoderCfg);
5310 CPUM_ASSERT_RD_MSR_FN(AmdFam10hBusUnitCfg2);
5311 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg);
5312 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg2);
5313 CPUM_ASSERT_RD_MSR_FN(AmdFam15hCombUnitCfg3);
5314 CPUM_ASSERT_RD_MSR_FN(AmdFam15hExecUnitCfg);
5315 CPUM_ASSERT_RD_MSR_FN(AmdFam15hLoadStoreCfg2);
5316 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchCtl);
5317 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchLinAddr);
5318 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5319 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpExecCtl);
5320 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpRip);
5321 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData);
5322 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData2);
5323 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsOpData3);
5324 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcLinAddr);
5325 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsDcPhysAddr);
5326 CPUM_ASSERT_RD_MSR_FN(AmdFam10hIbsCtl);
5327 CPUM_ASSERT_RD_MSR_FN(AmdFam14hIbsBrTarget);
5328
5329 AssertReturn(g_aCpumWrMsrFns[kCpumMsrWrFn_Invalid] == NULL, VERR_CPUM_IPE_2);
5330 CPUM_ASSERT_WR_MSR_FN(Ia32P5McAddr);
5331 CPUM_ASSERT_WR_MSR_FN(Ia32P5McType);
5332 CPUM_ASSERT_WR_MSR_FN(Ia32TimestampCounter);
5333 CPUM_ASSERT_WR_MSR_FN(Ia32ApicBase);
5334 CPUM_ASSERT_WR_MSR_FN(Ia32FeatureControl);
5335 CPUM_ASSERT_WR_MSR_FN(Ia32BiosSignId);
5336 CPUM_ASSERT_WR_MSR_FN(Ia32BiosUpdateTrigger);
5337 CPUM_ASSERT_WR_MSR_FN(Ia32SmmMonitorCtl);
5338 CPUM_ASSERT_WR_MSR_FN(Ia32PmcN);
5339 CPUM_ASSERT_WR_MSR_FN(Ia32MonitorFilterLineSize);
5340 CPUM_ASSERT_WR_MSR_FN(Ia32MPerf);
5341 CPUM_ASSERT_WR_MSR_FN(Ia32APerf);
5342 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysBaseN);
5343 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrPhysMaskN);
5344 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrFixed);
5345 CPUM_ASSERT_WR_MSR_FN(Ia32MtrrDefType);
5346 CPUM_ASSERT_WR_MSR_FN(Ia32Pat);
5347 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterCs);
5348 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEsp);
5349 CPUM_ASSERT_WR_MSR_FN(Ia32SysEnterEip);
5350 CPUM_ASSERT_WR_MSR_FN(Ia32McgStatus);
5351 CPUM_ASSERT_WR_MSR_FN(Ia32McgCtl);
5352 CPUM_ASSERT_WR_MSR_FN(Ia32DebugCtl);
5353 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysBase);
5354 CPUM_ASSERT_WR_MSR_FN(Ia32SmrrPhysMask);
5355 CPUM_ASSERT_WR_MSR_FN(Ia32PlatformDcaCap);
5356 CPUM_ASSERT_WR_MSR_FN(Ia32Dca0Cap);
5357 CPUM_ASSERT_WR_MSR_FN(Ia32PerfEvtSelN);
5358 CPUM_ASSERT_WR_MSR_FN(Ia32PerfStatus);
5359 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCtl);
5360 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrN);
5361 CPUM_ASSERT_WR_MSR_FN(Ia32PerfCapabilities);
5362 CPUM_ASSERT_WR_MSR_FN(Ia32FixedCtrCtrl);
5363 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalStatus);
5364 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalCtrl);
5365 CPUM_ASSERT_WR_MSR_FN(Ia32PerfGlobalOvfCtrl);
5366 CPUM_ASSERT_WR_MSR_FN(Ia32PebsEnable);
5367 CPUM_ASSERT_WR_MSR_FN(Ia32ClockModulation);
5368 CPUM_ASSERT_WR_MSR_FN(Ia32ThermInterrupt);
5369 CPUM_ASSERT_WR_MSR_FN(Ia32ThermStatus);
5370 CPUM_ASSERT_WR_MSR_FN(Ia32MiscEnable);
5371 CPUM_ASSERT_WR_MSR_FN(Ia32McCtlStatusAddrMiscN);
5372 CPUM_ASSERT_WR_MSR_FN(Ia32McNCtl2);
5373 CPUM_ASSERT_WR_MSR_FN(Ia32DsArea);
5374 CPUM_ASSERT_WR_MSR_FN(Ia32TscDeadline);
5375 CPUM_ASSERT_WR_MSR_FN(Ia32X2ApicN);
5376 CPUM_ASSERT_WR_MSR_FN(Ia32DebugInterface);
5377
5378 CPUM_ASSERT_WR_MSR_FN(Amd64Efer);
5379 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallTarget);
5380 CPUM_ASSERT_WR_MSR_FN(Amd64LongSyscallTarget);
5381 CPUM_ASSERT_WR_MSR_FN(Amd64CompSyscallTarget);
5382 CPUM_ASSERT_WR_MSR_FN(Amd64SyscallFlagMask);
5383 CPUM_ASSERT_WR_MSR_FN(Amd64FsBase);
5384 CPUM_ASSERT_WR_MSR_FN(Amd64GsBase);
5385 CPUM_ASSERT_WR_MSR_FN(Amd64KernelGsBase);
5386 CPUM_ASSERT_WR_MSR_FN(Amd64TscAux);
5387
5388 CPUM_ASSERT_WR_MSR_FN(IntelEblCrPowerOn);
5389 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcHardPowerOn);
5390 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcSoftPowerOn);
5391 CPUM_ASSERT_WR_MSR_FN(IntelP4EbcFrequencyId);
5392 CPUM_ASSERT_WR_MSR_FN(IntelFlexRatio);
5393 CPUM_ASSERT_WR_MSR_FN(IntelPkgCStConfigControl);
5394 CPUM_ASSERT_WR_MSR_FN(IntelPmgIoCaptureBase);
5395 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromToN);
5396 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchFromN);
5397 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchToN);
5398 CPUM_ASSERT_WR_MSR_FN(IntelLastBranchTos);
5399 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl);
5400 CPUM_ASSERT_WR_MSR_FN(IntelBblCrCtl3);
5401 CPUM_ASSERT_WR_MSR_FN(IntelI7TemperatureTarget);
5402 CPUM_ASSERT_WR_MSR_FN(IntelI7MsrOffCoreResponseN);
5403 CPUM_ASSERT_WR_MSR_FN(IntelI7MiscPwrMgmt);
5404 CPUM_ASSERT_WR_MSR_FN(IntelP6CrN);
5405 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEcdx);
5406 CPUM_ASSERT_WR_MSR_FN(IntelCpuId1FeatureMaskEax);
5407 CPUM_ASSERT_WR_MSR_FN(IntelCpuId80000001FeatureMaskEcdx);
5408 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyAesNiCtl);
5409 CPUM_ASSERT_WR_MSR_FN(IntelI7TurboRatioLimit);
5410 CPUM_ASSERT_WR_MSR_FN(IntelI7LbrSelect);
5411 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyErrorControl);
5412 CPUM_ASSERT_WR_MSR_FN(IntelI7PowerCtl);
5413 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPebsNumAlt);
5414 CPUM_ASSERT_WR_MSR_FN(IntelI7PebsLdLat);
5415 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrCurrentConfig);
5416 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig);
5417 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN);
5418 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit);
5419 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit);
5420 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0PowerLimit);
5421 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp0Policy);
5422 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1PowerLimit);
5423 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPp1Policy);
5424 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyConfigTdpControl);
5425 CPUM_ASSERT_WR_MSR_FN(IntelI7IvyTurboActivationRatio);
5426 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalCtrl);
5427 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalStatus);
5428 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfGlobalOvfCtrl);
5429 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtrCtrl);
5430 CPUM_ASSERT_WR_MSR_FN(IntelI7UncPerfFixedCtr);
5431 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfCtrN);
5432 CPUM_ASSERT_WR_MSR_FN(IntelI7UncArbPerfEvtSelN);
5433 CPUM_ASSERT_WR_MSR_FN(IntelCore2EmttmCrTablesN);
5434 CPUM_ASSERT_WR_MSR_FN(IntelCore2SmmCStMiscInfo);
5435 CPUM_ASSERT_WR_MSR_FN(IntelCore1ExtConfig);
5436 CPUM_ASSERT_WR_MSR_FN(IntelCore1DtsCalControl);
5437 CPUM_ASSERT_WR_MSR_FN(IntelCore2PeciControl);
5438
5439 CPUM_ASSERT_WR_MSR_FN(P6LastIntFromIp);
5440 CPUM_ASSERT_WR_MSR_FN(P6LastIntToIp);
5441
5442 CPUM_ASSERT_WR_MSR_FN(AmdFam15hTscRate);
5443 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCfg);
5444 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLwpCbAddr);
5445 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMc4MiscN);
5446 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtlN);
5447 CPUM_ASSERT_WR_MSR_FN(AmdK8PerfCtrN);
5448 CPUM_ASSERT_WR_MSR_FN(AmdK8SysCfg);
5449 CPUM_ASSERT_WR_MSR_FN(AmdK8HwCr);
5450 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrBaseN);
5451 CPUM_ASSERT_WR_MSR_FN(AmdK8IorrMaskN);
5452 CPUM_ASSERT_WR_MSR_FN(AmdK8TopOfMemN);
5453 CPUM_ASSERT_WR_MSR_FN(AmdK8NbCfg1);
5454 CPUM_ASSERT_WR_MSR_FN(AmdK8McXcptRedir);
5455 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuNameN);
5456 CPUM_ASSERT_WR_MSR_FN(AmdK8HwThermalCtrl);
5457 CPUM_ASSERT_WR_MSR_FN(AmdK8SwThermalCtrl);
5458 CPUM_ASSERT_WR_MSR_FN(AmdK8FidVidControl);
5459 CPUM_ASSERT_WR_MSR_FN(AmdK8McCtlMaskN);
5460 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapN);
5461 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiOnIoTrapCtlSts);
5462 CPUM_ASSERT_WR_MSR_FN(AmdK8IntPendingMessage);
5463 CPUM_ASSERT_WR_MSR_FN(AmdK8SmiTriggerIoCycle);
5464 CPUM_ASSERT_WR_MSR_FN(AmdFam10hMmioCfgBaseAddr);
5465 CPUM_ASSERT_WR_MSR_FN(AmdFam10hTrapCtlMaybe);
5466 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateControl);
5467 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateStatus);
5468 CPUM_ASSERT_WR_MSR_FN(AmdFam10hPStateN);
5469 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidControl);
5470 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCofVidStatus);
5471 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCStateIoBaseAddr);
5472 CPUM_ASSERT_WR_MSR_FN(AmdFam10hCpuWatchdogTimer);
5473 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmBase);
5474 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmAddr);
5475 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmMask);
5476 CPUM_ASSERT_WR_MSR_FN(AmdK8VmCr);
5477 CPUM_ASSERT_WR_MSR_FN(AmdK8IgnNe);
5478 CPUM_ASSERT_WR_MSR_FN(AmdK8SmmCtl);
5479 CPUM_ASSERT_WR_MSR_FN(AmdK8VmHSavePa);
5480 CPUM_ASSERT_WR_MSR_FN(AmdFam10hVmLockKey);
5481 CPUM_ASSERT_WR_MSR_FN(AmdFam10hSmmLockKey);
5482 CPUM_ASSERT_WR_MSR_FN(AmdFam10hLocalSmiStatus);
5483 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkIdLength);
5484 CPUM_ASSERT_WR_MSR_FN(AmdFam10hOsVisWrkStatus);
5485 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtlN);
5486 CPUM_ASSERT_WR_MSR_FN(AmdFam16hL2IPerfCtrN);
5487 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtlN);
5488 CPUM_ASSERT_WR_MSR_FN(AmdFam15hNorthbridgePerfCtrN);
5489 CPUM_ASSERT_WR_MSR_FN(AmdK7MicrocodeCtl);
5490 CPUM_ASSERT_WR_MSR_FN(AmdK7ClusterIdMaybe);
5491 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd07hEbax);
5492 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd06hEcx);
5493 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlStd01hEdcx);
5494 CPUM_ASSERT_WR_MSR_FN(AmdK8CpuIdCtlExt01hEdcx);
5495 CPUM_ASSERT_WR_MSR_FN(AmdK8PatchLoader);
5496 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugStatusMaybe);
5497 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceBaseMaybe);
5498 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTracePtrMaybe);
5499 CPUM_ASSERT_WR_MSR_FN(AmdK7BHTraceLimitMaybe);
5500 CPUM_ASSERT_WR_MSR_FN(AmdK7HardwareDebugToolCfgMaybe);
5501 CPUM_ASSERT_WR_MSR_FN(AmdK7FastFlushCountMaybe);
5502 CPUM_ASSERT_WR_MSR_FN(AmdK7NodeId);
5503 CPUM_ASSERT_WR_MSR_FN(AmdK7DrXAddrMaskN);
5504 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMatchMaybe);
5505 CPUM_ASSERT_WR_MSR_FN(AmdK7Dr0DataMaskMaybe);
5506 CPUM_ASSERT_WR_MSR_FN(AmdK7LoadStoreCfg);
5507 CPUM_ASSERT_WR_MSR_FN(AmdK7InstrCacheCfg);
5508 CPUM_ASSERT_WR_MSR_FN(AmdK7DataCacheCfg);
5509 CPUM_ASSERT_WR_MSR_FN(AmdK7BusUnitCfg);
5510 CPUM_ASSERT_WR_MSR_FN(AmdK7DebugCtl2Maybe);
5511 CPUM_ASSERT_WR_MSR_FN(AmdFam15hFpuCfg);
5512 CPUM_ASSERT_WR_MSR_FN(AmdFam15hDecoderCfg);
5513 CPUM_ASSERT_WR_MSR_FN(AmdFam10hBusUnitCfg2);
5514 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg);
5515 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg2);
5516 CPUM_ASSERT_WR_MSR_FN(AmdFam15hCombUnitCfg3);
5517 CPUM_ASSERT_WR_MSR_FN(AmdFam15hExecUnitCfg);
5518 CPUM_ASSERT_WR_MSR_FN(AmdFam15hLoadStoreCfg2);
5519 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchCtl);
5520 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchLinAddr);
5521 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsFetchPhysAddr);
5522 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpExecCtl);
5523 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpRip);
5524 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData);
5525 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData2);
5526 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsOpData3);
5527 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcLinAddr);
5528 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsDcPhysAddr);
5529 CPUM_ASSERT_WR_MSR_FN(AmdFam10hIbsCtl);
5530 CPUM_ASSERT_WR_MSR_FN(AmdFam14hIbsBrTarget);
5531
5532 return VINF_SUCCESS;
5533}
5534#endif /* VBOX_STRICT && IN_RING3 */
5535
5536
5537/**
5538 * Gets the scalable bus frequency.
5539 *
5540 * The bus frequency is used as a base in several MSRs that gives the CPU and
5541 * other frequency ratios.
5542 *
5543 * @returns Scalable bus frequency in Hz. Will not return CPUM_SBUSFREQ_UNKNOWN.
5544 * @param pVM Pointer to the shared VM structure.
5545 */
5546VMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM)
5547{
5548 uint64_t uFreq = pVM->cpum.s.GuestInfo.uScalableBusFreq;
5549 if (uFreq == CPUM_SBUSFREQ_UNKNOWN)
5550 uFreq = CPUM_SBUSFREQ_100MHZ;
5551 return uFreq;
5552}
5553
5554
5555#ifdef IN_RING0
5556
5557/**
5558 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5559 *
5560 * @returns The register value.
5561 * @param pVCpu Pointer to the cross context CPU structure for
5562 * the calling EMT.
5563 * @thread EMT(pVCpu)
5564 */
5565VMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu)
5566{
5567 return pVCpu->cpum.s.GuestMsrs.msr.TscAux;
5568}
5569
5570
5571/**
5572 * Fast way for HM to access the MSR_K8_TSC_AUX register.
5573 *
5574 * @param pVCpu Pointer to the cross context CPU structure for
5575 * the calling EMT.
5576 * @param uValue The new value.
5577 * @thread EMT(pVCpu)
5578 */
5579VMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue)
5580{
5581 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
5582}
5583
5584#endif /* IN_RING0 */
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