VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 41905

Last change on this file since 41905 was 41905, checked in by vboxsync, 13 years ago

CPUMCTX++: Rearranging the CPUMCTX structure in preparation of some hidden selector register improvments.
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1/* $Id: CPUMAllRegs.cpp 41905 2012-06-24 01:19:25Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/patm.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/pdm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#include "CPUMInternal.h"
30#include <VBox/vmm/vm.h>
31#include <VBox/err.h>
32#include <VBox/dis.h>
33#include <VBox/log.h>
34#include <VBox/vmm/hwaccm.h>
35#include <VBox/vmm/tm.h>
36#include <iprt/assert.h>
37#include <iprt/asm.h>
38#include <iprt/asm-amd64-x86.h>
39#ifdef IN_RING3
40#include <iprt/thread.h>
41#endif
42
43/** Disable stack frame pointer generation here. */
44#if defined(_MSC_VER) && !defined(DEBUG)
45# pragma optimize("y", off)
46#endif
47
48
49/**
50 * Sets or resets an alternative hypervisor context core.
51 *
52 * This is called when we get a hypervisor trap set switch the context
53 * core with the trap frame on the stack. It is called again to reset
54 * back to the default context core when resuming hypervisor execution.
55 *
56 * @param pVCpu Pointer to the VMCPU.
57 * @param pCtxCore Pointer to the alternative context core or NULL
58 * to go back to the default context core.
59 */
60VMMDECL(void) CPUMHyperSetCtxCore(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
61{
62 PVM pVM = pVCpu->CTX_SUFF(pVM);
63
64 LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVCpu->cpum.s.CTX_SUFF(pHyperCore), pCtxCore));
65 if (!pCtxCore)
66 {
67 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
68 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))VM_R3_ADDR(pVM, pCtxCore);
69 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))VM_R0_ADDR(pVM, pCtxCore);
70 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))VM_RC_ADDR(pVM, pCtxCore);
71 }
72 else
73 {
74 pVCpu->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))MMHyperCCToR3(pVM, pCtxCore);
75 pVCpu->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))MMHyperCCToR0(pVM, pCtxCore);
76 pVCpu->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
77 }
78}
79
80
81/**
82 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
83 * This is only for reading in order to save a few calls.
84 *
85 * @param pVM Handle to the virtual machine.
86 */
87VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
88{
89 return pVCpu->cpum.s.CTX_SUFF(pHyperCore);
90}
91
92
93/**
94 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
95 *
96 * @returns VBox status code.
97 * @param pVM Handle to the virtual machine.
98 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
99 *
100 * @deprecated This will *not* (and has never) given the right picture of the
101 * hypervisor register state. With CPUMHyperSetCtxCore() this is
102 * getting much worse. So, use the individual functions for getting
103 * and esp. setting the hypervisor registers.
104 */
105VMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx)
106{
107 *ppCtx = &pVCpu->cpum.s.Hyper;
108 return VINF_SUCCESS;
109}
110
111
112VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
113{
114 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
115 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
116}
117
118
119VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
120{
121 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
122 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
123}
124
125
126VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
127{
128 pVCpu->cpum.s.Hyper.cr3 = cr3;
129
130#ifdef IN_RC
131 /* Update the current CR3. */
132 ASMSetCR3(cr3);
133#endif
134}
135
136VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
137{
138 return pVCpu->cpum.s.Hyper.cr3;
139}
140
141
142VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
143{
144 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs = SelCS;
145}
146
147
148VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
149{
150 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds = SelDS;
151}
152
153
154VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
155{
156 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es = SelES;
157}
158
159
160VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
161{
162 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs = SelFS;
163}
164
165
166VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
167{
168 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs = SelGS;
169}
170
171
172VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
173{
174 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss = SelSS;
175}
176
177
178VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
179{
180 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp = u32ESP;
181}
182
183
184VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
185{
186 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32 = Efl;
187 return VINF_SUCCESS;
188}
189
190
191VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
192{
193 pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip = u32EIP;
194}
195
196
197VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
198{
199 pVCpu->cpum.s.Hyper.tr = SelTR;
200}
201
202
203VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
204{
205 pVCpu->cpum.s.Hyper.ldtr = SelLDTR;
206}
207
208
209VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
210{
211 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
212 /** @todo in GC we must load it! */
213}
214
215
216VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
217{
218 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
219 /** @todo in GC we must load it! */
220}
221
222
223VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
224{
225 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
226 /** @todo in GC we must load it! */
227}
228
229
230VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
231{
232 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
233 /** @todo in GC we must load it! */
234}
235
236
237VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
238{
239 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
240 /** @todo in GC we must load it! */
241}
242
243
244VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
245{
246 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
247 /** @todo in GC we must load it! */
248}
249
250
251VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
252{
253 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->cs;
254}
255
256
257VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
258{
259 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ds;
260}
261
262
263VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
264{
265 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->es;
266}
267
268
269VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
270{
271 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->fs;
272}
273
274
275VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
276{
277 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->gs;
278}
279
280
281VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
282{
283 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ss;
284}
285
286
287VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
288{
289 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eax;
290}
291
292
293VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
294{
295 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebx;
296}
297
298
299VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
300{
301 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ecx;
302}
303
304
305VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
306{
307 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edx;
308}
309
310
311VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
312{
313 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esi;
314}
315
316
317VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
318{
319 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->edi;
320}
321
322
323VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
324{
325 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->ebp;
326}
327
328
329VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
330{
331 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->esp;
332}
333
334
335VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
336{
337 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32;
338}
339
340
341VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
342{
343 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->eip;
344}
345
346
347VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
348{
349 return pVCpu->cpum.s.CTX_SUFF(pHyperCore)->rip;
350}
351
352
353VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
354{
355 if (pcbLimit)
356 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
357 return pVCpu->cpum.s.Hyper.idtr.pIdt;
358}
359
360
361VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
362{
363 if (pcbLimit)
364 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
365 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
366}
367
368
369VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
370{
371 return pVCpu->cpum.s.Hyper.ldtr;
372}
373
374
375VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
376{
377 return pVCpu->cpum.s.Hyper.dr[0];
378}
379
380
381VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
382{
383 return pVCpu->cpum.s.Hyper.dr[1];
384}
385
386
387VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
388{
389 return pVCpu->cpum.s.Hyper.dr[2];
390}
391
392
393VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
394{
395 return pVCpu->cpum.s.Hyper.dr[3];
396}
397
398
399VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
400{
401 return pVCpu->cpum.s.Hyper.dr[6];
402}
403
404
405VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
406{
407 return pVCpu->cpum.s.Hyper.dr[7];
408}
409
410
411/**
412 * Gets the pointer to the internal CPUMCTXCORE structure.
413 * This is only for reading in order to save a few calls.
414 *
415 * @param pVCpu Handle to the virtual cpu.
416 */
417VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
418{
419 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
420}
421
422
423/**
424 * Sets the guest context core registers.
425 *
426 * @param pVCpu Handle to the virtual cpu.
427 * @param pCtxCore The new context core values.
428 */
429VMMDECL(void) CPUMSetGuestCtxCore(PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore)
430{
431 /** @todo #1410 requires selectors to be checked. (huh? 1410?) */
432
433 PCPUMCTXCORE pCtxCoreDst = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
434 *pCtxCoreDst = *pCtxCore;
435
436 /* Mask away invalid parts of the cpu context. */
437 if (!CPUMIsGuestInLongMode(pVCpu))
438 {
439 uint64_t u64Mask = UINT64_C(0xffffffff);
440
441 pCtxCoreDst->rip &= u64Mask;
442 pCtxCoreDst->rax &= u64Mask;
443 pCtxCoreDst->rbx &= u64Mask;
444 pCtxCoreDst->rcx &= u64Mask;
445 pCtxCoreDst->rdx &= u64Mask;
446 pCtxCoreDst->rsi &= u64Mask;
447 pCtxCoreDst->rdi &= u64Mask;
448 pCtxCoreDst->rbp &= u64Mask;
449 pCtxCoreDst->rsp &= u64Mask;
450 pCtxCoreDst->rflags.u &= u64Mask;
451
452 pCtxCoreDst->r8 = 0;
453 pCtxCoreDst->r9 = 0;
454 pCtxCoreDst->r10 = 0;
455 pCtxCoreDst->r11 = 0;
456 pCtxCoreDst->r12 = 0;
457 pCtxCoreDst->r13 = 0;
458 pCtxCoreDst->r14 = 0;
459 pCtxCoreDst->r15 = 0;
460 }
461}
462
463
464/**
465 * Queries the pointer to the internal CPUMCTX structure
466 *
467 * @returns The CPUMCTX pointer.
468 * @param pVCpu Handle to the virtual cpu.
469 */
470VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
471{
472 return &pVCpu->cpum.s.Guest;
473}
474
475VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
476{
477 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
478 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
479 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
480 return VINF_SUCCESS;
481}
482
483VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
484{
485 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
486 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
487 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
488 return VINF_SUCCESS;
489}
490
491VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
492{
493 pVCpu->cpum.s.Guest.tr = tr;
494 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
495 return VINF_SUCCESS;
496}
497
498VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
499{
500 pVCpu->cpum.s.Guest.ldtr = ldtr;
501 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
502 return VINF_SUCCESS;
503}
504
505
506/**
507 * Set the guest CR0.
508 *
509 * When called in GC, the hyper CR0 may be updated if that is
510 * required. The caller only has to take special action if AM,
511 * WP, PG or PE changes.
512 *
513 * @returns VINF_SUCCESS (consider it void).
514 * @param pVCpu Handle to the virtual cpu.
515 * @param cr0 The new CR0 value.
516 */
517VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
518{
519#ifdef IN_RC
520 /*
521 * Check if we need to change hypervisor CR0 because
522 * of math stuff.
523 */
524 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
525 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
526 {
527 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
528 {
529 /*
530 * We haven't saved the host FPU state yet, so TS and MT are both set
531 * and EM should be reflecting the guest EM (it always does this).
532 */
533 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
534 {
535 uint32_t HyperCR0 = ASMGetCR0();
536 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
537 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
538 HyperCR0 &= ~X86_CR0_EM;
539 HyperCR0 |= cr0 & X86_CR0_EM;
540 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
541 ASMSetCR0(HyperCR0);
542 }
543# ifdef VBOX_STRICT
544 else
545 {
546 uint32_t HyperCR0 = ASMGetCR0();
547 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
548 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
549 }
550# endif
551 }
552 else
553 {
554 /*
555 * Already saved the state, so we're just mirroring
556 * the guest flags.
557 */
558 uint32_t HyperCR0 = ASMGetCR0();
559 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
560 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
561 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
562 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
563 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
564 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
565 ASMSetCR0(HyperCR0);
566 }
567 }
568#endif /* IN_RC */
569
570 /*
571 * Check for changes causing TLB flushes (for REM).
572 * The caller is responsible for calling PGM when appropriate.
573 */
574 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
575 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
576 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
577 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
578
579 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
580 return VINF_SUCCESS;
581}
582
583
584VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
585{
586 pVCpu->cpum.s.Guest.cr2 = cr2;
587 return VINF_SUCCESS;
588}
589
590
591VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
592{
593 pVCpu->cpum.s.Guest.cr3 = cr3;
594 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
595 return VINF_SUCCESS;
596}
597
598
599VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
600{
601 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
602 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
603 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
604 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
605 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
606 cr4 &= ~X86_CR4_OSFSXR;
607 pVCpu->cpum.s.Guest.cr4 = cr4;
608 return VINF_SUCCESS;
609}
610
611
612VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
613{
614 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
615 return VINF_SUCCESS;
616}
617
618
619VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
620{
621 pVCpu->cpum.s.Guest.eip = eip;
622 return VINF_SUCCESS;
623}
624
625
626VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
627{
628 pVCpu->cpum.s.Guest.eax = eax;
629 return VINF_SUCCESS;
630}
631
632
633VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
634{
635 pVCpu->cpum.s.Guest.ebx = ebx;
636 return VINF_SUCCESS;
637}
638
639
640VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
641{
642 pVCpu->cpum.s.Guest.ecx = ecx;
643 return VINF_SUCCESS;
644}
645
646
647VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
648{
649 pVCpu->cpum.s.Guest.edx = edx;
650 return VINF_SUCCESS;
651}
652
653
654VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
655{
656 pVCpu->cpum.s.Guest.esp = esp;
657 return VINF_SUCCESS;
658}
659
660
661VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
662{
663 pVCpu->cpum.s.Guest.ebp = ebp;
664 return VINF_SUCCESS;
665}
666
667
668VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
669{
670 pVCpu->cpum.s.Guest.esi = esi;
671 return VINF_SUCCESS;
672}
673
674
675VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
676{
677 pVCpu->cpum.s.Guest.edi = edi;
678 return VINF_SUCCESS;
679}
680
681
682VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
683{
684 pVCpu->cpum.s.Guest.ss = ss;
685 return VINF_SUCCESS;
686}
687
688
689VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
690{
691 pVCpu->cpum.s.Guest.cs = cs;
692 return VINF_SUCCESS;
693}
694
695
696VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
697{
698 pVCpu->cpum.s.Guest.ds = ds;
699 return VINF_SUCCESS;
700}
701
702
703VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
704{
705 pVCpu->cpum.s.Guest.es = es;
706 return VINF_SUCCESS;
707}
708
709
710VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
711{
712 pVCpu->cpum.s.Guest.fs = fs;
713 return VINF_SUCCESS;
714}
715
716
717VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
718{
719 pVCpu->cpum.s.Guest.gs = gs;
720 return VINF_SUCCESS;
721}
722
723
724VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
725{
726 pVCpu->cpum.s.Guest.msrEFER = val;
727}
728
729
730/**
731 * Query an MSR.
732 *
733 * The caller is responsible for checking privilege if the call is the result
734 * of a RDMSR instruction. We'll do the rest.
735 *
736 * @retval VINF_SUCCESS on success.
737 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
738 * expected to take the appropriate actions. @a *puValue is set to 0.
739 * @param pVCpu Pointer to the VMCPU.
740 * @param idMsr The MSR.
741 * @param puValue Where to return the value.
742 *
743 * @remarks This will always return the right values, even when we're in the
744 * recompiler.
745 */
746VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
747{
748 /*
749 * If we don't indicate MSR support in the CPUID feature bits, indicate
750 * that a #GP(0) should be raised.
751 */
752 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
753 {
754 *puValue = 0;
755 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
756 }
757
758 int rc = VINF_SUCCESS;
759 uint8_t const u8Multiplier = 4;
760 switch (idMsr)
761 {
762 case MSR_IA32_TSC:
763 *puValue = TMCpuTickGet(pVCpu);
764 break;
765
766 case MSR_IA32_APICBASE:
767 rc = PDMApicGetBase(pVCpu->CTX_SUFF(pVM), puValue);
768 if (RT_SUCCESS(rc))
769 rc = VINF_SUCCESS;
770 else
771 {
772 *puValue = 0;
773 rc = VERR_CPUM_RAISE_GP_0;
774 }
775 break;
776
777 case MSR_IA32_CR_PAT:
778 *puValue = pVCpu->cpum.s.Guest.msrPAT;
779 break;
780
781 case MSR_IA32_SYSENTER_CS:
782 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
783 break;
784
785 case MSR_IA32_SYSENTER_EIP:
786 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
787 break;
788
789 case MSR_IA32_SYSENTER_ESP:
790 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
791 break;
792
793 case MSR_IA32_MTRR_CAP:
794 {
795 /* This is currently a bit weird. :-) */
796 uint8_t const cVariableRangeRegs = 0;
797 bool const fSystemManagementRangeRegisters = false;
798 bool const fFixedRangeRegisters = false;
799 bool const fWriteCombiningType = false;
800 *puValue = cVariableRangeRegs
801 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
802 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
803 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
804 break;
805 }
806
807 case MSR_IA32_MTRR_DEF_TYPE:
808 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
809 break;
810
811 case IA32_MTRR_FIX64K_00000:
812 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000;
813 break;
814 case IA32_MTRR_FIX16K_80000:
815 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000;
816 break;
817 case IA32_MTRR_FIX16K_A0000:
818 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000;
819 break;
820 case IA32_MTRR_FIX4K_C0000:
821 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000;
822 break;
823 case IA32_MTRR_FIX4K_C8000:
824 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000;
825 break;
826 case IA32_MTRR_FIX4K_D0000:
827 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000;
828 break;
829 case IA32_MTRR_FIX4K_D8000:
830 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000;
831 break;
832 case IA32_MTRR_FIX4K_E0000:
833 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000;
834 break;
835 case IA32_MTRR_FIX4K_E8000:
836 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000;
837 break;
838 case IA32_MTRR_FIX4K_F0000:
839 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000;
840 break;
841 case IA32_MTRR_FIX4K_F8000:
842 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000;
843 break;
844
845 case MSR_K6_EFER:
846 *puValue = pVCpu->cpum.s.Guest.msrEFER;
847 break;
848
849 case MSR_K8_SF_MASK:
850 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
851 break;
852
853 case MSR_K6_STAR:
854 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
855 break;
856
857 case MSR_K8_LSTAR:
858 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
859 break;
860
861 case MSR_K8_CSTAR:
862 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
863 break;
864
865 case MSR_K8_FS_BASE:
866 *puValue = pVCpu->cpum.s.Guest.fsHid.u64Base;
867 break;
868
869 case MSR_K8_GS_BASE:
870 *puValue = pVCpu->cpum.s.Guest.gsHid.u64Base;
871 break;
872
873 case MSR_K8_KERNEL_GS_BASE:
874 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
875 break;
876
877 case MSR_K8_TSC_AUX:
878 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
879 break;
880
881 case MSR_IA32_PERF_STATUS:
882 /** @todo could really be not exactly correct, maybe use host's values */
883 *puValue = UINT64_C(1000) /* TSC increment by tick */
884 | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
885 | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
886 break;
887
888 case MSR_IA32_FSB_CLOCK_STS:
889 /*
890 * Encoded as:
891 * 0 - 266
892 * 1 - 133
893 * 2 - 200
894 * 3 - return 166
895 * 5 - return 100
896 */
897 *puValue = (2 << 4);
898 break;
899
900 case MSR_IA32_PLATFORM_INFO:
901 *puValue = (u8Multiplier << 8) /* Flex ratio max */
902 | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
903 break;
904
905 case MSR_IA32_THERM_STATUS:
906 /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
907 *puValue = RT_BIT(31) /* validity bit */
908 | (UINT64_C(20) << 16) /* degrees till TCC */;
909 break;
910
911 case MSR_IA32_MISC_ENABLE:
912#if 0
913 /* Needs to be tested more before enabling. */
914 *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
915#else
916 /* Currenty we don't allow guests to modify enable MSRs. */
917 *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
918
919 if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
920
921 *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
922 /** @todo: add more cpuid-controlled features this way. */
923#endif
924 break;
925
926#if 0 /*def IN_RING0 */
927 case MSR_IA32_PLATFORM_ID:
928 case MSR_IA32_BIOS_SIGN_ID:
929 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
930 {
931 /* Available since the P6 family. VT-x implies that this feature is present. */
932 if (idMsr == MSR_IA32_PLATFORM_ID)
933 *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
934 else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
935 *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
936 break;
937 }
938 /* no break */
939#endif
940
941 default:
942 /* In X2APIC specification this range is reserved for APIC control. */
943 if ( idMsr >= MSR_IA32_APIC_START
944 && idMsr < MSR_IA32_APIC_END)
945 {
946 rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
947 if (RT_SUCCESS(rc))
948 rc = VINF_SUCCESS;
949 else
950 {
951 *puValue = 0;
952 rc = VERR_CPUM_RAISE_GP_0;
953 }
954 }
955 else
956 {
957 *puValue = 0;
958 rc = VERR_CPUM_RAISE_GP_0;
959 }
960 break;
961 }
962
963 return rc;
964}
965
966
967/**
968 * Sets the MSR.
969 *
970 * The caller is responsible for checking privilege if the call is the result
971 * of a WRMSR instruction. We'll do the rest.
972 *
973 * @retval VINF_SUCCESS on success.
974 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
975 * appropriate actions.
976 *
977 * @param pVCpu Pointer to the VMCPU.
978 * @param idMsr The MSR id.
979 * @param uValue The value to set.
980 *
981 * @remarks Everyone changing MSR values, including the recompiler, shall do it
982 * by calling this method. This makes sure we have current values and
983 * that we trigger all the right actions when something changes.
984 */
985VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
986{
987 /*
988 * If we don't indicate MSR support in the CPUID feature bits, indicate
989 * that a #GP(0) should be raised.
990 */
991 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
992 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
993
994 int rc = VINF_SUCCESS;
995 switch (idMsr)
996 {
997 case MSR_IA32_MISC_ENABLE:
998 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue;
999 break;
1000
1001 case MSR_IA32_TSC:
1002 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
1003 break;
1004
1005 case MSR_IA32_APICBASE:
1006 rc = PDMApicSetBase(pVCpu->CTX_SUFF(pVM), uValue);
1007 if (rc != VINF_SUCCESS)
1008 rc = VERR_CPUM_RAISE_GP_0;
1009 break;
1010
1011 case MSR_IA32_CR_PAT:
1012 pVCpu->cpum.s.Guest.msrPAT = uValue;
1013 break;
1014
1015 case MSR_IA32_SYSENTER_CS:
1016 pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
1017 break;
1018
1019 case MSR_IA32_SYSENTER_EIP:
1020 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
1021 break;
1022
1023 case MSR_IA32_SYSENTER_ESP:
1024 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
1025 break;
1026
1027 case MSR_IA32_MTRR_CAP:
1028 return VERR_CPUM_RAISE_GP_0;
1029
1030 case MSR_IA32_MTRR_DEF_TYPE:
1031 if ( (uValue & UINT64_C(0xfffffffffffff300))
1032 || ( (uValue & 0xff) != 0
1033 && (uValue & 0xff) != 1
1034 && (uValue & 0xff) != 4
1035 && (uValue & 0xff) != 5
1036 && (uValue & 0xff) != 6) )
1037 {
1038 Log(("MSR_IA32_MTRR_DEF_TYPE: #GP(0) - writing reserved value (%#llx)\n", uValue));
1039 return VERR_CPUM_RAISE_GP_0;
1040 }
1041 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
1042 break;
1043
1044 case IA32_MTRR_FIX64K_00000:
1045 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000 = uValue;
1046 break;
1047 case IA32_MTRR_FIX16K_80000:
1048 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000 = uValue;
1049 break;
1050 case IA32_MTRR_FIX16K_A0000:
1051 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000 = uValue;
1052 break;
1053 case IA32_MTRR_FIX4K_C0000:
1054 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000 = uValue;
1055 break;
1056 case IA32_MTRR_FIX4K_C8000:
1057 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000 = uValue;
1058 break;
1059 case IA32_MTRR_FIX4K_D0000:
1060 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000 = uValue;
1061 break;
1062 case IA32_MTRR_FIX4K_D8000:
1063 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000 = uValue;
1064 break;
1065 case IA32_MTRR_FIX4K_E0000:
1066 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000 = uValue;
1067 break;
1068 case IA32_MTRR_FIX4K_E8000:
1069 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000 = uValue;
1070 break;
1071 case IA32_MTRR_FIX4K_F0000:
1072 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000 = uValue;
1073 break;
1074 case IA32_MTRR_FIX4K_F8000:
1075 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000 = uValue;
1076 break;
1077
1078 case MSR_K6_EFER:
1079 {
1080 PVM pVM = pVCpu->CTX_SUFF(pVM);
1081 uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
1082 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1083 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1084 : 0;
1085 uint64_t fMask = 0;
1086
1087 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1088 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_NX)
1089 fMask |= MSR_K6_EFER_NXE;
1090 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
1091 fMask |= MSR_K6_EFER_LME;
1092 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_SEP)
1093 fMask |= MSR_K6_EFER_SCE;
1094 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1095 fMask |= MSR_K6_EFER_FFXSR;
1096
1097 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1098 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1099 if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1100 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1101 {
1102 Log(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1103 return VERR_CPUM_RAISE_GP_0;
1104 }
1105
1106 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1107 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1108 ("Unexpected value %RX64\n", uValue));
1109 pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
1110
1111 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1112 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1113 if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1114 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1115 {
1116 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1117 HWACCMFlushTLB(pVCpu);
1118
1119 /* Notify PGM about NXE changes. */
1120 if ( (uOldEFER & MSR_K6_EFER_NXE)
1121 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1122 PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
1123 }
1124 break;
1125 }
1126
1127 case MSR_K8_SF_MASK:
1128 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1129 break;
1130
1131 case MSR_K6_STAR:
1132 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1133 break;
1134
1135 case MSR_K8_LSTAR:
1136 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1137 break;
1138
1139 case MSR_K8_CSTAR:
1140 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1141 break;
1142
1143 case MSR_K8_FS_BASE:
1144 pVCpu->cpum.s.Guest.fsHid.u64Base = uValue;
1145 break;
1146
1147 case MSR_K8_GS_BASE:
1148 pVCpu->cpum.s.Guest.gsHid.u64Base = uValue;
1149 break;
1150
1151 case MSR_K8_KERNEL_GS_BASE:
1152 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1153 break;
1154
1155 case MSR_K8_TSC_AUX:
1156 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1157 break;
1158
1159 default:
1160 /* In X2APIC specification this range is reserved for APIC control. */
1161 if ( idMsr >= MSR_IA32_APIC_START
1162 && idMsr < MSR_IA32_APIC_END)
1163 {
1164 rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1165 if (rc != VINF_SUCCESS)
1166 rc = VERR_CPUM_RAISE_GP_0;
1167 }
1168 else
1169 {
1170 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
1171 /** @todo rc = VERR_CPUM_RAISE_GP_0 */
1172 Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
1173 }
1174 break;
1175 }
1176 return rc;
1177}
1178
1179
1180VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
1181{
1182 if (pcbLimit)
1183 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
1184 return pVCpu->cpum.s.Guest.idtr.pIdt;
1185}
1186
1187
1188VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
1189{
1190 if (pHidden)
1191 *pHidden = pVCpu->cpum.s.Guest.trHid;
1192 return pVCpu->cpum.s.Guest.tr;
1193}
1194
1195
1196VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
1197{
1198 return pVCpu->cpum.s.Guest.cs;
1199}
1200
1201
1202VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
1203{
1204 return pVCpu->cpum.s.Guest.ds;
1205}
1206
1207
1208VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
1209{
1210 return pVCpu->cpum.s.Guest.es;
1211}
1212
1213
1214VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
1215{
1216 return pVCpu->cpum.s.Guest.fs;
1217}
1218
1219
1220VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
1221{
1222 return pVCpu->cpum.s.Guest.gs;
1223}
1224
1225
1226VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
1227{
1228 return pVCpu->cpum.s.Guest.ss;
1229}
1230
1231
1232VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
1233{
1234 return pVCpu->cpum.s.Guest.ldtr;
1235}
1236
1237
1238VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
1239{
1240 return pVCpu->cpum.s.Guest.cr0;
1241}
1242
1243
1244VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
1245{
1246 return pVCpu->cpum.s.Guest.cr2;
1247}
1248
1249
1250VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
1251{
1252 return pVCpu->cpum.s.Guest.cr3;
1253}
1254
1255
1256VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
1257{
1258 return pVCpu->cpum.s.Guest.cr4;
1259}
1260
1261
1262VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
1263{
1264 uint64_t u64;
1265 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
1266 if (RT_FAILURE(rc))
1267 u64 = 0;
1268 return u64;
1269}
1270
1271
1272VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
1273{
1274 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
1275}
1276
1277
1278VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
1279{
1280 return pVCpu->cpum.s.Guest.eip;
1281}
1282
1283
1284VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1285{
1286 return pVCpu->cpum.s.Guest.rip;
1287}
1288
1289
1290VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1291{
1292 return pVCpu->cpum.s.Guest.eax;
1293}
1294
1295
1296VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1297{
1298 return pVCpu->cpum.s.Guest.ebx;
1299}
1300
1301
1302VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1303{
1304 return pVCpu->cpum.s.Guest.ecx;
1305}
1306
1307
1308VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1309{
1310 return pVCpu->cpum.s.Guest.edx;
1311}
1312
1313
1314VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1315{
1316 return pVCpu->cpum.s.Guest.esi;
1317}
1318
1319
1320VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1321{
1322 return pVCpu->cpum.s.Guest.edi;
1323}
1324
1325
1326VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1327{
1328 return pVCpu->cpum.s.Guest.esp;
1329}
1330
1331
1332VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1333{
1334 return pVCpu->cpum.s.Guest.ebp;
1335}
1336
1337
1338VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1339{
1340 return pVCpu->cpum.s.Guest.eflags.u32;
1341}
1342
1343
1344VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1345{
1346 switch (iReg)
1347 {
1348 case DISCREG_CR0:
1349 *pValue = pVCpu->cpum.s.Guest.cr0;
1350 break;
1351
1352 case DISCREG_CR2:
1353 *pValue = pVCpu->cpum.s.Guest.cr2;
1354 break;
1355
1356 case DISCREG_CR3:
1357 *pValue = pVCpu->cpum.s.Guest.cr3;
1358 break;
1359
1360 case DISCREG_CR4:
1361 *pValue = pVCpu->cpum.s.Guest.cr4;
1362 break;
1363
1364 case DISCREG_CR8:
1365 {
1366 uint8_t u8Tpr;
1367 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /*pfPending*/);
1368 if (RT_FAILURE(rc))
1369 {
1370 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1371 *pValue = 0;
1372 return rc;
1373 }
1374 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
1375 break;
1376 }
1377
1378 default:
1379 return VERR_INVALID_PARAMETER;
1380 }
1381 return VINF_SUCCESS;
1382}
1383
1384
1385VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1386{
1387 return pVCpu->cpum.s.Guest.dr[0];
1388}
1389
1390
1391VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1392{
1393 return pVCpu->cpum.s.Guest.dr[1];
1394}
1395
1396
1397VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1398{
1399 return pVCpu->cpum.s.Guest.dr[2];
1400}
1401
1402
1403VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1404{
1405 return pVCpu->cpum.s.Guest.dr[3];
1406}
1407
1408
1409VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1410{
1411 return pVCpu->cpum.s.Guest.dr[6];
1412}
1413
1414
1415VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1416{
1417 return pVCpu->cpum.s.Guest.dr[7];
1418}
1419
1420
1421VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1422{
1423 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1424 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1425 if (iReg == 4 || iReg == 5)
1426 iReg += 2;
1427 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1428 return VINF_SUCCESS;
1429}
1430
1431
1432VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1433{
1434 return pVCpu->cpum.s.Guest.msrEFER;
1435}
1436
1437
1438/**
1439 * Gets a CpuId leaf.
1440 *
1441 * @param pVCpu Pointer to the VMCPU.
1442 * @param iLeaf The CPUID leaf to get.
1443 * @param pEax Where to store the EAX value.
1444 * @param pEbx Where to store the EBX value.
1445 * @param pEcx Where to store the ECX value.
1446 * @param pEdx Where to store the EDX value.
1447 */
1448VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1449{
1450 PVM pVM = pVCpu->CTX_SUFF(pVM);
1451
1452 PCCPUMCPUID pCpuId;
1453 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1454 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1455 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1456 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1457 else if ( iLeaf - UINT32_C(0x40000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdHyper)
1458 && (pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_HVP))
1459 pCpuId = &pVM->cpum.s.aGuestCpuIdHyper[iLeaf - UINT32_C(0x40000000)]; /* Only report if HVP bit set. */
1460 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1461 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1462 else
1463 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1464
1465 uint32_t cCurrentCacheIndex = *pEcx;
1466
1467 *pEax = pCpuId->eax;
1468 *pEbx = pCpuId->ebx;
1469 *pEcx = pCpuId->ecx;
1470 *pEdx = pCpuId->edx;
1471
1472 if ( iLeaf == 1)
1473 {
1474 /* Bits 31-24: Initial APIC ID */
1475 Assert(pVCpu->idCpu <= 255);
1476 *pEbx |= (pVCpu->idCpu << 24);
1477 }
1478
1479 if ( iLeaf == 4
1480 && cCurrentCacheIndex < 3
1481 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1482 {
1483 uint32_t type, level, sharing, linesize,
1484 partitions, associativity, sets, cores;
1485
1486 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1487 partitions = 1;
1488 /* Those are only to shut up compiler, as they will always
1489 get overwritten, and compiler should be able to figure that out */
1490 sets = associativity = sharing = level = 1;
1491 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1492 switch (cCurrentCacheIndex)
1493 {
1494 case 0:
1495 type = 1;
1496 level = 1;
1497 sharing = 1;
1498 linesize = 64;
1499 associativity = 8;
1500 sets = 64;
1501 break;
1502 case 1:
1503 level = 1;
1504 type = 2;
1505 sharing = 1;
1506 linesize = 64;
1507 associativity = 8;
1508 sets = 64;
1509 break;
1510 default: /* shut up gcc.*/
1511 AssertFailed();
1512 case 2:
1513 level = 2;
1514 type = 3;
1515 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1516 linesize = 64;
1517 associativity = 24;
1518 sets = 4096;
1519 break;
1520 }
1521
1522 *pEax |= ((cores - 1) << 26) |
1523 ((sharing - 1) << 14) |
1524 (level << 5) |
1525 1;
1526 *pEbx = (linesize - 1) |
1527 ((partitions - 1) << 12) |
1528 ((associativity - 1) << 22); /* -1 encoding */
1529 *pEcx = sets - 1;
1530 }
1531
1532 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1533}
1534
1535/**
1536 * Gets a number of standard CPUID leafs.
1537 *
1538 * @returns Number of leafs.
1539 * @param pVM Pointer to the VM.
1540 * @remark Intended for PATM.
1541 */
1542VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1543{
1544 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1545}
1546
1547
1548/**
1549 * Gets a number of extended CPUID leafs.
1550 *
1551 * @returns Number of leafs.
1552 * @param pVM Pointer to the VM.
1553 * @remark Intended for PATM.
1554 */
1555VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1556{
1557 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1558}
1559
1560
1561/**
1562 * Gets a number of centaur CPUID leafs.
1563 *
1564 * @returns Number of leafs.
1565 * @param pVM Pointer to the VM.
1566 * @remark Intended for PATM.
1567 */
1568VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1569{
1570 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1571}
1572
1573
1574/**
1575 * Sets a CPUID feature bit.
1576 *
1577 * @param pVM Pointer to the VM.
1578 * @param enmFeature The feature to set.
1579 */
1580VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1581{
1582 switch (enmFeature)
1583 {
1584 /*
1585 * Set the APIC bit in both feature masks.
1586 */
1587 case CPUMCPUIDFEATURE_APIC:
1588 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1589 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1590 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1591 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1592 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1593 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1594 break;
1595
1596 /*
1597 * Set the x2APIC bit in the standard feature mask.
1598 */
1599 case CPUMCPUIDFEATURE_X2APIC:
1600 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1601 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1602 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1603 break;
1604
1605 /*
1606 * Set the sysenter/sysexit bit in the standard feature mask.
1607 * Assumes the caller knows what it's doing! (host must support these)
1608 */
1609 case CPUMCPUIDFEATURE_SEP:
1610 {
1611 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1612 {
1613 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1614 return;
1615 }
1616
1617 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1618 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1619 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1620 break;
1621 }
1622
1623 /*
1624 * Set the syscall/sysret bit in the extended feature mask.
1625 * Assumes the caller knows what it's doing! (host must support these)
1626 */
1627 case CPUMCPUIDFEATURE_SYSCALL:
1628 {
1629 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1630 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_SEP))
1631 {
1632#if HC_ARCH_BITS == 32
1633 /* X86_CPUID_AMD_FEATURE_EDX_SEP not set it seems in 32 bits mode.
1634 * Even when the cpu is capable of doing so in 64 bits mode.
1635 */
1636 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1637 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
1638 || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1639#endif
1640 {
1641 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1642 return;
1643 }
1644 }
1645 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1646 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_SEP;
1647 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1648 break;
1649 }
1650
1651 /*
1652 * Set the PAE bit in both feature masks.
1653 * Assumes the caller knows what it's doing! (host must support these)
1654 */
1655 case CPUMCPUIDFEATURE_PAE:
1656 {
1657 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1658 {
1659 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1660 return;
1661 }
1662
1663 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1664 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1665 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1666 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1667 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1668 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1669 break;
1670 }
1671
1672 /*
1673 * Set the LONG MODE bit in the extended feature mask.
1674 * Assumes the caller knows what it's doing! (host must support these)
1675 */
1676 case CPUMCPUIDFEATURE_LONG_MODE:
1677 {
1678 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1679 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1680 {
1681 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1682 return;
1683 }
1684
1685 /* Valid for both Intel and AMD. */
1686 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1687 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1688 break;
1689 }
1690
1691 /*
1692 * Set the NXE bit in the extended feature mask.
1693 * Assumes the caller knows what it's doing! (host must support these)
1694 */
1695 case CPUMCPUIDFEATURE_NXE:
1696 {
1697 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1698 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_NX))
1699 {
1700 LogRel(("WARNING: Can't turn on NXE when the host doesn't support it!!\n"));
1701 return;
1702 }
1703
1704 /* Valid for both Intel and AMD. */
1705 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_NX;
1706 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NXE\n"));
1707 break;
1708 }
1709
1710 case CPUMCPUIDFEATURE_LAHF:
1711 {
1712 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1713 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF))
1714 {
1715 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
1716 return;
1717 }
1718
1719 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1720 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
1721 break;
1722 }
1723
1724 case CPUMCPUIDFEATURE_PAT:
1725 {
1726 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1727 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
1728 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1729 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1730 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
1731 LogRel(("CPUMClearGuestCpuIdFeature: Enabled PAT\n"));
1732 break;
1733 }
1734
1735 case CPUMCPUIDFEATURE_RDTSCP:
1736 {
1737 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1738 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_RDTSCP)
1739 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
1740 {
1741 if (!pVM->cpum.s.u8PortableCpuIdLevel)
1742 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
1743 return;
1744 }
1745
1746 /* Valid for AMD only (for now). */
1747 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_RDTSCP;
1748 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
1749 break;
1750 }
1751
1752 /*
1753 * Set the Hypervisor Present bit in the standard feature mask.
1754 */
1755 case CPUMCPUIDFEATURE_HVP:
1756 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1757 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;
1758 LogRel(("CPUMSetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
1759 break;
1760
1761 default:
1762 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1763 break;
1764 }
1765 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1766 {
1767 PVMCPU pVCpu = &pVM->aCpus[i];
1768 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1769 }
1770}
1771
1772
1773/**
1774 * Queries a CPUID feature bit.
1775 *
1776 * @returns boolean for feature presence
1777 * @param pVM Pointer to the VM.
1778 * @param enmFeature The feature to query.
1779 */
1780VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1781{
1782 switch (enmFeature)
1783 {
1784 case CPUMCPUIDFEATURE_PAE:
1785 {
1786 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1787 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
1788 break;
1789 }
1790
1791 case CPUMCPUIDFEATURE_NXE:
1792 {
1793 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1794 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_NX);
1795 }
1796
1797 case CPUMCPUIDFEATURE_RDTSCP:
1798 {
1799 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1800 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1801 break;
1802 }
1803
1804 case CPUMCPUIDFEATURE_LONG_MODE:
1805 {
1806 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1807 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1808 break;
1809 }
1810
1811 default:
1812 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1813 break;
1814 }
1815 return false;
1816}
1817
1818
1819/**
1820 * Clears a CPUID feature bit.
1821 *
1822 * @param pVM Pointer to the VM.
1823 * @param enmFeature The feature to clear.
1824 */
1825VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1826{
1827 switch (enmFeature)
1828 {
1829 /*
1830 * Set the APIC bit in both feature masks.
1831 */
1832 case CPUMCPUIDFEATURE_APIC:
1833 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1834 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
1835 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1836 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1837 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
1838 Log(("CPUMSetGuestCpuIdFeature: Disabled APIC\n"));
1839 break;
1840
1841 /*
1842 * Clear the x2APIC bit in the standard feature mask.
1843 */
1844 case CPUMCPUIDFEATURE_X2APIC:
1845 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1846 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
1847 LogRel(("CPUMSetGuestCpuIdFeature: Disabled x2APIC\n"));
1848 break;
1849
1850 case CPUMCPUIDFEATURE_PAE:
1851 {
1852 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1853 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
1854 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1855 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1856 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
1857 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
1858 break;
1859 }
1860
1861 case CPUMCPUIDFEATURE_PAT:
1862 {
1863 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1864 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
1865 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1866 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1867 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
1868 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
1869 break;
1870 }
1871
1872 case CPUMCPUIDFEATURE_LONG_MODE:
1873 {
1874 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1875 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_LONG_MODE;
1876 break;
1877 }
1878
1879 case CPUMCPUIDFEATURE_LAHF:
1880 {
1881 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1882 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF;
1883 break;
1884 }
1885
1886 case CPUMCPUIDFEATURE_HVP:
1887 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1888 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP;
1889 break;
1890
1891 default:
1892 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1893 break;
1894 }
1895 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1896 {
1897 PVMCPU pVCpu = &pVM->aCpus[i];
1898 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1899 }
1900}
1901
1902
1903/**
1904 * Gets the host CPU vendor
1905 *
1906 * @returns CPU vendor
1907 * @param pVM Pointer to the VM.
1908 */
1909VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
1910{
1911 return pVM->cpum.s.enmHostCpuVendor;
1912}
1913
1914/**
1915 * Gets the CPU vendor
1916 *
1917 * @returns CPU vendor
1918 * @param pVM Pointer to the VM.
1919 */
1920VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
1921{
1922 return pVM->cpum.s.enmGuestCpuVendor;
1923}
1924
1925
1926VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
1927{
1928 pVCpu->cpum.s.Guest.dr[0] = uDr0;
1929 return CPUMRecalcHyperDRx(pVCpu);
1930}
1931
1932
1933VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
1934{
1935 pVCpu->cpum.s.Guest.dr[1] = uDr1;
1936 return CPUMRecalcHyperDRx(pVCpu);
1937}
1938
1939
1940VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
1941{
1942 pVCpu->cpum.s.Guest.dr[2] = uDr2;
1943 return CPUMRecalcHyperDRx(pVCpu);
1944}
1945
1946
1947VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
1948{
1949 pVCpu->cpum.s.Guest.dr[3] = uDr3;
1950 return CPUMRecalcHyperDRx(pVCpu);
1951}
1952
1953
1954VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
1955{
1956 pVCpu->cpum.s.Guest.dr[6] = uDr6;
1957 return CPUMRecalcHyperDRx(pVCpu);
1958}
1959
1960
1961VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
1962{
1963 pVCpu->cpum.s.Guest.dr[7] = uDr7;
1964 return CPUMRecalcHyperDRx(pVCpu);
1965}
1966
1967
1968VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
1969{
1970 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1971 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1972 if (iReg == 4 || iReg == 5)
1973 iReg += 2;
1974 pVCpu->cpum.s.Guest.dr[iReg] = Value;
1975 return CPUMRecalcHyperDRx(pVCpu);
1976}
1977
1978
1979/**
1980 * Recalculates the hypervisor DRx register values based on
1981 * current guest registers and DBGF breakpoints.
1982 *
1983 * This is called whenever a guest DRx register is modified and when DBGF
1984 * sets a hardware breakpoint. In guest context this function will reload
1985 * any (hyper) DRx registers which comes out with a different value.
1986 *
1987 * @returns VINF_SUCCESS.
1988 * @param pVCpu Pointer to the VMCPU.
1989 */
1990VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu)
1991{
1992 PVM pVM = pVCpu->CTX_SUFF(pVM);
1993
1994 /*
1995 * Compare the DR7s first.
1996 *
1997 * We only care about the enabled flags. The GE and LE flags are always
1998 * set and we don't care if the guest doesn't set them. GD is virtualized
1999 * when we dispatch #DB, we never enable it.
2000 */
2001 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
2002#ifdef CPUM_VIRTUALIZE_DRX
2003 const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
2004#else
2005 const RTGCUINTREG uGstDr7 = 0;
2006#endif
2007 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
2008 {
2009 /*
2010 * Ok, something is enabled. Recalc each of the breakpoints.
2011 * Straight forward code, not optimized/minimized in any way.
2012 */
2013 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
2014
2015 /* bp 0 */
2016 RTGCUINTREG uNewDr0;
2017 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
2018 {
2019 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2020 uNewDr0 = DBGFBpGetDR0(pVM);
2021 }
2022 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
2023 {
2024 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2025 uNewDr0 = CPUMGetGuestDR0(pVCpu);
2026 }
2027 else
2028 uNewDr0 = pVCpu->cpum.s.Hyper.dr[0];
2029
2030 /* bp 1 */
2031 RTGCUINTREG uNewDr1;
2032 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
2033 {
2034 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2035 uNewDr1 = DBGFBpGetDR1(pVM);
2036 }
2037 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
2038 {
2039 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2040 uNewDr1 = CPUMGetGuestDR1(pVCpu);
2041 }
2042 else
2043 uNewDr1 = pVCpu->cpum.s.Hyper.dr[1];
2044
2045 /* bp 2 */
2046 RTGCUINTREG uNewDr2;
2047 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
2048 {
2049 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2050 uNewDr2 = DBGFBpGetDR2(pVM);
2051 }
2052 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
2053 {
2054 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2055 uNewDr2 = CPUMGetGuestDR2(pVCpu);
2056 }
2057 else
2058 uNewDr2 = pVCpu->cpum.s.Hyper.dr[2];
2059
2060 /* bp 3 */
2061 RTGCUINTREG uNewDr3;
2062 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
2063 {
2064 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2065 uNewDr3 = DBGFBpGetDR3(pVM);
2066 }
2067 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
2068 {
2069 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2070 uNewDr3 = CPUMGetGuestDR3(pVCpu);
2071 }
2072 else
2073 uNewDr3 = pVCpu->cpum.s.Hyper.dr[3];
2074
2075 /*
2076 * Apply the updates.
2077 */
2078#ifdef IN_RC
2079 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
2080 {
2081 /** @todo save host DBx registers. */
2082 }
2083#endif
2084 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
2085 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
2086 CPUMSetHyperDR3(pVCpu, uNewDr3);
2087 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
2088 CPUMSetHyperDR2(pVCpu, uNewDr2);
2089 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
2090 CPUMSetHyperDR1(pVCpu, uNewDr1);
2091 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
2092 CPUMSetHyperDR0(pVCpu, uNewDr0);
2093 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
2094 CPUMSetHyperDR7(pVCpu, uNewDr7);
2095 }
2096 else
2097 {
2098#ifdef IN_RC
2099 if (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
2100 {
2101 /** @todo restore host DBx registers. */
2102 }
2103#endif
2104 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
2105 }
2106 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
2107 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
2108 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
2109 pVCpu->cpum.s.Hyper.dr[7]));
2110
2111 return VINF_SUCCESS;
2112}
2113
2114
2115/**
2116 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
2117 *
2118 * @returns true if in real mode, otherwise false.
2119 * @param pVCpu Pointer to the VMCPU.
2120 */
2121VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
2122{
2123 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
2124}
2125
2126
2127/**
2128 * Tests if the guest has the Page Size Extension enabled (PSE).
2129 *
2130 * @returns true if in real mode, otherwise false.
2131 * @param pVCpu Pointer to the VMCPU.
2132 */
2133VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
2134{
2135 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
2136 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
2137}
2138
2139
2140/**
2141 * Tests if the guest has the paging enabled (PG).
2142 *
2143 * @returns true if in real mode, otherwise false.
2144 * @param pVCpu Pointer to the VMCPU.
2145 */
2146VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
2147{
2148 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
2149}
2150
2151
2152/**
2153 * Tests if the guest has the paging enabled (PG).
2154 *
2155 * @returns true if in real mode, otherwise false.
2156 * @param pVCpu Pointer to the VMCPU.
2157 */
2158VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
2159{
2160 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
2161}
2162
2163
2164/**
2165 * Tests if the guest is running in real mode or not.
2166 *
2167 * @returns true if in real mode, otherwise false.
2168 * @param pVCpu Pointer to the VMCPU.
2169 */
2170VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
2171{
2172 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2173}
2174
2175
2176/**
2177 * Tests if the guest is running in real or virtual 8086 mode.
2178 *
2179 * @returns @c true if it is, @c false if not.
2180 * @param pVCpu Pointer to the VMCPU.
2181 */
2182VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
2183{
2184 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2185 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
2186}
2187
2188
2189/**
2190 * Tests if the guest is running in protected or not.
2191 *
2192 * @returns true if in protected mode, otherwise false.
2193 * @param pVCpu Pointer to the VMCPU.
2194 */
2195VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
2196{
2197 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2198}
2199
2200
2201/**
2202 * Tests if the guest is running in paged protected or not.
2203 *
2204 * @returns true if in paged protected mode, otherwise false.
2205 * @param pVCpu Pointer to the VMCPU.
2206 */
2207VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
2208{
2209 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
2210}
2211
2212
2213/**
2214 * Tests if the guest is running in long mode or not.
2215 *
2216 * @returns true if in long mode, otherwise false.
2217 * @param pVCpu Pointer to the VMCPU.
2218 */
2219VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
2220{
2221 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
2222}
2223
2224
2225/**
2226 * Tests if the guest is running in PAE mode or not.
2227 *
2228 * @returns true if in PAE mode, otherwise false.
2229 * @param pVCpu Pointer to the VMCPU.
2230 */
2231VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
2232{
2233 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
2234 && (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG)
2235 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
2236}
2237
2238
2239#ifndef IN_RING0
2240/**
2241 * Updates the EFLAGS while we're in raw-mode.
2242 *
2243 * @param pVCpu Pointer to the VMCPU.
2244 * @param pCtxCore The context core.
2245 * @param eflags The new EFLAGS value.
2246 */
2247VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t eflags)
2248{
2249 PVM pVM = pVCpu->CTX_SUFF(pVM);
2250
2251 if (!pVCpu->cpum.s.fRawEntered)
2252 {
2253 pCtxCore->eflags.u32 = eflags;
2254 return;
2255 }
2256 PATMRawSetEFlags(pVM, pCtxCore, eflags);
2257}
2258#endif /* !IN_RING0 */
2259
2260
2261/**
2262 * Gets the EFLAGS while we're in raw-mode.
2263 *
2264 * @returns The eflags.
2265 * @param pVCpu Pointer to the VMCPU.
2266 * @param pCtxCore The context core.
2267 */
2268VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2269{
2270#ifdef IN_RING0
2271 NOREF(pVCpu);
2272 return pCtxCore->eflags.u32;
2273#else
2274 PVM pVM = pVCpu->CTX_SUFF(pVM);
2275
2276 if (!pVCpu->cpum.s.fRawEntered)
2277 return pCtxCore->eflags.u32;
2278 return PATMRawGetEFlags(pVM, pCtxCore);
2279#endif
2280}
2281
2282
2283/**
2284 * Sets the specified changed flags (CPUM_CHANGED_*).
2285 *
2286 * @param pVCpu Pointer to the VMCPU.
2287 */
2288VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
2289{
2290 pVCpu->cpum.s.fChanged |= fChangedFlags;
2291}
2292
2293
2294/**
2295 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
2296 * @returns true if supported.
2297 * @returns false if not supported.
2298 * @param pVM Pointer to the VM.
2299 */
2300VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
2301{
2302 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
2303}
2304
2305
2306/**
2307 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
2308 * @returns true if used.
2309 * @returns false if not used.
2310 * @param pVM Pointer to the VM.
2311 */
2312VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
2313{
2314 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER) != 0;
2315}
2316
2317
2318/**
2319 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
2320 * @returns true if used.
2321 * @returns false if not used.
2322 * @param pVM Pointer to the VM.
2323 */
2324VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
2325{
2326 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL) != 0;
2327}
2328
2329#ifndef IN_RING3
2330
2331/**
2332 * Lazily sync in the FPU/XMM state
2333 *
2334 * @returns VBox status code.
2335 * @param pVCpu Pointer to the VMCPU.
2336 */
2337VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
2338{
2339 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
2340}
2341
2342#endif /* !IN_RING3 */
2343
2344/**
2345 * Checks if we activated the FPU/XMM state of the guest OS
2346 * @returns true if we did.
2347 * @returns false if not.
2348 * @param pVCpu Pointer to the VMCPU.
2349 */
2350VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
2351{
2352 return (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
2353}
2354
2355
2356/**
2357 * Deactivate the FPU/XMM state of the guest OS
2358 * @param pVCpu Pointer to the VMCPU.
2359 */
2360VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
2361{
2362 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
2363}
2364
2365
2366/**
2367 * Checks if the guest debug state is active
2368 *
2369 * @returns boolean
2370 * @param pVM Pointer to the VM.
2371 */
2372VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
2373{
2374 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS) != 0;
2375}
2376
2377/**
2378 * Checks if the hyper debug state is active
2379 *
2380 * @returns boolean
2381 * @param pVM Pointer to the VM.
2382 */
2383VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
2384{
2385 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HYPER) != 0;
2386}
2387
2388
2389/**
2390 * Mark the guest's debug state as inactive.
2391 *
2392 * @returns boolean
2393 * @param pVM Pointer to the VM.
2394 */
2395VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
2396{
2397 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
2398}
2399
2400
2401/**
2402 * Mark the hypervisor's debug state as inactive.
2403 *
2404 * @returns boolean
2405 * @param pVM Pointer to the VM.
2406 */
2407VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu)
2408{
2409 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2410}
2411
2412/**
2413 * Checks if the hidden selector registers are valid for the specified CPU.
2414 *
2415 * @returns true if they are.
2416 * @returns false if not.
2417 * @param pVCpu Pointer to the VM.
2418 */
2419VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVMCPU pVCpu)
2420{
2421 bool const fRc = !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID);
2422 Assert(fRc || !HWACCMIsEnabled(pVCpu->CTX_SUFF(pVM)));
2423 Assert(!pVCpu->cpum.s.fRemEntered);
2424 return fRc;
2425}
2426
2427
2428
2429/**
2430 * Get the current privilege level of the guest.
2431 *
2432 * @returns cpl
2433 * @param pVM Pointer to the VM.
2434 * @param pRegFrame Trap register frame.
2435 */
2436VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
2437{
2438 uint32_t cpl;
2439
2440 if (CPUMAreHiddenSelRegsValid(pVCpu))
2441 {
2442 /*
2443 * The hidden CS.DPL register is always equal to the CPL, it is
2444 * not affected by loading a conforming coding segment.
2445 *
2446 * This only seems to apply to AMD-V; in the VT-x case we *do* need to look
2447 * at SS. (ACP2 regression during install after a far call to ring 2)
2448 *
2449 * Seems it isn't necessiarly true for newer AMD-V CPUs even, we have
2450 * to move the VMCB.guest.u8CPL into Attr.n.u2Dpl to make this (and
2451 * other) code work right. So, forget CS.DPL, always use SS.DPL.
2452 */
2453 if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2454 {
2455 if (!pCtxCore->eflags.Bits.u1VM)
2456 cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
2457 else
2458 cpl = 3; /* REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
2459 }
2460 else
2461 cpl = 0; /* CPL set to 3 for VT-x real-mode emulation. */
2462 }
2463 else if (RT_LIKELY(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2464 {
2465 if (RT_LIKELY(!pCtxCore->eflags.Bits.u1VM))
2466 {
2467 /*
2468 * The SS RPL is always equal to the CPL, while the CS RPL
2469 * isn't necessarily equal if the segment is conforming.
2470 * See section 4.11.1 in the AMD manual.
2471 */
2472 cpl = (pCtxCore->ss & X86_SEL_RPL);
2473#ifndef IN_RING0
2474 if (cpl == 1)
2475 cpl = 0;
2476#endif
2477 }
2478 else
2479 cpl = 3;
2480 }
2481 else
2482 cpl = 0; /* real mode; cpl is zero */
2483
2484 return cpl;
2485}
2486
2487
2488/**
2489 * Gets the current guest CPU mode.
2490 *
2491 * If paging mode is what you need, check out PGMGetGuestMode().
2492 *
2493 * @returns The CPU mode.
2494 * @param pVCpu Pointer to the VMCPU.
2495 */
2496VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
2497{
2498 CPUMMODE enmMode;
2499 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2500 enmMode = CPUMMODE_REAL;
2501 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2502 enmMode = CPUMMODE_PROTECTED;
2503 else
2504 enmMode = CPUMMODE_LONG;
2505
2506 return enmMode;
2507}
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