EMAll.cpp@ 17596

Last change on this file since 17596 was 17531, checked in by vboxsync, 16 years ago
emInterpretStosWD: don't use PGMPhysWriteGCPtr but emRamWrite (new phys code only). I'd missed this case and it hit when booting windows with additions.
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1	/* $Id: EMAll.cpp 17531 2009-03-08 02:58:03Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_EM
26	#include <VBox/em.h>
27	#include <VBox/mm.h>
28	#include <VBox/selm.h>
29	#include <VBox/patm.h>
30	#include <VBox/csam.h>
31	#include <VBox/pgm.h>
32	#include <VBox/iom.h>
33	#include <VBox/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/vmm.h>
37	#include <VBox/hwaccm.h>
38	#include <VBox/tm.h>
39	#include <VBox/pdmapi.h>
40
41	#include <VBox/param.h>
42	#include <VBox/err.h>
43	#include <VBox/dis.h>
44	#include <VBox/disopcode.h>
45	#include <VBox/log.h>
46	#include <iprt/assert.h>
47	#include <iprt/asm.h>
48	#include <iprt/string.h>
49
50
51	/*******************************************************************************
52	* Defined Constants And Macros *
53	*******************************************************************************/
54	/** @def EM_ASSERT_FAULT_RETURN
55	* Safety check.
56	*
57	* Could in theory misfire on a cross page boundary access...
58	*
59	* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
60	* turns up an alias page instead of the original faulting one and annoying the
61	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
62	*/
63	#if 0
64	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
65	#else
66	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
67	#endif
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
74
75
76
77	/**
78	* Get the current execution manager status.
79	*
80	* @returns Current status.
81	*/
82	VMMDECL(EMSTATE) EMGetState(PVM pVM)
83	{
84	return pVM->em.s.enmState;
85	}
86
87	#ifndef IN_RC
88
89	/**
90	* Read callback for disassembly function; supports reading bytes that cross a page boundary
91	*
92	* @returns VBox status code.
93	* @param pSrc GC source pointer
94	* @param pDest HC destination pointer
95	* @param cb Number of bytes to read
96	* @param dwUserdata Callback specific user data (pCpu)
97	*
98	*/
99	DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t pDest, unsigned cb, void pvUserdata)
100	{
101	DISCPUSTATE pCpu = (DISCPUSTATE )pvUserdata;
102	PVM pVM = (PVM)pCpu->apvUserData[0];
103	# ifdef IN_RING0
104	int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
105	AssertMsgRC(rc, ("PGMPhysSimpleReadGCPtr failed for pSrc=%RGv cb=%x\n", pSrc, cb));
106	# else /* IN_RING3 */
107	if (!PATMIsPatchGCAddr(pVM, pSrc))
108	{
109	int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
110	AssertRC(rc);
111	}
112	else
113	{
114	for (uint32_t i = 0; i < cb; i++)
115	{
116	uint8_t opcode;
117	if (RT_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
118	{
119	*(pDest+i) = opcode;
120	}
121	}
122	}
123	# endif /* IN_RING3 */
124	return VINF_SUCCESS;
125	}
126
127	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
128	{
129	return DISCoreOneEx(InstrGC, pCpu->mode, EMReadBytes, pVM, pCpu, pOpsize);
130	}
131
132	#else /* IN_RC */
133
134	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
135	{
136	return DISCoreOne(pCpu, InstrGC, pOpsize);
137	}
138
139	#endif /* IN_RC */
140
141
142	/**
143	* Disassembles one instruction.
144	*
145	* @param pVM The VM handle.
146	* @param pCtxCore The context core (used for both the mode and instruction).
147	* @param pCpu Where to return the parsed instruction info.
148	* @param pcbInstr Where to return the instruction size. (optional)
149	*/
150	VMMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
151	{
152	RTGCPTR GCPtrInstr;
153	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
154	if (RT_FAILURE(rc))
155	{
156	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
157	pCtxCore->cs, (RTGCPTR)pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
158	return rc;
159	}
160	return EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pCpu, pcbInstr);
161	}
162
163
164	/**
165	* Disassembles one instruction.
166	*
167	* This is used by internally by the interpreter and by trap/access handlers.
168	*
169	* @param pVM The VM handle.
170	* @param GCPtrInstr The flat address of the instruction.
171	* @param pCtxCore The context core (used to determine the cpu mode).
172	* @param pCpu Where to return the parsed instruction info.
173	* @param pcbInstr Where to return the instruction size. (optional)
174	*/
175	VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
176	{
177	int rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
178	#ifdef IN_RC
179	NULL, NULL,
180	#else
181	EMReadBytes, pVM,
182	#endif
183	pCpu, pcbInstr);
184	if (RT_SUCCESS(rc))
185	return VINF_SUCCESS;
186	AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
187	return VERR_INTERNAL_ERROR;
188	}
189
190
191	/**
192	* Interprets the current instruction.
193	*
194	* @returns VBox status code.
195	* @retval VINF_* Scheduling instructions.
196	* @retval VERR_EM_INTERPRETER Something we can't cope with.
197	* @retval VERR_* Fatal errors.
198	*
199	* @param pVM The VM handle.
200	* @param pRegFrame The register frame.
201	* Updates the EIP if an instruction was executed successfully.
202	* @param pvFault The fault address (CR2).
203	* @param pcbSize Size of the write (if applicable).
204	*
205	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
206	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
207	* to worry about e.g. invalid modrm combinations (!)
208	*/
209	VMMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
210	{
211	RTGCPTR pbCode;
212
213	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
214	int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
215	if (RT_SUCCESS(rc))
216	{
217	uint32_t cbOp;
218	DISCPUSTATE Cpu;
219	Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
220	rc = emDisCoreOne(pVM, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
221	if (RT_SUCCESS(rc))
222	{
223	Assert(cbOp == Cpu.opsize);
224	rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, pvFault, pcbSize);
225	if (RT_SUCCESS(rc))
226	{
227	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
228	}
229	return rc;
230	}
231	}
232	return VERR_EM_INTERPRETER;
233	}
234
235
236	/**
237	* Interprets the current instruction using the supplied DISCPUSTATE structure.
238	*
239	* EIP is NOT updated!
240	*
241	* @returns VBox status code.
242	* @retval VINF_* Scheduling instructions. When these are returned, it
243	* starts to get a bit tricky to know whether code was
244	* executed or not... We'll address this when it becomes a problem.
245	* @retval VERR_EM_INTERPRETER Something we can't cope with.
246	* @retval VERR_* Fatal errors.
247	*
248	* @param pVM The VM handle.
249	* @param pCpu The disassembler cpu state for the instruction to be interpreted.
250	* @param pRegFrame The register frame. EIP is NOT changed!
251	* @param pvFault The fault address (CR2).
252	* @param pcbSize Size of the write (if applicable).
253	*
254	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
255	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
256	* to worry about e.g. invalid modrm combinations (!)
257	*
258	* @todo At this time we do NOT check if the instruction overwrites vital information.
259	* Make sure this can't happen!! (will add some assertions/checks later)
260	*/
261	VMMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
262	{
263	STAM_PROFILE_START(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
264	int rc = emInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, pcbSize);
265	STAM_PROFILE_STOP(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
266	if (RT_SUCCESS(rc))
267	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
268	else
269	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
270	return rc;
271	}
272
273
274	/**
275	* Interpret a port I/O instruction.
276	*
277	* @returns VBox status code suitable for scheduling.
278	* @param pVM The VM handle.
279	* @param pCtxCore The context core. This will be updated on successful return.
280	* @param pCpu The instruction to interpret.
281	* @param cbOp The size of the instruction.
282	* @remark This may raise exceptions.
283	*/
284	VMMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp)
285	{
286	/*
287	* Hand it on to IOM.
288	*/
289	#ifdef IN_RC
290	int rc = IOMGCIOPortHandler(pVM, pCtxCore, pCpu);
291	if (IOM_SUCCESS(rc))
292	pCtxCore->rip += cbOp;
293	return rc;
294	#else
295	AssertReleaseMsgFailed(("not implemented\n"));
296	return VERR_NOT_IMPLEMENTED;
297	#endif
298	}
299
300
301	DECLINLINE(int) emRamRead(PVM pVM, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
302	{
303	#ifdef IN_RC
304	int rc = MMGCRamRead(pVM, pvDst, (void *)GCPtrSrc, cb);
305	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
306	return rc;
307	/*
308	* The page pool cache may end up here in some cases because it
309	* flushed one of the shadow mappings used by the trapping
310	* instruction and it either flushed the TLB or the CPU reused it.
311	*/
312	#endif
313	#ifdef VBOX_WITH_NEW_PHYS_CODE
314	return PGMPhysInterpretedReadNoHandlers(pVM, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
315	#else
316	NOREF(pCtxCore);
317	# ifdef IN_RC
318	RTGCPHYS GCPhys;
319	rc = PGMPhysGCPtr2GCPhys(pVM, GCPtrSrc, &GCPhys);
320	AssertRCReturn(rc, rc);
321	PGMPhysRead(pVM, GCPhys, pvDst, cb);
322	return VINF_SUCCESS;
323	# else
324	return PGMPhysReadGCPtr(pVM, pvDst, GCPtrSrc, cb);
325	# endif
326	#endif
327	}
328
329
330	DECLINLINE(int) emRamWrite(PVM pVM, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, uint32_t cb)
331	{
332	#ifdef IN_RC
333	int rc = MMGCRamWrite(pVM, (void )(uintptr_t)GCPtrDst, (void )pvSrc, cb);
334	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
335	return rc;
336	/*
337	* The page pool cache may end up here in some cases because it
338	* flushed one of the shadow mappings used by the trapping
339	* instruction and it either flushed the TLB or the CPU reused it.
340	* We want to play safe here, verifying that we've got write
341	* access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
342	*/
343	#endif
344	#ifdef VBOX_WITH_NEW_PHYS_CODE
345	return PGMPhysInterpretedWriteNoHandlers(pVM, pCtxCore, GCPtrDst, pvSrc, cb, /fMayTrap/ false);
346	#else
347	NOREF(pCtxCore);
348	# ifdef IN_RC
349	uint64_t fFlags;
350	RTGCPHYS GCPhys;
351	rc = PGMGstGetPage(pVM, GCPtrDst, &fFlags, &GCPhys);
352	if (RT_FAILURE(rc))
353	return rc;
354	if ( !(fFlags & X86_PTE_RW)
355	&& (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
356	return VERR_ACCESS_DENIED;
357
358	PGMPhysWrite(pVM, GCPhys + ((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK), pvSrc, cb);
359	return VINF_SUCCESS;
360	# else
361	return PGMPhysWriteGCPtr(pVM, GCPtrDst, pvSrc, cb);
362	# endif
363	#endif
364	}
365
366
367	/** Convert sel:addr to a flat GC address. */
368	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr)
369	{
370	DIS_SELREG enmPrefixSeg = DISDetectSegReg(pCpu, pParam);
371	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
372	}
373
374
375	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
376	/**
377	* Get the mnemonic for the disassembled instruction.
378	*
379	* GC/R0 doesn't include the strings in the DIS tables because
380	* of limited space.
381	*/
382	static const char *emGetMnemonic(PDISCPUSTATE pCpu)
383	{
384	switch (pCpu->pCurInstr->opcode)
385	{
386	case OP_XCHG: return "Xchg";
387	case OP_DEC: return "Dec";
388	case OP_INC: return "Inc";
389	case OP_POP: return "Pop";
390	case OP_OR: return "Or";
391	case OP_AND: return "And";
392	case OP_MOV: return "Mov";
393	case OP_INVLPG: return "InvlPg";
394	case OP_CPUID: return "CpuId";
395	case OP_MOV_CR: return "MovCRx";
396	case OP_MOV_DR: return "MovDRx";
397	case OP_LLDT: return "LLdt";
398	case OP_LGDT: return "LGdt";
399	case OP_LIDT: return "LGdt";
400	case OP_CLTS: return "Clts";
401	case OP_MONITOR: return "Monitor";
402	case OP_MWAIT: return "MWait";
403	case OP_RDMSR: return "Rdmsr";
404	case OP_WRMSR: return "Wrmsr";
405	case OP_ADD: return "Add";
406	case OP_ADC: return "Adc";
407	case OP_SUB: return "Sub";
408	case OP_SBB: return "Sbb";
409	case OP_RDTSC: return "Rdtsc";
410	case OP_STI: return "Sti";
411	case OP_XADD: return "XAdd";
412	case OP_HLT: return "Hlt";
413	case OP_IRET: return "Iret";
414	case OP_MOVNTPS: return "MovNTPS";
415	case OP_STOSWD: return "StosWD";
416	case OP_WBINVD: return "WbInvd";
417	case OP_XOR: return "Xor";
418	case OP_BTR: return "Btr";
419	case OP_BTS: return "Bts";
420	case OP_BTC: return "Btc";
421	case OP_LMSW: return "Lmsw";
422	case OP_SMSW: return "Smsw";
423	case OP_CMPXCHG: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
424	case OP_CMPXCHG8B: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
425
426	default:
427	Log(("Unknown opcode %d\n", pCpu->pCurInstr->opcode));
428	return "???";
429	}
430	}
431	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
432
433
434	/**
435	* XCHG instruction emulation.
436	*/
437	static int emInterpretXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
438	{
439	OP_PARAMVAL param1, param2;
440
441	/* Source to make DISQueryParamVal read the register value - ugly hack */
442	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
443	if(RT_FAILURE(rc))
444	return VERR_EM_INTERPRETER;
445
446	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
447	if(RT_FAILURE(rc))
448	return VERR_EM_INTERPRETER;
449
450	#ifdef IN_RC
451	if (TRPMHasTrap(pVM))
452	{
453	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
454	{
455	#endif
456	RTGCPTR pParam1 = 0, pParam2 = 0;
457	uint64_t valpar1, valpar2;
458
459	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
460	switch(param1.type)
461	{
462	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
463	valpar1 = param1.val.val64;
464	break;
465
466	case PARMTYPE_ADDRESS:
467	pParam1 = (RTGCPTR)param1.val.val64;
468	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
469	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
470	rc = emRamRead(pVM, pRegFrame, &valpar1, pParam1, param1.size);
471	if (RT_FAILURE(rc))
472	{
473	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
474	return VERR_EM_INTERPRETER;
475	}
476	break;
477
478	default:
479	AssertFailed();
480	return VERR_EM_INTERPRETER;
481	}
482
483	switch(param2.type)
484	{
485	case PARMTYPE_ADDRESS:
486	pParam2 = (RTGCPTR)param2.val.val64;
487	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pParam2);
488	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
489	rc = emRamRead(pVM, pRegFrame, &valpar2, pParam2, param2.size);
490	if (RT_FAILURE(rc))
491	{
492	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
493	}
494	break;
495
496	case PARMTYPE_IMMEDIATE:
497	valpar2 = param2.val.val64;
498	break;
499
500	default:
501	AssertFailed();
502	return VERR_EM_INTERPRETER;
503	}
504
505	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
506	if (pParam1 == 0)
507	{
508	Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
509	switch(param1.size)
510	{
511	case 1: //special case for AH etc
512	rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t )valpar2); break;
513	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)valpar2); break;
514	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)valpar2); break;
515	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, valpar2); break;
516	default: AssertFailedReturn(VERR_EM_INTERPRETER);
517	}
518	if (RT_FAILURE(rc))
519	return VERR_EM_INTERPRETER;
520	}
521	else
522	{
523	rc = emRamWrite(pVM, pRegFrame, pParam1, &valpar2, param1.size);
524	if (RT_FAILURE(rc))
525	{
526	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
527	return VERR_EM_INTERPRETER;
528	}
529	}
530
531	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
532	if (pParam2 == 0)
533	{
534	Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
535	switch(param2.size)
536	{
537	case 1: //special case for AH etc
538	rc = DISWriteReg8(pRegFrame, pCpu->param2.base.reg_gen, (uint8_t )valpar1); break;
539	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param2.base.reg_gen, (uint16_t)valpar1); break;
540	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param2.base.reg_gen, (uint32_t)valpar1); break;
541	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param2.base.reg_gen, valpar1); break;
542	default: AssertFailedReturn(VERR_EM_INTERPRETER);
543	}
544	if (RT_FAILURE(rc))
545	return VERR_EM_INTERPRETER;
546	}
547	else
548	{
549	rc = emRamWrite(pVM, pRegFrame, pParam2, &valpar1, param2.size);
550	if (RT_FAILURE(rc))
551	{
552	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
553	return VERR_EM_INTERPRETER;
554	}
555	}
556
557	*pcbSize = param2.size;
558	return VINF_SUCCESS;
559	#ifdef IN_RC
560	}
561	}
562	#endif
563	return VERR_EM_INTERPRETER;
564	}
565
566
567	/**
568	* INC and DEC emulation.
569	*/
570	static int emInterpretIncDec(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
571	PFNEMULATEPARAM2 pfnEmulate)
572	{
573	OP_PARAMVAL param1;
574
575	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
576	if(RT_FAILURE(rc))
577	return VERR_EM_INTERPRETER;
578
579	#ifdef IN_RC
580	if (TRPMHasTrap(pVM))
581	{
582	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
583	{
584	#endif
585	RTGCPTR pParam1 = 0;
586	uint64_t valpar1;
587
588	if (param1.type == PARMTYPE_ADDRESS)
589	{
590	pParam1 = (RTGCPTR)param1.val.val64;
591	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
592	#ifdef IN_RC
593	/* Safety check (in theory it could cross a page boundary and fault there though) */
594	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
595	#endif
596	rc = emRamRead(pVM, pRegFrame, &valpar1, pParam1, param1.size);
597	if (RT_FAILURE(rc))
598	{
599	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
600	return VERR_EM_INTERPRETER;
601	}
602	}
603	else
604	{
605	AssertFailed();
606	return VERR_EM_INTERPRETER;
607	}
608
609	uint32_t eflags;
610
611	eflags = pfnEmulate(&valpar1, param1.size);
612
613	/* Write result back */
614	rc = emRamWrite(pVM, pRegFrame, pParam1, &valpar1, param1.size);
615	if (RT_FAILURE(rc))
616	{
617	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
618	return VERR_EM_INTERPRETER;
619	}
620
621	/* Update guest's eflags and finish. */
622	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
623	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
624
625	/* All done! */
626	*pcbSize = param1.size;
627	return VINF_SUCCESS;
628	#ifdef IN_RC
629	}
630	}
631	#endif
632	return VERR_EM_INTERPRETER;
633	}
634
635
636	/**
637	* POP Emulation.
638	*/
639	static int emInterpretPop(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
640	{
641	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
642	OP_PARAMVAL param1;
643	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
644	if(RT_FAILURE(rc))
645	return VERR_EM_INTERPRETER;
646
647	#ifdef IN_RC
648	if (TRPMHasTrap(pVM))
649	{
650	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
651	{
652	#endif
653	RTGCPTR pParam1 = 0;
654	uint32_t valpar1;
655	RTGCPTR pStackVal;
656
657	/* Read stack value first */
658	if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
659	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
660
661	/* Convert address; don't bother checking limits etc, as we only read here */
662	pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
663	if (pStackVal == 0)
664	return VERR_EM_INTERPRETER;
665
666	rc = emRamRead(pVM, pRegFrame, &valpar1, pStackVal, param1.size);
667	if (RT_FAILURE(rc))
668	{
669	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
670	return VERR_EM_INTERPRETER;
671	}
672
673	if (param1.type == PARMTYPE_ADDRESS)
674	{
675	pParam1 = (RTGCPTR)param1.val.val64;
676
677	/* pop [esp+xx] uses esp after the actual pop! */
678	AssertCompile(USE_REG_ESP == USE_REG_SP);
679	if ( (pCpu->param1.flags & USE_BASE)
680	&& (pCpu->param1.flags & (USE_REG_GEN16\|USE_REG_GEN32))
681	&& pCpu->param1.base.reg_gen == USE_REG_ESP
682	)
683	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
684
685	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
686	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
687	rc = emRamWrite(pVM, pRegFrame, pParam1, &valpar1, param1.size);
688	if (RT_FAILURE(rc))
689	{
690	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
691	return VERR_EM_INTERPRETER;
692	}
693
694	/* Update ESP as the last step */
695	pRegFrame->esp += param1.size;
696	}
697	else
698	{
699	#ifndef DEBUG_bird // annoying assertion.
700	AssertFailed();
701	#endif
702	return VERR_EM_INTERPRETER;
703	}
704
705	/* All done! */
706	*pcbSize = param1.size;
707	return VINF_SUCCESS;
708	#ifdef IN_RC
709	}
710	}
711	#endif
712	return VERR_EM_INTERPRETER;
713	}
714
715
716	/**
717	* XOR/OR/AND Emulation.
718	*/
719	static int emInterpretOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
720	PFNEMULATEPARAM3 pfnEmulate)
721	{
722	OP_PARAMVAL param1, param2;
723
724	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
725	if(RT_FAILURE(rc))
726	return VERR_EM_INTERPRETER;
727
728	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
729	if(RT_FAILURE(rc))
730	return VERR_EM_INTERPRETER;
731
732	#ifdef IN_RC
733	if (TRPMHasTrap(pVM))
734	{
735	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
736	{
737	#endif
738	RTGCPTR pParam1;
739	uint64_t valpar1, valpar2;
740
741	if (pCpu->param1.size != pCpu->param2.size)
742	{
743	if (pCpu->param1.size < pCpu->param2.size)
744	{
745	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
746	return VERR_EM_INTERPRETER;
747	}
748	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
749	pCpu->param2.size = pCpu->param1.size;
750	param2.size = param1.size;
751	}
752
753	/* The destination is always a virtual address */
754	if (param1.type == PARMTYPE_ADDRESS)
755	{
756	pParam1 = (RTGCPTR)param1.val.val64;
757	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
758	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
759	rc = emRamRead(pVM, pRegFrame, &valpar1, pParam1, param1.size);
760	if (RT_FAILURE(rc))
761	{
762	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
763	return VERR_EM_INTERPRETER;
764	}
765	}
766	else
767	{
768	AssertFailed();
769	return VERR_EM_INTERPRETER;
770	}
771
772	/* Register or immediate data */
773	switch(param2.type)
774	{
775	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
776	valpar2 = param2.val.val64;
777	break;
778
779	default:
780	AssertFailed();
781	return VERR_EM_INTERPRETER;
782	}
783
784	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pCpu), pParam1, valpar1, valpar2, param2.size, param1.size));
785
786	/* Data read, emulate instruction. */
787	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
788
789	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pCpu), valpar1));
790
791	/* Update guest's eflags and finish. */
792	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
793	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
794
795	/* And write it back */
796	rc = emRamWrite(pVM, pRegFrame, pParam1, &valpar1, param1.size);
797	if (RT_SUCCESS(rc))
798	{
799	/* All done! */
800	*pcbSize = param2.size;
801	return VINF_SUCCESS;
802	}
803	#ifdef IN_RC
804	}
805	}
806	#endif
807	return VERR_EM_INTERPRETER;
808	}
809
810
811	/**
812	* LOCK XOR/OR/AND Emulation.
813	*/
814	static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
815	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
816	{
817	void *pvParam1;
818	OP_PARAMVAL param1, param2;
819
820	#if HC_ARCH_BITS == 32
821	Assert(pCpu->param1.size <= 4);
822	#endif
823
824	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
825	if(RT_FAILURE(rc))
826	return VERR_EM_INTERPRETER;
827
828	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
829	if(RT_FAILURE(rc))
830	return VERR_EM_INTERPRETER;
831
832	if (pCpu->param1.size != pCpu->param2.size)
833	{
834	AssertMsgReturn(pCpu->param1.size >= pCpu->param2.size, /* should never happen! */
835	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size),
836	VERR_EM_INTERPRETER);
837
838	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
839	pCpu->param2.size = pCpu->param1.size;
840	param2.size = param1.size;
841	}
842
843	#ifdef IN_RC
844	/* Safety check (in theory it could cross a page boundary and fault there though) */
845	Assert( TRPMHasTrap(pVM)
846	&& (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW));
847	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
848	#endif
849
850	/* Register and immediate data == PARMTYPE_IMMEDIATE */
851	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
852	RTGCUINTREG ValPar2 = param2.val.val64;
853
854	/* The destination is always a virtual address */
855	AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
856
857	RTGCPTR GCPtrPar1 = param1.val.val64;
858	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
859	#ifdef IN_RC
860	pvParam1 = (void *)GCPtrPar1;
861	#else
862	PGMPAGEMAPLOCK Lock;
863	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
864	AssertRCReturn(rc, VERR_EM_INTERPRETER);
865	#endif
866
867	/* Try emulate it with a one-shot #PF handler in place. (RC) */
868	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
869
870	RTGCUINTREG32 eflags = 0;
871	#ifdef IN_RC
872	MMGCRamRegisterTrapHandler(pVM);
873	#endif
874	rc = pfnEmulate(pvParam1, ValPar2, pCpu->param2.size, &eflags);
875	#ifdef IN_RC
876	MMGCRamDeregisterTrapHandler(pVM);
877	#else
878	PGMPhysReleasePageMappingLock(pVM, &Lock);
879	#endif
880	if (RT_FAILURE(rc))
881	{
882	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
883	return VERR_EM_INTERPRETER;
884	}
885
886	/* Update guest's eflags and finish. */
887	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
888	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
889
890	*pcbSize = param2.size;
891	return VINF_SUCCESS;
892	}
893
894
895	/**
896	* ADD, ADC & SUB Emulation.
897	*/
898	static int emInterpretAddSub(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
899	PFNEMULATEPARAM3 pfnEmulate)
900	{
901	OP_PARAMVAL param1, param2;
902	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
903	if(RT_FAILURE(rc))
904	return VERR_EM_INTERPRETER;
905
906	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
907	if(RT_FAILURE(rc))
908	return VERR_EM_INTERPRETER;
909
910	#ifdef IN_RC
911	if (TRPMHasTrap(pVM))
912	{
913	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
914	{
915	#endif
916	RTGCPTR pParam1;
917	uint64_t valpar1, valpar2;
918
919	if (pCpu->param1.size != pCpu->param2.size)
920	{
921	if (pCpu->param1.size < pCpu->param2.size)
922	{
923	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
924	return VERR_EM_INTERPRETER;
925	}
926	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
927	pCpu->param2.size = pCpu->param1.size;
928	param2.size = param1.size;
929	}
930
931	/* The destination is always a virtual address */
932	if (param1.type == PARMTYPE_ADDRESS)
933	{
934	pParam1 = (RTGCPTR)param1.val.val64;
935	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
936	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
937	rc = emRamRead(pVM, pRegFrame, &valpar1, pParam1, param1.size);
938	if (RT_FAILURE(rc))
939	{
940	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
941	return VERR_EM_INTERPRETER;
942	}
943	}
944	else
945	{
946	#ifndef DEBUG_bird
947	AssertFailed();
948	#endif
949	return VERR_EM_INTERPRETER;
950	}
951
952	/* Register or immediate data */
953	switch(param2.type)
954	{
955	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
956	valpar2 = param2.val.val64;
957	break;
958
959	default:
960	AssertFailed();
961	return VERR_EM_INTERPRETER;
962	}
963
964	/* Data read, emulate instruction. */
965	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
966
967	/* Update guest's eflags and finish. */
968	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
969	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
970
971	/* And write it back */
972	rc = emRamWrite(pVM, pRegFrame, pParam1, &valpar1, param1.size);
973	if (RT_SUCCESS(rc))
974	{
975	/* All done! */
976	*pcbSize = param2.size;
977	return VINF_SUCCESS;
978	}
979	#ifdef IN_RC
980	}
981	}
982	#endif
983	return VERR_EM_INTERPRETER;
984	}
985
986
987	/**
988	* ADC Emulation.
989	*/
990	static int emInterpretAdc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
991	{
992	if (pRegFrame->eflags.Bits.u1CF)
993	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
994	else
995	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
996	}
997
998
999	/**
1000	* BTR/C/S Emulation.
1001	*/
1002	static int emInterpretBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
1003	PFNEMULATEPARAM2UINT32 pfnEmulate)
1004	{
1005	OP_PARAMVAL param1, param2;
1006	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1007	if(RT_FAILURE(rc))
1008	return VERR_EM_INTERPRETER;
1009
1010	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1011	if(RT_FAILURE(rc))
1012	return VERR_EM_INTERPRETER;
1013
1014	#ifdef IN_RC
1015	if (TRPMHasTrap(pVM))
1016	{
1017	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1018	{
1019	#endif
1020	RTGCPTR pParam1;
1021	uint64_t valpar1 = 0, valpar2;
1022	uint32_t eflags;
1023
1024	/* The destination is always a virtual address */
1025	if (param1.type != PARMTYPE_ADDRESS)
1026	return VERR_EM_INTERPRETER;
1027
1028	pParam1 = (RTGCPTR)param1.val.val64;
1029	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1030
1031	/* Register or immediate data */
1032	switch(param2.type)
1033	{
1034	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1035	valpar2 = param2.val.val64;
1036	break;
1037
1038	default:
1039	AssertFailed();
1040	return VERR_EM_INTERPRETER;
1041	}
1042
1043	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pCpu), pvFault, pParam1, valpar2));
1044	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1045	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
1046	rc = emRamRead(pVM, pRegFrame, &valpar1, pParam1, 1);
1047	if (RT_FAILURE(rc))
1048	{
1049	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1050	return VERR_EM_INTERPRETER;
1051	}
1052
1053	Log2(("emInterpretBtx: val=%x\n", valpar1));
1054	/* Data read, emulate bit test instruction. */
1055	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1056
1057	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1058
1059	/* Update guest's eflags and finish. */
1060	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1061	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1062
1063	/* And write it back */
1064	rc = emRamWrite(pVM, pRegFrame, pParam1, &valpar1, 1);
1065	if (RT_SUCCESS(rc))
1066	{
1067	/* All done! */
1068	*pcbSize = 1;
1069	return VINF_SUCCESS;
1070	}
1071	#ifdef IN_RC
1072	}
1073	}
1074	#endif
1075	return VERR_EM_INTERPRETER;
1076	}
1077
1078
1079	/**
1080	* LOCK BTR/C/S Emulation.
1081	*/
1082	static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1083	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1084	{
1085	void *pvParam1;
1086
1087	OP_PARAMVAL param1, param2;
1088	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1089	if(RT_FAILURE(rc))
1090	return VERR_EM_INTERPRETER;
1091
1092	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1093	if(RT_FAILURE(rc))
1094	return VERR_EM_INTERPRETER;
1095
1096	/* The destination is always a virtual address */
1097	if (param1.type != PARMTYPE_ADDRESS)
1098	return VERR_EM_INTERPRETER;
1099
1100	/* Register and immediate data == PARMTYPE_IMMEDIATE */
1101	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1102	uint64_t ValPar2 = param2.val.val64;
1103
1104	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1105	RTGCPTR GCPtrPar1 = param1.val.val64;
1106	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
1107	ValPar2 &= 7;
1108
1109	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1110	#ifdef IN_RC
1111	Assert(TRPMHasTrap(pVM));
1112	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
1113	#endif
1114
1115	#ifdef IN_RC
1116	pvParam1 = (void *)GCPtrPar1;
1117	#else
1118	PGMPAGEMAPLOCK Lock;
1119	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
1120	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1121	#endif
1122
1123	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));
1124
1125	/* Try emulate it with a one-shot #PF handler in place. (RC) */
1126	RTGCUINTREG32 eflags = 0;
1127	#ifdef IN_RC
1128	MMGCRamRegisterTrapHandler(pVM);
1129	#endif
1130	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
1131	#ifdef IN_RC
1132	MMGCRamDeregisterTrapHandler(pVM);
1133	#else
1134	PGMPhysReleasePageMappingLock(pVM, &Lock);
1135	#endif
1136	if (RT_FAILURE(rc))
1137	{
1138	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
1139	emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
1140	return VERR_EM_INTERPRETER;
1141	}
1142
1143	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1144
1145	/* Update guest's eflags and finish. */
1146	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1147	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1148
1149	*pcbSize = 1;
1150	return VINF_SUCCESS;
1151	}
1152
1153
1154	/**
1155	* MOV emulation.
1156	*/
1157	static int emInterpretMov(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1158	{
1159	OP_PARAMVAL param1, param2;
1160	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1161	if(RT_FAILURE(rc))
1162	return VERR_EM_INTERPRETER;
1163
1164	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1165	if(RT_FAILURE(rc))
1166	return VERR_EM_INTERPRETER;
1167
1168	#ifdef IN_RC
1169	if (TRPMHasTrap(pVM))
1170	{
1171	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1172	{
1173	#else
1174	/** @todo Make this the default and don't rely on TRPM information. */
1175	if (param1.type == PARMTYPE_ADDRESS)
1176	{
1177	#endif
1178	RTGCPTR pDest;
1179	uint64_t val64;
1180
1181	switch(param1.type)
1182	{
1183	case PARMTYPE_IMMEDIATE:
1184	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1185	return VERR_EM_INTERPRETER;
1186	/* fallthru */
1187
1188	case PARMTYPE_ADDRESS:
1189	pDest = (RTGCPTR)param1.val.val64;
1190	pDest = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pDest);
1191	break;
1192
1193	default:
1194	AssertFailed();
1195	return VERR_EM_INTERPRETER;
1196	}
1197
1198	switch(param2.type)
1199	{
1200	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1201	val64 = param2.val.val64;
1202	break;
1203
1204	default:
1205	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
1206	return VERR_EM_INTERPRETER;
1207	}
1208	#ifdef LOG_ENABLED
1209	if (pCpu->mode == CPUMODE_64BIT)
1210	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
1211	else
1212	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
1213	#endif
1214
1215	Assert(param2.size <= 8 && param2.size > 0);
1216	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
1217	rc = emRamWrite(pVM, pRegFrame, pDest, &val64, param2.size);
1218	if (RT_FAILURE(rc))
1219	return VERR_EM_INTERPRETER;
1220
1221	*pcbSize = param2.size;
1222	}
1223	else
1224	{ /* read fault */
1225	RTGCPTR pSrc;
1226	uint64_t val64;
1227
1228	/* Source */
1229	switch(param2.type)
1230	{
1231	case PARMTYPE_IMMEDIATE:
1232	if(!(param2.flags & (PARAM_VAL32\|PARAM_VAL64)))
1233	return VERR_EM_INTERPRETER;
1234	/* fallthru */
1235
1236	case PARMTYPE_ADDRESS:
1237	pSrc = (RTGCPTR)param2.val.val64;
1238	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pSrc);
1239	break;
1240
1241	default:
1242	return VERR_EM_INTERPRETER;
1243	}
1244
1245	Assert(param1.size <= 8 && param1.size > 0);
1246	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
1247	rc = emRamRead(pVM, pRegFrame, &val64, pSrc, param1.size);
1248	if (RT_FAILURE(rc))
1249	return VERR_EM_INTERPRETER;
1250
1251	/* Destination */
1252	switch(param1.type)
1253	{
1254	case PARMTYPE_REGISTER:
1255	switch(param1.size)
1256	{
1257	case 1: rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t) val64); break;
1258	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)val64); break;
1259	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)val64); break;
1260	case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, val64); break;
1261	default:
1262	return VERR_EM_INTERPRETER;
1263	}
1264	if (RT_FAILURE(rc))
1265	return rc;
1266	break;
1267
1268	default:
1269	return VERR_EM_INTERPRETER;
1270	}
1271	#ifdef LOG_ENABLED
1272	if (pCpu->mode == CPUMODE_64BIT)
1273	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1274	else
1275	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1276	#endif
1277	}
1278	return VINF_SUCCESS;
1279	#ifdef IN_RC
1280	}
1281	#endif
1282	return VERR_EM_INTERPRETER;
1283	}
1284
1285
1286	#ifndef IN_RC
1287	/**
1288	* [REP] STOSWD emulation
1289	*/
1290	static int emInterpretStosWD(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1291	{
1292	int rc;
1293	RTGCPTR GCDest, GCOffset;
1294	uint32_t cbSize;
1295	uint64_t cTransfers;
1296	int offIncrement;
1297
1298	/* Don't support any but these three prefix bytes. */
1299	if ((pCpu->prefix & ~(PREFIX_ADDRSIZE\|PREFIX_OPSIZE\|PREFIX_REP\|PREFIX_REX)))
1300	return VERR_EM_INTERPRETER;
1301
1302	switch (pCpu->addrmode)
1303	{
1304	case CPUMODE_16BIT:
1305	GCOffset = pRegFrame->di;
1306	cTransfers = pRegFrame->cx;
1307	break;
1308	case CPUMODE_32BIT:
1309	GCOffset = pRegFrame->edi;
1310	cTransfers = pRegFrame->ecx;
1311	break;
1312	case CPUMODE_64BIT:
1313	GCOffset = pRegFrame->rdi;
1314	cTransfers = pRegFrame->rcx;
1315	break;
1316	default:
1317	AssertFailed();
1318	return VERR_EM_INTERPRETER;
1319	}
1320
1321	GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
1322	switch (pCpu->opmode)
1323	{
1324	case CPUMODE_16BIT:
1325	cbSize = 2;
1326	break;
1327	case CPUMODE_32BIT:
1328	cbSize = 4;
1329	break;
1330	case CPUMODE_64BIT:
1331	cbSize = 8;
1332	break;
1333	default:
1334	AssertFailed();
1335	return VERR_EM_INTERPRETER;
1336	}
1337
1338	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
1339
1340	if (!(pCpu->prefix & PREFIX_REP))
1341	{
1342	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
1343
1344	#ifdef VBOX_WITH_NEW_PHYS_CODE
1345	rc = emRamWrite(pVM, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
1346	#else
1347	rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
1348	#endif
1349	if (RT_FAILURE(rc))
1350	return VERR_EM_INTERPRETER;
1351	Assert(rc == VINF_SUCCESS);
1352
1353	/* Update (e/r)di. */
1354	switch (pCpu->addrmode)
1355	{
1356	case CPUMODE_16BIT:
1357	pRegFrame->di += offIncrement;
1358	break;
1359	case CPUMODE_32BIT:
1360	pRegFrame->edi += offIncrement;
1361	break;
1362	case CPUMODE_64BIT:
1363	pRegFrame->rdi += offIncrement;
1364	break;
1365	default:
1366	AssertFailed();
1367	return VERR_EM_INTERPRETER;
1368	}
1369
1370	}
1371	else
1372	{
1373	if (!cTransfers)
1374	return VINF_SUCCESS;
1375
1376	/*
1377	* Do not try emulate cross page stuff here because we don't know what might
1378	* be waiting for us on the subsequent pages. The caller has only asked us to
1379	* ignore access handlers fro the current page.
1380	* This also fends off big stores which would quickly kill PGMR0DynMap.
1381	*/
1382	if ( cbSize > PAGE_SIZE
1383	\|\| cTransfers > PAGE_SIZE
1384	\|\| (GCDest >> PAGE_SHIFT) != ((GCDest + offIncrement * cTransfers) >> PAGE_SHIFT))
1385	{
1386	Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
1387	GCDest, cbSize, offIncrement, cTransfers));
1388	return VERR_EM_INTERPRETER;
1389	}
1390
1391	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
1392	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1393	rc = PGMVerifyAccess(pVM, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
1394	cTransfers * cbSize,
1395	X86_PTE_RW \| (CPUMGetGuestCPL(pVM, pRegFrame) == 3 ? X86_PTE_US : 0));
1396	if (rc != VINF_SUCCESS)
1397	{
1398	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
1399	return VERR_EM_INTERPRETER;
1400	}
1401
1402	/* REP case */
1403	while (cTransfers)
1404	{
1405	#ifdef VBOX_WITH_NEW_PHYS_CODE
1406	rc = emRamWrite(pVM, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
1407	#else
1408	rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
1409	#endif
1410	if (RT_FAILURE(rc))
1411	{
1412	rc = VERR_EM_INTERPRETER;
1413	break;
1414	}
1415
1416	Assert(rc == VINF_SUCCESS);
1417	GCOffset += offIncrement;
1418	GCDest += offIncrement;
1419	cTransfers--;
1420	}
1421
1422	/* Update the registers. */
1423	switch (pCpu->addrmode)
1424	{
1425	case CPUMODE_16BIT:
1426	pRegFrame->di = GCOffset;
1427	pRegFrame->cx = cTransfers;
1428	break;
1429	case CPUMODE_32BIT:
1430	pRegFrame->edi = GCOffset;
1431	pRegFrame->ecx = cTransfers;
1432	break;
1433	case CPUMODE_64BIT:
1434	pRegFrame->rdi = GCOffset;
1435	pRegFrame->rcx = cTransfers;
1436	break;
1437	default:
1438	AssertFailed();
1439	return VERR_EM_INTERPRETER;
1440	}
1441	}
1442
1443	*pcbSize = cbSize;
1444	return rc;
1445	}
1446	#endif /* !IN_RC */
1447
1448	#ifndef IN_RC
1449
1450	/**
1451	* [LOCK] CMPXCHG emulation.
1452	*/
1453	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1454	{
1455	OP_PARAMVAL param1, param2;
1456
1457	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
1458	Assert(pCpu->param1.size <= 4);
1459	#endif
1460
1461	/* Source to make DISQueryParamVal read the register value - ugly hack */
1462	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1463	if(RT_FAILURE(rc))
1464	return VERR_EM_INTERPRETER;
1465
1466	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1467	if(RT_FAILURE(rc))
1468	return VERR_EM_INTERPRETER;
1469
1470	uint64_t valpar;
1471	switch(param2.type)
1472	{
1473	case PARMTYPE_IMMEDIATE: /* register actually */
1474	valpar = param2.val.val64;
1475	break;
1476
1477	default:
1478	return VERR_EM_INTERPRETER;
1479	}
1480
1481	PGMPAGEMAPLOCK Lock;
1482	RTGCPTR GCPtrPar1;
1483	void *pvParam1;
1484	uint64_t eflags;
1485
1486	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1487	switch(param1.type)
1488	{
1489	case PARMTYPE_ADDRESS:
1490	GCPtrPar1 = param1.val.val64;
1491	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1492
1493	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
1494	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1495	break;
1496
1497	default:
1498	return VERR_EM_INTERPRETER;
1499	}
1500
1501	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar));
1502
1503	if (pCpu->prefix & PREFIX_LOCK)
1504	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1505	else
1506	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
1507
1508	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
1509
1510	/* Update guest's eflags and finish. */
1511	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1512	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1513
1514	*pcbSize = param2.size;
1515	PGMPhysReleasePageMappingLock(pVM, &Lock);
1516	return VINF_SUCCESS;
1517	}
1518
1519
1520	/**
1521	* [LOCK] CMPXCHG8B emulation.
1522	*/
1523	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1524	{
1525	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1526	OP_PARAMVAL param1;
1527
1528	/* Source to make DISQueryParamVal read the register value - ugly hack */
1529	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1530	if(RT_FAILURE(rc))
1531	return VERR_EM_INTERPRETER;
1532
1533	RTGCPTR GCPtrPar1;
1534	void *pvParam1;
1535	uint64_t eflags;
1536	PGMPAGEMAPLOCK Lock;
1537
1538	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1539	switch(param1.type)
1540	{
1541	case PARMTYPE_ADDRESS:
1542	GCPtrPar1 = param1.val.val64;
1543	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1544
1545	rc = PGMPhysGCPtr2CCPtr(pVM, GCPtrPar1, &pvParam1, &Lock);
1546	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1547	break;
1548
1549	default:
1550	return VERR_EM_INTERPRETER;
1551	}
1552
1553	LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax));
1554
1555	if (pCpu->prefix & PREFIX_LOCK)
1556	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1557	else
1558	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1559
1560	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1561
1562	/* Update guest's eflags and finish; note that only ZF is affected. */
1563	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1564	\| (eflags & (X86_EFL_ZF));
1565
1566	*pcbSize = 8;
1567	PGMPhysReleasePageMappingLock(pVM, &Lock);
1568	return VINF_SUCCESS;
1569	}
1570
1571	#else /* IN_RC */
1572
1573	/**
1574	* [LOCK] CMPXCHG emulation.
1575	*/
1576	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1577	{
1578	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1579	OP_PARAMVAL param1, param2;
1580
1581	/* Source to make DISQueryParamVal read the register value - ugly hack */
1582	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1583	if(RT_FAILURE(rc))
1584	return VERR_EM_INTERPRETER;
1585
1586	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1587	if(RT_FAILURE(rc))
1588	return VERR_EM_INTERPRETER;
1589
1590	if (TRPMHasTrap(pVM))
1591	{
1592	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1593	{
1594	RTRCPTR pParam1;
1595	uint32_t valpar, eflags;
1596
1597	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1598	switch(param1.type)
1599	{
1600	case PARMTYPE_ADDRESS:
1601	pParam1 = (RTRCPTR)param1.val.val64;
1602	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1603	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1604	break;
1605
1606	default:
1607	return VERR_EM_INTERPRETER;
1608	}
1609
1610	switch(param2.type)
1611	{
1612	case PARMTYPE_IMMEDIATE: /* register actually */
1613	valpar = param2.val.val32;
1614	break;
1615
1616	default:
1617	return VERR_EM_INTERPRETER;
1618	}
1619
1620	LogFlow(("%s %RRv eax=%08x %08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
1621
1622	MMGCRamRegisterTrapHandler(pVM);
1623	if (pCpu->prefix & PREFIX_LOCK)
1624	rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1625	else
1626	rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1627	MMGCRamDeregisterTrapHandler(pVM);
1628
1629	if (RT_FAILURE(rc))
1630	{
1631	Log(("%s %RGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
1632	return VERR_EM_INTERPRETER;
1633	}
1634
1635	LogFlow(("%s %RRv eax=%08x %08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
1636
1637	/* Update guest's eflags and finish. */
1638	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1639	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1640
1641	*pcbSize = param2.size;
1642	return VINF_SUCCESS;
1643	}
1644	}
1645	return VERR_EM_INTERPRETER;
1646	}
1647
1648
1649	/**
1650	* [LOCK] CMPXCHG8B emulation.
1651	*/
1652	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1653	{
1654	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1655	OP_PARAMVAL param1;
1656
1657	/* Source to make DISQueryParamVal read the register value - ugly hack */
1658	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1659	if(RT_FAILURE(rc))
1660	return VERR_EM_INTERPRETER;
1661
1662	if (TRPMHasTrap(pVM))
1663	{
1664	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1665	{
1666	RTRCPTR pParam1;
1667	uint32_t eflags;
1668
1669	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1670	switch(param1.type)
1671	{
1672	case PARMTYPE_ADDRESS:
1673	pParam1 = (RTRCPTR)param1.val.val64;
1674	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1675	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1676	break;
1677
1678	default:
1679	return VERR_EM_INTERPRETER;
1680	}
1681
1682	LogFlow(("%s %RRv=%08x eax=%08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
1683
1684	MMGCRamRegisterTrapHandler(pVM);
1685	if (pCpu->prefix & PREFIX_LOCK)
1686	rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1687	else
1688	rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1689	MMGCRamDeregisterTrapHandler(pVM);
1690
1691	if (RT_FAILURE(rc))
1692	{
1693	Log(("%s %RGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
1694	return VERR_EM_INTERPRETER;
1695	}
1696
1697	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1698
1699	/* Update guest's eflags and finish; note that only ZF is affected. */
1700	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1701	\| (eflags & (X86_EFL_ZF));
1702
1703	*pcbSize = 8;
1704	return VINF_SUCCESS;
1705	}
1706	}
1707	return VERR_EM_INTERPRETER;
1708	}
1709
1710	#endif /* IN_RC */
1711
1712	#ifdef IN_RC
1713	/**
1714	* [LOCK] XADD emulation.
1715	*/
1716	static int emInterpretXAdd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1717	{
1718	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1719	OP_PARAMVAL param1;
1720	uint32_t *pParamReg2;
1721	size_t cbSizeParamReg2;
1722
1723	/* Source to make DISQueryParamVal read the register value - ugly hack */
1724	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1725	if(RT_FAILURE(rc))
1726	return VERR_EM_INTERPRETER;
1727
1728	rc = DISQueryParamRegPtr(pRegFrame, pCpu, &pCpu->param2, (void **)&pParamReg2, &cbSizeParamReg2);
1729	Assert(cbSizeParamReg2 <= 4);
1730	if(RT_FAILURE(rc))
1731	return VERR_EM_INTERPRETER;
1732
1733	if (TRPMHasTrap(pVM))
1734	{
1735	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1736	{
1737	RTRCPTR pParam1;
1738	uint32_t eflags;
1739
1740	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1741	switch(param1.type)
1742	{
1743	case PARMTYPE_ADDRESS:
1744	pParam1 = (RTRCPTR)param1.val.val64;
1745	pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
1746	EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
1747	break;
1748
1749	default:
1750	return VERR_EM_INTERPRETER;
1751	}
1752
1753	LogFlow(("XAdd %RRv=%08x reg=%08x\n", pParam1, *pParamReg2));
1754
1755	MMGCRamRegisterTrapHandler(pVM);
1756	if (pCpu->prefix & PREFIX_LOCK)
1757	rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1758	else
1759	rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1760	MMGCRamDeregisterTrapHandler(pVM);
1761
1762	if (RT_FAILURE(rc))
1763	{
1764	Log(("XAdd %RGv reg=%08x -> emulation failed due to page fault!\n", pParam1, *pParamReg2));
1765	return VERR_EM_INTERPRETER;
1766	}
1767
1768	LogFlow(("XAdd %RGv reg=%08x ZF=%d\n", pParam1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
1769
1770	/* Update guest's eflags and finish. */
1771	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1772	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1773
1774	*pcbSize = cbSizeParamReg2;
1775	return VINF_SUCCESS;
1776	}
1777	}
1778	return VERR_EM_INTERPRETER;
1779	}
1780	#endif /* IN_RC */
1781
1782
1783	#ifdef IN_RC
1784	/**
1785	* Interpret IRET (currently only to V86 code)
1786	*
1787	* @returns VBox status code.
1788	* @param pVM The VM handle.
1789	* @param pRegFrame The register frame.
1790	*
1791	*/
1792	VMMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame)
1793	{
1794	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1795	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1796	int rc;
1797
1798	Assert(!CPUMIsGuestIn64BitCode(pVM, pRegFrame));
1799
1800	rc = emRamRead(pVM, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1801	rc \|= emRamRead(pVM, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1802	rc \|= emRamRead(pVM, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1803	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1804	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1805
1806	rc \|= emRamRead(pVM, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1807	rc \|= emRamRead(pVM, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1808	rc \|= emRamRead(pVM, pRegFrame, &es, (RTGCPTR)(pIretStack + 20), 4);
1809	rc \|= emRamRead(pVM, pRegFrame, &ds, (RTGCPTR)(pIretStack + 24), 4);
1810	rc \|= emRamRead(pVM, pRegFrame, &fs, (RTGCPTR)(pIretStack + 28), 4);
1811	rc \|= emRamRead(pVM, pRegFrame, &gs, (RTGCPTR)(pIretStack + 32), 4);
1812	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1813
1814	pRegFrame->eip = eip & 0xffff;
1815	pRegFrame->cs = cs;
1816
1817	/* Mask away all reserved bits */
1818	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1819	eflags &= uMask;
1820
1821	#ifndef IN_RING0
1822	CPUMRawSetEFlags(pVM, pRegFrame, eflags);
1823	#endif
1824	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1825
1826	pRegFrame->esp = esp;
1827	pRegFrame->ss = ss;
1828	pRegFrame->ds = ds;
1829	pRegFrame->es = es;
1830	pRegFrame->fs = fs;
1831	pRegFrame->gs = gs;
1832
1833	return VINF_SUCCESS;
1834	}
1835	#endif /* IN_RC */
1836
1837
1838	/**
1839	* IRET Emulation.
1840	*/
1841	static int emInterpretIret(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1842	{
1843	/* only allow direct calls to EMInterpretIret for now */
1844	return VERR_EM_INTERPRETER;
1845	}
1846
1847	/**
1848	* WBINVD Emulation.
1849	*/
1850	static int emInterpretWbInvd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1851	{
1852	/* Nothing to do. */
1853	return VINF_SUCCESS;
1854	}
1855
1856
1857	/**
1858	* Interpret INVLPG
1859	*
1860	* @returns VBox status code.
1861	* @param pVM The VM handle.
1862	* @param pRegFrame The register frame.
1863	* @param pAddrGC Operand address
1864	*
1865	*/
1866	VMMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1867	{
1868	int rc;
1869
1870	/** @todo is addr always a flat linear address or ds based
1871	* (in absence of segment override prefixes)????
1872	*/
1873	#ifdef IN_RC
1874	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1875	#endif
1876	rc = PGMInvalidatePage(pVM, pAddrGC);
1877	if ( rc == VINF_SUCCESS
1878	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1879	return VINF_SUCCESS;
1880	AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
1881	\|\| rc == VINF_EM_RAW_EMULATE_INSTR,
1882	("%Rrc addr=%RGv\n", rc, pAddrGC),
1883	VERR_EM_INTERPRETER);
1884	return rc;
1885	}
1886
1887
1888	/**
1889	* INVLPG Emulation.
1890	*/
1891	static int emInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1892	{
1893	OP_PARAMVAL param1;
1894	RTGCPTR addr;
1895
1896	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1897	if(RT_FAILURE(rc))
1898	return VERR_EM_INTERPRETER;
1899
1900	switch(param1.type)
1901	{
1902	case PARMTYPE_IMMEDIATE:
1903	case PARMTYPE_ADDRESS:
1904	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1905	return VERR_EM_INTERPRETER;
1906	addr = (RTGCPTR)param1.val.val64;
1907	break;
1908
1909	default:
1910	return VERR_EM_INTERPRETER;
1911	}
1912
1913	/** @todo is addr always a flat linear address or ds based
1914	* (in absence of segment override prefixes)????
1915	*/
1916	#ifdef IN_RC
1917	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
1918	#endif
1919	rc = PGMInvalidatePage(pVM, addr);
1920	if ( rc == VINF_SUCCESS
1921	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1922	return VINF_SUCCESS;
1923	AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
1924	\|\| rc == VINF_EM_RAW_EMULATE_INSTR,
1925	("%Rrc addr=%RGv\n", rc, addr),
1926	VERR_EM_INTERPRETER);
1927	return rc;
1928	}
1929
1930
1931	/**
1932	* Interpret CPUID given the parameters in the CPU context
1933	*
1934	* @returns VBox status code.
1935	* @param pVM The VM handle.
1936	* @param pRegFrame The register frame.
1937	*
1938	*/
1939	VMMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame)
1940	{
1941	uint32_t iLeaf = pRegFrame->eax;
1942
1943	/* cpuid clears the high dwords of the affected 64 bits registers. */
1944	pRegFrame->rax = 0;
1945	pRegFrame->rbx = 0;
1946	pRegFrame->rcx = 0;
1947	pRegFrame->rdx = 0;
1948
1949	/* Note: operates the same in 64 and non-64 bits mode. */
1950	CPUMGetGuestCpuId(pVM, iLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1951	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1952	return VINF_SUCCESS;
1953	}
1954
1955
1956	/**
1957	* CPUID Emulation.
1958	*/
1959	static int emInterpretCpuId(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1960	{
1961	int rc = EMInterpretCpuId(pVM, pRegFrame);
1962	return rc;
1963	}
1964
1965
1966	/**
1967	* Interpret CRx read
1968	*
1969	* @returns VBox status code.
1970	* @param pVM The VM handle.
1971	* @param pRegFrame The register frame.
1972	* @param DestRegGen General purpose register index (USE_REG_E**))
1973	* @param SrcRegCRx CRx register index (USE_REG_CR*)
1974	*
1975	*/
1976	VMMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1977	{
1978	int rc;
1979	uint64_t val64;
1980
1981	if (SrcRegCrx == USE_REG_CR8)
1982	{
1983	val64 = 0;
1984	rc = PDMApicGetTPR(pVM, (uint8_t *)&val64, NULL);
1985	AssertMsgRCReturn(rc, ("PDMApicGetTPR failed\n"), VERR_EM_INTERPRETER);
1986	}
1987	else
1988	{
1989	rc = CPUMGetGuestCRx(pVM, SrcRegCrx, &val64);
1990	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1991	}
1992
1993	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
1994	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1995	else
1996	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1997
1998	if(RT_SUCCESS(rc))
1999	{
2000	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
2001	return VINF_SUCCESS;
2002	}
2003	return VERR_EM_INTERPRETER;
2004	}
2005
2006
2007
2008	/**
2009	* Interpret CLTS
2010	*
2011	* @returns VBox status code.
2012	* @param pVM The VM handle.
2013	*
2014	*/
2015	VMMDECL(int) EMInterpretCLTS(PVM pVM)
2016	{
2017	uint64_t cr0 = CPUMGetGuestCR0(pVM);
2018	if (!(cr0 & X86_CR0_TS))
2019	return VINF_SUCCESS;
2020	return CPUMSetGuestCR0(pVM, cr0 & ~X86_CR0_TS);
2021	}
2022
2023	/**
2024	* CLTS Emulation.
2025	*/
2026	static int emInterpretClts(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2027	{
2028	return EMInterpretCLTS(pVM);
2029	}
2030
2031
2032	/**
2033	* Update CRx
2034	*
2035	* @returns VBox status code.
2036	* @param pVM The VM handle.
2037	* @param pRegFrame The register frame.
2038	* @param DestRegCRx CRx register index (USE_REG_CR*)
2039	* @param val New CRx value
2040	*
2041	*/
2042	static int emUpdateCRx(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
2043	{
2044	uint64_t oldval;
2045	uint64_t msrEFER;
2046	int rc, rc2;
2047
2048	/** @todo Clean up this mess. */
2049	LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
2050	switch (DestRegCrx)
2051	{
2052	case USE_REG_CR0:
2053	oldval = CPUMGetGuestCR0(pVM);
2054	#ifdef IN_RC
2055	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
2056	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
2057	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
2058	return VERR_EM_INTERPRETER;
2059	#endif
2060	rc = VINF_SUCCESS;
2061	CPUMSetGuestCR0(pVM, val);
2062	val = CPUMGetGuestCR0(pVM);
2063	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
2064	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
2065	{
2066	/* global flush */
2067	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2068	AssertRCReturn(rc, rc);
2069	}
2070
2071	/* Deal with long mode enabling/disabling. */
2072	msrEFER = CPUMGetGuestEFER(pVM);
2073	if (msrEFER & MSR_K6_EFER_LME)
2074	{
2075	if ( !(oldval & X86_CR0_PG)
2076	&& (val & X86_CR0_PG))
2077	{
2078	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2079	if (pRegFrame->csHid.Attr.n.u1Long)
2080	{
2081	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
2082	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2083	}
2084
2085	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2086	if (!(CPUMGetGuestCR4(pVM) & X86_CR4_PAE))
2087	{
2088	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
2089	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2090	}
2091	msrEFER \|= MSR_K6_EFER_LMA;
2092	}
2093	else
2094	if ( (oldval & X86_CR0_PG)
2095	&& !(val & X86_CR0_PG))
2096	{
2097	msrEFER &= ~MSR_K6_EFER_LMA;
2098	/* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
2099	}
2100	CPUMSetGuestEFER(pVM, msrEFER);
2101	}
2102	rc2 = PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2103	return rc2 == VINF_SUCCESS ? rc : rc2;
2104
2105	case USE_REG_CR2:
2106	rc = CPUMSetGuestCR2(pVM, val); AssertRC(rc);
2107	return VINF_SUCCESS;
2108
2109	case USE_REG_CR3:
2110	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
2111	rc = CPUMSetGuestCR3(pVM, val); AssertRC(rc);
2112	if (CPUMGetGuestCR0(pVM) & X86_CR0_PG)
2113	{
2114	/* flush */
2115	rc = PGMFlushTLB(pVM, val, !(CPUMGetGuestCR4(pVM) & X86_CR4_PGE));
2116	AssertRCReturn(rc, rc);
2117	}
2118	return rc;
2119
2120	case USE_REG_CR4:
2121	oldval = CPUMGetGuestCR4(pVM);
2122	rc = CPUMSetGuestCR4(pVM, val); AssertRC(rc);
2123	val = CPUMGetGuestCR4(pVM);
2124
2125	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2126	msrEFER = CPUMGetGuestEFER(pVM);
2127	if ( (msrEFER & MSR_K6_EFER_LMA)
2128	&& (oldval & X86_CR4_PAE)
2129	&& !(val & X86_CR4_PAE))
2130	{
2131	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
2132	}
2133
2134	rc = VINF_SUCCESS;
2135	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
2136	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
2137	{
2138	/* global flush */
2139	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
2140	AssertRCReturn(rc, rc);
2141	}
2142
2143	/* Feeling extremely lazy. */
2144	# ifdef IN_RC
2145	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
2146	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
2147	{
2148	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
2149	VM_FF_SET(pVM, VM_FF_TO_R3);
2150	}
2151	# endif
2152	if ((val ^ oldval) & X86_CR4_VME)
2153	VM_FF_SET(pVM, VM_FF_SELM_SYNC_TSS);
2154
2155	rc2 = PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
2156	return rc2 == VINF_SUCCESS ? rc : rc2;
2157
2158	case USE_REG_CR8:
2159	return PDMApicSetTPR(pVM, val);
2160
2161	default:
2162	AssertFailed();
2163	case USE_REG_CR1: /* illegal op */
2164	break;
2165	}
2166	return VERR_EM_INTERPRETER;
2167	}
2168
2169	/**
2170	* Interpret CRx write
2171	*
2172	* @returns VBox status code.
2173	* @param pVM The VM handle.
2174	* @param pRegFrame The register frame.
2175	* @param DestRegCRx CRx register index (USE_REG_CR*)
2176	* @param SrcRegGen General purpose register index (USE_REG_E**))
2177	*
2178	*/
2179	VMMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
2180	{
2181	uint64_t val;
2182	int rc;
2183
2184	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2185	{
2186	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2187	}
2188	else
2189	{
2190	uint32_t val32;
2191	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2192	val = val32;
2193	}
2194
2195	if (RT_SUCCESS(rc))
2196	return emUpdateCRx(pVM, pRegFrame, DestRegCrx, val);
2197
2198	return VERR_EM_INTERPRETER;
2199	}
2200
2201	/**
2202	* Interpret LMSW
2203	*
2204	* @returns VBox status code.
2205	* @param pVM The VM handle.
2206	* @param pRegFrame The register frame.
2207	* @param u16Data LMSW source data.
2208	*
2209	*/
2210	VMMDECL(int) EMInterpretLMSW(PVM pVM, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
2211	{
2212	uint64_t OldCr0 = CPUMGetGuestCR0(pVM);
2213
2214	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
2215	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
2216	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
2217
2218	return emUpdateCRx(pVM, pRegFrame, USE_REG_CR0, NewCr0);
2219	}
2220
2221	/**
2222	* LMSW Emulation.
2223	*/
2224	static int emInterpretLmsw(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2225	{
2226	OP_PARAMVAL param1;
2227	uint32_t val;
2228
2229	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2230	if(RT_FAILURE(rc))
2231	return VERR_EM_INTERPRETER;
2232
2233	switch(param1.type)
2234	{
2235	case PARMTYPE_IMMEDIATE:
2236	case PARMTYPE_ADDRESS:
2237	if(!(param1.flags & PARAM_VAL16))
2238	return VERR_EM_INTERPRETER;
2239	val = param1.val.val32;
2240	break;
2241
2242	default:
2243	return VERR_EM_INTERPRETER;
2244	}
2245
2246	LogFlow(("emInterpretLmsw %x\n", val));
2247	return EMInterpretLMSW(pVM, pRegFrame, val);
2248	}
2249
2250	#ifdef EM_EMULATE_SMSW
2251	/**
2252	* SMSW Emulation.
2253	*/
2254	static int emInterpretSmsw(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2255	{
2256	OP_PARAMVAL param1;
2257	uint64_t cr0 = CPUMGetGuestCR0(pVM);
2258
2259	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2260	if(RT_FAILURE(rc))
2261	return VERR_EM_INTERPRETER;
2262
2263	switch(param1.type)
2264	{
2265	case PARMTYPE_IMMEDIATE:
2266	if(param1.size != sizeof(uint16_t))
2267	return VERR_EM_INTERPRETER;
2268	LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pCpu->param1.base.reg_gen, cr0));
2269	rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, cr0);
2270	break;
2271
2272	case PARMTYPE_ADDRESS:
2273	{
2274	RTGCPTR pParam1;
2275
2276	/* Actually forced to 16 bits regardless of the operand size. */
2277	if(param1.size != sizeof(uint16_t))
2278	return VERR_EM_INTERPRETER;
2279
2280	pParam1 = (RTGCPTR)param1.val.val64;
2281	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
2282	LogFlow(("emInterpretSmsw %VGv <- cr0 (%x)\n", pParam1, cr0));
2283
2284	rc = emRamWrite(pVM, pRegFrame, pParam1, &cr0, sizeof(uint16_t));
2285	if (RT_FAILURE(rc))
2286	{
2287	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2288	return VERR_EM_INTERPRETER;
2289	}
2290	break;
2291	}
2292
2293	default:
2294	return VERR_EM_INTERPRETER;
2295	}
2296
2297	LogFlow(("emInterpretSmsw %x\n", cr0));
2298	return rc;
2299	}
2300	#endif
2301
2302	/**
2303	* MOV CRx
2304	*/
2305	static int emInterpretMovCRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2306	{
2307	if ((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_CR)
2308	return EMInterpretCRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_ctrl);
2309
2310	if (pCpu->param1.flags == USE_REG_CR && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2311	return EMInterpretCRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_ctrl, pCpu->param2.base.reg_gen);
2312
2313	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
2314	return VERR_EM_INTERPRETER;
2315	}
2316
2317
2318	/**
2319	* Interpret DRx write
2320	*
2321	* @returns VBox status code.
2322	* @param pVM The VM handle.
2323	* @param pRegFrame The register frame.
2324	* @param DestRegDRx DRx register index (USE_REG_DR*)
2325	* @param SrcRegGen General purpose register index (USE_REG_E**))
2326	*
2327	*/
2328	VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
2329	{
2330	uint64_t val;
2331	int rc;
2332
2333	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2334	{
2335	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2336	}
2337	else
2338	{
2339	uint32_t val32;
2340	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2341	val = val32;
2342	}
2343
2344	if (RT_SUCCESS(rc))
2345	{
2346	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
2347	rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
2348	if (RT_SUCCESS(rc))
2349	return rc;
2350	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
2351	}
2352	return VERR_EM_INTERPRETER;
2353	}
2354
2355
2356	/**
2357	* Interpret DRx read
2358	*
2359	* @returns VBox status code.
2360	* @param pVM The VM handle.
2361	* @param pRegFrame The register frame.
2362	* @param DestRegGen General purpose register index (USE_REG_E**))
2363	* @param SrcRegDRx DRx register index (USE_REG_DR*)
2364	*
2365	*/
2366	VMMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
2367	{
2368	uint64_t val64;
2369
2370	int rc = CPUMGetGuestDRx(pVM, SrcRegDrx, &val64);
2371	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
2372	if (CPUMIsGuestIn64BitCode(pVM, pRegFrame))
2373	{
2374	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2375	}
2376	else
2377	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2378
2379	if (RT_SUCCESS(rc))
2380	return VINF_SUCCESS;
2381
2382	return VERR_EM_INTERPRETER;
2383	}
2384
2385
2386	/**
2387	* MOV DRx
2388	*/
2389	static int emInterpretMovDRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2390	{
2391	int rc = VERR_EM_INTERPRETER;
2392
2393	if((pCpu->param1.flags == USE_REG_GEN32 \|\| pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_DBG)
2394	{
2395	rc = EMInterpretDRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_dbg);
2396	}
2397	else
2398	if(pCpu->param1.flags == USE_REG_DBG && (pCpu->param2.flags == USE_REG_GEN32 \|\| pCpu->param2.flags == USE_REG_GEN64))
2399	{
2400	rc = EMInterpretDRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_dbg, pCpu->param2.base.reg_gen);
2401	}
2402	else
2403	AssertMsgFailed(("Unexpected debug register move\n"));
2404
2405	return rc;
2406	}
2407
2408
2409	/**
2410	* LLDT Emulation.
2411	*/
2412	static int emInterpretLLdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2413	{
2414	OP_PARAMVAL param1;
2415	RTSEL sel;
2416
2417	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2418	if(RT_FAILURE(rc))
2419	return VERR_EM_INTERPRETER;
2420
2421	switch(param1.type)
2422	{
2423	case PARMTYPE_ADDRESS:
2424	return VERR_EM_INTERPRETER; //feeling lazy right now
2425
2426	case PARMTYPE_IMMEDIATE:
2427	if(!(param1.flags & PARAM_VAL16))
2428	return VERR_EM_INTERPRETER;
2429	sel = (RTSEL)param1.val.val16;
2430	break;
2431
2432	default:
2433	return VERR_EM_INTERPRETER;
2434	}
2435
2436	if (sel == 0)
2437	{
2438	if (CPUMGetHyperLDTR(pVM) == 0)
2439	{
2440	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
2441	return VINF_SUCCESS;
2442	}
2443	}
2444	//still feeling lazy
2445	return VERR_EM_INTERPRETER;
2446	}
2447
2448	#ifdef IN_RING0
2449	/**
2450	* LIDT/LGDT Emulation.
2451	*/
2452	static int emInterpretLIGdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2453	{
2454	OP_PARAMVAL param1;
2455	RTGCPTR pParam1;
2456	X86XDTR32 dtr32;
2457
2458	Log(("Emulate %s at %RGv\n", emGetMnemonic(pCpu), (RTGCPTR)pRegFrame->rip));
2459
2460	/* Only for the VT-x real-mode emulation case. */
2461	if (!CPUMIsGuestInRealMode(pVM))
2462	return VERR_EM_INTERPRETER;
2463
2464	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2465	if(RT_FAILURE(rc))
2466	return VERR_EM_INTERPRETER;
2467
2468	switch(param1.type)
2469	{
2470	case PARMTYPE_ADDRESS:
2471	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, param1.val.val16);
2472	break;
2473
2474	default:
2475	return VERR_EM_INTERPRETER;
2476	}
2477
2478	rc = emRamRead(pVM, pRegFrame, &dtr32, pParam1, sizeof(dtr32));
2479	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2480
2481	if (!(pCpu->prefix & PREFIX_OPSIZE))
2482	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
2483
2484	if (pCpu->pCurInstr->opcode == OP_LIDT)
2485	CPUMSetGuestIDTR(pVM, dtr32.uAddr, dtr32.cb);
2486	else
2487	CPUMSetGuestGDTR(pVM, dtr32.uAddr, dtr32.cb);
2488
2489	return VINF_SUCCESS;
2490	}
2491	#endif
2492
2493
2494	#ifdef IN_RC
2495	/**
2496	* STI Emulation.
2497	*
2498	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
2499	*/
2500	static int emInterpretSti(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2501	{
2502	PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
2503
2504	if(!pGCState)
2505	{
2506	Assert(pGCState);
2507	return VERR_EM_INTERPRETER;
2508	}
2509	pGCState->uVMFlags \|= X86_EFL_IF;
2510
2511	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
2512	Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
2513
2514	pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize;
2515	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2516
2517	return VINF_SUCCESS;
2518	}
2519	#endif /* IN_RC */
2520
2521
2522	/**
2523	* HLT Emulation.
2524	*/
2525	static int emInterpretHlt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2526	{
2527	return VINF_EM_HALT;
2528	}
2529
2530
2531	/**
2532	* Interpret RDTSC
2533	*
2534	* @returns VBox status code.
2535	* @param pVM The VM handle.
2536	* @param pRegFrame The register frame.
2537	*
2538	*/
2539	VMMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame)
2540	{
2541	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2542
2543	if (uCR4 & X86_CR4_TSD)
2544	return VERR_EM_INTERPRETER; /* genuine #GP */
2545
2546	uint64_t uTicks = TMCpuTickGet(pVM);
2547
2548	/* Same behaviour in 32 & 64 bits mode */
2549	pRegFrame->rax = (uint32_t)uTicks;
2550	pRegFrame->rdx = (uTicks >> 32ULL);
2551
2552	return VINF_SUCCESS;
2553	}
2554
2555	VMMDECL(int) EMInterpretRdtscp(PVM pVM, PCPUMCTX pCtx)
2556	{
2557	unsigned uCR4 = CPUMGetGuestCR4(pVM);
2558
2559	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
2560	{
2561	AssertFailed();
2562	return VERR_EM_INTERPRETER; /* genuine #UD */
2563	}
2564
2565	if (uCR4 & X86_CR4_TSD)
2566	return VERR_EM_INTERPRETER; /* genuine #GP */
2567
2568	uint64_t uTicks = TMCpuTickGet(pVM);
2569
2570	/* Same behaviour in 32 & 64 bits mode */
2571	pCtx->rax = (uint32_t)uTicks;
2572	pCtx->rdx = (uTicks >> 32ULL);
2573	/* Low dword of the TSC_AUX msr only. */
2574	pCtx->rcx = (uint32_t)CPUMGetGuestMsr(pVM, MSR_K8_TSC_AUX);
2575
2576	return VINF_SUCCESS;
2577	}
2578
2579	/**
2580	* RDTSC Emulation.
2581	*/
2582	static int emInterpretRdtsc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2583	{
2584	return EMInterpretRdtsc(pVM, pRegFrame);
2585	}
2586
2587
2588	/**
2589	* MONITOR Emulation.
2590	*/
2591	static int emInterpretMonitor(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2592	{
2593	uint32_t u32Dummy, u32ExtFeatures, cpl;
2594
2595	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2596	if (pRegFrame->ecx != 0)
2597	return VERR_EM_INTERPRETER; /* illegal value. */
2598
2599	/* Get the current privilege level. */
2600	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2601	if (cpl != 0)
2602	return VERR_EM_INTERPRETER; /* supervisor only */
2603
2604	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2605	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2606	return VERR_EM_INTERPRETER; /* not supported */
2607
2608	return VINF_SUCCESS;
2609	}
2610
2611
2612	/**
2613	* MWAIT Emulation.
2614	*/
2615	static int emInterpretMWait(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2616	{
2617	uint32_t u32Dummy, u32ExtFeatures, cpl;
2618
2619	Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2620	if (pRegFrame->ecx != 0)
2621	return VERR_EM_INTERPRETER; /* illegal value. */
2622
2623	/* Get the current privilege level. */
2624	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2625	if (cpl != 0)
2626	return VERR_EM_INTERPRETER; /* supervisor only */
2627
2628	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2629	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2630	return VERR_EM_INTERPRETER; /* not supported */
2631
2632	/** @todo not completely correct */
2633	return VINF_EM_HALT;
2634	}
2635
2636
2637	#ifdef LOG_ENABLED
2638	static const char *emMSRtoString(uint32_t uMsr)
2639	{
2640	switch (uMsr)
2641	{
2642	case MSR_IA32_APICBASE:
2643	return "MSR_IA32_APICBASE";
2644	case MSR_IA32_CR_PAT:
2645	return "MSR_IA32_CR_PAT";
2646	case MSR_IA32_SYSENTER_CS:
2647	return "MSR_IA32_SYSENTER_CS";
2648	case MSR_IA32_SYSENTER_EIP:
2649	return "MSR_IA32_SYSENTER_EIP";
2650	case MSR_IA32_SYSENTER_ESP:
2651	return "MSR_IA32_SYSENTER_ESP";
2652	case MSR_K6_EFER:
2653	return "MSR_K6_EFER";
2654	case MSR_K8_SF_MASK:
2655	return "MSR_K8_SF_MASK";
2656	case MSR_K6_STAR:
2657	return "MSR_K6_STAR";
2658	case MSR_K8_LSTAR:
2659	return "MSR_K8_LSTAR";
2660	case MSR_K8_CSTAR:
2661	return "MSR_K8_CSTAR";
2662	case MSR_K8_FS_BASE:
2663	return "MSR_K8_FS_BASE";
2664	case MSR_K8_GS_BASE:
2665	return "MSR_K8_GS_BASE";
2666	case MSR_K8_KERNEL_GS_BASE:
2667	return "MSR_K8_KERNEL_GS_BASE";
2668	case MSR_K8_TSC_AUX:
2669	return "MSR_K8_TSC_AUX";
2670	case MSR_IA32_BIOS_SIGN_ID:
2671	return "Unsupported MSR_IA32_BIOS_SIGN_ID";
2672	case MSR_IA32_PLATFORM_ID:
2673	return "Unsupported MSR_IA32_PLATFORM_ID";
2674	case MSR_IA32_BIOS_UPDT_TRIG:
2675	return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
2676	case MSR_IA32_TSC:
2677	return "Unsupported MSR_IA32_TSC";
2678	case MSR_IA32_MTRR_CAP:
2679	return "Unsupported MSR_IA32_MTRR_CAP";
2680	case MSR_IA32_MCP_CAP:
2681	return "Unsupported MSR_IA32_MCP_CAP";
2682	case MSR_IA32_MCP_STATUS:
2683	return "Unsupported MSR_IA32_MCP_STATUS";
2684	case MSR_IA32_MCP_CTRL:
2685	return "Unsupported MSR_IA32_MCP_CTRL";
2686	case MSR_IA32_MTRR_DEF_TYPE:
2687	return "Unsupported MSR_IA32_MTRR_DEF_TYPE";
2688	case MSR_K7_EVNTSEL0:
2689	return "Unsupported MSR_K7_EVNTSEL0";
2690	case MSR_K7_EVNTSEL1:
2691	return "Unsupported MSR_K7_EVNTSEL1";
2692	case MSR_K7_EVNTSEL2:
2693	return "Unsupported MSR_K7_EVNTSEL2";
2694	case MSR_K7_EVNTSEL3:
2695	return "Unsupported MSR_K7_EVNTSEL3";
2696	case MSR_IA32_MC0_CTL:
2697	return "Unsupported MSR_IA32_MC0_CTL";
2698	case MSR_IA32_MC0_STATUS:
2699	return "Unsupported MSR_IA32_MC0_STATUS";
2700	}
2701	return "Unknown MSR";
2702	}
2703	#endif /* LOG_ENABLED */
2704
2705
2706	/**
2707	* Interpret RDMSR
2708	*
2709	* @returns VBox status code.
2710	* @param pVM The VM handle.
2711	* @param pRegFrame The register frame.
2712	*
2713	*/
2714	VMMDECL(int) EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2715	{
2716	uint32_t u32Dummy, u32Features, cpl;
2717	uint64_t val;
2718	CPUMCTX *pCtx;
2719	int rc = VINF_SUCCESS;
2720
2721	/** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
2722	* That version clears the high dwords of both RDX & RAX */
2723	pCtx = CPUMQueryGuestCtxPtr(pVM);
2724
2725	/* Get the current privilege level. */
2726	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2727	if (cpl != 0)
2728	return VERR_EM_INTERPRETER; /* supervisor only */
2729
2730	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2731	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2732	return VERR_EM_INTERPRETER; /* not supported */
2733
2734	switch (pRegFrame->ecx)
2735	{
2736	case MSR_IA32_APICBASE:
2737	rc = PDMApicGetBase(pVM, &val);
2738	AssertRC(rc);
2739	break;
2740
2741	case MSR_IA32_CR_PAT:
2742	val = pCtx->msrPAT;
2743	break;
2744
2745	case MSR_IA32_SYSENTER_CS:
2746	val = pCtx->SysEnter.cs;
2747	break;
2748
2749	case MSR_IA32_SYSENTER_EIP:
2750	val = pCtx->SysEnter.eip;
2751	break;
2752
2753	case MSR_IA32_SYSENTER_ESP:
2754	val = pCtx->SysEnter.esp;
2755	break;
2756
2757	case MSR_K6_EFER:
2758	val = pCtx->msrEFER;
2759	break;
2760
2761	case MSR_K8_SF_MASK:
2762	val = pCtx->msrSFMASK;
2763	break;
2764
2765	case MSR_K6_STAR:
2766	val = pCtx->msrSTAR;
2767	break;
2768
2769	case MSR_K8_LSTAR:
2770	val = pCtx->msrLSTAR;
2771	break;
2772
2773	case MSR_K8_CSTAR:
2774	val = pCtx->msrCSTAR;
2775	break;
2776
2777	case MSR_K8_FS_BASE:
2778	val = pCtx->fsHid.u64Base;
2779	break;
2780
2781	case MSR_K8_GS_BASE:
2782	val = pCtx->gsHid.u64Base;
2783	break;
2784
2785	case MSR_K8_KERNEL_GS_BASE:
2786	val = pCtx->msrKERNELGSBASE;
2787	break;
2788
2789	case MSR_K8_TSC_AUX:
2790	val = CPUMGetGuestMsr(pVM, MSR_K8_TSC_AUX);
2791	break;
2792
2793	#if 0 /def IN_RING0 /
2794	case MSR_IA32_PLATFORM_ID:
2795	case MSR_IA32_BIOS_SIGN_ID:
2796	if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
2797	{
2798	/* Available since the P6 family. VT-x implies that this feature is present. */
2799	if (pRegFrame->ecx == MSR_IA32_PLATFORM_ID)
2800	val = ASMRdMsr(MSR_IA32_PLATFORM_ID);
2801	else
2802	if (pRegFrame->ecx == MSR_IA32_BIOS_SIGN_ID)
2803	val = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
2804	break;
2805	}
2806	/* no break */
2807	#endif
2808	default:
2809	/* In X2APIC specification this range is reserved for APIC control. */
2810	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
2811	rc = PDMApicReadMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, &val);
2812	else
2813	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2814	val = 0;
2815	break;
2816	}
2817	LogFlow(("EMInterpretRdmsr %s (%x) -> val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2818	if (rc == VINF_SUCCESS)
2819	{
2820	pRegFrame->rax = (uint32_t) val;
2821	pRegFrame->rdx = (uint32_t) (val >> 32ULL);
2822	}
2823	return rc;
2824	}
2825
2826
2827	/**
2828	* RDMSR Emulation.
2829	*/
2830	static int emInterpretRdmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2831	{
2832	/* Note: the Intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2833	Assert(!(pCpu->prefix & PREFIX_REX));
2834	return EMInterpretRdmsr(pVM, pRegFrame);
2835	}
2836
2837
2838	/**
2839	* Interpret WRMSR
2840	*
2841	* @returns VBox status code.
2842	* @param pVM The VM handle.
2843	* @param pRegFrame The register frame.
2844	*/
2845	VMMDECL(int) EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2846	{
2847	uint32_t u32Dummy, u32Features, cpl;
2848	uint64_t val;
2849	CPUMCTX *pCtx;
2850
2851	/* Note: works the same in 32 and 64 bits modes. */
2852	pCtx = CPUMQueryGuestCtxPtr(pVM);
2853
2854	/* Get the current privilege level. */
2855	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2856	if (cpl != 0)
2857	return VERR_EM_INTERPRETER; /* supervisor only */
2858
2859	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2860	if (!(u32Features & X86_CPUID_FEATURE_EDX_MSR))
2861	return VERR_EM_INTERPRETER; /* not supported */
2862
2863	val = RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx);
2864	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
2865	switch (pRegFrame->ecx)
2866	{
2867	case MSR_IA32_APICBASE:
2868	{
2869	int rc = PDMApicSetBase(pVM, val);
2870	AssertRC(rc);
2871	break;
2872	}
2873
2874	case MSR_IA32_CR_PAT:
2875	pCtx->msrPAT = val;
2876	break;
2877
2878	case MSR_IA32_SYSENTER_CS:
2879	pCtx->SysEnter.cs = val & 0xffff; /* 16 bits selector */
2880	break;
2881
2882	case MSR_IA32_SYSENTER_EIP:
2883	pCtx->SysEnter.eip = val;
2884	break;
2885
2886	case MSR_IA32_SYSENTER_ESP:
2887	pCtx->SysEnter.esp = val;
2888	break;
2889
2890	case MSR_K6_EFER:
2891	{
2892	uint64_t uMask = 0;
2893	uint64_t oldval = pCtx->msrEFER;
2894
2895	/* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
2896	CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2897	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_NX)
2898	uMask \|= MSR_K6_EFER_NXE;
2899	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
2900	uMask \|= MSR_K6_EFER_LME;
2901	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_SEP)
2902	uMask \|= MSR_K6_EFER_SCE;
2903	if (u32Features & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
2904	uMask \|= MSR_K6_EFER_FFXSR;
2905
2906	/* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2907	if ( ((pCtx->msrEFER & MSR_K6_EFER_LME) != (val & uMask & MSR_K6_EFER_LME))
2908	&& (pCtx->cr0 & X86_CR0_PG))
2909	{
2910	AssertMsgFailed(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
2911	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2912	}
2913
2914	/* There are a few more: e.g. MSR_K6_EFER_LMSLE */
2915	AssertMsg(!(val & ~(MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA /* ignored anyway */ \|MSR_K6_EFER_SCE\|MSR_K6_EFER_FFXSR)), ("Unexpected value %RX64\n", val));
2916	pCtx->msrEFER = (pCtx->msrEFER & ~uMask) \| (val & uMask);
2917
2918	/* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
2919	if ((oldval & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE\|MSR_K6_EFER_LME\|MSR_K6_EFER_LMA)))
2920	HWACCMFlushTLB(pVM);
2921
2922	break;
2923	}
2924
2925	case MSR_K8_SF_MASK:
2926	pCtx->msrSFMASK = val;
2927	break;
2928
2929	case MSR_K6_STAR:
2930	pCtx->msrSTAR = val;
2931	break;
2932
2933	case MSR_K8_LSTAR:
2934	pCtx->msrLSTAR = val;
2935	break;
2936
2937	case MSR_K8_CSTAR:
2938	pCtx->msrCSTAR = val;
2939	break;
2940
2941	case MSR_K8_FS_BASE:
2942	pCtx->fsHid.u64Base = val;
2943	break;
2944
2945	case MSR_K8_GS_BASE:
2946	pCtx->gsHid.u64Base = val;
2947	break;
2948
2949	case MSR_K8_KERNEL_GS_BASE:
2950	pCtx->msrKERNELGSBASE = val;
2951	break;
2952
2953	case MSR_K8_TSC_AUX:
2954	CPUMSetGuestMsr(pVM, MSR_K8_TSC_AUX, val);
2955	break;
2956
2957	default:
2958	/* In X2APIC specification this range is reserved for APIC control. */
2959	if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
2960	return PDMApicWriteMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, val);
2961
2962	/* We should actually trigger a #GP here, but don't as that might cause more trouble. */
2963	break;
2964	}
2965	return VINF_SUCCESS;
2966	}
2967
2968
2969	/**
2970	* WRMSR Emulation.
2971	*/
2972	static int emInterpretWrmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2973	{
2974	return EMInterpretWrmsr(pVM, pRegFrame);
2975	}
2976
2977
2978	/**
2979	* Internal worker.
2980	* @copydoc EMInterpretInstructionCPU
2981	*/
2982	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2983	{
2984	Assert(pcbSize);
2985	*pcbSize = 0;
2986
2987	/*
2988	* Only supervisor guest code!!
2989	* And no complicated prefixes.
2990	*/
2991	/* Get the current privilege level. */
2992	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2993	if ( cpl != 0
2994	&& pCpu->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
2995	{
2996	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
2997	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
2998	return VERR_EM_INTERPRETER;
2999	}
3000
3001	#ifdef IN_RC
3002	if ( (pCpu->prefix & (PREFIX_REPNE \| PREFIX_REP))
3003	\|\| ( (pCpu->prefix & PREFIX_LOCK)
3004	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
3005	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
3006	&& pCpu->pCurInstr->opcode != OP_XADD
3007	&& pCpu->pCurInstr->opcode != OP_OR
3008	&& pCpu->pCurInstr->opcode != OP_BTR
3009	)
3010	)
3011	#else
3012	if ( (pCpu->prefix & PREFIX_REPNE)
3013	\|\| ( (pCpu->prefix & PREFIX_REP)
3014	&& pCpu->pCurInstr->opcode != OP_STOSWD
3015	)
3016	\|\| ( (pCpu->prefix & PREFIX_LOCK)
3017	&& pCpu->pCurInstr->opcode != OP_OR
3018	&& pCpu->pCurInstr->opcode != OP_BTR
3019	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
3020	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
3021	)
3022	)
3023	#endif
3024	{
3025	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
3026	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
3027	return VERR_EM_INTERPRETER;
3028	}
3029
3030	#if HC_ARCH_BITS == 32
3031	/*
3032	* Unable to emulate most >4 bytes accesses in 32 bits mode.
3033	* Whitelisted instructions are safe.
3034	*/
3035	if ( pCpu->param1.size > 4
3036	&& CPUMIsGuestIn64BitCode(pVM, pRegFrame))
3037	{
3038	uint32_t uOpCode = pCpu->pCurInstr->opcode;
3039	if ( uOpCode != OP_STOSWD
3040	&& uOpCode != OP_MOV
3041	&& uOpCode != OP_CMPXCHG8B
3042	&& uOpCode != OP_XCHG
3043	&& uOpCode != OP_BTS
3044	&& uOpCode != OP_BTR
3045	&& uOpCode != OP_BTC
3046	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
3047	&& uOpCode != OP_CMPXCHG /* solaris */
3048	&& uOpCode != OP_AND /* windows */
3049	&& uOpCode != OP_OR /* windows */
3050	&& uOpCode != OP_XOR /* because we can */
3051	&& uOpCode != OP_ADD /* windows (dripple) */
3052	&& uOpCode != OP_ADC /* because we can */
3053	&& uOpCode != OP_SUB /* because we can */
3054	/** @todo OP_BTS or is that a different kind of failure? */
3055	# endif
3056	)
3057	{
3058	# ifdef VBOX_WITH_STATISTICS
3059	switch (pCpu->pCurInstr->opcode)
3060	{
3061	# define INTERPRET_FAILED_CASE(opcode, Instr) \
3062	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
3063	INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
3064	INTERPRET_FAILED_CASE(OP_DEC,Dec);
3065	INTERPRET_FAILED_CASE(OP_INC,Inc);
3066	INTERPRET_FAILED_CASE(OP_POP,Pop);
3067	INTERPRET_FAILED_CASE(OP_OR, Or);
3068	INTERPRET_FAILED_CASE(OP_XOR,Xor);
3069	INTERPRET_FAILED_CASE(OP_AND,And);
3070	INTERPRET_FAILED_CASE(OP_MOV,Mov);
3071	INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
3072	INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
3073	INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
3074	INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
3075	INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
3076	INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
3077	INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
3078	INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
3079	INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
3080	INTERPRET_FAILED_CASE(OP_CLTS,Clts);
3081	INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
3082	INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
3083	INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
3084	INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
3085	INTERPRET_FAILED_CASE(OP_ADD,Add);
3086	INTERPRET_FAILED_CASE(OP_SUB,Sub);
3087	INTERPRET_FAILED_CASE(OP_ADC,Adc);
3088	INTERPRET_FAILED_CASE(OP_BTR,Btr);
3089	INTERPRET_FAILED_CASE(OP_BTS,Bts);
3090	INTERPRET_FAILED_CASE(OP_BTC,Btc);
3091	INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
3092	INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
3093	INTERPRET_FAILED_CASE(OP_STI, Sti);
3094	INTERPRET_FAILED_CASE(OP_XADD,XAdd);
3095	INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
3096	INTERPRET_FAILED_CASE(OP_HLT, Hlt);
3097	INTERPRET_FAILED_CASE(OP_IRET,Iret);
3098	INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
3099	INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3100	# undef INTERPRET_FAILED_CASE
3101	default:
3102	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3103	break;
3104	}
3105	# endif /* VBOX_WITH_STATISTICS */
3106	return VERR_EM_INTERPRETER;
3107	}
3108	}
3109	#endif
3110
3111	int rc;
3112	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
3113	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pCpu)));
3114	#endif
3115	switch (pCpu->pCurInstr->opcode)
3116	{
3117	/*
3118	* Macros for generating the right case statements.
3119	*/
3120	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3121	case opcode:\
3122	if (pCpu->prefix & PREFIX_LOCK) \
3123	rc = emInterpretLock##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3124	else \
3125	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3126	if (RT_SUCCESS(rc)) \
3127	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3128	else \
3129	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3130	return rc
3131	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3132	case opcode:\
3133	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3134	if (RT_SUCCESS(rc)) \
3135	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3136	else \
3137	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3138	return rc
3139
3140	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3141	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3142	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3143	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3144
3145	#define INTERPRET_CASE(opcode, Instr) \
3146	case opcode:\
3147	rc = emInterpret##Instr(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
3148	if (RT_SUCCESS(rc)) \
3149	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3150	else \
3151	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3152	return rc
3153
3154	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3155	case opcode:\
3156	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
3157	if (RT_SUCCESS(rc)) \
3158	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3159	else \
3160	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3161	return rc
3162
3163	#define INTERPRET_STAT_CASE(opcode, Instr) \
3164	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3165
3166	/*
3167	* The actual case statements.
3168	*/
3169	INTERPRET_CASE(OP_XCHG,Xchg);
3170	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3171	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3172	INTERPRET_CASE(OP_POP,Pop);
3173	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3174	INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
3175	INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
3176	INTERPRET_CASE(OP_MOV,Mov);
3177	#ifndef IN_RC
3178	INTERPRET_CASE(OP_STOSWD,StosWD);
3179	#endif
3180	INTERPRET_CASE(OP_INVLPG,InvlPg);
3181	INTERPRET_CASE(OP_CPUID,CpuId);
3182	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3183	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3184	INTERPRET_CASE(OP_LLDT,LLdt);
3185	#ifdef IN_RING0
3186	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3187	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3188	#endif
3189	INTERPRET_CASE(OP_LMSW,Lmsw);
3190	#ifdef EM_EMULATE_SMSW
3191	INTERPRET_CASE(OP_SMSW,Smsw);
3192	#endif
3193	INTERPRET_CASE(OP_CLTS,Clts);
3194	INTERPRET_CASE(OP_MONITOR, Monitor);
3195	INTERPRET_CASE(OP_MWAIT, MWait);
3196	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3197	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3198	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3199	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3200	INTERPRET_CASE(OP_ADC,Adc);
3201	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3202	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3203	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3204	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3205	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3206	#ifdef IN_RC
3207	INTERPRET_CASE(OP_STI,Sti);
3208	INTERPRET_CASE(OP_XADD, XAdd);
3209	#endif
3210	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3211	INTERPRET_CASE(OP_HLT,Hlt);
3212	INTERPRET_CASE(OP_IRET,Iret);
3213	INTERPRET_CASE(OP_WBINVD,WbInvd);
3214	#ifdef VBOX_WITH_STATISTICS
3215	# ifndef IN_RC
3216	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3217	# endif
3218	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3219	#endif
3220
3221	default:
3222	Log3(("emInterpretInstructionCPU: opcode=%d\n", pCpu->pCurInstr->opcode));
3223	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3224	return VERR_EM_INTERPRETER;
3225
3226	#undef INTERPRET_CASE_EX_PARAM2
3227	#undef INTERPRET_STAT_CASE
3228	#undef INTERPRET_CASE_EX
3229	#undef INTERPRET_CASE
3230	} /* switch (opcode) */
3231	AssertFailed();
3232	return VERR_INTERNAL_ERROR;
3233	}
3234
3235
3236	/**
3237	* Sets the PC for which interrupts should be inhibited.
3238	*
3239	* @param pVM The VM handle.
3240	* @param PC The PC.
3241	*/
3242	VMMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC)
3243	{
3244	pVM->em.s.GCPtrInhibitInterrupts = PC;
3245	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
3246	}
3247
3248
3249	/**
3250	* Gets the PC for which interrupts should be inhibited.
3251	*
3252	* There are a few instructions which inhibits or delays interrupts
3253	* for the instruction following them. These instructions are:
3254	* - STI
3255	* - MOV SS, r/m16
3256	* - POP SS
3257	*
3258	* @returns The PC for which interrupts should be inhibited.
3259	* @param pVM VM handle.
3260	*
3261	*/
3262	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM)
3263	{
3264	return pVM->em.s.GCPtrInhibitInterrupts;
3265	}
3266

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 17596

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