VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp@ 53534

Last change on this file since 53534 was 53466, checked in by vboxsync, 10 years ago

VMM/MSRs: Added status codes for returning to ring-3 to service the MSR access.
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File size: 9.9 KB
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1/* $Id: GIMAllHv.cpp 53466 2014-12-05 16:07:33Z vboxsync $ */
2/** @file
3 * GIM - Guest Interface Manager, Microsoft Hyper-V, All Contexts.
4 */
5
6/*
7 * Copyright (C) 2014 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_GIM
22#include "GIMHvInternal.h"
23#include "GIMInternal.h"
24
25#include <VBox/err.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/tm.h>
28#include <VBox/vmm/vm.h>
29#include <VBox/vmm/pgm.h>
30#include <VBox/vmm/pdmdev.h>
31#include <VBox/vmm/pdmapi.h>
32
33#include <iprt/asm-amd64-x86.h>
34#include <iprt/spinlock.h>
35
36
37/**
38 * Handles the Hyper-V hypercall.
39 *
40 * @returns VBox status code.
41 * @param pVCpu Pointer to the VMCPU.
42 * @param pCtx Pointer to the guest-CPU context.
43 */
44VMM_INT_DECL(int) GIMHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
45{
46 PVM pVM = pVCpu->CTX_SUFF(pVM);
47 if (!MSR_GIM_HV_HYPERCALL_IS_ENABLED(pVM->gim.s.u.Hv.u64HypercallMsr))
48 return VERR_GIM_HYPERCALLS_NOT_ENABLED;
49
50 /** @todo Handle hypercalls. Fail for now */
51 return VERR_GIM_IPE_3;
52}
53
54
55/**
56 * Returns whether the guest has configured and enabled the use of Hyper-V's
57 * hypercall interface.
58 *
59 * @returns true if hypercalls are enabled, false otherwise.
60 * @param pVCpu Pointer to the VMCPU.
61 */
62VMM_INT_DECL(bool) GIMHvAreHypercallsEnabled(PVMCPU pVCpu)
63{
64 return MSR_GIM_HV_HYPERCALL_IS_ENABLED(pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv.u64HypercallMsr);
65}
66
67
68/**
69 * Returns whether the guest has configured and enabled the use of Hyper-V's
70 * paravirtualized TSC.
71 *
72 * @returns true if paravirt. TSC is enabled, false otherwise.
73 * @param pVM Pointer to the VM.
74 */
75VMM_INT_DECL(bool) GIMHvIsParavirtTscEnabled(PVM pVM)
76{
77 return MSR_GIM_HV_REF_TSC_IS_ENABLED(pVM->gim.s.u.Hv.u64TscPageMsr);
78}
79
80
81/**
82 * MSR read handler for Hyper-V.
83 *
84 * @returns Strict VBox status code like CPUMQueryGuestMsr.
85 * @retval VINF_CPUM_R3_MSR_READ
86 * @retval VERR_CPUM_RAISE_GP_0
87 *
88 * @param pVCpu Pointer to the VMCPU.
89 * @param idMsr The MSR being read.
90 * @param pRange The range this MSR belongs to.
91 * @param puValue Where to store the MSR value read.
92 */
93VMM_INT_DECL(VBOXSTRICTRC) GIMHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
94{
95 NOREF(pRange);
96 PVM pVM = pVCpu->CTX_SUFF(pVM);
97 PGIMHV pHv = &pVM->gim.s.u.Hv;
98
99 switch (idMsr)
100 {
101 case MSR_GIM_HV_TIME_REF_COUNT:
102 {
103 /* Hyper-V reports the time in 100 ns units (10 MHz). */
104 uint64_t u64Tsc = TMCpuTickGet(pVCpu);
105 uint64_t u64TscHz = TMCpuTicksPerSecond(pVM);
106 uint64_t u64Tsc100Ns = u64TscHz / UINT64_C(10000000); /* 100 ns */
107 *puValue = (u64Tsc / u64Tsc100Ns);
108 return VINF_SUCCESS;
109 }
110
111 case MSR_GIM_HV_VP_INDEX:
112 *puValue = pVCpu->idCpu;
113 return VINF_SUCCESS;
114
115 case MSR_GIM_HV_TPR:
116 PDMApicReadMSR(pVM, pVCpu->idCpu, 0x80, puValue);
117 return VINF_SUCCESS;
118
119 case MSR_GIM_HV_EOI:
120 PDMApicReadMSR(pVM, pVCpu->idCpu, 0x0B, puValue);
121 return VINF_SUCCESS;
122
123 case MSR_GIM_HV_ICR:
124 PDMApicReadMSR(pVM, pVCpu->idCpu, 0x30, puValue);
125 return VINF_SUCCESS;
126
127 case MSR_GIM_HV_GUEST_OS_ID:
128 *puValue = pHv->u64GuestOsIdMsr;
129 return VINF_SUCCESS;
130
131 case MSR_GIM_HV_HYPERCALL:
132 *puValue = pHv->u64HypercallMsr;
133 return VINF_SUCCESS;
134
135 case MSR_GIM_HV_REF_TSC:
136 *puValue = pHv->u64TscPageMsr;
137 return VINF_SUCCESS;
138
139 case MSR_GIM_HV_TSC_FREQ:
140 *puValue = TMCpuTicksPerSecond(pVM);
141 return VINF_SUCCESS;
142
143 case MSR_GIM_HV_APIC_FREQ:
144 {
145 int rc = PDMApicGetTimerFreq(pVM, puValue);
146 if (RT_FAILURE(rc))
147 return VERR_CPUM_RAISE_GP_0;
148 return VINF_SUCCESS;
149 }
150
151 case MSR_GIM_HV_RESET:
152 *puValue = 0;
153 return VINF_SUCCESS;
154
155 default:
156#ifdef IN_RING3
157 static uint32_t s_cTimes = 0;
158 if (s_cTimes++ < 20)
159 LogRel(("GIM: HyperV: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
160#endif
161 LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
162 break;
163 }
164
165 return VERR_CPUM_RAISE_GP_0;
166}
167
168
169/**
170 * MSR write handler for Hyper-V.
171 *
172 * @returns Strict VBox status code like CPUMSetGuestMsr.
173 * @retval VINF_CPUM_R3_MSR_WRITE
174 * @retval VERR_CPUM_RAISE_GP_0
175 *
176 * @param pVCpu Pointer to the VMCPU.
177 * @param idMsr The MSR being written.
178 * @param pRange The range this MSR belongs to.
179 * @param uRawValue The raw value with the ignored bits not masked.
180 */
181VMM_INT_DECL(VBOXSTRICTRC) GIMHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
182{
183 NOREF(pRange);
184 PVM pVM = pVCpu->CTX_SUFF(pVM);
185 PGIMHV pHv = &pVM->gim.s.u.Hv;
186
187 switch (idMsr)
188 {
189 case MSR_GIM_HV_TPR:
190 PDMApicWriteMSR(pVM, pVCpu->idCpu, 0x80, uRawValue);
191 return VINF_SUCCESS;
192
193 case MSR_GIM_HV_EOI:
194 PDMApicWriteMSR(pVM, pVCpu->idCpu, 0x0B, uRawValue);
195 return VINF_SUCCESS;
196
197 case MSR_GIM_HV_ICR:
198 PDMApicWriteMSR(pVM, pVCpu->idCpu, 0x30, uRawValue);
199 return VINF_SUCCESS;
200
201 case MSR_GIM_HV_GUEST_OS_ID:
202 {
203#ifndef IN_RING3
204 return VINF_CPUM_R3_MSR_WRITE;
205#else
206 /* Disable the hypercall-page if 0 is written to this MSR. */
207 if (!uRawValue)
208 {
209 GIMR3HvDisableHypercallPage(pVM);
210 pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_ENABLE_BIT;
211 }
212 pHv->u64GuestOsIdMsr = uRawValue;
213 return VINF_SUCCESS;
214#endif /* IN_RING3 */
215 }
216
217 case MSR_GIM_HV_HYPERCALL:
218 {
219#ifndef IN_RING3
220 return VINF_CPUM_R3_MSR_WRITE;
221#else /* IN_RING3 */
222 /* First, update all but the hypercall enable bit. */
223 pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_ENABLE_BIT);
224
225 /* Hypercalls can only be enabled when the guest has set the Guest-OS Id Msr. */
226 bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_HYPERCALL_ENABLE_BIT);
227 if ( fEnable
228 && !pHv->u64GuestOsIdMsr)
229 {
230 return VINF_SUCCESS;
231 }
232
233 /* Is the guest disabling the hypercall-page? Allow it regardless of the Guest-OS Id Msr. */
234 if (!fEnable)
235 {
236 GIMR3HvDisableHypercallPage(pVM);
237 pHv->u64HypercallMsr = uRawValue;
238 return VINF_SUCCESS;
239 }
240
241 /* Enable the hypercall-page. */
242 RTGCPHYS GCPhysHypercallPage = MSR_GIM_HV_HYPERCALL_GUEST_PFN(uRawValue) << PAGE_SHIFT;
243 int rc = GIMR3HvEnableHypercallPage(pVM, GCPhysHypercallPage);
244 if (RT_SUCCESS(rc))
245 {
246 pHv->u64HypercallMsr = uRawValue;
247 return VINF_SUCCESS;
248 }
249
250 return VERR_CPUM_RAISE_GP_0;
251#endif /* IN_RING3 */
252 }
253
254 case MSR_GIM_HV_REF_TSC:
255 {
256#ifndef IN_RING3
257 return VINF_CPUM_R3_MSR_WRITE;
258#else /* IN_RING3 */
259 /* First, update all but the TSC-page enable bit. */
260 pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE_BIT);
261
262 /* Is the guest disabling the TSC-page? */
263 bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_REF_TSC_ENABLE_BIT);
264 if (!fEnable)
265 {
266 GIMR3HvDisableTscPage(pVM);
267 pHv->u64TscPageMsr = uRawValue;
268 return VINF_SUCCESS;
269 }
270
271 /* Enable the TSC-page. */
272 RTGCPHYS GCPhysTscPage = MSR_GIM_HV_REF_TSC_GUEST_PFN(uRawValue) << PAGE_SHIFT;
273 int rc = GIMR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence */, 0 /* uTscSequence */);
274 if (RT_SUCCESS(rc))
275 {
276 pHv->u64TscPageMsr = uRawValue;
277 return VINF_SUCCESS;
278 }
279
280 return VERR_CPUM_RAISE_GP_0;
281#endif /* IN_RING3 */
282 }
283
284 case MSR_GIM_HV_RESET:
285 {
286#ifndef IN_RING3
287 return VINF_CPUM_R3_MSR_WRITE;
288#else
289 if (MSR_GIM_HV_RESET_IS_SET(uRawValue))
290 {
291 LogRel(("GIM: HyperV: Reset initiated through MSR.\n"));
292 int rc = PDMDevHlpVMReset(pVM->gim.s.pDevInsR3);
293 AssertRC(rc);
294 }
295 /* else: Ignore writes to other bits. */
296 return VINF_SUCCESS;
297#endif /* IN_RING3 */
298 }
299
300 case MSR_GIM_HV_TIME_REF_COUNT: /* Read-only MSRs. */
301 case MSR_GIM_HV_VP_INDEX:
302 case MSR_GIM_HV_TSC_FREQ:
303 case MSR_GIM_HV_APIC_FREQ:
304 LogFunc(("WrMsr on read-only MSR %#RX32 -> #GP(0)\n", idMsr));
305 return VERR_CPUM_RAISE_GP_0;
306
307 default:
308#ifdef IN_RING3
309 static uint32_t s_cTimes = 0;
310 if (s_cTimes++ < 20)
311 LogRel(("GIM: HyperV: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr, uRawValue & UINT64_C(0xffffffff00000000),
312 uRawValue & UINT64_C(0xffffffff)));
313#endif
314 LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
315 break;
316 }
317
318 return VERR_CPUM_RAISE_GP_0;
319}
320
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