IEMAll.cpp@ 53466

Last change on this file since 53466 was 53466, checked in by vboxsync, 10 years ago
VMM/MSRs: Added status codes for returning to ring-3 to service the MSR access.
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1	/* $Id: IEMAll.cpp 53466 2014-12-05 16:07:33Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager - All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2011-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_iem IEM - Interpreted Execution Manager
20	*
21	* The interpreted exeuction manager (IEM) is for executing short guest code
22	* sequences that are causing too many exits / virtualization traps. It will
23	* also be used to interpret single instructions, thus replacing the selective
24	* interpreters in EM and IOM.
25	*
26	* Design goals:
27	* - Relatively small footprint, although we favour speed and correctness
28	* over size.
29	* - Reasonably fast.
30	* - Correctly handle lock prefixed instructions.
31	* - Complete instruction set - eventually.
32	* - Refactorable into a recompiler, maybe.
33	* - Replace EMInterpret*.
34	*
35	* Using the existing disassembler has been considered, however this is thought
36	* to conflict with speed as the disassembler chews things a bit too much while
37	* leaving us with a somewhat complicated state to interpret afterwards.
38	*
39	*
40	* The current code is very much work in progress. You've been warned!
41	*
42	*
43	* @section sec_iem_fpu_instr FPU Instructions
44	*
45	* On x86 and AMD64 hosts, the FPU instructions are implemented by executing the
46	* same or equivalent instructions on the host FPU. To make life easy, we also
47	* let the FPU prioritize the unmasked exceptions for us. This however, only
48	* works reliably when CR0.NE is set, i.e. when using \#MF instead the IRQ 13
49	* for FPU exception delivery, because with CR0.NE=0 there is a window where we
50	* can trigger spurious FPU exceptions.
51	*
52	* The guest FPU state is not loaded into the host CPU and kept there till we
53	* leave IEM because the calling conventions have declared an all year open
54	* season on much of the FPU state. For instance an innocent looking call to
55	* memcpy might end up using a whole bunch of XMM or MM registers if the
56	* particular implementation finds it worthwhile.
57	*
58	*
59	* @section sec_iem_logging Logging
60	*
61	* The IEM code uses the \"IEM\" log group for the main logging. The different
62	* logging levels/flags are generally used for the following purposes:
63	* - Level 1 (Log) : Errors, exceptions, interrupts and such major events.
64	* - Flow (LogFlow): Basic enter/exit IEM state info.
65	* - Level 2 (Log2): ?
66	* - Level 3 (Log3): More detailed enter/exit IEM state info.
67	* - Level 4 (Log4): Decoding mnemonics w/ EIP.
68	* - Level 5 (Log5): Decoding details.
69	* - Level 6 (Log6): Enables/disables the lockstep comparison with REM.
70	*
71	*/
72
73	/** @def IEM_VERIFICATION_MODE_MINIMAL
74	* Use for pitting IEM against EM or something else in ring-0 or raw-mode
75	* context. */
76	//#define IEM_VERIFICATION_MODE_MINIMAL
77	//#define IEM_LOG_MEMORY_WRITES
78	#define IEM_IMPLEMENTS_TASKSWITCH
79
80	/*******************************************************************************
81	* Header Files *
82	*******************************************************************************/
83	#define LOG_GROUP LOG_GROUP_IEM
84	#include <VBox/vmm/iem.h>
85	#include <VBox/vmm/cpum.h>
86	#include <VBox/vmm/pdm.h>
87	#include <VBox/vmm/pgm.h>
88	#include <internal/pgm.h>
89	#include <VBox/vmm/iom.h>
90	#include <VBox/vmm/em.h>
91	#include <VBox/vmm/hm.h>
92	#include <VBox/vmm/tm.h>
93	#include <VBox/vmm/dbgf.h>
94	#include <VBox/vmm/dbgftrace.h>
95	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
96	# include <VBox/vmm/patm.h>
97	# if defined(VBOX_WITH_CALL_RECORD) \|\| defined(REM_MONITOR_CODE_PAGES)
98	# include <VBox/vmm/csam.h>
99	# endif
100	#endif
101	#include "IEMInternal.h"
102	#ifdef IEM_VERIFICATION_MODE_FULL
103	# include <VBox/vmm/rem.h>
104	# include <VBox/vmm/mm.h>
105	#endif
106	#include <VBox/vmm/vm.h>
107	#include <VBox/log.h>
108	#include <VBox/err.h>
109	#include <VBox/param.h>
110	#include <VBox/dis.h>
111	#include <VBox/disopcode.h>
112	#include <iprt/assert.h>
113	#include <iprt/string.h>
114	#include <iprt/x86.h>
115
116
117
118	/*******************************************************************************
119	* Structures and Typedefs *
120	*******************************************************************************/
121	/** @typedef PFNIEMOP
122	* Pointer to an opcode decoder function.
123	*/
124
125	/** @def FNIEMOP_DEF
126	* Define an opcode decoder function.
127	*
128	* We're using macors for this so that adding and removing parameters as well as
129	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
130	*
131	* @param a_Name The function name.
132	*/
133
134
135	#if defined(__GNUC__) && defined(RT_ARCH_X86)
136	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PIEMCPU pIemCpu);
137	# define FNIEMOP_DEF(a_Name) \
138	static VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PIEMCPU pIemCpu)
139	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
140	static VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0)
141	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
142	static VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0, a_Type1 a_Name1)
143
144	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
145	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PIEMCPU pIemCpu);
146	# define FNIEMOP_DEF(a_Name) \
147	static /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PIEMCPU pIemCpu) RT_NO_THROW
148	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
149	static /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0) RT_NO_THROW
150	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
151	static /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW
152
153	#elif defined(__GNUC__)
154	typedef VBOXSTRICTRC (* PFNIEMOP)(PIEMCPU pIemCpu);
155	# define FNIEMOP_DEF(a_Name) \
156	static VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PIEMCPU pIemCpu)
157	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
158	static VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0)
159	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
160	static VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0, a_Type1 a_Name1)
161
162	#else
163	typedef VBOXSTRICTRC (* PFNIEMOP)(PIEMCPU pIemCpu);
164	# define FNIEMOP_DEF(a_Name) \
165	static VBOXSTRICTRC a_Name(PIEMCPU pIemCpu) RT_NO_THROW
166	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
167	static VBOXSTRICTRC a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0) RT_NO_THROW
168	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
169	static VBOXSTRICTRC a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW
170
171	#endif
172
173
174	/**
175	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
176	*/
177	typedef union IEMSELDESC
178	{
179	/** The legacy view. */
180	X86DESC Legacy;
181	/** The long mode view. */
182	X86DESC64 Long;
183	} IEMSELDESC;
184	/** Pointer to a selector descriptor table entry. */
185	typedef IEMSELDESC *PIEMSELDESC;
186
187
188	/*******************************************************************************
189	* Defined Constants And Macros *
190	*******************************************************************************/
191	/** @name IEM status codes.
192	*
193	* Not quite sure how this will play out in the end, just aliasing safe status
194	* codes for now.
195	*
196	* @{ */
197	#define VINF_IEM_RAISED_XCPT VINF_EM_RESCHEDULE
198	/** @} */
199
200	/** Temporary hack to disable the double execution. Will be removed in favor
201	* of a dedicated execution mode in EM. */
202	//#define IEM_VERIFICATION_MODE_NO_REM
203
204	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
205	* due to GCC lacking knowledge about the value range of a switch. */
206	#define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
207
208	/**
209	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
210	* occation.
211	*/
212	#ifdef LOG_ENABLED
213	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
214	do { \
215	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
216	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
217	} while (0)
218	#else
219	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
220	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
221	#endif
222
223	/**
224	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
225	* occation using the supplied logger statement.
226	*
227	* @param a_LoggerArgs What to log on failure.
228	*/
229	#ifdef LOG_ENABLED
230	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
231	do { \
232	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
233	/LogFunc(a_LoggerArgs);/ \
234	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
235	} while (0)
236	#else
237	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
238	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
239	#endif
240
241	/**
242	* Call an opcode decoder function.
243	*
244	* We're using macors for this so that adding and removing parameters can be
245	* done as we please. See FNIEMOP_DEF.
246	*/
247	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pIemCpu)
248
249	/**
250	* Call a common opcode decoder function taking one extra argument.
251	*
252	* We're using macors for this so that adding and removing parameters can be
253	* done as we please. See FNIEMOP_DEF_1.
254	*/
255	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pIemCpu, a0)
256
257	/**
258	* Call a common opcode decoder function taking one extra argument.
259	*
260	* We're using macors for this so that adding and removing parameters can be
261	* done as we please. See FNIEMOP_DEF_1.
262	*/
263	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pIemCpu, a0, a1)
264
265	/**
266	* Check if we're currently executing in real or virtual 8086 mode.
267	*
268	* @returns @c true if it is, @c false if not.
269	* @param a_pIemCpu The IEM state of the current CPU.
270	*/
271	#define IEM_IS_REAL_OR_V86_MODE(a_pIemCpu) (CPUMIsGuestInRealOrV86ModeEx((a_pIemCpu)->CTX_SUFF(pCtx)))
272
273	/**
274	* Check if we're currently executing in virtual 8086 mode.
275	*
276	* @returns @c true if it is, @c false if not.
277	* @param a_pIemCpu The IEM state of the current CPU.
278	*/
279	#define IEM_IS_V86_MODE(a_pIemCpu) (CPUMIsGuestInV86ModeEx((a_pIemCpu)->CTX_SUFF(pCtx)))
280
281	/**
282	* Check if we're currently executing in long mode.
283	*
284	* @returns @c true if it is, @c false if not.
285	* @param a_pIemCpu The IEM state of the current CPU.
286	*/
287	#define IEM_IS_LONG_MODE(a_pIemCpu) (CPUMIsGuestInLongModeEx((a_pIemCpu)->CTX_SUFF(pCtx)))
288
289	/**
290	* Check if we're currently executing in real mode.
291	*
292	* @returns @c true if it is, @c false if not.
293	* @param a_pIemCpu The IEM state of the current CPU.
294	*/
295	#define IEM_IS_REAL_MODE(a_pIemCpu) (CPUMIsGuestInRealModeEx((a_pIemCpu)->CTX_SUFF(pCtx)))
296
297	/**
298	* Tests if an AMD CPUID feature (extended) is marked present - ECX.
299	*/
300	#define IEM_IS_AMD_CPUID_FEATURE_PRESENT_ECX(a_fEcx) iemRegIsAmdCpuIdFeaturePresent(pIemCpu, 0, (a_fEcx))
301
302	/**
303	* Tests if an AMD CPUID feature (extended) is marked present - EDX.
304	*/
305	#define IEM_IS_AMD_CPUID_FEATURE_PRESENT_EDX(a_fEdx) iemRegIsAmdCpuIdFeaturePresent(pIemCpu, (a_fEdx), 0)
306
307	/**
308	* Tests if at least on of the specified AMD CPUID features (extended) are
309	* marked present.
310	*/
311	#define IEM_IS_AMD_CPUID_FEATURES_ANY_PRESENT(a_fEdx, a_fEcx) iemRegIsAmdCpuIdFeaturePresent(pIemCpu, (a_fEdx), (a_fEcx))
312
313	/**
314	* Checks if an Intel CPUID feature is present.
315	*/
316	#define IEM_IS_INTEL_CPUID_FEATURE_PRESENT_EDX(a_fEdx) \
317	( ((a_fEdx) & (X86_CPUID_FEATURE_EDX_TSC \| 0)) \
318	\|\| iemRegIsIntelCpuIdFeaturePresent(pIemCpu, (a_fEdx), 0) )
319
320	/**
321	* Checks if an Intel CPUID feature is present.
322	*/
323	#define IEM_IS_INTEL_CPUID_FEATURE_PRESENT_ECX(a_fEcx) \
324	( iemRegIsIntelCpuIdFeaturePresent(pIemCpu, 0, (a_fEcx)) )
325
326	/**
327	* Checks if an Intel CPUID feature is present in the host CPU.
328	*/
329	#define IEM_IS_INTEL_CPUID_FEATURE_PRESENT_EDX_ON_HOST(a_fEdx) \
330	( (a_fEdx) & pIemCpu->fHostCpuIdStdFeaturesEdx )
331
332	/**
333	* Evaluates to true if we're presenting an Intel CPU to the guest.
334	*/
335	#define IEM_IS_GUEST_CPU_INTEL(a_pIemCpu) ( (a_pIemCpu)->enmCpuVendor == CPUMCPUVENDOR_INTEL )
336
337	/**
338	* Evaluates to true if we're presenting an AMD CPU to the guest.
339	*/
340	#define IEM_IS_GUEST_CPU_AMD(a_pIemCpu) ( (a_pIemCpu)->enmCpuVendor == CPUMCPUVENDOR_AMD )
341
342	/**
343	* Check if the address is canonical.
344	*/
345	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
346
347
348	/*******************************************************************************
349	* Global Variables *
350	*******************************************************************************/
351	extern const PFNIEMOP g_apfnOneByteMap[256]; /* not static since we need to forward declare it. */
352
353
354	/** Function table for the ADD instruction. */
355	static const IEMOPBINSIZES g_iemAImpl_add =
356	{
357	iemAImpl_add_u8, iemAImpl_add_u8_locked,
358	iemAImpl_add_u16, iemAImpl_add_u16_locked,
359	iemAImpl_add_u32, iemAImpl_add_u32_locked,
360	iemAImpl_add_u64, iemAImpl_add_u64_locked
361	};
362
363	/** Function table for the ADC instruction. */
364	static const IEMOPBINSIZES g_iemAImpl_adc =
365	{
366	iemAImpl_adc_u8, iemAImpl_adc_u8_locked,
367	iemAImpl_adc_u16, iemAImpl_adc_u16_locked,
368	iemAImpl_adc_u32, iemAImpl_adc_u32_locked,
369	iemAImpl_adc_u64, iemAImpl_adc_u64_locked
370	};
371
372	/** Function table for the SUB instruction. */
373	static const IEMOPBINSIZES g_iemAImpl_sub =
374	{
375	iemAImpl_sub_u8, iemAImpl_sub_u8_locked,
376	iemAImpl_sub_u16, iemAImpl_sub_u16_locked,
377	iemAImpl_sub_u32, iemAImpl_sub_u32_locked,
378	iemAImpl_sub_u64, iemAImpl_sub_u64_locked
379	};
380
381	/** Function table for the SBB instruction. */
382	static const IEMOPBINSIZES g_iemAImpl_sbb =
383	{
384	iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked,
385	iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked,
386	iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked,
387	iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked
388	};
389
390	/** Function table for the OR instruction. */
391	static const IEMOPBINSIZES g_iemAImpl_or =
392	{
393	iemAImpl_or_u8, iemAImpl_or_u8_locked,
394	iemAImpl_or_u16, iemAImpl_or_u16_locked,
395	iemAImpl_or_u32, iemAImpl_or_u32_locked,
396	iemAImpl_or_u64, iemAImpl_or_u64_locked
397	};
398
399	/** Function table for the XOR instruction. */
400	static const IEMOPBINSIZES g_iemAImpl_xor =
401	{
402	iemAImpl_xor_u8, iemAImpl_xor_u8_locked,
403	iemAImpl_xor_u16, iemAImpl_xor_u16_locked,
404	iemAImpl_xor_u32, iemAImpl_xor_u32_locked,
405	iemAImpl_xor_u64, iemAImpl_xor_u64_locked
406	};
407
408	/** Function table for the AND instruction. */
409	static const IEMOPBINSIZES g_iemAImpl_and =
410	{
411	iemAImpl_and_u8, iemAImpl_and_u8_locked,
412	iemAImpl_and_u16, iemAImpl_and_u16_locked,
413	iemAImpl_and_u32, iemAImpl_and_u32_locked,
414	iemAImpl_and_u64, iemAImpl_and_u64_locked
415	};
416
417	/** Function table for the CMP instruction.
418	* @remarks Making operand order ASSUMPTIONS.
419	*/
420	static const IEMOPBINSIZES g_iemAImpl_cmp =
421	{
422	iemAImpl_cmp_u8, NULL,
423	iemAImpl_cmp_u16, NULL,
424	iemAImpl_cmp_u32, NULL,
425	iemAImpl_cmp_u64, NULL
426	};
427
428	/** Function table for the TEST instruction.
429	* @remarks Making operand order ASSUMPTIONS.
430	*/
431	static const IEMOPBINSIZES g_iemAImpl_test =
432	{
433	iemAImpl_test_u8, NULL,
434	iemAImpl_test_u16, NULL,
435	iemAImpl_test_u32, NULL,
436	iemAImpl_test_u64, NULL
437	};
438
439	/** Function table for the BT instruction. */
440	static const IEMOPBINSIZES g_iemAImpl_bt =
441	{
442	NULL, NULL,
443	iemAImpl_bt_u16, NULL,
444	iemAImpl_bt_u32, NULL,
445	iemAImpl_bt_u64, NULL
446	};
447
448	/** Function table for the BTC instruction. */
449	static const IEMOPBINSIZES g_iemAImpl_btc =
450	{
451	NULL, NULL,
452	iemAImpl_btc_u16, iemAImpl_btc_u16_locked,
453	iemAImpl_btc_u32, iemAImpl_btc_u32_locked,
454	iemAImpl_btc_u64, iemAImpl_btc_u64_locked
455	};
456
457	/** Function table for the BTR instruction. */
458	static const IEMOPBINSIZES g_iemAImpl_btr =
459	{
460	NULL, NULL,
461	iemAImpl_btr_u16, iemAImpl_btr_u16_locked,
462	iemAImpl_btr_u32, iemAImpl_btr_u32_locked,
463	iemAImpl_btr_u64, iemAImpl_btr_u64_locked
464	};
465
466	/** Function table for the BTS instruction. */
467	static const IEMOPBINSIZES g_iemAImpl_bts =
468	{
469	NULL, NULL,
470	iemAImpl_bts_u16, iemAImpl_bts_u16_locked,
471	iemAImpl_bts_u32, iemAImpl_bts_u32_locked,
472	iemAImpl_bts_u64, iemAImpl_bts_u64_locked
473	};
474
475	/** Function table for the BSF instruction. */
476	static const IEMOPBINSIZES g_iemAImpl_bsf =
477	{
478	NULL, NULL,
479	iemAImpl_bsf_u16, NULL,
480	iemAImpl_bsf_u32, NULL,
481	iemAImpl_bsf_u64, NULL
482	};
483
484	/** Function table for the BSR instruction. */
485	static const IEMOPBINSIZES g_iemAImpl_bsr =
486	{
487	NULL, NULL,
488	iemAImpl_bsr_u16, NULL,
489	iemAImpl_bsr_u32, NULL,
490	iemAImpl_bsr_u64, NULL
491	};
492
493	/** Function table for the IMUL instruction. */
494	static const IEMOPBINSIZES g_iemAImpl_imul_two =
495	{
496	NULL, NULL,
497	iemAImpl_imul_two_u16, NULL,
498	iemAImpl_imul_two_u32, NULL,
499	iemAImpl_imul_two_u64, NULL
500	};
501
502	/** Group 1 /r lookup table. */
503	static const PCIEMOPBINSIZES g_apIemImplGrp1[8] =
504	{
505	&g_iemAImpl_add,
506	&g_iemAImpl_or,
507	&g_iemAImpl_adc,
508	&g_iemAImpl_sbb,
509	&g_iemAImpl_and,
510	&g_iemAImpl_sub,
511	&g_iemAImpl_xor,
512	&g_iemAImpl_cmp
513	};
514
515	/** Function table for the INC instruction. */
516	static const IEMOPUNARYSIZES g_iemAImpl_inc =
517	{
518	iemAImpl_inc_u8, iemAImpl_inc_u8_locked,
519	iemAImpl_inc_u16, iemAImpl_inc_u16_locked,
520	iemAImpl_inc_u32, iemAImpl_inc_u32_locked,
521	iemAImpl_inc_u64, iemAImpl_inc_u64_locked
522	};
523
524	/** Function table for the DEC instruction. */
525	static const IEMOPUNARYSIZES g_iemAImpl_dec =
526	{
527	iemAImpl_dec_u8, iemAImpl_dec_u8_locked,
528	iemAImpl_dec_u16, iemAImpl_dec_u16_locked,
529	iemAImpl_dec_u32, iemAImpl_dec_u32_locked,
530	iemAImpl_dec_u64, iemAImpl_dec_u64_locked
531	};
532
533	/** Function table for the NEG instruction. */
534	static const IEMOPUNARYSIZES g_iemAImpl_neg =
535	{
536	iemAImpl_neg_u8, iemAImpl_neg_u8_locked,
537	iemAImpl_neg_u16, iemAImpl_neg_u16_locked,
538	iemAImpl_neg_u32, iemAImpl_neg_u32_locked,
539	iemAImpl_neg_u64, iemAImpl_neg_u64_locked
540	};
541
542	/** Function table for the NOT instruction. */
543	static const IEMOPUNARYSIZES g_iemAImpl_not =
544	{
545	iemAImpl_not_u8, iemAImpl_not_u8_locked,
546	iemAImpl_not_u16, iemAImpl_not_u16_locked,
547	iemAImpl_not_u32, iemAImpl_not_u32_locked,
548	iemAImpl_not_u64, iemAImpl_not_u64_locked
549	};
550
551
552	/** Function table for the ROL instruction. */
553	static const IEMOPSHIFTSIZES g_iemAImpl_rol =
554	{
555	iemAImpl_rol_u8,
556	iemAImpl_rol_u16,
557	iemAImpl_rol_u32,
558	iemAImpl_rol_u64
559	};
560
561	/** Function table for the ROR instruction. */
562	static const IEMOPSHIFTSIZES g_iemAImpl_ror =
563	{
564	iemAImpl_ror_u8,
565	iemAImpl_ror_u16,
566	iemAImpl_ror_u32,
567	iemAImpl_ror_u64
568	};
569
570	/** Function table for the RCL instruction. */
571	static const IEMOPSHIFTSIZES g_iemAImpl_rcl =
572	{
573	iemAImpl_rcl_u8,
574	iemAImpl_rcl_u16,
575	iemAImpl_rcl_u32,
576	iemAImpl_rcl_u64
577	};
578
579	/** Function table for the RCR instruction. */
580	static const IEMOPSHIFTSIZES g_iemAImpl_rcr =
581	{
582	iemAImpl_rcr_u8,
583	iemAImpl_rcr_u16,
584	iemAImpl_rcr_u32,
585	iemAImpl_rcr_u64
586	};
587
588	/** Function table for the SHL instruction. */
589	static const IEMOPSHIFTSIZES g_iemAImpl_shl =
590	{
591	iemAImpl_shl_u8,
592	iemAImpl_shl_u16,
593	iemAImpl_shl_u32,
594	iemAImpl_shl_u64
595	};
596
597	/** Function table for the SHR instruction. */
598	static const IEMOPSHIFTSIZES g_iemAImpl_shr =
599	{
600	iemAImpl_shr_u8,
601	iemAImpl_shr_u16,
602	iemAImpl_shr_u32,
603	iemAImpl_shr_u64
604	};
605
606	/** Function table for the SAR instruction. */
607	static const IEMOPSHIFTSIZES g_iemAImpl_sar =
608	{
609	iemAImpl_sar_u8,
610	iemAImpl_sar_u16,
611	iemAImpl_sar_u32,
612	iemAImpl_sar_u64
613	};
614
615
616	/** Function table for the MUL instruction. */
617	static const IEMOPMULDIVSIZES g_iemAImpl_mul =
618	{
619	iemAImpl_mul_u8,
620	iemAImpl_mul_u16,
621	iemAImpl_mul_u32,
622	iemAImpl_mul_u64
623	};
624
625	/** Function table for the IMUL instruction working implicitly on rAX. */
626	static const IEMOPMULDIVSIZES g_iemAImpl_imul =
627	{
628	iemAImpl_imul_u8,
629	iemAImpl_imul_u16,
630	iemAImpl_imul_u32,
631	iemAImpl_imul_u64
632	};
633
634	/** Function table for the DIV instruction. */
635	static const IEMOPMULDIVSIZES g_iemAImpl_div =
636	{
637	iemAImpl_div_u8,
638	iemAImpl_div_u16,
639	iemAImpl_div_u32,
640	iemAImpl_div_u64
641	};
642
643	/** Function table for the MUL instruction. */
644	static const IEMOPMULDIVSIZES g_iemAImpl_idiv =
645	{
646	iemAImpl_idiv_u8,
647	iemAImpl_idiv_u16,
648	iemAImpl_idiv_u32,
649	iemAImpl_idiv_u64
650	};
651
652	/** Function table for the SHLD instruction */
653	static const IEMOPSHIFTDBLSIZES g_iemAImpl_shld =
654	{
655	iemAImpl_shld_u16,
656	iemAImpl_shld_u32,
657	iemAImpl_shld_u64,
658	};
659
660	/** Function table for the SHRD instruction */
661	static const IEMOPSHIFTDBLSIZES g_iemAImpl_shrd =
662	{
663	iemAImpl_shrd_u16,
664	iemAImpl_shrd_u32,
665	iemAImpl_shrd_u64,
666	};
667
668
669	/** Function table for the PUNPCKLBW instruction */
670	static const IEMOPMEDIAF1L1 g_iemAImpl_punpcklbw = { iemAImpl_punpcklbw_u64, iemAImpl_punpcklbw_u128 };
671	/** Function table for the PUNPCKLBD instruction */
672	static const IEMOPMEDIAF1L1 g_iemAImpl_punpcklwd = { iemAImpl_punpcklwd_u64, iemAImpl_punpcklwd_u128 };
673	/** Function table for the PUNPCKLDQ instruction */
674	static const IEMOPMEDIAF1L1 g_iemAImpl_punpckldq = { iemAImpl_punpckldq_u64, iemAImpl_punpckldq_u128 };
675	/** Function table for the PUNPCKLQDQ instruction */
676	static const IEMOPMEDIAF1L1 g_iemAImpl_punpcklqdq = { NULL, iemAImpl_punpcklqdq_u128 };
677
678	/** Function table for the PUNPCKHBW instruction */
679	static const IEMOPMEDIAF1H1 g_iemAImpl_punpckhbw = { iemAImpl_punpckhbw_u64, iemAImpl_punpckhbw_u128 };
680	/** Function table for the PUNPCKHBD instruction */
681	static const IEMOPMEDIAF1H1 g_iemAImpl_punpckhwd = { iemAImpl_punpckhwd_u64, iemAImpl_punpckhwd_u128 };
682	/** Function table for the PUNPCKHDQ instruction */
683	static const IEMOPMEDIAF1H1 g_iemAImpl_punpckhdq = { iemAImpl_punpckhdq_u64, iemAImpl_punpckhdq_u128 };
684	/** Function table for the PUNPCKHQDQ instruction */
685	static const IEMOPMEDIAF1H1 g_iemAImpl_punpckhqdq = { NULL, iemAImpl_punpckhqdq_u128 };
686
687	/** Function table for the PXOR instruction */
688	static const IEMOPMEDIAF2 g_iemAImpl_pxor = { iemAImpl_pxor_u64, iemAImpl_pxor_u128 };
689	/** Function table for the PCMPEQB instruction */
690	static const IEMOPMEDIAF2 g_iemAImpl_pcmpeqb = { iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqb_u128 };
691	/** Function table for the PCMPEQW instruction */
692	static const IEMOPMEDIAF2 g_iemAImpl_pcmpeqw = { iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqw_u128 };
693	/** Function table for the PCMPEQD instruction */
694	static const IEMOPMEDIAF2 g_iemAImpl_pcmpeqd = { iemAImpl_pcmpeqd_u64, iemAImpl_pcmpeqd_u128 };
695
696
697	#if defined(IEM_VERIFICATION_MODE_MINIMAL) \|\| defined(IEM_LOG_MEMORY_WRITES)
698	/** What IEM just wrote. */
699	uint8_t g_abIemWrote[256];
700	/** How much IEM just wrote. */
701	size_t g_cbIemWrote;
702	#endif
703
704
705	/*******************************************************************************
706	* Internal Functions *
707	*******************************************************************************/
708	static VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PIEMCPU pIemCpu, uint16_t uErr);
709	static VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PIEMCPU pIemCpu);
710	static VBOXSTRICTRC iemRaiseTaskSwitchFault0(PIEMCPU pIemCpu);
711	static VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PIEMCPU pIemCpu, uint16_t uSel);
712	/static VBOXSTRICTRC iemRaiseSelectorNotPresent(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess);/
713	static VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel);
714	static VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr);
715	static VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel);
716	static VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr);
717	static VBOXSTRICTRC iemRaiseGeneralProtectionFault(PIEMCPU pIemCpu, uint16_t uErr);
718	static VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PIEMCPU pIemCpu);
719	static VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PIEMCPU pIemCpu, RTSEL uSel);
720	static VBOXSTRICTRC iemRaiseSelectorBounds(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess);
721	static VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PIEMCPU pIemCpu, RTSEL Sel);
722	static VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess);
723	static VBOXSTRICTRC iemRaisePageFault(PIEMCPU pIemCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc);
724	static VBOXSTRICTRC iemRaiseAlignmentCheckException(PIEMCPU pIemCpu);
725	static VBOXSTRICTRC iemMemMap(PIEMCPU pIemCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t fAccess);
726	static VBOXSTRICTRC iemMemCommitAndUnmap(PIEMCPU pIemCpu, void *pvMem, uint32_t fAccess);
727	static VBOXSTRICTRC iemMemFetchDataU32(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem);
728	static VBOXSTRICTRC iemMemFetchDataU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem);
729	static VBOXSTRICTRC iemMemFetchSysU8(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem);
730	static VBOXSTRICTRC iemMemFetchSysU16(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem);
731	static VBOXSTRICTRC iemMemFetchSysU32(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem);
732	static VBOXSTRICTRC iemMemFetchSysU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem);
733	static VBOXSTRICTRC iemMemFetchSelDescWithErr(PIEMCPU pIemCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt, uint16_t uErrorCode);
734	static VBOXSTRICTRC iemMemFetchSelDesc(PIEMCPU pIemCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt);
735	static VBOXSTRICTRC iemMemStackPushCommitSpecial(PIEMCPU pIemCpu, void *pvMem, uint64_t uNewRsp);
736	static VBOXSTRICTRC iemMemStackPushBeginSpecial(PIEMCPU pIemCpu, size_t cbMem, void *ppvMem, uint64_t puNewRsp);
737	static VBOXSTRICTRC iemMemStackPushU32(PIEMCPU pIemCpu, uint32_t u32Value);
738	static VBOXSTRICTRC iemMemStackPushU16(PIEMCPU pIemCpu, uint16_t u16Value);
739	static VBOXSTRICTRC iemMemMarkSelDescAccessed(PIEMCPU pIemCpu, uint16_t uSel);
740	static uint16_t iemSRegFetchU16(PIEMCPU pIemCpu, uint8_t iSegReg);
741
742	#if defined(IEM_VERIFICATION_MODE_FULL) && !defined(IEM_VERIFICATION_MODE_MINIMAL)
743	static PIEMVERIFYEVTREC iemVerifyAllocRecord(PIEMCPU pIemCpu);
744	#endif
745	static VBOXSTRICTRC iemVerifyFakeIOPortRead(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue);
746	static VBOXSTRICTRC iemVerifyFakeIOPortWrite(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue);
747
748
749
750	/**
751	* Sets the pass up status.
752	*
753	* @returns VINF_SUCCESS.
754	* @param pIemCpu The per CPU IEM state of the calling thread.
755	* @param rcPassUp The pass up status. Must be informational.
756	* VINF_SUCCESS is not allowed.
757	*/
758	static int iemSetPassUpStatus(PIEMCPU pIemCpu, VBOXSTRICTRC rcPassUp)
759	{
760	AssertRC(VBOXSTRICTRC_VAL(rcPassUp)); Assert(rcPassUp != VINF_SUCCESS);
761
762	int32_t const rcOldPassUp = pIemCpu->rcPassUp;
763	if (rcOldPassUp == VINF_SUCCESS)
764	pIemCpu->rcPassUp = VBOXSTRICTRC_VAL(rcPassUp);
765	/* If both are EM scheduling codes, use EM priority rules. */
766	else if ( rcOldPassUp >= VINF_EM_FIRST && rcOldPassUp <= VINF_EM_LAST
767	&& rcPassUp >= VINF_EM_FIRST && rcPassUp <= VINF_EM_LAST)
768	{
769	if (rcPassUp < rcOldPassUp)
770	{
771	Log(("IEM: rcPassUp=%Rrc! rcOldPassUp=%Rrc\n", VBOXSTRICTRC_VAL(rcPassUp), rcOldPassUp));
772	pIemCpu->rcPassUp = VBOXSTRICTRC_VAL(rcPassUp);
773	}
774	else
775	Log(("IEM: rcPassUp=%Rrc rcOldPassUp=%Rrc!\n", VBOXSTRICTRC_VAL(rcPassUp), rcOldPassUp));
776	}
777	/* Override EM scheduling with specific status code. */
778	else if (rcOldPassUp >= VINF_EM_FIRST && rcOldPassUp <= VINF_EM_LAST)
779	{
780	Log(("IEM: rcPassUp=%Rrc! rcOldPassUp=%Rrc\n", VBOXSTRICTRC_VAL(rcPassUp), rcOldPassUp));
781	pIemCpu->rcPassUp = VBOXSTRICTRC_VAL(rcPassUp);
782	}
783	/* Don't override specific status code, first come first served. */
784	else
785	Log(("IEM: rcPassUp=%Rrc rcOldPassUp=%Rrc!\n", VBOXSTRICTRC_VAL(rcPassUp), rcOldPassUp));
786	return VINF_SUCCESS;
787	}
788
789
790	/**
791	* Initializes the execution state.
792	*
793	* @param pIemCpu The per CPU IEM state.
794	* @param fBypassHandlers Whether to bypass access handlers.
795	*/
796	DECLINLINE(void) iemInitExec(PIEMCPU pIemCpu, bool fBypassHandlers)
797	{
798	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
799	PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu);
800
801	#if defined(VBOX_STRICT) && (defined(IEM_VERIFICATION_MODE_FULL) \|\| !defined(VBOX_WITH_RAW_MODE_NOT_R0))
802	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs));
803	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ss));
804	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->es));
805	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ds));
806	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->fs));
807	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->gs));
808	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ldtr));
809	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->tr));
810	#endif
811
812	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
813	CPUMGuestLazyLoadHiddenCsAndSs(pVCpu);
814	#endif
815	pIemCpu->uCpl = CPUMGetGuestCPL(pVCpu);
816	IEMMODE enmMode = CPUMIsGuestIn64BitCodeEx(pCtx)
817	? IEMMODE_64BIT
818	: pCtx->cs.Attr.n.u1DefBig /** @todo check if this is correct... */
819	? IEMMODE_32BIT
820	: IEMMODE_16BIT;
821	pIemCpu->enmCpuMode = enmMode;
822	#ifdef VBOX_STRICT
823	pIemCpu->enmDefAddrMode = (IEMMODE)0xc0fe;
824	pIemCpu->enmEffAddrMode = (IEMMODE)0xc0fe;
825	pIemCpu->enmDefOpSize = (IEMMODE)0xc0fe;
826	pIemCpu->enmEffOpSize = (IEMMODE)0xc0fe;
827	pIemCpu->fPrefixes = (IEMMODE)0xfeedbeef;
828	pIemCpu->uRexReg = 127;
829	pIemCpu->uRexB = 127;
830	pIemCpu->uRexIndex = 127;
831	pIemCpu->iEffSeg = 127;
832	pIemCpu->offOpcode = 127;
833	pIemCpu->cbOpcode = 127;
834	#endif
835
836	pIemCpu->cActiveMappings = 0;
837	pIemCpu->iNextMapping = 0;
838	pIemCpu->rcPassUp = VINF_SUCCESS;
839	pIemCpu->fBypassHandlers = fBypassHandlers;
840	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
841	pIemCpu->fInPatchCode = pIemCpu->uCpl == 0
842	&& pCtx->cs.u64Base == 0
843	&& pCtx->cs.u32Limit == UINT32_MAX
844	&& PATMIsPatchGCAddr(IEMCPU_TO_VM(pIemCpu), pCtx->eip);
845	if (!pIemCpu->fInPatchCode)
846	CPUMRawLeave(pVCpu, CPUMCTX2CORE(pCtx), VINF_SUCCESS);
847	#endif
848	}
849
850
851	/**
852	* Initializes the decoder state.
853	*
854	* @param pIemCpu The per CPU IEM state.
855	* @param fBypassHandlers Whether to bypass access handlers.
856	*/
857	DECLINLINE(void) iemInitDecoder(PIEMCPU pIemCpu, bool fBypassHandlers)
858	{
859	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
860	PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu);
861
862	#if defined(VBOX_STRICT) && (defined(IEM_VERIFICATION_MODE_FULL) \|\| !defined(VBOX_WITH_RAW_MODE_NOT_R0))
863	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs));
864	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ss));
865	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->es));
866	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ds));
867	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->fs));
868	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->gs));
869	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ldtr));
870	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->tr));
871	#endif
872
873	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
874	CPUMGuestLazyLoadHiddenCsAndSs(pVCpu);
875	#endif
876	pIemCpu->uCpl = CPUMGetGuestCPL(pVCpu);
877	#ifdef IEM_VERIFICATION_MODE_FULL
878	if (pIemCpu->uInjectCpl != UINT8_MAX)
879	pIemCpu->uCpl = pIemCpu->uInjectCpl;
880	#endif
881	IEMMODE enmMode = CPUMIsGuestIn64BitCodeEx(pCtx)
882	? IEMMODE_64BIT
883	: pCtx->cs.Attr.n.u1DefBig /** @todo check if this is correct... */
884	? IEMMODE_32BIT
885	: IEMMODE_16BIT;
886	pIemCpu->enmCpuMode = enmMode;
887	pIemCpu->enmDefAddrMode = enmMode; /** @todo check if this is correct... */
888	pIemCpu->enmEffAddrMode = enmMode;
889	if (enmMode != IEMMODE_64BIT)
890	{
891	pIemCpu->enmDefOpSize = enmMode; /** @todo check if this is correct... */
892	pIemCpu->enmEffOpSize = enmMode;
893	}
894	else
895	{
896	pIemCpu->enmDefOpSize = IEMMODE_32BIT;
897	pIemCpu->enmEffOpSize = IEMMODE_32BIT;
898	}
899	pIemCpu->fPrefixes = 0;
900	pIemCpu->uRexReg = 0;
901	pIemCpu->uRexB = 0;
902	pIemCpu->uRexIndex = 0;
903	pIemCpu->iEffSeg = X86_SREG_DS;
904	pIemCpu->offOpcode = 0;
905	pIemCpu->cbOpcode = 0;
906	pIemCpu->cActiveMappings = 0;
907	pIemCpu->iNextMapping = 0;
908	pIemCpu->rcPassUp = VINF_SUCCESS;
909	pIemCpu->fBypassHandlers = fBypassHandlers;
910	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
911	pIemCpu->fInPatchCode = pIemCpu->uCpl == 0
912	&& pCtx->cs.u64Base == 0
913	&& pCtx->cs.u32Limit == UINT32_MAX
914	&& PATMIsPatchGCAddr(IEMCPU_TO_VM(pIemCpu), pCtx->eip);
915	if (!pIemCpu->fInPatchCode)
916	CPUMRawLeave(pVCpu, CPUMCTX2CORE(pCtx), VINF_SUCCESS);
917	#endif
918
919	#ifdef DBGFTRACE_ENABLED
920	switch (enmMode)
921	{
922	case IEMMODE_64BIT:
923	RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "I64/%u %08llx", pIemCpu->uCpl, pCtx->rip);
924	break;
925	case IEMMODE_32BIT:
926	RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "I32/%u %04x:%08x", pIemCpu->uCpl, pCtx->cs.Sel, pCtx->eip);
927	break;
928	case IEMMODE_16BIT:
929	RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "I16/%u %04x:%04x", pIemCpu->uCpl, pCtx->cs.Sel, pCtx->eip);
930	break;
931	}
932	#endif
933	}
934
935
936	/**
937	* Prefetch opcodes the first time when starting executing.
938	*
939	* @returns Strict VBox status code.
940	* @param pIemCpu The IEM state.
941	* @param fBypassHandlers Whether to bypass access handlers.
942	*/
943	static VBOXSTRICTRC iemInitDecoderAndPrefetchOpcodes(PIEMCPU pIemCpu, bool fBypassHandlers)
944	{
945	#ifdef IEM_VERIFICATION_MODE_FULL
946	uint8_t const cbOldOpcodes = pIemCpu->cbOpcode;
947	#endif
948	iemInitDecoder(pIemCpu, fBypassHandlers);
949
950	/*
951	* What we're doing here is very similar to iemMemMap/iemMemBounceBufferMap.
952	*
953	* First translate CS:rIP to a physical address.
954	*/
955	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
956	uint32_t cbToTryRead;
957	RTGCPTR GCPtrPC;
958	if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
959	{
960	cbToTryRead = PAGE_SIZE;
961	GCPtrPC = pCtx->rip;
962	if (!IEM_IS_CANONICAL(GCPtrPC))
963	return iemRaiseGeneralProtectionFault0(pIemCpu);
964	cbToTryRead = PAGE_SIZE - (GCPtrPC & PAGE_OFFSET_MASK);
965	}
966	else
967	{
968	uint32_t GCPtrPC32 = pCtx->eip;
969	AssertMsg(!(GCPtrPC32 & ~(uint32_t)UINT16_MAX) \|\| pIemCpu->enmCpuMode == IEMMODE_32BIT, ("%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip));
970	if (GCPtrPC32 > pCtx->cs.u32Limit)
971	return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
972	cbToTryRead = pCtx->cs.u32Limit - GCPtrPC32 + 1;
973	if (!cbToTryRead) /* overflowed */
974	{
975	Assert(GCPtrPC32 == 0); Assert(pCtx->cs.u32Limit == UINT32_MAX);
976	cbToTryRead = UINT32_MAX;
977	}
978	GCPtrPC = (uint32_t)pCtx->cs.u64Base + GCPtrPC32;
979	Assert(GCPtrPC <= UINT32_MAX);
980	}
981
982	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
983	/* Allow interpretation of patch manager code blocks since they can for
984	instance throw #PFs for perfectly good reasons. */
985	if (pIemCpu->fInPatchCode)
986	{
987	size_t cbRead = 0;
988	int rc = PATMReadPatchCode(IEMCPU_TO_VM(pIemCpu), GCPtrPC, pIemCpu->abOpcode, sizeof(pIemCpu->abOpcode), &cbRead);
989	AssertRCReturn(rc, rc);
990	pIemCpu->cbOpcode = (uint8_t)cbRead; Assert(pIemCpu->cbOpcode == cbRead); Assert(cbRead > 0);
991	return VINF_SUCCESS;
992	}
993	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
994
995	RTGCPHYS GCPhys;
996	uint64_t fFlags;
997	int rc = PGMGstGetPage(IEMCPU_TO_VMCPU(pIemCpu), GCPtrPC, &fFlags, &GCPhys);
998	if (RT_FAILURE(rc))
999	{
1000	Log(("iemInitDecoderAndPrefetchOpcodes: %RGv - rc=%Rrc\n", GCPtrPC, rc));
1001	return iemRaisePageFault(pIemCpu, GCPtrPC, IEM_ACCESS_INSTRUCTION, rc);
1002	}
1003	if (!(fFlags & X86_PTE_US) && pIemCpu->uCpl == 3)
1004	{
1005	Log(("iemInitDecoderAndPrefetchOpcodes: %RGv - supervisor page\n", GCPtrPC));
1006	return iemRaisePageFault(pIemCpu, GCPtrPC, IEM_ACCESS_INSTRUCTION, VERR_ACCESS_DENIED);
1007	}
1008	if ((fFlags & X86_PTE_PAE_NX) && (pCtx->msrEFER & MSR_K6_EFER_NXE))
1009	{
1010	Log(("iemInitDecoderAndPrefetchOpcodes: %RGv - NX\n", GCPtrPC));
1011	return iemRaisePageFault(pIemCpu, GCPtrPC, IEM_ACCESS_INSTRUCTION, VERR_ACCESS_DENIED);
1012	}
1013	GCPhys \|= GCPtrPC & PAGE_OFFSET_MASK;
1014	/** @todo Check reserved bits and such stuff. PGM is better at doing
1015	* that, so do it when implementing the guest virtual address
1016	* TLB... */
1017
1018	#ifdef IEM_VERIFICATION_MODE_FULL
1019	/*
1020	* Optimistic optimization: Use unconsumed opcode bytes from the previous
1021	* instruction.
1022	*/
1023	/** @todo optimize this differently by not using PGMPhysRead. */
1024	RTGCPHYS const offPrevOpcodes = GCPhys - pIemCpu->GCPhysOpcodes;
1025	pIemCpu->GCPhysOpcodes = GCPhys;
1026	if ( offPrevOpcodes < cbOldOpcodes
1027	&& PAGE_SIZE - (GCPhys & PAGE_OFFSET_MASK) > sizeof(pIemCpu->abOpcode))
1028	{
1029	uint8_t cbNew = cbOldOpcodes - (uint8_t)offPrevOpcodes;
1030	memmove(&pIemCpu->abOpcode[0], &pIemCpu->abOpcode[offPrevOpcodes], cbNew);
1031	pIemCpu->cbOpcode = cbNew;
1032	return VINF_SUCCESS;
1033	}
1034	#endif
1035
1036	/*
1037	* Read the bytes at this address.
1038	*/
1039	PVM pVM = IEMCPU_TO_VM(pIemCpu);
1040	#if defined(IN_RING3) && defined(VBOX_WITH_RAW_MODE_NOT_R0)
1041	size_t cbActual;
1042	if ( PATMIsEnabled(pVM)
1043	&& RT_SUCCESS(PATMR3ReadOrgInstr(pVM, GCPtrPC, pIemCpu->abOpcode, sizeof(pIemCpu->abOpcode), &cbActual)))
1044	{
1045	Log4(("decode - Read %u unpatched bytes at %RGv\n", cbActual, GCPtrPC));
1046	Assert(cbActual > 0);
1047	pIemCpu->cbOpcode = (uint8_t)cbActual;
1048	}
1049	else
1050	#endif
1051	{
1052	uint32_t cbLeftOnPage = PAGE_SIZE - (GCPtrPC & PAGE_OFFSET_MASK);
1053	if (cbToTryRead > cbLeftOnPage)
1054	cbToTryRead = cbLeftOnPage;
1055	if (cbToTryRead > sizeof(pIemCpu->abOpcode))
1056	cbToTryRead = sizeof(pIemCpu->abOpcode);
1057
1058	if (!pIemCpu->fBypassHandlers)
1059	rc = PGMPhysRead(pVM, GCPhys, pIemCpu->abOpcode, cbToTryRead);
1060	else
1061	rc = PGMPhysSimpleReadGCPhys(pVM, pIemCpu->abOpcode, GCPhys, cbToTryRead);
1062	if (rc != VINF_SUCCESS)
1063	{
1064	/** @todo status code handling */
1065	Log(("iemInitDecoderAndPrefetchOpcodes: %RGv/%RGp LB %#x - read error - rc=%Rrc (!!)\n",
1066	GCPtrPC, GCPhys, rc, cbToTryRead));
1067	return rc;
1068	}
1069	pIemCpu->cbOpcode = cbToTryRead;
1070	}
1071
1072	return VINF_SUCCESS;
1073	}
1074
1075
1076	/**
1077	* Try fetch at least @a cbMin bytes more opcodes, raise the appropriate
1078	* exception if it fails.
1079	*
1080	* @returns Strict VBox status code.
1081	* @param pIemCpu The IEM state.
1082	* @param cbMin The minimum number of bytes relative offOpcode
1083	* that must be read.
1084	*/
1085	static VBOXSTRICTRC iemOpcodeFetchMoreBytes(PIEMCPU pIemCpu, size_t cbMin)
1086	{
1087	/*
1088	* What we're doing here is very similar to iemMemMap/iemMemBounceBufferMap.
1089	*
1090	* First translate CS:rIP to a physical address.
1091	*/
1092	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1093	uint8_t cbLeft = pIemCpu->cbOpcode - pIemCpu->offOpcode; Assert(cbLeft < cbMin);
1094	uint32_t cbToTryRead;
1095	RTGCPTR GCPtrNext;
1096	if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
1097	{
1098	cbToTryRead = PAGE_SIZE;
1099	GCPtrNext = pCtx->rip + pIemCpu->cbOpcode;
1100	if (!IEM_IS_CANONICAL(GCPtrNext))
1101	return iemRaiseGeneralProtectionFault0(pIemCpu);
1102	}
1103	else
1104	{
1105	uint32_t GCPtrNext32 = pCtx->eip;
1106	Assert(!(GCPtrNext32 & ~(uint32_t)UINT16_MAX) \|\| pIemCpu->enmCpuMode == IEMMODE_32BIT);
1107	GCPtrNext32 += pIemCpu->cbOpcode;
1108	if (GCPtrNext32 > pCtx->cs.u32Limit)
1109	return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
1110	cbToTryRead = pCtx->cs.u32Limit - GCPtrNext32 + 1;
1111	if (!cbToTryRead) /* overflowed */
1112	{
1113	Assert(GCPtrNext32 == 0); Assert(pCtx->cs.u32Limit == UINT32_MAX);
1114	cbToTryRead = UINT32_MAX;
1115	/** @todo check out wrapping around the code segment. */
1116	}
1117	if (cbToTryRead < cbMin - cbLeft)
1118	return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
1119	GCPtrNext = (uint32_t)pCtx->cs.u64Base + GCPtrNext32;
1120	}
1121
1122	/* Only read up to the end of the page, and make sure we don't read more
1123	than the opcode buffer can hold. */
1124	uint32_t cbLeftOnPage = PAGE_SIZE - (GCPtrNext & PAGE_OFFSET_MASK);
1125	if (cbToTryRead > cbLeftOnPage)
1126	cbToTryRead = cbLeftOnPage;
1127	if (cbToTryRead > sizeof(pIemCpu->abOpcode) - pIemCpu->cbOpcode)
1128	cbToTryRead = sizeof(pIemCpu->abOpcode) - pIemCpu->cbOpcode;
1129	Assert(cbToTryRead >= cbMin - cbLeft); /* ASSUMPTION based on iemInitDecoderAndPrefetchOpcodes. */
1130
1131	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
1132	/* Allow interpretation of patch manager code blocks since they can for
1133	instance throw #PFs for perfectly good reasons. */
1134	if (pIemCpu->fInPatchCode)
1135	{
1136	size_t cbRead = 0;
1137	int rc = PATMReadPatchCode(IEMCPU_TO_VM(pIemCpu), GCPtrNext, pIemCpu->abOpcode, cbToTryRead, &cbRead);
1138	AssertRCReturn(rc, rc);
1139	pIemCpu->cbOpcode = (uint8_t)cbRead; Assert(pIemCpu->cbOpcode == cbRead); Assert(cbRead > 0);
1140	return VINF_SUCCESS;
1141	}
1142	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
1143
1144	RTGCPHYS GCPhys;
1145	uint64_t fFlags;
1146	int rc = PGMGstGetPage(IEMCPU_TO_VMCPU(pIemCpu), GCPtrNext, &fFlags, &GCPhys);
1147	if (RT_FAILURE(rc))
1148	{
1149	Log(("iemOpcodeFetchMoreBytes: %RGv - rc=%Rrc\n", GCPtrNext, rc));
1150	return iemRaisePageFault(pIemCpu, GCPtrNext, IEM_ACCESS_INSTRUCTION, rc);
1151	}
1152	if (!(fFlags & X86_PTE_US) && pIemCpu->uCpl == 3)
1153	{
1154	Log(("iemOpcodeFetchMoreBytes: %RGv - supervisor page\n", GCPtrNext));
1155	return iemRaisePageFault(pIemCpu, GCPtrNext, IEM_ACCESS_INSTRUCTION, VERR_ACCESS_DENIED);
1156	}
1157	if ((fFlags & X86_PTE_PAE_NX) && (pCtx->msrEFER & MSR_K6_EFER_NXE))
1158	{
1159	Log(("iemOpcodeFetchMoreBytes: %RGv - NX\n", GCPtrNext));
1160	return iemRaisePageFault(pIemCpu, GCPtrNext, IEM_ACCESS_INSTRUCTION, VERR_ACCESS_DENIED);
1161	}
1162	GCPhys \|= GCPtrNext & PAGE_OFFSET_MASK;
1163	Log5(("GCPtrNext=%RGv GCPhys=%RGp cbOpcodes=%#x\n", GCPtrNext, GCPhys, pIemCpu->cbOpcode));
1164	/** @todo Check reserved bits and such stuff. PGM is better at doing
1165	* that, so do it when implementing the guest virtual address
1166	* TLB... */
1167
1168	/*
1169	* Read the bytes at this address.
1170	*
1171	* We read all unpatched bytes in iemInitDecoderAndPrefetchOpcodes already,
1172	* and since PATM should only patch the start of an instruction there
1173	* should be no need to check again here.
1174	*/
1175	if (!pIemCpu->fBypassHandlers)
1176	rc = PGMPhysRead(IEMCPU_TO_VM(pIemCpu), GCPhys, &pIemCpu->abOpcode[pIemCpu->cbOpcode], cbToTryRead);
1177	else
1178	rc = PGMPhysSimpleReadGCPhys(IEMCPU_TO_VM(pIemCpu), &pIemCpu->abOpcode[pIemCpu->cbOpcode], GCPhys, cbToTryRead);
1179	if (rc != VINF_SUCCESS)
1180	{
1181	/** @todo status code handling */
1182	Log(("iemOpcodeFetchMoreBytes: %RGv - read error - rc=%Rrc (!!)\n", GCPtrNext, rc));
1183	return rc;
1184	}
1185	pIemCpu->cbOpcode += cbToTryRead;
1186	Log5(("%.*Rhxs\n", pIemCpu->cbOpcode, pIemCpu->abOpcode));
1187
1188	return VINF_SUCCESS;
1189	}
1190
1191
1192	/**
1193	* Deals with the problematic cases that iemOpcodeGetNextU8 doesn't like.
1194	*
1195	* @returns Strict VBox status code.
1196	* @param pIemCpu The IEM state.
1197	* @param pb Where to return the opcode byte.
1198	*/
1199	DECL_NO_INLINE(static, VBOXSTRICTRC) iemOpcodeGetNextU8Slow(PIEMCPU pIemCpu, uint8_t *pb)
1200	{
1201	VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 1);
1202	if (rcStrict == VINF_SUCCESS)
1203	{
1204	uint8_t offOpcode = pIemCpu->offOpcode;
1205	*pb = pIemCpu->abOpcode[offOpcode];
1206	pIemCpu->offOpcode = offOpcode + 1;
1207	}
1208	else
1209	*pb = 0;
1210	return rcStrict;
1211	}
1212
1213
1214	/**
1215	* Fetches the next opcode byte.
1216	*
1217	* @returns Strict VBox status code.
1218	* @param pIemCpu The IEM state.
1219	* @param pu8 Where to return the opcode byte.
1220	*/
1221	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU8(PIEMCPU pIemCpu, uint8_t *pu8)
1222	{
1223	uint8_t const offOpcode = pIemCpu->offOpcode;
1224	if (RT_UNLIKELY(offOpcode >= pIemCpu->cbOpcode))
1225	return iemOpcodeGetNextU8Slow(pIemCpu, pu8);
1226
1227	*pu8 = pIemCpu->abOpcode[offOpcode];
1228	pIemCpu->offOpcode = offOpcode + 1;
1229	return VINF_SUCCESS;
1230	}
1231
1232
1233	/**
1234	* Fetches the next opcode byte, returns automatically on failure.
1235	*
1236	* @param a_pu8 Where to return the opcode byte.
1237	* @remark Implicitly references pIemCpu.
1238	*/
1239	#define IEM_OPCODE_GET_NEXT_U8(a_pu8) \
1240	do \
1241	{ \
1242	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU8(pIemCpu, (a_pu8)); \
1243	if (rcStrict2 != VINF_SUCCESS) \
1244	return rcStrict2; \
1245	} while (0)
1246
1247
1248	/**
1249	* Fetches the next signed byte from the opcode stream.
1250	*
1251	* @returns Strict VBox status code.
1252	* @param pIemCpu The IEM state.
1253	* @param pi8 Where to return the signed byte.
1254	*/
1255	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8(PIEMCPU pIemCpu, int8_t *pi8)
1256	{
1257	return iemOpcodeGetNextU8(pIemCpu, (uint8_t *)pi8);
1258	}
1259
1260
1261	/**
1262	* Fetches the next signed byte from the opcode stream, returning automatically
1263	* on failure.
1264	*
1265	* @param pi8 Where to return the signed byte.
1266	* @remark Implicitly references pIemCpu.
1267	*/
1268	#define IEM_OPCODE_GET_NEXT_S8(a_pi8) \
1269	do \
1270	{ \
1271	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8(pIemCpu, (a_pi8)); \
1272	if (rcStrict2 != VINF_SUCCESS) \
1273	return rcStrict2; \
1274	} while (0)
1275
1276
1277	/**
1278	* Deals with the problematic cases that iemOpcodeGetNextS8SxU16 doesn't like.
1279	*
1280	* @returns Strict VBox status code.
1281	* @param pIemCpu The IEM state.
1282	* @param pu16 Where to return the opcode dword.
1283	*/
1284	DECL_NO_INLINE(static, VBOXSTRICTRC) iemOpcodeGetNextS8SxU16Slow(PIEMCPU pIemCpu, uint16_t *pu16)
1285	{
1286	uint8_t u8;
1287	VBOXSTRICTRC rcStrict = iemOpcodeGetNextU8Slow(pIemCpu, &u8);
1288	if (rcStrict == VINF_SUCCESS)
1289	*pu16 = (int8_t)u8;
1290	return rcStrict;
1291	}
1292
1293
1294	/**
1295	* Fetches the next signed byte from the opcode stream, extending it to
1296	* unsigned 16-bit.
1297	*
1298	* @returns Strict VBox status code.
1299	* @param pIemCpu The IEM state.
1300	* @param pu16 Where to return the unsigned word.
1301	*/
1302	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU16(PIEMCPU pIemCpu, uint16_t *pu16)
1303	{
1304	uint8_t const offOpcode = pIemCpu->offOpcode;
1305	if (RT_UNLIKELY(offOpcode >= pIemCpu->cbOpcode))
1306	return iemOpcodeGetNextS8SxU16Slow(pIemCpu, pu16);
1307
1308	*pu16 = (int8_t)pIemCpu->abOpcode[offOpcode];
1309	pIemCpu->offOpcode = offOpcode + 1;
1310	return VINF_SUCCESS;
1311	}
1312
1313
1314	/**
1315	* Fetches the next signed byte from the opcode stream and sign-extending it to
1316	* a word, returning automatically on failure.
1317	*
1318	* @param pu16 Where to return the word.
1319	* @remark Implicitly references pIemCpu.
1320	*/
1321	#define IEM_OPCODE_GET_NEXT_S8_SX_U16(a_pu16) \
1322	do \
1323	{ \
1324	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU16(pIemCpu, (a_pu16)); \
1325	if (rcStrict2 != VINF_SUCCESS) \
1326	return rcStrict2; \
1327	} while (0)
1328
1329
1330	/**
1331	* Deals with the problematic cases that iemOpcodeGetNextS8SxU32 doesn't like.
1332	*
1333	* @returns Strict VBox status code.
1334	* @param pIemCpu The IEM state.
1335	* @param pu32 Where to return the opcode dword.
1336	*/
1337	DECL_NO_INLINE(static, VBOXSTRICTRC) iemOpcodeGetNextS8SxU32Slow(PIEMCPU pIemCpu, uint32_t *pu32)
1338	{
1339	uint8_t u8;
1340	VBOXSTRICTRC rcStrict = iemOpcodeGetNextU8Slow(pIemCpu, &u8);
1341	if (rcStrict == VINF_SUCCESS)
1342	*pu32 = (int8_t)u8;
1343	return rcStrict;
1344	}
1345
1346
1347	/**
1348	* Fetches the next signed byte from the opcode stream, extending it to
1349	* unsigned 32-bit.
1350	*
1351	* @returns Strict VBox status code.
1352	* @param pIemCpu The IEM state.
1353	* @param pu32 Where to return the unsigned dword.
1354	*/
1355	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU32(PIEMCPU pIemCpu, uint32_t *pu32)
1356	{
1357	uint8_t const offOpcode = pIemCpu->offOpcode;
1358	if (RT_UNLIKELY(offOpcode >= pIemCpu->cbOpcode))
1359	return iemOpcodeGetNextS8SxU32Slow(pIemCpu, pu32);
1360
1361	*pu32 = (int8_t)pIemCpu->abOpcode[offOpcode];
1362	pIemCpu->offOpcode = offOpcode + 1;
1363	return VINF_SUCCESS;
1364	}
1365
1366
1367	/**
1368	* Fetches the next signed byte from the opcode stream and sign-extending it to
1369	* a word, returning automatically on failure.
1370	*
1371	* @param pu32 Where to return the word.
1372	* @remark Implicitly references pIemCpu.
1373	*/
1374	#define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) \
1375	do \
1376	{ \
1377	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU32(pIemCpu, (a_pu32)); \
1378	if (rcStrict2 != VINF_SUCCESS) \
1379	return rcStrict2; \
1380	} while (0)
1381
1382
1383	/**
1384	* Deals with the problematic cases that iemOpcodeGetNextS8SxU64 doesn't like.
1385	*
1386	* @returns Strict VBox status code.
1387	* @param pIemCpu The IEM state.
1388	* @param pu64 Where to return the opcode qword.
1389	*/
1390	DECL_NO_INLINE(static, VBOXSTRICTRC) iemOpcodeGetNextS8SxU64Slow(PIEMCPU pIemCpu, uint64_t *pu64)
1391	{
1392	uint8_t u8;
1393	VBOXSTRICTRC rcStrict = iemOpcodeGetNextU8Slow(pIemCpu, &u8);
1394	if (rcStrict == VINF_SUCCESS)
1395	*pu64 = (int8_t)u8;
1396	return rcStrict;
1397	}
1398
1399
1400	/**
1401	* Fetches the next signed byte from the opcode stream, extending it to
1402	* unsigned 64-bit.
1403	*
1404	* @returns Strict VBox status code.
1405	* @param pIemCpu The IEM state.
1406	* @param pu64 Where to return the unsigned qword.
1407	*/
1408	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU64(PIEMCPU pIemCpu, uint64_t *pu64)
1409	{
1410	uint8_t const offOpcode = pIemCpu->offOpcode;
1411	if (RT_UNLIKELY(offOpcode >= pIemCpu->cbOpcode))
1412	return iemOpcodeGetNextS8SxU64Slow(pIemCpu, pu64);
1413
1414	*pu64 = (int8_t)pIemCpu->abOpcode[offOpcode];
1415	pIemCpu->offOpcode = offOpcode + 1;
1416	return VINF_SUCCESS;
1417	}
1418
1419
1420	/**
1421	* Fetches the next signed byte from the opcode stream and sign-extending it to
1422	* a word, returning automatically on failure.
1423	*
1424	* @param pu64 Where to return the word.
1425	* @remark Implicitly references pIemCpu.
1426	*/
1427	#define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) \
1428	do \
1429	{ \
1430	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU64(pIemCpu, (a_pu64)); \
1431	if (rcStrict2 != VINF_SUCCESS) \
1432	return rcStrict2; \
1433	} while (0)
1434
1435
1436	/**
1437	* Deals with the problematic cases that iemOpcodeGetNextU16 doesn't like.
1438	*
1439	* @returns Strict VBox status code.
1440	* @param pIemCpu The IEM state.
1441	* @param pu16 Where to return the opcode word.
1442	*/
1443	DECL_NO_INLINE(static, VBOXSTRICTRC) iemOpcodeGetNextU16Slow(PIEMCPU pIemCpu, uint16_t *pu16)
1444	{
1445	VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 2);
1446	if (rcStrict == VINF_SUCCESS)
1447	{
1448	uint8_t offOpcode = pIemCpu->offOpcode;
1449	*pu16 = RT_MAKE_U16(pIemCpu->abOpcode[offOpcode], pIemCpu->abOpcode[offOpcode + 1]);
1450	pIemCpu->offOpcode = offOpcode + 2;
1451	}
1452	else
1453	*pu16 = 0;
1454	return rcStrict;
1455	}
1456
1457
1458	/**
1459	* Fetches the next opcode word.
1460	*
1461	* @returns Strict VBox status code.
1462	* @param pIemCpu The IEM state.
1463	* @param pu16 Where to return the opcode word.
1464	*/
1465	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU16(PIEMCPU pIemCpu, uint16_t *pu16)
1466	{
1467	uint8_t const offOpcode = pIemCpu->offOpcode;
1468	if (RT_UNLIKELY(offOpcode + 2 > pIemCpu->cbOpcode))
1469	return iemOpcodeGetNextU16Slow(pIemCpu, pu16);
1470
1471	*pu16 = RT_MAKE_U16(pIemCpu->abOpcode[offOpcode], pIemCpu->abOpcode[offOpcode + 1]);
1472	pIemCpu->offOpcode = offOpcode + 2;
1473	return VINF_SUCCESS;
1474	}
1475
1476
1477	/**
1478	* Fetches the next opcode word, returns automatically on failure.
1479	*
1480	* @param a_pu16 Where to return the opcode word.
1481	* @remark Implicitly references pIemCpu.
1482	*/
1483	#define IEM_OPCODE_GET_NEXT_U16(a_pu16) \
1484	do \
1485	{ \
1486	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU16(pIemCpu, (a_pu16)); \
1487	if (rcStrict2 != VINF_SUCCESS) \
1488	return rcStrict2; \
1489	} while (0)
1490
1491
1492	/**
1493	* Deals with the problematic cases that iemOpcodeGetNextU16ZxU32 doesn't like.
1494	*
1495	* @returns Strict VBox status code.
1496	* @param pIemCpu The IEM state.
1497	* @param pu32 Where to return the opcode double word.
1498	*/
1499	DECL_NO_INLINE(static, VBOXSTRICTRC) iemOpcodeGetNextU16ZxU32Slow(PIEMCPU pIemCpu, uint32_t *pu32)
1500	{
1501	VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 2);
1502	if (rcStrict == VINF_SUCCESS)
1503	{
1504	uint8_t offOpcode = pIemCpu->offOpcode;
1505	*pu32 = RT_MAKE_U16(pIemCpu->abOpcode[offOpcode], pIemCpu->abOpcode[offOpcode + 1]);
1506	pIemCpu->offOpcode = offOpcode + 2;
1507	}
1508	else
1509	*pu32 = 0;
1510	return rcStrict;
1511	}
1512
1513
1514	/**
1515	* Fetches the next opcode word, zero extending it to a double word.
1516	*
1517	* @returns Strict VBox status code.
1518	* @param pIemCpu The IEM state.
1519	* @param pu32 Where to return the opcode double word.
1520	*/
1521	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU16ZxU32(PIEMCPU pIemCpu, uint32_t *pu32)
1522	{
1523	uint8_t const offOpcode = pIemCpu->offOpcode;
1524	if (RT_UNLIKELY(offOpcode + 2 > pIemCpu->cbOpcode))
1525	return iemOpcodeGetNextU16ZxU32Slow(pIemCpu, pu32);
1526
1527	*pu32 = RT_MAKE_U16(pIemCpu->abOpcode[offOpcode], pIemCpu->abOpcode[offOpcode + 1]);
1528	pIemCpu->offOpcode = offOpcode + 2;
1529	return VINF_SUCCESS;
1530	}
1531
1532
1533	/**
1534	* Fetches the next opcode word and zero extends it to a double word, returns
1535	* automatically on failure.
1536	*
1537	* @param a_pu32 Where to return the opcode double word.
1538	* @remark Implicitly references pIemCpu.
1539	*/
1540	#define IEM_OPCODE_GET_NEXT_U16_ZX_U32(a_pu32) \
1541	do \
1542	{ \
1543	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU16ZxU32(pIemCpu, (a_pu32)); \
1544	if (rcStrict2 != VINF_SUCCESS) \
1545	return rcStrict2; \
1546	} while (0)
1547
1548
1549	/**
1550	* Deals with the problematic cases that iemOpcodeGetNextU16ZxU64 doesn't like.
1551	*
1552	* @returns Strict VBox status code.
1553	* @param pIemCpu The IEM state.
1554	* @param pu64 Where to return the opcode quad word.
1555	*/
1556	DECL_NO_INLINE(static, VBOXSTRICTRC) iemOpcodeGetNextU16ZxU64Slow(PIEMCPU pIemCpu, uint64_t *pu64)
1557	{
1558	VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 2);
1559	if (rcStrict == VINF_SUCCESS)
1560	{
1561	uint8_t offOpcode = pIemCpu->offOpcode;
1562	*pu64 = RT_MAKE_U16(pIemCpu->abOpcode[offOpcode], pIemCpu->abOpcode[offOpcode + 1]);
1563	pIemCpu->offOpcode = offOpcode + 2;
1564	}
1565	else
1566	*pu64 = 0;
1567	return rcStrict;
1568	}
1569
1570
1571	/**
1572	* Fetches the next opcode word, zero extending it to a quad word.
1573	*
1574	* @returns Strict VBox status code.
1575	* @param pIemCpu The IEM state.
1576	* @param pu64 Where to return the opcode quad word.
1577	*/
1578	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU16ZxU64(PIEMCPU pIemCpu, uint64_t *pu64)
1579	{
1580	uint8_t const offOpcode = pIemCpu->offOpcode;
1581	if (RT_UNLIKELY(offOpcode + 2 > pIemCpu->cbOpcode))
1582	return iemOpcodeGetNextU16ZxU64Slow(pIemCpu, pu64);
1583
1584	*pu64 = RT_MAKE_U16(pIemCpu->abOpcode[offOpcode], pIemCpu->abOpcode[offOpcode + 1]);
1585	pIemCpu->offOpcode = offOpcode + 2;
1586	return VINF_SUCCESS;
1587	}
1588
1589
1590	/**
1591	* Fetches the next opcode word and zero extends it to a quad word, returns
1592	* automatically on failure.
1593	*
1594	* @param a_pu64 Where to return the opcode quad word.
1595	* @remark Implicitly references pIemCpu.
1596	*/
1597	#define IEM_OPCODE_GET_NEXT_U16_ZX_U64(a_pu64) \
1598	do \
1599	{ \
1600	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU16ZxU64(pIemCpu, (a_pu64)); \
1601	if (rcStrict2 != VINF_SUCCESS) \
1602	return rcStrict2; \
1603	} while (0)
1604
1605
1606	/**
1607	* Fetches the next signed word from the opcode stream.
1608	*
1609	* @returns Strict VBox status code.
1610	* @param pIemCpu The IEM state.
1611	* @param pi16 Where to return the signed word.
1612	*/
1613	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS16(PIEMCPU pIemCpu, int16_t *pi16)
1614	{
1615	return iemOpcodeGetNextU16(pIemCpu, (uint16_t *)pi16);
1616	}
1617
1618
1619	/**
1620	* Fetches the next signed word from the opcode stream, returning automatically
1621	* on failure.
1622	*
1623	* @param pi16 Where to return the signed word.
1624	* @remark Implicitly references pIemCpu.
1625	*/
1626	#define IEM_OPCODE_GET_NEXT_S16(a_pi16) \
1627	do \
1628	{ \
1629	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS16(pIemCpu, (a_pi16)); \
1630	if (rcStrict2 != VINF_SUCCESS) \
1631	return rcStrict2; \
1632	} while (0)
1633
1634
1635	/**
1636	* Deals with the problematic cases that iemOpcodeGetNextU32 doesn't like.
1637	*
1638	* @returns Strict VBox status code.
1639	* @param pIemCpu The IEM state.
1640	* @param pu32 Where to return the opcode dword.
1641	*/
1642	DECL_NO_INLINE(static, VBOXSTRICTRC) iemOpcodeGetNextU32Slow(PIEMCPU pIemCpu, uint32_t *pu32)
1643	{
1644	VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 4);
1645	if (rcStrict == VINF_SUCCESS)
1646	{
1647	uint8_t offOpcode = pIemCpu->offOpcode;
1648	*pu32 = RT_MAKE_U32_FROM_U8(pIemCpu->abOpcode[offOpcode],
1649	pIemCpu->abOpcode[offOpcode + 1],
1650	pIemCpu->abOpcode[offOpcode + 2],
1651	pIemCpu->abOpcode[offOpcode + 3]);
1652	pIemCpu->offOpcode = offOpcode + 4;
1653	}
1654	else
1655	*pu32 = 0;
1656	return rcStrict;
1657	}
1658
1659
1660	/**
1661	* Fetches the next opcode dword.
1662	*
1663	* @returns Strict VBox status code.
1664	* @param pIemCpu The IEM state.
1665	* @param pu32 Where to return the opcode double word.
1666	*/
1667	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU32(PIEMCPU pIemCpu, uint32_t *pu32)
1668	{
1669	uint8_t const offOpcode = pIemCpu->offOpcode;
1670	if (RT_UNLIKELY(offOpcode + 4 > pIemCpu->cbOpcode))
1671	return iemOpcodeGetNextU32Slow(pIemCpu, pu32);
1672
1673	*pu32 = RT_MAKE_U32_FROM_U8(pIemCpu->abOpcode[offOpcode],
1674	pIemCpu->abOpcode[offOpcode + 1],
1675	pIemCpu->abOpcode[offOpcode + 2],
1676	pIemCpu->abOpcode[offOpcode + 3]);
1677	pIemCpu->offOpcode = offOpcode + 4;
1678	return VINF_SUCCESS;
1679	}
1680
1681
1682	/**
1683	* Fetches the next opcode dword, returns automatically on failure.
1684	*
1685	* @param a_pu32 Where to return the opcode dword.
1686	* @remark Implicitly references pIemCpu.
1687	*/
1688	#define IEM_OPCODE_GET_NEXT_U32(a_pu32) \
1689	do \
1690	{ \
1691	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU32(pIemCpu, (a_pu32)); \
1692	if (rcStrict2 != VINF_SUCCESS) \
1693	return rcStrict2; \
1694	} while (0)
1695
1696
1697	/**
1698	* Deals with the problematic cases that iemOpcodeGetNextU32ZxU64 doesn't like.
1699	*
1700	* @returns Strict VBox status code.
1701	* @param pIemCpu The IEM state.
1702	* @param pu32 Where to return the opcode dword.
1703	*/
1704	DECL_NO_INLINE(static, VBOXSTRICTRC) iemOpcodeGetNextU32ZxU64Slow(PIEMCPU pIemCpu, uint64_t *pu64)
1705	{
1706	VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 4);
1707	if (rcStrict == VINF_SUCCESS)
1708	{
1709	uint8_t offOpcode = pIemCpu->offOpcode;
1710	*pu64 = RT_MAKE_U32_FROM_U8(pIemCpu->abOpcode[offOpcode],
1711	pIemCpu->abOpcode[offOpcode + 1],
1712	pIemCpu->abOpcode[offOpcode + 2],
1713	pIemCpu->abOpcode[offOpcode + 3]);
1714	pIemCpu->offOpcode = offOpcode + 4;
1715	}
1716	else
1717	*pu64 = 0;
1718	return rcStrict;
1719	}
1720
1721
1722	/**
1723	* Fetches the next opcode dword, zero extending it to a quad word.
1724	*
1725	* @returns Strict VBox status code.
1726	* @param pIemCpu The IEM state.
1727	* @param pu64 Where to return the opcode quad word.
1728	*/
1729	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU32ZxU64(PIEMCPU pIemCpu, uint64_t *pu64)
1730	{
1731	uint8_t const offOpcode = pIemCpu->offOpcode;
1732	if (RT_UNLIKELY(offOpcode + 4 > pIemCpu->cbOpcode))
1733	return iemOpcodeGetNextU32ZxU64Slow(pIemCpu, pu64);
1734
1735	*pu64 = RT_MAKE_U32_FROM_U8(pIemCpu->abOpcode[offOpcode],
1736	pIemCpu->abOpcode[offOpcode + 1],
1737	pIemCpu->abOpcode[offOpcode + 2],
1738	pIemCpu->abOpcode[offOpcode + 3]);
1739	pIemCpu->offOpcode = offOpcode + 4;
1740	return VINF_SUCCESS;
1741	}
1742
1743
1744	/**
1745	* Fetches the next opcode dword and zero extends it to a quad word, returns
1746	* automatically on failure.
1747	*
1748	* @param a_pu64 Where to return the opcode quad word.
1749	* @remark Implicitly references pIemCpu.
1750	*/
1751	#define IEM_OPCODE_GET_NEXT_U32_ZX_U64(a_pu64) \
1752	do \
1753	{ \
1754	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU32ZxU64(pIemCpu, (a_pu64)); \
1755	if (rcStrict2 != VINF_SUCCESS) \
1756	return rcStrict2; \
1757	} while (0)
1758
1759
1760	/**
1761	* Fetches the next signed double word from the opcode stream.
1762	*
1763	* @returns Strict VBox status code.
1764	* @param pIemCpu The IEM state.
1765	* @param pi32 Where to return the signed double word.
1766	*/
1767	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS32(PIEMCPU pIemCpu, int32_t *pi32)
1768	{
1769	return iemOpcodeGetNextU32(pIemCpu, (uint32_t *)pi32);
1770	}
1771
1772	/**
1773	* Fetches the next signed double word from the opcode stream, returning
1774	* automatically on failure.
1775	*
1776	* @param pi32 Where to return the signed double word.
1777	* @remark Implicitly references pIemCpu.
1778	*/
1779	#define IEM_OPCODE_GET_NEXT_S32(a_pi32) \
1780	do \
1781	{ \
1782	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS32(pIemCpu, (a_pi32)); \
1783	if (rcStrict2 != VINF_SUCCESS) \
1784	return rcStrict2; \
1785	} while (0)
1786
1787
1788	/**
1789	* Deals with the problematic cases that iemOpcodeGetNextS32SxU64 doesn't like.
1790	*
1791	* @returns Strict VBox status code.
1792	* @param pIemCpu The IEM state.
1793	* @param pu64 Where to return the opcode qword.
1794	*/
1795	DECL_NO_INLINE(static, VBOXSTRICTRC) iemOpcodeGetNextS32SxU64Slow(PIEMCPU pIemCpu, uint64_t *pu64)
1796	{
1797	VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 4);
1798	if (rcStrict == VINF_SUCCESS)
1799	{
1800	uint8_t offOpcode = pIemCpu->offOpcode;
1801	*pu64 = (int32_t)RT_MAKE_U32_FROM_U8(pIemCpu->abOpcode[offOpcode],
1802	pIemCpu->abOpcode[offOpcode + 1],
1803	pIemCpu->abOpcode[offOpcode + 2],
1804	pIemCpu->abOpcode[offOpcode + 3]);
1805	pIemCpu->offOpcode = offOpcode + 4;
1806	}
1807	else
1808	*pu64 = 0;
1809	return rcStrict;
1810	}
1811
1812
1813	/**
1814	* Fetches the next opcode dword, sign extending it into a quad word.
1815	*
1816	* @returns Strict VBox status code.
1817	* @param pIemCpu The IEM state.
1818	* @param pu64 Where to return the opcode quad word.
1819	*/
1820	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS32SxU64(PIEMCPU pIemCpu, uint64_t *pu64)
1821	{
1822	uint8_t const offOpcode = pIemCpu->offOpcode;
1823	if (RT_UNLIKELY(offOpcode + 4 > pIemCpu->cbOpcode))
1824	return iemOpcodeGetNextS32SxU64Slow(pIemCpu, pu64);
1825
1826	int32_t i32 = RT_MAKE_U32_FROM_U8(pIemCpu->abOpcode[offOpcode],
1827	pIemCpu->abOpcode[offOpcode + 1],
1828	pIemCpu->abOpcode[offOpcode + 2],
1829	pIemCpu->abOpcode[offOpcode + 3]);
1830	*pu64 = i32;
1831	pIemCpu->offOpcode = offOpcode + 4;
1832	return VINF_SUCCESS;
1833	}
1834
1835
1836	/**
1837	* Fetches the next opcode double word and sign extends it to a quad word,
1838	* returns automatically on failure.
1839	*
1840	* @param a_pu64 Where to return the opcode quad word.
1841	* @remark Implicitly references pIemCpu.
1842	*/
1843	#define IEM_OPCODE_GET_NEXT_S32_SX_U64(a_pu64) \
1844	do \
1845	{ \
1846	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS32SxU64(pIemCpu, (a_pu64)); \
1847	if (rcStrict2 != VINF_SUCCESS) \
1848	return rcStrict2; \
1849	} while (0)
1850
1851
1852	/**
1853	* Deals with the problematic cases that iemOpcodeGetNextU64 doesn't like.
1854	*
1855	* @returns Strict VBox status code.
1856	* @param pIemCpu The IEM state.
1857	* @param pu64 Where to return the opcode qword.
1858	*/
1859	DECL_NO_INLINE(static, VBOXSTRICTRC) iemOpcodeGetNextU64Slow(PIEMCPU pIemCpu, uint64_t *pu64)
1860	{
1861	VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pIemCpu, 8);
1862	if (rcStrict == VINF_SUCCESS)
1863	{
1864	uint8_t offOpcode = pIemCpu->offOpcode;
1865	*pu64 = RT_MAKE_U64_FROM_U8(pIemCpu->abOpcode[offOpcode],
1866	pIemCpu->abOpcode[offOpcode + 1],
1867	pIemCpu->abOpcode[offOpcode + 2],
1868	pIemCpu->abOpcode[offOpcode + 3],
1869	pIemCpu->abOpcode[offOpcode + 4],
1870	pIemCpu->abOpcode[offOpcode + 5],
1871	pIemCpu->abOpcode[offOpcode + 6],
1872	pIemCpu->abOpcode[offOpcode + 7]);
1873	pIemCpu->offOpcode = offOpcode + 8;
1874	}
1875	else
1876	*pu64 = 0;
1877	return rcStrict;
1878	}
1879
1880
1881	/**
1882	* Fetches the next opcode qword.
1883	*
1884	* @returns Strict VBox status code.
1885	* @param pIemCpu The IEM state.
1886	* @param pu64 Where to return the opcode qword.
1887	*/
1888	DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU64(PIEMCPU pIemCpu, uint64_t *pu64)
1889	{
1890	uint8_t const offOpcode = pIemCpu->offOpcode;
1891	if (RT_UNLIKELY(offOpcode + 8 > pIemCpu->cbOpcode))
1892	return iemOpcodeGetNextU64Slow(pIemCpu, pu64);
1893
1894	*pu64 = RT_MAKE_U64_FROM_U8(pIemCpu->abOpcode[offOpcode],
1895	pIemCpu->abOpcode[offOpcode + 1],
1896	pIemCpu->abOpcode[offOpcode + 2],
1897	pIemCpu->abOpcode[offOpcode + 3],
1898	pIemCpu->abOpcode[offOpcode + 4],
1899	pIemCpu->abOpcode[offOpcode + 5],
1900	pIemCpu->abOpcode[offOpcode + 6],
1901	pIemCpu->abOpcode[offOpcode + 7]);
1902	pIemCpu->offOpcode = offOpcode + 8;
1903	return VINF_SUCCESS;
1904	}
1905
1906
1907	/**
1908	* Fetches the next opcode quad word, returns automatically on failure.
1909	*
1910	* @param a_pu64 Where to return the opcode quad word.
1911	* @remark Implicitly references pIemCpu.
1912	*/
1913	#define IEM_OPCODE_GET_NEXT_U64(a_pu64) \
1914	do \
1915	{ \
1916	VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU64(pIemCpu, (a_pu64)); \
1917	if (rcStrict2 != VINF_SUCCESS) \
1918	return rcStrict2; \
1919	} while (0)
1920
1921
1922	/** @name Misc Worker Functions.
1923	* @{
1924	*/
1925
1926
1927	/**
1928	* Validates a new SS segment.
1929	*
1930	* @returns VBox strict status code.
1931	* @param pIemCpu The IEM per CPU instance data.
1932	* @param pCtx The CPU context.
1933	* @param NewSS The new SS selctor.
1934	* @param uCpl The CPL to load the stack for.
1935	* @param pDesc Where to return the descriptor.
1936	*/
1937	static VBOXSTRICTRC iemMiscValidateNewSS(PIEMCPU pIemCpu, PCCPUMCTX pCtx, RTSEL NewSS, uint8_t uCpl, PIEMSELDESC pDesc)
1938	{
1939	NOREF(pCtx);
1940
1941	/* Null selectors are not allowed (we're not called for dispatching
1942	interrupts with SS=0 in long mode). */
1943	if (!(NewSS & X86_SEL_MASK_OFF_RPL))
1944	{
1945	Log(("iemMiscValidateNewSSandRsp: #x - null selector -> #TS(0)\n", NewSS));
1946	return iemRaiseTaskSwitchFault0(pIemCpu);
1947	}
1948
1949	/** @todo testcase: check that the TSS.ssX RPL is checked. Also check when. */
1950	if ((NewSS & X86_SEL_RPL) != uCpl)
1951	{
1952	Log(("iemMiscValidateNewSSandRsp: %#x - RPL and CPL (%d) differs -> #TS\n", NewSS, uCpl));
1953	return iemRaiseTaskSwitchFaultBySelector(pIemCpu, NewSS);
1954	}
1955
1956	/*
1957	* Read the descriptor.
1958	*/
1959	VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pIemCpu, pDesc, NewSS, X86_XCPT_TS);
1960	if (rcStrict != VINF_SUCCESS)
1961	return rcStrict;
1962
1963	/*
1964	* Perform the descriptor validation documented for LSS, POP SS and MOV SS.
1965	*/
1966	if (!pDesc->Legacy.Gen.u1DescType)
1967	{
1968	Log(("iemMiscValidateNewSSandRsp: %#x - system selector -> #TS\n", NewSS, pDesc->Legacy.Gen.u4Type));
1969	return iemRaiseTaskSwitchFaultBySelector(pIemCpu, NewSS);
1970	}
1971
1972	if ( (pDesc->Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
1973	\|\| !(pDesc->Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
1974	{
1975	Log(("iemMiscValidateNewSSandRsp: %#x - code or read only (%#x) -> #TS\n", NewSS, pDesc->Legacy.Gen.u4Type));
1976	return iemRaiseTaskSwitchFaultBySelector(pIemCpu, NewSS);
1977	}
1978	if (pDesc->Legacy.Gen.u2Dpl != uCpl)
1979	{
1980	Log(("iemMiscValidateNewSSandRsp: %#x - DPL (%d) and CPL (%d) differs -> #TS\n", NewSS, pDesc->Legacy.Gen.u2Dpl, uCpl));
1981	return iemRaiseTaskSwitchFaultBySelector(pIemCpu, NewSS);
1982	}
1983
1984	/* Is it there? */
1985	/** @todo testcase: Is this checked before the canonical / limit check below? */
1986	if (!pDesc->Legacy.Gen.u1Present)
1987	{
1988	Log(("iemMiscValidateNewSSandRsp: %#x - segment not present -> #NP\n", NewSS));
1989	return iemRaiseSelectorNotPresentBySelector(pIemCpu, NewSS);
1990	}
1991
1992	return VINF_SUCCESS;
1993	}
1994
1995
1996	/**
1997	* Gets the correct EFLAGS regardless of whether PATM stores parts of them or
1998	* not.
1999	*
2000	* @param a_pIemCpu The IEM per CPU data.
2001	* @param a_pCtx The CPU context.
2002	*/
2003	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2004	# define IEMMISC_GET_EFL(a_pIemCpu, a_pCtx) \
2005	( IEM_VERIFICATION_ENABLED(a_pIemCpu) \
2006	? (a_pCtx)->eflags.u \
2007	: CPUMRawGetEFlags(IEMCPU_TO_VMCPU(a_pIemCpu)) )
2008	#else
2009	# define IEMMISC_GET_EFL(a_pIemCpu, a_pCtx) \
2010	( (a_pCtx)->eflags.u )
2011	#endif
2012
2013	/**
2014	* Updates the EFLAGS in the correct manner wrt. PATM.
2015	*
2016	* @param a_pIemCpu The IEM per CPU data.
2017	* @param a_pCtx The CPU context.
2018	*/
2019	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2020	# define IEMMISC_SET_EFL(a_pIemCpu, a_pCtx, a_fEfl) \
2021	do { \
2022	if (IEM_VERIFICATION_ENABLED(a_pIemCpu)) \
2023	(a_pCtx)->eflags.u = (a_fEfl); \
2024	else \
2025	CPUMRawSetEFlags(IEMCPU_TO_VMCPU(a_pIemCpu), a_fEfl); \
2026	} while (0)
2027	#else
2028	# define IEMMISC_SET_EFL(a_pIemCpu, a_pCtx, a_fEfl) \
2029	do { \
2030	(a_pCtx)->eflags.u = (a_fEfl); \
2031	} while (0)
2032	#endif
2033
2034
2035	/** @} */
2036
2037	/** @name Raising Exceptions.
2038	*
2039	* @{
2040	*/
2041
2042	/** @name IEM_XCPT_FLAGS_XXX - flags for iemRaiseXcptOrInt.
2043	* @{ */
2044	/** CPU exception. */
2045	#define IEM_XCPT_FLAGS_T_CPU_XCPT RT_BIT_32(0)
2046	/** External interrupt (from PIC, APIC, whatever). */
2047	#define IEM_XCPT_FLAGS_T_EXT_INT RT_BIT_32(1)
2048	/** Software interrupt (int or into, not bound).
2049	* Returns to the following instruction */
2050	#define IEM_XCPT_FLAGS_T_SOFT_INT RT_BIT_32(2)
2051	/** Takes an error code. */
2052	#define IEM_XCPT_FLAGS_ERR RT_BIT_32(3)
2053	/** Takes a CR2. */
2054	#define IEM_XCPT_FLAGS_CR2 RT_BIT_32(4)
2055	/** Generated by the breakpoint instruction. */
2056	#define IEM_XCPT_FLAGS_BP_INSTR RT_BIT_32(5)
2057	/** Generated by a DRx instruction breakpoint and RF should be cleared. */
2058	#define IEM_XCPT_FLAGS_DRx_INSTR_BP RT_BIT_32(6)
2059	/** @} */
2060
2061
2062	/**
2063	* Loads the specified stack far pointer from the TSS.
2064	*
2065	* @returns VBox strict status code.
2066	* @param pIemCpu The IEM per CPU instance data.
2067	* @param pCtx The CPU context.
2068	* @param uCpl The CPL to load the stack for.
2069	* @param pSelSS Where to return the new stack segment.
2070	* @param puEsp Where to return the new stack pointer.
2071	*/
2072	static VBOXSTRICTRC iemRaiseLoadStackFromTss32Or16(PIEMCPU pIemCpu, PCCPUMCTX pCtx, uint8_t uCpl,
2073	PRTSEL pSelSS, uint32_t *puEsp)
2074	{
2075	VBOXSTRICTRC rcStrict;
2076	Assert(uCpl < 4);
2077	puEsp = 0; / make gcc happy */
2078	pSelSS = 0; / make gcc happy */
2079
2080	switch (pCtx->tr.Attr.n.u4Type)
2081	{
2082	/*
2083	* 16-bit TSS (X86TSS16).
2084	*/
2085	case X86_SEL_TYPE_SYS_286_TSS_AVAIL: AssertFailed();
2086	case X86_SEL_TYPE_SYS_286_TSS_BUSY:
2087	{
2088	uint32_t off = uCpl * 4 + 2;
2089	if (off + 4 > pCtx->tr.u32Limit)
2090	{
2091	Log(("LoadStackFromTss32Or16: out of bounds! uCpl=%d, u32Limit=%#x TSS16\n", uCpl, pCtx->tr.u32Limit));
2092	return iemRaiseTaskSwitchFaultCurrentTSS(pIemCpu);
2093	}
2094
2095	uint32_t u32Tmp = 0; /* gcc maybe... */
2096	rcStrict = iemMemFetchSysU32(pIemCpu, &u32Tmp, UINT8_MAX, pCtx->tr.u64Base + off);
2097	if (rcStrict == VINF_SUCCESS)
2098	{
2099	*puEsp = RT_LOWORD(u32Tmp);
2100	*pSelSS = RT_HIWORD(u32Tmp);
2101	return VINF_SUCCESS;
2102	}
2103	break;
2104	}
2105
2106	/*
2107	* 32-bit TSS (X86TSS32).
2108	*/
2109	case X86_SEL_TYPE_SYS_386_TSS_AVAIL: AssertFailed();
2110	case X86_SEL_TYPE_SYS_386_TSS_BUSY:
2111	{
2112	uint32_t off = uCpl * 8 + 4;
2113	if (off + 7 > pCtx->tr.u32Limit)
2114	{
2115	Log(("LoadStackFromTss32Or16: out of bounds! uCpl=%d, u32Limit=%#x TSS16\n", uCpl, pCtx->tr.u32Limit));
2116	return iemRaiseTaskSwitchFaultCurrentTSS(pIemCpu);
2117	}
2118
2119	uint64_t u64Tmp;
2120	rcStrict = iemMemFetchSysU64(pIemCpu, &u64Tmp, UINT8_MAX, pCtx->tr.u64Base + off);
2121	if (rcStrict == VINF_SUCCESS)
2122	{
2123	*puEsp = u64Tmp & UINT32_MAX;
2124	*pSelSS = (RTSEL)(u64Tmp >> 32);
2125	return VINF_SUCCESS;
2126	}
2127	break;
2128	}
2129
2130	default:
2131	AssertFailedReturn(VERR_INTERNAL_ERROR_2);
2132	}
2133	return rcStrict;
2134	}
2135
2136
2137	/**
2138	* Loads the specified stack pointer from the 64-bit TSS.
2139	*
2140	* @returns VBox strict status code.
2141	* @param pIemCpu The IEM per CPU instance data.
2142	* @param pCtx The CPU context.
2143	* @param uCpl The CPL to load the stack for.
2144	* @param uIst The interrupt stack table index, 0 if to use uCpl.
2145	* @param puRsp Where to return the new stack pointer.
2146	*/
2147	static VBOXSTRICTRC iemRaiseLoadStackFromTss64(PIEMCPU pIemCpu, PCCPUMCTX pCtx, uint8_t uCpl, uint8_t uIst,
2148	uint64_t *puRsp)
2149	{
2150	Assert(uCpl < 4);
2151	Assert(uIst < 8);
2152	puRsp = 0; / make gcc happy */
2153
2154	AssertReturn(pCtx->tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY, VERR_INTERNAL_ERROR_2);
2155
2156	uint32_t off;
2157	if (uIst)
2158	off = (uIst - 1) * sizeof(uint64_t) + RT_OFFSETOF(X86TSS64, ist1);
2159	else
2160	off = uCpl * sizeof(uint64_t) + RT_OFFSETOF(X86TSS64, rsp0);
2161	if (off + sizeof(uint64_t) > pCtx->tr.u32Limit)
2162	{
2163	Log(("iemRaiseLoadStackFromTss64: out of bounds! uCpl=%d uIst=%d, u32Limit=%#x\n", uCpl, uIst, pCtx->tr.u32Limit));
2164	return iemRaiseTaskSwitchFaultCurrentTSS(pIemCpu);
2165	}
2166
2167	return iemMemFetchSysU64(pIemCpu, puRsp, UINT8_MAX, pCtx->tr.u64Base + off);
2168	}
2169
2170
2171	/**
2172	* Adjust the CPU state according to the exception being raised.
2173	*
2174	* @param pCtx The CPU context.
2175	* @param u8Vector The exception that has been raised.
2176	*/
2177	DECLINLINE(void) iemRaiseXcptAdjustState(PCPUMCTX pCtx, uint8_t u8Vector)
2178	{
2179	switch (u8Vector)
2180	{
2181	case X86_XCPT_DB:
2182	pCtx->dr[7] &= ~X86_DR7_GD;
2183	break;
2184	/** @todo Read the AMD and Intel exception reference... */
2185	}
2186	}
2187
2188
2189	/**
2190	* Implements exceptions and interrupts for real mode.
2191	*
2192	* @returns VBox strict status code.
2193	* @param pIemCpu The IEM per CPU instance data.
2194	* @param pCtx The CPU context.
2195	* @param cbInstr The number of bytes to offset rIP by in the return
2196	* address.
2197	* @param u8Vector The interrupt / exception vector number.
2198	* @param fFlags The flags.
2199	* @param uErr The error value if IEM_XCPT_FLAGS_ERR is set.
2200	* @param uCr2 The CR2 value if IEM_XCPT_FLAGS_CR2 is set.
2201	*/
2202	static VBOXSTRICTRC
2203	iemRaiseXcptOrIntInRealMode(PIEMCPU pIemCpu,
2204	PCPUMCTX pCtx,
2205	uint8_t cbInstr,
2206	uint8_t u8Vector,
2207	uint32_t fFlags,
2208	uint16_t uErr,
2209	uint64_t uCr2)
2210	{
2211	AssertReturn(pIemCpu->enmCpuMode == IEMMODE_16BIT, VERR_INTERNAL_ERROR_3);
2212	NOREF(uErr); NOREF(uCr2);
2213
2214	/*
2215	* Read the IDT entry.
2216	*/
2217	if (pCtx->idtr.cbIdt < UINT32_C(4) * u8Vector + 3)
2218	{
2219	Log(("RaiseXcptOrIntInRealMode: %#x is out of bounds (%#x)\n", u8Vector, pCtx->idtr.cbIdt));
2220	return iemRaiseGeneralProtectionFault(pIemCpu, X86_TRAP_ERR_IDT \| ((uint16_t)u8Vector << X86_TRAP_ERR_SEL_SHIFT));
2221	}
2222	RTFAR16 Idte;
2223	VBOXSTRICTRC rcStrict = iemMemFetchDataU32(pIemCpu, (uint32_t *)&Idte, UINT8_MAX,
2224	pCtx->idtr.pIdt + UINT32_C(4) * u8Vector);
2225	if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
2226	return rcStrict;
2227
2228	/*
2229	* Push the stack frame.
2230	*/
2231	uint16_t *pu16Frame;
2232	uint64_t uNewRsp;
2233	rcStrict = iemMemStackPushBeginSpecial(pIemCpu, 6, (void **)&pu16Frame, &uNewRsp);
2234	if (rcStrict != VINF_SUCCESS)
2235	return rcStrict;
2236
2237	uint32_t fEfl = IEMMISC_GET_EFL(pIemCpu, pCtx);
2238	pu16Frame[2] = (uint16_t)fEfl;
2239	pu16Frame[1] = (uint16_t)pCtx->cs.Sel;
2240	pu16Frame[0] = (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT) ? pCtx->ip + cbInstr : pCtx->ip;
2241	rcStrict = iemMemStackPushCommitSpecial(pIemCpu, pu16Frame, uNewRsp);
2242	if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
2243	return rcStrict;
2244
2245	/*
2246	* Load the vector address into cs:ip and make exception specific state
2247	* adjustments.
2248	*/
2249	pCtx->cs.Sel = Idte.sel;
2250	pCtx->cs.ValidSel = Idte.sel;
2251	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2252	pCtx->cs.u64Base = (uint32_t)Idte.sel << 4;
2253	/** @todo do we load attribs and limit as well? Should we check against limit like far jump? */
2254	pCtx->rip = Idte.off;
2255	fEfl &= ~X86_EFL_IF;
2256	IEMMISC_SET_EFL(pIemCpu, pCtx, fEfl);
2257
2258	/** @todo do we actually do this in real mode? */
2259	if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
2260	iemRaiseXcptAdjustState(pCtx, u8Vector);
2261
2262	return fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT ? VINF_IEM_RAISED_XCPT : VINF_SUCCESS;
2263	}
2264
2265
2266	/**
2267	* Loads a NULL data selector into when coming from V8086 mode.
2268	*
2269	* @param pIemCpu The IEM per CPU instance data.
2270	* @param pSReg Pointer to the segment register.
2271	*/
2272	static void iemHlpLoadNullDataSelectorOnV86Xcpt(PIEMCPU pIemCpu, PCPUMSELREG pSReg)
2273	{
2274	pSReg->Sel = 0;
2275	pSReg->ValidSel = 0;
2276	if (IEM_IS_GUEST_CPU_INTEL(pIemCpu) && !IEM_FULL_VERIFICATION_REM_ENABLED(pIemCpu))
2277	{
2278	/* VT-x (Intel 3960x) doesn't change the base and limit, clears and sets the following attributes */
2279	pSReg->Attr.u &= X86DESCATTR_DT \| X86DESCATTR_TYPE \| X86DESCATTR_DPL \| X86DESCATTR_G \| X86DESCATTR_D;
2280	pSReg->Attr.u \|= X86DESCATTR_UNUSABLE;
2281	}
2282	else
2283	{
2284	pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
2285	/** @todo check this on AMD-V */
2286	pSReg->u64Base = 0;
2287	pSReg->u32Limit = 0;
2288	}
2289	}
2290
2291
2292	/**
2293	* Loads a segment selector during a task switch in V8086 mode.
2294	*
2295	* @param pIemCpu The IEM per CPU instance data.
2296	* @param pSReg Pointer to the segment register.
2297	* @param uSel The selector value to load.
2298	*/
2299	static void iemHlpLoadSelectorInV86Mode(PIEMCPU pIemCpu, PCPUMSELREG pSReg, uint16_t uSel)
2300	{
2301	/* See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers". */
2302	pSReg->Sel = uSel;
2303	pSReg->ValidSel = uSel;
2304	pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
2305	pSReg->u64Base = uSel << 4;
2306	pSReg->u32Limit = 0xffff;
2307	pSReg->Attr.u = 0xf3;
2308	}
2309
2310
2311	/**
2312	* Loads a NULL data selector into a selector register, both the hidden and
2313	* visible parts, in protected mode.
2314	*
2315	* @param pIemCpu The IEM state of the calling EMT.
2316	* @param pSReg Pointer to the segment register.
2317	* @param uRpl The RPL.
2318	*/
2319	static void iemHlpLoadNullDataSelectorProt(PIEMCPU pIemCpu, PCPUMSELREG pSReg, RTSEL uRpl)
2320	{
2321	/** @todo Testcase: write a testcase checking what happends when loading a NULL
2322	* data selector in protected mode. */
2323	pSReg->Sel = uRpl;
2324	pSReg->ValidSel = uRpl;
2325	pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
2326	if (IEM_IS_GUEST_CPU_INTEL(pIemCpu) && !IEM_FULL_VERIFICATION_REM_ENABLED(pIemCpu))
2327	{
2328	/* VT-x (Intel 3960x) observed doing something like this. */
2329	pSReg->Attr.u = X86DESCATTR_UNUSABLE \| X86DESCATTR_G \| X86DESCATTR_D \| (pIemCpu->uCpl << X86DESCATTR_DPL_SHIFT);
2330	pSReg->u32Limit = UINT32_MAX;
2331	pSReg->u64Base = 0;
2332	}
2333	else
2334	{
2335	pSReg->Attr.u = X86DESCATTR_UNUSABLE;
2336	pSReg->u32Limit = 0;
2337	pSReg->u64Base = 0;
2338	}
2339	}
2340
2341
2342	/**
2343	* Loads a segment selector during a task switch in protected mode. In this task
2344	* switch scenario, we would throw #TS exceptions rather than #GPs.
2345	*
2346	* @returns VBox strict status code.
2347	* @param pIemCpu The IEM per CPU instance data.
2348	* @param pSReg Pointer to the segment register.
2349	* @param uSel The new selector value.
2350	*
2351	* @remarks This does -NOT- handle CS or SS.
2352	* @remarks This expects pIemCpu->uCpl to be up to date.
2353	*/
2354	static VBOXSTRICTRC iemHlpTaskSwitchLoadDataSelectorInProtMode(PIEMCPU pIemCpu, PCPUMSELREG pSReg, uint16_t uSel)
2355	{
2356	Assert(pIemCpu->enmCpuMode != IEMMODE_64BIT);
2357
2358	/* Null data selector. */
2359	if (!(uSel & X86_SEL_MASK_OFF_RPL))
2360	{
2361	iemHlpLoadNullDataSelectorProt(pIemCpu, pSReg, uSel);
2362	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(IEMCPU_TO_VMCPU(pIemCpu), pSReg));
2363	CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_HIDDEN_SEL_REGS);
2364	return VINF_SUCCESS;
2365	}
2366
2367	/* Fetch the descriptor. */
2368	IEMSELDESC Desc;
2369	VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pIemCpu, &Desc, uSel, X86_XCPT_TS);
2370	if (rcStrict != VINF_SUCCESS)
2371	{
2372	Log(("iemHlpTaskSwitchLoadDataSelectorInProtMode: failed to fetch selector. uSel=%u rc=%Rrc\n", uSel,
2373	VBOXSTRICTRC_VAL(rcStrict)));
2374	return rcStrict;
2375	}
2376
2377	/* Must be a data segment or readable code segment. */
2378	if ( !Desc.Legacy.Gen.u1DescType
2379	\|\| (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
2380	{
2381	Log(("iemHlpTaskSwitchLoadDataSelectorInProtMode: invalid segment type. uSel=%u Desc.u4Type=%#x\n", uSel,
2382	Desc.Legacy.Gen.u4Type));
2383	return iemRaiseTaskSwitchFaultWithErr(pIemCpu, uSel & X86_SEL_MASK_OFF_RPL);
2384	}
2385
2386	/* Check privileges for data segments and non-conforming code segments. */
2387	if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
2388	!= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
2389	{
2390	/* The RPL and the new CPL must be less than or equal to the DPL. */
2391	if ( (unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl
2392	\|\| (pIemCpu->uCpl > Desc.Legacy.Gen.u2Dpl))
2393	{
2394	Log(("iemHlpTaskSwitchLoadDataSelectorInProtMode: Invalid priv. uSel=%u uSel.RPL=%u DPL=%u CPL=%u\n",
2395	uSel, (uSel & X86_SEL_RPL), Desc.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
2396	return iemRaiseTaskSwitchFaultWithErr(pIemCpu, uSel & X86_SEL_MASK_OFF_RPL);
2397	}
2398	}
2399
2400	/* Is it there? */
2401	if (!Desc.Legacy.Gen.u1Present)
2402	{
2403	Log(("iemHlpTaskSwitchLoadDataSelectorInProtMode: Segment not present. uSel=%u\n", uSel));
2404	return iemRaiseSelectorNotPresentWithErr(pIemCpu, uSel & X86_SEL_MASK_OFF_RPL);
2405	}
2406
2407	/* The base and limit. */
2408	uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
2409	uint64_t u64Base = X86DESC_BASE(&Desc.Legacy);
2410
2411	/*
2412	* Ok, everything checked out fine. Now set the accessed bit before
2413	* committing the result into the registers.
2414	*/
2415	if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2416	{
2417	rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uSel);
2418	if (rcStrict != VINF_SUCCESS)
2419	return rcStrict;
2420	Desc.Legacy.Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
2421	}
2422
2423	/* Commit */
2424	pSReg->Sel = uSel;
2425	pSReg->Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
2426	pSReg->u32Limit = cbLimit;
2427	pSReg->u64Base = u64Base; /** @todo testcase/investigate: seen claims that the upper half of the base remains unchanged... */
2428	pSReg->ValidSel = uSel;
2429	pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
2430	if (IEM_IS_GUEST_CPU_INTEL(pIemCpu) && !IEM_FULL_VERIFICATION_REM_ENABLED(pIemCpu))
2431	pSReg->Attr.u &= ~X86DESCATTR_UNUSABLE;
2432
2433	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(IEMCPU_TO_VMCPU(pIemCpu), pSReg));
2434	CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_HIDDEN_SEL_REGS);
2435	return VINF_SUCCESS;
2436	}
2437
2438
2439	/**
2440	* Performs a task switch.
2441	*
2442	* If the task switch is the result of a JMP, CALL or IRET instruction, the
2443	* caller is responsible for performing the necessary checks (like DPL, TSS
2444	* present etc.) which are specific to JMP/CALL/IRET. See Intel Instruction
2445	* reference for JMP, CALL, IRET.
2446	*
2447	* If the task switch is the due to a software interrupt or hardware exception,
2448	* the caller is responsible for validating the TSS selector and descriptor. See
2449	* Intel Instruction reference for INT n.
2450	*
2451	* @returns VBox strict status code.
2452	* @param pIemCpu The IEM per CPU instance data.
2453	* @param pCtx The CPU context.
2454	* @param enmTaskSwitch What caused this task switch.
2455	* @param uNextEip The EIP effective after the task switch.
2456	* @param fFlags The flags.
2457	* @param uErr The error value if IEM_XCPT_FLAGS_ERR is set.
2458	* @param uCr2 The CR2 value if IEM_XCPT_FLAGS_CR2 is set.
2459	* @param SelTSS The TSS selector of the new task.
2460	* @param pNewDescTSS Pointer to the new TSS descriptor.
2461	*/
2462	static VBOXSTRICTRC iemTaskSwitch(PIEMCPU pIemCpu,
2463	PCPUMCTX pCtx,
2464	IEMTASKSWITCH enmTaskSwitch,
2465	uint32_t uNextEip,
2466	uint32_t fFlags,
2467	uint16_t uErr,
2468	uint64_t uCr2,
2469	RTSEL SelTSS,
2470	PIEMSELDESC pNewDescTSS)
2471	{
2472	Assert(!IEM_IS_REAL_MODE(pIemCpu));
2473	Assert(pIemCpu->enmCpuMode != IEMMODE_64BIT);
2474
2475	uint32_t const uNewTSSType = pNewDescTSS->Legacy.Gate.u4Type;
2476	Assert( uNewTSSType == X86_SEL_TYPE_SYS_286_TSS_AVAIL
2477	\|\| uNewTSSType == X86_SEL_TYPE_SYS_286_TSS_BUSY
2478	\|\| uNewTSSType == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2479	\|\| uNewTSSType == X86_SEL_TYPE_SYS_386_TSS_BUSY);
2480
2481	bool const fIsNewTSS386 = ( uNewTSSType == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2482	\|\| uNewTSSType == X86_SEL_TYPE_SYS_386_TSS_BUSY);
2483
2484	Log(("iemTaskSwitch: enmTaskSwitch=%u NewTSS=%#x fIsNewTSS386=%RTbool EIP=%#RGv uNextEip=%#RGv\n", enmTaskSwitch, SelTSS,
2485	fIsNewTSS386, pCtx->eip, uNextEip));
2486
2487	/* Update CR2 in case it's a page-fault. */
2488	/** @todo This should probably be done much earlier in IEM/PGM. See
2489	* @bugref{5653} comment #49. */
2490	if (fFlags & IEM_XCPT_FLAGS_CR2)
2491	pCtx->cr2 = uCr2;
2492
2493	/*
2494	* Check the new TSS limit. See Intel spec. 6.15 "Exception and Interrupt Reference"
2495	* subsection "Interrupt 10 - Invalid TSS Exception (#TS)".
2496	*/
2497	uint32_t const uNewTSSLimit = pNewDescTSS->Legacy.Gen.u16LimitLow \| (pNewDescTSS->Legacy.Gen.u4LimitHigh << 16);
2498	uint32_t const uNewTSSLimitMin = fIsNewTSS386 ? X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN : X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN;
2499	if (uNewTSSLimit < uNewTSSLimitMin)
2500	{
2501	Log(("iemTaskSwitch: Invalid new TSS limit. enmTaskSwitch=%u uNewTSSLimit=%#x uNewTSSLimitMin=%#x -> #TS\n",
2502	enmTaskSwitch, uNewTSSLimit, uNewTSSLimitMin));
2503	return iemRaiseTaskSwitchFaultWithErr(pIemCpu, SelTSS & X86_SEL_MASK_OFF_RPL);
2504	}
2505
2506	/*
2507	* Check the current TSS limit. The last written byte to the current TSS during the
2508	* task switch will be 2 bytes at offset 0x5C (32-bit) and 1 byte at offset 0x28 (16-bit).
2509	* See Intel spec. 7.2.1 "Task-State Segment (TSS)" for static and dynamic fields.
2510	*
2511	* The AMD docs doesn't mention anything about limit checks with LTR which suggests you can
2512	* end up with smaller than "legal" TSS limits.
2513	*/
2514	uint32_t const uCurTSSLimit = pCtx->tr.u32Limit;
2515	uint32_t const uCurTSSLimitMin = fIsNewTSS386 ? 0x5F : 0x29;
2516	if (uCurTSSLimit < uCurTSSLimitMin)
2517	{
2518	Log(("iemTaskSwitch: Invalid current TSS limit. enmTaskSwitch=%u uCurTSSLimit=%#x uCurTSSLimitMin=%#x -> #TS\n",
2519	enmTaskSwitch, uCurTSSLimit, uCurTSSLimitMin));
2520	return iemRaiseTaskSwitchFaultWithErr(pIemCpu, SelTSS & X86_SEL_MASK_OFF_RPL);
2521	}
2522
2523	/*
2524	* Verify that the new TSS can be accessed and map it. Map only the required contents
2525	* and not the entire TSS.
2526	*/
2527	void *pvNewTSS;
2528	uint32_t cbNewTSS = uNewTSSLimitMin + 1;
2529	RTGCPTR GCPtrNewTSS = X86DESC_BASE(&pNewDescTSS->Legacy);
2530	AssertCompile(RTASSERT_OFFSET_OF(X86TSS32, IntRedirBitmap) == X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
2531	/** @todo Handle if the TSS crosses a page boundary. Intel specifies that it may
2532	* not perform correct translation if this happens. See Intel spec. 7.2.1
2533	* "Task-State Segment" */
2534	VBOXSTRICTRC rcStrict = iemMemMap(pIemCpu, &pvNewTSS, cbNewTSS, UINT8_MAX, GCPtrNewTSS, IEM_ACCESS_SYS_RW);
2535	if (rcStrict != VINF_SUCCESS)
2536	{
2537	Log(("iemTaskSwitch: Failed to read new TSS. enmTaskSwitch=%u cbNewTSS=%u uNewTSSLimit=%u rc=%Rrc\n", enmTaskSwitch,
2538	cbNewTSS, uNewTSSLimit, VBOXSTRICTRC_VAL(rcStrict)));
2539	return rcStrict;
2540	}
2541
2542	/*
2543	* Clear the busy bit in current task's TSS descriptor if it's a task switch due to JMP/IRET.
2544	*/
2545	uint32_t u32EFlags = pCtx->eflags.u32;
2546	if ( enmTaskSwitch == IEMTASKSWITCH_JUMP
2547	\|\| enmTaskSwitch == IEMTASKSWITCH_IRET)
2548	{
2549	PX86DESC pDescCurTSS;
2550	rcStrict = iemMemMap(pIemCpu, (void *)&pDescCurTSS, sizeof(pDescCurTSS), UINT8_MAX,
2551	pCtx->gdtr.pGdt + (pCtx->tr.Sel & X86_SEL_MASK), IEM_ACCESS_SYS_RW);
2552	if (rcStrict != VINF_SUCCESS)
2553	{
2554	Log(("iemTaskSwitch: Failed to read new TSS descriptor in GDT. enmTaskSwitch=%u pGdt=%#RX64 rc=%Rrc\n",
2555	enmTaskSwitch, pCtx->gdtr.pGdt, VBOXSTRICTRC_VAL(rcStrict)));
2556	return rcStrict;
2557	}
2558
2559	pDescCurTSS->Gate.u4Type &= ~X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
2560	rcStrict = iemMemCommitAndUnmap(pIemCpu, pDescCurTSS, IEM_ACCESS_SYS_RW);
2561	if (rcStrict != VINF_SUCCESS)
2562	{
2563	Log(("iemTaskSwitch: Failed to commit new TSS descriptor in GDT. enmTaskSwitch=%u pGdt=%#RX64 rc=%Rrc\n",
2564	enmTaskSwitch, pCtx->gdtr.pGdt, VBOXSTRICTRC_VAL(rcStrict)));
2565	return rcStrict;
2566	}
2567
2568	/* Clear EFLAGS.NT (Nested Task) in the eflags memory image, if it's a task switch due to an IRET. */
2569	if (enmTaskSwitch == IEMTASKSWITCH_IRET)
2570	{
2571	Assert( uNewTSSType == X86_SEL_TYPE_SYS_286_TSS_BUSY
2572	\|\| uNewTSSType == X86_SEL_TYPE_SYS_386_TSS_BUSY);
2573	u32EFlags &= ~X86_EFL_NT;
2574	}
2575	}
2576
2577	/*
2578	* Save the CPU state into the current TSS.
2579	*/
2580	RTGCPTR GCPtrCurTSS = pCtx->tr.u64Base;
2581	if (GCPtrNewTSS == GCPtrCurTSS)
2582	{
2583	Log(("iemTaskSwitch: Switching to the same TSS! enmTaskSwitch=%u GCPtr[Cur\|New]TSS=%#RGv\n", enmTaskSwitch, GCPtrCurTSS));
2584	Log(("uCurCr3=%#x uCurEip=%#x uCurEflags=%#x uCurEax=%#x uCurEsp=%#x uCurEbp=%#x uCurCS=%#04x uCurSS=%#04x uCurLdt=%#x\n",
2585	pCtx->cr3, pCtx->eip, pCtx->eflags.u32, pCtx->eax, pCtx->esp, pCtx->ebp, pCtx->cs.Sel, pCtx->ss.Sel, pCtx->ldtr.Sel));
2586	}
2587	if (fIsNewTSS386)
2588	{
2589	/*
2590	* Verify that the current TSS (32-bit) can be accessed, only the minimum required size.
2591	* See Intel spec. 7.2.1 "Task-State Segment (TSS)" for static and dynamic fields.
2592	*/
2593	void *pvCurTSS32;
2594	uint32_t offCurTSS = RT_OFFSETOF(X86TSS32, eip);
2595	uint32_t cbCurTSS = RT_OFFSETOF(X86TSS32, selLdt) - RT_OFFSETOF(X86TSS32, eip);
2596	AssertCompile(RTASSERT_OFFSET_OF(X86TSS32, selLdt) - RTASSERT_OFFSET_OF(X86TSS32, eip) == 64);
2597	rcStrict = iemMemMap(pIemCpu, &pvCurTSS32, cbCurTSS, UINT8_MAX, GCPtrCurTSS + offCurTSS, IEM_ACCESS_SYS_RW);
2598	if (rcStrict != VINF_SUCCESS)
2599	{
2600	Log(("iemTaskSwitch: Failed to read current 32-bit TSS. enmTaskSwitch=%u GCPtrCurTSS=%#RGv cb=%u rc=%Rrc\n",
2601	enmTaskSwitch, GCPtrCurTSS, cbCurTSS, VBOXSTRICTRC_VAL(rcStrict)));
2602	return rcStrict;
2603	}
2604
2605	/* !! WARNING !! Access -only- the members (dynamic fields) that are mapped, i.e interval [offCurTSS..cbCurTSS). */
2606	PX86TSS32 pCurTSS32 = (PX86TSS32)((uintptr_t)pvCurTSS32 - offCurTSS);
2607	pCurTSS32->eip = uNextEip;
2608	pCurTSS32->eflags = u32EFlags;
2609	pCurTSS32->eax = pCtx->eax;
2610	pCurTSS32->ecx = pCtx->ecx;
2611	pCurTSS32->edx = pCtx->edx;
2612	pCurTSS32->ebx = pCtx->ebx;
2613	pCurTSS32->esp = pCtx->esp;
2614	pCurTSS32->ebp = pCtx->ebp;
2615	pCurTSS32->esi = pCtx->esi;
2616	pCurTSS32->edi = pCtx->edi;
2617	pCurTSS32->es = pCtx->es.Sel;
2618	pCurTSS32->cs = pCtx->cs.Sel;
2619	pCurTSS32->ss = pCtx->ss.Sel;
2620	pCurTSS32->ds = pCtx->ds.Sel;
2621	pCurTSS32->fs = pCtx->fs.Sel;
2622	pCurTSS32->gs = pCtx->gs.Sel;
2623
2624	rcStrict = iemMemCommitAndUnmap(pIemCpu, pvCurTSS32, IEM_ACCESS_SYS_RW);
2625	if (rcStrict != VINF_SUCCESS)
2626	{
2627	Log(("iemTaskSwitch: Failed to commit current 32-bit TSS. enmTaskSwitch=%u rc=%Rrc\n", enmTaskSwitch,
2628	VBOXSTRICTRC_VAL(rcStrict)));
2629	return rcStrict;
2630	}
2631	}
2632	else
2633	{
2634	/*
2635	* Verify that the current TSS (16-bit) can be accessed. Again, only the minimum required size.
2636	*/
2637	void *pvCurTSS16;
2638	uint32_t offCurTSS = RT_OFFSETOF(X86TSS16, ip);
2639	uint32_t cbCurTSS = RT_OFFSETOF(X86TSS16, selLdt) - RT_OFFSETOF(X86TSS16, ip);
2640	AssertCompile(RTASSERT_OFFSET_OF(X86TSS16, selLdt) - RTASSERT_OFFSET_OF(X86TSS16, ip) == 28);
2641	rcStrict = iemMemMap(pIemCpu, &pvCurTSS16, cbCurTSS, UINT8_MAX, GCPtrCurTSS + offCurTSS, IEM_ACCESS_SYS_RW);
2642	if (rcStrict != VINF_SUCCESS)
2643	{
2644	Log(("iemTaskSwitch: Failed to read current 16-bit TSS. enmTaskSwitch=%u GCPtrCurTSS=%#RGv cb=%u rc=%Rrc\n",
2645	enmTaskSwitch, GCPtrCurTSS, cbCurTSS, VBOXSTRICTRC_VAL(rcStrict)));
2646	return rcStrict;
2647	}
2648
2649	/* !! WARNING !! Access -only- the members (dynamic fields) that are mapped, i.e interval [offCurTSS..cbCurTSS). */
2650	PX86TSS16 pCurTSS16 = (PX86TSS16)((uintptr_t)pvCurTSS16 - offCurTSS);
2651	pCurTSS16->ip = uNextEip;
2652	pCurTSS16->flags = u32EFlags;
2653	pCurTSS16->ax = pCtx->ax;
2654	pCurTSS16->cx = pCtx->cx;
2655	pCurTSS16->dx = pCtx->dx;
2656	pCurTSS16->bx = pCtx->bx;
2657	pCurTSS16->sp = pCtx->sp;
2658	pCurTSS16->bp = pCtx->bp;
2659	pCurTSS16->si = pCtx->si;
2660	pCurTSS16->di = pCtx->di;
2661	pCurTSS16->es = pCtx->es.Sel;
2662	pCurTSS16->cs = pCtx->cs.Sel;
2663	pCurTSS16->ss = pCtx->ss.Sel;
2664	pCurTSS16->ds = pCtx->ds.Sel;
2665
2666	rcStrict = iemMemCommitAndUnmap(pIemCpu, pvCurTSS16, IEM_ACCESS_SYS_RW);
2667	if (rcStrict != VINF_SUCCESS)
2668	{
2669	Log(("iemTaskSwitch: Failed to commit current 16-bit TSS. enmTaskSwitch=%u rc=%Rrc\n", enmTaskSwitch,
2670	VBOXSTRICTRC_VAL(rcStrict)));
2671	return rcStrict;
2672	}
2673	}
2674
2675	/*
2676	* Update the previous task link field for the new TSS, if the task switch is due to a CALL/INT_XCPT.
2677	*/
2678	if ( enmTaskSwitch == IEMTASKSWITCH_CALL
2679	\|\| enmTaskSwitch == IEMTASKSWITCH_INT_XCPT)
2680	{
2681	/* 16 or 32-bit TSS doesn't matter, we only access the first, common 16-bit field (selPrev) here. */
2682	PX86TSS32 pNewTSS = (PX86TSS32)pvNewTSS;
2683	pNewTSS->selPrev = pCtx->tr.Sel;
2684	}
2685
2686	/*
2687	* Read the state from the new TSS into temporaries. Setting it immediately as the new CPU state is tricky,
2688	* it's done further below with error handling (e.g. CR3 changes will go through PGM).
2689	*/
2690	uint32_t uNewCr3, uNewEip, uNewEflags, uNewEax, uNewEcx, uNewEdx, uNewEbx, uNewEsp, uNewEbp, uNewEsi, uNewEdi;
2691	uint16_t uNewES, uNewCS, uNewSS, uNewDS, uNewFS, uNewGS, uNewLdt;
2692	bool fNewDebugTrap;
2693	if (fIsNewTSS386)
2694	{
2695	PX86TSS32 pNewTSS32 = (PX86TSS32)pvNewTSS;
2696	uNewCr3 = (pCtx->cr0 & X86_CR0_PG) ? pNewTSS32->cr3 : 0;
2697	uNewEip = pNewTSS32->eip;
2698	uNewEflags = pNewTSS32->eflags;
2699	uNewEax = pNewTSS32->eax;
2700	uNewEcx = pNewTSS32->ecx;
2701	uNewEdx = pNewTSS32->edx;
2702	uNewEbx = pNewTSS32->ebx;
2703	uNewEsp = pNewTSS32->esp;
2704	uNewEbp = pNewTSS32->ebp;
2705	uNewEsi = pNewTSS32->esi;
2706	uNewEdi = pNewTSS32->edi;
2707	uNewES = pNewTSS32->es;
2708	uNewCS = pNewTSS32->cs;
2709	uNewSS = pNewTSS32->ss;
2710	uNewDS = pNewTSS32->ds;
2711	uNewFS = pNewTSS32->fs;
2712	uNewGS = pNewTSS32->gs;
2713	uNewLdt = pNewTSS32->selLdt;
2714	fNewDebugTrap = RT_BOOL(pNewTSS32->fDebugTrap);
2715	}
2716	else
2717	{
2718	PX86TSS16 pNewTSS16 = (PX86TSS16)pvNewTSS;
2719	uNewCr3 = 0;
2720	uNewEip = pNewTSS16->ip;
2721	uNewEflags = pNewTSS16->flags;
2722	uNewEax = UINT32_C(0xffff0000) \| pNewTSS16->ax;
2723	uNewEcx = UINT32_C(0xffff0000) \| pNewTSS16->cx;
2724	uNewEdx = UINT32_C(0xffff0000) \| pNewTSS16->dx;
2725	uNewEbx = UINT32_C(0xffff0000) \| pNewTSS16->bx;
2726	uNewEsp = UINT32_C(0xffff0000) \| pNewTSS16->sp;
2727	uNewEbp = UINT32_C(0xffff0000) \| pNewTSS16->bp;
2728	uNewEsi = UINT32_C(0xffff0000) \| pNewTSS16->si;
2729	uNewEdi = UINT32_C(0xffff0000) \| pNewTSS16->di;
2730	uNewES = pNewTSS16->es;
2731	uNewCS = pNewTSS16->cs;
2732	uNewSS = pNewTSS16->ss;
2733	uNewDS = pNewTSS16->ds;
2734	uNewFS = 0;
2735	uNewGS = 0;
2736	uNewLdt = pNewTSS16->selLdt;
2737	fNewDebugTrap = false;
2738	}
2739
2740	if (GCPtrNewTSS == GCPtrCurTSS)
2741	Log(("uNewCr3=%#x uNewEip=%#x uNewEflags=%#x uNewEax=%#x uNewEsp=%#x uNewEbp=%#x uNewCS=%#04x uNewSS=%#04x uNewLdt=%#x\n",
2742	uNewCr3, uNewEip, uNewEflags, uNewEax, uNewEsp, uNewEbp, uNewCS, uNewSS, uNewLdt));
2743
2744	/*
2745	* We're done accessing the new TSS.
2746	*/
2747	rcStrict = iemMemCommitAndUnmap(pIemCpu, pvNewTSS, IEM_ACCESS_SYS_RW);
2748	if (rcStrict != VINF_SUCCESS)
2749	{
2750	Log(("iemTaskSwitch: Failed to commit new TSS. enmTaskSwitch=%u rc=%Rrc\n", enmTaskSwitch, VBOXSTRICTRC_VAL(rcStrict)));
2751	return rcStrict;
2752	}
2753
2754	/*
2755	* Set the busy bit in the new TSS descriptor, if the task switch is a JMP/CALL/INT_XCPT.
2756	*/
2757	if (enmTaskSwitch != IEMTASKSWITCH_IRET)
2758	{
2759	rcStrict = iemMemMap(pIemCpu, (void *)&pNewDescTSS, sizeof(pNewDescTSS), UINT8_MAX,
2760	pCtx->gdtr.pGdt + (SelTSS & X86_SEL_MASK), IEM_ACCESS_SYS_RW);
2761	if (rcStrict != VINF_SUCCESS)
2762	{
2763	Log(("iemTaskSwitch: Failed to read new TSS descriptor in GDT (2). enmTaskSwitch=%u pGdt=%#RX64 rc=%Rrc\n",
2764	enmTaskSwitch, pCtx->gdtr.pGdt, VBOXSTRICTRC_VAL(rcStrict)));
2765	return rcStrict;
2766	}
2767
2768	/* Check that the descriptor indicates the new TSS is available (not busy). */
2769	AssertMsg( pNewDescTSS->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL
2770	\|\| pNewDescTSS->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL,
2771	("Invalid TSS descriptor type=%#x", pNewDescTSS->Legacy.Gate.u4Type));
2772
2773	pNewDescTSS->Legacy.Gate.u4Type \|= X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
2774	rcStrict = iemMemCommitAndUnmap(pIemCpu, pNewDescTSS, IEM_ACCESS_SYS_RW);
2775	if (rcStrict != VINF_SUCCESS)
2776	{
2777	Log(("iemTaskSwitch: Failed to commit new TSS descriptor in GDT (2). enmTaskSwitch=%u pGdt=%#RX64 rc=%Rrc\n",
2778	enmTaskSwitch, pCtx->gdtr.pGdt, VBOXSTRICTRC_VAL(rcStrict)));
2779	return rcStrict;
2780	}
2781	}
2782
2783	/*
2784	* From this point on, we're technically in the new task. We will defer exceptions
2785	* until the completion of the task switch but before executing any instructions in the new task.
2786	*/
2787	pCtx->tr.Sel = SelTSS;
2788	pCtx->tr.ValidSel = SelTSS;
2789	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2790	pCtx->tr.Attr.u = X86DESC_GET_HID_ATTR(&pNewDescTSS->Legacy);
2791	pCtx->tr.u32Limit = X86DESC_LIMIT_G(&pNewDescTSS->Legacy);
2792	pCtx->tr.u64Base = X86DESC_BASE(&pNewDescTSS->Legacy);
2793	CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_TR);
2794
2795	/* Set the busy bit in TR. */
2796	pCtx->tr.Attr.n.u4Type \|= X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
2797	/* Set EFLAGS.NT (Nested Task) in the eflags loaded from the new TSS, if it's a task switch due to a CALL/INT_XCPT. */
2798	if ( enmTaskSwitch == IEMTASKSWITCH_CALL
2799	\|\| enmTaskSwitch == IEMTASKSWITCH_INT_XCPT)
2800	{
2801	uNewEflags \|= X86_EFL_NT;
2802	}
2803
2804	pCtx->dr[7] &= ~X86_DR7_LE_ALL; /** @todo Should we clear DR7.LE bit too? */
2805	pCtx->cr0 \|= X86_CR0_TS;
2806	CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_CR0);
2807
2808	pCtx->eip = uNewEip;
2809	pCtx->eax = uNewEax;
2810	pCtx->ecx = uNewEcx;
2811	pCtx->edx = uNewEdx;
2812	pCtx->ebx = uNewEbx;
2813	pCtx->esp = uNewEsp;
2814	pCtx->ebp = uNewEbp;
2815	pCtx->esi = uNewEsi;
2816	pCtx->edi = uNewEdi;
2817
2818	uNewEflags &= X86_EFL_LIVE_MASK;
2819	uNewEflags \|= X86_EFL_RA1_MASK;
2820	IEMMISC_SET_EFL(pIemCpu, pCtx, uNewEflags);
2821
2822	/*
2823	* Switch the selectors here and do the segment checks later. If we throw exceptions, the selectors
2824	* will be valid in the exception handler. We cannot update the hidden parts until we've switched CR3
2825	* due to the hidden part data originating from the guest LDT/GDT which is accessed through paging.
2826	*/
2827	pCtx->es.Sel = uNewES;
2828	pCtx->es.fFlags = CPUMSELREG_FLAGS_STALE;
2829	pCtx->es.Attr.u &= ~X86DESCATTR_P;
2830
2831	pCtx->cs.Sel = uNewCS;
2832	pCtx->cs.fFlags = CPUMSELREG_FLAGS_STALE;
2833	pCtx->cs.Attr.u &= ~X86DESCATTR_P;
2834
2835	pCtx->ss.Sel = uNewSS;
2836	pCtx->ss.fFlags = CPUMSELREG_FLAGS_STALE;
2837	pCtx->ss.Attr.u &= ~X86DESCATTR_P;
2838
2839	pCtx->ds.Sel = uNewDS;
2840	pCtx->ds.fFlags = CPUMSELREG_FLAGS_STALE;
2841	pCtx->ds.Attr.u &= ~X86DESCATTR_P;
2842
2843	pCtx->fs.Sel = uNewFS;
2844	pCtx->fs.fFlags = CPUMSELREG_FLAGS_STALE;
2845	pCtx->fs.Attr.u &= ~X86DESCATTR_P;
2846
2847	pCtx->gs.Sel = uNewGS;
2848	pCtx->gs.fFlags = CPUMSELREG_FLAGS_STALE;
2849	pCtx->gs.Attr.u &= ~X86DESCATTR_P;
2850	CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_HIDDEN_SEL_REGS);
2851
2852	pCtx->ldtr.Sel = uNewLdt;
2853	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_STALE;
2854	pCtx->ldtr.Attr.u &= ~X86DESCATTR_P;
2855	CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_LDTR);
2856
2857	if (IEM_IS_GUEST_CPU_INTEL(pIemCpu) && !IEM_FULL_VERIFICATION_REM_ENABLED(pIemCpu))
2858	{
2859	pCtx->es.Attr.u \|= X86DESCATTR_UNUSABLE;
2860	pCtx->cs.Attr.u \|= X86DESCATTR_UNUSABLE;
2861	pCtx->ss.Attr.u \|= X86DESCATTR_UNUSABLE;
2862	pCtx->ds.Attr.u \|= X86DESCATTR_UNUSABLE;
2863	pCtx->fs.Attr.u \|= X86DESCATTR_UNUSABLE;
2864	pCtx->gs.Attr.u \|= X86DESCATTR_UNUSABLE;
2865	pCtx->ldtr.Attr.u \|= X86DESCATTR_UNUSABLE;
2866	}
2867
2868	/*
2869	* Switch CR3 for the new task.
2870	*/
2871	if ( fIsNewTSS386
2872	&& (pCtx->cr0 & X86_CR0_PG))
2873	{
2874	/** @todo Should we update and flush TLBs only if CR3 value actually changes? */
2875	if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
2876	{
2877	int rc = CPUMSetGuestCR3(IEMCPU_TO_VMCPU(pIemCpu), uNewCr3);
2878	AssertRCSuccessReturn(rc, rc);
2879	}
2880	else
2881	pCtx->cr3 = uNewCr3;
2882
2883	/* Inform PGM. */
2884	if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
2885	{
2886	int rc = PGMFlushTLB(IEMCPU_TO_VMCPU(pIemCpu), pCtx->cr3, !(pCtx->cr4 & X86_CR4_PGE));
2887	AssertRCReturn(rc, rc);
2888	/* ignore informational status codes */
2889	}
2890	CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_CR3);
2891	}
2892
2893	/*
2894	* Switch LDTR for the new task.
2895	*/
2896	if (!(uNewLdt & X86_SEL_MASK_OFF_RPL))
2897	iemHlpLoadNullDataSelectorProt(pIemCpu, &pCtx->ldtr, uNewLdt);
2898	else
2899	{
2900	Assert(!pCtx->ldtr.Attr.n.u1Present); /* Ensures that LDT.TI check passes in iemMemFetchSelDesc() below. */
2901
2902	IEMSELDESC DescNewLdt;
2903	rcStrict = iemMemFetchSelDesc(pIemCpu, &DescNewLdt, uNewLdt, X86_XCPT_TS);
2904	if (rcStrict != VINF_SUCCESS)
2905	{
2906	Log(("iemTaskSwitch: fetching LDT failed. enmTaskSwitch=%u uNewLdt=%u cbGdt=%u rc=%Rrc\n", enmTaskSwitch,
2907	uNewLdt, pCtx->gdtr.cbGdt, VBOXSTRICTRC_VAL(rcStrict)));
2908	return rcStrict;
2909	}
2910	if ( !DescNewLdt.Legacy.Gen.u1Present
2911	\|\| DescNewLdt.Legacy.Gen.u1DescType
2912	\|\| DescNewLdt.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
2913	{
2914	Log(("iemTaskSwitch: Invalid LDT. enmTaskSwitch=%u uNewLdt=%u DescNewLdt.Legacy.u=%#RX64 -> #TS\n", enmTaskSwitch,
2915	uNewLdt, DescNewLdt.Legacy.u));
2916	return iemRaiseTaskSwitchFaultWithErr(pIemCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
2917	}
2918
2919	pCtx->ldtr.ValidSel = uNewLdt;
2920	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2921	pCtx->ldtr.u64Base = X86DESC_BASE(&DescNewLdt.Legacy);
2922	pCtx->ldtr.u32Limit = X86DESC_LIMIT_G(&DescNewLdt.Legacy);
2923	pCtx->ldtr.Attr.u = X86DESC_GET_HID_ATTR(&DescNewLdt.Legacy);
2924	if (IEM_IS_GUEST_CPU_INTEL(pIemCpu) && !IEM_FULL_VERIFICATION_REM_ENABLED(pIemCpu))
2925	pCtx->ldtr.Attr.u &= ~X86DESCATTR_UNUSABLE;
2926	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(IEMCPU_TO_VMCPU(pIemCpu), &pCtx->ldtr));
2927	}
2928
2929	IEMSELDESC DescSS;
2930	if (IEM_IS_V86_MODE(pIemCpu))
2931	{
2932	pIemCpu->uCpl = 3;
2933	iemHlpLoadSelectorInV86Mode(pIemCpu, &pCtx->es, uNewES);
2934	iemHlpLoadSelectorInV86Mode(pIemCpu, &pCtx->cs, uNewCS);
2935	iemHlpLoadSelectorInV86Mode(pIemCpu, &pCtx->ss, uNewSS);
2936	iemHlpLoadSelectorInV86Mode(pIemCpu, &pCtx->ds, uNewDS);
2937	iemHlpLoadSelectorInV86Mode(pIemCpu, &pCtx->fs, uNewFS);
2938	iemHlpLoadSelectorInV86Mode(pIemCpu, &pCtx->gs, uNewGS);
2939	}
2940	else
2941	{
2942	uint8_t uNewCpl = (uNewCS & X86_SEL_RPL);
2943
2944	/*
2945	* Load the stack segment for the new task.
2946	*/
2947	if (!(uNewSS & X86_SEL_MASK_OFF_RPL))
2948	{
2949	Log(("iemTaskSwitch: Null stack segment. enmTaskSwitch=%u uNewSS=%#x -> #TS\n", enmTaskSwitch, uNewSS));
2950	return iemRaiseTaskSwitchFaultWithErr(pIemCpu, uNewSS & X86_SEL_MASK_OFF_RPL);
2951	}
2952
2953	/* Fetch the descriptor. */
2954	rcStrict = iemMemFetchSelDesc(pIemCpu, &DescSS, uNewSS, X86_XCPT_TS);
2955	if (rcStrict != VINF_SUCCESS)
2956	{
2957	Log(("iemTaskSwitch: failed to fetch SS. uNewSS=%#x rc=%Rrc\n", uNewSS,
2958	VBOXSTRICTRC_VAL(rcStrict)));
2959	return rcStrict;
2960	}
2961
2962	/* SS must be a data segment and writable. */
2963	if ( !DescSS.Legacy.Gen.u1DescType
2964	\|\| (DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
2965	\|\| !(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE))
2966	{
2967	Log(("iemTaskSwitch: SS invalid descriptor type. uNewSS=%#x u1DescType=%u u4Type=%#x\n",
2968	uNewSS, DescSS.Legacy.Gen.u1DescType, DescSS.Legacy.Gen.u4Type));
2969	return iemRaiseTaskSwitchFaultWithErr(pIemCpu, uNewSS & X86_SEL_MASK_OFF_RPL);
2970	}
2971
2972	/* The SS.RPL, SS.DPL, CS.RPL (CPL) must be equal. */
2973	if ( (uNewSS & X86_SEL_RPL) != uNewCpl
2974	\|\| DescSS.Legacy.Gen.u2Dpl != uNewCpl)
2975	{
2976	Log(("iemTaskSwitch: Invalid priv. for SS. uNewSS=%#x SS.DPL=%u uNewCpl=%u -> #TS\n", uNewSS, DescSS.Legacy.Gen.u2Dpl,
2977	uNewCpl));
2978	return iemRaiseTaskSwitchFaultWithErr(pIemCpu, uNewSS & X86_SEL_MASK_OFF_RPL);
2979	}
2980
2981	/* Is it there? */
2982	if (!DescSS.Legacy.Gen.u1Present)
2983	{
2984	Log(("iemTaskSwitch: SS not present. uNewSS=%#x -> #NP\n", uNewSS));
2985	return iemRaiseSelectorNotPresentWithErr(pIemCpu, uNewSS & X86_SEL_MASK_OFF_RPL);
2986	}
2987
2988	uint32_t cbLimit = X86DESC_LIMIT_G(&DescSS.Legacy);
2989	uint64_t u64Base = X86DESC_BASE(&DescSS.Legacy);
2990
2991	/* Set the accessed bit before committing the result into SS. */
2992	if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2993	{
2994	rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewSS);
2995	if (rcStrict != VINF_SUCCESS)
2996	return rcStrict;
2997	DescSS.Legacy.Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
2998	}
2999
3000	/* Commit SS. */
3001	pCtx->ss.Sel = uNewSS;
3002	pCtx->ss.ValidSel = uNewSS;
3003	pCtx->ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3004	pCtx->ss.u32Limit = cbLimit;
3005	pCtx->ss.u64Base = u64Base;
3006	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
3007	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(IEMCPU_TO_VMCPU(pIemCpu), &pCtx->ss));
3008
3009	/* CPL has changed, update IEM before loading rest of segments. */
3010	pIemCpu->uCpl = uNewCpl;
3011
3012	/*
3013	* Load the data segments for the new task.
3014	*/
3015	rcStrict = iemHlpTaskSwitchLoadDataSelectorInProtMode(pIemCpu, &pCtx->es, uNewES);
3016	if (rcStrict != VINF_SUCCESS)
3017	return rcStrict;
3018	rcStrict = iemHlpTaskSwitchLoadDataSelectorInProtMode(pIemCpu, &pCtx->ds, uNewDS);
3019	if (rcStrict != VINF_SUCCESS)
3020	return rcStrict;
3021	rcStrict = iemHlpTaskSwitchLoadDataSelectorInProtMode(pIemCpu, &pCtx->fs, uNewFS);
3022	if (rcStrict != VINF_SUCCESS)
3023	return rcStrict;
3024	rcStrict = iemHlpTaskSwitchLoadDataSelectorInProtMode(pIemCpu, &pCtx->gs, uNewGS);
3025	if (rcStrict != VINF_SUCCESS)
3026	return rcStrict;
3027
3028	/*
3029	* Load the code segment for the new task.
3030	*/
3031	if (!(uNewCS & X86_SEL_MASK_OFF_RPL))
3032	{
3033	Log(("iemTaskSwitch #TS: Null code segment. enmTaskSwitch=%u uNewCS=%#x\n", enmTaskSwitch, uNewCS));
3034	return iemRaiseTaskSwitchFaultWithErr(pIemCpu, uNewCS & X86_SEL_MASK_OFF_RPL);
3035	}
3036
3037	/* Fetch the descriptor. */
3038	IEMSELDESC DescCS;
3039	rcStrict = iemMemFetchSelDesc(pIemCpu, &DescCS, uNewCS, X86_XCPT_TS);
3040	if (rcStrict != VINF_SUCCESS)
3041	{
3042	Log(("iemTaskSwitch: failed to fetch CS. uNewCS=%u rc=%Rrc\n", uNewCS, VBOXSTRICTRC_VAL(rcStrict)));
3043	return rcStrict;
3044	}
3045
3046	/* CS must be a code segment. */
3047	if ( !DescCS.Legacy.Gen.u1DescType
3048	\|\| !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3049	{
3050	Log(("iemTaskSwitch: CS invalid descriptor type. uNewCS=%#x u1DescType=%u u4Type=%#x -> #TS\n", uNewCS,
3051	DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
3052	return iemRaiseTaskSwitchFaultWithErr(pIemCpu, uNewCS & X86_SEL_MASK_OFF_RPL);
3053	}
3054
3055	/* For conforming CS, DPL must be less than or equal to the RPL. */
3056	if ( (DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
3057	&& DescCS.Legacy.Gen.u2Dpl > (uNewCS & X86_SEL_RPL))
3058	{
3059	Log(("iemTaskSwitch: confirming CS DPL > RPL. uNewCS=%#x u4Type=%#x DPL=%u -> #TS\n", uNewCS, DescCS.Legacy.Gen.u4Type,
3060	DescCS.Legacy.Gen.u2Dpl));
3061	return iemRaiseTaskSwitchFaultWithErr(pIemCpu, uNewCS & X86_SEL_MASK_OFF_RPL);
3062	}
3063
3064	/* For non-conforming CS, DPL must match RPL. */
3065	if ( !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
3066	&& DescCS.Legacy.Gen.u2Dpl != (uNewCS & X86_SEL_RPL))
3067	{
3068	Log(("iemTaskSwitch: non-confirming CS DPL RPL mismatch. uNewCS=%#x u4Type=%#x DPL=%u -> #TS\n", uNewCS,
3069	DescCS.Legacy.Gen.u4Type, DescCS.Legacy.Gen.u2Dpl));
3070	return iemRaiseTaskSwitchFaultWithErr(pIemCpu, uNewCS & X86_SEL_MASK_OFF_RPL);
3071	}
3072
3073	/* Is it there? */
3074	if (!DescCS.Legacy.Gen.u1Present)
3075	{
3076	Log(("iemTaskSwitch: CS not present. uNewCS=%#x -> #NP\n", uNewCS));
3077	return iemRaiseSelectorNotPresentWithErr(pIemCpu, uNewCS & X86_SEL_MASK_OFF_RPL);
3078	}
3079
3080	cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
3081	u64Base = X86DESC_BASE(&DescCS.Legacy);
3082
3083	/* Set the accessed bit before committing the result into CS. */
3084	if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3085	{
3086	rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewCS);
3087	if (rcStrict != VINF_SUCCESS)
3088	return rcStrict;
3089	DescCS.Legacy.Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
3090	}
3091
3092	/* Commit CS. */
3093	pCtx->cs.Sel = uNewCS;
3094	pCtx->cs.ValidSel = uNewCS;
3095	pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3096	pCtx->cs.u32Limit = cbLimit;
3097	pCtx->cs.u64Base = u64Base;
3098	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
3099	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(IEMCPU_TO_VMCPU(pIemCpu), &pCtx->cs));
3100	}
3101
3102	/** @todo Debug trap. */
3103	if (fIsNewTSS386 && fNewDebugTrap)
3104	Log(("iemTaskSwitch: Debug Trap set in new TSS. Not implemented!\n"));
3105
3106	/*
3107	* Construct the error code masks based on what caused this task switch.
3108	* See Intel Instruction reference for INT.
3109	*/
3110	uint16_t uExt;
3111	if ( enmTaskSwitch == IEMTASKSWITCH_INT_XCPT
3112	&& !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT))
3113	{
3114	uExt = 1;
3115	}
3116	else
3117	uExt = 0;
3118
3119	/*
3120	* Push any error code on to the new stack.
3121	*/
3122	if (fFlags & IEM_XCPT_FLAGS_ERR)
3123	{
3124	Assert(enmTaskSwitch == IEMTASKSWITCH_INT_XCPT);
3125	uint32_t cbLimitSS = X86DESC_LIMIT_G(&DescSS.Legacy);
3126	uint8_t const cbStackFrame = fIsNewTSS386 ? 4 : 2;
3127
3128	/* Check that there is sufficient space on the stack. */
3129	/** @todo Factor out segment limit checking for normal/expand down segments
3130	* into a separate function. */
3131	if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_DOWN))
3132	{
3133	if ( pCtx->esp - 1 > cbLimitSS
3134	\|\| pCtx->esp < cbStackFrame)
3135	{
3136	/** @todo Intel says #SS(EXT) for INT/XCPT, I couldn't figure out AMD yet. */
3137	Log(("iemTaskSwitch: SS=%#x ESP=%#x cbStackFrame=%#x is out of bounds -> #SS\n", pCtx->ss.Sel, pCtx->esp,
3138	cbStackFrame));
3139	return iemRaiseStackSelectorNotPresentWithErr(pIemCpu, uExt);
3140	}
3141	}
3142	else
3143	{
3144	if ( pCtx->esp - 1 > (DescSS.Legacy.Gen.u4Type & X86_DESC_DB ? UINT32_MAX : UINT32_C(0xffff))
3145	\|\| pCtx->esp - cbStackFrame < cbLimitSS + UINT32_C(1))
3146	{
3147	Log(("iemTaskSwitch: SS=%#x ESP=%#x cbStackFrame=%#x (expand down) is out of bounds -> #SS\n", pCtx->ss.Sel, pCtx->esp,
3148	cbStackFrame));
3149	return iemRaiseStackSelectorNotPresentWithErr(pIemCpu, uExt);
3150	}
3151	}
3152
3153
3154	if (fIsNewTSS386)
3155	rcStrict = iemMemStackPushU32(pIemCpu, uErr);
3156	else
3157	rcStrict = iemMemStackPushU16(pIemCpu, uErr);
3158	if (rcStrict != VINF_SUCCESS)
3159	{
3160	Log(("iemTaskSwitch: Can't push error code to new task's stack. %s-bit TSS. rc=%Rrc\n", fIsNewTSS386 ? "32" : "16",
3161	VBOXSTRICTRC_VAL(rcStrict)));
3162	return rcStrict;
3163	}
3164	}
3165
3166	/* Check the new EIP against the new CS limit. */
3167	if (pCtx->eip > pCtx->cs.u32Limit)
3168	{
3169	Log(("iemHlpTaskSwitchLoadDataSelectorInProtMode: New EIP exceeds CS limit. uNewEIP=%#RGv CS limit=%u -> #GP(0)\n",
3170	pCtx->eip, pCtx->cs.u32Limit));
3171	/** @todo Intel says #GP(EXT) for INT/XCPT, I couldn't figure out AMD yet. */
3172	return iemRaiseGeneralProtectionFault(pIemCpu, uExt);
3173	}
3174
3175	Log(("iemTaskSwitch: Success! New CS:EIP=%#04x:%#x SS=%#04x\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel));
3176	return fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT ? VINF_IEM_RAISED_XCPT : VINF_SUCCESS;
3177	}
3178
3179
3180	/**
3181	* Implements exceptions and interrupts for protected mode.
3182	*
3183	* @returns VBox strict status code.
3184	* @param pIemCpu The IEM per CPU instance data.
3185	* @param pCtx The CPU context.
3186	* @param cbInstr The number of bytes to offset rIP by in the return
3187	* address.
3188	* @param u8Vector The interrupt / exception vector number.
3189	* @param fFlags The flags.
3190	* @param uErr The error value if IEM_XCPT_FLAGS_ERR is set.
3191	* @param uCr2 The CR2 value if IEM_XCPT_FLAGS_CR2 is set.
3192	*/
3193	static VBOXSTRICTRC
3194	iemRaiseXcptOrIntInProtMode(PIEMCPU pIemCpu,
3195	PCPUMCTX pCtx,
3196	uint8_t cbInstr,
3197	uint8_t u8Vector,
3198	uint32_t fFlags,
3199	uint16_t uErr,
3200	uint64_t uCr2)
3201	{
3202	/*
3203	* Read the IDT entry.
3204	*/
3205	if (pCtx->idtr.cbIdt < UINT32_C(8) * u8Vector + 7)
3206	{
3207	Log(("RaiseXcptOrIntInProtMode: %#x is out of bounds (%#x)\n", u8Vector, pCtx->idtr.cbIdt));
3208	return iemRaiseGeneralProtectionFault(pIemCpu, X86_TRAP_ERR_IDT \| ((uint16_t)u8Vector << X86_TRAP_ERR_SEL_SHIFT));
3209	}
3210	X86DESC Idte;
3211	VBOXSTRICTRC rcStrict = iemMemFetchSysU64(pIemCpu, &Idte.u, UINT8_MAX,
3212	pCtx->idtr.pIdt + UINT32_C(8) * u8Vector);
3213	if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
3214	return rcStrict;
3215	Log(("iemRaiseXcptOrIntInProtMode: vec=%#x P=%u DPL=%u DT=%u:%u A=%u %04x:%04x%04x\n",
3216	u8Vector, Idte.Gate.u1Present, Idte.Gate.u2Dpl, Idte.Gate.u1DescType, Idte.Gate.u4Type,
3217	Idte.Gate.u4ParmCount, Idte.Gate.u16Sel, Idte.Gate.u16OffsetHigh, Idte.Gate.u16OffsetLow));
3218
3219	/*
3220	* Check the descriptor type, DPL and such.
3221	* ASSUMES this is done in the same order as described for call-gate calls.
3222	*/
3223	if (Idte.Gate.u1DescType)
3224	{
3225	Log(("RaiseXcptOrIntInProtMode %#x - not system selector (%#x) -> #GP\n", u8Vector, Idte.Gate.u4Type));
3226	return iemRaiseGeneralProtectionFault(pIemCpu, X86_TRAP_ERR_IDT \| ((uint16_t)u8Vector << X86_TRAP_ERR_SEL_SHIFT));
3227	}
3228	bool fTaskGate = false;
3229	uint8_t f32BitGate = true;
3230	uint32_t fEflToClear = X86_EFL_TF \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM;
3231	switch (Idte.Gate.u4Type)
3232	{
3233	case X86_SEL_TYPE_SYS_UNDEFINED:
3234	case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
3235	case X86_SEL_TYPE_SYS_LDT:
3236	case X86_SEL_TYPE_SYS_286_TSS_BUSY:
3237	case X86_SEL_TYPE_SYS_286_CALL_GATE:
3238	case X86_SEL_TYPE_SYS_UNDEFINED2:
3239	case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
3240	case X86_SEL_TYPE_SYS_UNDEFINED3:
3241	case X86_SEL_TYPE_SYS_386_TSS_BUSY:
3242	case X86_SEL_TYPE_SYS_386_CALL_GATE:
3243	case X86_SEL_TYPE_SYS_UNDEFINED4:
3244	{
3245	/** @todo check what actually happens when the type is wrong...
3246	* esp. call gates. */
3247	Log(("RaiseXcptOrIntInProtMode %#x - invalid type (%#x) -> #GP\n", u8Vector, Idte.Gate.u4Type));
3248	return iemRaiseGeneralProtectionFault(pIemCpu, X86_TRAP_ERR_IDT \| ((uint16_t)u8Vector << X86_TRAP_ERR_SEL_SHIFT));
3249	}
3250
3251	case X86_SEL_TYPE_SYS_286_INT_GATE:
3252	f32BitGate = false;
3253	case X86_SEL_TYPE_SYS_386_INT_GATE:
3254	fEflToClear \|= X86_EFL_IF;
3255	break;
3256
3257	case X86_SEL_TYPE_SYS_TASK_GATE:
3258	fTaskGate = true;
3259	#ifndef IEM_IMPLEMENTS_TASKSWITCH
3260	IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(("Task gates\n"));
3261	#endif
3262	break;
3263
3264	case X86_SEL_TYPE_SYS_286_TRAP_GATE:
3265	f32BitGate = false;
3266	case X86_SEL_TYPE_SYS_386_TRAP_GATE:
3267	break;
3268
3269	IEM_NOT_REACHED_DEFAULT_CASE_RET();
3270	}
3271
3272	/* Check DPL against CPL if applicable. */
3273	if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3274	{
3275	if (pIemCpu->uCpl > Idte.Gate.u2Dpl)
3276	{
3277	Log(("RaiseXcptOrIntInProtMode %#x - CPL (%d) > DPL (%d) -> #GP\n", u8Vector, pIemCpu->uCpl, Idte.Gate.u2Dpl));
3278	return iemRaiseGeneralProtectionFault(pIemCpu, X86_TRAP_ERR_IDT \| ((uint16_t)u8Vector << X86_TRAP_ERR_SEL_SHIFT));
3279	}
3280	}
3281
3282	/* Is it there? */
3283	if (!Idte.Gate.u1Present)
3284	{
3285	Log(("RaiseXcptOrIntInProtMode %#x - not present -> #NP\n", u8Vector));
3286	return iemRaiseSelectorNotPresentWithErr(pIemCpu, X86_TRAP_ERR_IDT \| ((uint16_t)u8Vector << X86_TRAP_ERR_SEL_SHIFT));
3287	}
3288
3289	/* Is it a task-gate? */
3290	if (fTaskGate)
3291	{
3292	/*
3293	* Construct the error code masks based on what caused this task switch.
3294	* See Intel Instruction reference for INT.
3295	*/
3296	uint16_t const uExt = (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT) ? 0 : 1;
3297	uint16_t const uSelMask = X86_SEL_MASK_OFF_RPL;
3298	RTSEL SelTSS = Idte.Gate.u16Sel;
3299
3300	/*
3301	* Fetch the TSS descriptor in the GDT.
3302	*/
3303	IEMSELDESC DescTSS;
3304	rcStrict = iemMemFetchSelDescWithErr(pIemCpu, &DescTSS, SelTSS, X86_XCPT_GP, (SelTSS & uSelMask) \| uExt);
3305	if (rcStrict != VINF_SUCCESS)
3306	{
3307	Log(("RaiseXcptOrIntInProtMode %#x - failed to fetch TSS selector %#x, rc=%Rrc\n", u8Vector, SelTSS,
3308	VBOXSTRICTRC_VAL(rcStrict)));
3309	return rcStrict;
3310	}
3311
3312	/* The TSS descriptor must be a system segment and be available (not busy). */
3313	if ( DescTSS.Legacy.Gen.u1DescType
3314	\|\| ( DescTSS.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_286_TSS_AVAIL
3315	&& DescTSS.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL))
3316	{
3317	Log(("RaiseXcptOrIntInProtMode %#x - TSS selector %#x of task gate not a system descriptor or not available %#RX64\n",
3318	u8Vector, SelTSS, DescTSS.Legacy.au64));
3319	return iemRaiseGeneralProtectionFault(pIemCpu, (SelTSS & uSelMask) \| uExt);
3320	}
3321
3322	/* The TSS must be present. */
3323	if (!DescTSS.Legacy.Gen.u1Present)
3324	{
3325	Log(("RaiseXcptOrIntInProtMode %#x - TSS selector %#x not present %#RX64\n", u8Vector, SelTSS, DescTSS.Legacy.au64));
3326	return iemRaiseSelectorNotPresentWithErr(pIemCpu, (SelTSS & uSelMask) \| uExt);
3327	}
3328
3329	/* Do the actual task switch. */
3330	return iemTaskSwitch(pIemCpu, pCtx, IEMTASKSWITCH_INT_XCPT, pCtx->eip, fFlags, uErr, uCr2, SelTSS, &DescTSS);
3331	}
3332
3333	/* A null CS is bad. */
3334	RTSEL NewCS = Idte.Gate.u16Sel;
3335	if (!(NewCS & X86_SEL_MASK_OFF_RPL))
3336	{
3337	Log(("RaiseXcptOrIntInProtMode %#x - CS=%#x -> #GP\n", u8Vector, NewCS));
3338	return iemRaiseGeneralProtectionFault0(pIemCpu);
3339	}
3340
3341	/* Fetch the descriptor for the new CS. */
3342	IEMSELDESC DescCS;
3343	rcStrict = iemMemFetchSelDesc(pIemCpu, &DescCS, NewCS, X86_XCPT_GP); /** @todo correct exception? */
3344	if (rcStrict != VINF_SUCCESS)
3345	{
3346	Log(("RaiseXcptOrIntInProtMode %#x - CS=%#x - rc=%Rrc\n", u8Vector, NewCS, VBOXSTRICTRC_VAL(rcStrict)));
3347	return rcStrict;
3348	}
3349
3350	/* Must be a code segment. */
3351	if (!DescCS.Legacy.Gen.u1DescType)
3352	{
3353	Log(("RaiseXcptOrIntInProtMode %#x - CS=%#x - system selector (%#x) -> #GP\n", u8Vector, NewCS, DescCS.Legacy.Gen.u4Type));
3354	return iemRaiseGeneralProtectionFault(pIemCpu, NewCS & X86_SEL_MASK_OFF_RPL);
3355	}
3356	if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3357	{
3358	Log(("RaiseXcptOrIntInProtMode %#x - CS=%#x - data selector (%#x) -> #GP\n", u8Vector, NewCS, DescCS.Legacy.Gen.u4Type));
3359	return iemRaiseGeneralProtectionFault(pIemCpu, NewCS & X86_SEL_MASK_OFF_RPL);
3360	}
3361
3362	/* Don't allow lowering the privilege level. */
3363	/** @todo Does the lowering of privileges apply to software interrupts
3364	* only? This has bearings on the more-privileged or
3365	* same-privilege stack behavior further down. A testcase would
3366	* be nice. */
3367	if (DescCS.Legacy.Gen.u2Dpl > pIemCpu->uCpl)
3368	{
3369	Log(("RaiseXcptOrIntInProtMode %#x - CS=%#x - DPL (%d) > CPL (%d) -> #GP\n",
3370	u8Vector, NewCS, DescCS.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
3371	return iemRaiseGeneralProtectionFault(pIemCpu, NewCS & X86_SEL_MASK_OFF_RPL);
3372	}
3373
3374	/* Make sure the selector is present. */
3375	if (!DescCS.Legacy.Gen.u1Present)
3376	{
3377	Log(("RaiseXcptOrIntInProtMode %#x - CS=%#x - segment not present -> #NP\n", u8Vector, NewCS));
3378	return iemRaiseSelectorNotPresentBySelector(pIemCpu, NewCS);
3379	}
3380
3381	/* Check the new EIP against the new CS limit. */
3382	uint32_t const uNewEip = Idte.Gate.u4Type == X86_SEL_TYPE_SYS_286_INT_GATE
3383	\|\| Idte.Gate.u4Type == X86_SEL_TYPE_SYS_286_TRAP_GATE
3384	? Idte.Gate.u16OffsetLow
3385	: Idte.Gate.u16OffsetLow \| ((uint32_t)Idte.Gate.u16OffsetHigh << 16);
3386	uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3387	if (uNewEip > cbLimitCS)
3388	{
3389	Log(("RaiseXcptOrIntInProtMode %#x - EIP=%#x > cbLimitCS=%#x (CS=%#x) -> #GP(0)\n",
3390	u8Vector, uNewEip, cbLimitCS, NewCS));
3391	return iemRaiseGeneralProtectionFault(pIemCpu, 0);
3392	}
3393
3394	/* Calc the flag image to push. */
3395	uint32_t fEfl = IEMMISC_GET_EFL(pIemCpu, pCtx);
3396	if (fFlags & (IEM_XCPT_FLAGS_DRx_INSTR_BP \| IEM_XCPT_FLAGS_T_SOFT_INT))
3397	fEfl &= ~X86_EFL_RF;
3398	else if (!IEM_FULL_VERIFICATION_REM_ENABLED(pIemCpu))
3399	fEfl \|= X86_EFL_RF; /* Vagueness is all I've found on this so far... / /* @todo Automatically pushing EFLAGS.RF. */
3400
3401	/* From V8086 mode only go to CPL 0. */
3402	uint8_t const uNewCpl = DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF
3403	? pIemCpu->uCpl : DescCS.Legacy.Gen.u2Dpl;
3404	if ((fEfl & X86_EFL_VM) && uNewCpl != 0) /** @todo When exactly is this raised? */
3405	{
3406	Log(("RaiseXcptOrIntInProtMode %#x - CS=%#x - New CPL (%d) != 0 w/ VM=1 -> #GP\n", u8Vector, NewCS, uNewCpl));
3407	return iemRaiseGeneralProtectionFault(pIemCpu, 0);
3408	}
3409
3410	/*
3411	* If the privilege level changes, we need to get a new stack from the TSS.
3412	* This in turns means validating the new SS and ESP...
3413	*/
3414	if (uNewCpl != pIemCpu->uCpl)
3415	{
3416	RTSEL NewSS;
3417	uint32_t uNewEsp;
3418	rcStrict = iemRaiseLoadStackFromTss32Or16(pIemCpu, pCtx, uNewCpl, &NewSS, &uNewEsp);
3419	if (rcStrict != VINF_SUCCESS)
3420	return rcStrict;
3421
3422	IEMSELDESC DescSS;
3423	rcStrict = iemMiscValidateNewSS(pIemCpu, pCtx, NewSS, uNewCpl, &DescSS);
3424	if (rcStrict != VINF_SUCCESS)
3425	return rcStrict;
3426
3427	/* Check that there is sufficient space for the stack frame. */
3428	uint32_t cbLimitSS = X86DESC_LIMIT_G(&DescSS.Legacy);
3429	uint8_t const cbStackFrame = !(fEfl & X86_EFL_VM)
3430	? (fFlags & IEM_XCPT_FLAGS_ERR ? 12 : 10) << f32BitGate
3431	: (fFlags & IEM_XCPT_FLAGS_ERR ? 20 : 18) << f32BitGate;
3432
3433	if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_DOWN))
3434	{
3435	if ( uNewEsp - 1 > cbLimitSS
3436	\|\| uNewEsp < cbStackFrame)
3437	{
3438	Log(("RaiseXcptOrIntInProtMode: %#x - SS=%#x ESP=%#x cbStackFrame=%#x is out of bounds -> #GP\n",
3439	u8Vector, NewSS, uNewEsp, cbStackFrame));
3440	return iemRaiseSelectorBoundsBySelector(pIemCpu, NewSS);
3441	}
3442	}
3443	else
3444	{
3445	if ( uNewEsp - 1 > (DescSS.Legacy.Gen.u4Type & X86_DESC_DB ? UINT32_MAX : UINT32_C(0xffff))
3446	\|\| uNewEsp - cbStackFrame < cbLimitSS + UINT32_C(1))
3447	{
3448	Log(("RaiseXcptOrIntInProtMode: %#x - SS=%#x ESP=%#x cbStackFrame=%#x (expand down) is out of bounds -> #GP\n",
3449	u8Vector, NewSS, uNewEsp, cbStackFrame));
3450	return iemRaiseSelectorBoundsBySelector(pIemCpu, NewSS);
3451	}
3452	}
3453
3454	/*
3455	* Start making changes.
3456	*/
3457
3458	/* Create the stack frame. */
3459	RTPTRUNION uStackFrame;
3460	rcStrict = iemMemMap(pIemCpu, &uStackFrame.pv, cbStackFrame, UINT8_MAX,
3461	uNewEsp - cbStackFrame + X86DESC_BASE(&DescSS.Legacy), IEM_ACCESS_STACK_W \| IEM_ACCESS_WHAT_SYS); /* _SYS is a hack ... */
3462	if (rcStrict != VINF_SUCCESS)
3463	return rcStrict;
3464	void * const pvStackFrame = uStackFrame.pv;
3465	if (f32BitGate)
3466	{
3467	if (fFlags & IEM_XCPT_FLAGS_ERR)
3468	*uStackFrame.pu32++ = uErr;
3469	uStackFrame.pu32[0] = (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT) ? pCtx->eip + cbInstr : pCtx->eip;
3470	uStackFrame.pu32[1] = (pCtx->cs.Sel & ~X86_SEL_RPL) \| pIemCpu->uCpl;
3471	uStackFrame.pu32[2] = fEfl;
3472	uStackFrame.pu32[3] = pCtx->esp;
3473	uStackFrame.pu32[4] = pCtx->ss.Sel;
3474	if (fEfl & X86_EFL_VM)
3475	{
3476	uStackFrame.pu32[1] = pCtx->cs.Sel;
3477	uStackFrame.pu32[5] = pCtx->es.Sel;
3478	uStackFrame.pu32[6] = pCtx->ds.Sel;
3479	uStackFrame.pu32[7] = pCtx->fs.Sel;
3480	uStackFrame.pu32[8] = pCtx->gs.Sel;
3481	}
3482	}
3483	else
3484	{
3485	if (fFlags & IEM_XCPT_FLAGS_ERR)
3486	*uStackFrame.pu16++ = uErr;
3487	uStackFrame.pu16[0] = (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT) ? pCtx->ip + cbInstr : pCtx->ip;
3488	uStackFrame.pu16[1] = (pCtx->cs.Sel & ~X86_SEL_RPL) \| pIemCpu->uCpl;
3489	uStackFrame.pu16[2] = fEfl;
3490	uStackFrame.pu16[3] = pCtx->sp;
3491	uStackFrame.pu16[4] = pCtx->ss.Sel;
3492	if (fEfl & X86_EFL_VM)
3493	{
3494	uStackFrame.pu16[1] = pCtx->cs.Sel;
3495	uStackFrame.pu16[5] = pCtx->es.Sel;
3496	uStackFrame.pu16[6] = pCtx->ds.Sel;
3497	uStackFrame.pu16[7] = pCtx->fs.Sel;
3498	uStackFrame.pu16[8] = pCtx->gs.Sel;
3499	}
3500	}
3501	rcStrict = iemMemCommitAndUnmap(pIemCpu, pvStackFrame, IEM_ACCESS_STACK_W \| IEM_ACCESS_WHAT_SYS);
3502	if (rcStrict != VINF_SUCCESS)
3503	return rcStrict;
3504
3505	/* Mark the selectors 'accessed' (hope this is the correct time). */
3506	/** @todo testcase: excatly _when_ are the accessed bits set - before or
3507	* after pushing the stack frame? (Write protect the gdt + stack to
3508	* find out.) */
3509	if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3510	{
3511	rcStrict = iemMemMarkSelDescAccessed(pIemCpu, NewCS);
3512	if (rcStrict != VINF_SUCCESS)
3513	return rcStrict;
3514	DescCS.Legacy.Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
3515	}
3516
3517	if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3518	{
3519	rcStrict = iemMemMarkSelDescAccessed(pIemCpu, NewSS);
3520	if (rcStrict != VINF_SUCCESS)
3521	return rcStrict;
3522	DescSS.Legacy.Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
3523	}
3524
3525	/*
3526	* Start comitting the register changes (joins with the DPL=CPL branch).
3527	*/
3528	pCtx->ss.Sel = NewSS;
3529	pCtx->ss.ValidSel = NewSS;
3530	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
3531	pCtx->ss.u32Limit = cbLimitSS;
3532	pCtx->ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3533	pCtx->ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3534	pCtx->rsp = uNewEsp - cbStackFrame; /** @todo Is the high word cleared for 16-bit stacks and/or interrupt handlers? */
3535	pIemCpu->uCpl = uNewCpl;
3536
3537	if (fEfl & X86_EFL_VM)
3538	{
3539	iemHlpLoadNullDataSelectorOnV86Xcpt(pIemCpu, &pCtx->gs);
3540	iemHlpLoadNullDataSelectorOnV86Xcpt(pIemCpu, &pCtx->fs);
3541	iemHlpLoadNullDataSelectorOnV86Xcpt(pIemCpu, &pCtx->es);
3542	iemHlpLoadNullDataSelectorOnV86Xcpt(pIemCpu, &pCtx->ds);
3543	}
3544	}
3545	/*
3546	* Same privilege, no stack change and smaller stack frame.
3547	*/
3548	else
3549	{
3550	uint64_t uNewRsp;
3551	RTPTRUNION uStackFrame;
3552	uint8_t const cbStackFrame = (fFlags & IEM_XCPT_FLAGS_ERR ? 8 : 6) << f32BitGate;
3553	rcStrict = iemMemStackPushBeginSpecial(pIemCpu, cbStackFrame, &uStackFrame.pv, &uNewRsp);
3554	if (rcStrict != VINF_SUCCESS)
3555	return rcStrict;
3556	void * const pvStackFrame = uStackFrame.pv;
3557
3558	if (f32BitGate)
3559	{
3560	if (fFlags & IEM_XCPT_FLAGS_ERR)
3561	*uStackFrame.pu32++ = uErr;
3562	uStackFrame.pu32[0] = fFlags & IEM_XCPT_FLAGS_T_SOFT_INT ? pCtx->eip + cbInstr : pCtx->eip;
3563	uStackFrame.pu32[1] = (pCtx->cs.Sel & ~X86_SEL_RPL) \| pIemCpu->uCpl;
3564	uStackFrame.pu32[2] = fEfl;
3565	}
3566	else
3567	{
3568	if (fFlags & IEM_XCPT_FLAGS_ERR)
3569	*uStackFrame.pu16++ = uErr;
3570	uStackFrame.pu16[0] = fFlags & IEM_XCPT_FLAGS_T_SOFT_INT ? pCtx->eip + cbInstr : pCtx->eip;
3571	uStackFrame.pu16[1] = (pCtx->cs.Sel & ~X86_SEL_RPL) \| pIemCpu->uCpl;
3572	uStackFrame.pu16[2] = fEfl;
3573	}
3574	rcStrict = iemMemCommitAndUnmap(pIemCpu, pvStackFrame, IEM_ACCESS_STACK_W); /* don't use the commit here */
3575	if (rcStrict != VINF_SUCCESS)
3576	return rcStrict;
3577
3578	/* Mark the CS selector as 'accessed'. */
3579	if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3580	{
3581	rcStrict = iemMemMarkSelDescAccessed(pIemCpu, NewCS);
3582	if (rcStrict != VINF_SUCCESS)
3583	return rcStrict;
3584	DescCS.Legacy.Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
3585	}
3586
3587	/*
3588	* Start committing the register changes (joins with the other branch).
3589	*/
3590	pCtx->rsp = uNewRsp;
3591	}
3592
3593	/* ... register committing continues. */
3594	pCtx->cs.Sel = (NewCS & ~X86_SEL_RPL) \| uNewCpl;
3595	pCtx->cs.ValidSel = (NewCS & ~X86_SEL_RPL) \| uNewCpl;
3596	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
3597	pCtx->cs.u32Limit = cbLimitCS;
3598	pCtx->cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3599	pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3600
3601	pCtx->rip = uNewEip;
3602	fEfl &= ~fEflToClear;
3603	IEMMISC_SET_EFL(pIemCpu, pCtx, fEfl);
3604
3605	if (fFlags & IEM_XCPT_FLAGS_CR2)
3606	pCtx->cr2 = uCr2;
3607
3608	if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3609	iemRaiseXcptAdjustState(pCtx, u8Vector);
3610
3611	return fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT ? VINF_IEM_RAISED_XCPT : VINF_SUCCESS;
3612	}
3613
3614
3615	/**
3616	* Implements exceptions and interrupts for long mode.
3617	*
3618	* @returns VBox strict status code.
3619	* @param pIemCpu The IEM per CPU instance data.
3620	* @param pCtx The CPU context.
3621	* @param cbInstr The number of bytes to offset rIP by in the return
3622	* address.
3623	* @param u8Vector The interrupt / exception vector number.
3624	* @param fFlags The flags.
3625	* @param uErr The error value if IEM_XCPT_FLAGS_ERR is set.
3626	* @param uCr2 The CR2 value if IEM_XCPT_FLAGS_CR2 is set.
3627	*/
3628	static VBOXSTRICTRC
3629	iemRaiseXcptOrIntInLongMode(PIEMCPU pIemCpu,
3630	PCPUMCTX pCtx,
3631	uint8_t cbInstr,
3632	uint8_t u8Vector,
3633	uint32_t fFlags,
3634	uint16_t uErr,
3635	uint64_t uCr2)
3636	{
3637	/*
3638	* Read the IDT entry.
3639	*/
3640	uint16_t offIdt = (uint16_t)u8Vector << 4;
3641	if (pCtx->idtr.cbIdt < offIdt + 7)
3642	{
3643	Log(("iemRaiseXcptOrIntInLongMode: %#x is out of bounds (%#x)\n", u8Vector, pCtx->idtr.cbIdt));
3644	return iemRaiseGeneralProtectionFault(pIemCpu, X86_TRAP_ERR_IDT \| ((uint16_t)u8Vector << X86_TRAP_ERR_SEL_SHIFT));
3645	}
3646	X86DESC64 Idte;
3647	VBOXSTRICTRC rcStrict = iemMemFetchSysU64(pIemCpu, &Idte.au64[0], UINT8_MAX, pCtx->idtr.pIdt + offIdt);
3648	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3649	rcStrict = iemMemFetchSysU64(pIemCpu, &Idte.au64[1], UINT8_MAX, pCtx->idtr.pIdt + offIdt + 8);
3650	if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
3651	return rcStrict;
3652	Log(("iemRaiseXcptOrIntInLongMode: vec=%#x P=%u DPL=%u DT=%u:%u IST=%u %04x:%08x%04x%04x\n",
3653	u8Vector, Idte.Gate.u1Present, Idte.Gate.u2Dpl, Idte.Gate.u1DescType, Idte.Gate.u4Type,
3654	Idte.Gate.u3IST, Idte.Gate.u16Sel, Idte.Gate.u32OffsetTop, Idte.Gate.u16OffsetHigh, Idte.Gate.u16OffsetLow));
3655
3656	/*
3657	* Check the descriptor type, DPL and such.
3658	* ASSUMES this is done in the same order as described for call-gate calls.
3659	*/
3660	if (Idte.Gate.u1DescType)
3661	{
3662	Log(("iemRaiseXcptOrIntInLongMode %#x - not system selector (%#x) -> #GP\n", u8Vector, Idte.Gate.u4Type));
3663	return iemRaiseGeneralProtectionFault(pIemCpu, X86_TRAP_ERR_IDT \| ((uint16_t)u8Vector << X86_TRAP_ERR_SEL_SHIFT));
3664	}
3665	uint32_t fEflToClear = X86_EFL_TF \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM;
3666	switch (Idte.Gate.u4Type)
3667	{
3668	case AMD64_SEL_TYPE_SYS_INT_GATE:
3669	fEflToClear \|= X86_EFL_IF;
3670	break;
3671	case AMD64_SEL_TYPE_SYS_TRAP_GATE:
3672	break;
3673
3674	default:
3675	Log(("iemRaiseXcptOrIntInLongMode %#x - invalid type (%#x) -> #GP\n", u8Vector, Idte.Gate.u4Type));
3676	return iemRaiseGeneralProtectionFault(pIemCpu, X86_TRAP_ERR_IDT \| ((uint16_t)u8Vector << X86_TRAP_ERR_SEL_SHIFT));
3677	}
3678
3679	/* Check DPL against CPL if applicable. */
3680	if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
3681	{
3682	if (pIemCpu->uCpl > Idte.Gate.u2Dpl)
3683	{
3684	Log(("iemRaiseXcptOrIntInLongMode %#x - CPL (%d) > DPL (%d) -> #GP\n", u8Vector, pIemCpu->uCpl, Idte.Gate.u2Dpl));
3685	return iemRaiseGeneralProtectionFault(pIemCpu, X86_TRAP_ERR_IDT \| ((uint16_t)u8Vector << X86_TRAP_ERR_SEL_SHIFT));
3686	}
3687	}
3688
3689	/* Is it there? */
3690	if (!Idte.Gate.u1Present)
3691	{
3692	Log(("iemRaiseXcptOrIntInLongMode %#x - not present -> #NP\n", u8Vector));
3693	return iemRaiseSelectorNotPresentWithErr(pIemCpu, X86_TRAP_ERR_IDT \| ((uint16_t)u8Vector << X86_TRAP_ERR_SEL_SHIFT));
3694	}
3695
3696	/* A null CS is bad. */
3697	RTSEL NewCS = Idte.Gate.u16Sel;
3698	if (!(NewCS & X86_SEL_MASK_OFF_RPL))
3699	{
3700	Log(("iemRaiseXcptOrIntInLongMode %#x - CS=%#x -> #GP\n", u8Vector, NewCS));
3701	return iemRaiseGeneralProtectionFault0(pIemCpu);
3702	}
3703
3704	/* Fetch the descriptor for the new CS. */
3705	IEMSELDESC DescCS;
3706	rcStrict = iemMemFetchSelDesc(pIemCpu, &DescCS, NewCS, X86_XCPT_GP);
3707	if (rcStrict != VINF_SUCCESS)
3708	{
3709	Log(("iemRaiseXcptOrIntInLongMode %#x - CS=%#x - rc=%Rrc\n", u8Vector, NewCS, VBOXSTRICTRC_VAL(rcStrict)));
3710	return rcStrict;
3711	}
3712
3713	/* Must be a 64-bit code segment. */
3714	if (!DescCS.Long.Gen.u1DescType)
3715	{
3716	Log(("iemRaiseXcptOrIntInLongMode %#x - CS=%#x - system selector (%#x) -> #GP\n", u8Vector, NewCS, DescCS.Legacy.Gen.u4Type));
3717	return iemRaiseGeneralProtectionFault(pIemCpu, NewCS & X86_SEL_MASK_OFF_RPL);
3718	}
3719	if ( !DescCS.Long.Gen.u1Long
3720	\|\| DescCS.Long.Gen.u1DefBig
3721	\|\| !(DescCS.Long.Gen.u4Type & X86_SEL_TYPE_CODE) )
3722	{
3723	Log(("iemRaiseXcptOrIntInLongMode %#x - CS=%#x - not 64-bit code selector (%#x, L=%u, D=%u) -> #GP\n",
3724	u8Vector, NewCS, DescCS.Legacy.Gen.u4Type, DescCS.Long.Gen.u1Long, DescCS.Long.Gen.u1DefBig));
3725	return iemRaiseGeneralProtectionFault(pIemCpu, NewCS & X86_SEL_MASK_OFF_RPL);
3726	}
3727
3728	/* Don't allow lowering the privilege level. For non-conforming CS
3729	selectors, the CS.DPL sets the privilege level the trap/interrupt
3730	handler runs at. For conforming CS selectors, the CPL remains
3731	unchanged, but the CS.DPL must be <= CPL. */
3732	/** @todo Testcase: Interrupt handler with CS.DPL=1, interrupt dispatched
3733	* when CPU in Ring-0. Result \#GP? */
3734	if (DescCS.Legacy.Gen.u2Dpl > pIemCpu->uCpl)
3735	{
3736	Log(("iemRaiseXcptOrIntInLongMode %#x - CS=%#x - DPL (%d) > CPL (%d) -> #GP\n",
3737	u8Vector, NewCS, DescCS.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
3738	return iemRaiseGeneralProtectionFault(pIemCpu, NewCS & X86_SEL_MASK_OFF_RPL);
3739	}
3740
3741
3742	/* Make sure the selector is present. */
3743	if (!DescCS.Legacy.Gen.u1Present)
3744	{
3745	Log(("iemRaiseXcptOrIntInLongMode %#x - CS=%#x - segment not present -> #NP\n", u8Vector, NewCS));
3746	return iemRaiseSelectorNotPresentBySelector(pIemCpu, NewCS);
3747	}
3748
3749	/* Check that the new RIP is canonical. */
3750	uint64_t const uNewRip = Idte.Gate.u16OffsetLow
3751	\| ((uint32_t)Idte.Gate.u16OffsetHigh << 16)
3752	\| ((uint64_t)Idte.Gate.u32OffsetTop << 32);
3753	if (!IEM_IS_CANONICAL(uNewRip))
3754	{
3755	Log(("iemRaiseXcptOrIntInLongMode %#x - RIP=%#RX64 - Not canonical -> #GP(0)\n", u8Vector, uNewRip));
3756	return iemRaiseGeneralProtectionFault0(pIemCpu);
3757	}
3758
3759	/*
3760	* If the privilege level changes or if the IST isn't zero, we need to get
3761	* a new stack from the TSS.
3762	*/
3763	uint64_t uNewRsp;
3764	uint8_t const uNewCpl = DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF
3765	? pIemCpu->uCpl : DescCS.Legacy.Gen.u2Dpl;
3766	if ( uNewCpl != pIemCpu->uCpl
3767	\|\| Idte.Gate.u3IST != 0)
3768	{
3769	rcStrict = iemRaiseLoadStackFromTss64(pIemCpu, pCtx, uNewCpl, Idte.Gate.u3IST, &uNewRsp);
3770	if (rcStrict != VINF_SUCCESS)
3771	return rcStrict;
3772	}
3773	else
3774	uNewRsp = pCtx->rsp;
3775	uNewRsp &= ~(uint64_t)0xf;
3776
3777	/*
3778	* Calc the flag image to push.
3779	*/
3780	uint32_t fEfl = IEMMISC_GET_EFL(pIemCpu, pCtx);
3781	if (fFlags & (IEM_XCPT_FLAGS_DRx_INSTR_BP \| IEM_XCPT_FLAGS_T_SOFT_INT))
3782	fEfl &= ~X86_EFL_RF;
3783	else if (!IEM_FULL_VERIFICATION_REM_ENABLED(pIemCpu))
3784	fEfl \|= X86_EFL_RF; /* Vagueness is all I've found on this so far... / /* @todo Automatically pushing EFLAGS.RF. */
3785
3786	/*
3787	* Start making changes.
3788	*/
3789
3790	/* Create the stack frame. */
3791	uint32_t cbStackFrame = sizeof(uint64_t) * (5 + !!(fFlags & IEM_XCPT_FLAGS_ERR));
3792	RTPTRUNION uStackFrame;
3793	rcStrict = iemMemMap(pIemCpu, &uStackFrame.pv, cbStackFrame, UINT8_MAX,
3794	uNewRsp - cbStackFrame, IEM_ACCESS_STACK_W \| IEM_ACCESS_WHAT_SYS); /* _SYS is a hack ... */
3795	if (rcStrict != VINF_SUCCESS)
3796	return rcStrict;
3797	void * const pvStackFrame = uStackFrame.pv;
3798
3799	if (fFlags & IEM_XCPT_FLAGS_ERR)
3800	*uStackFrame.pu64++ = uErr;
3801	uStackFrame.pu64[0] = fFlags & IEM_XCPT_FLAGS_T_SOFT_INT ? pCtx->rip + cbInstr : pCtx->rip;
3802	uStackFrame.pu64[1] = (pCtx->cs.Sel & ~X86_SEL_RPL) \| pIemCpu->uCpl; /* CPL paranoia */
3803	uStackFrame.pu64[2] = fEfl;
3804	uStackFrame.pu64[3] = pCtx->rsp;
3805	uStackFrame.pu64[4] = pCtx->ss.Sel;
3806	rcStrict = iemMemCommitAndUnmap(pIemCpu, pvStackFrame, IEM_ACCESS_STACK_W \| IEM_ACCESS_WHAT_SYS);
3807	if (rcStrict != VINF_SUCCESS)
3808	return rcStrict;
3809
3810	/* Mark the CS selectors 'accessed' (hope this is the correct time). */
3811	/** @todo testcase: excatly _when_ are the accessed bits set - before or
3812	* after pushing the stack frame? (Write protect the gdt + stack to
3813	* find out.) */
3814	if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3815	{
3816	rcStrict = iemMemMarkSelDescAccessed(pIemCpu, NewCS);
3817	if (rcStrict != VINF_SUCCESS)
3818	return rcStrict;
3819	DescCS.Legacy.Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
3820	}
3821
3822	/*
3823	* Start comitting the register changes.
3824	*/
3825	/** @todo research/testcase: Figure out what VT-x and AMD-V loads into the
3826	* hidden registers when interrupting 32-bit or 16-bit code! */
3827	if (uNewCpl != pIemCpu->uCpl)
3828	{
3829	pCtx->ss.Sel = 0 \| uNewCpl;
3830	pCtx->ss.ValidSel = 0 \| uNewCpl;
3831	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
3832	pCtx->ss.u32Limit = UINT32_MAX;
3833	pCtx->ss.u64Base = 0;
3834	pCtx->ss.Attr.u = (uNewCpl << X86DESCATTR_DPL_SHIFT) \| X86DESCATTR_UNUSABLE;
3835	}
3836	pCtx->rsp = uNewRsp - cbStackFrame;
3837	pCtx->cs.Sel = (NewCS & ~X86_SEL_RPL) \| uNewCpl;
3838	pCtx->cs.ValidSel = (NewCS & ~X86_SEL_RPL) \| uNewCpl;
3839	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
3840	pCtx->cs.u32Limit = X86DESC_LIMIT_G(&DescCS.Legacy);
3841	pCtx->cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3842	pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3843	pCtx->rip = uNewRip;
3844	pIemCpu->uCpl = uNewCpl;
3845
3846	fEfl &= ~fEflToClear;
3847	IEMMISC_SET_EFL(pIemCpu, pCtx, fEfl);
3848
3849	if (fFlags & IEM_XCPT_FLAGS_CR2)
3850	pCtx->cr2 = uCr2;
3851
3852	if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
3853	iemRaiseXcptAdjustState(pCtx, u8Vector);
3854
3855	return fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT ? VINF_IEM_RAISED_XCPT : VINF_SUCCESS;
3856	}
3857
3858
3859	/**
3860	* Implements exceptions and interrupts.
3861	*
3862	* All exceptions and interrupts goes thru this function!
3863	*
3864	* @returns VBox strict status code.
3865	* @param pIemCpu The IEM per CPU instance data.
3866	* @param cbInstr The number of bytes to offset rIP by in the return
3867	* address.
3868	* @param u8Vector The interrupt / exception vector number.
3869	* @param fFlags The flags.
3870	* @param uErr The error value if IEM_XCPT_FLAGS_ERR is set.
3871	* @param uCr2 The CR2 value if IEM_XCPT_FLAGS_CR2 is set.
3872	*/
3873	DECL_NO_INLINE(static, VBOXSTRICTRC)
3874	iemRaiseXcptOrInt(PIEMCPU pIemCpu,
3875	uint8_t cbInstr,
3876	uint8_t u8Vector,
3877	uint32_t fFlags,
3878	uint16_t uErr,
3879	uint64_t uCr2)
3880	{
3881	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
3882
3883	/*
3884	* Perform the V8086 IOPL check and upgrade the fault without nesting.
3885	*/
3886	if ( pCtx->eflags.Bits.u1VM
3887	&& pCtx->eflags.Bits.u2IOPL != 3
3888	&& (fFlags & (IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR)) == IEM_XCPT_FLAGS_T_SOFT_INT
3889	&& (pCtx->cr0 & X86_CR0_PE) )
3890	{
3891	Log(("iemRaiseXcptOrInt: V8086 IOPL check failed for int %#x -> #GP(0)\n", u8Vector));
3892	fFlags = IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR;
3893	u8Vector = X86_XCPT_GP;
3894	uErr = 0;
3895	}
3896	#ifdef DBGFTRACE_ENABLED
3897	RTTraceBufAddMsgF(IEMCPU_TO_VM(pIemCpu)->CTX_SUFF(hTraceBuf), "Xcpt/%u: %02x %u %x %x %llx %04x:%04llx %04x:%04llx",
3898	pIemCpu->cXcptRecursions, u8Vector, cbInstr, fFlags, uErr, uCr2,
3899	pCtx->cs.Sel, pCtx->rip, pCtx->ss.Sel, pCtx->rsp);
3900	#endif
3901
3902	/*
3903	* Do recursion accounting.
3904	*/
3905	uint8_t const uPrevXcpt = pIemCpu->uCurXcpt;
3906	uint32_t const fPrevXcpt = pIemCpu->fCurXcpt;
3907	if (pIemCpu->cXcptRecursions == 0)
3908	Log(("iemRaiseXcptOrInt: %#x at %04x:%RGv cbInstr=%#x fFlags=%#x uErr=%#x uCr2=%llx\n",
3909	u8Vector, pCtx->cs.Sel, pCtx->rip, cbInstr, fFlags, uErr, uCr2));
3910	else
3911	{
3912	Log(("iemRaiseXcptOrInt: %#x at %04x:%RGv cbInstr=%#x fFlags=%#x uErr=%#x uCr2=%llx; prev=%#x depth=%d flags=%#x\n",
3913	u8Vector, pCtx->cs.Sel, pCtx->rip, cbInstr, fFlags, uErr, uCr2, pIemCpu->uCurXcpt, pIemCpu->cXcptRecursions + 1, fPrevXcpt));
3914
3915	/** @todo double and tripple faults. */
3916	if (pIemCpu->cXcptRecursions >= 3)
3917	{
3918	#ifdef DEBUG_bird
3919	AssertFailed();
3920	#endif
3921	IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(("Too many fault nestings.\n"));
3922	}
3923
3924	/** @todo set X86_TRAP_ERR_EXTERNAL when appropriate.
3925	if (fPrevXcpt & IEM_XCPT_FLAGS_T_EXT_INT)
3926	{
3927	....
3928	} */
3929	}
3930	pIemCpu->cXcptRecursions++;
3931	pIemCpu->uCurXcpt = u8Vector;
3932	pIemCpu->fCurXcpt = fFlags;
3933
3934	/*
3935	* Extensive logging.
3936	*/
3937	#if defined(LOG_ENABLED) && defined(IN_RING3)
3938	if (LogIs3Enabled())
3939	{
3940	PVM pVM = IEMCPU_TO_VM(pIemCpu);
3941	PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu);
3942	char szRegs[4096];
3943	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
3944	"rax=%016VR{rax} rbx=%016VR{rbx} rcx=%016VR{rcx} rdx=%016VR{rdx}\n"
3945	"rsi=%016VR{rsi} rdi=%016VR{rdi} r8 =%016VR{r8} r9 =%016VR{r9}\n"
3946	"r10=%016VR{r10} r11=%016VR{r11} r12=%016VR{r12} r13=%016VR{r13}\n"
3947	"r14=%016VR{r14} r15=%016VR{r15} %VRF{rflags}\n"
3948	"rip=%016VR{rip} rsp=%016VR{rsp} rbp=%016VR{rbp}\n"
3949	"cs={%04VR{cs} base=%016VR{cs_base} limit=%08VR{cs_lim} flags=%04VR{cs_attr}} cr0=%016VR{cr0}\n"
3950	"ds={%04VR{ds} base=%016VR{ds_base} limit=%08VR{ds_lim} flags=%04VR{ds_attr}} cr2=%016VR{cr2}\n"
3951	"es={%04VR{es} base=%016VR{es_base} limit=%08VR{es_lim} flags=%04VR{es_attr}} cr3=%016VR{cr3}\n"
3952	"fs={%04VR{fs} base=%016VR{fs_base} limit=%08VR{fs_lim} flags=%04VR{fs_attr}} cr4=%016VR{cr4}\n"
3953	"gs={%04VR{gs} base=%016VR{gs_base} limit=%08VR{gs_lim} flags=%04VR{gs_attr}} cr8=%016VR{cr8}\n"
3954	"ss={%04VR{ss} base=%016VR{ss_base} limit=%08VR{ss_lim} flags=%04VR{ss_attr}}\n"
3955	"dr0=%016VR{dr0} dr1=%016VR{dr1} dr2=%016VR{dr2} dr3=%016VR{dr3}\n"
3956	"dr6=%016VR{dr6} dr7=%016VR{dr7}\n"
3957	"gdtr=%016VR{gdtr_base}:%04VR{gdtr_lim} idtr=%016VR{idtr_base}:%04VR{idtr_lim} rflags=%08VR{rflags}\n"
3958	"ldtr={%04VR{ldtr} base=%016VR{ldtr_base} limit=%08VR{ldtr_lim} flags=%08VR{ldtr_attr}}\n"
3959	"tr ={%04VR{tr} base=%016VR{tr_base} limit=%08VR{tr_lim} flags=%08VR{tr_attr}}\n"
3960	" sysenter={cs=%04VR{sysenter_cs} eip=%08VR{sysenter_eip} esp=%08VR{sysenter_esp}}\n"
3961	" efer=%016VR{efer}\n"
3962	" pat=%016VR{pat}\n"
3963	" sf_mask=%016VR{sf_mask}\n"
3964	"krnl_gs_base=%016VR{krnl_gs_base}\n"
3965	" lstar=%016VR{lstar}\n"
3966	" star=%016VR{star} cstar=%016VR{cstar}\n"
3967	"fcw=%04VR{fcw} fsw=%04VR{fsw} ftw=%04VR{ftw} mxcsr=%04VR{mxcsr} mxcsr_mask=%04VR{mxcsr_mask}\n"
3968	);
3969
3970	char szInstr[256];
3971	DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
3972	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
3973	szInstr, sizeof(szInstr), NULL);
3974	Log3(("%s%s\n", szRegs, szInstr));
3975	}
3976	#endif /* LOG_ENABLED */
3977
3978	/*
3979	* Call the mode specific worker function.
3980	*/
3981	VBOXSTRICTRC rcStrict;
3982	if (!(pCtx->cr0 & X86_CR0_PE))
3983	rcStrict = iemRaiseXcptOrIntInRealMode( pIemCpu, pCtx, cbInstr, u8Vector, fFlags, uErr, uCr2);
3984	else if (pCtx->msrEFER & MSR_K6_EFER_LMA)
3985	rcStrict = iemRaiseXcptOrIntInLongMode( pIemCpu, pCtx, cbInstr, u8Vector, fFlags, uErr, uCr2);
3986	else
3987	rcStrict = iemRaiseXcptOrIntInProtMode( pIemCpu, pCtx, cbInstr, u8Vector, fFlags, uErr, uCr2);
3988
3989	/*
3990	* Unwind.
3991	*/
3992	pIemCpu->cXcptRecursions--;
3993	pIemCpu->uCurXcpt = uPrevXcpt;
3994	pIemCpu->fCurXcpt = fPrevXcpt;
3995	Log(("iemRaiseXcptOrInt: returns %Rrc (vec=%#x); cs:rip=%04x:%RGv ss:rsp=%04x:%RGv cpl=%u\n",
3996	VBOXSTRICTRC_VAL(rcStrict), u8Vector, pCtx->cs.Sel, pCtx->rip, pCtx->ss.Sel, pCtx->esp, pIemCpu->uCpl));
3997	return rcStrict;
3998	}
3999
4000
4001	/** \#DE - 00. */
4002	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseDivideError(PIEMCPU pIemCpu)
4003	{
4004	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_DE, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
4005	}
4006
4007
4008	/** \#DB - 01.
4009	* @note This automatically clear DR7.GD. */
4010	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseDebugException(PIEMCPU pIemCpu)
4011	{
4012	/** @todo set/clear RF. */
4013	pIemCpu->CTX_SUFF(pCtx)->dr[7] &= ~X86_DR7_GD;
4014	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_DB, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
4015	}
4016
4017
4018	/** \#UD - 06. */
4019	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseUndefinedOpcode(PIEMCPU pIemCpu)
4020	{
4021	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_UD, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
4022	}
4023
4024
4025	/** \#NM - 07. */
4026	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseDeviceNotAvailable(PIEMCPU pIemCpu)
4027	{
4028	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_NM, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
4029	}
4030
4031
4032	/** \#TS(err) - 0a. */
4033	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseTaskSwitchFaultWithErr(PIEMCPU pIemCpu, uint16_t uErr)
4034	{
4035	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_TS, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR, uErr, 0);
4036	}
4037
4038
4039	/** \#TS(tr) - 0a. */
4040	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseTaskSwitchFaultCurrentTSS(PIEMCPU pIemCpu)
4041	{
4042	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_TS, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR,
4043	pIemCpu->CTX_SUFF(pCtx)->tr.Sel, 0);
4044	}
4045
4046
4047	/** \#TS(0) - 0a. */
4048	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseTaskSwitchFault0(PIEMCPU pIemCpu)
4049	{
4050	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_TS, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR,
4051	0, 0);
4052	}
4053
4054
4055	/** \#TS(err) - 0a. */
4056	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseTaskSwitchFaultBySelector(PIEMCPU pIemCpu, uint16_t uSel)
4057	{
4058	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_TS, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR,
4059	uSel & X86_SEL_MASK_OFF_RPL, 0);
4060	}
4061
4062
4063	/** \#NP(err) - 0b. */
4064	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr)
4065	{
4066	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_NP, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR, uErr, 0);
4067	}
4068
4069
4070	/** \#NP(seg) - 0b. */
4071	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseSelectorNotPresentBySegReg(PIEMCPU pIemCpu, uint32_t iSegReg)
4072	{
4073	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_NP, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR,
4074	iemSRegFetchU16(pIemCpu, iSegReg) & ~X86_SEL_RPL, 0);
4075	}
4076
4077
4078	/** \#NP(sel) - 0b. */
4079	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel)
4080	{
4081	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_NP, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR,
4082	uSel & ~X86_SEL_RPL, 0);
4083	}
4084
4085
4086	/** \#SS(seg) - 0c. */
4087	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseStackSelectorNotPresentBySelector(PIEMCPU pIemCpu, uint16_t uSel)
4088	{
4089	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_SS, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR,
4090	uSel & ~X86_SEL_RPL, 0);
4091	}
4092
4093
4094	/** \#SS(err) - 0c. */
4095	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseStackSelectorNotPresentWithErr(PIEMCPU pIemCpu, uint16_t uErr)
4096	{
4097	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_SS, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR, uErr, 0);
4098	}
4099
4100
4101	/** \#GP(n) - 0d. */
4102	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseGeneralProtectionFault(PIEMCPU pIemCpu, uint16_t uErr)
4103	{
4104	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR, uErr, 0);
4105	}
4106
4107
4108	/** \#GP(0) - 0d. */
4109	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseGeneralProtectionFault0(PIEMCPU pIemCpu)
4110	{
4111	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR, 0, 0);
4112	}
4113
4114
4115	/** \#GP(sel) - 0d. */
4116	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseGeneralProtectionFaultBySelector(PIEMCPU pIemCpu, RTSEL Sel)
4117	{
4118	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR,
4119	Sel & ~X86_SEL_RPL, 0);
4120	}
4121
4122
4123	/** \#GP(0) - 0d. */
4124	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseNotCanonical(PIEMCPU pIemCpu)
4125	{
4126	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR, 0, 0);
4127	}
4128
4129
4130	/** \#GP(sel) - 0d. */
4131	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseSelectorBounds(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess)
4132	{
4133	NOREF(iSegReg); NOREF(fAccess);
4134	return iemRaiseXcptOrInt(pIemCpu, 0, iSegReg == X86_SREG_SS ? X86_XCPT_SS : X86_XCPT_GP,
4135	IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR, 0, 0);
4136	}
4137
4138
4139	/** \#GP(sel) - 0d. */
4140	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseSelectorBoundsBySelector(PIEMCPU pIemCpu, RTSEL Sel)
4141	{
4142	NOREF(Sel);
4143	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR, 0, 0);
4144	}
4145
4146
4147	/** \#GP(sel) - 0d. */
4148	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseSelectorInvalidAccess(PIEMCPU pIemCpu, uint32_t iSegReg, uint32_t fAccess)
4149	{
4150	NOREF(iSegReg); NOREF(fAccess);
4151	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR, 0, 0);
4152	}
4153
4154
4155	/** \#PF(n) - 0e. */
4156	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaisePageFault(PIEMCPU pIemCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc)
4157	{
4158	uint16_t uErr;
4159	switch (rc)
4160	{
4161	case VERR_PAGE_NOT_PRESENT:
4162	case VERR_PAGE_TABLE_NOT_PRESENT:
4163	case VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT:
4164	case VERR_PAGE_MAP_LEVEL4_NOT_PRESENT:
4165	uErr = 0;
4166	break;
4167
4168	default:
4169	AssertMsgFailed(("%Rrc\n", rc));
4170	case VERR_ACCESS_DENIED:
4171	uErr = X86_TRAP_PF_P;
4172	break;
4173
4174	/** @todo reserved */
4175	}
4176
4177	if (pIemCpu->uCpl == 3)
4178	uErr \|= X86_TRAP_PF_US;
4179
4180	if ( (fAccess & IEM_ACCESS_WHAT_MASK) == IEM_ACCESS_WHAT_CODE
4181	&& ( (pIemCpu->CTX_SUFF(pCtx)->cr4 & X86_CR4_PAE)
4182	&& (pIemCpu->CTX_SUFF(pCtx)->msrEFER & MSR_K6_EFER_NXE) ) )
4183	uErr \|= X86_TRAP_PF_ID;
4184
4185	#if 0 /* This is so much non-sense, really. Why was it done like that? */
4186	/* Note! RW access callers reporting a WRITE protection fault, will clear
4187	the READ flag before calling. So, read-modify-write accesses (RW)
4188	can safely be reported as READ faults. */
4189	if ((fAccess & (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_TYPE_READ)) == IEM_ACCESS_TYPE_WRITE)
4190	uErr \|= X86_TRAP_PF_RW;
4191	#else
4192	if (fAccess & IEM_ACCESS_TYPE_WRITE)
4193	{
4194	if (!IEM_FULL_VERIFICATION_REM_ENABLED(pIemCpu) \|\| !(fAccess & IEM_ACCESS_TYPE_READ))
4195	uErr \|= X86_TRAP_PF_RW;
4196	}
4197	#endif
4198
4199	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_PF, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR \| IEM_XCPT_FLAGS_CR2,
4200	uErr, GCPtrWhere);
4201	}
4202
4203
4204	/** \#MF(0) - 10. */
4205	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseMathFault(PIEMCPU pIemCpu)
4206	{
4207	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_MF, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
4208	}
4209
4210
4211	/** \#AC(0) - 11. */
4212	DECL_NO_INLINE(static, VBOXSTRICTRC) iemRaiseAlignmentCheckException(PIEMCPU pIemCpu)
4213	{
4214	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_AC, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
4215	}
4216
4217
4218	/**
4219	* Macro for calling iemCImplRaiseDivideError().
4220	*
4221	* This enables us to add/remove arguments and force different levels of
4222	* inlining as we wish.
4223	*
4224	* @return Strict VBox status code.
4225	*/
4226	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
4227	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError)
4228	{
4229	NOREF(cbInstr);
4230	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_DE, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
4231	}
4232
4233
4234	/**
4235	* Macro for calling iemCImplRaiseInvalidLockPrefix().
4236	*
4237	* This enables us to add/remove arguments and force different levels of
4238	* inlining as we wish.
4239	*
4240	* @return Strict VBox status code.
4241	*/
4242	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
4243	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix)
4244	{
4245	NOREF(cbInstr);
4246	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_UD, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
4247	}
4248
4249
4250	/**
4251	* Macro for calling iemCImplRaiseInvalidOpcode().
4252	*
4253	* This enables us to add/remove arguments and force different levels of
4254	* inlining as we wish.
4255	*
4256	* @return Strict VBox status code.
4257	*/
4258	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
4259	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode)
4260	{
4261	NOREF(cbInstr);
4262	return iemRaiseXcptOrInt(pIemCpu, 0, X86_XCPT_UD, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
4263	}
4264
4265
4266	/** @} */
4267
4268
4269	/*
4270	*
4271	* Helpers routines.
4272	* Helpers routines.
4273	* Helpers routines.
4274	*
4275	*/
4276
4277	/**
4278	* Recalculates the effective operand size.
4279	*
4280	* @param pIemCpu The IEM state.
4281	*/
4282	static void iemRecalEffOpSize(PIEMCPU pIemCpu)
4283	{
4284	switch (pIemCpu->enmCpuMode)
4285	{
4286	case IEMMODE_16BIT:
4287	pIemCpu->enmEffOpSize = pIemCpu->fPrefixes & IEM_OP_PRF_SIZE_OP ? IEMMODE_32BIT : IEMMODE_16BIT;
4288	break;
4289	case IEMMODE_32BIT:
4290	pIemCpu->enmEffOpSize = pIemCpu->fPrefixes & IEM_OP_PRF_SIZE_OP ? IEMMODE_16BIT : IEMMODE_32BIT;
4291	break;
4292	case IEMMODE_64BIT:
4293	switch (pIemCpu->fPrefixes & (IEM_OP_PRF_SIZE_REX_W \| IEM_OP_PRF_SIZE_OP))
4294	{
4295	case 0:
4296	pIemCpu->enmEffOpSize = pIemCpu->enmDefOpSize;
4297	break;
4298	case IEM_OP_PRF_SIZE_OP:
4299	pIemCpu->enmEffOpSize = IEMMODE_16BIT;
4300	break;
4301	case IEM_OP_PRF_SIZE_REX_W:
4302	case IEM_OP_PRF_SIZE_REX_W \| IEM_OP_PRF_SIZE_OP:
4303	pIemCpu->enmEffOpSize = IEMMODE_64BIT;
4304	break;
4305	}
4306	break;
4307	default:
4308	AssertFailed();
4309	}
4310	}
4311
4312
4313	/**
4314	* Sets the default operand size to 64-bit and recalculates the effective
4315	* operand size.
4316	*
4317	* @param pIemCpu The IEM state.
4318	*/
4319	static void iemRecalEffOpSize64Default(PIEMCPU pIemCpu)
4320	{
4321	Assert(pIemCpu->enmCpuMode == IEMMODE_64BIT);
4322	pIemCpu->enmDefOpSize = IEMMODE_64BIT;
4323	if ((pIemCpu->fPrefixes & (IEM_OP_PRF_SIZE_REX_W \| IEM_OP_PRF_SIZE_OP)) != IEM_OP_PRF_SIZE_OP)
4324	pIemCpu->enmEffOpSize = IEMMODE_64BIT;
4325	else
4326	pIemCpu->enmEffOpSize = IEMMODE_16BIT;
4327	}
4328
4329
4330	/*
4331	*
4332	* Common opcode decoders.
4333	* Common opcode decoders.
4334	* Common opcode decoders.
4335	*
4336	*/
4337	//#include <iprt/mem.h>
4338
4339	/**
4340	* Used to add extra details about a stub case.
4341	* @param pIemCpu The IEM per CPU state.
4342	*/
4343	static void iemOpStubMsg2(PIEMCPU pIemCpu)
4344	{
4345	#if defined(LOG_ENABLED) && defined(IN_RING3)
4346	PVM pVM = IEMCPU_TO_VM(pIemCpu);
4347	PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu);
4348	char szRegs[4096];
4349	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
4350	"rax=%016VR{rax} rbx=%016VR{rbx} rcx=%016VR{rcx} rdx=%016VR{rdx}\n"
4351	"rsi=%016VR{rsi} rdi=%016VR{rdi} r8 =%016VR{r8} r9 =%016VR{r9}\n"
4352	"r10=%016VR{r10} r11=%016VR{r11} r12=%016VR{r12} r13=%016VR{r13}\n"
4353	"r14=%016VR{r14} r15=%016VR{r15} %VRF{rflags}\n"
4354	"rip=%016VR{rip} rsp=%016VR{rsp} rbp=%016VR{rbp}\n"
4355	"cs={%04VR{cs} base=%016VR{cs_base} limit=%08VR{cs_lim} flags=%04VR{cs_attr}} cr0=%016VR{cr0}\n"
4356	"ds={%04VR{ds} base=%016VR{ds_base} limit=%08VR{ds_lim} flags=%04VR{ds_attr}} cr2=%016VR{cr2}\n"
4357	"es={%04VR{es} base=%016VR{es_base} limit=%08VR{es_lim} flags=%04VR{es_attr}} cr3=%016VR{cr3}\n"
4358	"fs={%04VR{fs} base=%016VR{fs_base} limit=%08VR{fs_lim} flags=%04VR{fs_attr}} cr4=%016VR{cr4}\n"
4359	"gs={%04VR{gs} base=%016VR{gs_base} limit=%08VR{gs_lim} flags=%04VR{gs_attr}} cr8=%016VR{cr8}\n"
4360	"ss={%04VR{ss} base=%016VR{ss_base} limit=%08VR{ss_lim} flags=%04VR{ss_attr}}\n"
4361	"dr0=%016VR{dr0} dr1=%016VR{dr1} dr2=%016VR{dr2} dr3=%016VR{dr3}\n"
4362	"dr6=%016VR{dr6} dr7=%016VR{dr7}\n"
4363	"gdtr=%016VR{gdtr_base}:%04VR{gdtr_lim} idtr=%016VR{idtr_base}:%04VR{idtr_lim} rflags=%08VR{rflags}\n"
4364	"ldtr={%04VR{ldtr} base=%016VR{ldtr_base} limit=%08VR{ldtr_lim} flags=%08VR{ldtr_attr}}\n"
4365	"tr ={%04VR{tr} base=%016VR{tr_base} limit=%08VR{tr_lim} flags=%08VR{tr_attr}}\n"
4366	" sysenter={cs=%04VR{sysenter_cs} eip=%08VR{sysenter_eip} esp=%08VR{sysenter_esp}}\n"
4367	" efer=%016VR{efer}\n"
4368	" pat=%016VR{pat}\n"
4369	" sf_mask=%016VR{sf_mask}\n"
4370	"krnl_gs_base=%016VR{krnl_gs_base}\n"
4371	" lstar=%016VR{lstar}\n"
4372	" star=%016VR{star} cstar=%016VR{cstar}\n"
4373	"fcw=%04VR{fcw} fsw=%04VR{fsw} ftw=%04VR{ftw} mxcsr=%04VR{mxcsr} mxcsr_mask=%04VR{mxcsr_mask}\n"
4374	);
4375
4376	char szInstr[256];
4377	DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
4378	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
4379	szInstr, sizeof(szInstr), NULL);
4380
4381	RTAssertMsg2Weak("%s%s\n", szRegs, szInstr);
4382	#else
4383	RTAssertMsg2Weak("cs:rip=%04x:%RX64\n", pIemCpu->CTX_SUFF(pCtx)->cs, pIemCpu->CTX_SUFF(pCtx)->rip);
4384	#endif
4385	}
4386
4387	/**
4388	* Complains about a stub.
4389	*
4390	* Providing two versions of this macro, one for daily use and one for use when
4391	* working on IEM.
4392	*/
4393	#if 0
4394	# define IEMOP_BITCH_ABOUT_STUB() \
4395	do { \
4396	RTAssertMsg1(NULL, __LINE__, __FILE__, __FUNCTION__); \
4397	iemOpStubMsg2(pIemCpu); \
4398	RTAssertPanic(); \
4399	} while (0)
4400	#else
4401	# define IEMOP_BITCH_ABOUT_STUB() Log(("Stub: %s (line %d)\n", __FUNCTION__, __LINE__));
4402	#endif
4403
4404	/** Stubs an opcode. */
4405	#define FNIEMOP_STUB(a_Name) \
4406	FNIEMOP_DEF(a_Name) \
4407	{ \
4408	IEMOP_BITCH_ABOUT_STUB(); \
4409	return VERR_IEM_INSTR_NOT_IMPLEMENTED; \
4410	} \
4411	typedef int ignore_semicolon
4412
4413	/** Stubs an opcode. */
4414	#define FNIEMOP_STUB_1(a_Name, a_Type0, a_Name0) \
4415	FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4416	{ \
4417	IEMOP_BITCH_ABOUT_STUB(); \
4418	NOREF(a_Name0); \
4419	return VERR_IEM_INSTR_NOT_IMPLEMENTED; \
4420	} \
4421	typedef int ignore_semicolon
4422
4423	/** Stubs an opcode which currently should raise \#UD. */
4424	#define FNIEMOP_UD_STUB(a_Name) \
4425	FNIEMOP_DEF(a_Name) \
4426	{ \
4427	Log(("Unsupported instruction %Rfn\n", __FUNCTION__)); \
4428	return IEMOP_RAISE_INVALID_OPCODE(); \
4429	} \
4430	typedef int ignore_semicolon
4431
4432	/** Stubs an opcode which currently should raise \#UD. */
4433	#define FNIEMOP_UD_STUB_1(a_Name, a_Type0, a_Name0) \
4434	FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4435	{ \
4436	NOREF(a_Name0); \
4437	Log(("Unsupported instruction %Rfn\n", __FUNCTION__)); \
4438	return IEMOP_RAISE_INVALID_OPCODE(); \
4439	} \
4440	typedef int ignore_semicolon
4441
4442
4443
4444	/** @name Register Access.
4445	* @{
4446	*/
4447
4448	/**
4449	* Gets a reference (pointer) to the specified hidden segment register.
4450	*
4451	* @returns Hidden register reference.
4452	* @param pIemCpu The per CPU data.
4453	* @param iSegReg The segment register.
4454	*/
4455	static PCPUMSELREG iemSRegGetHid(PIEMCPU pIemCpu, uint8_t iSegReg)
4456	{
4457	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4458	PCPUMSELREG pSReg;
4459	switch (iSegReg)
4460	{
4461	case X86_SREG_ES: pSReg = &pCtx->es; break;
4462	case X86_SREG_CS: pSReg = &pCtx->cs; break;
4463	case X86_SREG_SS: pSReg = &pCtx->ss; break;
4464	case X86_SREG_DS: pSReg = &pCtx->ds; break;
4465	case X86_SREG_FS: pSReg = &pCtx->fs; break;
4466	case X86_SREG_GS: pSReg = &pCtx->gs; break;
4467	default:
4468	AssertFailedReturn(NULL);
4469	}
4470	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
4471	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(IEMCPU_TO_VMCPU(pIemCpu), pSReg))
4472	CPUMGuestLazyLoadHiddenSelectorReg(IEMCPU_TO_VMCPU(pIemCpu), pSReg);
4473	#else
4474	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(IEMCPU_TO_VMCPU(pIemCpu), pSReg));
4475	#endif
4476	return pSReg;
4477	}
4478
4479
4480	/**
4481	* Gets a reference (pointer) to the specified segment register (the selector
4482	* value).
4483	*
4484	* @returns Pointer to the selector variable.
4485	* @param pIemCpu The per CPU data.
4486	* @param iSegReg The segment register.
4487	*/
4488	static uint16_t *iemSRegRef(PIEMCPU pIemCpu, uint8_t iSegReg)
4489	{
4490	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4491	switch (iSegReg)
4492	{
4493	case X86_SREG_ES: return &pCtx->es.Sel;
4494	case X86_SREG_CS: return &pCtx->cs.Sel;
4495	case X86_SREG_SS: return &pCtx->ss.Sel;
4496	case X86_SREG_DS: return &pCtx->ds.Sel;
4497	case X86_SREG_FS: return &pCtx->fs.Sel;
4498	case X86_SREG_GS: return &pCtx->gs.Sel;
4499	}
4500	AssertFailedReturn(NULL);
4501	}
4502
4503
4504	/**
4505	* Fetches the selector value of a segment register.
4506	*
4507	* @returns The selector value.
4508	* @param pIemCpu The per CPU data.
4509	* @param iSegReg The segment register.
4510	*/
4511	static uint16_t iemSRegFetchU16(PIEMCPU pIemCpu, uint8_t iSegReg)
4512	{
4513	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4514	switch (iSegReg)
4515	{
4516	case X86_SREG_ES: return pCtx->es.Sel;
4517	case X86_SREG_CS: return pCtx->cs.Sel;
4518	case X86_SREG_SS: return pCtx->ss.Sel;
4519	case X86_SREG_DS: return pCtx->ds.Sel;
4520	case X86_SREG_FS: return pCtx->fs.Sel;
4521	case X86_SREG_GS: return pCtx->gs.Sel;
4522	}
4523	AssertFailedReturn(0xffff);
4524	}
4525
4526
4527	/**
4528	* Gets a reference (pointer) to the specified general register.
4529	*
4530	* @returns Register reference.
4531	* @param pIemCpu The per CPU data.
4532	* @param iReg The general register.
4533	*/
4534	static void *iemGRegRef(PIEMCPU pIemCpu, uint8_t iReg)
4535	{
4536	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4537	switch (iReg)
4538	{
4539	case X86_GREG_xAX: return &pCtx->rax;
4540	case X86_GREG_xCX: return &pCtx->rcx;
4541	case X86_GREG_xDX: return &pCtx->rdx;
4542	case X86_GREG_xBX: return &pCtx->rbx;
4543	case X86_GREG_xSP: return &pCtx->rsp;
4544	case X86_GREG_xBP: return &pCtx->rbp;
4545	case X86_GREG_xSI: return &pCtx->rsi;
4546	case X86_GREG_xDI: return &pCtx->rdi;
4547	case X86_GREG_x8: return &pCtx->r8;
4548	case X86_GREG_x9: return &pCtx->r9;
4549	case X86_GREG_x10: return &pCtx->r10;
4550	case X86_GREG_x11: return &pCtx->r11;
4551	case X86_GREG_x12: return &pCtx->r12;
4552	case X86_GREG_x13: return &pCtx->r13;
4553	case X86_GREG_x14: return &pCtx->r14;
4554	case X86_GREG_x15: return &pCtx->r15;
4555	}
4556	AssertFailedReturn(NULL);
4557	}
4558
4559
4560	/**
4561	* Gets a reference (pointer) to the specified 8-bit general register.
4562	*
4563	* Because of AH, CH, DH and BH we cannot use iemGRegRef directly here.
4564	*
4565	* @returns Register reference.
4566	* @param pIemCpu The per CPU data.
4567	* @param iReg The register.
4568	*/
4569	static uint8_t *iemGRegRefU8(PIEMCPU pIemCpu, uint8_t iReg)
4570	{
4571	if (pIemCpu->fPrefixes & IEM_OP_PRF_REX)
4572	return (uint8_t *)iemGRegRef(pIemCpu, iReg);
4573
4574	uint8_t pu8Reg = (uint8_t )iemGRegRef(pIemCpu, iReg & 3);
4575	if (iReg >= 4)
4576	pu8Reg++;
4577	return pu8Reg;
4578	}
4579
4580
4581	/**
4582	* Fetches the value of a 8-bit general register.
4583	*
4584	* @returns The register value.
4585	* @param pIemCpu The per CPU data.
4586	* @param iReg The register.
4587	*/
4588	static uint8_t iemGRegFetchU8(PIEMCPU pIemCpu, uint8_t iReg)
4589	{
4590	uint8_t const *pbSrc = iemGRegRefU8(pIemCpu, iReg);
4591	return *pbSrc;
4592	}
4593
4594
4595	/**
4596	* Fetches the value of a 16-bit general register.
4597	*
4598	* @returns The register value.
4599	* @param pIemCpu The per CPU data.
4600	* @param iReg The register.
4601	*/
4602	static uint16_t iemGRegFetchU16(PIEMCPU pIemCpu, uint8_t iReg)
4603	{
4604	return (uint16_t )iemGRegRef(pIemCpu, iReg);
4605	}
4606
4607
4608	/**
4609	* Fetches the value of a 32-bit general register.
4610	*
4611	* @returns The register value.
4612	* @param pIemCpu The per CPU data.
4613	* @param iReg The register.
4614	*/
4615	static uint32_t iemGRegFetchU32(PIEMCPU pIemCpu, uint8_t iReg)
4616	{
4617	return (uint32_t )iemGRegRef(pIemCpu, iReg);
4618	}
4619
4620
4621	/**
4622	* Fetches the value of a 64-bit general register.
4623	*
4624	* @returns The register value.
4625	* @param pIemCpu The per CPU data.
4626	* @param iReg The register.
4627	*/
4628	static uint64_t iemGRegFetchU64(PIEMCPU pIemCpu, uint8_t iReg)
4629	{
4630	return (uint64_t )iemGRegRef(pIemCpu, iReg);
4631	}
4632
4633
4634	/**
4635	* Is the FPU state in FXSAVE format or not.
4636	*
4637	* @returns true if it is, false if it's in FNSAVE.
4638	* @param pVCpu Pointer to the VMCPU.
4639	*/
4640	DECLINLINE(bool) iemFRegIsFxSaveFormat(PIEMCPU pIemCpu)
4641	{
4642	#ifdef RT_ARCH_AMD64
4643	NOREF(pIemCpu);
4644	return true;
4645	#else
4646	NOREF(pIemCpu); /// @todo return pVCpu->pVMR3->cpum.s.CPUFeatures.edx.u1FXSR;
4647	return true;
4648	#endif
4649	}
4650
4651
4652	/**
4653	* Adds a 8-bit signed jump offset to RIP/EIP/IP.
4654	*
4655	* May raise a \#GP(0) if the new RIP is non-canonical or outside the code
4656	* segment limit.
4657	*
4658	* @param pIemCpu The per CPU data.
4659	* @param offNextInstr The offset of the next instruction.
4660	*/
4661	static VBOXSTRICTRC iemRegRipRelativeJumpS8(PIEMCPU pIemCpu, int8_t offNextInstr)
4662	{
4663	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4664	switch (pIemCpu->enmEffOpSize)
4665	{
4666	case IEMMODE_16BIT:
4667	{
4668	uint16_t uNewIp = pCtx->ip + offNextInstr + pIemCpu->offOpcode;
4669	if ( uNewIp > pCtx->cs.u32Limit
4670	&& pIemCpu->enmCpuMode != IEMMODE_64BIT) /* no need to check for non-canonical. */
4671	return iemRaiseGeneralProtectionFault0(pIemCpu);
4672	pCtx->rip = uNewIp;
4673	break;
4674	}
4675
4676	case IEMMODE_32BIT:
4677	{
4678	Assert(pCtx->rip <= UINT32_MAX);
4679	Assert(pIemCpu->enmCpuMode != IEMMODE_64BIT);
4680
4681	uint32_t uNewEip = pCtx->eip + offNextInstr + pIemCpu->offOpcode;
4682	if (uNewEip > pCtx->cs.u32Limit)
4683	return iemRaiseGeneralProtectionFault0(pIemCpu);
4684	pCtx->rip = uNewEip;
4685	break;
4686	}
4687
4688	case IEMMODE_64BIT:
4689	{
4690	Assert(pIemCpu->enmCpuMode == IEMMODE_64BIT);
4691
4692	uint64_t uNewRip = pCtx->rip + offNextInstr + pIemCpu->offOpcode;
4693	if (!IEM_IS_CANONICAL(uNewRip))
4694	return iemRaiseGeneralProtectionFault0(pIemCpu);
4695	pCtx->rip = uNewRip;
4696	break;
4697	}
4698
4699	IEM_NOT_REACHED_DEFAULT_CASE_RET();
4700	}
4701
4702	pCtx->eflags.Bits.u1RF = 0;
4703	return VINF_SUCCESS;
4704	}
4705
4706
4707	/**
4708	* Adds a 16-bit signed jump offset to RIP/EIP/IP.
4709	*
4710	* May raise a \#GP(0) if the new RIP is non-canonical or outside the code
4711	* segment limit.
4712	*
4713	* @returns Strict VBox status code.
4714	* @param pIemCpu The per CPU data.
4715	* @param offNextInstr The offset of the next instruction.
4716	*/
4717	static VBOXSTRICTRC iemRegRipRelativeJumpS16(PIEMCPU pIemCpu, int16_t offNextInstr)
4718	{
4719	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4720	Assert(pIemCpu->enmEffOpSize == IEMMODE_16BIT);
4721
4722	uint16_t uNewIp = pCtx->ip + offNextInstr + pIemCpu->offOpcode;
4723	if ( uNewIp > pCtx->cs.u32Limit
4724	&& pIemCpu->enmCpuMode != IEMMODE_64BIT) /* no need to check for non-canonical. */
4725	return iemRaiseGeneralProtectionFault0(pIemCpu);
4726	/** @todo Test 16-bit jump in 64-bit mode. possible? */
4727	pCtx->rip = uNewIp;
4728	pCtx->eflags.Bits.u1RF = 0;
4729
4730	return VINF_SUCCESS;
4731	}
4732
4733
4734	/**
4735	* Adds a 32-bit signed jump offset to RIP/EIP/IP.
4736	*
4737	* May raise a \#GP(0) if the new RIP is non-canonical or outside the code
4738	* segment limit.
4739	*
4740	* @returns Strict VBox status code.
4741	* @param pIemCpu The per CPU data.
4742	* @param offNextInstr The offset of the next instruction.
4743	*/
4744	static VBOXSTRICTRC iemRegRipRelativeJumpS32(PIEMCPU pIemCpu, int32_t offNextInstr)
4745	{
4746	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4747	Assert(pIemCpu->enmEffOpSize != IEMMODE_16BIT);
4748
4749	if (pIemCpu->enmEffOpSize == IEMMODE_32BIT)
4750	{
4751	Assert(pCtx->rip <= UINT32_MAX); Assert(pIemCpu->enmCpuMode != IEMMODE_64BIT);
4752
4753	uint32_t uNewEip = pCtx->eip + offNextInstr + pIemCpu->offOpcode;
4754	if (uNewEip > pCtx->cs.u32Limit)
4755	return iemRaiseGeneralProtectionFault0(pIemCpu);
4756	pCtx->rip = uNewEip;
4757	}
4758	else
4759	{
4760	Assert(pIemCpu->enmCpuMode == IEMMODE_64BIT);
4761
4762	uint64_t uNewRip = pCtx->rip + offNextInstr + pIemCpu->offOpcode;
4763	if (!IEM_IS_CANONICAL(uNewRip))
4764	return iemRaiseGeneralProtectionFault0(pIemCpu);
4765	pCtx->rip = uNewRip;
4766	}
4767	pCtx->eflags.Bits.u1RF = 0;
4768	return VINF_SUCCESS;
4769	}
4770
4771
4772	/**
4773	* Performs a near jump to the specified address.
4774	*
4775	* May raise a \#GP(0) if the new RIP is non-canonical or outside the code
4776	* segment limit.
4777	*
4778	* @param pIemCpu The per CPU data.
4779	* @param uNewRip The new RIP value.
4780	*/
4781	static VBOXSTRICTRC iemRegRipJump(PIEMCPU pIemCpu, uint64_t uNewRip)
4782	{
4783	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4784	switch (pIemCpu->enmEffOpSize)
4785	{
4786	case IEMMODE_16BIT:
4787	{
4788	Assert(uNewRip <= UINT16_MAX);
4789	if ( uNewRip > pCtx->cs.u32Limit
4790	&& pIemCpu->enmCpuMode != IEMMODE_64BIT) /* no need to check for non-canonical. */
4791	return iemRaiseGeneralProtectionFault0(pIemCpu);
4792	/** @todo Test 16-bit jump in 64-bit mode. */
4793	pCtx->rip = uNewRip;
4794	break;
4795	}
4796
4797	case IEMMODE_32BIT:
4798	{
4799	Assert(uNewRip <= UINT32_MAX);
4800	Assert(pCtx->rip <= UINT32_MAX);
4801	Assert(pIemCpu->enmCpuMode != IEMMODE_64BIT);
4802
4803	if (uNewRip > pCtx->cs.u32Limit)
4804	return iemRaiseGeneralProtectionFault0(pIemCpu);
4805	pCtx->rip = uNewRip;
4806	break;
4807	}
4808
4809	case IEMMODE_64BIT:
4810	{
4811	Assert(pIemCpu->enmCpuMode == IEMMODE_64BIT);
4812
4813	if (!IEM_IS_CANONICAL(uNewRip))
4814	return iemRaiseGeneralProtectionFault0(pIemCpu);
4815	pCtx->rip = uNewRip;
4816	break;
4817	}
4818
4819	IEM_NOT_REACHED_DEFAULT_CASE_RET();
4820	}
4821
4822	pCtx->eflags.Bits.u1RF = 0;
4823	return VINF_SUCCESS;
4824	}
4825
4826
4827	/**
4828	* Get the address of the top of the stack.
4829	*
4830	* @param pIemCpu The per CPU data.
4831	* @param pCtx The CPU context which SP/ESP/RSP should be
4832	* read.
4833	*/
4834	DECLINLINE(RTGCPTR) iemRegGetEffRsp(PCIEMCPU pIemCpu, PCCPUMCTX pCtx)
4835	{
4836	if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
4837	return pCtx->rsp;
4838	if (pCtx->ss.Attr.n.u1DefBig)
4839	return pCtx->esp;
4840	return pCtx->sp;
4841	}
4842
4843
4844	/**
4845	* Updates the RIP/EIP/IP to point to the next instruction.
4846	*
4847	* This function leaves the EFLAGS.RF flag alone.
4848	*
4849	* @param pIemCpu The per CPU data.
4850	* @param cbInstr The number of bytes to add.
4851	*/
4852	static void iemRegAddToRipKeepRF(PIEMCPU pIemCpu, uint8_t cbInstr)
4853	{
4854	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4855	switch (pIemCpu->enmCpuMode)
4856	{
4857	case IEMMODE_16BIT:
4858	Assert(pCtx->rip <= UINT16_MAX);
4859	pCtx->eip += cbInstr;
4860	pCtx->eip &= UINT32_C(0xffff);
4861	break;
4862
4863	case IEMMODE_32BIT:
4864	pCtx->eip += cbInstr;
4865	Assert(pCtx->rip <= UINT32_MAX);
4866	break;
4867
4868	case IEMMODE_64BIT:
4869	pCtx->rip += cbInstr;
4870	break;
4871	default: AssertFailed();
4872	}
4873	}
4874
4875
4876	#if 0
4877	/**
4878	* Updates the RIP/EIP/IP to point to the next instruction.
4879	*
4880	* @param pIemCpu The per CPU data.
4881	*/
4882	static void iemRegUpdateRipKeepRF(PIEMCPU pIemCpu)
4883	{
4884	return iemRegAddToRipKeepRF(pIemCpu, pIemCpu->offOpcode);
4885	}
4886	#endif
4887
4888
4889
4890	/**
4891	* Updates the RIP/EIP/IP to point to the next instruction and clears EFLAGS.RF.
4892	*
4893	* @param pIemCpu The per CPU data.
4894	* @param cbInstr The number of bytes to add.
4895	*/
4896	static void iemRegAddToRipAndClearRF(PIEMCPU pIemCpu, uint8_t cbInstr)
4897	{
4898	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4899
4900	pCtx->eflags.Bits.u1RF = 0;
4901
4902	switch (pIemCpu->enmCpuMode)
4903	{
4904	case IEMMODE_16BIT:
4905	Assert(pCtx->rip <= UINT16_MAX);
4906	pCtx->eip += cbInstr;
4907	pCtx->eip &= UINT32_C(0xffff);
4908	break;
4909
4910	case IEMMODE_32BIT:
4911	pCtx->eip += cbInstr;
4912	Assert(pCtx->rip <= UINT32_MAX);
4913	break;
4914
4915	case IEMMODE_64BIT:
4916	pCtx->rip += cbInstr;
4917	break;
4918	default: AssertFailed();
4919	}
4920	}
4921
4922
4923	/**
4924	* Updates the RIP/EIP/IP to point to the next instruction and clears EFLAGS.RF.
4925	*
4926	* @param pIemCpu The per CPU data.
4927	*/
4928	static void iemRegUpdateRipAndClearRF(PIEMCPU pIemCpu)
4929	{
4930	return iemRegAddToRipAndClearRF(pIemCpu, pIemCpu->offOpcode);
4931	}
4932
4933
4934	/**
4935	* Adds to the stack pointer.
4936	*
4937	* @param pIemCpu The per CPU data.
4938	* @param pCtx The CPU context which SP/ESP/RSP should be
4939	* updated.
4940	* @param cbToAdd The number of bytes to add.
4941	*/
4942	DECLINLINE(void) iemRegAddToRsp(PCIEMCPU pIemCpu, PCPUMCTX pCtx, uint8_t cbToAdd)
4943	{
4944	if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
4945	pCtx->rsp += cbToAdd;
4946	else if (pCtx->ss.Attr.n.u1DefBig)
4947	pCtx->esp += cbToAdd;
4948	else
4949	pCtx->sp += cbToAdd;
4950	}
4951
4952
4953	/**
4954	* Subtracts from the stack pointer.
4955	*
4956	* @param pIemCpu The per CPU data.
4957	* @param pCtx The CPU context which SP/ESP/RSP should be
4958	* updated.
4959	* @param cbToSub The number of bytes to subtract.
4960	*/
4961	DECLINLINE(void) iemRegSubFromRsp(PCIEMCPU pIemCpu, PCPUMCTX pCtx, uint8_t cbToSub)
4962	{
4963	if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
4964	pCtx->rsp -= cbToSub;
4965	else if (pCtx->ss.Attr.n.u1DefBig)
4966	pCtx->esp -= cbToSub;
4967	else
4968	pCtx->sp -= cbToSub;
4969	}
4970
4971
4972	/**
4973	* Adds to the temporary stack pointer.
4974	*
4975	* @param pIemCpu The per CPU data.
4976	* @param pTmpRsp The temporary SP/ESP/RSP to update.
4977	* @param cbToAdd The number of bytes to add.
4978	* @param pCtx Where to get the current stack mode.
4979	*/
4980	DECLINLINE(void) iemRegAddToRspEx(PCIEMCPU pIemCpu, PCCPUMCTX pCtx, PRTUINT64U pTmpRsp, uint16_t cbToAdd)
4981	{
4982	if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
4983	pTmpRsp->u += cbToAdd;
4984	else if (pCtx->ss.Attr.n.u1DefBig)
4985	pTmpRsp->DWords.dw0 += cbToAdd;
4986	else
4987	pTmpRsp->Words.w0 += cbToAdd;
4988	}
4989
4990
4991	/**
4992	* Subtracts from the temporary stack pointer.
4993	*
4994	* @param pIemCpu The per CPU data.
4995	* @param pTmpRsp The temporary SP/ESP/RSP to update.
4996	* @param cbToSub The number of bytes to subtract.
4997	* @param pCtx Where to get the current stack mode.
4998	* @remarks The @a cbToSub argument MUST be 16-bit, iemCImpl_enter is
4999	* expecting that.
5000	*/
5001	DECLINLINE(void) iemRegSubFromRspEx(PCIEMCPU pIemCpu, PCCPUMCTX pCtx, PRTUINT64U pTmpRsp, uint16_t cbToSub)
5002	{
5003	if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
5004	pTmpRsp->u -= cbToSub;
5005	else if (pCtx->ss.Attr.n.u1DefBig)
5006	pTmpRsp->DWords.dw0 -= cbToSub;
5007	else
5008	pTmpRsp->Words.w0 -= cbToSub;
5009	}
5010
5011
5012	/**
5013	* Calculates the effective stack address for a push of the specified size as
5014	* well as the new RSP value (upper bits may be masked).
5015	*
5016	* @returns Effective stack addressf for the push.
5017	* @param pIemCpu The IEM per CPU data.
5018	* @param pCtx Where to get the current stack mode.
5019	* @param cbItem The size of the stack item to pop.
5020	* @param puNewRsp Where to return the new RSP value.
5021	*/
5022	DECLINLINE(RTGCPTR) iemRegGetRspForPush(PCIEMCPU pIemCpu, PCCPUMCTX pCtx, uint8_t cbItem, uint64_t *puNewRsp)
5023	{
5024	RTUINT64U uTmpRsp;
5025	RTGCPTR GCPtrTop;
5026	uTmpRsp.u = pCtx->rsp;
5027
5028	if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
5029	GCPtrTop = uTmpRsp.u -= cbItem;
5030	else if (pCtx->ss.Attr.n.u1DefBig)
5031	GCPtrTop = uTmpRsp.DWords.dw0 -= cbItem;
5032	else
5033	GCPtrTop = uTmpRsp.Words.w0 -= cbItem;
5034	*puNewRsp = uTmpRsp.u;
5035	return GCPtrTop;
5036	}
5037
5038
5039	/**
5040	* Gets the current stack pointer and calculates the value after a pop of the
5041	* specified size.
5042	*
5043	* @returns Current stack pointer.
5044	* @param pIemCpu The per CPU data.
5045	* @param pCtx Where to get the current stack mode.
5046	* @param cbItem The size of the stack item to pop.
5047	* @param puNewRsp Where to return the new RSP value.
5048	*/
5049	DECLINLINE(RTGCPTR) iemRegGetRspForPop(PCIEMCPU pIemCpu, PCCPUMCTX pCtx, uint8_t cbItem, uint64_t *puNewRsp)
5050	{
5051	RTUINT64U uTmpRsp;
5052	RTGCPTR GCPtrTop;
5053	uTmpRsp.u = pCtx->rsp;
5054
5055	if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
5056	{
5057	GCPtrTop = uTmpRsp.u;
5058	uTmpRsp.u += cbItem;
5059	}
5060	else if (pCtx->ss.Attr.n.u1DefBig)
5061	{
5062	GCPtrTop = uTmpRsp.DWords.dw0;
5063	uTmpRsp.DWords.dw0 += cbItem;
5064	}
5065	else
5066	{
5067	GCPtrTop = uTmpRsp.Words.w0;
5068	uTmpRsp.Words.w0 += cbItem;
5069	}
5070	*puNewRsp = uTmpRsp.u;
5071	return GCPtrTop;
5072	}
5073
5074
5075	/**
5076	* Calculates the effective stack address for a push of the specified size as
5077	* well as the new temporary RSP value (upper bits may be masked).
5078	*
5079	* @returns Effective stack addressf for the push.
5080	* @param pIemCpu The per CPU data.
5081	* @param pTmpRsp The temporary stack pointer. This is updated.
5082	* @param cbItem The size of the stack item to pop.
5083	* @param puNewRsp Where to return the new RSP value.
5084	*/
5085	DECLINLINE(RTGCPTR) iemRegGetRspForPushEx(PCIEMCPU pIemCpu, PCCPUMCTX pCtx, PRTUINT64U pTmpRsp, uint8_t cbItem)
5086	{
5087	RTGCPTR GCPtrTop;
5088
5089	if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
5090	GCPtrTop = pTmpRsp->u -= cbItem;
5091	else if (pCtx->ss.Attr.n.u1DefBig)
5092	GCPtrTop = pTmpRsp->DWords.dw0 -= cbItem;
5093	else
5094	GCPtrTop = pTmpRsp->Words.w0 -= cbItem;
5095	return GCPtrTop;
5096	}
5097
5098
5099	/**
5100	* Gets the effective stack address for a pop of the specified size and
5101	* calculates and updates the temporary RSP.
5102	*
5103	* @returns Current stack pointer.
5104	* @param pIemCpu The per CPU data.
5105	* @param pTmpRsp The temporary stack pointer. This is updated.
5106	* @param pCtx Where to get the current stack mode.
5107	* @param cbItem The size of the stack item to pop.
5108	*/
5109	DECLINLINE(RTGCPTR) iemRegGetRspForPopEx(PCIEMCPU pIemCpu, PCCPUMCTX pCtx, PRTUINT64U pTmpRsp, uint8_t cbItem)
5110	{
5111	RTGCPTR GCPtrTop;
5112	if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
5113	{
5114	GCPtrTop = pTmpRsp->u;
5115	pTmpRsp->u += cbItem;
5116	}
5117	else if (pCtx->ss.Attr.n.u1DefBig)
5118	{
5119	GCPtrTop = pTmpRsp->DWords.dw0;
5120	pTmpRsp->DWords.dw0 += cbItem;
5121	}
5122	else
5123	{
5124	GCPtrTop = pTmpRsp->Words.w0;
5125	pTmpRsp->Words.w0 += cbItem;
5126	}
5127	return GCPtrTop;
5128	}
5129
5130
5131	/**
5132	* Checks if an Intel CPUID feature bit is set.
5133	*
5134	* @returns true / false.
5135	*
5136	* @param pIemCpu The IEM per CPU data.
5137	* @param fEdx The EDX bit to test, or 0 if ECX.
5138	* @param fEcx The ECX bit to test, or 0 if EDX.
5139	* @remarks Used via IEM_IS_INTEL_CPUID_FEATURE_PRESENT_EDX,
5140	* IEM_IS_INTEL_CPUID_FEATURE_PRESENT_ECX and others.
5141	*/
5142	static bool iemRegIsIntelCpuIdFeaturePresent(PIEMCPU pIemCpu, uint32_t fEdx, uint32_t fEcx)
5143	{
5144	uint32_t uEax, uEbx, uEcx, uEdx;
5145	CPUMGetGuestCpuId(IEMCPU_TO_VMCPU(pIemCpu), 0x00000001, &uEax, &uEbx, &uEcx, &uEdx);
5146	return (fEcx && (uEcx & fEcx))
5147	\|\| (fEdx && (uEdx & fEdx));
5148	}
5149
5150
5151	/**
5152	* Checks if an AMD CPUID feature bit is set.
5153	*
5154	* @returns true / false.
5155	*
5156	* @param pIemCpu The IEM per CPU data.
5157	* @param fEdx The EDX bit to test, or 0 if ECX.
5158	* @param fEcx The ECX bit to test, or 0 if EDX.
5159	* @remarks Used via IEM_IS_AMD_CPUID_FEATURE_PRESENT_EDX,
5160	* IEM_IS_AMD_CPUID_FEATURE_PRESENT_ECX and others.
5161	*/
5162	static bool iemRegIsAmdCpuIdFeaturePresent(PIEMCPU pIemCpu, uint32_t fEdx, uint32_t fEcx)
5163	{
5164	uint32_t uEax, uEbx, uEcx, uEdx;
5165	CPUMGetGuestCpuId(IEMCPU_TO_VMCPU(pIemCpu), 0x80000001, &uEax, &uEbx, &uEcx, &uEdx);
5166	return (fEcx && (uEcx & fEcx))
5167	\|\| (fEdx && (uEdx & fEdx));
5168	}
5169
5170	/** @} */
5171
5172
5173	/** @name FPU access and helpers.
5174	*
5175	* @{
5176	*/
5177
5178
5179	/**
5180	* Hook for preparing to use the host FPU.
5181	*
5182	* This is necessary in ring-0 and raw-mode context.
5183	*
5184	* @param pIemCpu The IEM per CPU data.
5185	*/
5186	DECLINLINE(void) iemFpuPrepareUsage(PIEMCPU pIemCpu)
5187	{
5188	#ifdef IN_RING3
5189	NOREF(pIemCpu);
5190	#else
5191	/** @todo RZ: FIXME */
5192	//# error "Implement me"
5193	#endif
5194	}
5195
5196
5197	/**
5198	* Hook for preparing to use the host FPU for SSE
5199	*
5200	* This is necessary in ring-0 and raw-mode context.
5201	*
5202	* @param pIemCpu The IEM per CPU data.
5203	*/
5204	DECLINLINE(void) iemFpuPrepareUsageSse(PIEMCPU pIemCpu)
5205	{
5206	iemFpuPrepareUsage(pIemCpu);
5207	}
5208
5209
5210	/**
5211	* Stores a QNaN value into a FPU register.
5212	*
5213	* @param pReg Pointer to the register.
5214	*/
5215	DECLINLINE(void) iemFpuStoreQNan(PRTFLOAT80U pReg)
5216	{
5217	pReg->au32[0] = UINT32_C(0x00000000);
5218	pReg->au32[1] = UINT32_C(0xc0000000);
5219	pReg->au16[4] = UINT16_C(0xffff);
5220	}
5221
5222
5223	/**
5224	* Updates the FOP, FPU.CS and FPUIP registers.
5225	*
5226	* @param pIemCpu The IEM per CPU data.
5227	* @param pCtx The CPU context.
5228	*/
5229	DECLINLINE(void) iemFpuUpdateOpcodeAndIpWorker(PIEMCPU pIemCpu, PCPUMCTX pCtx)
5230	{
5231	pCtx->fpu.FOP = pIemCpu->abOpcode[pIemCpu->offFpuOpcode]
5232	\| ((uint16_t)(pIemCpu->abOpcode[pIemCpu->offFpuOpcode - 1] & 0x7) << 8);
5233	/** @todo FPU.CS and FPUIP needs to be kept seperately. */
5234	if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
5235	{
5236	/** @todo Testcase: making assumptions about how FPUIP and FPUDP are handled
5237	* happens in real mode here based on the fnsave and fnstenv images. */
5238	pCtx->fpu.CS = 0;
5239	pCtx->fpu.FPUIP = pCtx->eip \| ((uint32_t)pCtx->cs.Sel << 4);
5240	}
5241	else
5242	{
5243	pCtx->fpu.CS = pCtx->cs.Sel;
5244	pCtx->fpu.FPUIP = pCtx->rip;
5245	}
5246	}
5247
5248
5249	/**
5250	* Updates the FPU.DS and FPUDP registers.
5251	*
5252	* @param pIemCpu The IEM per CPU data.
5253	* @param pCtx The CPU context.
5254	* @param iEffSeg The effective segment register.
5255	* @param GCPtrEff The effective address relative to @a iEffSeg.
5256	*/
5257	DECLINLINE(void) iemFpuUpdateDP(PIEMCPU pIemCpu, PCPUMCTX pCtx, uint8_t iEffSeg, RTGCPTR GCPtrEff)
5258	{
5259	RTSEL sel;
5260	switch (iEffSeg)
5261	{
5262	case X86_SREG_DS: sel = pCtx->ds.Sel; break;
5263	case X86_SREG_SS: sel = pCtx->ss.Sel; break;
5264	case X86_SREG_CS: sel = pCtx->cs.Sel; break;
5265	case X86_SREG_ES: sel = pCtx->es.Sel; break;
5266	case X86_SREG_FS: sel = pCtx->fs.Sel; break;
5267	case X86_SREG_GS: sel = pCtx->gs.Sel; break;
5268	default:
5269	AssertMsgFailed(("%d\n", iEffSeg));
5270	sel = pCtx->ds.Sel;
5271	}
5272	/** @todo FPU.DS and FPUDP needs to be kept seperately. */
5273	if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
5274	{
5275	pCtx->fpu.DS = 0;
5276	pCtx->fpu.FPUDP = (uint32_t)GCPtrEff \| ((uint32_t)sel << 4);
5277	}
5278	else
5279	{
5280	pCtx->fpu.DS = sel;
5281	pCtx->fpu.FPUDP = GCPtrEff;
5282	}
5283	}
5284
5285
5286	/**
5287	* Rotates the stack registers in the push direction.
5288	*
5289	* @param pCtx The CPU context.
5290	* @remarks This is a complete waste of time, but fxsave stores the registers in
5291	* stack order.
5292	*/
5293	DECLINLINE(void) iemFpuRotateStackPush(PCPUMCTX pCtx)
5294	{
5295	RTFLOAT80U r80Tmp = pCtx->fpu.aRegs[7].r80;
5296	pCtx->fpu.aRegs[7].r80 = pCtx->fpu.aRegs[6].r80;
5297	pCtx->fpu.aRegs[6].r80 = pCtx->fpu.aRegs[5].r80;
5298	pCtx->fpu.aRegs[5].r80 = pCtx->fpu.aRegs[4].r80;
5299	pCtx->fpu.aRegs[4].r80 = pCtx->fpu.aRegs[3].r80;
5300	pCtx->fpu.aRegs[3].r80 = pCtx->fpu.aRegs[2].r80;
5301	pCtx->fpu.aRegs[2].r80 = pCtx->fpu.aRegs[1].r80;
5302	pCtx->fpu.aRegs[1].r80 = pCtx->fpu.aRegs[0].r80;
5303	pCtx->fpu.aRegs[0].r80 = r80Tmp;
5304	}
5305
5306
5307	/**
5308	* Rotates the stack registers in the pop direction.
5309	*
5310	* @param pCtx The CPU context.
5311	* @remarks This is a complete waste of time, but fxsave stores the registers in
5312	* stack order.
5313	*/
5314	DECLINLINE(void) iemFpuRotateStackPop(PCPUMCTX pCtx)
5315	{
5316	RTFLOAT80U r80Tmp = pCtx->fpu.aRegs[0].r80;
5317	pCtx->fpu.aRegs[0].r80 = pCtx->fpu.aRegs[1].r80;
5318	pCtx->fpu.aRegs[1].r80 = pCtx->fpu.aRegs[2].r80;
5319	pCtx->fpu.aRegs[2].r80 = pCtx->fpu.aRegs[3].r80;
5320	pCtx->fpu.aRegs[3].r80 = pCtx->fpu.aRegs[4].r80;
5321	pCtx->fpu.aRegs[4].r80 = pCtx->fpu.aRegs[5].r80;
5322	pCtx->fpu.aRegs[5].r80 = pCtx->fpu.aRegs[6].r80;
5323	pCtx->fpu.aRegs[6].r80 = pCtx->fpu.aRegs[7].r80;
5324	pCtx->fpu.aRegs[7].r80 = r80Tmp;
5325	}
5326
5327
5328	/**
5329	* Updates FSW and pushes a FPU result onto the FPU stack if no pending
5330	* exception prevents it.
5331	*
5332	* @param pIemCpu The IEM per CPU data.
5333	* @param pResult The FPU operation result to push.
5334	* @param pCtx The CPU context.
5335	*/
5336	static void iemFpuMaybePushResult(PIEMCPU pIemCpu, PIEMFPURESULT pResult, PCPUMCTX pCtx)
5337	{
5338	/* Update FSW and bail if there are pending exceptions afterwards. */
5339	uint16_t fFsw = pCtx->fpu.FSW & ~X86_FSW_C_MASK;
5340	fFsw \|= pResult->FSW & ~X86_FSW_TOP_MASK;
5341	if ( (fFsw & (X86_FSW_IE \| X86_FSW_ZE \| X86_FSW_DE))
5342	& ~(pCtx->fpu.FCW & (X86_FCW_IM \| X86_FCW_ZM \| X86_FCW_DM)))
5343	{
5344	pCtx->fpu.FSW = fFsw;
5345	return;
5346	}
5347
5348	uint16_t iNewTop = (X86_FSW_TOP_GET(fFsw) + 7) & X86_FSW_TOP_SMASK;
5349	if (!(pCtx->fpu.FTW & RT_BIT(iNewTop)))
5350	{
5351	/* All is fine, push the actual value. */
5352	pCtx->fpu.FTW \|= RT_BIT(iNewTop);
5353	pCtx->fpu.aRegs[7].r80 = pResult->r80Result;
5354	}
5355	else if (pCtx->fpu.FCW & X86_FCW_IM)
5356	{
5357	/* Masked stack overflow, push QNaN. */
5358	fFsw \|= X86_FSW_IE \| X86_FSW_SF \| X86_FSW_C1;
5359	iemFpuStoreQNan(&pCtx->fpu.aRegs[7].r80);
5360	}
5361	else
5362	{
5363	/* Raise stack overflow, don't push anything. */
5364	pCtx->fpu.FSW \|= pResult->FSW & ~X86_FSW_C_MASK;
5365	pCtx->fpu.FSW \|= X86_FSW_IE \| X86_FSW_SF \| X86_FSW_C1 \| X86_FSW_B \| X86_FSW_ES;
5366	return;
5367	}
5368
5369	fFsw &= ~X86_FSW_TOP_MASK;
5370	fFsw \|= iNewTop << X86_FSW_TOP_SHIFT;
5371	pCtx->fpu.FSW = fFsw;
5372
5373	iemFpuRotateStackPush(pCtx);
5374	}
5375
5376
5377	/**
5378	* Stores a result in a FPU register and updates the FSW and FTW.
5379	*
5380	* @param pIemCpu The IEM per CPU data.
5381	* @param pResult The result to store.
5382	* @param iStReg Which FPU register to store it in.
5383	* @param pCtx The CPU context.
5384	*/
5385	static void iemFpuStoreResultOnly(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iStReg, PCPUMCTX pCtx)
5386	{
5387	Assert(iStReg < 8);
5388	uint16_t iReg = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + iStReg) & X86_FSW_TOP_SMASK;
5389	pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
5390	pCtx->fpu.FSW \|= pResult->FSW & ~X86_FSW_TOP_MASK;
5391	pCtx->fpu.FTW \|= RT_BIT(iReg);
5392	pCtx->fpu.aRegs[iStReg].r80 = pResult->r80Result;
5393	}
5394
5395
5396	/**
5397	* Only updates the FPU status word (FSW) with the result of the current
5398	* instruction.
5399	*
5400	* @param pCtx The CPU context.
5401	* @param u16FSW The FSW output of the current instruction.
5402	*/
5403	static void iemFpuUpdateFSWOnly(PCPUMCTX pCtx, uint16_t u16FSW)
5404	{
5405	pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
5406	pCtx->fpu.FSW \|= u16FSW & ~X86_FSW_TOP_MASK;
5407	}
5408
5409
5410	/**
5411	* Pops one item off the FPU stack if no pending exception prevents it.
5412	*
5413	* @param pCtx The CPU context.
5414	*/
5415	static void iemFpuMaybePopOne(PCPUMCTX pCtx)
5416	{
5417	/* Check pending exceptions. */
5418	uint16_t uFSW = pCtx->fpu.FSW;
5419	if ( (pCtx->fpu.FSW & (X86_FSW_IE \| X86_FSW_ZE \| X86_FSW_DE))
5420	& ~(pCtx->fpu.FCW & (X86_FCW_IM \| X86_FCW_ZM \| X86_FCW_DM)))
5421	return;
5422
5423	/* TOP--. */
5424	uint16_t iOldTop = uFSW & X86_FSW_TOP_MASK;
5425	uFSW &= ~X86_FSW_TOP_MASK;
5426	uFSW \|= (iOldTop + (UINT16_C(9) << X86_FSW_TOP_SHIFT)) & X86_FSW_TOP_MASK;
5427	pCtx->fpu.FSW = uFSW;
5428
5429	/* Mark the previous ST0 as empty. */
5430	iOldTop >>= X86_FSW_TOP_SHIFT;
5431	pCtx->fpu.FTW &= ~RT_BIT(iOldTop);
5432
5433	/* Rotate the registers. */
5434	iemFpuRotateStackPop(pCtx);
5435	}
5436
5437
5438	/**
5439	* Pushes a FPU result onto the FPU stack if no pending exception prevents it.
5440	*
5441	* @param pIemCpu The IEM per CPU data.
5442	* @param pResult The FPU operation result to push.
5443	*/
5444	static void iemFpuPushResult(PIEMCPU pIemCpu, PIEMFPURESULT pResult)
5445	{
5446	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5447	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5448	iemFpuMaybePushResult(pIemCpu, pResult, pCtx);
5449	}
5450
5451
5452	/**
5453	* Pushes a FPU result onto the FPU stack if no pending exception prevents it,
5454	* and sets FPUDP and FPUDS.
5455	*
5456	* @param pIemCpu The IEM per CPU data.
5457	* @param pResult The FPU operation result to push.
5458	* @param iEffSeg The effective segment register.
5459	* @param GCPtrEff The effective address relative to @a iEffSeg.
5460	*/
5461	static void iemFpuPushResultWithMemOp(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff)
5462	{
5463	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5464	iemFpuUpdateDP(pIemCpu, pCtx, iEffSeg, GCPtrEff);
5465	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5466	iemFpuMaybePushResult(pIemCpu, pResult, pCtx);
5467	}
5468
5469
5470	/**
5471	* Replace ST0 with the first value and push the second onto the FPU stack,
5472	* unless a pending exception prevents it.
5473	*
5474	* @param pIemCpu The IEM per CPU data.
5475	* @param pResult The FPU operation result to store and push.
5476	*/
5477	static void iemFpuPushResultTwo(PIEMCPU pIemCpu, PIEMFPURESULTTWO pResult)
5478	{
5479	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5480	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5481
5482	/* Update FSW and bail if there are pending exceptions afterwards. */
5483	uint16_t fFsw = pCtx->fpu.FSW & ~X86_FSW_C_MASK;
5484	fFsw \|= pResult->FSW & ~X86_FSW_TOP_MASK;
5485	if ( (fFsw & (X86_FSW_IE \| X86_FSW_ZE \| X86_FSW_DE))
5486	& ~(pCtx->fpu.FCW & (X86_FCW_IM \| X86_FCW_ZM \| X86_FCW_DM)))
5487	{
5488	pCtx->fpu.FSW = fFsw;
5489	return;
5490	}
5491
5492	uint16_t iNewTop = (X86_FSW_TOP_GET(fFsw) + 7) & X86_FSW_TOP_SMASK;
5493	if (!(pCtx->fpu.FTW & RT_BIT(iNewTop)))
5494	{
5495	/* All is fine, push the actual value. */
5496	pCtx->fpu.FTW \|= RT_BIT(iNewTop);
5497	pCtx->fpu.aRegs[0].r80 = pResult->r80Result1;
5498	pCtx->fpu.aRegs[7].r80 = pResult->r80Result2;
5499	}
5500	else if (pCtx->fpu.FCW & X86_FCW_IM)
5501	{
5502	/* Masked stack overflow, push QNaN. */
5503	fFsw \|= X86_FSW_IE \| X86_FSW_SF \| X86_FSW_C1;
5504	iemFpuStoreQNan(&pCtx->fpu.aRegs[0].r80);
5505	iemFpuStoreQNan(&pCtx->fpu.aRegs[7].r80);
5506	}
5507	else
5508	{
5509	/* Raise stack overflow, don't push anything. */
5510	pCtx->fpu.FSW \|= pResult->FSW & ~X86_FSW_C_MASK;
5511	pCtx->fpu.FSW \|= X86_FSW_IE \| X86_FSW_SF \| X86_FSW_C1 \| X86_FSW_B \| X86_FSW_ES;
5512	return;
5513	}
5514
5515	fFsw &= ~X86_FSW_TOP_MASK;
5516	fFsw \|= iNewTop << X86_FSW_TOP_SHIFT;
5517	pCtx->fpu.FSW = fFsw;
5518
5519	iemFpuRotateStackPush(pCtx);
5520	}
5521
5522
5523	/**
5524	* Stores a result in a FPU register, updates the FSW, FTW, FPUIP, FPUCS, and
5525	* FOP.
5526	*
5527	* @param pIemCpu The IEM per CPU data.
5528	* @param pResult The result to store.
5529	* @param iStReg Which FPU register to store it in.
5530	* @param pCtx The CPU context.
5531	*/
5532	static void iemFpuStoreResult(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iStReg)
5533	{
5534	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5535	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5536	iemFpuStoreResultOnly(pIemCpu, pResult, iStReg, pCtx);
5537	}
5538
5539
5540	/**
5541	* Stores a result in a FPU register, updates the FSW, FTW, FPUIP, FPUCS, and
5542	* FOP, and then pops the stack.
5543	*
5544	* @param pIemCpu The IEM per CPU data.
5545	* @param pResult The result to store.
5546	* @param iStReg Which FPU register to store it in.
5547	* @param pCtx The CPU context.
5548	*/
5549	static void iemFpuStoreResultThenPop(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iStReg)
5550	{
5551	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5552	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5553	iemFpuStoreResultOnly(pIemCpu, pResult, iStReg, pCtx);
5554	iemFpuMaybePopOne(pCtx);
5555	}
5556
5557
5558	/**
5559	* Stores a result in a FPU register, updates the FSW, FTW, FPUIP, FPUCS, FOP,
5560	* FPUDP, and FPUDS.
5561	*
5562	* @param pIemCpu The IEM per CPU data.
5563	* @param pResult The result to store.
5564	* @param iStReg Which FPU register to store it in.
5565	* @param pCtx The CPU context.
5566	* @param iEffSeg The effective memory operand selector register.
5567	* @param GCPtrEff The effective memory operand offset.
5568	*/
5569	static void iemFpuStoreResultWithMemOp(PIEMCPU pIemCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff)
5570	{
5571	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5572	iemFpuUpdateDP(pIemCpu, pIemCpu->CTX_SUFF(pCtx), iEffSeg, GCPtrEff);
5573	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5574	iemFpuStoreResultOnly(pIemCpu, pResult, iStReg, pCtx);
5575	}
5576
5577
5578	/**
5579	* Stores a result in a FPU register, updates the FSW, FTW, FPUIP, FPUCS, FOP,
5580	* FPUDP, and FPUDS, and then pops the stack.
5581	*
5582	* @param pIemCpu The IEM per CPU data.
5583	* @param pResult The result to store.
5584	* @param iStReg Which FPU register to store it in.
5585	* @param pCtx The CPU context.
5586	* @param iEffSeg The effective memory operand selector register.
5587	* @param GCPtrEff The effective memory operand offset.
5588	*/
5589	static void iemFpuStoreResultWithMemOpThenPop(PIEMCPU pIemCpu, PIEMFPURESULT pResult,
5590	uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff)
5591	{
5592	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5593	iemFpuUpdateDP(pIemCpu, pCtx, iEffSeg, GCPtrEff);
5594	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5595	iemFpuStoreResultOnly(pIemCpu, pResult, iStReg, pCtx);
5596	iemFpuMaybePopOne(pCtx);
5597	}
5598
5599
5600	/**
5601	* Updates the FOP, FPUIP, and FPUCS. For FNOP.
5602	*
5603	* @param pIemCpu The IEM per CPU data.
5604	*/
5605	static void iemFpuUpdateOpcodeAndIp(PIEMCPU pIemCpu)
5606	{
5607	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pIemCpu->CTX_SUFF(pCtx));
5608	}
5609
5610
5611	/**
5612	* Marks the specified stack register as free (for FFREE).
5613	*
5614	* @param pIemCpu The IEM per CPU data.
5615	* @param iStReg The register to free.
5616	*/
5617	static void iemFpuStackFree(PIEMCPU pIemCpu, uint8_t iStReg)
5618	{
5619	Assert(iStReg < 8);
5620	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5621	uint8_t iReg = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + iStReg) & X86_FSW_TOP_SMASK;
5622	pCtx->fpu.FTW &= ~RT_BIT(iReg);
5623	}
5624
5625
5626	/**
5627	* Increments FSW.TOP, i.e. pops an item off the stack without freeing it.
5628	*
5629	* @param pIemCpu The IEM per CPU data.
5630	*/
5631	static void iemFpuStackIncTop(PIEMCPU pIemCpu)
5632	{
5633	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5634	uint16_t uFsw = pCtx->fpu.FSW;
5635	uint16_t uTop = uFsw & X86_FSW_TOP_MASK;
5636	uTop = (uTop + (1 << X86_FSW_TOP_SHIFT)) & X86_FSW_TOP_MASK;
5637	uFsw &= ~X86_FSW_TOP_MASK;
5638	uFsw \|= uTop;
5639	pCtx->fpu.FSW = uFsw;
5640	}
5641
5642
5643	/**
5644	* Decrements FSW.TOP, i.e. push an item off the stack without storing anything.
5645	*
5646	* @param pIemCpu The IEM per CPU data.
5647	*/
5648	static void iemFpuStackDecTop(PIEMCPU pIemCpu)
5649	{
5650	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5651	uint16_t uFsw = pCtx->fpu.FSW;
5652	uint16_t uTop = uFsw & X86_FSW_TOP_MASK;
5653	uTop = (uTop + (7 << X86_FSW_TOP_SHIFT)) & X86_FSW_TOP_MASK;
5654	uFsw &= ~X86_FSW_TOP_MASK;
5655	uFsw \|= uTop;
5656	pCtx->fpu.FSW = uFsw;
5657	}
5658
5659
5660	/**
5661	* Updates the FSW, FOP, FPUIP, and FPUCS.
5662	*
5663	* @param pIemCpu The IEM per CPU data.
5664	* @param u16FSW The FSW from the current instruction.
5665	*/
5666	static void iemFpuUpdateFSW(PIEMCPU pIemCpu, uint16_t u16FSW)
5667	{
5668	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5669	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5670	iemFpuUpdateFSWOnly(pCtx, u16FSW);
5671	}
5672
5673
5674	/**
5675	* Updates the FSW, FOP, FPUIP, and FPUCS, then pops the stack.
5676	*
5677	* @param pIemCpu The IEM per CPU data.
5678	* @param u16FSW The FSW from the current instruction.
5679	*/
5680	static void iemFpuUpdateFSWThenPop(PIEMCPU pIemCpu, uint16_t u16FSW)
5681	{
5682	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5683	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5684	iemFpuUpdateFSWOnly(pCtx, u16FSW);
5685	iemFpuMaybePopOne(pCtx);
5686	}
5687
5688
5689	/**
5690	* Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS.
5691	*
5692	* @param pIemCpu The IEM per CPU data.
5693	* @param u16FSW The FSW from the current instruction.
5694	* @param iEffSeg The effective memory operand selector register.
5695	* @param GCPtrEff The effective memory operand offset.
5696	*/
5697	static void iemFpuUpdateFSWWithMemOp(PIEMCPU pIemCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff)
5698	{
5699	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5700	iemFpuUpdateDP(pIemCpu, pCtx, iEffSeg, GCPtrEff);
5701	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5702	iemFpuUpdateFSWOnly(pCtx, u16FSW);
5703	}
5704
5705
5706	/**
5707	* Updates the FSW, FOP, FPUIP, and FPUCS, then pops the stack twice.
5708	*
5709	* @param pIemCpu The IEM per CPU data.
5710	* @param u16FSW The FSW from the current instruction.
5711	*/
5712	static void iemFpuUpdateFSWThenPopPop(PIEMCPU pIemCpu, uint16_t u16FSW)
5713	{
5714	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5715	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5716	iemFpuUpdateFSWOnly(pCtx, u16FSW);
5717	iemFpuMaybePopOne(pCtx);
5718	iemFpuMaybePopOne(pCtx);
5719	}
5720
5721
5722	/**
5723	* Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS, then pops the stack.
5724	*
5725	* @param pIemCpu The IEM per CPU data.
5726	* @param u16FSW The FSW from the current instruction.
5727	* @param iEffSeg The effective memory operand selector register.
5728	* @param GCPtrEff The effective memory operand offset.
5729	*/
5730	static void iemFpuUpdateFSWWithMemOpThenPop(PIEMCPU pIemCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff)
5731	{
5732	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5733	iemFpuUpdateDP(pIemCpu, pCtx, iEffSeg, GCPtrEff);
5734	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5735	iemFpuUpdateFSWOnly(pCtx, u16FSW);
5736	iemFpuMaybePopOne(pCtx);
5737	}
5738
5739
5740	/**
5741	* Worker routine for raising an FPU stack underflow exception.
5742	*
5743	* @param pIemCpu The IEM per CPU data.
5744	* @param iStReg The stack register being accessed.
5745	* @param pCtx The CPU context.
5746	*/
5747	static void iemFpuStackUnderflowOnly(PIEMCPU pIemCpu, uint8_t iStReg, PCPUMCTX pCtx)
5748	{
5749	Assert(iStReg < 8 \|\| iStReg == UINT8_MAX);
5750	if (pCtx->fpu.FCW & X86_FCW_IM)
5751	{
5752	/* Masked underflow. */
5753	pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
5754	pCtx->fpu.FSW \|= X86_FSW_IE \| X86_FSW_SF;
5755	uint16_t iReg = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + iStReg) & X86_FSW_TOP_SMASK;
5756	if (iStReg != UINT8_MAX)
5757	{
5758	pCtx->fpu.FTW \|= RT_BIT(iReg);
5759	iemFpuStoreQNan(&pCtx->fpu.aRegs[iStReg].r80);
5760	}
5761	}
5762	else
5763	{
5764	pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
5765	pCtx->fpu.FSW \|= X86_FSW_IE \| X86_FSW_SF \| X86_FSW_ES \| X86_FSW_B;
5766	}
5767	}
5768
5769
5770	/**
5771	* Raises a FPU stack underflow exception.
5772	*
5773	* @param pIemCpu The IEM per CPU data.
5774	* @param iStReg The destination register that should be loaded
5775	* with QNaN if \#IS is not masked. Specify
5776	* UINT8_MAX if none (like for fcom).
5777	*/
5778	DECL_NO_INLINE(static, void) iemFpuStackUnderflow(PIEMCPU pIemCpu, uint8_t iStReg)
5779	{
5780	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5781	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5782	iemFpuStackUnderflowOnly(pIemCpu, iStReg, pCtx);
5783	}
5784
5785
5786	DECL_NO_INLINE(static, void)
5787	iemFpuStackUnderflowWithMemOp(PIEMCPU pIemCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff)
5788	{
5789	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5790	iemFpuUpdateDP(pIemCpu, pCtx, iEffSeg, GCPtrEff);
5791	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5792	iemFpuStackUnderflowOnly(pIemCpu, iStReg, pCtx);
5793	}
5794
5795
5796	DECL_NO_INLINE(static, void) iemFpuStackUnderflowThenPop(PIEMCPU pIemCpu, uint8_t iStReg)
5797	{
5798	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5799	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5800	iemFpuStackUnderflowOnly(pIemCpu, iStReg, pCtx);
5801	iemFpuMaybePopOne(pCtx);
5802	}
5803
5804
5805	DECL_NO_INLINE(static, void)
5806	iemFpuStackUnderflowWithMemOpThenPop(PIEMCPU pIemCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff)
5807	{
5808	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5809	iemFpuUpdateDP(pIemCpu, pCtx, iEffSeg, GCPtrEff);
5810	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5811	iemFpuStackUnderflowOnly(pIemCpu, iStReg, pCtx);
5812	iemFpuMaybePopOne(pCtx);
5813	}
5814
5815
5816	DECL_NO_INLINE(static, void) iemFpuStackUnderflowThenPopPop(PIEMCPU pIemCpu)
5817	{
5818	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5819	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5820	iemFpuStackUnderflowOnly(pIemCpu, UINT8_MAX, pCtx);
5821	iemFpuMaybePopOne(pCtx);
5822	iemFpuMaybePopOne(pCtx);
5823	}
5824
5825
5826	DECL_NO_INLINE(static, void)
5827	iemFpuStackPushUnderflow(PIEMCPU pIemCpu)
5828	{
5829	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5830	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5831
5832	if (pCtx->fpu.FCW & X86_FCW_IM)
5833	{
5834	/* Masked overflow - Push QNaN. */
5835	uint16_t iNewTop = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + 7) & X86_FSW_TOP_SMASK;
5836	pCtx->fpu.FSW &= ~(X86_FSW_TOP_MASK \| X86_FSW_C_MASK);
5837	pCtx->fpu.FSW \|= X86_FSW_IE \| X86_FSW_SF;
5838	pCtx->fpu.FSW \|= iNewTop << X86_FSW_TOP_SHIFT;
5839	pCtx->fpu.FTW \|= RT_BIT(iNewTop);
5840	iemFpuStoreQNan(&pCtx->fpu.aRegs[7].r80);
5841	iemFpuRotateStackPush(pCtx);
5842	}
5843	else
5844	{
5845	/* Exception pending - don't change TOP or the register stack. */
5846	pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
5847	pCtx->fpu.FSW \|= X86_FSW_IE \| X86_FSW_SF \| X86_FSW_ES \| X86_FSW_B;
5848	}
5849	}
5850
5851
5852	DECL_NO_INLINE(static, void)
5853	iemFpuStackPushUnderflowTwo(PIEMCPU pIemCpu)
5854	{
5855	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5856	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5857
5858	if (pCtx->fpu.FCW & X86_FCW_IM)
5859	{
5860	/* Masked overflow - Push QNaN. */
5861	uint16_t iNewTop = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + 7) & X86_FSW_TOP_SMASK;
5862	pCtx->fpu.FSW &= ~(X86_FSW_TOP_MASK \| X86_FSW_C_MASK);
5863	pCtx->fpu.FSW \|= X86_FSW_IE \| X86_FSW_SF;
5864	pCtx->fpu.FSW \|= iNewTop << X86_FSW_TOP_SHIFT;
5865	pCtx->fpu.FTW \|= RT_BIT(iNewTop);
5866	iemFpuStoreQNan(&pCtx->fpu.aRegs[0].r80);
5867	iemFpuStoreQNan(&pCtx->fpu.aRegs[7].r80);
5868	iemFpuRotateStackPush(pCtx);
5869	}
5870	else
5871	{
5872	/* Exception pending - don't change TOP or the register stack. */
5873	pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
5874	pCtx->fpu.FSW \|= X86_FSW_IE \| X86_FSW_SF \| X86_FSW_ES \| X86_FSW_B;
5875	}
5876	}
5877
5878
5879	/**
5880	* Worker routine for raising an FPU stack overflow exception on a push.
5881	*
5882	* @param pIemCpu The IEM per CPU data.
5883	* @param pCtx The CPU context.
5884	*/
5885	static void iemFpuStackPushOverflowOnly(PIEMCPU pIemCpu, PCPUMCTX pCtx)
5886	{
5887	if (pCtx->fpu.FCW & X86_FCW_IM)
5888	{
5889	/* Masked overflow. */
5890	uint16_t iNewTop = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + 7) & X86_FSW_TOP_SMASK;
5891	pCtx->fpu.FSW &= ~(X86_FSW_TOP_MASK \| X86_FSW_C_MASK);
5892	pCtx->fpu.FSW \|= X86_FSW_C1 \| X86_FSW_IE \| X86_FSW_SF;
5893	pCtx->fpu.FSW \|= iNewTop << X86_FSW_TOP_SHIFT;
5894	pCtx->fpu.FTW \|= RT_BIT(iNewTop);
5895	iemFpuStoreQNan(&pCtx->fpu.aRegs[7].r80);
5896	iemFpuRotateStackPush(pCtx);
5897	}
5898	else
5899	{
5900	/* Exception pending - don't change TOP or the register stack. */
5901	pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
5902	pCtx->fpu.FSW \|= X86_FSW_C1 \| X86_FSW_IE \| X86_FSW_SF \| X86_FSW_ES \| X86_FSW_B;
5903	}
5904	}
5905
5906
5907	/**
5908	* Raises a FPU stack overflow exception on a push.
5909	*
5910	* @param pIemCpu The IEM per CPU data.
5911	*/
5912	DECL_NO_INLINE(static, void) iemFpuStackPushOverflow(PIEMCPU pIemCpu)
5913	{
5914	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5915	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5916	iemFpuStackPushOverflowOnly(pIemCpu, pCtx);
5917	}
5918
5919
5920	/**
5921	* Raises a FPU stack overflow exception on a push with a memory operand.
5922	*
5923	* @param pIemCpu The IEM per CPU data.
5924	* @param iEffSeg The effective memory operand selector register.
5925	* @param GCPtrEff The effective memory operand offset.
5926	*/
5927	DECL_NO_INLINE(static, void)
5928	iemFpuStackPushOverflowWithMemOp(PIEMCPU pIemCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff)
5929	{
5930	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5931	iemFpuUpdateDP(pIemCpu, pCtx, iEffSeg, GCPtrEff);
5932	iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
5933	iemFpuStackPushOverflowOnly(pIemCpu, pCtx);
5934	}
5935
5936
5937	static int iemFpuStRegNotEmpty(PIEMCPU pIemCpu, uint8_t iStReg)
5938	{
5939	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5940	uint16_t iReg = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + iStReg) & X86_FSW_TOP_SMASK;
5941	if (pCtx->fpu.FTW & RT_BIT(iReg))
5942	return VINF_SUCCESS;
5943	return VERR_NOT_FOUND;
5944	}
5945
5946
5947	static int iemFpuStRegNotEmptyRef(PIEMCPU pIemCpu, uint8_t iStReg, PCRTFLOAT80U *ppRef)
5948	{
5949	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5950	uint16_t iReg = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + iStReg) & X86_FSW_TOP_SMASK;
5951	if (pCtx->fpu.FTW & RT_BIT(iReg))
5952	{
5953	*ppRef = &pCtx->fpu.aRegs[iStReg].r80;
5954	return VINF_SUCCESS;
5955	}
5956	return VERR_NOT_FOUND;
5957	}
5958
5959
5960	static int iemFpu2StRegsNotEmptyRef(PIEMCPU pIemCpu, uint8_t iStReg0, PCRTFLOAT80U *ppRef0,
5961	uint8_t iStReg1, PCRTFLOAT80U *ppRef1)
5962	{
5963	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5964	uint16_t iTop = X86_FSW_TOP_GET(pCtx->fpu.FSW);
5965	uint16_t iReg0 = (iTop + iStReg0) & X86_FSW_TOP_SMASK;
5966	uint16_t iReg1 = (iTop + iStReg1) & X86_FSW_TOP_SMASK;
5967	if ((pCtx->fpu.FTW & (RT_BIT(iReg0) \| RT_BIT(iReg1))) == (RT_BIT(iReg0) \| RT_BIT(iReg1)))
5968	{
5969	*ppRef0 = &pCtx->fpu.aRegs[iStReg0].r80;
5970	*ppRef1 = &pCtx->fpu.aRegs[iStReg1].r80;
5971	return VINF_SUCCESS;
5972	}
5973	return VERR_NOT_FOUND;
5974	}
5975
5976
5977	static int iemFpu2StRegsNotEmptyRefFirst(PIEMCPU pIemCpu, uint8_t iStReg0, PCRTFLOAT80U *ppRef0, uint8_t iStReg1)
5978	{
5979	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5980	uint16_t iTop = X86_FSW_TOP_GET(pCtx->fpu.FSW);
5981	uint16_t iReg0 = (iTop + iStReg0) & X86_FSW_TOP_SMASK;
5982	uint16_t iReg1 = (iTop + iStReg1) & X86_FSW_TOP_SMASK;
5983	if ((pCtx->fpu.FTW & (RT_BIT(iReg0) \| RT_BIT(iReg1))) == (RT_BIT(iReg0) \| RT_BIT(iReg1)))
5984	{
5985	*ppRef0 = &pCtx->fpu.aRegs[iStReg0].r80;
5986	return VINF_SUCCESS;
5987	}
5988	return VERR_NOT_FOUND;
5989	}
5990
5991
5992	/**
5993	* Updates the FPU exception status after FCW is changed.
5994	*
5995	* @param pCtx The CPU context.
5996	*/
5997	static void iemFpuRecalcExceptionStatus(PCPUMCTX pCtx)
5998	{
5999	uint16_t u16Fsw = pCtx->fpu.FSW;
6000	if ((u16Fsw & X86_FSW_XCPT_MASK) & ~(pCtx->fpu.FCW & X86_FCW_XCPT_MASK))
6001	u16Fsw \|= X86_FSW_ES \| X86_FSW_B;
6002	else
6003	u16Fsw &= ~(X86_FSW_ES \| X86_FSW_B);
6004	pCtx->fpu.FSW = u16Fsw;
6005	}
6006
6007
6008	/**
6009	* Calculates the full FTW (FPU tag word) for use in FNSTENV and FNSAVE.
6010	*
6011	* @returns The full FTW.
6012	* @param pCtx The CPU state.
6013	*/
6014	static uint16_t iemFpuCalcFullFtw(PCCPUMCTX pCtx)
6015	{
6016	uint8_t const u8Ftw = (uint8_t)pCtx->fpu.FTW;
6017	uint16_t u16Ftw = 0;
6018	unsigned const iTop = X86_FSW_TOP_GET(pCtx->fpu.FSW);
6019	for (unsigned iSt = 0; iSt < 8; iSt++)
6020	{
6021	unsigned const iReg = (iSt + iTop) & 7;
6022	if (!(u8Ftw & RT_BIT(iReg)))
6023	u16Ftw \|= 3 << (iReg * 2); /* empty */
6024	else
6025	{
6026	uint16_t uTag;
6027	PCRTFLOAT80U const pr80Reg = &pCtx->fpu.aRegs[iSt].r80;
6028	if (pr80Reg->s.uExponent == 0x7fff)
6029	uTag = 2; /* Exponent is all 1's => Special. */
6030	else if (pr80Reg->s.uExponent == 0x0000)
6031	{
6032	if (pr80Reg->s.u64Mantissa == 0x0000)
6033	uTag = 1; /* All bits are zero => Zero. */
6034	else
6035	uTag = 2; /* Must be special. */
6036	}
6037	else if (pr80Reg->s.u64Mantissa & RT_BIT_64(63)) /* The J bit. */
6038	uTag = 0; /* Valid. */
6039	else
6040	uTag = 2; /* Must be special. */
6041
6042	u16Ftw \|= uTag << (iReg * 2); /* empty */
6043	}
6044	}
6045
6046	return u16Ftw;
6047	}
6048
6049
6050	/**
6051	* Converts a full FTW to a compressed one (for use in FLDENV and FRSTOR).
6052	*
6053	* @returns The compressed FTW.
6054	* @param u16FullFtw The full FTW to convert.
6055	*/
6056	static uint16_t iemFpuCompressFtw(uint16_t u16FullFtw)
6057	{
6058	uint8_t u8Ftw = 0;
6059	for (unsigned i = 0; i < 8; i++)
6060	{
6061	if ((u16FullFtw & 3) != 3 /empty/)
6062	u8Ftw \|= RT_BIT(i);
6063	u16FullFtw >>= 2;
6064	}
6065
6066	return u8Ftw;
6067	}
6068
6069	/** @} */
6070
6071
6072	/** @name Memory access.
6073	*
6074	* @{
6075	*/
6076
6077
6078	/**
6079	* Updates the IEMCPU::cbWritten counter if applicable.
6080	*
6081	* @param pIemCpu The IEM per CPU data.
6082	* @param fAccess The access being accounted for.
6083	* @param cbMem The access size.
6084	*/
6085	DECL_FORCE_INLINE(void) iemMemUpdateWrittenCounter(PIEMCPU pIemCpu, uint32_t fAccess, size_t cbMem)
6086	{
6087	if ( (fAccess & (IEM_ACCESS_WHAT_MASK \| IEM_ACCESS_TYPE_WRITE)) == (IEM_ACCESS_WHAT_STACK \| IEM_ACCESS_TYPE_WRITE)
6088	\|\| (fAccess & (IEM_ACCESS_WHAT_MASK \| IEM_ACCESS_TYPE_WRITE)) == (IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_TYPE_WRITE) )
6089	pIemCpu->cbWritten += (uint32_t)cbMem;
6090	}
6091
6092
6093	/**
6094	* Checks if the given segment can be written to, raise the appropriate
6095	* exception if not.
6096	*
6097	* @returns VBox strict status code.
6098	*
6099	* @param pIemCpu The IEM per CPU data.
6100	* @param pHid Pointer to the hidden register.
6101	* @param iSegReg The register number.
6102	* @param pu64BaseAddr Where to return the base address to use for the
6103	* segment. (In 64-bit code it may differ from the
6104	* base in the hidden segment.)
6105	*/
6106	static VBOXSTRICTRC iemMemSegCheckWriteAccessEx(PIEMCPU pIemCpu, PCCPUMSELREGHID pHid, uint8_t iSegReg, uint64_t *pu64BaseAddr)
6107	{
6108	if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
6109	*pu64BaseAddr = iSegReg < X86_SREG_FS ? 0 : pHid->u64Base;
6110	else
6111	{
6112	if (!pHid->Attr.n.u1Present)
6113	return iemRaiseSelectorNotPresentBySegReg(pIemCpu, iSegReg);
6114
6115	if ( ( (pHid->Attr.n.u4Type & X86_SEL_TYPE_CODE)
6116	\|\| !(pHid->Attr.n.u4Type & X86_SEL_TYPE_WRITE) )
6117	&& pIemCpu->enmCpuMode != IEMMODE_64BIT )
6118	return iemRaiseSelectorInvalidAccess(pIemCpu, iSegReg, IEM_ACCESS_DATA_W);
6119	*pu64BaseAddr = pHid->u64Base;
6120	}
6121	return VINF_SUCCESS;
6122	}
6123
6124
6125	/**
6126	* Checks if the given segment can be read from, raise the appropriate
6127	* exception if not.
6128	*
6129	* @returns VBox strict status code.
6130	*
6131	* @param pIemCpu The IEM per CPU data.
6132	* @param pHid Pointer to the hidden register.
6133	* @param iSegReg The register number.
6134	* @param pu64BaseAddr Where to return the base address to use for the
6135	* segment. (In 64-bit code it may differ from the
6136	* base in the hidden segment.)
6137	*/
6138	static VBOXSTRICTRC iemMemSegCheckReadAccessEx(PIEMCPU pIemCpu, PCCPUMSELREGHID pHid, uint8_t iSegReg, uint64_t *pu64BaseAddr)
6139	{
6140	if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
6141	*pu64BaseAddr = iSegReg < X86_SREG_FS ? 0 : pHid->u64Base;
6142	else
6143	{
6144	if (!pHid->Attr.n.u1Present)
6145	return iemRaiseSelectorNotPresentBySegReg(pIemCpu, iSegReg);
6146
6147	if ((pHid->Attr.n.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
6148	return iemRaiseSelectorInvalidAccess(pIemCpu, iSegReg, IEM_ACCESS_DATA_R);
6149	*pu64BaseAddr = pHid->u64Base;
6150	}
6151	return VINF_SUCCESS;
6152	}
6153
6154
6155	/**
6156	* Applies the segment limit, base and attributes.
6157	*
6158	* This may raise a \#GP or \#SS.
6159	*
6160	* @returns VBox strict status code.
6161	*
6162	* @param pIemCpu The IEM per CPU data.
6163	* @param fAccess The kind of access which is being performed.
6164	* @param iSegReg The index of the segment register to apply.
6165	* This is UINT8_MAX if none (for IDT, GDT, LDT,
6166	* TSS, ++).
6167	* @param pGCPtrMem Pointer to the guest memory address to apply
6168	* segmentation to. Input and output parameter.
6169	*/
6170	static VBOXSTRICTRC iemMemApplySegment(PIEMCPU pIemCpu, uint32_t fAccess, uint8_t iSegReg,
6171	size_t cbMem, PRTGCPTR pGCPtrMem)
6172	{
6173	if (iSegReg == UINT8_MAX)
6174	return VINF_SUCCESS;
6175
6176	PCPUMSELREGHID pSel = iemSRegGetHid(pIemCpu, iSegReg);
6177	switch (pIemCpu->enmCpuMode)
6178	{
6179	case IEMMODE_16BIT:
6180	case IEMMODE_32BIT:
6181	{
6182	RTGCPTR32 GCPtrFirst32 = (RTGCPTR32)*pGCPtrMem;
6183	RTGCPTR32 GCPtrLast32 = GCPtrFirst32 + (uint32_t)cbMem - 1;
6184
6185	Assert(pSel->Attr.n.u1Present);
6186	Assert(pSel->Attr.n.u1DescType);
6187	if (!(pSel->Attr.n.u4Type & X86_SEL_TYPE_CODE))
6188	{
6189	if ( (fAccess & IEM_ACCESS_TYPE_WRITE)
6190	&& !(pSel->Attr.n.u4Type & X86_SEL_TYPE_WRITE) )
6191	return iemRaiseSelectorInvalidAccess(pIemCpu, iSegReg, fAccess);
6192
6193	if (!IEM_IS_REAL_OR_V86_MODE(pIemCpu))
6194	{
6195	/** @todo CPL check. */
6196	}
6197
6198	/*
6199	* There are two kinds of data selectors, normal and expand down.
6200	*/
6201	if (!(pSel->Attr.n.u4Type & X86_SEL_TYPE_DOWN))
6202	{
6203	if ( GCPtrFirst32 > pSel->u32Limit
6204	\|\| GCPtrLast32 > pSel->u32Limit) /* yes, in real mode too (since 80286). */
6205	return iemRaiseSelectorBounds(pIemCpu, iSegReg, fAccess);
6206	}
6207	else
6208	{
6209	/*
6210	* The upper boundary is defined by the B bit, not the G bit!
6211	*/
6212	if ( GCPtrFirst32 < pSel->u32Limit + UINT32_C(1)
6213	\|\| GCPtrLast32 > (pSel->Attr.n.u1DefBig ? UINT32_MAX : UINT32_C(0xffff)))
6214	return iemRaiseSelectorBounds(pIemCpu, iSegReg, fAccess);
6215	}
6216	*pGCPtrMem = GCPtrFirst32 += (uint32_t)pSel->u64Base;
6217	}
6218	else
6219	{
6220
6221	/*
6222	* Code selector and usually be used to read thru, writing is
6223	* only permitted in real and V8086 mode.
6224	*/
6225	if ( ( (fAccess & IEM_ACCESS_TYPE_WRITE)
6226	\|\| ( (fAccess & IEM_ACCESS_TYPE_READ)
6227	&& !(pSel->Attr.n.u4Type & X86_SEL_TYPE_READ)) )
6228	&& !IEM_IS_REAL_OR_V86_MODE(pIemCpu) )
6229	return iemRaiseSelectorInvalidAccess(pIemCpu, iSegReg, fAccess);
6230
6231	if ( GCPtrFirst32 > pSel->u32Limit
6232	\|\| GCPtrLast32 > pSel->u32Limit) /* yes, in real mode too (since 80286). */
6233	return iemRaiseSelectorBounds(pIemCpu, iSegReg, fAccess);
6234
6235	if (!IEM_IS_REAL_OR_V86_MODE(pIemCpu))
6236	{
6237	/** @todo CPL check. */
6238	}
6239
6240	*pGCPtrMem = GCPtrFirst32 += (uint32_t)pSel->u64Base;
6241	}
6242	return VINF_SUCCESS;
6243	}
6244
6245	case IEMMODE_64BIT:
6246	if (iSegReg == X86_SREG_GS \|\| iSegReg == X86_SREG_FS)
6247	*pGCPtrMem += pSel->u64Base;
6248	return VINF_SUCCESS;
6249
6250	default:
6251	AssertFailedReturn(VERR_INTERNAL_ERROR_5);
6252	}
6253	}
6254
6255
6256	/**
6257	* Translates a virtual address to a physical physical address and checks if we
6258	* can access the page as specified.
6259	*
6260	* @param pIemCpu The IEM per CPU data.
6261	* @param GCPtrMem The virtual address.
6262	* @param fAccess The intended access.
6263	* @param pGCPhysMem Where to return the physical address.
6264	*/
6265	static VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PIEMCPU pIemCpu, RTGCPTR GCPtrMem, uint32_t fAccess,
6266	PRTGCPHYS pGCPhysMem)
6267	{
6268	/** @todo Need a different PGM interface here. We're currently using
6269	* generic / REM interfaces. this won't cut it for R0 & RC. */
6270	RTGCPHYS GCPhys;
6271	uint64_t fFlags;
6272	int rc = PGMGstGetPage(IEMCPU_TO_VMCPU(pIemCpu), GCPtrMem, &fFlags, &GCPhys);
6273	if (RT_FAILURE(rc))
6274	{
6275	/** @todo Check unassigned memory in unpaged mode. */
6276	/** @todo Reserved bits in page tables. Requires new PGM interface. */
6277	*pGCPhysMem = NIL_RTGCPHYS;
6278	return iemRaisePageFault(pIemCpu, GCPtrMem, fAccess, rc);
6279	}
6280
6281	/* If the page is writable and does not have the no-exec bit set, all
6282	access is allowed. Otherwise we'll have to check more carefully... */
6283	if ((fFlags & (X86_PTE_RW \| X86_PTE_US \| X86_PTE_PAE_NX)) != (X86_PTE_RW \| X86_PTE_US))
6284	{
6285	/* Write to read only memory? */
6286	if ( (fAccess & IEM_ACCESS_TYPE_WRITE)
6287	&& !(fFlags & X86_PTE_RW)
6288	&& ( pIemCpu->uCpl != 0
6289	\|\| (pIemCpu->CTX_SUFF(pCtx)->cr0 & X86_CR0_WP)))
6290	{
6291	Log(("iemMemPageTranslateAndCheckAccess: GCPtrMem=%RGv - read-only page -> #PF\n", GCPtrMem));
6292	*pGCPhysMem = NIL_RTGCPHYS;
6293	return iemRaisePageFault(pIemCpu, GCPtrMem, fAccess & ~IEM_ACCESS_TYPE_READ, VERR_ACCESS_DENIED);
6294	}
6295
6296	/* Kernel memory accessed by userland? */
6297	if ( !(fFlags & X86_PTE_US)
6298	&& pIemCpu->uCpl == 3
6299	&& !(fAccess & IEM_ACCESS_WHAT_SYS))
6300	{
6301	Log(("iemMemPageTranslateAndCheckAccess: GCPtrMem=%RGv - user access to kernel page -> #PF\n", GCPtrMem));
6302	*pGCPhysMem = NIL_RTGCPHYS;
6303	return iemRaisePageFault(pIemCpu, GCPtrMem, fAccess, VERR_ACCESS_DENIED);
6304	}
6305
6306	/* Executing non-executable memory? */
6307	if ( (fAccess & IEM_ACCESS_TYPE_EXEC)
6308	&& (fFlags & X86_PTE_PAE_NX)
6309	&& (pIemCpu->CTX_SUFF(pCtx)->msrEFER & MSR_K6_EFER_NXE) )
6310	{
6311	Log(("iemMemPageTranslateAndCheckAccess: GCPtrMem=%RGv - NX -> #PF\n", GCPtrMem));
6312	*pGCPhysMem = NIL_RTGCPHYS;
6313	return iemRaisePageFault(pIemCpu, GCPtrMem, fAccess & ~(IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE),
6314	VERR_ACCESS_DENIED);
6315	}
6316	}
6317
6318	/*
6319	* Set the dirty / access flags.
6320	* ASSUMES this is set when the address is translated rather than on committ...
6321	*/
6322	/** @todo testcase: check when A and D bits are actually set by the CPU. */
6323	uint32_t fAccessedDirty = fAccess & IEM_ACCESS_TYPE_WRITE ? X86_PTE_D \| X86_PTE_A : X86_PTE_A;
6324	if ((fFlags & fAccessedDirty) != fAccessedDirty)
6325	{
6326	int rc2 = PGMGstModifyPage(IEMCPU_TO_VMCPU(pIemCpu), GCPtrMem, 1, fAccessedDirty, ~(uint64_t)fAccessedDirty);
6327	AssertRC(rc2);
6328	}
6329
6330	GCPhys \|= GCPtrMem & PAGE_OFFSET_MASK;
6331	*pGCPhysMem = GCPhys;
6332	return VINF_SUCCESS;
6333	}
6334
6335
6336
6337	/**
6338	* Maps a physical page.
6339	*
6340	* @returns VBox status code (see PGMR3PhysTlbGCPhys2Ptr).
6341	* @param pIemCpu The IEM per CPU data.
6342	* @param GCPhysMem The physical address.
6343	* @param fAccess The intended access.
6344	* @param ppvMem Where to return the mapping address.
6345	* @param pLock The PGM lock.
6346	*/
6347	static int iemMemPageMap(PIEMCPU pIemCpu, RTGCPHYS GCPhysMem, uint32_t fAccess, void **ppvMem, PPGMPAGEMAPLOCK pLock)
6348	{
6349	#ifdef IEM_VERIFICATION_MODE_FULL
6350	/* Force the alternative path so we can ignore writes. */
6351	if ((fAccess & IEM_ACCESS_TYPE_WRITE) && !pIemCpu->fNoRem)
6352	{
6353	if (IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
6354	{
6355	int rc2 = PGMPhysIemQueryAccess(IEMCPU_TO_VM(pIemCpu), GCPhysMem,
6356	RT_BOOL(fAccess & IEM_ACCESS_TYPE_WRITE), pIemCpu->fBypassHandlers);
6357	if (RT_FAILURE(rc2))
6358	pIemCpu->fProblematicMemory = true;
6359	}
6360	return VERR_PGM_PHYS_TLB_CATCH_ALL;
6361	}
6362	#endif
6363	#ifdef IEM_LOG_MEMORY_WRITES
6364	if (fAccess & IEM_ACCESS_TYPE_WRITE)
6365	return VERR_PGM_PHYS_TLB_CATCH_ALL;
6366	#endif
6367	#ifdef IEM_VERIFICATION_MODE_MINIMAL
6368	return VERR_PGM_PHYS_TLB_CATCH_ALL;
6369	#endif
6370
6371	/** @todo This API may require some improving later. A private deal with PGM
6372	* regarding locking and unlocking needs to be struct. A couple of TLBs
6373	* living in PGM, but with publicly accessible inlined access methods
6374	* could perhaps be an even better solution. */
6375	int rc = PGMPhysIemGCPhys2Ptr(IEMCPU_TO_VM(pIemCpu), IEMCPU_TO_VMCPU(pIemCpu),
6376	GCPhysMem,
6377	RT_BOOL(fAccess & IEM_ACCESS_TYPE_WRITE),
6378	pIemCpu->fBypassHandlers,
6379	ppvMem,
6380	pLock);
6381	/Log(("PGMPhysIemGCPhys2Ptr %Rrc pLock=%.Rhxs\n", rc, sizeof(pLock), pLock));/
6382	AssertMsg(rc == VINF_SUCCESS \|\| RT_FAILURE_NP(rc), ("%Rrc\n", rc));
6383
6384	#ifdef IEM_VERIFICATION_MODE_FULL
6385	if (RT_FAILURE(rc) && IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
6386	pIemCpu->fProblematicMemory = true;
6387	#endif
6388	return rc;
6389	}
6390
6391
6392	/**
6393	* Unmap a page previously mapped by iemMemPageMap.
6394	*
6395	* @param pIemCpu The IEM per CPU data.
6396	* @param GCPhysMem The physical address.
6397	* @param fAccess The intended access.
6398	* @param pvMem What iemMemPageMap returned.
6399	* @param pLock The PGM lock.
6400	*/
6401	DECLINLINE(void) iemMemPageUnmap(PIEMCPU pIemCpu, RTGCPHYS GCPhysMem, uint32_t fAccess, const void *pvMem, PPGMPAGEMAPLOCK pLock)
6402	{
6403	NOREF(pIemCpu);
6404	NOREF(GCPhysMem);
6405	NOREF(fAccess);
6406	NOREF(pvMem);
6407	PGMPhysReleasePageMappingLock(IEMCPU_TO_VM(pIemCpu), pLock);
6408	}
6409
6410
6411	/**
6412	* Looks up a memory mapping entry.
6413	*
6414	* @returns The mapping index (positive) or VERR_NOT_FOUND (negative).
6415	* @param pIemCpu The IEM per CPU data.
6416	* @param pvMem The memory address.
6417	* @param fAccess The access to.
6418	*/
6419	DECLINLINE(int) iemMapLookup(PIEMCPU pIemCpu, void *pvMem, uint32_t fAccess)
6420	{
6421	fAccess &= IEM_ACCESS_WHAT_MASK \| IEM_ACCESS_TYPE_MASK;
6422	if ( pIemCpu->aMemMappings[0].pv == pvMem
6423	&& (pIemCpu->aMemMappings[0].fAccess & (IEM_ACCESS_WHAT_MASK \| IEM_ACCESS_TYPE_MASK)) == fAccess)
6424	return 0;
6425	if ( pIemCpu->aMemMappings[1].pv == pvMem
6426	&& (pIemCpu->aMemMappings[1].fAccess & (IEM_ACCESS_WHAT_MASK \| IEM_ACCESS_TYPE_MASK)) == fAccess)
6427	return 1;
6428	if ( pIemCpu->aMemMappings[2].pv == pvMem
6429	&& (pIemCpu->aMemMappings[2].fAccess & (IEM_ACCESS_WHAT_MASK \| IEM_ACCESS_TYPE_MASK)) == fAccess)
6430	return 2;
6431	return VERR_NOT_FOUND;
6432	}
6433
6434
6435	/**
6436	* Finds a free memmap entry when using iNextMapping doesn't work.
6437	*
6438	* @returns Memory mapping index, 1024 on failure.
6439	* @param pIemCpu The IEM per CPU data.
6440	*/
6441	static unsigned iemMemMapFindFree(PIEMCPU pIemCpu)
6442	{
6443	/*
6444	* The easy case.
6445	*/
6446	if (pIemCpu->cActiveMappings == 0)
6447	{
6448	pIemCpu->iNextMapping = 1;
6449	return 0;
6450	}
6451
6452	/* There should be enough mappings for all instructions. */
6453	AssertReturn(pIemCpu->cActiveMappings < RT_ELEMENTS(pIemCpu->aMemMappings), 1024);
6454
6455	for (unsigned i = 0; i < RT_ELEMENTS(pIemCpu->aMemMappings); i++)
6456	if (pIemCpu->aMemMappings[i].fAccess == IEM_ACCESS_INVALID)
6457	return i;
6458
6459	AssertFailedReturn(1024);
6460	}
6461
6462
6463	/**
6464	* Commits a bounce buffer that needs writing back and unmaps it.
6465	*
6466	* @returns Strict VBox status code.
6467	* @param pIemCpu The IEM per CPU data.
6468	* @param iMemMap The index of the buffer to commit.
6469	*/
6470	static VBOXSTRICTRC iemMemBounceBufferCommitAndUnmap(PIEMCPU pIemCpu, unsigned iMemMap)
6471	{
6472	Assert(pIemCpu->aMemMappings[iMemMap].fAccess & IEM_ACCESS_BOUNCE_BUFFERED);
6473	Assert(pIemCpu->aMemMappings[iMemMap].fAccess & IEM_ACCESS_TYPE_WRITE);
6474
6475	/*
6476	* Do the writing.
6477	*/
6478	int rc;
6479	#ifndef IEM_VERIFICATION_MODE_MINIMAL
6480	if ( !pIemCpu->aMemBbMappings[iMemMap].fUnassigned
6481	&& !IEM_VERIFICATION_ENABLED(pIemCpu))
6482	{
6483	uint16_t const cbFirst = pIemCpu->aMemBbMappings[iMemMap].cbFirst;
6484	uint16_t const cbSecond = pIemCpu->aMemBbMappings[iMemMap].cbSecond;
6485	uint8_t const *pbBuf = &pIemCpu->aBounceBuffers[iMemMap].ab[0];
6486	if (!pIemCpu->fBypassHandlers)
6487	{
6488	rc = PGMPhysWrite(IEMCPU_TO_VM(pIemCpu),
6489	pIemCpu->aMemBbMappings[iMemMap].GCPhysFirst,
6490	pbBuf,
6491	cbFirst);
6492	if (cbSecond && rc == VINF_SUCCESS)
6493	rc = PGMPhysWrite(IEMCPU_TO_VM(pIemCpu),
6494	pIemCpu->aMemBbMappings[iMemMap].GCPhysSecond,
6495	pbBuf + cbFirst,
6496	cbSecond);
6497	}
6498	else
6499	{
6500	rc = PGMPhysSimpleWriteGCPhys(IEMCPU_TO_VM(pIemCpu),
6501	pIemCpu->aMemBbMappings[iMemMap].GCPhysFirst,
6502	pbBuf,
6503	cbFirst);
6504	if (cbSecond && rc == VINF_SUCCESS)
6505	rc = PGMPhysSimpleWriteGCPhys(IEMCPU_TO_VM(pIemCpu),
6506	pIemCpu->aMemBbMappings[iMemMap].GCPhysSecond,
6507	pbBuf + cbFirst,
6508	cbSecond);
6509	}
6510	if (rc != VINF_SUCCESS)
6511	{
6512	/** @todo status code handling */
6513	Log(("iemMemBounceBufferCommitAndUnmap: %s GCPhysFirst=%RGp/%#x GCPhysSecond=%RGp/%#x %Rrc (!!)\n",
6514	pIemCpu->fBypassHandlers ? "PGMPhysWrite" : "PGMPhysSimpleWriteGCPhys",
6515	pIemCpu->aMemBbMappings[iMemMap].GCPhysFirst, cbFirst,
6516	pIemCpu->aMemBbMappings[iMemMap].GCPhysSecond, cbSecond, rc));
6517	}
6518	}
6519	else
6520	#endif
6521	rc = VINF_SUCCESS;
6522
6523	#if defined(IEM_VERIFICATION_MODE_FULL) && defined(IN_RING3)
6524	/*
6525	* Record the write(s).
6526	*/
6527	if (!pIemCpu->fNoRem)
6528	{
6529	PIEMVERIFYEVTREC pEvtRec = iemVerifyAllocRecord(pIemCpu);
6530	if (pEvtRec)
6531	{
6532	pEvtRec->enmEvent = IEMVERIFYEVENT_RAM_WRITE;
6533	pEvtRec->u.RamWrite.GCPhys = pIemCpu->aMemBbMappings[iMemMap].GCPhysFirst;
6534	pEvtRec->u.RamWrite.cb = pIemCpu->aMemBbMappings[iMemMap].cbFirst;
6535	memcpy(pEvtRec->u.RamWrite.ab, &pIemCpu->aBounceBuffers[iMemMap].ab[0], pIemCpu->aMemBbMappings[iMemMap].cbFirst);
6536	AssertCompile(sizeof(pEvtRec->u.RamWrite.ab) == sizeof(pIemCpu->aBounceBuffers[0].ab));
6537	pEvtRec->pNext = *pIemCpu->ppIemEvtRecNext;
6538	*pIemCpu->ppIemEvtRecNext = pEvtRec;
6539	}
6540	if (pIemCpu->aMemBbMappings[iMemMap].cbSecond)
6541	{
6542	pEvtRec = iemVerifyAllocRecord(pIemCpu);
6543	if (pEvtRec)
6544	{
6545	pEvtRec->enmEvent = IEMVERIFYEVENT_RAM_WRITE;
6546	pEvtRec->u.RamWrite.GCPhys = pIemCpu->aMemBbMappings[iMemMap].GCPhysSecond;
6547	pEvtRec->u.RamWrite.cb = pIemCpu->aMemBbMappings[iMemMap].cbSecond;
6548	memcpy(pEvtRec->u.RamWrite.ab,
6549	&pIemCpu->aBounceBuffers[iMemMap].ab[pIemCpu->aMemBbMappings[iMemMap].cbFirst],
6550	pIemCpu->aMemBbMappings[iMemMap].cbSecond);
6551	pEvtRec->pNext = *pIemCpu->ppIemEvtRecNext;
6552	*pIemCpu->ppIemEvtRecNext = pEvtRec;
6553	}
6554	}
6555	}
6556	#endif
6557	#if defined(IEM_VERIFICATION_MODE_MINIMAL) \|\| defined(IEM_LOG_MEMORY_WRITES)
6558	if (rc == VINF_SUCCESS)
6559	{
6560	Log(("IEM Wrote %RGp: %.*Rhxs\n", pIemCpu->aMemBbMappings[iMemMap].GCPhysFirst,
6561	RT_MAX(RT_MIN(pIemCpu->aMemBbMappings[iMemMap].cbFirst, 64), 1), &pIemCpu->aBounceBuffers[iMemMap].ab[0]));
6562	if (pIemCpu->aMemBbMappings[iMemMap].cbSecond)
6563	Log(("IEM Wrote %RGp: %.*Rhxs [2nd page]\n", pIemCpu->aMemBbMappings[iMemMap].GCPhysSecond,
6564	RT_MIN(pIemCpu->aMemBbMappings[iMemMap].cbSecond, 64),
6565	&pIemCpu->aBounceBuffers[iMemMap].ab[pIemCpu->aMemBbMappings[iMemMap].cbFirst]));
6566
6567	size_t cbWrote = pIemCpu->aMemBbMappings[iMemMap].cbFirst + pIemCpu->aMemBbMappings[iMemMap].cbSecond;
6568	g_cbIemWrote = cbWrote;
6569	memcpy(g_abIemWrote, &pIemCpu->aBounceBuffers[iMemMap].ab[0], RT_MIN(cbWrote, sizeof(g_abIemWrote)));
6570	}
6571	#endif
6572
6573	/*
6574	* Free the mapping entry.
6575	*/
6576	pIemCpu->aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
6577	Assert(pIemCpu->cActiveMappings != 0);
6578	pIemCpu->cActiveMappings--;
6579	return rc;
6580	}
6581
6582
6583	/**
6584	* iemMemMap worker that deals with a request crossing pages.
6585	*/
6586	static VBOXSTRICTRC iemMemBounceBufferMapCrossPage(PIEMCPU pIemCpu, int iMemMap, void **ppvMem,
6587	size_t cbMem, RTGCPTR GCPtrFirst, uint32_t fAccess)
6588	{
6589	/*
6590	* Do the address translations.
6591	*/
6592	RTGCPHYS GCPhysFirst;
6593	VBOXSTRICTRC rcStrict = iemMemPageTranslateAndCheckAccess(pIemCpu, GCPtrFirst, fAccess, &GCPhysFirst);
6594	if (rcStrict != VINF_SUCCESS)
6595	return rcStrict;
6596
6597	/** @todo Testcase & AMD-V/VT-x verification: Check if CR2 should really be the
6598	* last byte. */
6599	RTGCPHYS GCPhysSecond;
6600	rcStrict = iemMemPageTranslateAndCheckAccess(pIemCpu, GCPtrFirst + (cbMem - 1), fAccess, &GCPhysSecond);
6601	if (rcStrict != VINF_SUCCESS)
6602	return rcStrict;
6603	GCPhysSecond &= ~(RTGCPHYS)PAGE_OFFSET_MASK;
6604
6605	#ifdef IEM_VERIFICATION_MODE_FULL
6606	/*
6607	* Detect problematic memory when verifying so we can select
6608	* the right execution engine. (TLB: Redo this.)
6609	*/
6610	if (IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
6611	{
6612	int rc2 = PGMPhysIemQueryAccess(IEMCPU_TO_VM(pIemCpu), GCPhysFirst,
6613	RT_BOOL(fAccess & IEM_ACCESS_TYPE_WRITE), pIemCpu->fBypassHandlers);
6614	if (RT_SUCCESS(rc2))
6615	rc2 = PGMPhysIemQueryAccess(IEMCPU_TO_VM(pIemCpu), GCPhysSecond,
6616	RT_BOOL(fAccess & IEM_ACCESS_TYPE_WRITE), pIemCpu->fBypassHandlers);
6617	if (RT_FAILURE(rc2))
6618	pIemCpu->fProblematicMemory = true;
6619	}
6620	#endif
6621
6622
6623	/*
6624	* Read in the current memory content if it's a read, execute or partial
6625	* write access.
6626	*/
6627	uint8_t *pbBuf = &pIemCpu->aBounceBuffers[iMemMap].ab[0];
6628	uint32_t const cbFirstPage = PAGE_SIZE - (GCPhysFirst & PAGE_OFFSET_MASK);
6629	uint32_t const cbSecondPage = (uint32_t)(cbMem - cbFirstPage);
6630
6631	if (fAccess & (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_PARTIAL_WRITE))
6632	{
6633	int rc;
6634	if (!pIemCpu->fBypassHandlers)
6635	{
6636	rc = PGMPhysRead(IEMCPU_TO_VM(pIemCpu), GCPhysFirst, pbBuf, cbFirstPage);
6637	if (rc != VINF_SUCCESS)
6638	{
6639	/** @todo status code handling */
6640	Log(("iemMemBounceBufferMapPhys: PGMPhysRead GCPhysFirst=%RGp rc=%Rrc (!!)\n", GCPhysFirst, rc));
6641	return rc;
6642	}
6643	rc = PGMPhysRead(IEMCPU_TO_VM(pIemCpu), GCPhysSecond, pbBuf + cbFirstPage, cbSecondPage);
6644	if (rc != VINF_SUCCESS)
6645	{
6646	/** @todo status code handling */
6647	Log(("iemMemBounceBufferMapPhys: PGMPhysRead GCPhysSecond=%RGp rc=%Rrc (!!)\n", GCPhysSecond, rc));
6648	return rc;
6649	}
6650	}
6651	else
6652	{
6653	rc = PGMPhysSimpleReadGCPhys(IEMCPU_TO_VM(pIemCpu), pbBuf, GCPhysFirst, cbFirstPage);
6654	if (rc != VINF_SUCCESS)
6655	{
6656	/** @todo status code handling */
6657	Log(("iemMemBounceBufferMapPhys: PGMPhysSimpleReadGCPhys GCPhysFirst=%RGp rc=%Rrc (!!)\n", GCPhysFirst, rc));
6658	return rc;
6659	}
6660	rc = PGMPhysSimpleReadGCPhys(IEMCPU_TO_VM(pIemCpu), pbBuf + cbFirstPage, GCPhysSecond, cbSecondPage);
6661	if (rc != VINF_SUCCESS)
6662	{
6663	/** @todo status code handling */
6664	Log(("iemMemBounceBufferMapPhys: PGMPhysSimpleReadGCPhys GCPhysSecond=%RGp rc=%Rrc (!!)\n", GCPhysSecond, rc));
6665	return rc;
6666	}
6667	}
6668
6669	#if defined(IEM_VERIFICATION_MODE_FULL) && defined(IN_RING3)
6670	if ( !pIemCpu->fNoRem
6671	&& (fAccess & (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_EXEC)) )
6672	{
6673	/*
6674	* Record the reads.
6675	*/
6676	PIEMVERIFYEVTREC pEvtRec = iemVerifyAllocRecord(pIemCpu);
6677	if (pEvtRec)
6678	{
6679	pEvtRec->enmEvent = IEMVERIFYEVENT_RAM_READ;
6680	pEvtRec->u.RamRead.GCPhys = GCPhysFirst;
6681	pEvtRec->u.RamRead.cb = cbFirstPage;
6682	pEvtRec->pNext = *pIemCpu->ppIemEvtRecNext;
6683	*pIemCpu->ppIemEvtRecNext = pEvtRec;
6684	}
6685	pEvtRec = iemVerifyAllocRecord(pIemCpu);
6686	if (pEvtRec)
6687	{
6688	pEvtRec->enmEvent = IEMVERIFYEVENT_RAM_READ;
6689	pEvtRec->u.RamRead.GCPhys = GCPhysSecond;
6690	pEvtRec->u.RamRead.cb = cbSecondPage;
6691	pEvtRec->pNext = *pIemCpu->ppIemEvtRecNext;
6692	*pIemCpu->ppIemEvtRecNext = pEvtRec;
6693	}
6694	}
6695	#endif
6696	}
6697	#ifdef VBOX_STRICT
6698	else
6699	memset(pbBuf, 0xcc, cbMem);
6700	#endif
6701	#ifdef VBOX_STRICT
6702	if (cbMem < sizeof(pIemCpu->aBounceBuffers[iMemMap].ab))
6703	memset(pbBuf + cbMem, 0xaa, sizeof(pIemCpu->aBounceBuffers[iMemMap].ab) - cbMem);
6704	#endif
6705
6706	/*
6707	* Commit the bounce buffer entry.
6708	*/
6709	pIemCpu->aMemBbMappings[iMemMap].GCPhysFirst = GCPhysFirst;
6710	pIemCpu->aMemBbMappings[iMemMap].GCPhysSecond = GCPhysSecond;
6711	pIemCpu->aMemBbMappings[iMemMap].cbFirst = (uint16_t)cbFirstPage;
6712	pIemCpu->aMemBbMappings[iMemMap].cbSecond = (uint16_t)cbSecondPage;
6713	pIemCpu->aMemBbMappings[iMemMap].fUnassigned = false;
6714	pIemCpu->aMemMappings[iMemMap].pv = pbBuf;
6715	pIemCpu->aMemMappings[iMemMap].fAccess = fAccess \| IEM_ACCESS_BOUNCE_BUFFERED;
6716	pIemCpu->iNextMapping = iMemMap + 1;
6717	pIemCpu->cActiveMappings++;
6718
6719	iemMemUpdateWrittenCounter(pIemCpu, fAccess, cbMem);
6720	*ppvMem = pbBuf;
6721	return VINF_SUCCESS;
6722	}
6723
6724
6725	/**
6726	* iemMemMap woker that deals with iemMemPageMap failures.
6727	*/
6728	static VBOXSTRICTRC iemMemBounceBufferMapPhys(PIEMCPU pIemCpu, unsigned iMemMap, void **ppvMem, size_t cbMem,
6729	RTGCPHYS GCPhysFirst, uint32_t fAccess, VBOXSTRICTRC rcMap)
6730	{
6731	/*
6732	* Filter out conditions we can handle and the ones which shouldn't happen.
6733	*/
6734	if ( rcMap != VERR_PGM_PHYS_TLB_CATCH_WRITE
6735	&& rcMap != VERR_PGM_PHYS_TLB_CATCH_ALL
6736	&& rcMap != VERR_PGM_PHYS_TLB_UNASSIGNED)
6737	{
6738	AssertReturn(RT_FAILURE_NP(rcMap), VERR_INTERNAL_ERROR_3);
6739	return rcMap;
6740	}
6741	pIemCpu->cPotentialExits++;
6742
6743	/*
6744	* Read in the current memory content if it's a read, execute or partial
6745	* write access.
6746	*/
6747	uint8_t *pbBuf = &pIemCpu->aBounceBuffers[iMemMap].ab[0];
6748	if (fAccess & (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_PARTIAL_WRITE))
6749	{
6750	if (rcMap == VERR_PGM_PHYS_TLB_UNASSIGNED)
6751	memset(pbBuf, 0xff, cbMem);
6752	else
6753	{
6754	int rc;
6755	if (!pIemCpu->fBypassHandlers)
6756	rc = PGMPhysRead(IEMCPU_TO_VM(pIemCpu), GCPhysFirst, pbBuf, cbMem);
6757	else
6758	rc = PGMPhysSimpleReadGCPhys(IEMCPU_TO_VM(pIemCpu), pbBuf, GCPhysFirst, cbMem);
6759	if (rc != VINF_SUCCESS)
6760	{
6761	/** @todo status code handling */
6762	Log(("iemMemBounceBufferMapPhys: %s GCPhysFirst=%RGp rc=%Rrc (!!)\n",
6763	pIemCpu->fBypassHandlers ? "PGMPhysRead" : "PGMPhysSimpleReadGCPhys", GCPhysFirst, rc));
6764	return rc;
6765	}
6766	}
6767
6768	#if defined(IEM_VERIFICATION_MODE_FULL) && defined(IN_RING3)
6769	if ( !pIemCpu->fNoRem
6770	&& (fAccess & (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_EXEC)) )
6771	{
6772	/*
6773	* Record the read.
6774	*/
6775	PIEMVERIFYEVTREC pEvtRec = iemVerifyAllocRecord(pIemCpu);
6776	if (pEvtRec)
6777	{
6778	pEvtRec->enmEvent = IEMVERIFYEVENT_RAM_READ;
6779	pEvtRec->u.RamRead.GCPhys = GCPhysFirst;
6780	pEvtRec->u.RamRead.cb = (uint32_t)cbMem;
6781	pEvtRec->pNext = *pIemCpu->ppIemEvtRecNext;
6782	*pIemCpu->ppIemEvtRecNext = pEvtRec;
6783	}
6784	}
6785	#endif
6786	}
6787	#ifdef VBOX_STRICT
6788	else
6789	memset(pbBuf, 0xcc, cbMem);
6790	#endif
6791	#ifdef VBOX_STRICT
6792	if (cbMem < sizeof(pIemCpu->aBounceBuffers[iMemMap].ab))
6793	memset(pbBuf + cbMem, 0xaa, sizeof(pIemCpu->aBounceBuffers[iMemMap].ab) - cbMem);
6794	#endif
6795
6796	/*
6797	* Commit the bounce buffer entry.
6798	*/
6799	pIemCpu->aMemBbMappings[iMemMap].GCPhysFirst = GCPhysFirst;
6800	pIemCpu->aMemBbMappings[iMemMap].GCPhysSecond = NIL_RTGCPHYS;
6801	pIemCpu->aMemBbMappings[iMemMap].cbFirst = (uint16_t)cbMem;
6802	pIemCpu->aMemBbMappings[iMemMap].cbSecond = 0;
6803	pIemCpu->aMemBbMappings[iMemMap].fUnassigned = rcMap == VERR_PGM_PHYS_TLB_UNASSIGNED;
6804	pIemCpu->aMemMappings[iMemMap].pv = pbBuf;
6805	pIemCpu->aMemMappings[iMemMap].fAccess = fAccess \| IEM_ACCESS_BOUNCE_BUFFERED;
6806	pIemCpu->iNextMapping = iMemMap + 1;
6807	pIemCpu->cActiveMappings++;
6808
6809	iemMemUpdateWrittenCounter(pIemCpu, fAccess, cbMem);
6810	*ppvMem = pbBuf;
6811	return VINF_SUCCESS;
6812	}
6813
6814
6815
6816	/**
6817	* Maps the specified guest memory for the given kind of access.
6818	*
6819	* This may be using bounce buffering of the memory if it's crossing a page
6820	* boundary or if there is an access handler installed for any of it. Because
6821	* of lock prefix guarantees, we're in for some extra clutter when this
6822	* happens.
6823	*
6824	* This may raise a \#GP, \#SS, \#PF or \#AC.
6825	*
6826	* @returns VBox strict status code.
6827	*
6828	* @param pIemCpu The IEM per CPU data.
6829	* @param ppvMem Where to return the pointer to the mapped
6830	* memory.
6831	* @param cbMem The number of bytes to map. This is usually 1,
6832	* 2, 4, 6, 8, 12, 16, 32 or 512. When used by
6833	* string operations it can be up to a page.
6834	* @param iSegReg The index of the segment register to use for
6835	* this access. The base and limits are checked.
6836	* Use UINT8_MAX to indicate that no segmentation
6837	* is required (for IDT, GDT and LDT accesses).
6838	* @param GCPtrMem The address of the guest memory.
6839	* @param a_fAccess How the memory is being accessed. The
6840	* IEM_ACCESS_TYPE_XXX bit is used to figure out
6841	* how to map the memory, while the
6842	* IEM_ACCESS_WHAT_XXX bit is used when raising
6843	* exceptions.
6844	*/
6845	static VBOXSTRICTRC iemMemMap(PIEMCPU pIemCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t fAccess)
6846	{
6847	/*
6848	* Check the input and figure out which mapping entry to use.
6849	*/
6850	Assert(cbMem <= 64 \|\| cbMem == 512 \|\| cbMem == 108 \|\| cbMem == 104 \|\| cbMem == 94); /* 512 is the max! */
6851	Assert(~(fAccess & ~(IEM_ACCESS_TYPE_MASK \| IEM_ACCESS_WHAT_MASK)));
6852
6853	unsigned iMemMap = pIemCpu->iNextMapping;
6854	if ( iMemMap >= RT_ELEMENTS(pIemCpu->aMemMappings)
6855	\|\| pIemCpu->aMemMappings[iMemMap].fAccess != IEM_ACCESS_INVALID)
6856	{
6857	iMemMap = iemMemMapFindFree(pIemCpu);
6858	AssertReturn(iMemMap < RT_ELEMENTS(pIemCpu->aMemMappings), VERR_INTERNAL_ERROR_3);
6859	}
6860
6861	/*
6862	* Map the memory, checking that we can actually access it. If something
6863	* slightly complicated happens, fall back on bounce buffering.
6864	*/
6865	VBOXSTRICTRC rcStrict = iemMemApplySegment(pIemCpu, fAccess, iSegReg, cbMem, &GCPtrMem);
6866	if (rcStrict != VINF_SUCCESS)
6867	return rcStrict;
6868
6869	if ((GCPtrMem & PAGE_OFFSET_MASK) + cbMem > PAGE_SIZE) /* Crossing a page boundary? */
6870	return iemMemBounceBufferMapCrossPage(pIemCpu, iMemMap, ppvMem, cbMem, GCPtrMem, fAccess);
6871
6872	RTGCPHYS GCPhysFirst;
6873	rcStrict = iemMemPageTranslateAndCheckAccess(pIemCpu, GCPtrMem, fAccess, &GCPhysFirst);
6874	if (rcStrict != VINF_SUCCESS)
6875	return rcStrict;
6876
6877	void *pvMem;
6878	rcStrict = iemMemPageMap(pIemCpu, GCPhysFirst, fAccess, &pvMem, &pIemCpu->aMemMappingLocks[iMemMap].Lock);
6879	if (rcStrict != VINF_SUCCESS)
6880	return iemMemBounceBufferMapPhys(pIemCpu, iMemMap, ppvMem, cbMem, GCPhysFirst, fAccess, rcStrict);
6881
6882	/*
6883	* Fill in the mapping table entry.
6884	*/
6885	pIemCpu->aMemMappings[iMemMap].pv = pvMem;
6886	pIemCpu->aMemMappings[iMemMap].fAccess = fAccess;
6887	pIemCpu->iNextMapping = iMemMap + 1;
6888	pIemCpu->cActiveMappings++;
6889
6890	iemMemUpdateWrittenCounter(pIemCpu, fAccess, cbMem);
6891	*ppvMem = pvMem;
6892	return VINF_SUCCESS;
6893	}
6894
6895
6896	/**
6897	* Commits the guest memory if bounce buffered and unmaps it.
6898	*
6899	* @returns Strict VBox status code.
6900	* @param pIemCpu The IEM per CPU data.
6901	* @param pvMem The mapping.
6902	* @param fAccess The kind of access.
6903	*/
6904	static VBOXSTRICTRC iemMemCommitAndUnmap(PIEMCPU pIemCpu, void *pvMem, uint32_t fAccess)
6905	{
6906	int iMemMap = iemMapLookup(pIemCpu, pvMem, fAccess);
6907	AssertReturn(iMemMap >= 0, iMemMap);
6908
6909	/* If it's bounce buffered, we may need to write back the buffer. */
6910	if (pIemCpu->aMemMappings[iMemMap].fAccess & IEM_ACCESS_BOUNCE_BUFFERED)
6911	{
6912	if (pIemCpu->aMemMappings[iMemMap].fAccess & IEM_ACCESS_TYPE_WRITE)
6913	return iemMemBounceBufferCommitAndUnmap(pIemCpu, iMemMap);
6914	}
6915	/* Otherwise unlock it. */
6916	else
6917	PGMPhysReleasePageMappingLock(IEMCPU_TO_VM(pIemCpu), &pIemCpu->aMemMappingLocks[iMemMap].Lock);
6918
6919	/* Free the entry. */
6920	pIemCpu->aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
6921	Assert(pIemCpu->cActiveMappings != 0);
6922	pIemCpu->cActiveMappings--;
6923	return VINF_SUCCESS;
6924	}
6925
6926
6927	/**
6928	* Rollbacks mappings, releasing page locks and such.
6929	*
6930	* The caller shall only call this after checking cActiveMappings.
6931	*
6932	* @returns Strict VBox status code to pass up.
6933	* @param pIemCpu The IEM per CPU data.
6934	*/
6935	static void iemMemRollback(PIEMCPU pIemCpu)
6936	{
6937	Assert(pIemCpu->cActiveMappings > 0);
6938
6939	uint32_t iMemMap = RT_ELEMENTS(pIemCpu->aMemMappings);
6940	while (iMemMap-- > 0)
6941	{
6942	uint32_t fAccess = pIemCpu->aMemMappings[iMemMap].fAccess;
6943	if (fAccess != IEM_ACCESS_INVALID)
6944	{
6945	pIemCpu->aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
6946	if (!(fAccess & IEM_ACCESS_BOUNCE_BUFFERED))
6947	PGMPhysReleasePageMappingLock(IEMCPU_TO_VM(pIemCpu), &pIemCpu->aMemMappingLocks[iMemMap].Lock);
6948	Assert(pIemCpu->cActiveMappings > 0);
6949	pIemCpu->cActiveMappings--;
6950	}
6951	}
6952	}
6953
6954
6955	/**
6956	* Fetches a data byte.
6957	*
6958	* @returns Strict VBox status code.
6959	* @param pIemCpu The IEM per CPU data.
6960	* @param pu8Dst Where to return the byte.
6961	* @param iSegReg The index of the segment register to use for
6962	* this access. The base and limits are checked.
6963	* @param GCPtrMem The address of the guest memory.
6964	*/
6965	static VBOXSTRICTRC iemMemFetchDataU8(PIEMCPU pIemCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
6966	{
6967	/* The lazy approach for now... */
6968	uint8_t const *pu8Src;
6969	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu8Src, sizeof(pu8Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
6970	if (rc == VINF_SUCCESS)
6971	{
6972	pu8Dst = pu8Src;
6973	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu8Src, IEM_ACCESS_DATA_R);
6974	}
6975	return rc;
6976	}
6977
6978
6979	/**
6980	* Fetches a data word.
6981	*
6982	* @returns Strict VBox status code.
6983	* @param pIemCpu The IEM per CPU data.
6984	* @param pu16Dst Where to return the word.
6985	* @param iSegReg The index of the segment register to use for
6986	* this access. The base and limits are checked.
6987	* @param GCPtrMem The address of the guest memory.
6988	*/
6989	static VBOXSTRICTRC iemMemFetchDataU16(PIEMCPU pIemCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
6990	{
6991	/* The lazy approach for now... */
6992	uint16_t const *pu16Src;
6993	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu16Src, sizeof(pu16Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
6994	if (rc == VINF_SUCCESS)
6995	{
6996	pu16Dst = pu16Src;
6997	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu16Src, IEM_ACCESS_DATA_R);
6998	}
6999	return rc;
7000	}
7001
7002
7003	/**
7004	* Fetches a data dword.
7005	*
7006	* @returns Strict VBox status code.
7007	* @param pIemCpu The IEM per CPU data.
7008	* @param pu32Dst Where to return the dword.
7009	* @param iSegReg The index of the segment register to use for
7010	* this access. The base and limits are checked.
7011	* @param GCPtrMem The address of the guest memory.
7012	*/
7013	static VBOXSTRICTRC iemMemFetchDataU32(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
7014	{
7015	/* The lazy approach for now... */
7016	uint32_t const *pu32Src;
7017	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu32Src, sizeof(pu32Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
7018	if (rc == VINF_SUCCESS)
7019	{
7020	pu32Dst = pu32Src;
7021	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu32Src, IEM_ACCESS_DATA_R);
7022	}
7023	return rc;
7024	}
7025
7026
7027	#ifdef SOME_UNUSED_FUNCTION
7028	/**
7029	* Fetches a data dword and sign extends it to a qword.
7030	*
7031	* @returns Strict VBox status code.
7032	* @param pIemCpu The IEM per CPU data.
7033	* @param pu64Dst Where to return the sign extended value.
7034	* @param iSegReg The index of the segment register to use for
7035	* this access. The base and limits are checked.
7036	* @param GCPtrMem The address of the guest memory.
7037	*/
7038	static VBOXSTRICTRC iemMemFetchDataS32SxU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
7039	{
7040	/* The lazy approach for now... */
7041	int32_t const *pi32Src;
7042	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pi32Src, sizeof(pi32Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
7043	if (rc == VINF_SUCCESS)
7044	{
7045	pu64Dst = pi32Src;
7046	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pi32Src, IEM_ACCESS_DATA_R);
7047	}
7048	#ifdef __GNUC__ /* warning: GCC may be a royal pain */
7049	else
7050	*pu64Dst = 0;
7051	#endif
7052	return rc;
7053	}
7054	#endif
7055
7056
7057	/**
7058	* Fetches a data qword.
7059	*
7060	* @returns Strict VBox status code.
7061	* @param pIemCpu The IEM per CPU data.
7062	* @param pu64Dst Where to return the qword.
7063	* @param iSegReg The index of the segment register to use for
7064	* this access. The base and limits are checked.
7065	* @param GCPtrMem The address of the guest memory.
7066	*/
7067	static VBOXSTRICTRC iemMemFetchDataU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
7068	{
7069	/* The lazy approach for now... */
7070	uint64_t const *pu64Src;
7071	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu64Src, sizeof(pu64Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
7072	if (rc == VINF_SUCCESS)
7073	{
7074	pu64Dst = pu64Src;
7075	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu64Src, IEM_ACCESS_DATA_R);
7076	}
7077	return rc;
7078	}
7079
7080
7081	/**
7082	* Fetches a data qword, aligned at a 16 byte boundrary (for SSE).
7083	*
7084	* @returns Strict VBox status code.
7085	* @param pIemCpu The IEM per CPU data.
7086	* @param pu64Dst Where to return the qword.
7087	* @param iSegReg The index of the segment register to use for
7088	* this access. The base and limits are checked.
7089	* @param GCPtrMem The address of the guest memory.
7090	*/
7091	static VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
7092	{
7093	/* The lazy approach for now... */
7094	/** @todo testcase: Ordering of \#SS(0) vs \#GP() vs \#PF on SSE stuff. */
7095	if (RT_UNLIKELY(GCPtrMem & 15))
7096	return iemRaiseGeneralProtectionFault0(pIemCpu);
7097
7098	uint64_t const *pu64Src;
7099	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu64Src, sizeof(pu64Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
7100	if (rc == VINF_SUCCESS)
7101	{
7102	pu64Dst = pu64Src;
7103	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu64Src, IEM_ACCESS_DATA_R);
7104	}
7105	return rc;
7106	}
7107
7108
7109	/**
7110	* Fetches a data tword.
7111	*
7112	* @returns Strict VBox status code.
7113	* @param pIemCpu The IEM per CPU data.
7114	* @param pr80Dst Where to return the tword.
7115	* @param iSegReg The index of the segment register to use for
7116	* this access. The base and limits are checked.
7117	* @param GCPtrMem The address of the guest memory.
7118	*/
7119	static VBOXSTRICTRC iemMemFetchDataR80(PIEMCPU pIemCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
7120	{
7121	/* The lazy approach for now... */
7122	PCRTFLOAT80U pr80Src;
7123	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pr80Src, sizeof(pr80Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
7124	if (rc == VINF_SUCCESS)
7125	{
7126	pr80Dst = pr80Src;
7127	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pr80Src, IEM_ACCESS_DATA_R);
7128	}
7129	return rc;
7130	}
7131
7132
7133	/**
7134	* Fetches a data dqword (double qword), generally SSE related.
7135	*
7136	* @returns Strict VBox status code.
7137	* @param pIemCpu The IEM per CPU data.
7138	* @param pu128Dst Where to return the qword.
7139	* @param iSegReg The index of the segment register to use for
7140	* this access. The base and limits are checked.
7141	* @param GCPtrMem The address of the guest memory.
7142	*/
7143	static VBOXSTRICTRC iemMemFetchDataU128(PIEMCPU pIemCpu, uint128_t *pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
7144	{
7145	/* The lazy approach for now... */
7146	uint128_t const *pu128Src;
7147	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu128Src, sizeof(pu128Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
7148	if (rc == VINF_SUCCESS)
7149	{
7150	pu128Dst = pu128Src;
7151	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu128Src, IEM_ACCESS_DATA_R);
7152	}
7153	return rc;
7154	}
7155
7156
7157	/**
7158	* Fetches a data dqword (double qword) at an aligned address, generally SSE
7159	* related.
7160	*
7161	* Raises \#GP(0) if not aligned.
7162	*
7163	* @returns Strict VBox status code.
7164	* @param pIemCpu The IEM per CPU data.
7165	* @param pu128Dst Where to return the qword.
7166	* @param iSegReg The index of the segment register to use for
7167	* this access. The base and limits are checked.
7168	* @param GCPtrMem The address of the guest memory.
7169	*/
7170	static VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PIEMCPU pIemCpu, uint128_t *pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
7171	{
7172	/* The lazy approach for now... */
7173	/** @todo testcase: Ordering of \#SS(0) vs \#GP() vs \#PF on SSE stuff. */
7174	if ((GCPtrMem & 15) && !(pIemCpu->CTX_SUFF(pCtx)->fpu.MXCSR & X86_MSXCR_MM)) /** @todo should probably check this after applying seg.u64Base... Check real HW. */
7175	return iemRaiseGeneralProtectionFault0(pIemCpu);
7176
7177	uint128_t const *pu128Src;
7178	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu128Src, sizeof(pu128Src), iSegReg, GCPtrMem, IEM_ACCESS_DATA_R);
7179	if (rc == VINF_SUCCESS)
7180	{
7181	pu128Dst = pu128Src;
7182	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu128Src, IEM_ACCESS_DATA_R);
7183	}
7184	return rc;
7185	}
7186
7187
7188
7189
7190	/**
7191	* Fetches a descriptor register (lgdt, lidt).
7192	*
7193	* @returns Strict VBox status code.
7194	* @param pIemCpu The IEM per CPU data.
7195	* @param pcbLimit Where to return the limit.
7196	* @param pGCPTrBase Where to return the base.
7197	* @param iSegReg The index of the segment register to use for
7198	* this access. The base and limits are checked.
7199	* @param GCPtrMem The address of the guest memory.
7200	* @param enmOpSize The effective operand size.
7201	*/
7202	static VBOXSTRICTRC iemMemFetchDataXdtr(PIEMCPU pIemCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase,
7203	uint8_t iSegReg, RTGCPTR GCPtrMem, IEMMODE enmOpSize)
7204	{
7205	uint8_t const *pu8Src;
7206	VBOXSTRICTRC rcStrict = iemMemMap(pIemCpu,
7207	(void **)&pu8Src,
7208	enmOpSize == IEMMODE_64BIT
7209	? 2 + 8
7210	: enmOpSize == IEMMODE_32BIT
7211	? 2 + 4
7212	: 2 + 3,
7213	iSegReg,
7214	GCPtrMem,
7215	IEM_ACCESS_DATA_R);
7216	if (rcStrict == VINF_SUCCESS)
7217	{
7218	*pcbLimit = RT_MAKE_U16(pu8Src[0], pu8Src[1]);
7219	switch (enmOpSize)
7220	{
7221	case IEMMODE_16BIT:
7222	*pGCPtrBase = RT_MAKE_U32_FROM_U8(pu8Src[2], pu8Src[3], pu8Src[4], 0);
7223	break;
7224	case IEMMODE_32BIT:
7225	*pGCPtrBase = RT_MAKE_U32_FROM_U8(pu8Src[2], pu8Src[3], pu8Src[4], pu8Src[5]);
7226	break;
7227	case IEMMODE_64BIT:
7228	*pGCPtrBase = RT_MAKE_U64_FROM_U8(pu8Src[2], pu8Src[3], pu8Src[4], pu8Src[5],
7229	pu8Src[6], pu8Src[7], pu8Src[8], pu8Src[9]);
7230	break;
7231
7232	IEM_NOT_REACHED_DEFAULT_CASE_RET();
7233	}
7234	rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)pu8Src, IEM_ACCESS_DATA_R);
7235	}
7236	return rcStrict;
7237	}
7238
7239
7240
7241	/**
7242	* Stores a data byte.
7243	*
7244	* @returns Strict VBox status code.
7245	* @param pIemCpu The IEM per CPU data.
7246	* @param iSegReg The index of the segment register to use for
7247	* this access. The base and limits are checked.
7248	* @param GCPtrMem The address of the guest memory.
7249	* @param u8Value The value to store.
7250	*/
7251	static VBOXSTRICTRC iemMemStoreDataU8(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value)
7252	{
7253	/* The lazy approach for now... */
7254	uint8_t *pu8Dst;
7255	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu8Dst, sizeof(pu8Dst), iSegReg, GCPtrMem, IEM_ACCESS_DATA_W);
7256	if (rc == VINF_SUCCESS)
7257	{
7258	*pu8Dst = u8Value;
7259	rc = iemMemCommitAndUnmap(pIemCpu, pu8Dst, IEM_ACCESS_DATA_W);
7260	}
7261	return rc;
7262	}
7263
7264
7265	/**
7266	* Stores a data word.
7267	*
7268	* @returns Strict VBox status code.
7269	* @param pIemCpu The IEM per CPU data.
7270	* @param iSegReg The index of the segment register to use for
7271	* this access. The base and limits are checked.
7272	* @param GCPtrMem The address of the guest memory.
7273	* @param u16Value The value to store.
7274	*/
7275	static VBOXSTRICTRC iemMemStoreDataU16(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value)
7276	{
7277	/* The lazy approach for now... */
7278	uint16_t *pu16Dst;
7279	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu16Dst, sizeof(pu16Dst), iSegReg, GCPtrMem, IEM_ACCESS_DATA_W);
7280	if (rc == VINF_SUCCESS)
7281	{
7282	*pu16Dst = u16Value;
7283	rc = iemMemCommitAndUnmap(pIemCpu, pu16Dst, IEM_ACCESS_DATA_W);
7284	}
7285	return rc;
7286	}
7287
7288
7289	/**
7290	* Stores a data dword.
7291	*
7292	* @returns Strict VBox status code.
7293	* @param pIemCpu The IEM per CPU data.
7294	* @param iSegReg The index of the segment register to use for
7295	* this access. The base and limits are checked.
7296	* @param GCPtrMem The address of the guest memory.
7297	* @param u32Value The value to store.
7298	*/
7299	static VBOXSTRICTRC iemMemStoreDataU32(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value)
7300	{
7301	/* The lazy approach for now... */
7302	uint32_t *pu32Dst;
7303	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu32Dst, sizeof(pu32Dst), iSegReg, GCPtrMem, IEM_ACCESS_DATA_W);
7304	if (rc == VINF_SUCCESS)
7305	{
7306	*pu32Dst = u32Value;
7307	rc = iemMemCommitAndUnmap(pIemCpu, pu32Dst, IEM_ACCESS_DATA_W);
7308	}
7309	return rc;
7310	}
7311
7312
7313	/**
7314	* Stores a data qword.
7315	*
7316	* @returns Strict VBox status code.
7317	* @param pIemCpu The IEM per CPU data.
7318	* @param iSegReg The index of the segment register to use for
7319	* this access. The base and limits are checked.
7320	* @param GCPtrMem The address of the guest memory.
7321	* @param u64Value The value to store.
7322	*/
7323	static VBOXSTRICTRC iemMemStoreDataU64(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value)
7324	{
7325	/* The lazy approach for now... */
7326	uint64_t *pu64Dst;
7327	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu64Dst, sizeof(pu64Dst), iSegReg, GCPtrMem, IEM_ACCESS_DATA_W);
7328	if (rc == VINF_SUCCESS)
7329	{
7330	*pu64Dst = u64Value;
7331	rc = iemMemCommitAndUnmap(pIemCpu, pu64Dst, IEM_ACCESS_DATA_W);
7332	}
7333	return rc;
7334	}
7335
7336
7337	/**
7338	* Stores a data dqword.
7339	*
7340	* @returns Strict VBox status code.
7341	* @param pIemCpu The IEM per CPU data.
7342	* @param iSegReg The index of the segment register to use for
7343	* this access. The base and limits are checked.
7344	* @param GCPtrMem The address of the guest memory.
7345	* @param u64Value The value to store.
7346	*/
7347	static VBOXSTRICTRC iemMemStoreDataU128(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint128_t u128Value)
7348	{
7349	/* The lazy approach for now... */
7350	uint128_t *pu128Dst;
7351	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu128Dst, sizeof(pu128Dst), iSegReg, GCPtrMem, IEM_ACCESS_DATA_W);
7352	if (rc == VINF_SUCCESS)
7353	{
7354	*pu128Dst = u128Value;
7355	rc = iemMemCommitAndUnmap(pIemCpu, pu128Dst, IEM_ACCESS_DATA_W);
7356	}
7357	return rc;
7358	}
7359
7360
7361	/**
7362	* Stores a data dqword, SSE aligned.
7363	*
7364	* @returns Strict VBox status code.
7365	* @param pIemCpu The IEM per CPU data.
7366	* @param iSegReg The index of the segment register to use for
7367	* this access. The base and limits are checked.
7368	* @param GCPtrMem The address of the guest memory.
7369	* @param u64Value The value to store.
7370	*/
7371	static VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PIEMCPU pIemCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint128_t u128Value)
7372	{
7373	/* The lazy approach for now... */
7374	if ((GCPtrMem & 15) && !(pIemCpu->CTX_SUFF(pCtx)->fpu.MXCSR & X86_MSXCR_MM)) /** @todo should probably check this after applying seg.u64Base... Check real HW. */
7375	return iemRaiseGeneralProtectionFault0(pIemCpu);
7376
7377	uint128_t *pu128Dst;
7378	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu128Dst, sizeof(pu128Dst), iSegReg, GCPtrMem, IEM_ACCESS_DATA_W);
7379	if (rc == VINF_SUCCESS)
7380	{
7381	*pu128Dst = u128Value;
7382	rc = iemMemCommitAndUnmap(pIemCpu, pu128Dst, IEM_ACCESS_DATA_W);
7383	}
7384	return rc;
7385	}
7386
7387
7388	/**
7389	* Stores a descriptor register (sgdt, sidt).
7390	*
7391	* @returns Strict VBox status code.
7392	* @param pIemCpu The IEM per CPU data.
7393	* @param cbLimit The limit.
7394	* @param GCPTrBase The base address.
7395	* @param iSegReg The index of the segment register to use for
7396	* this access. The base and limits are checked.
7397	* @param GCPtrMem The address of the guest memory.
7398	* @param enmOpSize The effective operand size.
7399	*/
7400	static VBOXSTRICTRC iemMemStoreDataXdtr(PIEMCPU pIemCpu, uint16_t cbLimit, RTGCPTR GCPtrBase,
7401	uint8_t iSegReg, RTGCPTR GCPtrMem, IEMMODE enmOpSize)
7402	{
7403	uint8_t *pu8Src;
7404	VBOXSTRICTRC rcStrict = iemMemMap(pIemCpu,
7405	(void **)&pu8Src,
7406	enmOpSize == IEMMODE_64BIT
7407	? 2 + 8
7408	: enmOpSize == IEMMODE_32BIT
7409	? 2 + 4
7410	: 2 + 3,
7411	iSegReg,
7412	GCPtrMem,
7413	IEM_ACCESS_DATA_W);
7414	if (rcStrict == VINF_SUCCESS)
7415	{
7416	pu8Src[0] = RT_BYTE1(cbLimit);
7417	pu8Src[1] = RT_BYTE2(cbLimit);
7418	pu8Src[2] = RT_BYTE1(GCPtrBase);
7419	pu8Src[3] = RT_BYTE2(GCPtrBase);
7420	pu8Src[4] = RT_BYTE3(GCPtrBase);
7421	if (enmOpSize == IEMMODE_16BIT)
7422	pu8Src[5] = 0; /* Note! the 286 stored 0xff here. */
7423	else
7424	{
7425	pu8Src[5] = RT_BYTE4(GCPtrBase);
7426	if (enmOpSize == IEMMODE_64BIT)
7427	{
7428	pu8Src[6] = RT_BYTE5(GCPtrBase);
7429	pu8Src[7] = RT_BYTE6(GCPtrBase);
7430	pu8Src[8] = RT_BYTE7(GCPtrBase);
7431	pu8Src[9] = RT_BYTE8(GCPtrBase);
7432	}
7433	}
7434	rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)pu8Src, IEM_ACCESS_DATA_W);
7435	}
7436	return rcStrict;
7437	}
7438
7439
7440	/**
7441	* Pushes a word onto the stack.
7442	*
7443	* @returns Strict VBox status code.
7444	* @param pIemCpu The IEM per CPU data.
7445	* @param u16Value The value to push.
7446	*/
7447	static VBOXSTRICTRC iemMemStackPushU16(PIEMCPU pIemCpu, uint16_t u16Value)
7448	{
7449	/* Increment the stack pointer. */
7450	uint64_t uNewRsp;
7451	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7452	RTGCPTR GCPtrTop = iemRegGetRspForPush(pIemCpu, pCtx, 2, &uNewRsp);
7453
7454	/* Write the word the lazy way. */
7455	uint16_t *pu16Dst;
7456	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu16Dst, sizeof(pu16Dst), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_W);
7457	if (rc == VINF_SUCCESS)
7458	{
7459	*pu16Dst = u16Value;
7460	rc = iemMemCommitAndUnmap(pIemCpu, pu16Dst, IEM_ACCESS_STACK_W);
7461	}
7462
7463	/* Commit the new RSP value unless we an access handler made trouble. */
7464	if (rc == VINF_SUCCESS)
7465	pCtx->rsp = uNewRsp;
7466
7467	return rc;
7468	}
7469
7470
7471	/**
7472	* Pushes a dword onto the stack.
7473	*
7474	* @returns Strict VBox status code.
7475	* @param pIemCpu The IEM per CPU data.
7476	* @param u32Value The value to push.
7477	*/
7478	static VBOXSTRICTRC iemMemStackPushU32(PIEMCPU pIemCpu, uint32_t u32Value)
7479	{
7480	/* Increment the stack pointer. */
7481	uint64_t uNewRsp;
7482	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7483	RTGCPTR GCPtrTop = iemRegGetRspForPush(pIemCpu, pCtx, 4, &uNewRsp);
7484
7485	/* Write the dword the lazy way. */
7486	uint32_t *pu32Dst;
7487	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu32Dst, sizeof(pu32Dst), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_W);
7488	if (rc == VINF_SUCCESS)
7489	{
7490	*pu32Dst = u32Value;
7491	rc = iemMemCommitAndUnmap(pIemCpu, pu32Dst, IEM_ACCESS_STACK_W);
7492	}
7493
7494	/* Commit the new RSP value unless we an access handler made trouble. */
7495	if (rc == VINF_SUCCESS)
7496	pCtx->rsp = uNewRsp;
7497
7498	return rc;
7499	}
7500
7501
7502	/**
7503	* Pushes a dword segment register value onto the stack.
7504	*
7505	* @returns Strict VBox status code.
7506	* @param pIemCpu The IEM per CPU data.
7507	* @param u16Value The value to push.
7508	*/
7509	static VBOXSTRICTRC iemMemStackPushU32SReg(PIEMCPU pIemCpu, uint32_t u32Value)
7510	{
7511	/* Increment the stack pointer. */
7512	uint64_t uNewRsp;
7513	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7514	RTGCPTR GCPtrTop = iemRegGetRspForPush(pIemCpu, pCtx, 4, &uNewRsp);
7515
7516	VBOXSTRICTRC rc;
7517	if (IEM_FULL_VERIFICATION_REM_ENABLED(pIemCpu))
7518	{
7519	/* The recompiler writes a full dword. */
7520	uint32_t *pu32Dst;
7521	rc = iemMemMap(pIemCpu, (void *)&pu32Dst, sizeof(pu32Dst), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_W);
7522	if (rc == VINF_SUCCESS)
7523	{
7524	*pu32Dst = u32Value;
7525	rc = iemMemCommitAndUnmap(pIemCpu, pu32Dst, IEM_ACCESS_STACK_W);
7526	}
7527	}
7528	else
7529	{
7530	/* The intel docs talks about zero extending the selector register
7531	value. My actual intel CPU here might be zero extending the value
7532	but it still only writes the lower word... */
7533	/** @todo Test this on new HW and on AMD and in 64-bit mode. Also test what
7534	* happens when crossing an electric page boundrary, is the high word
7535	* checked for write accessibility or not? Probably it is. What about
7536	* segment limits? */
7537	uint16_t *pu16Dst;
7538	rc = iemMemMap(pIemCpu, (void **)&pu16Dst, sizeof(uint32_t), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_RW);
7539	if (rc == VINF_SUCCESS)
7540	{
7541	*pu16Dst = (uint16_t)u32Value;
7542	rc = iemMemCommitAndUnmap(pIemCpu, pu16Dst, IEM_ACCESS_STACK_RW);
7543	}
7544	}
7545
7546	/* Commit the new RSP value unless we an access handler made trouble. */
7547	if (rc == VINF_SUCCESS)
7548	pCtx->rsp = uNewRsp;
7549
7550	return rc;
7551	}
7552
7553
7554	/**
7555	* Pushes a qword onto the stack.
7556	*
7557	* @returns Strict VBox status code.
7558	* @param pIemCpu The IEM per CPU data.
7559	* @param u64Value The value to push.
7560	*/
7561	static VBOXSTRICTRC iemMemStackPushU64(PIEMCPU pIemCpu, uint64_t u64Value)
7562	{
7563	/* Increment the stack pointer. */
7564	uint64_t uNewRsp;
7565	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7566	RTGCPTR GCPtrTop = iemRegGetRspForPush(pIemCpu, pCtx, 8, &uNewRsp);
7567
7568	/* Write the word the lazy way. */
7569	uint64_t *pu64Dst;
7570	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu64Dst, sizeof(pu64Dst), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_W);
7571	if (rc == VINF_SUCCESS)
7572	{
7573	*pu64Dst = u64Value;
7574	rc = iemMemCommitAndUnmap(pIemCpu, pu64Dst, IEM_ACCESS_STACK_W);
7575	}
7576
7577	/* Commit the new RSP value unless we an access handler made trouble. */
7578	if (rc == VINF_SUCCESS)
7579	pCtx->rsp = uNewRsp;
7580
7581	return rc;
7582	}
7583
7584
7585	/**
7586	* Pops a word from the stack.
7587	*
7588	* @returns Strict VBox status code.
7589	* @param pIemCpu The IEM per CPU data.
7590	* @param pu16Value Where to store the popped value.
7591	*/
7592	static VBOXSTRICTRC iemMemStackPopU16(PIEMCPU pIemCpu, uint16_t *pu16Value)
7593	{
7594	/* Increment the stack pointer. */
7595	uint64_t uNewRsp;
7596	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7597	RTGCPTR GCPtrTop = iemRegGetRspForPop(pIemCpu, pCtx, 2, &uNewRsp);
7598
7599	/* Write the word the lazy way. */
7600	uint16_t const *pu16Src;
7601	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu16Src, sizeof(pu16Src), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_R);
7602	if (rc == VINF_SUCCESS)
7603	{
7604	pu16Value = pu16Src;
7605	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu16Src, IEM_ACCESS_STACK_R);
7606
7607	/* Commit the new RSP value. */
7608	if (rc == VINF_SUCCESS)
7609	pCtx->rsp = uNewRsp;
7610	}
7611
7612	return rc;
7613	}
7614
7615
7616	/**
7617	* Pops a dword from the stack.
7618	*
7619	* @returns Strict VBox status code.
7620	* @param pIemCpu The IEM per CPU data.
7621	* @param pu32Value Where to store the popped value.
7622	*/
7623	static VBOXSTRICTRC iemMemStackPopU32(PIEMCPU pIemCpu, uint32_t *pu32Value)
7624	{
7625	/* Increment the stack pointer. */
7626	uint64_t uNewRsp;
7627	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7628	RTGCPTR GCPtrTop = iemRegGetRspForPop(pIemCpu, pCtx, 4, &uNewRsp);
7629
7630	/* Write the word the lazy way. */
7631	uint32_t const *pu32Src;
7632	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu32Src, sizeof(pu32Src), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_R);
7633	if (rc == VINF_SUCCESS)
7634	{
7635	pu32Value = pu32Src;
7636	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu32Src, IEM_ACCESS_STACK_R);
7637
7638	/* Commit the new RSP value. */
7639	if (rc == VINF_SUCCESS)
7640	pCtx->rsp = uNewRsp;
7641	}
7642
7643	return rc;
7644	}
7645
7646
7647	/**
7648	* Pops a qword from the stack.
7649	*
7650	* @returns Strict VBox status code.
7651	* @param pIemCpu The IEM per CPU data.
7652	* @param pu64Value Where to store the popped value.
7653	*/
7654	static VBOXSTRICTRC iemMemStackPopU64(PIEMCPU pIemCpu, uint64_t *pu64Value)
7655	{
7656	/* Increment the stack pointer. */
7657	uint64_t uNewRsp;
7658	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7659	RTGCPTR GCPtrTop = iemRegGetRspForPop(pIemCpu, pCtx, 8, &uNewRsp);
7660
7661	/* Write the word the lazy way. */
7662	uint64_t const *pu64Src;
7663	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu64Src, sizeof(pu64Src), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_R);
7664	if (rc == VINF_SUCCESS)
7665	{
7666	pu64Value = pu64Src;
7667	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu64Src, IEM_ACCESS_STACK_R);
7668
7669	/* Commit the new RSP value. */
7670	if (rc == VINF_SUCCESS)
7671	pCtx->rsp = uNewRsp;
7672	}
7673
7674	return rc;
7675	}
7676
7677
7678	/**
7679	* Pushes a word onto the stack, using a temporary stack pointer.
7680	*
7681	* @returns Strict VBox status code.
7682	* @param pIemCpu The IEM per CPU data.
7683	* @param u16Value The value to push.
7684	* @param pTmpRsp Pointer to the temporary stack pointer.
7685	*/
7686	static VBOXSTRICTRC iemMemStackPushU16Ex(PIEMCPU pIemCpu, uint16_t u16Value, PRTUINT64U pTmpRsp)
7687	{
7688	/* Increment the stack pointer. */
7689	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7690	RTUINT64U NewRsp = *pTmpRsp;
7691	RTGCPTR GCPtrTop = iemRegGetRspForPushEx(pIemCpu, pCtx, &NewRsp, 2);
7692
7693	/* Write the word the lazy way. */
7694	uint16_t *pu16Dst;
7695	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu16Dst, sizeof(pu16Dst), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_W);
7696	if (rc == VINF_SUCCESS)
7697	{
7698	*pu16Dst = u16Value;
7699	rc = iemMemCommitAndUnmap(pIemCpu, pu16Dst, IEM_ACCESS_STACK_W);
7700	}
7701
7702	/* Commit the new RSP value unless we an access handler made trouble. */
7703	if (rc == VINF_SUCCESS)
7704	*pTmpRsp = NewRsp;
7705
7706	return rc;
7707	}
7708
7709
7710	/**
7711	* Pushes a dword onto the stack, using a temporary stack pointer.
7712	*
7713	* @returns Strict VBox status code.
7714	* @param pIemCpu The IEM per CPU data.
7715	* @param u32Value The value to push.
7716	* @param pTmpRsp Pointer to the temporary stack pointer.
7717	*/
7718	static VBOXSTRICTRC iemMemStackPushU32Ex(PIEMCPU pIemCpu, uint32_t u32Value, PRTUINT64U pTmpRsp)
7719	{
7720	/* Increment the stack pointer. */
7721	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7722	RTUINT64U NewRsp = *pTmpRsp;
7723	RTGCPTR GCPtrTop = iemRegGetRspForPushEx(pIemCpu, pCtx, &NewRsp, 4);
7724
7725	/* Write the word the lazy way. */
7726	uint32_t *pu32Dst;
7727	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu32Dst, sizeof(pu32Dst), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_W);
7728	if (rc == VINF_SUCCESS)
7729	{
7730	*pu32Dst = u32Value;
7731	rc = iemMemCommitAndUnmap(pIemCpu, pu32Dst, IEM_ACCESS_STACK_W);
7732	}
7733
7734	/* Commit the new RSP value unless we an access handler made trouble. */
7735	if (rc == VINF_SUCCESS)
7736	*pTmpRsp = NewRsp;
7737
7738	return rc;
7739	}
7740
7741
7742	/**
7743	* Pushes a dword onto the stack, using a temporary stack pointer.
7744	*
7745	* @returns Strict VBox status code.
7746	* @param pIemCpu The IEM per CPU data.
7747	* @param u64Value The value to push.
7748	* @param pTmpRsp Pointer to the temporary stack pointer.
7749	*/
7750	static VBOXSTRICTRC iemMemStackPushU64Ex(PIEMCPU pIemCpu, uint64_t u64Value, PRTUINT64U pTmpRsp)
7751	{
7752	/* Increment the stack pointer. */
7753	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7754	RTUINT64U NewRsp = *pTmpRsp;
7755	RTGCPTR GCPtrTop = iemRegGetRspForPushEx(pIemCpu, pCtx, &NewRsp, 8);
7756
7757	/* Write the word the lazy way. */
7758	uint64_t *pu64Dst;
7759	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu64Dst, sizeof(pu64Dst), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_W);
7760	if (rc == VINF_SUCCESS)
7761	{
7762	*pu64Dst = u64Value;
7763	rc = iemMemCommitAndUnmap(pIemCpu, pu64Dst, IEM_ACCESS_STACK_W);
7764	}
7765
7766	/* Commit the new RSP value unless we an access handler made trouble. */
7767	if (rc == VINF_SUCCESS)
7768	*pTmpRsp = NewRsp;
7769
7770	return rc;
7771	}
7772
7773
7774	/**
7775	* Pops a word from the stack, using a temporary stack pointer.
7776	*
7777	* @returns Strict VBox status code.
7778	* @param pIemCpu The IEM per CPU data.
7779	* @param pu16Value Where to store the popped value.
7780	* @param pTmpRsp Pointer to the temporary stack pointer.
7781	*/
7782	static VBOXSTRICTRC iemMemStackPopU16Ex(PIEMCPU pIemCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp)
7783	{
7784	/* Increment the stack pointer. */
7785	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7786	RTUINT64U NewRsp = *pTmpRsp;
7787	RTGCPTR GCPtrTop = iemRegGetRspForPopEx(pIemCpu, pCtx, &NewRsp, 2);
7788
7789	/* Write the word the lazy way. */
7790	uint16_t const *pu16Src;
7791	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu16Src, sizeof(pu16Src), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_R);
7792	if (rc == VINF_SUCCESS)
7793	{
7794	pu16Value = pu16Src;
7795	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu16Src, IEM_ACCESS_STACK_R);
7796
7797	/* Commit the new RSP value. */
7798	if (rc == VINF_SUCCESS)
7799	*pTmpRsp = NewRsp;
7800	}
7801
7802	return rc;
7803	}
7804
7805
7806	/**
7807	* Pops a dword from the stack, using a temporary stack pointer.
7808	*
7809	* @returns Strict VBox status code.
7810	* @param pIemCpu The IEM per CPU data.
7811	* @param pu32Value Where to store the popped value.
7812	* @param pTmpRsp Pointer to the temporary stack pointer.
7813	*/
7814	static VBOXSTRICTRC iemMemStackPopU32Ex(PIEMCPU pIemCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp)
7815	{
7816	/* Increment the stack pointer. */
7817	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7818	RTUINT64U NewRsp = *pTmpRsp;
7819	RTGCPTR GCPtrTop = iemRegGetRspForPopEx(pIemCpu, pCtx, &NewRsp, 4);
7820
7821	/* Write the word the lazy way. */
7822	uint32_t const *pu32Src;
7823	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu32Src, sizeof(pu32Src), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_R);
7824	if (rc == VINF_SUCCESS)
7825	{
7826	pu32Value = pu32Src;
7827	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu32Src, IEM_ACCESS_STACK_R);
7828
7829	/* Commit the new RSP value. */
7830	if (rc == VINF_SUCCESS)
7831	*pTmpRsp = NewRsp;
7832	}
7833
7834	return rc;
7835	}
7836
7837
7838	/**
7839	* Pops a qword from the stack, using a temporary stack pointer.
7840	*
7841	* @returns Strict VBox status code.
7842	* @param pIemCpu The IEM per CPU data.
7843	* @param pu64Value Where to store the popped value.
7844	* @param pTmpRsp Pointer to the temporary stack pointer.
7845	*/
7846	static VBOXSTRICTRC iemMemStackPopU64Ex(PIEMCPU pIemCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp)
7847	{
7848	/* Increment the stack pointer. */
7849	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7850	RTUINT64U NewRsp = *pTmpRsp;
7851	RTGCPTR GCPtrTop = iemRegGetRspForPopEx(pIemCpu, pCtx, &NewRsp, 8);
7852
7853	/* Write the word the lazy way. */
7854	uint64_t const *pu64Src;
7855	VBOXSTRICTRC rcStrict = iemMemMap(pIemCpu, (void *)&pu64Src, sizeof(pu64Src), X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_R);
7856	if (rcStrict == VINF_SUCCESS)
7857	{
7858	pu64Value = pu64Src;
7859	rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)pu64Src, IEM_ACCESS_STACK_R);
7860
7861	/* Commit the new RSP value. */
7862	if (rcStrict == VINF_SUCCESS)
7863	*pTmpRsp = NewRsp;
7864	}
7865
7866	return rcStrict;
7867	}
7868
7869
7870	/**
7871	* Begin a special stack push (used by interrupt, exceptions and such).
7872	*
7873	* This will raise #SS or #PF if appropriate.
7874	*
7875	* @returns Strict VBox status code.
7876	* @param pIemCpu The IEM per CPU data.
7877	* @param cbMem The number of bytes to push onto the stack.
7878	* @param ppvMem Where to return the pointer to the stack memory.
7879	* As with the other memory functions this could be
7880	* direct access or bounce buffered access, so
7881	* don't commit register until the commit call
7882	* succeeds.
7883	* @param puNewRsp Where to return the new RSP value. This must be
7884	* passed unchanged to
7885	* iemMemStackPushCommitSpecial().
7886	*/
7887	static VBOXSTRICTRC iemMemStackPushBeginSpecial(PIEMCPU pIemCpu, size_t cbMem, void *ppvMem, uint64_t puNewRsp)
7888	{
7889	Assert(cbMem < UINT8_MAX);
7890	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7891	RTGCPTR GCPtrTop = iemRegGetRspForPush(pIemCpu, pCtx, (uint8_t)cbMem, puNewRsp);
7892	return iemMemMap(pIemCpu, ppvMem, cbMem, X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_W);
7893	}
7894
7895
7896	/**
7897	* Commits a special stack push (started by iemMemStackPushBeginSpecial).
7898	*
7899	* This will update the rSP.
7900	*
7901	* @returns Strict VBox status code.
7902	* @param pIemCpu The IEM per CPU data.
7903	* @param pvMem The pointer returned by
7904	* iemMemStackPushBeginSpecial().
7905	* @param uNewRsp The new RSP value returned by
7906	* iemMemStackPushBeginSpecial().
7907	*/
7908	static VBOXSTRICTRC iemMemStackPushCommitSpecial(PIEMCPU pIemCpu, void *pvMem, uint64_t uNewRsp)
7909	{
7910	VBOXSTRICTRC rcStrict = iemMemCommitAndUnmap(pIemCpu, pvMem, IEM_ACCESS_STACK_W);
7911	if (rcStrict == VINF_SUCCESS)
7912	pIemCpu->CTX_SUFF(pCtx)->rsp = uNewRsp;
7913	return rcStrict;
7914	}
7915
7916
7917	/**
7918	* Begin a special stack pop (used by iret, retf and such).
7919	*
7920	* This will raise \#SS or \#PF if appropriate.
7921	*
7922	* @returns Strict VBox status code.
7923	* @param pIemCpu The IEM per CPU data.
7924	* @param cbMem The number of bytes to push onto the stack.
7925	* @param ppvMem Where to return the pointer to the stack memory.
7926	* @param puNewRsp Where to return the new RSP value. This must be
7927	* passed unchanged to
7928	* iemMemStackPopCommitSpecial() or applied
7929	* manually if iemMemStackPopDoneSpecial() is used.
7930	*/
7931	static VBOXSTRICTRC iemMemStackPopBeginSpecial(PIEMCPU pIemCpu, size_t cbMem, void const *ppvMem, uint64_t puNewRsp)
7932	{
7933	Assert(cbMem < UINT8_MAX);
7934	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7935	RTGCPTR GCPtrTop = iemRegGetRspForPop(pIemCpu, pCtx, (uint8_t)cbMem, puNewRsp);
7936	return iemMemMap(pIemCpu, (void **)ppvMem, cbMem, X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_R);
7937	}
7938
7939
7940	/**
7941	* Continue a special stack pop (used by iret and retf).
7942	*
7943	* This will raise \#SS or \#PF if appropriate.
7944	*
7945	* @returns Strict VBox status code.
7946	* @param pIemCpu The IEM per CPU data.
7947	* @param cbMem The number of bytes to push onto the stack.
7948	* @param ppvMem Where to return the pointer to the stack memory.
7949	* @param puNewRsp Where to return the new RSP value. This must be
7950	* passed unchanged to
7951	* iemMemStackPopCommitSpecial() or applied
7952	* manually if iemMemStackPopDoneSpecial() is used.
7953	*/
7954	static VBOXSTRICTRC iemMemStackPopContinueSpecial(PIEMCPU pIemCpu, size_t cbMem, void const *ppvMem, uint64_t puNewRsp)
7955	{
7956	Assert(cbMem < UINT8_MAX);
7957	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
7958	RTUINT64U NewRsp;
7959	NewRsp.u = *puNewRsp;
7960	RTGCPTR GCPtrTop = iemRegGetRspForPopEx(pIemCpu, pCtx, &NewRsp, 8);
7961	*puNewRsp = NewRsp.u;
7962	return iemMemMap(pIemCpu, (void **)ppvMem, cbMem, X86_SREG_SS, GCPtrTop, IEM_ACCESS_STACK_R);
7963	}
7964
7965
7966	/**
7967	* Commits a special stack pop (started by iemMemStackPopBeginSpecial).
7968	*
7969	* This will update the rSP.
7970	*
7971	* @returns Strict VBox status code.
7972	* @param pIemCpu The IEM per CPU data.
7973	* @param pvMem The pointer returned by
7974	* iemMemStackPopBeginSpecial().
7975	* @param uNewRsp The new RSP value returned by
7976	* iemMemStackPopBeginSpecial().
7977	*/
7978	static VBOXSTRICTRC iemMemStackPopCommitSpecial(PIEMCPU pIemCpu, void const *pvMem, uint64_t uNewRsp)
7979	{
7980	VBOXSTRICTRC rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)pvMem, IEM_ACCESS_STACK_R);
7981	if (rcStrict == VINF_SUCCESS)
7982	pIemCpu->CTX_SUFF(pCtx)->rsp = uNewRsp;
7983	return rcStrict;
7984	}
7985
7986
7987	/**
7988	* Done with a special stack pop (started by iemMemStackPopBeginSpecial or
7989	* iemMemStackPopContinueSpecial).
7990	*
7991	* The caller will manually commit the rSP.
7992	*
7993	* @returns Strict VBox status code.
7994	* @param pIemCpu The IEM per CPU data.
7995	* @param pvMem The pointer returned by
7996	* iemMemStackPopBeginSpecial() or
7997	* iemMemStackPopContinueSpecial().
7998	*/
7999	static VBOXSTRICTRC iemMemStackPopDoneSpecial(PIEMCPU pIemCpu, void const *pvMem)
8000	{
8001	return iemMemCommitAndUnmap(pIemCpu, (void *)pvMem, IEM_ACCESS_STACK_R);
8002	}
8003
8004
8005	/**
8006	* Fetches a system table byte.
8007	*
8008	* @returns Strict VBox status code.
8009	* @param pIemCpu The IEM per CPU data.
8010	* @param pbDst Where to return the byte.
8011	* @param iSegReg The index of the segment register to use for
8012	* this access. The base and limits are checked.
8013	* @param GCPtrMem The address of the guest memory.
8014	*/
8015	static VBOXSTRICTRC iemMemFetchSysU8(PIEMCPU pIemCpu, uint8_t *pbDst, uint8_t iSegReg, RTGCPTR GCPtrMem)
8016	{
8017	/* The lazy approach for now... */
8018	uint8_t const *pbSrc;
8019	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pbSrc, sizeof(pbSrc), iSegReg, GCPtrMem, IEM_ACCESS_SYS_R);
8020	if (rc == VINF_SUCCESS)
8021	{
8022	pbDst = pbSrc;
8023	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pbSrc, IEM_ACCESS_SYS_R);
8024	}
8025	return rc;
8026	}
8027
8028
8029	/**
8030	* Fetches a system table word.
8031	*
8032	* @returns Strict VBox status code.
8033	* @param pIemCpu The IEM per CPU data.
8034	* @param pu16Dst Where to return the word.
8035	* @param iSegReg The index of the segment register to use for
8036	* this access. The base and limits are checked.
8037	* @param GCPtrMem The address of the guest memory.
8038	*/
8039	static VBOXSTRICTRC iemMemFetchSysU16(PIEMCPU pIemCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
8040	{
8041	/* The lazy approach for now... */
8042	uint16_t const *pu16Src;
8043	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu16Src, sizeof(pu16Src), iSegReg, GCPtrMem, IEM_ACCESS_SYS_R);
8044	if (rc == VINF_SUCCESS)
8045	{
8046	pu16Dst = pu16Src;
8047	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu16Src, IEM_ACCESS_SYS_R);
8048	}
8049	return rc;
8050	}
8051
8052
8053	/**
8054	* Fetches a system table dword.
8055	*
8056	* @returns Strict VBox status code.
8057	* @param pIemCpu The IEM per CPU data.
8058	* @param pu32Dst Where to return the dword.
8059	* @param iSegReg The index of the segment register to use for
8060	* this access. The base and limits are checked.
8061	* @param GCPtrMem The address of the guest memory.
8062	*/
8063	static VBOXSTRICTRC iemMemFetchSysU32(PIEMCPU pIemCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
8064	{
8065	/* The lazy approach for now... */
8066	uint32_t const *pu32Src;
8067	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu32Src, sizeof(pu32Src), iSegReg, GCPtrMem, IEM_ACCESS_SYS_R);
8068	if (rc == VINF_SUCCESS)
8069	{
8070	pu32Dst = pu32Src;
8071	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu32Src, IEM_ACCESS_SYS_R);
8072	}
8073	return rc;
8074	}
8075
8076
8077	/**
8078	* Fetches a system table qword.
8079	*
8080	* @returns Strict VBox status code.
8081	* @param pIemCpu The IEM per CPU data.
8082	* @param pu64Dst Where to return the qword.
8083	* @param iSegReg The index of the segment register to use for
8084	* this access. The base and limits are checked.
8085	* @param GCPtrMem The address of the guest memory.
8086	*/
8087	static VBOXSTRICTRC iemMemFetchSysU64(PIEMCPU pIemCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem)
8088	{
8089	/* The lazy approach for now... */
8090	uint64_t const *pu64Src;
8091	VBOXSTRICTRC rc = iemMemMap(pIemCpu, (void *)&pu64Src, sizeof(pu64Src), iSegReg, GCPtrMem, IEM_ACCESS_SYS_R);
8092	if (rc == VINF_SUCCESS)
8093	{
8094	pu64Dst = pu64Src;
8095	rc = iemMemCommitAndUnmap(pIemCpu, (void *)pu64Src, IEM_ACCESS_SYS_R);
8096	}
8097	return rc;
8098	}
8099
8100
8101	/**
8102	* Fetches a descriptor table entry with caller specified error code.
8103	*
8104	* @returns Strict VBox status code.
8105	* @param pIemCpu The IEM per CPU.
8106	* @param pDesc Where to return the descriptor table entry.
8107	* @param uSel The selector which table entry to fetch.
8108	* @param uXcpt The exception to raise on table lookup error.
8109	* @param uErrorCode The error code associated with the exception.
8110	*/
8111	static VBOXSTRICTRC iemMemFetchSelDescWithErr(PIEMCPU pIemCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt,
8112	uint16_t uErrorCode)
8113	{
8114	AssertPtr(pDesc);
8115	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
8116
8117	/** @todo did the 286 require all 8 bytes to be accessible? */
8118	/*
8119	* Get the selector table base and check bounds.
8120	*/
8121	RTGCPTR GCPtrBase;
8122	if (uSel & X86_SEL_LDT)
8123	{
8124	if ( !pCtx->ldtr.Attr.n.u1Present
8125	\|\| (uSel \| X86_SEL_RPL_LDT) > pCtx->ldtr.u32Limit )
8126	{
8127	Log(("iemMemFetchSelDesc: LDT selector %#x is out of bounds (%3x) or ldtr is NP (%#x)\n",
8128	uSel, pCtx->ldtr.u32Limit, pCtx->ldtr.Sel));
8129	return iemRaiseXcptOrInt(pIemCpu, 0, uXcpt, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR,
8130	uErrorCode, 0);
8131	}
8132
8133	Assert(pCtx->ldtr.Attr.n.u1Present);
8134	GCPtrBase = pCtx->ldtr.u64Base;
8135	}
8136	else
8137	{
8138	if ((uSel \| X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
8139	{
8140	Log(("iemMemFetchSelDesc: GDT selector %#x is out of bounds (%3x)\n", uSel, pCtx->gdtr.cbGdt));
8141	return iemRaiseXcptOrInt(pIemCpu, 0, uXcpt, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR,
8142	uErrorCode, 0);
8143	}
8144	GCPtrBase = pCtx->gdtr.pGdt;
8145	}
8146
8147	/*
8148	* Read the legacy descriptor and maybe the long mode extensions if
8149	* required.
8150	*/
8151	VBOXSTRICTRC rcStrict = iemMemFetchSysU64(pIemCpu, &pDesc->Legacy.u, UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK));
8152	if (rcStrict == VINF_SUCCESS)
8153	{
8154	if ( !IEM_IS_LONG_MODE(pIemCpu)
8155	\|\| pDesc->Legacy.Gen.u1DescType)
8156	pDesc->Long.au64[1] = 0;
8157	else if ((uint32_t)(uSel \| X86_SEL_RPL_LDT) + 8 <= (uSel & X86_SEL_LDT ? pCtx->ldtr.u32Limit : pCtx->gdtr.cbGdt))
8158	rcStrict = iemMemFetchSysU64(pIemCpu, &pDesc->Long.au64[1], UINT8_MAX, GCPtrBase + (uSel \| X86_SEL_RPL_LDT) + 1);
8159	else
8160	{
8161	Log(("iemMemFetchSelDesc: system selector %#x is out of bounds\n", uSel));
8162	/** @todo is this the right exception? */
8163	return iemRaiseXcptOrInt(pIemCpu, 0, uXcpt, IEM_XCPT_FLAGS_T_CPU_XCPT \| IEM_XCPT_FLAGS_ERR, uErrorCode, 0);
8164	}
8165	}
8166	return rcStrict;
8167	}
8168
8169
8170	/**
8171	* Fetches a descriptor table entry.
8172	*
8173	* @returns Strict VBox status code.
8174	* @param pIemCpu The IEM per CPU.
8175	* @param pDesc Where to return the descriptor table entry.
8176	* @param uSel The selector which table entry to fetch.
8177	* @param uXcpt The exception to raise on table lookup error.
8178	*/
8179	static VBOXSTRICTRC iemMemFetchSelDesc(PIEMCPU pIemCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt)
8180	{
8181	return iemMemFetchSelDescWithErr(pIemCpu, pDesc, uSel, uXcpt, uSel & X86_SEL_MASK_OFF_RPL);
8182	}
8183
8184
8185	/**
8186	* Fakes a long mode stack selector for SS = 0.
8187	*
8188	* @param pDescSs Where to return the fake stack descriptor.
8189	* @param uDpl The DPL we want.
8190	*/
8191	static void iemMemFakeStackSelDesc(PIEMSELDESC pDescSs, uint32_t uDpl)
8192	{
8193	pDescSs->Long.au64[0] = 0;
8194	pDescSs->Long.au64[1] = 0;
8195	pDescSs->Long.Gen.u4Type = X86_SEL_TYPE_RW_ACC;
8196	pDescSs->Long.Gen.u1DescType = 1; /* 1 = code / data, 0 = system. */
8197	pDescSs->Long.Gen.u2Dpl = uDpl;
8198	pDescSs->Long.Gen.u1Present = 1;
8199	pDescSs->Long.Gen.u1Long = 1;
8200	}
8201
8202
8203	/**
8204	* Marks the selector descriptor as accessed (only non-system descriptors).
8205	*
8206	* This function ASSUMES that iemMemFetchSelDesc has be called previously and
8207	* will therefore skip the limit checks.
8208	*
8209	* @returns Strict VBox status code.
8210	* @param pIemCpu The IEM per CPU.
8211	* @param uSel The selector.
8212	*/
8213	static VBOXSTRICTRC iemMemMarkSelDescAccessed(PIEMCPU pIemCpu, uint16_t uSel)
8214	{
8215	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
8216
8217	/*
8218	* Get the selector table base and calculate the entry address.
8219	*/
8220	RTGCPTR GCPtr = uSel & X86_SEL_LDT
8221	? pCtx->ldtr.u64Base
8222	: pCtx->gdtr.pGdt;
8223	GCPtr += uSel & X86_SEL_MASK;
8224
8225	/*
8226	* ASMAtomicBitSet will assert if the address is misaligned, so do some
8227	* ugly stuff to avoid this. This will make sure it's an atomic access
8228	* as well more or less remove any question about 8-bit or 32-bit accesss.
8229	*/
8230	VBOXSTRICTRC rcStrict;
8231	uint32_t volatile *pu32;
8232	if ((GCPtr & 3) == 0)
8233	{
8234	/* The normal case, map the 32-bit bits around the accessed bit (40). */
8235	GCPtr += 2 + 2;
8236	rcStrict = iemMemMap(pIemCpu, (void **)&pu32, 4, UINT8_MAX, GCPtr, IEM_ACCESS_SYS_RW);
8237	if (rcStrict != VINF_SUCCESS)
8238	return rcStrict;
8239	ASMAtomicBitSet(pu32, 8); /* X86_SEL_TYPE_ACCESSED is 1, but it is preceeded by u8BaseHigh1. */
8240	}
8241	else
8242	{
8243	/* The misaligned GDT/LDT case, map the whole thing. */
8244	rcStrict = iemMemMap(pIemCpu, (void **)&pu32, 8, UINT8_MAX, GCPtr, IEM_ACCESS_SYS_RW);
8245	if (rcStrict != VINF_SUCCESS)
8246	return rcStrict;
8247	switch ((uintptr_t)pu32 & 3)
8248	{
8249	case 0: ASMAtomicBitSet(pu32, 40 + 0 - 0); break;
8250	case 1: ASMAtomicBitSet((uint8_t volatile *)pu32 + 3, 40 + 0 - 24); break;
8251	case 2: ASMAtomicBitSet((uint8_t volatile *)pu32 + 2, 40 + 0 - 16); break;
8252	case 3: ASMAtomicBitSet((uint8_t volatile *)pu32 + 1, 40 + 0 - 8); break;
8253	}
8254	}
8255
8256	return iemMemCommitAndUnmap(pIemCpu, (void *)pu32, IEM_ACCESS_SYS_RW);
8257	}
8258
8259	/** @} */
8260
8261
8262	/*
8263	* Include the C/C++ implementation of instruction.
8264	*/
8265	#include "IEMAllCImpl.cpp.h"
8266
8267
8268
8269	/** @name "Microcode" macros.
8270	*
8271	* The idea is that we should be able to use the same code to interpret
8272	* instructions as well as recompiler instructions. Thus this obfuscation.
8273	*
8274	* @{
8275	*/
8276	#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
8277	#define IEM_MC_END() }
8278	#define IEM_MC_PAUSE() do {} while (0)
8279	#define IEM_MC_CONTINUE() do {} while (0)
8280
8281	/** Internal macro. */
8282	#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
8283	do \
8284	{ \
8285	VBOXSTRICTRC rcStrict2 = a_Expr; \
8286	if (rcStrict2 != VINF_SUCCESS) \
8287	return rcStrict2; \
8288	} while (0)
8289
8290	#define IEM_MC_ADVANCE_RIP() iemRegUpdateRipAndClearRF(pIemCpu)
8291	#define IEM_MC_REL_JMP_S8(a_i8) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS8(pIemCpu, a_i8))
8292	#define IEM_MC_REL_JMP_S16(a_i16) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS16(pIemCpu, a_i16))
8293	#define IEM_MC_REL_JMP_S32(a_i32) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS32(pIemCpu, a_i32))
8294	#define IEM_MC_SET_RIP_U16(a_u16NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pIemCpu), (a_u16NewIP)))
8295	#define IEM_MC_SET_RIP_U32(a_u32NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pIemCpu), (a_u32NewIP)))
8296	#define IEM_MC_SET_RIP_U64(a_u64NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pIemCpu), (a_u64NewIP)))
8297
8298	#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pIemCpu)
8299	#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
8300	do { \
8301	if ((pIemCpu)->CTX_SUFF(pCtx)->cr0 & (X86_CR0_EM \| X86_CR0_TS)) \
8302	return iemRaiseDeviceNotAvailable(pIemCpu); \
8303	} while (0)
8304	#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
8305	do { \
8306	if ((pIemCpu)->CTX_SUFF(pCtx)->fpu.FSW & X86_FSW_ES) \
8307	return iemRaiseMathFault(pIemCpu); \
8308	} while (0)
8309	#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
8310	do { \
8311	if ( (pIemCpu->CTX_SUFF(pCtx)->cr0 & X86_CR0_EM) \
8312	\|\| !(pIemCpu->CTX_SUFF(pCtx)->cr4 & X86_CR4_OSFSXR) \
8313	\|\| !IEM_IS_INTEL_CPUID_FEATURE_PRESENT_EDX(X86_CPUID_FEATURE_EDX_SSE2) ) \
8314	return iemRaiseUndefinedOpcode(pIemCpu); \
8315	if (pIemCpu->CTX_SUFF(pCtx)->cr0 & X86_CR0_TS) \
8316	return iemRaiseDeviceNotAvailable(pIemCpu); \
8317	} while (0)
8318	#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
8319	do { \
8320	if ( ((pIemCpu)->CTX_SUFF(pCtx)->cr0 & X86_CR0_EM) \
8321	\|\| !IEM_IS_INTEL_CPUID_FEATURE_PRESENT_EDX(X86_CPUID_FEATURE_EDX_MMX) ) \
8322	return iemRaiseUndefinedOpcode(pIemCpu); \
8323	if (pIemCpu->CTX_SUFF(pCtx)->cr0 & X86_CR0_TS) \
8324	return iemRaiseDeviceNotAvailable(pIemCpu); \
8325	} while (0)
8326	#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
8327	do { \
8328	if ( ((pIemCpu)->CTX_SUFF(pCtx)->cr0 & X86_CR0_EM) \
8329	\|\| ( !IEM_IS_INTEL_CPUID_FEATURE_PRESENT_EDX(X86_CPUID_FEATURE_EDX_SSE) \
8330	&& !IEM_IS_AMD_CPUID_FEATURE_PRESENT_EDX(X86_CPUID_AMD_FEATURE_EDX_AXMMX) ) ) \
8331	return iemRaiseUndefinedOpcode(pIemCpu); \
8332	if (pIemCpu->CTX_SUFF(pCtx)->cr0 & X86_CR0_TS) \
8333	return iemRaiseDeviceNotAvailable(pIemCpu); \
8334	} while (0)
8335	#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
8336	do { \
8337	if (pIemCpu->uCpl != 0) \
8338	return iemRaiseGeneralProtectionFault0(pIemCpu); \
8339	} while (0)
8340
8341
8342	#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
8343	#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
8344	#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
8345	#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
8346	#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
8347	#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
8348	#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
8349	uint32_t a_Name; \
8350	uint32_t *a_pName = &a_Name
8351	#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
8352	do { (pIemCpu)->CTX_SUFF(pCtx)->eflags.u = (a_EFlags); Assert((pIemCpu)->CTX_SUFF(pCtx)->eflags.u & X86_EFL_1); } while (0)
8353
8354	#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
8355	#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
8356
8357	#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pIemCpu, (a_iGReg))
8358	#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pIemCpu, (a_iGReg))
8359	#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pIemCpu, (a_iGReg))
8360	#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pIemCpu, (a_iGReg))
8361	#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pIemCpu, (a_iGReg))
8362	#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pIemCpu, (a_iGReg))
8363	#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pIemCpu, (a_iGReg))
8364	#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pIemCpu, (a_iGReg))
8365	#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pIemCpu, (a_iGReg))
8366	#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pIemCpu, (a_iGReg))
8367	#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pIemCpu, (a_iGReg))
8368	#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pIemCpu, (a_iGReg))
8369	#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pIemCpu, (a_iGReg))
8370	#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pIemCpu, (a_iGReg))
8371	#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pIemCpu, (a_iGReg))
8372	#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pIemCpu, (a_iGReg))
8373	#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
8374	#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) (a_u16Dst) = iemSRegFetchU16(pIemCpu, (a_iSReg))
8375	#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) (a_u32Dst) = iemSRegFetchU16(pIemCpu, (a_iSReg))
8376	#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) (a_u64Dst) = iemSRegFetchU16(pIemCpu, (a_iSReg))
8377	#define IEM_MC_FETCH_CR0_U16(a_u16Dst) (a_u16Dst) = (uint16_t)(pIemCpu)->CTX_SUFF(pCtx)->cr0
8378	#define IEM_MC_FETCH_CR0_U32(a_u32Dst) (a_u32Dst) = (uint32_t)(pIemCpu)->CTX_SUFF(pCtx)->cr0
8379	#define IEM_MC_FETCH_CR0_U64(a_u64Dst) (a_u64Dst) = (pIemCpu)->CTX_SUFF(pCtx)->cr0
8380	#define IEM_MC_FETCH_LDTR_U16(a_u16Dst) (a_u16Dst) = (pIemCpu)->CTX_SUFF(pCtx)->ldtr.Sel
8381	#define IEM_MC_FETCH_LDTR_U32(a_u32Dst) (a_u32Dst) = (pIemCpu)->CTX_SUFF(pCtx)->ldtr.Sel
8382	#define IEM_MC_FETCH_LDTR_U64(a_u64Dst) (a_u64Dst) = (pIemCpu)->CTX_SUFF(pCtx)->ldtr.Sel
8383	#define IEM_MC_FETCH_TR_U16(a_u16Dst) (a_u16Dst) = (pIemCpu)->CTX_SUFF(pCtx)->tr.Sel
8384	#define IEM_MC_FETCH_TR_U32(a_u32Dst) (a_u32Dst) = (pIemCpu)->CTX_SUFF(pCtx)->tr.Sel
8385	#define IEM_MC_FETCH_TR_U64(a_u64Dst) (a_u64Dst) = (pIemCpu)->CTX_SUFF(pCtx)->tr.Sel
8386	/** @note Not for IOPL or IF testing or modification. */
8387	#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = (pIemCpu)->CTX_SUFF(pCtx)->eflags.u
8388	#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)(pIemCpu)->CTX_SUFF(pCtx)->eflags.u
8389	#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pIemCpu->CTX_SUFF(pCtx)->fpu.FSW
8390	#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pIemCpu->CTX_SUFF(pCtx)->fpu.FCW
8391
8392	#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8(pIemCpu, (a_iGReg)) = (a_u8Value)
8393	#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) (uint16_t )iemGRegRef(pIemCpu, (a_iGReg)) = (a_u16Value)
8394	#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) (uint64_t )iemGRegRef(pIemCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
8395	#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) (uint64_t )iemGRegRef(pIemCpu, (a_iGReg)) = (a_u64Value)
8396	#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
8397	#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
8398	#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
8399	#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
8400	#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) (uint64_t )iemGRegRef(pIemCpu, (a_iGReg)) &= UINT32_MAX
8401	#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
8402	#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
8403	do { pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
8404
8405	#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8(pIemCpu, (a_iGReg))
8406	#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = (uint16_t *)iemGRegRef(pIemCpu, (a_iGReg))
8407	/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
8408	* Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
8409	#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = (uint32_t *)iemGRegRef(pIemCpu, (a_iGReg))
8410	#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = (uint64_t *)iemGRegRef(pIemCpu, (a_iGReg))
8411	/** @note Not for IOPL or IF testing or modification. */
8412	#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &(pIemCpu)->CTX_SUFF(pCtx)->eflags.u
8413
8414	#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) (uint8_t )iemGRegRef(pIemCpu, (a_iGReg)) += (a_u8Value)
8415	#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) (uint16_t )iemGRegRef(pIemCpu, (a_iGReg)) += (a_u16Value)
8416	#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
8417	do { \
8418	uint32_t pu32Reg = (uint32_t )iemGRegRef(pIemCpu, (a_iGReg)); \
8419	*pu32Reg += (a_u32Value); \
8420	pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
8421	} while (0)
8422	#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) (uint64_t )iemGRegRef(pIemCpu, (a_iGReg)) += (a_u64Value)
8423
8424	#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) (uint8_t )iemGRegRef(pIemCpu, (a_iGReg)) -= (a_u8Value)
8425	#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) (uint16_t )iemGRegRef(pIemCpu, (a_iGReg)) -= (a_u16Value)
8426	#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
8427	do { \
8428	uint32_t pu32Reg = (uint32_t )iemGRegRef(pIemCpu, (a_iGReg)); \
8429	*pu32Reg -= (a_u32Value); \
8430	pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
8431	} while (0)
8432	#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) (uint64_t )iemGRegRef(pIemCpu, (a_iGReg)) -= (a_u64Value)
8433
8434	#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pIemCpu, (a_iGReg)); } while (0)
8435	#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pIemCpu, (a_iGReg)); } while (0)
8436	#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pIemCpu, (a_iGReg)); } while (0)
8437	#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pIemCpu, (a_iGReg)); } while (0)
8438	#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
8439	#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
8440	#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
8441
8442	#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
8443	#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
8444	#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
8445	#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
8446
8447	#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
8448	#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
8449	#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
8450
8451	#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) \|= (a_u8Mask); } while (0)
8452	#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) \|= (a_u32Mask); } while (0)
8453
8454	#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
8455	#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
8456	#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
8457
8458	#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
8459	#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
8460	#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
8461
8462	#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
8463
8464	#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) \|= (a_u32Mask); } while (0)
8465
8466	#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) (uint8_t )iemGRegRef(pIemCpu, (a_iGReg)) &= (a_u8Value)
8467	#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) (uint16_t )iemGRegRef(pIemCpu, (a_iGReg)) &= (a_u16Value)
8468	#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
8469	do { \
8470	uint32_t pu32Reg = (uint32_t )iemGRegRef(pIemCpu, (a_iGReg)); \
8471	*pu32Reg &= (a_u32Value); \
8472	pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
8473	} while (0)
8474	#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) (uint64_t )iemGRegRef(pIemCpu, (a_iGReg)) &= (a_u64Value)
8475
8476	#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) (uint8_t )iemGRegRef(pIemCpu, (a_iGReg)) \|= (a_u8Value)
8477	#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) (uint16_t )iemGRegRef(pIemCpu, (a_iGReg)) \|= (a_u16Value)
8478	#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
8479	do { \
8480	uint32_t pu32Reg = (uint32_t )iemGRegRef(pIemCpu, (a_iGReg)); \
8481	*pu32Reg \|= (a_u32Value); \
8482	pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
8483	} while (0)
8484	#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) (uint64_t )iemGRegRef(pIemCpu, (a_iGReg)) \|= (a_u64Value)
8485
8486
8487	/** @note Not for IOPL or IF modification. */
8488	#define IEM_MC_SET_EFL_BIT(a_fBit) do { (pIemCpu)->CTX_SUFF(pCtx)->eflags.u \|= (a_fBit); } while (0)
8489	/** @note Not for IOPL or IF modification. */
8490	#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { (pIemCpu)->CTX_SUFF(pCtx)->eflags.u &= ~(a_fBit); } while (0)
8491	/** @note Not for IOPL or IF modification. */
8492	#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { (pIemCpu)->CTX_SUFF(pCtx)->eflags.u ^= (a_fBit); } while (0)
8493
8494	#define IEM_MC_CLEAR_FSW_EX() do { (pIemCpu)->CTX_SUFF(pCtx)->fpu.FSW &= X86_FSW_C_MASK \| X86_FSW_TOP_MASK; } while (0)
8495
8496
8497	#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
8498	do { (a_u64Value) = pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].mmx; } while (0)
8499	#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
8500	do { (a_u32Value) = pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].au32[0]; } while (0)
8501	#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) \
8502	do { pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].mmx = (a_u64Value); } while (0)
8503	#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) \
8504	do { pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); } while (0)
8505	#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) \
8506	(a_pu64Dst) = (&pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].mmx)
8507	#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
8508	(a_pu64Dst) = ((uint64_t const *)&pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].mmx)
8509	#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
8510	(a_pu32Dst) = ((uint32_t const *)&pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].mmx)
8511
8512	#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
8513	do { (a_u128Value) = pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].xmm; } while (0)
8514	#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
8515	do { (a_u64Value) = pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au64[0]; } while (0)
8516	#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
8517	do { (a_u32Value) = pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au32[0]; } while (0)
8518	#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
8519	do { pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].xmm = (a_u128Value); } while (0)
8520	#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
8521	do { pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
8522	pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au64[1] = 0; \
8523	} while (0)
8524	#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
8525	do { pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
8526	pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au64[1] = 0; \
8527	} while (0)
8528	#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
8529	(a_pu128Dst) = (&pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].xmm)
8530	#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
8531	(a_pu128Dst) = ((uint128_t const *)&pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].xmm)
8532	#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
8533	(a_pu64Dst) = ((uint64_t const *)&pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au64[0])
8534
8535	#define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
8536	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pIemCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
8537	#define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
8538	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pIemCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
8539	#define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
8540	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pIemCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
8541
8542	#define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
8543	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pIemCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
8544	#define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
8545	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pIemCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
8546	#define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
8547	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pIemCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
8548
8549	#define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
8550	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pIemCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
8551	#define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
8552	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pIemCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
8553	#define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
8554	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pIemCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
8555
8556	#define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
8557	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pIemCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
8558
8559	#define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
8560	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pIemCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
8561	#define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
8562	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pIemCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
8563	#define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
8564	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pIemCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
8565	#define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
8566	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pIemCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
8567
8568	#define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
8569	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pIemCpu, &(a_r32Dst).u32, (a_iSeg), (a_GCPtrMem)))
8570	#define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
8571	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pIemCpu, &(a_r64Dst).au64[0], (a_iSeg), (a_GCPtrMem)))
8572	#define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
8573	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pIemCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
8574
8575	#define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
8576	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pIemCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
8577	#define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
8578	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pIemCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
8579
8580
8581
8582	#define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
8583	do { \
8584	uint8_t u8Tmp; \
8585	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pIemCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
8586	(a_u16Dst) = u8Tmp; \
8587	} while (0)
8588	#define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
8589	do { \
8590	uint8_t u8Tmp; \
8591	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pIemCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
8592	(a_u32Dst) = u8Tmp; \
8593	} while (0)
8594	#define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
8595	do { \
8596	uint8_t u8Tmp; \
8597	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pIemCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
8598	(a_u64Dst) = u8Tmp; \
8599	} while (0)
8600	#define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
8601	do { \
8602	uint16_t u16Tmp; \
8603	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pIemCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
8604	(a_u32Dst) = u16Tmp; \
8605	} while (0)
8606	#define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
8607	do { \
8608	uint16_t u16Tmp; \
8609	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pIemCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
8610	(a_u64Dst) = u16Tmp; \
8611	} while (0)
8612	#define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
8613	do { \
8614	uint32_t u32Tmp; \
8615	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pIemCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
8616	(a_u64Dst) = u32Tmp; \
8617	} while (0)
8618
8619	#define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
8620	do { \
8621	uint8_t u8Tmp; \
8622	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pIemCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
8623	(a_u16Dst) = (int8_t)u8Tmp; \
8624	} while (0)
8625	#define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
8626	do { \
8627	uint8_t u8Tmp; \
8628	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pIemCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
8629	(a_u32Dst) = (int8_t)u8Tmp; \
8630	} while (0)
8631	#define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
8632	do { \
8633	uint8_t u8Tmp; \
8634	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pIemCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
8635	(a_u64Dst) = (int8_t)u8Tmp; \
8636	} while (0)
8637	#define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
8638	do { \
8639	uint16_t u16Tmp; \
8640	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pIemCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
8641	(a_u32Dst) = (int16_t)u16Tmp; \
8642	} while (0)
8643	#define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
8644	do { \
8645	uint16_t u16Tmp; \
8646	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pIemCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
8647	(a_u64Dst) = (int16_t)u16Tmp; \
8648	} while (0)
8649	#define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
8650	do { \
8651	uint32_t u32Tmp; \
8652	IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pIemCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
8653	(a_u64Dst) = (int32_t)u32Tmp; \
8654	} while (0)
8655
8656	#define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
8657	IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pIemCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
8658	#define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
8659	IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pIemCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
8660	#define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
8661	IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pIemCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
8662	#define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
8663	IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pIemCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
8664
8665	#define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
8666	IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pIemCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
8667	#define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
8668	IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pIemCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
8669	#define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
8670	IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pIemCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
8671	#define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
8672	IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pIemCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
8673
8674	#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
8675	#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
8676	#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
8677	#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
8678	#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u32 = UINT32_C(0xffc00000)
8679	#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->au64[0] = UINT64_C(0xfff8000000000000)
8680	#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
8681	do { \
8682	(a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
8683	(a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
8684	} while (0)
8685
8686	#define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
8687	IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pIemCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
8688	#define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
8689	IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pIemCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
8690
8691
8692	#define IEM_MC_PUSH_U16(a_u16Value) \
8693	IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pIemCpu, (a_u16Value)))
8694	#define IEM_MC_PUSH_U32(a_u32Value) \
8695	IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pIemCpu, (a_u32Value)))
8696	#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
8697	IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pIemCpu, (a_u32Value)))
8698	#define IEM_MC_PUSH_U64(a_u64Value) \
8699	IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pIemCpu, (a_u64Value)))
8700
8701	#define IEM_MC_POP_U16(a_pu16Value) \
8702	IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pIemCpu, (a_pu16Value)))
8703	#define IEM_MC_POP_U32(a_pu32Value) \
8704	IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pIemCpu, (a_pu32Value)))
8705	#define IEM_MC_POP_U64(a_pu64Value) \
8706	IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pIemCpu, (a_pu64Value)))
8707
8708	/** Maps guest memory for direct or bounce buffered access.
8709	* The purpose is to pass it to an operand implementation, thus the a_iArg.
8710	* @remarks May return.
8711	*/
8712	#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
8713	IEM_MC_RETURN_ON_FAILURE(iemMemMap(pIemCpu, (void *)&(a_pMem), sizeof((a_pMem)), (a_iSeg), (a_GCPtrMem), (a_fAccess)))
8714
8715	/** Maps guest memory for direct or bounce buffered access.
8716	* The purpose is to pass it to an operand implementation, thus the a_iArg.
8717	* @remarks May return.
8718	*/
8719	#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_iArg) \
8720	IEM_MC_RETURN_ON_FAILURE(iemMemMap(pIemCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), (a_GCPtrMem), (a_fAccess)))
8721
8722	/** Commits the memory and unmaps the guest memory.
8723	* @remarks May return.
8724	*/
8725	#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
8726	IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pIemCpu, (a_pvMem), (a_fAccess)))
8727
8728	/** Commits the memory and unmaps the guest memory unless the FPU status word
8729	* indicates (@a a_u16FSW) and FPU control word indicates a pending exception
8730	* that would cause FLD not to store.
8731	*
8732	* The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
8733	* store, while \#P will not.
8734	*
8735	* @remarks May in theory return - for now.
8736	*/
8737	#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
8738	do { \
8739	if ( !(a_u16FSW & X86_FSW_ES) \
8740	\|\| !( (a_u16FSW & (X86_FSW_UE \| X86_FSW_OE \| X86_FSW_IE)) \
8741	& ~(pIemCpu->CTX_SUFF(pCtx)->fpu.FCW & X86_FCW_MASK_ALL) ) ) \
8742	IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pIemCpu, (a_pvMem), (a_fAccess))); \
8743	} while (0)
8744
8745	/** Calculate efficient address from R/M. */
8746	#define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
8747	IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pIemCpu, (bRm), (cbImm), &(a_GCPtrEff)))
8748
8749	#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
8750	#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
8751	#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
8752	#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
8753	#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
8754	#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
8755	#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
8756
8757	/**
8758	* Defers the rest of the instruction emulation to a C implementation routine
8759	* and returns, only taking the standard parameters.
8760	*
8761	* @param a_pfnCImpl The pointer to the C routine.
8762	* @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
8763	*/
8764	#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pIemCpu, pIemCpu->offOpcode)
8765
8766	/**
8767	* Defers the rest of instruction emulation to a C implementation routine and
8768	* returns, taking one argument in addition to the standard ones.
8769	*
8770	* @param a_pfnCImpl The pointer to the C routine.
8771	* @param a0 The argument.
8772	*/
8773	#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pIemCpu, pIemCpu->offOpcode, a0)
8774
8775	/**
8776	* Defers the rest of the instruction emulation to a C implementation routine
8777	* and returns, taking two arguments in addition to the standard ones.
8778	*
8779	* @param a_pfnCImpl The pointer to the C routine.
8780	* @param a0 The first extra argument.
8781	* @param a1 The second extra argument.
8782	*/
8783	#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pIemCpu, pIemCpu->offOpcode, a0, a1)
8784
8785	/**
8786	* Defers the rest of the instruction emulation to a C implementation routine
8787	* and returns, taking three arguments in addition to the standard ones.
8788	*
8789	* @param a_pfnCImpl The pointer to the C routine.
8790	* @param a0 The first extra argument.
8791	* @param a1 The second extra argument.
8792	* @param a2 The third extra argument.
8793	*/
8794	#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pIemCpu, pIemCpu->offOpcode, a0, a1, a2)
8795
8796	/**
8797	* Defers the rest of the instruction emulation to a C implementation routine
8798	* and returns, taking four arguments in addition to the standard ones.
8799	*
8800	* @param a_pfnCImpl The pointer to the C routine.
8801	* @param a0 The first extra argument.
8802	* @param a1 The second extra argument.
8803	* @param a2 The third extra argument.
8804	* @param a3 The fourth extra argument.
8805	*/
8806	#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pIemCpu, pIemCpu->offOpcode, a0, a1, a2, a3)
8807
8808	/**
8809	* Defers the rest of the instruction emulation to a C implementation routine
8810	* and returns, taking two arguments in addition to the standard ones.
8811	*
8812	* @param a_pfnCImpl The pointer to the C routine.
8813	* @param a0 The first extra argument.
8814	* @param a1 The second extra argument.
8815	* @param a2 The third extra argument.
8816	* @param a3 The fourth extra argument.
8817	* @param a4 The fifth extra argument.
8818	*/
8819	#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pIemCpu, pIemCpu->offOpcode, a0, a1, a2, a3, a4)
8820
8821	/**
8822	* Defers the entire instruction emulation to a C implementation routine and
8823	* returns, only taking the standard parameters.
8824	*
8825	* This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
8826	*
8827	* @param a_pfnCImpl The pointer to the C routine.
8828	* @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
8829	*/
8830	#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pIemCpu, pIemCpu->offOpcode)
8831
8832	/**
8833	* Defers the entire instruction emulation to a C implementation routine and
8834	* returns, taking one argument in addition to the standard ones.
8835	*
8836	* This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
8837	*
8838	* @param a_pfnCImpl The pointer to the C routine.
8839	* @param a0 The argument.
8840	*/
8841	#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pIemCpu, pIemCpu->offOpcode, a0)
8842
8843	/**
8844	* Defers the entire instruction emulation to a C implementation routine and
8845	* returns, taking two arguments in addition to the standard ones.
8846	*
8847	* This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
8848	*
8849	* @param a_pfnCImpl The pointer to the C routine.
8850	* @param a0 The first extra argument.
8851	* @param a1 The second extra argument.
8852	*/
8853	#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pIemCpu, pIemCpu->offOpcode, a0, a1)
8854
8855	/**
8856	* Defers the entire instruction emulation to a C implementation routine and
8857	* returns, taking three arguments in addition to the standard ones.
8858	*
8859	* This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
8860	*
8861	* @param a_pfnCImpl The pointer to the C routine.
8862	* @param a0 The first extra argument.
8863	* @param a1 The second extra argument.
8864	* @param a2 The third extra argument.
8865	*/
8866	#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pIemCpu, pIemCpu->offOpcode, a0, a1, a2)
8867
8868	/**
8869	* Calls a FPU assembly implementation taking one visible argument.
8870	*
8871	* @param a_pfnAImpl Pointer to the assembly FPU routine.
8872	* @param a0 The first extra argument.
8873	*/
8874	#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
8875	do { \
8876	iemFpuPrepareUsage(pIemCpu); \
8877	a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0)); \
8878	} while (0)
8879
8880	/**
8881	* Calls a FPU assembly implementation taking two visible arguments.
8882	*
8883	* @param a_pfnAImpl Pointer to the assembly FPU routine.
8884	* @param a0 The first extra argument.
8885	* @param a1 The second extra argument.
8886	*/
8887	#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
8888	do { \
8889	iemFpuPrepareUsage(pIemCpu); \
8890	a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0), (a1)); \
8891	} while (0)
8892
8893	/**
8894	* Calls a FPU assembly implementation taking three visible arguments.
8895	*
8896	* @param a_pfnAImpl Pointer to the assembly FPU routine.
8897	* @param a0 The first extra argument.
8898	* @param a1 The second extra argument.
8899	* @param a2 The third extra argument.
8900	*/
8901	#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
8902	do { \
8903	iemFpuPrepareUsage(pIemCpu); \
8904	a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0), (a1), (a2)); \
8905	} while (0)
8906
8907	#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
8908	do { \
8909	(a_FpuData).FSW = (a_FSW); \
8910	(a_FpuData).r80Result = *(a_pr80Value); \
8911	} while (0)
8912
8913	/** Pushes FPU result onto the stack. */
8914	#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
8915	iemFpuPushResult(pIemCpu, &a_FpuData)
8916	/** Pushes FPU result onto the stack and sets the FPUDP. */
8917	#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
8918	iemFpuPushResultWithMemOp(pIemCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
8919
8920	/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
8921	#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
8922	iemFpuPushResultTwo(pIemCpu, &a_FpuDataTwo)
8923
8924	/** Stores FPU result in a stack register. */
8925	#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
8926	iemFpuStoreResult(pIemCpu, &a_FpuData, a_iStReg)
8927	/** Stores FPU result in a stack register and pops the stack. */
8928	#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
8929	iemFpuStoreResultThenPop(pIemCpu, &a_FpuData, a_iStReg)
8930	/** Stores FPU result in a stack register and sets the FPUDP. */
8931	#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
8932	iemFpuStoreResultWithMemOp(pIemCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
8933	/** Stores FPU result in a stack register, sets the FPUDP, and pops the
8934	* stack. */
8935	#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
8936	iemFpuStoreResultWithMemOpThenPop(pIemCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
8937
8938	/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
8939	#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
8940	iemFpuUpdateOpcodeAndIp(pIemCpu)
8941	/** Free a stack register (for FFREE and FFREEP). */
8942	#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
8943	iemFpuStackFree(pIemCpu, a_iStReg)
8944	/** Increment the FPU stack pointer. */
8945	#define IEM_MC_FPU_STACK_INC_TOP() \
8946	iemFpuStackIncTop(pIemCpu)
8947	/** Decrement the FPU stack pointer. */
8948	#define IEM_MC_FPU_STACK_DEC_TOP() \
8949	iemFpuStackDecTop(pIemCpu)
8950
8951	/** Updates the FSW, FOP, FPUIP, and FPUCS. */
8952	#define IEM_MC_UPDATE_FSW(a_u16FSW) \
8953	iemFpuUpdateFSW(pIemCpu, a_u16FSW)
8954	/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
8955	#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
8956	iemFpuUpdateFSW(pIemCpu, a_u16FSW)
8957	/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
8958	#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
8959	iemFpuUpdateFSWWithMemOp(pIemCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
8960	/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
8961	#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
8962	iemFpuUpdateFSWThenPop(pIemCpu, a_u16FSW)
8963	/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
8964	* stack. */
8965	#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
8966	iemFpuUpdateFSWWithMemOpThenPop(pIemCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
8967	/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
8968	#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
8969	iemFpuUpdateFSWThenPop(pIemCpu, a_u16FSW)
8970
8971	/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
8972	#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
8973	iemFpuStackUnderflow(pIemCpu, a_iStDst)
8974	/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
8975	* stack. */
8976	#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
8977	iemFpuStackUnderflowThenPop(pIemCpu, a_iStDst)
8978	/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
8979	* FPUDS. */
8980	#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
8981	iemFpuStackUnderflowWithMemOp(pIemCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
8982	/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
8983	* FPUDS. Pops stack. */
8984	#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
8985	iemFpuStackUnderflowWithMemOpThenPop(pIemCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
8986	/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
8987	* stack twice. */
8988	#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
8989	iemFpuStackUnderflowThenPopPop(pIemCpu)
8990	/** Raises a FPU stack underflow exception for an instruction pushing a result
8991	* value onto the stack. Sets FPUIP, FPUCS and FOP. */
8992	#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
8993	iemFpuStackPushUnderflow(pIemCpu)
8994	/** Raises a FPU stack underflow exception for an instruction pushing a result
8995	* value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
8996	#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
8997	iemFpuStackPushUnderflowTwo(pIemCpu)
8998
8999	/** Raises a FPU stack overflow exception as part of a push attempt. Sets
9000	* FPUIP, FPUCS and FOP. */
9001	#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
9002	iemFpuStackPushOverflow(pIemCpu)
9003	/** Raises a FPU stack overflow exception as part of a push attempt. Sets
9004	* FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
9005	#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
9006	iemFpuStackPushOverflowWithMemOp(pIemCpu, a_iEffSeg, a_GCPtrEff)
9007	/** Indicates that we (might) have modified the FPU state. */
9008	#define IEM_MC_USED_FPU() \
9009	CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_FPU_REM)
9010
9011	/**
9012	* Calls a MMX assembly implementation taking two visible arguments.
9013	*
9014	* @param a_pfnAImpl Pointer to the assembly MMX routine.
9015	* @param a0 The first extra argument.
9016	* @param a1 The second extra argument.
9017	*/
9018	#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
9019	do { \
9020	iemFpuPrepareUsage(pIemCpu); \
9021	a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0), (a1)); \
9022	} while (0)
9023
9024	/**
9025	* Calls a MMX assembly implementation taking three visible arguments.
9026	*
9027	* @param a_pfnAImpl Pointer to the assembly MMX routine.
9028	* @param a0 The first extra argument.
9029	* @param a1 The second extra argument.
9030	* @param a2 The third extra argument.
9031	*/
9032	#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
9033	do { \
9034	iemFpuPrepareUsage(pIemCpu); \
9035	a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0), (a1), (a2)); \
9036	} while (0)
9037
9038
9039	/**
9040	* Calls a SSE assembly implementation taking two visible arguments.
9041	*
9042	* @param a_pfnAImpl Pointer to the assembly MMX routine.
9043	* @param a0 The first extra argument.
9044	* @param a1 The second extra argument.
9045	*/
9046	#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
9047	do { \
9048	iemFpuPrepareUsageSse(pIemCpu); \
9049	a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0), (a1)); \
9050	} while (0)
9051
9052	/**
9053	* Calls a SSE assembly implementation taking three visible arguments.
9054	*
9055	* @param a_pfnAImpl Pointer to the assembly MMX routine.
9056	* @param a0 The first extra argument.
9057	* @param a1 The second extra argument.
9058	* @param a2 The third extra argument.
9059	*/
9060	#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
9061	do { \
9062	iemFpuPrepareUsageSse(pIemCpu); \
9063	a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0), (a1), (a2)); \
9064	} while (0)
9065
9066
9067	/** @note Not for IOPL or IF testing. */
9068	#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBit)) {
9069	/** @note Not for IOPL or IF testing. */
9070	#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBit))) {
9071	/** @note Not for IOPL or IF testing. */
9072	#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBits)) {
9073	/** @note Not for IOPL or IF testing. */
9074	#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBits))) {
9075	/** @note Not for IOPL or IF testing. */
9076	#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
9077	if ( !!(pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBit1)) \
9078	!= !!(pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBit2)) ) {
9079	/** @note Not for IOPL or IF testing. */
9080	#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
9081	if ( !!(pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBit1)) \
9082	== !!(pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBit2)) ) {
9083	/** @note Not for IOPL or IF testing. */
9084	#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
9085	if ( (pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBit)) \
9086	\|\| !!(pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBit1)) \
9087	!= !!(pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBit2)) ) {
9088	/** @note Not for IOPL or IF testing. */
9089	#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
9090	if ( !(pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBit)) \
9091	&& !!(pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBit1)) \
9092	== !!(pIemCpu->CTX_SUFF(pCtx)->eflags.u & (a_fBit2)) ) {
9093	#define IEM_MC_IF_CX_IS_NZ() if (pIemCpu->CTX_SUFF(pCtx)->cx != 0) {
9094	#define IEM_MC_IF_ECX_IS_NZ() if (pIemCpu->CTX_SUFF(pCtx)->ecx != 0) {
9095	#define IEM_MC_IF_RCX_IS_NZ() if (pIemCpu->CTX_SUFF(pCtx)->rcx != 0) {
9096	/** @note Not for IOPL or IF testing. */
9097	#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
9098	if ( pIemCpu->CTX_SUFF(pCtx)->cx != 0 \
9099	&& (pIemCpu->CTX_SUFF(pCtx)->eflags.u & a_fBit)) {
9100	/** @note Not for IOPL or IF testing. */
9101	#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
9102	if ( pIemCpu->CTX_SUFF(pCtx)->ecx != 0 \
9103	&& (pIemCpu->CTX_SUFF(pCtx)->eflags.u & a_fBit)) {
9104	/** @note Not for IOPL or IF testing. */
9105	#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
9106	if ( pIemCpu->CTX_SUFF(pCtx)->rcx != 0 \
9107	&& (pIemCpu->CTX_SUFF(pCtx)->eflags.u & a_fBit)) {
9108	/** @note Not for IOPL or IF testing. */
9109	#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
9110	if ( pIemCpu->CTX_SUFF(pCtx)->cx != 0 \
9111	&& !(pIemCpu->CTX_SUFF(pCtx)->eflags.u & a_fBit)) {
9112	/** @note Not for IOPL or IF testing. */
9113	#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
9114	if ( pIemCpu->CTX_SUFF(pCtx)->ecx != 0 \
9115	&& !(pIemCpu->CTX_SUFF(pCtx)->eflags.u & a_fBit)) {
9116	/** @note Not for IOPL or IF testing. */
9117	#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
9118	if ( pIemCpu->CTX_SUFF(pCtx)->rcx != 0 \
9119	&& !(pIemCpu->CTX_SUFF(pCtx)->eflags.u & a_fBit)) {
9120	#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
9121	#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if ((uint64_t )iemGRegRef(pIemCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
9122	#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
9123	if (iemFpuStRegNotEmpty(pIemCpu, (a_iSt)) == VINF_SUCCESS) {
9124	#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
9125	if (iemFpuStRegNotEmpty(pIemCpu, (a_iSt)) != VINF_SUCCESS) {
9126	#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
9127	if (iemFpuStRegNotEmptyRef(pIemCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
9128	#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
9129	if (iemFpu2StRegsNotEmptyRef(pIemCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
9130	#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
9131	if (iemFpu2StRegsNotEmptyRefFirst(pIemCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
9132	#define IEM_MC_IF_FCW_IM() \
9133	if (pIemCpu->CTX_SUFF(pCtx)->fpu.FCW & X86_FCW_IM) {
9134
9135	#define IEM_MC_ELSE() } else {
9136	#define IEM_MC_ENDIF() } do {} while (0)
9137
9138	/** @} */
9139
9140
9141	/** @name Opcode Debug Helpers.
9142	* @{
9143	*/
9144	#ifdef DEBUG
9145	# define IEMOP_MNEMONIC(a_szMnemonic) \
9146	Log4(("decode - %04x:%RGv %s%s [#%u]\n", pIemCpu->CTX_SUFF(pCtx)->cs.Sel, pIemCpu->CTX_SUFF(pCtx)->rip, \
9147	pIemCpu->fPrefixes & IEM_OP_PRF_LOCK ? "lock " : "", a_szMnemonic, pIemCpu->cInstructions))
9148	# define IEMOP_MNEMONIC2(a_szMnemonic, a_szOps) \
9149	Log4(("decode - %04x:%RGv %s%s %s [#%u]\n", pIemCpu->CTX_SUFF(pCtx)->cs.Sel, pIemCpu->CTX_SUFF(pCtx)->rip, \
9150	pIemCpu->fPrefixes & IEM_OP_PRF_LOCK ? "lock " : "", a_szMnemonic, a_szOps, pIemCpu->cInstructions))
9151	#else
9152	# define IEMOP_MNEMONIC(a_szMnemonic) do { } while (0)
9153	# define IEMOP_MNEMONIC2(a_szMnemonic, a_szOps) do { } while (0)
9154	#endif
9155
9156	/** @} */
9157
9158
9159	/** @name Opcode Helpers.
9160	* @{
9161	*/
9162
9163	/** The instruction raises an \#UD in real and V8086 mode. */
9164	#define IEMOP_HLP_NO_REAL_OR_V86_MODE() \
9165	do \
9166	{ \
9167	if (IEM_IS_REAL_OR_V86_MODE(pIemCpu)) \
9168	return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \
9169	} while (0)
9170
9171	/** The instruction allows no lock prefixing (in this encoding), throw #UD if
9172	* lock prefixed.
9173	* @deprecated IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX */
9174	#define IEMOP_HLP_NO_LOCK_PREFIX() \
9175	do \
9176	{ \
9177	if (pIemCpu->fPrefixes & IEM_OP_PRF_LOCK) \
9178	return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \
9179	} while (0)
9180
9181	/** The instruction is not available in 64-bit mode, throw #UD if we're in
9182	* 64-bit mode. */
9183	#define IEMOP_HLP_NO_64BIT() \
9184	do \
9185	{ \
9186	if (pIemCpu->enmCpuMode == IEMMODE_64BIT) \
9187	return IEMOP_RAISE_INVALID_OPCODE(); \
9188	} while (0)
9189
9190	/** The instruction is only available in 64-bit mode, throw #UD if we're not in
9191	* 64-bit mode. */
9192	#define IEMOP_HLP_ONLY_64BIT() \
9193	do \
9194	{ \
9195	if (pIemCpu->enmCpuMode != IEMMODE_64BIT) \
9196	return IEMOP_RAISE_INVALID_OPCODE(); \
9197	} while (0)
9198
9199	/** The instruction defaults to 64-bit operand size if 64-bit mode. */
9200	#define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE() \
9201	do \
9202	{ \
9203	if (pIemCpu->enmCpuMode == IEMMODE_64BIT) \
9204	iemRecalEffOpSize64Default(pIemCpu); \
9205	} while (0)
9206
9207	/** The instruction has 64-bit operand size if 64-bit mode. */
9208	#define IEMOP_HLP_64BIT_OP_SIZE() \
9209	do \
9210	{ \
9211	if (pIemCpu->enmCpuMode == IEMMODE_64BIT) \
9212	pIemCpu->enmEffOpSize = pIemCpu->enmDefOpSize = IEMMODE_64BIT; \
9213	} while (0)
9214
9215	/** Only a REX prefix immediately preceeding the first opcode byte takes
9216	* effect. This macro helps ensuring this as well as logging bad guest code. */
9217	#define IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE(a_szPrf) \
9218	do \
9219	{ \
9220	if (RT_UNLIKELY(pIemCpu->fPrefixes & IEM_OP_PRF_REX)) \
9221	{ \
9222	Log5((a_szPrf ": Overriding REX prefix at %RX16! fPrefixes=%#x\n", \
9223	pIemCpu->CTX_SUFF(pCtx)->rip, pIemCpu->fPrefixes)); \
9224	pIemCpu->fPrefixes &= ~IEM_OP_PRF_REX_MASK; \
9225	pIemCpu->uRexB = 0; \
9226	pIemCpu->uRexIndex = 0; \
9227	pIemCpu->uRexReg = 0; \
9228	iemRecalEffOpSize(pIemCpu); \
9229	} \
9230	} while (0)
9231
9232	/**
9233	* Done decoding.
9234	*/
9235	#define IEMOP_HLP_DONE_DECODING() \
9236	do \
9237	{ \
9238	/nothing for now, maybe later... / \
9239	} while (0)
9240
9241	/**
9242	* Done decoding, raise \#UD exception if lock prefix present.
9243	*/
9244	#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX() \
9245	do \
9246	{ \
9247	if (pIemCpu->fPrefixes & IEM_OP_PRF_LOCK) \
9248	return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \
9249	} while (0)
9250	#define IEMOP_HLP_DECODED_NL_1(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_fDisOpType) \
9251	do \
9252	{ \
9253	if (pIemCpu->fPrefixes & IEM_OP_PRF_LOCK) \
9254	{ \
9255	NOREF(a_uDisOpNo); NOREF(a_fIemOpFlags); NOREF(a_uDisParam0); NOREF(a_fDisOpType); \
9256	return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \
9257	} \
9258	} while (0)
9259	#define IEMOP_HLP_DECODED_NL_2(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_uDisParam1, a_fDisOpType) \
9260	do \
9261	{ \
9262	if (pIemCpu->fPrefixes & IEM_OP_PRF_LOCK) \
9263	{ \
9264	NOREF(a_uDisOpNo); NOREF(a_fIemOpFlags); NOREF(a_uDisParam0); NOREF(a_uDisParam1); NOREF(a_fDisOpType); \
9265	return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \
9266	} \
9267	} while (0)
9268
9269
9270	/**
9271	* Calculates the effective address of a ModR/M memory operand.
9272	*
9273	* Meant to be used via IEM_MC_CALC_RM_EFF_ADDR.
9274	*
9275	* @return Strict VBox status code.
9276	* @param pIemCpu The IEM per CPU data.
9277	* @param bRm The ModRM byte.
9278	* @param cbImm The size of any immediate following the
9279	* effective address opcode bytes. Important for
9280	* RIP relative addressing.
9281	* @param pGCPtrEff Where to return the effective address.
9282	*/
9283	static VBOXSTRICTRC iemOpHlpCalcRmEffAddr(PIEMCPU pIemCpu, uint8_t bRm, uint8_t cbImm, PRTGCPTR pGCPtrEff)
9284	{
9285	Log5(("iemOpHlpCalcRmEffAddr: bRm=%#x\n", bRm));
9286	PCCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
9287	#define SET_SS_DEF() \
9288	do \
9289	{ \
9290	if (!(pIemCpu->fPrefixes & IEM_OP_PRF_SEG_MASK)) \
9291	pIemCpu->iEffSeg = X86_SREG_SS; \
9292	} while (0)
9293
9294	if (pIemCpu->enmCpuMode != IEMMODE_64BIT)
9295	{
9296	/** @todo Check the effective address size crap! */
9297	if (pIemCpu->enmEffAddrMode == IEMMODE_16BIT)
9298	{
9299	uint16_t u16EffAddr;
9300
9301	/* Handle the disp16 form with no registers first. */
9302	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 6)
9303	IEM_OPCODE_GET_NEXT_U16(&u16EffAddr);
9304	else
9305	{
9306	/* Get the displacment. */
9307	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
9308	{
9309	case 0: u16EffAddr = 0; break;
9310	case 1: IEM_OPCODE_GET_NEXT_S8_SX_U16(&u16EffAddr); break;
9311	case 2: IEM_OPCODE_GET_NEXT_U16(&u16EffAddr); break;
9312	default: AssertFailedReturn(VERR_INTERNAL_ERROR_2); /* (caller checked for these) */
9313	}
9314
9315	/* Add the base and index registers to the disp. */
9316	switch (bRm & X86_MODRM_RM_MASK)
9317	{
9318	case 0: u16EffAddr += pCtx->bx + pCtx->si; break;
9319	case 1: u16EffAddr += pCtx->bx + pCtx->di; break;
9320	case 2: u16EffAddr += pCtx->bp + pCtx->si; SET_SS_DEF(); break;
9321	case 3: u16EffAddr += pCtx->bp + pCtx->di; SET_SS_DEF(); break;
9322	case 4: u16EffAddr += pCtx->si; break;
9323	case 5: u16EffAddr += pCtx->di; break;
9324	case 6: u16EffAddr += pCtx->bp; SET_SS_DEF(); break;
9325	case 7: u16EffAddr += pCtx->bx; break;
9326	}
9327	}
9328
9329	*pGCPtrEff = u16EffAddr;
9330	}
9331	else
9332	{
9333	Assert(pIemCpu->enmEffAddrMode == IEMMODE_32BIT);
9334	uint32_t u32EffAddr;
9335
9336	/* Handle the disp32 form with no registers first. */
9337	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
9338	IEM_OPCODE_GET_NEXT_U32(&u32EffAddr);
9339	else
9340	{
9341	/* Get the register (or SIB) value. */
9342	switch ((bRm & X86_MODRM_RM_MASK))
9343	{
9344	case 0: u32EffAddr = pCtx->eax; break;
9345	case 1: u32EffAddr = pCtx->ecx; break;
9346	case 2: u32EffAddr = pCtx->edx; break;
9347	case 3: u32EffAddr = pCtx->ebx; break;
9348	case 4: /* SIB */
9349	{
9350	uint8_t bSib; IEM_OPCODE_GET_NEXT_U8(&bSib);
9351
9352	/* Get the index and scale it. */
9353	switch ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
9354	{
9355	case 0: u32EffAddr = pCtx->eax; break;
9356	case 1: u32EffAddr = pCtx->ecx; break;
9357	case 2: u32EffAddr = pCtx->edx; break;
9358	case 3: u32EffAddr = pCtx->ebx; break;
9359	case 4: u32EffAddr = 0; /none / break;
9360	case 5: u32EffAddr = pCtx->ebp; break;
9361	case 6: u32EffAddr = pCtx->esi; break;
9362	case 7: u32EffAddr = pCtx->edi; break;
9363	IEM_NOT_REACHED_DEFAULT_CASE_RET();
9364	}
9365	u32EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
9366
9367	/* add base */
9368	switch (bSib & X86_SIB_BASE_MASK)
9369	{
9370	case 0: u32EffAddr += pCtx->eax; break;
9371	case 1: u32EffAddr += pCtx->ecx; break;
9372	case 2: u32EffAddr += pCtx->edx; break;
9373	case 3: u32EffAddr += pCtx->ebx; break;
9374	case 4: u32EffAddr += pCtx->esp; SET_SS_DEF(); break;
9375	case 5:
9376	if ((bRm & X86_MODRM_MOD_MASK) != 0)
9377	{
9378	u32EffAddr += pCtx->ebp;
9379	SET_SS_DEF();
9380	}
9381	else
9382	{
9383	uint32_t u32Disp;
9384	IEM_OPCODE_GET_NEXT_U32(&u32Disp);
9385	u32EffAddr += u32Disp;
9386	}
9387	break;
9388	case 6: u32EffAddr += pCtx->esi; break;
9389	case 7: u32EffAddr += pCtx->edi; break;
9390	IEM_NOT_REACHED_DEFAULT_CASE_RET();
9391	}
9392	break;
9393	}
9394	case 5: u32EffAddr = pCtx->ebp; SET_SS_DEF(); break;
9395	case 6: u32EffAddr = pCtx->esi; break;
9396	case 7: u32EffAddr = pCtx->edi; break;
9397	IEM_NOT_REACHED_DEFAULT_CASE_RET();
9398	}
9399
9400	/* Get and add the displacement. */
9401	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
9402	{
9403	case 0:
9404	break;
9405	case 1:
9406	{
9407	int8_t i8Disp; IEM_OPCODE_GET_NEXT_S8(&i8Disp);
9408	u32EffAddr += i8Disp;
9409	break;
9410	}
9411	case 2:
9412	{
9413	uint32_t u32Disp; IEM_OPCODE_GET_NEXT_U32(&u32Disp);
9414	u32EffAddr += u32Disp;
9415	break;
9416	}
9417	default:
9418	AssertFailedReturn(VERR_INTERNAL_ERROR_2); /* (caller checked for these) */
9419	}
9420
9421	}
9422	if (pIemCpu->enmEffAddrMode == IEMMODE_32BIT)
9423	*pGCPtrEff = u32EffAddr;
9424	else
9425	{
9426	Assert(pIemCpu->enmEffAddrMode == IEMMODE_16BIT);
9427	*pGCPtrEff = u32EffAddr & UINT16_MAX;
9428	}
9429	}
9430	}
9431	else
9432	{
9433	uint64_t u64EffAddr;
9434
9435	/* Handle the rip+disp32 form with no registers first. */
9436	if ((bRm & (X86_MODRM_MOD_MASK \| X86_MODRM_RM_MASK)) == 5)
9437	{
9438	IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64EffAddr);
9439	u64EffAddr += pCtx->rip + pIemCpu->offOpcode + cbImm;
9440	}
9441	else
9442	{
9443	/* Get the register (or SIB) value. */
9444	switch ((bRm & X86_MODRM_RM_MASK) \| pIemCpu->uRexB)
9445	{
9446	case 0: u64EffAddr = pCtx->rax; break;
9447	case 1: u64EffAddr = pCtx->rcx; break;
9448	case 2: u64EffAddr = pCtx->rdx; break;
9449	case 3: u64EffAddr = pCtx->rbx; break;
9450	case 5: u64EffAddr = pCtx->rbp; SET_SS_DEF(); break;
9451	case 6: u64EffAddr = pCtx->rsi; break;
9452	case 7: u64EffAddr = pCtx->rdi; break;
9453	case 8: u64EffAddr = pCtx->r8; break;
9454	case 9: u64EffAddr = pCtx->r9; break;
9455	case 10: u64EffAddr = pCtx->r10; break;
9456	case 11: u64EffAddr = pCtx->r11; break;
9457	case 13: u64EffAddr = pCtx->r13; break;
9458	case 14: u64EffAddr = pCtx->r14; break;
9459	case 15: u64EffAddr = pCtx->r15; break;
9460	/* SIB */
9461	case 4:
9462	case 12:
9463	{
9464	uint8_t bSib; IEM_OPCODE_GET_NEXT_U8(&bSib);
9465
9466	/* Get the index and scale it. */
9467	switch (((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) \| pIemCpu->uRexIndex)
9468	{
9469	case 0: u64EffAddr = pCtx->rax; break;
9470	case 1: u64EffAddr = pCtx->rcx; break;
9471	case 2: u64EffAddr = pCtx->rdx; break;
9472	case 3: u64EffAddr = pCtx->rbx; break;
9473	case 4: u64EffAddr = 0; /none / break;
9474	case 5: u64EffAddr = pCtx->rbp; break;
9475	case 6: u64EffAddr = pCtx->rsi; break;
9476	case 7: u64EffAddr = pCtx->rdi; break;
9477	case 8: u64EffAddr = pCtx->r8; break;
9478	case 9: u64EffAddr = pCtx->r9; break;
9479	case 10: u64EffAddr = pCtx->r10; break;
9480	case 11: u64EffAddr = pCtx->r11; break;
9481	case 12: u64EffAddr = pCtx->r12; break;
9482	case 13: u64EffAddr = pCtx->r13; break;
9483	case 14: u64EffAddr = pCtx->r14; break;
9484	case 15: u64EffAddr = pCtx->r15; break;
9485	IEM_NOT_REACHED_DEFAULT_CASE_RET();
9486	}
9487	u64EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
9488
9489	/* add base */
9490	switch ((bSib & X86_SIB_BASE_MASK) \| pIemCpu->uRexB)
9491	{
9492	case 0: u64EffAddr += pCtx->rax; break;
9493	case 1: u64EffAddr += pCtx->rcx; break;
9494	case 2: u64EffAddr += pCtx->rdx; break;
9495	case 3: u64EffAddr += pCtx->rbx; break;
9496	case 4: u64EffAddr += pCtx->rsp; SET_SS_DEF(); break;
9497	case 6: u64EffAddr += pCtx->rsi; break;
9498	case 7: u64EffAddr += pCtx->rdi; break;
9499	case 8: u64EffAddr += pCtx->r8; break;
9500	case 9: u64EffAddr += pCtx->r9; break;
9501	case 10: u64EffAddr += pCtx->r10; break;
9502	case 11: u64EffAddr += pCtx->r11; break;
9503	case 12: u64EffAddr += pCtx->r12; break;
9504	case 14: u64EffAddr += pCtx->r14; break;
9505	case 15: u64EffAddr += pCtx->r15; break;
9506	/* complicated encodings */
9507	case 5:
9508	case 13:
9509	if ((bRm & X86_MODRM_MOD_MASK) != 0)
9510	{
9511	if (!pIemCpu->uRexB)
9512	{
9513	u64EffAddr += pCtx->rbp;
9514	SET_SS_DEF();
9515	}
9516	else
9517	u64EffAddr += pCtx->r13;
9518	}
9519	else
9520	{
9521	uint32_t u32Disp;
9522	IEM_OPCODE_GET_NEXT_U32(&u32Disp);
9523	u64EffAddr += (int32_t)u32Disp;
9524	}
9525	break;
9526	IEM_NOT_REACHED_DEFAULT_CASE_RET();
9527	}
9528	break;
9529	}
9530	IEM_NOT_REACHED_DEFAULT_CASE_RET();
9531	}
9532
9533	/* Get and add the displacement. */
9534	switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
9535	{
9536	case 0:
9537	break;
9538	case 1:
9539	{
9540	int8_t i8Disp;
9541	IEM_OPCODE_GET_NEXT_S8(&i8Disp);
9542	u64EffAddr += i8Disp;
9543	break;
9544	}
9545	case 2:
9546	{
9547	uint32_t u32Disp;
9548	IEM_OPCODE_GET_NEXT_U32(&u32Disp);
9549	u64EffAddr += (int32_t)u32Disp;
9550	break;
9551	}
9552	IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* (caller checked for these) */
9553	}
9554
9555	}
9556
9557	if (pIemCpu->enmEffAddrMode == IEMMODE_64BIT)
9558	*pGCPtrEff = u64EffAddr;
9559	else
9560	{
9561	Assert(pIemCpu->enmEffAddrMode == IEMMODE_32BIT);
9562	*pGCPtrEff = u64EffAddr & UINT32_MAX;
9563	}
9564	}
9565
9566	Log5(("iemOpHlpCalcRmEffAddr: EffAddr=%#010RGv\n", *pGCPtrEff));
9567	return VINF_SUCCESS;
9568	}
9569
9570	/** @} */
9571
9572
9573
9574	/*
9575	* Include the instructions
9576	*/
9577	#include "IEMAllInstructions.cpp.h"
9578
9579
9580
9581
9582	#if defined(IEM_VERIFICATION_MODE_FULL) && defined(IN_RING3)
9583
9584	/**
9585	* Sets up execution verification mode.
9586	*/
9587	static void iemExecVerificationModeSetup(PIEMCPU pIemCpu)
9588	{
9589	PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu);
9590	PCPUMCTX pOrgCtx = pIemCpu->CTX_SUFF(pCtx);
9591
9592	/*
9593	* Always note down the address of the current instruction.
9594	*/
9595	pIemCpu->uOldCs = pOrgCtx->cs.Sel;
9596	pIemCpu->uOldRip = pOrgCtx->rip;
9597
9598	/*
9599	* Enable verification and/or logging.
9600	*/
9601	bool fNewNoRem = !LogIs6Enabled(); /* logging triggers the no-rem/rem verification stuff */;
9602	if ( fNewNoRem
9603	&& ( 0
9604	#if 0 /* auto enable on first paged protected mode interrupt */
9605	\|\| ( pOrgCtx->eflags.Bits.u1IF
9606	&& (pOrgCtx->cr0 & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG)
9607	&& TRPMHasTrap(pVCpu)
9608	&& EMGetInhibitInterruptsPC(pVCpu) != pOrgCtx->rip) )
9609	#endif
9610	#if 0
9611	\|\| ( pOrgCtx->cs == 0x10
9612	&& ( pOrgCtx->rip == 0x90119e3e
9613	\|\| pOrgCtx->rip == 0x901d9810)
9614	#endif
9615	#if 0 /* Auto enable DSL - FPU stuff. */
9616	\|\| ( pOrgCtx->cs == 0x10
9617	&& (// pOrgCtx->rip == 0xc02ec07f
9618	//\|\| pOrgCtx->rip == 0xc02ec082
9619	//\|\| pOrgCtx->rip == 0xc02ec0c9
9620	0
9621	\|\| pOrgCtx->rip == 0x0c010e7c4 /* fxsave */ ) )
9622	#endif
9623	#if 0 /* Auto enable DSL - fstp st0 stuff. */
9624	\|\| (pOrgCtx->cs.Sel == 0x23 pOrgCtx->rip == 0x804aff7)
9625	#endif
9626	#if 0
9627	\|\| pOrgCtx->rip == 0x9022bb3a
9628	#endif
9629	#if 0
9630	\|\| (pOrgCtx->cs.Sel == 0x58 && pOrgCtx->rip == 0x3be) /* NT4SP1 sidt/sgdt in early loader code */
9631	#endif
9632	#if 0
9633	\|\| (pOrgCtx->cs.Sel == 8 && pOrgCtx->rip == 0x8013ec28) /* NT4SP1 first str (early boot) */
9634	\|\| (pOrgCtx->cs.Sel == 8 && pOrgCtx->rip == 0x80119e3f) /* NT4SP1 second str (early boot) */
9635	#endif
9636	#if 0 /* NT4SP1 - later on the blue screen, things goes wrong... */
9637	\|\| (pOrgCtx->cs.Sel == 8 && pOrgCtx->rip == 0x8010a5df)
9638	\|\| (pOrgCtx->cs.Sel == 8 && pOrgCtx->rip == 0x8013a7c4)
9639	\|\| (pOrgCtx->cs.Sel == 8 && pOrgCtx->rip == 0x8013a7d2)
9640	#endif
9641	#if 0 /* NT4SP1 - xadd early boot. */
9642	\|\| (pOrgCtx->cs.Sel == 8 && pOrgCtx->rip == 0x8019cf0f)
9643	#endif
9644	#if 0 /* NT4SP1 - wrmsr (intel MSR). */
9645	\|\| (pOrgCtx->cs.Sel == 8 && pOrgCtx->rip == 0x8011a6d4)
9646	#endif
9647	#if 0 /* NT4SP1 - cmpxchg (AMD). */
9648	\|\| (pOrgCtx->cs.Sel == 8 && pOrgCtx->rip == 0x801684c1)
9649	#endif
9650	#if 0 /* NT4SP1 - fnstsw + 2 (AMD). */
9651	\|\| (pOrgCtx->cs.Sel == 8 && pOrgCtx->rip == 0x801c6b88+2)
9652	#endif
9653	#if 0 /* NT4SP1 - iret to v8086 -- too generic a place? (N/A with GAs installed) */
9654	\|\| (pOrgCtx->cs.Sel == 8 && pOrgCtx->rip == 0x8013bd5d)
9655
9656	#endif
9657	#if 0 /* NT4SP1 - iret to v8086 (executing edlin) */
9658	\|\| (pOrgCtx->cs.Sel == 8 && pOrgCtx->rip == 0x8013b609)
9659
9660	#endif
9661	#if 0 /* NT4SP1 - frstor [ecx] */
9662	\|\| (pOrgCtx->cs.Sel == 8 && pOrgCtx->rip == 0x8013d11f)
9663	#endif
9664	#if 0 /* xxxxxx - All long mode code. */
9665	\|\| (pOrgCtx->msrEFER & MSR_K6_EFER_LMA)
9666	#endif
9667	#if 0 /* rep movsq linux 3.7 64-bit boot. */
9668	\|\| (pOrgCtx->rip == 0x0000000000100241)
9669	#endif
9670	#if 0 /* linux 3.7 64-bit boot - '000000000215e240'. */
9671	\|\| (pOrgCtx->rip == 0x000000000215e240)
9672	#endif
9673	#if 0 /* DOS's size-overridden iret to v8086. */
9674	\|\| (pOrgCtx->rip == 0x427 && pOrgCtx->cs.Sel == 0xb8)
9675	#endif
9676	)
9677	)
9678	{
9679	RTLogGroupSettings(NULL, "iem.eo.l6.l2");
9680	RTLogFlags(NULL, "enabled");
9681	fNewNoRem = false;
9682	}
9683	if (fNewNoRem != pIemCpu->fNoRem)
9684	{
9685	pIemCpu->fNoRem = fNewNoRem;
9686	if (!fNewNoRem)
9687	{
9688	LogAlways(("Enabling verification mode!\n"));
9689	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
9690	}
9691	else
9692	LogAlways(("Disabling verification mode!\n"));
9693	}
9694
9695	/*
9696	* Switch state.
9697	*/
9698	if (IEM_VERIFICATION_ENABLED(pIemCpu))
9699	{
9700	static CPUMCTX s_DebugCtx; /* Ugly! */
9701
9702	s_DebugCtx = *pOrgCtx;
9703	pIemCpu->CTX_SUFF(pCtx) = &s_DebugCtx;
9704	}
9705
9706	/*
9707	* See if there is an interrupt pending in TRPM and inject it if we can.
9708	*/
9709	pIemCpu->uInjectCpl = UINT8_MAX;
9710	if ( pOrgCtx->eflags.Bits.u1IF
9711	&& TRPMHasTrap(pVCpu)
9712	&& EMGetInhibitInterruptsPC(pVCpu) != pOrgCtx->rip)
9713	{
9714	uint8_t u8TrapNo;
9715	TRPMEVENT enmType;
9716	RTGCUINT uErrCode;
9717	RTGCPTR uCr2;
9718	int rc2 = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrCode, &uCr2, NULL /* pu8InstLen */); AssertRC(rc2);
9719	IEMInjectTrap(pVCpu, u8TrapNo, enmType, (uint16_t)uErrCode, uCr2, 0 /* cbInstr */);
9720	if (!IEM_VERIFICATION_ENABLED(pIemCpu))
9721	TRPMResetTrap(pVCpu);
9722	pIemCpu->uInjectCpl = pIemCpu->uCpl;
9723	}
9724
9725	/*
9726	* Reset the counters.
9727	*/
9728	pIemCpu->cIOReads = 0;
9729	pIemCpu->cIOWrites = 0;
9730	pIemCpu->fIgnoreRaxRdx = false;
9731	pIemCpu->fOverlappingMovs = false;
9732	pIemCpu->fProblematicMemory = false;
9733	pIemCpu->fUndefinedEFlags = 0;
9734
9735	if (IEM_VERIFICATION_ENABLED(pIemCpu))
9736	{
9737	/*
9738	* Free all verification records.
9739	*/
9740	PIEMVERIFYEVTREC pEvtRec = pIemCpu->pIemEvtRecHead;
9741	pIemCpu->pIemEvtRecHead = NULL;
9742	pIemCpu->ppIemEvtRecNext = &pIemCpu->pIemEvtRecHead;
9743	do
9744	{
9745	while (pEvtRec)
9746	{
9747	PIEMVERIFYEVTREC pNext = pEvtRec->pNext;
9748	pEvtRec->pNext = pIemCpu->pFreeEvtRec;
9749	pIemCpu->pFreeEvtRec = pEvtRec;
9750	pEvtRec = pNext;
9751	}
9752	pEvtRec = pIemCpu->pOtherEvtRecHead;
9753	pIemCpu->pOtherEvtRecHead = NULL;
9754	pIemCpu->ppOtherEvtRecNext = &pIemCpu->pOtherEvtRecHead;
9755	} while (pEvtRec);
9756	}
9757	}
9758
9759
9760	/**
9761	* Allocate an event record.
9762	* @returns Pointer to a record.
9763	*/
9764	static PIEMVERIFYEVTREC iemVerifyAllocRecord(PIEMCPU pIemCpu)
9765	{
9766	if (!IEM_VERIFICATION_ENABLED(pIemCpu))
9767	return NULL;
9768
9769	PIEMVERIFYEVTREC pEvtRec = pIemCpu->pFreeEvtRec;
9770	if (pEvtRec)
9771	pIemCpu->pFreeEvtRec = pEvtRec->pNext;
9772	else
9773	{
9774	if (!pIemCpu->ppIemEvtRecNext)
9775	return NULL; /* Too early (fake PCIBIOS), ignore notification. */
9776
9777	pEvtRec = (PIEMVERIFYEVTREC)MMR3HeapAlloc(IEMCPU_TO_VM(pIemCpu), MM_TAG_EM /* lazy bird/, sizeof(pEvtRec));
9778	if (!pEvtRec)
9779	return NULL;
9780	}
9781	pEvtRec->enmEvent = IEMVERIFYEVENT_INVALID;
9782	pEvtRec->pNext = NULL;
9783	return pEvtRec;
9784	}
9785
9786
9787	/**
9788	* IOMMMIORead notification.
9789	*/
9790	VMM_INT_DECL(void) IEMNotifyMMIORead(PVM pVM, RTGCPHYS GCPhys, size_t cbValue)
9791	{
9792	PVMCPU pVCpu = VMMGetCpu(pVM);
9793	if (!pVCpu)
9794	return;
9795	PIEMCPU pIemCpu = &pVCpu->iem.s;
9796	PIEMVERIFYEVTREC pEvtRec = iemVerifyAllocRecord(pIemCpu);
9797	if (!pEvtRec)
9798	return;
9799	pEvtRec->enmEvent = IEMVERIFYEVENT_RAM_READ;
9800	pEvtRec->u.RamRead.GCPhys = GCPhys;
9801	pEvtRec->u.RamRead.cb = (uint32_t)cbValue;
9802	pEvtRec->pNext = *pIemCpu->ppOtherEvtRecNext;
9803	*pIemCpu->ppOtherEvtRecNext = pEvtRec;
9804	}
9805
9806
9807	/**
9808	* IOMMMIOWrite notification.
9809	*/
9810	VMM_INT_DECL(void) IEMNotifyMMIOWrite(PVM pVM, RTGCPHYS GCPhys, uint32_t u32Value, size_t cbValue)
9811	{
9812	PVMCPU pVCpu = VMMGetCpu(pVM);
9813	if (!pVCpu)
9814	return;
9815	PIEMCPU pIemCpu = &pVCpu->iem.s;
9816	PIEMVERIFYEVTREC pEvtRec = iemVerifyAllocRecord(pIemCpu);
9817	if (!pEvtRec)
9818	return;
9819	pEvtRec->enmEvent = IEMVERIFYEVENT_RAM_WRITE;
9820	pEvtRec->u.RamWrite.GCPhys = GCPhys;
9821	pEvtRec->u.RamWrite.cb = (uint32_t)cbValue;
9822	pEvtRec->u.RamWrite.ab[0] = RT_BYTE1(u32Value);
9823	pEvtRec->u.RamWrite.ab[1] = RT_BYTE2(u32Value);
9824	pEvtRec->u.RamWrite.ab[2] = RT_BYTE3(u32Value);
9825	pEvtRec->u.RamWrite.ab[3] = RT_BYTE4(u32Value);
9826	pEvtRec->pNext = *pIemCpu->ppOtherEvtRecNext;
9827	*pIemCpu->ppOtherEvtRecNext = pEvtRec;
9828	}
9829
9830
9831	/**
9832	* IOMIOPortRead notification.
9833	*/
9834	VMM_INT_DECL(void) IEMNotifyIOPortRead(PVM pVM, RTIOPORT Port, size_t cbValue)
9835	{
9836	PVMCPU pVCpu = VMMGetCpu(pVM);
9837	if (!pVCpu)
9838	return;
9839	PIEMCPU pIemCpu = &pVCpu->iem.s;
9840	PIEMVERIFYEVTREC pEvtRec = iemVerifyAllocRecord(pIemCpu);
9841	if (!pEvtRec)
9842	return;
9843	pEvtRec->enmEvent = IEMVERIFYEVENT_IOPORT_READ;
9844	pEvtRec->u.IOPortRead.Port = Port;
9845	pEvtRec->u.IOPortRead.cbValue = (uint32_t)cbValue;
9846	pEvtRec->pNext = *pIemCpu->ppOtherEvtRecNext;
9847	*pIemCpu->ppOtherEvtRecNext = pEvtRec;
9848	}
9849
9850	/**
9851	* IOMIOPortWrite notification.
9852	*/
9853	VMM_INT_DECL(void) IEMNotifyIOPortWrite(PVM pVM, RTIOPORT Port, uint32_t u32Value, size_t cbValue)
9854	{
9855	PVMCPU pVCpu = VMMGetCpu(pVM);
9856	if (!pVCpu)
9857	return;
9858	PIEMCPU pIemCpu = &pVCpu->iem.s;
9859	PIEMVERIFYEVTREC pEvtRec = iemVerifyAllocRecord(pIemCpu);
9860	if (!pEvtRec)
9861	return;
9862	pEvtRec->enmEvent = IEMVERIFYEVENT_IOPORT_WRITE;
9863	pEvtRec->u.IOPortWrite.Port = Port;
9864	pEvtRec->u.IOPortWrite.cbValue = (uint32_t)cbValue;
9865	pEvtRec->u.IOPortWrite.u32Value = u32Value;
9866	pEvtRec->pNext = *pIemCpu->ppOtherEvtRecNext;
9867	*pIemCpu->ppOtherEvtRecNext = pEvtRec;
9868	}
9869
9870
9871	VMM_INT_DECL(void) IEMNotifyIOPortReadString(PVM pVM, RTIOPORT Port, RTGCPTR GCPtrDst, RTGCUINTREG cTransfers, size_t cbValue)
9872	{
9873	AssertFailed();
9874	}
9875
9876
9877	VMM_INT_DECL(void) IEMNotifyIOPortWriteString(PVM pVM, RTIOPORT Port, RTGCPTR GCPtrSrc, RTGCUINTREG cTransfers, size_t cbValue)
9878	{
9879	AssertFailed();
9880	}
9881
9882
9883	/**
9884	* Fakes and records an I/O port read.
9885	*
9886	* @returns VINF_SUCCESS.
9887	* @param pIemCpu The IEM per CPU data.
9888	* @param Port The I/O port.
9889	* @param pu32Value Where to store the fake value.
9890	* @param cbValue The size of the access.
9891	*/
9892	static VBOXSTRICTRC iemVerifyFakeIOPortRead(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue)
9893	{
9894	PIEMVERIFYEVTREC pEvtRec = iemVerifyAllocRecord(pIemCpu);
9895	if (pEvtRec)
9896	{
9897	pEvtRec->enmEvent = IEMVERIFYEVENT_IOPORT_READ;
9898	pEvtRec->u.IOPortRead.Port = Port;
9899	pEvtRec->u.IOPortRead.cbValue = (uint32_t)cbValue;
9900	pEvtRec->pNext = *pIemCpu->ppIemEvtRecNext;
9901	*pIemCpu->ppIemEvtRecNext = pEvtRec;
9902	}
9903	pIemCpu->cIOReads++;
9904	*pu32Value = 0xcccccccc;
9905	return VINF_SUCCESS;
9906	}
9907
9908
9909	/**
9910	* Fakes and records an I/O port write.
9911	*
9912	* @returns VINF_SUCCESS.
9913	* @param pIemCpu The IEM per CPU data.
9914	* @param Port The I/O port.
9915	* @param u32Value The value being written.
9916	* @param cbValue The size of the access.
9917	*/
9918	static VBOXSTRICTRC iemVerifyFakeIOPortWrite(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue)
9919	{
9920	PIEMVERIFYEVTREC pEvtRec = iemVerifyAllocRecord(pIemCpu);
9921	if (pEvtRec)
9922	{
9923	pEvtRec->enmEvent = IEMVERIFYEVENT_IOPORT_WRITE;
9924	pEvtRec->u.IOPortWrite.Port = Port;
9925	pEvtRec->u.IOPortWrite.cbValue = (uint32_t)cbValue;
9926	pEvtRec->u.IOPortWrite.u32Value = u32Value;
9927	pEvtRec->pNext = *pIemCpu->ppIemEvtRecNext;
9928	*pIemCpu->ppIemEvtRecNext = pEvtRec;
9929	}
9930	pIemCpu->cIOWrites++;
9931	return VINF_SUCCESS;
9932	}
9933
9934
9935	/**
9936	* Used to add extra details about a stub case.
9937	* @param pIemCpu The IEM per CPU state.
9938	*/
9939	static void iemVerifyAssertMsg2(PIEMCPU pIemCpu)
9940	{
9941	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
9942	PVM pVM = IEMCPU_TO_VM(pIemCpu);
9943	PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu);
9944	char szRegs[4096];
9945	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
9946	"rax=%016VR{rax} rbx=%016VR{rbx} rcx=%016VR{rcx} rdx=%016VR{rdx}\n"
9947	"rsi=%016VR{rsi} rdi=%016VR{rdi} r8 =%016VR{r8} r9 =%016VR{r9}\n"
9948	"r10=%016VR{r10} r11=%016VR{r11} r12=%016VR{r12} r13=%016VR{r13}\n"
9949	"r14=%016VR{r14} r15=%016VR{r15} %VRF{rflags}\n"
9950	"rip=%016VR{rip} rsp=%016VR{rsp} rbp=%016VR{rbp}\n"
9951	"cs={%04VR{cs} base=%016VR{cs_base} limit=%08VR{cs_lim} flags=%04VR{cs_attr}} cr0=%016VR{cr0}\n"
9952	"ds={%04VR{ds} base=%016VR{ds_base} limit=%08VR{ds_lim} flags=%04VR{ds_attr}} cr2=%016VR{cr2}\n"
9953	"es={%04VR{es} base=%016VR{es_base} limit=%08VR{es_lim} flags=%04VR{es_attr}} cr3=%016VR{cr3}\n"
9954	"fs={%04VR{fs} base=%016VR{fs_base} limit=%08VR{fs_lim} flags=%04VR{fs_attr}} cr4=%016VR{cr4}\n"
9955	"gs={%04VR{gs} base=%016VR{gs_base} limit=%08VR{gs_lim} flags=%04VR{gs_attr}} cr8=%016VR{cr8}\n"
9956	"ss={%04VR{ss} base=%016VR{ss_base} limit=%08VR{ss_lim} flags=%04VR{ss_attr}}\n"
9957	"dr0=%016VR{dr0} dr1=%016VR{dr1} dr2=%016VR{dr2} dr3=%016VR{dr3}\n"
9958	"dr6=%016VR{dr6} dr7=%016VR{dr7}\n"
9959	"gdtr=%016VR{gdtr_base}:%04VR{gdtr_lim} idtr=%016VR{idtr_base}:%04VR{idtr_lim} rflags=%08VR{rflags}\n"
9960	"ldtr={%04VR{ldtr} base=%016VR{ldtr_base} limit=%08VR{ldtr_lim} flags=%08VR{ldtr_attr}}\n"
9961	"tr ={%04VR{tr} base=%016VR{tr_base} limit=%08VR{tr_lim} flags=%08VR{tr_attr}}\n"
9962	" sysenter={cs=%04VR{sysenter_cs} eip=%08VR{sysenter_eip} esp=%08VR{sysenter_esp}}\n"
9963	" efer=%016VR{efer}\n"
9964	" pat=%016VR{pat}\n"
9965	" sf_mask=%016VR{sf_mask}\n"
9966	"krnl_gs_base=%016VR{krnl_gs_base}\n"
9967	" lstar=%016VR{lstar}\n"
9968	" star=%016VR{star} cstar=%016VR{cstar}\n"
9969	"fcw=%04VR{fcw} fsw=%04VR{fsw} ftw=%04VR{ftw} mxcsr=%04VR{mxcsr} mxcsr_mask=%04VR{mxcsr_mask}\n"
9970	);
9971
9972	char szInstr1[256];
9973	DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pIemCpu->uOldCs, pIemCpu->uOldRip,
9974	DBGF_DISAS_FLAGS_DEFAULT_MODE,
9975	szInstr1, sizeof(szInstr1), NULL);
9976	char szInstr2[256];
9977	DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
9978	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
9979	szInstr2, sizeof(szInstr2), NULL);
9980
9981	RTAssertMsg2Weak("%s%s\n%s\n", szRegs, szInstr1, szInstr2);
9982	}
9983
9984
9985	/**
9986	* Used by iemVerifyAssertRecord and iemVerifyAssertRecords to add a record
9987	* dump to the assertion info.
9988	*
9989	* @param pEvtRec The record to dump.
9990	*/
9991	static void iemVerifyAssertAddRecordDump(PIEMVERIFYEVTREC pEvtRec)
9992	{
9993	switch (pEvtRec->enmEvent)
9994	{
9995	case IEMVERIFYEVENT_IOPORT_READ:
9996	RTAssertMsg2Add("I/O PORT READ from %#6x, %d bytes\n",
9997	pEvtRec->u.IOPortWrite.Port,
9998	pEvtRec->u.IOPortWrite.cbValue);
9999	break;
10000	case IEMVERIFYEVENT_IOPORT_WRITE:
10001	RTAssertMsg2Add("I/O PORT WRITE to %#6x, %d bytes, value %#x\n",
10002	pEvtRec->u.IOPortWrite.Port,
10003	pEvtRec->u.IOPortWrite.cbValue,
10004	pEvtRec->u.IOPortWrite.u32Value);
10005	break;
10006	case IEMVERIFYEVENT_RAM_READ:
10007	RTAssertMsg2Add("RAM READ at %RGp, %#4zx bytes\n",
10008	pEvtRec->u.RamRead.GCPhys,
10009	pEvtRec->u.RamRead.cb);
10010	break;
10011	case IEMVERIFYEVENT_RAM_WRITE:
10012	RTAssertMsg2Add("RAM WRITE at %RGp, %#4zx bytes: %.*Rhxs\n",
10013	pEvtRec->u.RamWrite.GCPhys,
10014	pEvtRec->u.RamWrite.cb,
10015	(int)pEvtRec->u.RamWrite.cb,
10016	pEvtRec->u.RamWrite.ab);
10017	break;
10018	default:
10019	AssertMsgFailed(("Invalid event type %d\n", pEvtRec->enmEvent));
10020	break;
10021	}
10022	}
10023
10024
10025	/**
10026	* Raises an assertion on the specified record, showing the given message with
10027	* a record dump attached.
10028	*
10029	* @param pIemCpu The IEM per CPU data.
10030	* @param pEvtRec1 The first record.
10031	* @param pEvtRec2 The second record.
10032	* @param pszMsg The message explaining why we're asserting.
10033	*/
10034	static void iemVerifyAssertRecords(PIEMCPU pIemCpu, PIEMVERIFYEVTREC pEvtRec1, PIEMVERIFYEVTREC pEvtRec2, const char *pszMsg)
10035	{
10036	RTAssertMsg1(pszMsg, __LINE__, __FILE__, __PRETTY_FUNCTION__);
10037	iemVerifyAssertAddRecordDump(pEvtRec1);
10038	iemVerifyAssertAddRecordDump(pEvtRec2);
10039	iemVerifyAssertMsg2(pIemCpu);
10040	RTAssertPanic();
10041	}
10042
10043
10044	/**
10045	* Raises an assertion on the specified record, showing the given message with
10046	* a record dump attached.
10047	*
10048	* @param pIemCpu The IEM per CPU data.
10049	* @param pEvtRec1 The first record.
10050	* @param pszMsg The message explaining why we're asserting.
10051	*/
10052	static void iemVerifyAssertRecord(PIEMCPU pIemCpu, PIEMVERIFYEVTREC pEvtRec, const char *pszMsg)
10053	{
10054	RTAssertMsg1(pszMsg, __LINE__, __FILE__, __PRETTY_FUNCTION__);
10055	iemVerifyAssertAddRecordDump(pEvtRec);
10056	iemVerifyAssertMsg2(pIemCpu);
10057	RTAssertPanic();
10058	}
10059
10060
10061	/**
10062	* Verifies a write record.
10063	*
10064	* @param pIemCpu The IEM per CPU data.
10065	* @param pEvtRec The write record.
10066	* @param fRem Set if REM was doing the other executing. If clear
10067	* it was HM.
10068	*/
10069	static void iemVerifyWriteRecord(PIEMCPU pIemCpu, PIEMVERIFYEVTREC pEvtRec, bool fRem)
10070	{
10071	uint8_t abBuf[sizeof(pEvtRec->u.RamWrite.ab)]; RT_ZERO(abBuf);
10072	Assert(sizeof(abBuf) >= pEvtRec->u.RamWrite.cb);
10073	int rc = PGMPhysSimpleReadGCPhys(IEMCPU_TO_VM(pIemCpu), abBuf, pEvtRec->u.RamWrite.GCPhys, pEvtRec->u.RamWrite.cb);
10074	if ( RT_FAILURE(rc)
10075	\|\| memcmp(abBuf, pEvtRec->u.RamWrite.ab, pEvtRec->u.RamWrite.cb) )
10076	{
10077	/* fend off ins */
10078	if ( !pIemCpu->cIOReads
10079	\|\| pEvtRec->u.RamWrite.ab[0] != 0xcc
10080	\|\| ( pEvtRec->u.RamWrite.cb != 1
10081	&& pEvtRec->u.RamWrite.cb != 2
10082	&& pEvtRec->u.RamWrite.cb != 4) )
10083	{
10084	/* fend off ROMs and MMIO */
10085	if ( pEvtRec->u.RamWrite.GCPhys - UINT32_C(0x000a0000) > UINT32_C(0x60000)
10086	&& pEvtRec->u.RamWrite.GCPhys - UINT32_C(0xfffc0000) > UINT32_C(0x40000) )
10087	{
10088	/* fend off fxsave */
10089	if (pEvtRec->u.RamWrite.cb != 512)
10090	{
10091	const char *pszWho = fRem ? "rem" : HMR3IsVmxEnabled(IEMCPU_TO_VM(pIemCpu)->pUVM) ? "vmx" : "svm";
10092	RTAssertMsg1(NULL, __LINE__, __FILE__, __PRETTY_FUNCTION__);
10093	RTAssertMsg2Weak("Memory at %RGv differs\n", pEvtRec->u.RamWrite.GCPhys);
10094	RTAssertMsg2Add("%s: %.*Rhxs\n"
10095	"iem: %.*Rhxs\n",
10096	pszWho, pEvtRec->u.RamWrite.cb, abBuf,
10097	pEvtRec->u.RamWrite.cb, pEvtRec->u.RamWrite.ab);
10098	iemVerifyAssertAddRecordDump(pEvtRec);
10099	iemVerifyAssertMsg2(pIemCpu);
10100	RTAssertPanic();
10101	}
10102	}
10103	}
10104	}
10105
10106	}
10107
10108	/**
10109	* Performs the post-execution verfication checks.
10110	*/
10111	static void iemExecVerificationModeCheck(PIEMCPU pIemCpu)
10112	{
10113	if (!IEM_VERIFICATION_ENABLED(pIemCpu))
10114	return;
10115
10116	/*
10117	* Switch back the state.
10118	*/
10119	PCPUMCTX pOrgCtx = CPUMQueryGuestCtxPtr(IEMCPU_TO_VMCPU(pIemCpu));
10120	PCPUMCTX pDebugCtx = pIemCpu->CTX_SUFF(pCtx);
10121	Assert(pOrgCtx != pDebugCtx);
10122	pIemCpu->CTX_SUFF(pCtx) = pOrgCtx;
10123
10124	/*
10125	* Execute the instruction in REM.
10126	*/
10127	bool fRem = false;
10128	PVM pVM = IEMCPU_TO_VM(pIemCpu);
10129	PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu);
10130	VBOXSTRICTRC rc = VERR_EM_CANNOT_EXEC_GUEST;
10131	#ifdef IEM_VERIFICATION_MODE_FULL_HM
10132	if ( HMIsEnabled(pVM)
10133	&& pIemCpu->cIOReads == 0
10134	&& pIemCpu->cIOWrites == 0
10135	&& !pIemCpu->fProblematicMemory)
10136	{
10137	uint64_t uStartRip = pOrgCtx->rip;
10138	unsigned iLoops = 0;
10139	do
10140	{
10141	rc = EMR3HmSingleInstruction(pVM, pVCpu, EM_ONE_INS_FLAGS_RIP_CHANGE);
10142	iLoops++;
10143	} while ( rc == VINF_SUCCESS
10144	\|\| ( rc == VINF_EM_DBG_STEPPED
10145	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
10146	&& EMGetInhibitInterruptsPC(pVCpu) == pOrgCtx->rip)
10147	\|\| ( pOrgCtx->rip != pDebugCtx->rip
10148	&& pIemCpu->uInjectCpl != UINT8_MAX
10149	&& iLoops < 8) );
10150	if (rc == VINF_EM_RESCHEDULE && pOrgCtx->rip != uStartRip)
10151	rc = VINF_SUCCESS;
10152	}
10153	#endif
10154	if ( rc == VERR_EM_CANNOT_EXEC_GUEST
10155	\|\| rc == VINF_IOM_R3_IOPORT_READ
10156	\|\| rc == VINF_IOM_R3_IOPORT_WRITE
10157	\|\| rc == VINF_IOM_R3_MMIO_READ
10158	\|\| rc == VINF_IOM_R3_MMIO_READ_WRITE
10159	\|\| rc == VINF_IOM_R3_MMIO_WRITE
10160	\|\| rc == VINF_CPUM_R3_MSR_READ
10161	\|\| rc == VINF_CPUM_R3_MSR_WRITE
10162	\|\| rc == VINF_EM_RESCHEDULE
10163	)
10164	{
10165	EMRemLock(pVM);
10166	rc = REMR3EmulateInstruction(pVM, pVCpu);
10167	AssertRC(rc);
10168	EMRemUnlock(pVM);
10169	fRem = true;
10170	}
10171
10172	/*
10173	* Compare the register states.
10174	*/
10175	unsigned cDiffs = 0;
10176	if (memcmp(pOrgCtx, pDebugCtx, sizeof(*pDebugCtx)))
10177	{
10178	//Log(("REM and IEM ends up with different registers!\n"));
10179	const char *pszWho = fRem ? "rem" : HMR3IsVmxEnabled(pVM->pUVM) ? "vmx" : "svm";
10180
10181	# define CHECK_FIELD(a_Field) \
10182	do \
10183	{ \
10184	if (pOrgCtx->a_Field != pDebugCtx->a_Field) \
10185	{ \
10186	switch (sizeof(pOrgCtx->a_Field)) \
10187	{ \
10188	case 1: RTAssertMsg2Weak(" %8s differs - iem=%02x - %s=%02x\n", #a_Field, pDebugCtx->a_Field, pszWho, pOrgCtx->a_Field); break; \
10189	case 2: RTAssertMsg2Weak(" %8s differs - iem=%04x - %s=%04x\n", #a_Field, pDebugCtx->a_Field, pszWho, pOrgCtx->a_Field); break; \
10190	case 4: RTAssertMsg2Weak(" %8s differs - iem=%08x - %s=%08x\n", #a_Field, pDebugCtx->a_Field, pszWho, pOrgCtx->a_Field); break; \
10191	case 8: RTAssertMsg2Weak(" %8s differs - iem=%016llx - %s=%016llx\n", #a_Field, pDebugCtx->a_Field, pszWho, pOrgCtx->a_Field); break; \
10192	default: RTAssertMsg2Weak(" %8s differs\n", #a_Field); break; \
10193	} \
10194	cDiffs++; \
10195	} \
10196	} while (0)
10197
10198	# define CHECK_BIT_FIELD(a_Field) \
10199	do \
10200	{ \
10201	if (pOrgCtx->a_Field != pDebugCtx->a_Field) \
10202	{ \
10203	RTAssertMsg2Weak(" %8s differs - iem=%02x - %s=%02x\n", #a_Field, pDebugCtx->a_Field, pszWho, pOrgCtx->a_Field); \
10204	cDiffs++; \
10205	} \
10206	} while (0)
10207
10208	# define CHECK_SEL(a_Sel) \
10209	do \
10210	{ \
10211	CHECK_FIELD(a_Sel.Sel); \
10212	CHECK_FIELD(a_Sel.Attr.u); \
10213	CHECK_FIELD(a_Sel.u64Base); \
10214	CHECK_FIELD(a_Sel.u32Limit); \
10215	CHECK_FIELD(a_Sel.fFlags); \
10216	} while (0)
10217
10218	#if 1 /* The recompiler doesn't update these the intel way. */
10219	if (fRem)
10220	{
10221	pOrgCtx->fpu.FOP = pDebugCtx->fpu.FOP;
10222	pOrgCtx->fpu.FPUIP = pDebugCtx->fpu.FPUIP;
10223	pOrgCtx->fpu.CS = pDebugCtx->fpu.CS;
10224	pOrgCtx->fpu.Rsrvd1 = pDebugCtx->fpu.Rsrvd1;
10225	pOrgCtx->fpu.FPUDP = pDebugCtx->fpu.FPUDP;
10226	pOrgCtx->fpu.DS = pDebugCtx->fpu.DS;
10227	pOrgCtx->fpu.Rsrvd2 = pDebugCtx->fpu.Rsrvd2;
10228	//pOrgCtx->fpu.MXCSR_MASK = pDebugCtx->fpu.MXCSR_MASK;
10229	if ((pOrgCtx->fpu.FSW & X86_FSW_TOP_MASK) == (pDebugCtx->fpu.FSW & X86_FSW_TOP_MASK))
10230	pOrgCtx->fpu.FSW = pDebugCtx->fpu.FSW;
10231	}
10232	#endif
10233	if (memcmp(&pOrgCtx->fpu, &pDebugCtx->fpu, sizeof(pDebugCtx->fpu)))
10234	{
10235	RTAssertMsg2Weak(" the FPU state differs\n");
10236	cDiffs++;
10237	CHECK_FIELD(fpu.FCW);
10238	CHECK_FIELD(fpu.FSW);
10239	CHECK_FIELD(fpu.FTW);
10240	CHECK_FIELD(fpu.FOP);
10241	CHECK_FIELD(fpu.FPUIP);
10242	CHECK_FIELD(fpu.CS);
10243	CHECK_FIELD(fpu.Rsrvd1);
10244	CHECK_FIELD(fpu.FPUDP);
10245	CHECK_FIELD(fpu.DS);
10246	CHECK_FIELD(fpu.Rsrvd2);
10247	CHECK_FIELD(fpu.MXCSR);
10248	CHECK_FIELD(fpu.MXCSR_MASK);
10249	CHECK_FIELD(fpu.aRegs[0].au64[0]); CHECK_FIELD(fpu.aRegs[0].au64[1]);
10250	CHECK_FIELD(fpu.aRegs[1].au64[0]); CHECK_FIELD(fpu.aRegs[1].au64[1]);
10251	CHECK_FIELD(fpu.aRegs[2].au64[0]); CHECK_FIELD(fpu.aRegs[2].au64[1]);
10252	CHECK_FIELD(fpu.aRegs[3].au64[0]); CHECK_FIELD(fpu.aRegs[3].au64[1]);
10253	CHECK_FIELD(fpu.aRegs[4].au64[0]); CHECK_FIELD(fpu.aRegs[4].au64[1]);
10254	CHECK_FIELD(fpu.aRegs[5].au64[0]); CHECK_FIELD(fpu.aRegs[5].au64[1]);
10255	CHECK_FIELD(fpu.aRegs[6].au64[0]); CHECK_FIELD(fpu.aRegs[6].au64[1]);
10256	CHECK_FIELD(fpu.aRegs[7].au64[0]); CHECK_FIELD(fpu.aRegs[7].au64[1]);
10257	CHECK_FIELD(fpu.aXMM[ 0].au64[0]); CHECK_FIELD(fpu.aXMM[ 0].au64[1]);
10258	CHECK_FIELD(fpu.aXMM[ 1].au64[0]); CHECK_FIELD(fpu.aXMM[ 1].au64[1]);
10259	CHECK_FIELD(fpu.aXMM[ 2].au64[0]); CHECK_FIELD(fpu.aXMM[ 2].au64[1]);
10260	CHECK_FIELD(fpu.aXMM[ 3].au64[0]); CHECK_FIELD(fpu.aXMM[ 3].au64[1]);
10261	CHECK_FIELD(fpu.aXMM[ 4].au64[0]); CHECK_FIELD(fpu.aXMM[ 4].au64[1]);
10262	CHECK_FIELD(fpu.aXMM[ 5].au64[0]); CHECK_FIELD(fpu.aXMM[ 5].au64[1]);
10263	CHECK_FIELD(fpu.aXMM[ 6].au64[0]); CHECK_FIELD(fpu.aXMM[ 6].au64[1]);
10264	CHECK_FIELD(fpu.aXMM[ 7].au64[0]); CHECK_FIELD(fpu.aXMM[ 7].au64[1]);
10265	CHECK_FIELD(fpu.aXMM[ 8].au64[0]); CHECK_FIELD(fpu.aXMM[ 8].au64[1]);
10266	CHECK_FIELD(fpu.aXMM[ 9].au64[0]); CHECK_FIELD(fpu.aXMM[ 9].au64[1]);
10267	CHECK_FIELD(fpu.aXMM[10].au64[0]); CHECK_FIELD(fpu.aXMM[10].au64[1]);
10268	CHECK_FIELD(fpu.aXMM[11].au64[0]); CHECK_FIELD(fpu.aXMM[11].au64[1]);
10269	CHECK_FIELD(fpu.aXMM[12].au64[0]); CHECK_FIELD(fpu.aXMM[12].au64[1]);
10270	CHECK_FIELD(fpu.aXMM[13].au64[0]); CHECK_FIELD(fpu.aXMM[13].au64[1]);
10271	CHECK_FIELD(fpu.aXMM[14].au64[0]); CHECK_FIELD(fpu.aXMM[14].au64[1]);
10272	CHECK_FIELD(fpu.aXMM[15].au64[0]); CHECK_FIELD(fpu.aXMM[15].au64[1]);
10273	for (unsigned i = 0; i < RT_ELEMENTS(pOrgCtx->fpu.au32RsrvdRest); i++)
10274	CHECK_FIELD(fpu.au32RsrvdRest[i]);
10275	}
10276	CHECK_FIELD(rip);
10277	uint32_t fFlagsMask = UINT32_MAX & ~pIemCpu->fUndefinedEFlags;
10278	if ((pOrgCtx->rflags.u & fFlagsMask) != (pDebugCtx->rflags.u & fFlagsMask))
10279	{
10280	RTAssertMsg2Weak(" rflags differs - iem=%08llx %s=%08llx\n", pDebugCtx->rflags.u, pszWho, pOrgCtx->rflags.u);
10281	CHECK_BIT_FIELD(rflags.Bits.u1CF);
10282	CHECK_BIT_FIELD(rflags.Bits.u1Reserved0);
10283	CHECK_BIT_FIELD(rflags.Bits.u1PF);
10284	CHECK_BIT_FIELD(rflags.Bits.u1Reserved1);
10285	CHECK_BIT_FIELD(rflags.Bits.u1AF);
10286	CHECK_BIT_FIELD(rflags.Bits.u1Reserved2);
10287	CHECK_BIT_FIELD(rflags.Bits.u1ZF);
10288	CHECK_BIT_FIELD(rflags.Bits.u1SF);
10289	CHECK_BIT_FIELD(rflags.Bits.u1TF);
10290	CHECK_BIT_FIELD(rflags.Bits.u1IF);
10291	CHECK_BIT_FIELD(rflags.Bits.u1DF);
10292	CHECK_BIT_FIELD(rflags.Bits.u1OF);
10293	CHECK_BIT_FIELD(rflags.Bits.u2IOPL);
10294	CHECK_BIT_FIELD(rflags.Bits.u1NT);
10295	CHECK_BIT_FIELD(rflags.Bits.u1Reserved3);
10296	if (0 && !fRem) /** @todo debug the occational clear RF flags when running against VT-x. */
10297	CHECK_BIT_FIELD(rflags.Bits.u1RF);
10298	CHECK_BIT_FIELD(rflags.Bits.u1VM);
10299	CHECK_BIT_FIELD(rflags.Bits.u1AC);
10300	CHECK_BIT_FIELD(rflags.Bits.u1VIF);
10301	CHECK_BIT_FIELD(rflags.Bits.u1VIP);
10302	CHECK_BIT_FIELD(rflags.Bits.u1ID);
10303	}
10304
10305	if (pIemCpu->cIOReads != 1 && !pIemCpu->fIgnoreRaxRdx)
10306	CHECK_FIELD(rax);
10307	CHECK_FIELD(rcx);
10308	if (!pIemCpu->fIgnoreRaxRdx)
10309	CHECK_FIELD(rdx);
10310	CHECK_FIELD(rbx);
10311	CHECK_FIELD(rsp);
10312	CHECK_FIELD(rbp);
10313	CHECK_FIELD(rsi);
10314	CHECK_FIELD(rdi);
10315	CHECK_FIELD(r8);
10316	CHECK_FIELD(r9);
10317	CHECK_FIELD(r10);
10318	CHECK_FIELD(r11);
10319	CHECK_FIELD(r12);
10320	CHECK_FIELD(r13);
10321	CHECK_SEL(cs);
10322	CHECK_SEL(ss);
10323	CHECK_SEL(ds);
10324	CHECK_SEL(es);
10325	CHECK_SEL(fs);
10326	CHECK_SEL(gs);
10327	CHECK_FIELD(cr0);
10328
10329	/* Klugde #1: REM fetches code and across the page boundrary and faults on the next page, while we execute
10330	the faulting instruction first: 001b:77f61ff3 66 8b 42 02 mov ax, word [edx+002h] (NT4SP1) */
10331	/* Kludge #2: CR2 differs slightly on cross page boundrary faults, we report the last address of the access
10332	while REM reports the address of the first byte on the page. Pending investigation as to which is correct. */
10333	if (pOrgCtx->cr2 != pDebugCtx->cr2)
10334	{
10335	if (pIemCpu->uOldCs == 0x1b && pIemCpu->uOldRip == 0x77f61ff3 && fRem)
10336	{ /* ignore */ }
10337	else if ( (pOrgCtx->cr2 & ~(uint64_t)3) == (pDebugCtx->cr2 & ~(uint64_t)3)
10338	&& (pOrgCtx->cr2 & PAGE_OFFSET_MASK) == 0
10339	&& fRem)
10340	{ /* ignore */ }
10341	else
10342	CHECK_FIELD(cr2);
10343	}
10344	CHECK_FIELD(cr3);
10345	CHECK_FIELD(cr4);
10346	CHECK_FIELD(dr[0]);
10347	CHECK_FIELD(dr[1]);
10348	CHECK_FIELD(dr[2]);
10349	CHECK_FIELD(dr[3]);
10350	CHECK_FIELD(dr[6]);
10351	if (!fRem \|\| (pOrgCtx->dr[7] & ~X86_DR7_RA1_MASK) != (pDebugCtx->dr[7] & ~X86_DR7_RA1_MASK)) /* REM 'mov drX,greg' bug.*/
10352	CHECK_FIELD(dr[7]);
10353	CHECK_FIELD(gdtr.cbGdt);
10354	CHECK_FIELD(gdtr.pGdt);
10355	CHECK_FIELD(idtr.cbIdt);
10356	CHECK_FIELD(idtr.pIdt);
10357	CHECK_SEL(ldtr);
10358	CHECK_SEL(tr);
10359	CHECK_FIELD(SysEnter.cs);
10360	CHECK_FIELD(SysEnter.eip);
10361	CHECK_FIELD(SysEnter.esp);
10362	CHECK_FIELD(msrEFER);
10363	CHECK_FIELD(msrSTAR);
10364	CHECK_FIELD(msrPAT);
10365	CHECK_FIELD(msrLSTAR);
10366	CHECK_FIELD(msrCSTAR);
10367	CHECK_FIELD(msrSFMASK);
10368	CHECK_FIELD(msrKERNELGSBASE);
10369
10370	if (cDiffs != 0)
10371	{
10372	DBGFR3Info(pVM->pUVM, "cpumguest", "verbose", NULL);
10373	RTAssertMsg1(NULL, __LINE__, __FILE__, __FUNCTION__);
10374	iemVerifyAssertMsg2(pIemCpu);
10375	RTAssertPanic();
10376	}
10377	# undef CHECK_FIELD
10378	# undef CHECK_BIT_FIELD
10379	}
10380
10381	/*
10382	* If the register state compared fine, check the verification event
10383	* records.
10384	*/
10385	if (cDiffs == 0 && !pIemCpu->fOverlappingMovs)
10386	{
10387	/*
10388	* Compare verficiation event records.
10389	* - I/O port accesses should be a 1:1 match.
10390	*/
10391	PIEMVERIFYEVTREC pIemRec = pIemCpu->pIemEvtRecHead;
10392	PIEMVERIFYEVTREC pOtherRec = pIemCpu->pOtherEvtRecHead;
10393	while (pIemRec && pOtherRec)
10394	{
10395	/* Since we might miss RAM writes and reads, ignore reads and check
10396	that any written memory is the same extra ones. */
10397	while ( IEMVERIFYEVENT_IS_RAM(pIemRec->enmEvent)
10398	&& !IEMVERIFYEVENT_IS_RAM(pOtherRec->enmEvent)
10399	&& pIemRec->pNext)
10400	{
10401	if (pIemRec->enmEvent == IEMVERIFYEVENT_RAM_WRITE)
10402	iemVerifyWriteRecord(pIemCpu, pIemRec, fRem);
10403	pIemRec = pIemRec->pNext;
10404	}
10405
10406	/* Do the compare. */
10407	if (pIemRec->enmEvent != pOtherRec->enmEvent)
10408	{
10409	iemVerifyAssertRecords(pIemCpu, pIemRec, pOtherRec, "Type mismatches");
10410	break;
10411	}
10412	bool fEquals;
10413	switch (pIemRec->enmEvent)
10414	{
10415	case IEMVERIFYEVENT_IOPORT_READ:
10416	fEquals = pIemRec->u.IOPortRead.Port == pOtherRec->u.IOPortRead.Port
10417	&& pIemRec->u.IOPortRead.cbValue == pOtherRec->u.IOPortRead.cbValue;
10418	break;
10419	case IEMVERIFYEVENT_IOPORT_WRITE:
10420	fEquals = pIemRec->u.IOPortWrite.Port == pOtherRec->u.IOPortWrite.Port
10421	&& pIemRec->u.IOPortWrite.cbValue == pOtherRec->u.IOPortWrite.cbValue
10422	&& pIemRec->u.IOPortWrite.u32Value == pOtherRec->u.IOPortWrite.u32Value;
10423	break;
10424	case IEMVERIFYEVENT_RAM_READ:
10425	fEquals = pIemRec->u.RamRead.GCPhys == pOtherRec->u.RamRead.GCPhys
10426	&& pIemRec->u.RamRead.cb == pOtherRec->u.RamRead.cb;
10427	break;
10428	case IEMVERIFYEVENT_RAM_WRITE:
10429	fEquals = pIemRec->u.RamWrite.GCPhys == pOtherRec->u.RamWrite.GCPhys
10430	&& pIemRec->u.RamWrite.cb == pOtherRec->u.RamWrite.cb
10431	&& !memcmp(pIemRec->u.RamWrite.ab, pOtherRec->u.RamWrite.ab, pIemRec->u.RamWrite.cb);
10432	break;
10433	default:
10434	fEquals = false;
10435	break;
10436	}
10437	if (!fEquals)
10438	{
10439	iemVerifyAssertRecords(pIemCpu, pIemRec, pOtherRec, "Mismatch");
10440	break;
10441	}
10442
10443	/* advance */
10444	pIemRec = pIemRec->pNext;
10445	pOtherRec = pOtherRec->pNext;
10446	}
10447
10448	/* Ignore extra writes and reads. */
10449	while (pIemRec && IEMVERIFYEVENT_IS_RAM(pIemRec->enmEvent))
10450	{
10451	if (pIemRec->enmEvent == IEMVERIFYEVENT_RAM_WRITE)
10452	iemVerifyWriteRecord(pIemCpu, pIemRec, fRem);
10453	pIemRec = pIemRec->pNext;
10454	}
10455	if (pIemRec != NULL)
10456	iemVerifyAssertRecord(pIemCpu, pIemRec, "Extra IEM record!");
10457	else if (pOtherRec != NULL)
10458	iemVerifyAssertRecord(pIemCpu, pOtherRec, "Extra Other record!");
10459	}
10460	pIemCpu->CTX_SUFF(pCtx) = pOrgCtx;
10461	}
10462
10463	#else /* !IEM_VERIFICATION_MODE_FULL \|\| !IN_RING3 */
10464
10465	/* stubs */
10466	static VBOXSTRICTRC iemVerifyFakeIOPortRead(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t *pu32Value, size_t cbValue)
10467	{
10468	NOREF(pIemCpu); NOREF(Port); NOREF(pu32Value); NOREF(cbValue);
10469	return VERR_INTERNAL_ERROR;
10470	}
10471
10472	static VBOXSTRICTRC iemVerifyFakeIOPortWrite(PIEMCPU pIemCpu, RTIOPORT Port, uint32_t u32Value, size_t cbValue)
10473	{
10474	NOREF(pIemCpu); NOREF(Port); NOREF(u32Value); NOREF(cbValue);
10475	return VERR_INTERNAL_ERROR;
10476	}
10477
10478	#endif /* !IEM_VERIFICATION_MODE_FULL \|\| !IN_RING3 */
10479
10480
10481	#ifdef LOG_ENABLED
10482	/**
10483	* Logs the current instruction.
10484	* @param pVCpu The cross context virtual CPU structure of the caller.
10485	* @param pCtx The current CPU context.
10486	* @param fSameCtx Set if we have the same context information as the VMM,
10487	* clear if we may have already executed an instruction in
10488	* our debug context. When clear, we assume IEMCPU holds
10489	* valid CPU mode info.
10490	*/
10491	static void iemLogCurInstr(PVMCPU pVCpu, PCPUMCTX pCtx, bool fSameCtx)
10492	{
10493	# ifdef IN_RING3
10494	if (LogIs2Enabled())
10495	{
10496	char szInstr[256];
10497	uint32_t cbInstr = 0;
10498	if (fSameCtx)
10499	DBGFR3DisasInstrEx(pVCpu->pVMR3->pUVM, pVCpu->idCpu, 0, 0,
10500	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
10501	szInstr, sizeof(szInstr), &cbInstr);
10502	else
10503	{
10504	uint32_t fFlags = 0;
10505	switch (pVCpu->iem.s.enmCpuMode)
10506	{
10507	case IEMMODE_64BIT: fFlags \|= DBGF_DISAS_FLAGS_64BIT_MODE; break;
10508	case IEMMODE_32BIT: fFlags \|= DBGF_DISAS_FLAGS_32BIT_MODE; break;
10509	case IEMMODE_16BIT:
10510	if (!(pCtx->cr0 & X86_CR0_PE) \|\| pCtx->eflags.Bits.u1VM)
10511	fFlags \|= DBGF_DISAS_FLAGS_16BIT_REAL_MODE;
10512	else
10513	fFlags \|= DBGF_DISAS_FLAGS_16BIT_MODE;
10514	break;
10515	}
10516	DBGFR3DisasInstrEx(pVCpu->pVMR3->pUVM, pVCpu->idCpu, pCtx->cs.Sel, pCtx->rip, fFlags,
10517	szInstr, sizeof(szInstr), &cbInstr);
10518	}
10519
10520	Log2(("****\n"
10521	" eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
10522	" eip=%08x esp=%08x ebp=%08x iopl=%d tr=%04x\n"
10523	" cs=%04x ss=%04x ds=%04x es=%04x fs=%04x gs=%04x efl=%08x\n"
10524	" fsw=%04x fcw=%04x ftw=%02x mxcsr=%04x/%04x\n"
10525	" %s\n"
10526	,
10527	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
10528	pCtx->eip, pCtx->esp, pCtx->ebp, pCtx->eflags.Bits.u2IOPL, pCtx->tr.Sel,
10529	pCtx->cs.Sel, pCtx->ss.Sel, pCtx->ds.Sel, pCtx->es.Sel,
10530	pCtx->fs.Sel, pCtx->gs.Sel, pCtx->eflags.u,
10531	pCtx->fpu.FSW, pCtx->fpu.FCW, pCtx->fpu.FTW, pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK,
10532	szInstr));
10533
10534	if (LogIs3Enabled())
10535	DBGFR3Info(pVCpu->pVMR3->pUVM, "cpumguest", "verbose", NULL);
10536	}
10537	else
10538	# endif
10539	LogFlow(("IEMExecOne: cs:rip=%04x:%08RX64 ss:rsp=%04x:%08RX64 EFL=%06x\n",
10540	pCtx->cs.Sel, pCtx->rip, pCtx->ss.Sel, pCtx->rsp, pCtx->eflags.u));
10541	}
10542	#endif
10543
10544
10545	/**
10546	* Makes status code addjustments (pass up from I/O and access handler)
10547	* as well as maintaining statistics.
10548	*
10549	* @returns Strict VBox status code to pass up.
10550	* @param pIemCpu The IEM per CPU data.
10551	* @param rcStrict The status from executing an instruction.
10552	*/
10553	DECL_FORCE_INLINE(VBOXSTRICTRC) iemExecStatusCodeFiddling(PIEMCPU pIemCpu, VBOXSTRICTRC rcStrict)
10554	{
10555	if (rcStrict != VINF_SUCCESS)
10556	{
10557	if (RT_SUCCESS(rcStrict))
10558	{
10559	AssertMsg( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
10560	\|\| rcStrict == VINF_IOM_R3_IOPORT_READ
10561	\|\| rcStrict == VINF_IOM_R3_IOPORT_WRITE
10562	\|\| rcStrict == VINF_IOM_R3_MMIO_READ
10563	\|\| rcStrict == VINF_IOM_R3_MMIO_READ_WRITE
10564	\|\| rcStrict == VINF_IOM_R3_MMIO_WRITE
10565	\|\| rcStrict == VINF_CPUM_R3_MSR_READ
10566	\|\| rcStrict == VINF_CPUM_R3_MSR_WRITE
10567	, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
10568	int32_t const rcPassUp = pIemCpu->rcPassUp;
10569	if (rcPassUp == VINF_SUCCESS)
10570	pIemCpu->cRetInfStatuses++;
10571	else if ( rcPassUp < VINF_EM_FIRST
10572	\|\| rcPassUp > VINF_EM_LAST
10573	\|\| rcPassUp < VBOXSTRICTRC_VAL(rcStrict))
10574	{
10575	Log(("IEM: rcPassUp=%Rrc! rcStrict=%Rrc\n", rcPassUp, VBOXSTRICTRC_VAL(rcStrict)));
10576	pIemCpu->cRetPassUpStatus++;
10577	rcStrict = rcPassUp;
10578	}
10579	else
10580	{
10581	Log(("IEM: rcPassUp=%Rrc rcStrict=%Rrc!\n", rcPassUp, VBOXSTRICTRC_VAL(rcStrict)));
10582	pIemCpu->cRetInfStatuses++;
10583	}
10584	}
10585	else if (rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED)
10586	pIemCpu->cRetAspectNotImplemented++;
10587	else if (rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED)
10588	pIemCpu->cRetInstrNotImplemented++;
10589	#ifdef IEM_VERIFICATION_MODE_FULL
10590	else if (rcStrict == VERR_IEM_RESTART_INSTRUCTION)
10591	rcStrict = VINF_SUCCESS;
10592	#endif
10593	else
10594	pIemCpu->cRetErrStatuses++;
10595	}
10596	else if (pIemCpu->rcPassUp != VINF_SUCCESS)
10597	{
10598	pIemCpu->cRetPassUpStatus++;
10599	rcStrict = pIemCpu->rcPassUp;
10600	}
10601
10602	return rcStrict;
10603	}
10604
10605
10606	/**
10607	* The actual code execution bits of IEMExecOne, IEMExecOneEx, and
10608	* IEMExecOneWithPrefetchedByPC.
10609	*
10610	* @return Strict VBox status code.
10611	* @param pVCpu The current virtual CPU.
10612	* @param pIemCpu The IEM per CPU data.
10613	* @param fExecuteInhibit If set, execute the instruction following CLI,
10614	* POP SS and MOV SS,GR.
10615	*/
10616	DECL_FORCE_INLINE(VBOXSTRICTRC) iemExecOneInner(PVMCPU pVCpu, PIEMCPU pIemCpu, bool fExecuteInhibit)
10617	{
10618	uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
10619	VBOXSTRICTRC rcStrict = FNIEMOP_CALL(g_apfnOneByteMap[b]);
10620	if (rcStrict == VINF_SUCCESS)
10621	pIemCpu->cInstructions++;
10622	if (pIemCpu->cActiveMappings > 0)
10623	iemMemRollback(pIemCpu);
10624	//#ifdef DEBUG
10625	// AssertMsg(pIemCpu->offOpcode == cbInstr \|\| rcStrict != VINF_SUCCESS, ("%u %u\n", pIemCpu->offOpcode, cbInstr));
10626	//#endif
10627
10628	/* Execute the next instruction as well if a cli, pop ss or
10629	mov ss, Gr has just completed successfully. */
10630	if ( fExecuteInhibit
10631	&& rcStrict == VINF_SUCCESS
10632	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
10633	&& EMGetInhibitInterruptsPC(pVCpu) == pIemCpu->CTX_SUFF(pCtx)->rip )
10634	{
10635	rcStrict = iemInitDecoderAndPrefetchOpcodes(pIemCpu, pIemCpu->fBypassHandlers);
10636	if (rcStrict == VINF_SUCCESS)
10637	{
10638	# ifdef LOG_ENABLED
10639	iemLogCurInstr(IEMCPU_TO_VMCPU(pIemCpu), pIemCpu->CTX_SUFF(pCtx), false);
10640	# endif
10641	IEM_OPCODE_GET_NEXT_U8(&b);
10642	rcStrict = FNIEMOP_CALL(g_apfnOneByteMap[b]);
10643	if (rcStrict == VINF_SUCCESS)
10644	pIemCpu->cInstructions++;
10645	if (pIemCpu->cActiveMappings > 0)
10646	iemMemRollback(pIemCpu);
10647	}
10648	EMSetInhibitInterruptsPC(pVCpu, UINT64_C(0x7777555533331111));
10649	}
10650
10651	/*
10652	* Return value fiddling, statistics and sanity assertions.
10653	*/
10654	rcStrict = iemExecStatusCodeFiddling(pIemCpu, rcStrict);
10655
10656	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pIemCpu->CTX_SUFF(pCtx)->cs));
10657	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pIemCpu->CTX_SUFF(pCtx)->ss));
10658	#if defined(IEM_VERIFICATION_MODE_FULL)
10659	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pIemCpu->CTX_SUFF(pCtx)->es));
10660	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pIemCpu->CTX_SUFF(pCtx)->ds));
10661	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pIemCpu->CTX_SUFF(pCtx)->fs));
10662	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pIemCpu->CTX_SUFF(pCtx)->gs));
10663	#endif
10664	return rcStrict;
10665	}
10666
10667
10668	#ifdef IN_RC
10669	/**
10670	* Re-enters raw-mode or ensure we return to ring-3.
10671	*
10672	* @returns rcStrict, maybe modified.
10673	* @param pIemCpu The IEM CPU structure.
10674	* @param pVCpu The cross context virtual CPU structure of the caller.
10675	* @param pCtx The current CPU context.
10676	* @param rcStrict The status code returne by the interpreter.
10677	*/
10678	DECLINLINE(VBOXSTRICTRC) iemRCRawMaybeReenter(PIEMCPU pIemCpu, PVMCPU pVCpu, PCPUMCTX pCtx, VBOXSTRICTRC rcStrict)
10679	{
10680	if (!pIemCpu->fInPatchCode)
10681	CPUMRawEnter(pVCpu, CPUMCTX2CORE(pCtx));
10682	return rcStrict;
10683	}
10684	#endif
10685
10686
10687	/**
10688	* Execute one instruction.
10689	*
10690	* @return Strict VBox status code.
10691	* @param pVCpu The current virtual CPU.
10692	*/
10693	VMMDECL(VBOXSTRICTRC) IEMExecOne(PVMCPU pVCpu)
10694	{
10695	PIEMCPU pIemCpu = &pVCpu->iem.s;
10696
10697	#if defined(IEM_VERIFICATION_MODE_FULL) && defined(IN_RING3)
10698	iemExecVerificationModeSetup(pIemCpu);
10699	#endif
10700	#ifdef LOG_ENABLED
10701	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
10702	iemLogCurInstr(pVCpu, pCtx, true);
10703	#endif
10704
10705	/*
10706	* Do the decoding and emulation.
10707	*/
10708	VBOXSTRICTRC rcStrict = iemInitDecoderAndPrefetchOpcodes(pIemCpu, false);
10709	if (rcStrict == VINF_SUCCESS)
10710	rcStrict = iemExecOneInner(pVCpu, pIemCpu, true);
10711
10712	#if defined(IEM_VERIFICATION_MODE_FULL) && defined(IN_RING3)
10713	/*
10714	* Assert some sanity.
10715	*/
10716	iemExecVerificationModeCheck(pIemCpu);
10717	#endif
10718	#ifdef IN_RC
10719	rcStrict = iemRCRawMaybeReenter(pIemCpu, pVCpu, pIemCpu->CTX_SUFF(pCtx), rcStrict);
10720	#endif
10721	if (rcStrict != VINF_SUCCESS)
10722	LogFlow(("IEMExecOne: cs:rip=%04x:%08RX64 ss:rsp=%04x:%08RX64 EFL=%06x - rcStrict=%Rrc\n",
10723	pCtx->cs.Sel, pCtx->rip, pCtx->ss.Sel, pCtx->rsp, pCtx->eflags.u, VBOXSTRICTRC_VAL(rcStrict)));
10724	return rcStrict;
10725	}
10726
10727
10728	VMMDECL(VBOXSTRICTRC) IEMExecOneEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten)
10729	{
10730	PIEMCPU pIemCpu = &pVCpu->iem.s;
10731	PCPUMCTX pCtx = pVCpu->iem.s.CTX_SUFF(pCtx);
10732	AssertReturn(CPUMCTX2CORE(pCtx) == pCtxCore, VERR_IEM_IPE_3);
10733
10734	uint32_t const cbOldWritten = pIemCpu->cbWritten;
10735	VBOXSTRICTRC rcStrict = iemInitDecoderAndPrefetchOpcodes(pIemCpu, false);
10736	if (rcStrict == VINF_SUCCESS)
10737	{
10738	rcStrict = iemExecOneInner(pVCpu, pIemCpu, true);
10739	if (pcbWritten)
10740	*pcbWritten = pIemCpu->cbWritten - cbOldWritten;
10741	}
10742
10743	#ifdef IN_RC
10744	rcStrict = iemRCRawMaybeReenter(pIemCpu, pVCpu, pCtx, rcStrict);
10745	#endif
10746	return rcStrict;
10747	}
10748
10749
10750	VMMDECL(VBOXSTRICTRC) IEMExecOneWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
10751	const void *pvOpcodeBytes, size_t cbOpcodeBytes)
10752	{
10753	PIEMCPU pIemCpu = &pVCpu->iem.s;
10754	PCPUMCTX pCtx = pVCpu->iem.s.CTX_SUFF(pCtx);
10755	AssertReturn(CPUMCTX2CORE(pCtx) == pCtxCore, VERR_IEM_IPE_3);
10756
10757	VBOXSTRICTRC rcStrict;
10758	if ( cbOpcodeBytes
10759	&& pCtx->rip == OpcodeBytesPC)
10760	{
10761	iemInitDecoder(pIemCpu, false);
10762	pIemCpu->cbOpcode = (uint8_t)RT_MIN(cbOpcodeBytes, sizeof(pIemCpu->abOpcode));
10763	memcpy(pIemCpu->abOpcode, pvOpcodeBytes, pIemCpu->cbOpcode);
10764	rcStrict = VINF_SUCCESS;
10765	}
10766	else
10767	rcStrict = iemInitDecoderAndPrefetchOpcodes(pIemCpu, false);
10768	if (rcStrict == VINF_SUCCESS)
10769	{
10770	rcStrict = iemExecOneInner(pVCpu, pIemCpu, true);
10771	}
10772
10773	#ifdef IN_RC
10774	rcStrict = iemRCRawMaybeReenter(pIemCpu, pVCpu, pCtx, rcStrict);
10775	#endif
10776	return rcStrict;
10777	}
10778
10779
10780	VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten)
10781	{
10782	PIEMCPU pIemCpu = &pVCpu->iem.s;
10783	PCPUMCTX pCtx = pVCpu->iem.s.CTX_SUFF(pCtx);
10784	AssertReturn(CPUMCTX2CORE(pCtx) == pCtxCore, VERR_IEM_IPE_3);
10785
10786	uint32_t const cbOldWritten = pIemCpu->cbWritten;
10787	VBOXSTRICTRC rcStrict = iemInitDecoderAndPrefetchOpcodes(pIemCpu, true);
10788	if (rcStrict == VINF_SUCCESS)
10789	{
10790	rcStrict = iemExecOneInner(pVCpu, pIemCpu, false);
10791	if (pcbWritten)
10792	*pcbWritten = pIemCpu->cbWritten - cbOldWritten;
10793	}
10794
10795	#ifdef IN_RC
10796	rcStrict = iemRCRawMaybeReenter(pIemCpu, pVCpu, pCtx, rcStrict);
10797	#endif
10798	return rcStrict;
10799	}
10800
10801
10802	VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
10803	const void *pvOpcodeBytes, size_t cbOpcodeBytes)
10804	{
10805	PIEMCPU pIemCpu = &pVCpu->iem.s;
10806	PCPUMCTX pCtx = pVCpu->iem.s.CTX_SUFF(pCtx);
10807	AssertReturn(CPUMCTX2CORE(pCtx) == pCtxCore, VERR_IEM_IPE_3);
10808
10809	VBOXSTRICTRC rcStrict;
10810	if ( cbOpcodeBytes
10811	&& pCtx->rip == OpcodeBytesPC)
10812	{
10813	iemInitDecoder(pIemCpu, true);
10814	pIemCpu->cbOpcode = (uint8_t)RT_MIN(cbOpcodeBytes, sizeof(pIemCpu->abOpcode));
10815	memcpy(pIemCpu->abOpcode, pvOpcodeBytes, pIemCpu->cbOpcode);
10816	rcStrict = VINF_SUCCESS;
10817	}
10818	else
10819	rcStrict = iemInitDecoderAndPrefetchOpcodes(pIemCpu, true);
10820	if (rcStrict == VINF_SUCCESS)
10821	rcStrict = iemExecOneInner(pVCpu, pIemCpu, false);
10822
10823	#ifdef IN_RC
10824	rcStrict = iemRCRawMaybeReenter(pIemCpu, pVCpu, pCtx, rcStrict);
10825	#endif
10826	return rcStrict;
10827	}
10828
10829
10830	VMMDECL(VBOXSTRICTRC) IEMExecLots(PVMCPU pVCpu)
10831	{
10832	PIEMCPU pIemCpu = &pVCpu->iem.s;
10833
10834	/*
10835	* See if there is an interrupt pending in TRPM and inject it if we can.
10836	*/
10837	#if !defined(IEM_VERIFICATION_MODE_FULL) \|\| !defined(IN_RING3)
10838	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
10839	# ifdef IEM_VERIFICATION_MODE_FULL
10840	pIemCpu->uInjectCpl = UINT8_MAX;
10841	# endif
10842	if ( pCtx->eflags.Bits.u1IF
10843	&& TRPMHasTrap(pVCpu)
10844	&& EMGetInhibitInterruptsPC(pVCpu) != pCtx->rip)
10845	{
10846	uint8_t u8TrapNo;
10847	TRPMEVENT enmType;
10848	RTGCUINT uErrCode;
10849	RTGCPTR uCr2;
10850	int rc2 = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrCode, &uCr2, NULL /* pu8InstLen */); AssertRC(rc2);
10851	IEMInjectTrap(pVCpu, u8TrapNo, enmType, (uint16_t)uErrCode, uCr2, 0 /* cbInstr */);
10852	if (!IEM_VERIFICATION_ENABLED(pIemCpu))
10853	TRPMResetTrap(pVCpu);
10854	}
10855	#else
10856	iemExecVerificationModeSetup(pIemCpu);
10857	PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
10858	#endif
10859
10860	/*
10861	* Log the state.
10862	*/
10863	#ifdef LOG_ENABLED
10864	iemLogCurInstr(pVCpu, pCtx, true);
10865	#endif
10866
10867	/*
10868	* Do the decoding and emulation.
10869	*/
10870	VBOXSTRICTRC rcStrict = iemInitDecoderAndPrefetchOpcodes(pIemCpu, false);
10871	if (rcStrict == VINF_SUCCESS)
10872	rcStrict = iemExecOneInner(pVCpu, pIemCpu, true);
10873
10874	#if defined(IEM_VERIFICATION_MODE_FULL) && defined(IN_RING3)
10875	/*
10876	* Assert some sanity.
10877	*/
10878	iemExecVerificationModeCheck(pIemCpu);
10879	#endif
10880
10881	/*
10882	* Maybe re-enter raw-mode and log.
10883	*/
10884	#ifdef IN_RC
10885	rcStrict = iemRCRawMaybeReenter(pIemCpu, pVCpu, pIemCpu->CTX_SUFF(pCtx), rcStrict);
10886	#endif
10887	if (rcStrict != VINF_SUCCESS)
10888	LogFlow(("IEMExecLots: cs:rip=%04x:%08RX64 ss:rsp=%04x:%08RX64 EFL=%06x - rcStrict=%Rrc\n",
10889	pCtx->cs.Sel, pCtx->rip, pCtx->ss.Sel, pCtx->rsp, pCtx->eflags.u, VBOXSTRICTRC_VAL(rcStrict)));
10890	return rcStrict;
10891	}
10892
10893
10894
10895	/**
10896	* Injects a trap, fault, abort, software interrupt or external interrupt.
10897	*
10898	* The parameter list matches TRPMQueryTrapAll pretty closely.
10899	*
10900	* @returns Strict VBox status code.
10901	* @param pVCpu The current virtual CPU.
10902	* @param u8TrapNo The trap number.
10903	* @param enmType What type is it (trap/fault/abort), software
10904	* interrupt or hardware interrupt.
10905	* @param uErrCode The error code if applicable.
10906	* @param uCr2 The CR2 value if applicable.
10907	* @param cbInstr The instruction length (only relevant for
10908	* software interrupts).
10909	*/
10910	VMM_INT_DECL(VBOXSTRICTRC) IEMInjectTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType, uint16_t uErrCode, RTGCPTR uCr2,
10911	uint8_t cbInstr)
10912	{
10913	iemInitDecoder(&pVCpu->iem.s, false);
10914	#ifdef DBGFTRACE_ENABLED
10915	RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "IEMInjectTrap: %x %d %x %llx",
10916	u8TrapNo, enmType, uErrCode, uCr2);
10917	#endif
10918
10919	uint32_t fFlags;
10920	switch (enmType)
10921	{
10922	case TRPM_HARDWARE_INT:
10923	Log(("IEMInjectTrap: %#4x ext\n", u8TrapNo));
10924	fFlags = IEM_XCPT_FLAGS_T_EXT_INT;
10925	uErrCode = uCr2 = 0;
10926	break;
10927
10928	case TRPM_SOFTWARE_INT:
10929	Log(("IEMInjectTrap: %#4x soft\n", u8TrapNo));
10930	fFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
10931	uErrCode = uCr2 = 0;
10932	break;
10933
10934	case TRPM_TRAP:
10935	Log(("IEMInjectTrap: %#4x trap err=%#x cr2=%#RGv\n", u8TrapNo, uErrCode, uCr2));
10936	fFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
10937	if (u8TrapNo == X86_XCPT_PF)
10938	fFlags \|= IEM_XCPT_FLAGS_CR2;
10939	switch (u8TrapNo)
10940	{
10941	case X86_XCPT_DF:
10942	case X86_XCPT_TS:
10943	case X86_XCPT_NP:
10944	case X86_XCPT_SS:
10945	case X86_XCPT_PF:
10946	case X86_XCPT_AC:
10947	fFlags \|= IEM_XCPT_FLAGS_ERR;
10948	break;
10949
10950	case X86_XCPT_NMI:
10951	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
10952	break;
10953	}
10954	break;
10955
10956	IEM_NOT_REACHED_DEFAULT_CASE_RET();
10957	}
10958
10959	return iemRaiseXcptOrInt(&pVCpu->iem.s, cbInstr, u8TrapNo, fFlags, uErrCode, uCr2);
10960	}
10961
10962
10963	/**
10964	* Injects the active TRPM event.
10965	*
10966	* @returns Strict VBox status code.
10967	* @param pVCpu Pointer to the VMCPU.
10968	*/
10969	VMMDECL(VBOXSTRICTRC) IEMInjectTrpmEvent(PVMCPU pVCpu)
10970	{
10971	#ifndef IEM_IMPLEMENTS_TASKSWITCH
10972	IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(("Event injection\n"));
10973	#else
10974	uint8_t u8TrapNo;
10975	TRPMEVENT enmType;
10976	RTGCUINT uErrCode;
10977	RTGCUINTPTR uCr2;
10978	uint8_t cbInstr;
10979	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrCode, &uCr2, &cbInstr);
10980	if (RT_FAILURE(rc))
10981	return rc;
10982
10983	VBOXSTRICTRC rcStrict = IEMInjectTrap(pVCpu, u8TrapNo, enmType, uErrCode, uCr2, cbInstr);
10984
10985	/** @todo Are there any other codes that imply the event was successfully
10986	* delivered to the guest? See @bugref{6607}. */
10987	if ( rcStrict == VINF_SUCCESS
10988	\|\| rcStrict == VINF_IEM_RAISED_XCPT)
10989	{
10990	TRPMResetTrap(pVCpu);
10991	}
10992	return rcStrict;
10993	#endif
10994	}
10995
10996
10997	VMM_INT_DECL(int) IEMBreakpointSet(PVM pVM, RTGCPTR GCPtrBp)
10998	{
10999	return VERR_NOT_IMPLEMENTED;
11000	}
11001
11002
11003	VMM_INT_DECL(int) IEMBreakpointClear(PVM pVM, RTGCPTR GCPtrBp)
11004	{
11005	return VERR_NOT_IMPLEMENTED;
11006	}
11007
11008
11009	#if 0 /* The IRET-to-v8086 mode in PATM is very optimistic, so I don't dare do this yet. */
11010	/**
11011	* Executes a IRET instruction with default operand size.
11012	*
11013	* This is for PATM.
11014	*
11015	* @returns VBox status code.
11016	* @param pVCpu The current virtual CPU.
11017	* @param pCtxCore The register frame.
11018	*/
11019	VMM_INT_DECL(int) IEMExecInstr_iret(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
11020	{
11021	PIEMCPU pIemCpu = &pVCpu->iem.s;
11022	PCPUMCTX pCtx = pVCpu->iem.s.CTX_SUFF(pCtx);
11023
11024	iemCtxCoreToCtx(pCtx, pCtxCore);
11025	iemInitDecoder(pIemCpu);
11026	VBOXSTRICTRC rcStrict = iemCImpl_iret(pIemCpu, 1, pIemCpu->enmDefOpSize);
11027	if (rcStrict == VINF_SUCCESS)
11028	iemCtxToCtxCore(pCtxCore, pCtx);
11029	else
11030	LogFlow(("IEMExecInstr_iret: cs:rip=%04x:%08RX64 ss:rsp=%04x:%08RX64 EFL=%06x - rcStrict=%Rrc\n",
11031	pCtx->cs, pCtx->rip, pCtx->ss, pCtx->rsp, pCtx->eflags.u, VBOXSTRICTRC_VAL(rcStrict)));
11032	return rcStrict;
11033	}
11034	#endif
11035
11036
11037
11038	/**
11039	* Interface for HM and EM for executing string I/O OUT (write) instructions.
11040	*
11041	* This API ASSUMES that the caller has already verified that the guest code is
11042	* allowed to access the I/O port. (The I/O port is in the DX register in the
11043	* guest state.)
11044	*
11045	* @returns Strict VBox status code.
11046	* @param pVCpu The cross context per virtual CPU structure.
11047	* @param cbValue The size of the I/O port access (1, 2, or 4).
11048	* @param enmAddrMode The addressing mode.
11049	* @param fRepPrefix Indicates whether a repeat prefix is used
11050	* (doesn't matter which for this instruction).
11051	* @param cbInstr The instruction length in bytes.
11052	* @param iEffSeg The effective segment address.
11053	*/
11054	VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoWrite(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
11055	bool fRepPrefix, uint8_t cbInstr, uint8_t iEffSeg)
11056	{
11057	AssertMsgReturn(iEffSeg < X86_SREG_COUNT, ("%#x\n", iEffSeg), VERR_IEM_INVALID_EFF_SEG);
11058	AssertReturn(cbInstr - 1U <= 14U, VERR_IEM_INVALID_INSTR_LENGTH);
11059
11060	/*
11061	* State init.
11062	*/
11063	PIEMCPU pIemCpu = &pVCpu->iem.s;
11064	iemInitExec(pIemCpu, false /fBypassHandlers/);
11065
11066	/*
11067	* Switch orgy for getting to the right handler.
11068	*/
11069	VBOXSTRICTRC rcStrict;
11070	if (fRepPrefix)
11071	{
11072	switch (enmAddrMode)
11073	{
11074	case IEMMODE_16BIT:
11075	switch (cbValue)
11076	{
11077	case 1: rcStrict = iemCImpl_rep_outs_op8_addr16(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11078	case 2: rcStrict = iemCImpl_rep_outs_op16_addr16(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11079	case 4: rcStrict = iemCImpl_rep_outs_op32_addr16(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11080	default:
11081	AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_IEM_INVALID_OPERAND_SIZE);
11082	}
11083	break;
11084
11085	case IEMMODE_32BIT:
11086	switch (cbValue)
11087	{
11088	case 1: rcStrict = iemCImpl_rep_outs_op8_addr32(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11089	case 2: rcStrict = iemCImpl_rep_outs_op16_addr32(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11090	case 4: rcStrict = iemCImpl_rep_outs_op32_addr32(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11091	default:
11092	AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_IEM_INVALID_OPERAND_SIZE);
11093	}
11094	break;
11095
11096	case IEMMODE_64BIT:
11097	switch (cbValue)
11098	{
11099	case 1: rcStrict = iemCImpl_rep_outs_op8_addr64(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11100	case 2: rcStrict = iemCImpl_rep_outs_op16_addr64(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11101	case 4: rcStrict = iemCImpl_rep_outs_op32_addr64(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11102	default:
11103	AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_IEM_INVALID_OPERAND_SIZE);
11104	}
11105	break;
11106
11107	default:
11108	AssertMsgFailedReturn(("enmAddrMode=%d\n", enmAddrMode), VERR_IEM_INVALID_ADDRESS_MODE);
11109	}
11110	}
11111	else
11112	{
11113	switch (enmAddrMode)
11114	{
11115	case IEMMODE_16BIT:
11116	switch (cbValue)
11117	{
11118	case 1: rcStrict = iemCImpl_outs_op8_addr16(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11119	case 2: rcStrict = iemCImpl_outs_op16_addr16(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11120	case 4: rcStrict = iemCImpl_outs_op32_addr16(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11121	default:
11122	AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_IEM_INVALID_OPERAND_SIZE);
11123	}
11124	break;
11125
11126	case IEMMODE_32BIT:
11127	switch (cbValue)
11128	{
11129	case 1: rcStrict = iemCImpl_outs_op8_addr32(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11130	case 2: rcStrict = iemCImpl_outs_op16_addr32(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11131	case 4: rcStrict = iemCImpl_outs_op32_addr32(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11132	default:
11133	AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_IEM_INVALID_OPERAND_SIZE);
11134	}
11135	break;
11136
11137	case IEMMODE_64BIT:
11138	switch (cbValue)
11139	{
11140	case 1: rcStrict = iemCImpl_outs_op8_addr64(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11141	case 2: rcStrict = iemCImpl_outs_op16_addr64(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11142	case 4: rcStrict = iemCImpl_outs_op32_addr64(pIemCpu, cbInstr, iEffSeg, true /fIoChecked/); break;
11143	default:
11144	AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_IEM_INVALID_OPERAND_SIZE);
11145	}
11146	break;
11147
11148	default:
11149	AssertMsgFailedReturn(("enmAddrMode=%d\n", enmAddrMode), VERR_IEM_INVALID_ADDRESS_MODE);
11150	}
11151	}
11152
11153	return iemExecStatusCodeFiddling(pIemCpu, rcStrict);
11154	}
11155
11156
11157	/**
11158	* Interface for HM and EM for executing string I/O IN (read) instructions.
11159	*
11160	* This API ASSUMES that the caller has already verified that the guest code is
11161	* allowed to access the I/O port. (The I/O port is in the DX register in the
11162	* guest state.)
11163	*
11164	* @returns Strict VBox status code.
11165	* @param pVCpu The cross context per virtual CPU structure.
11166	* @param cbValue The size of the I/O port access (1, 2, or 4).
11167	* @param enmAddrMode The addressing mode.
11168	* @param fRepPrefix Indicates whether a repeat prefix is used
11169	* (doesn't matter which for this instruction).
11170	* @param cbInstr The instruction length in bytes.
11171	*/
11172	VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoRead(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
11173	bool fRepPrefix, uint8_t cbInstr)
11174	{
11175	AssertReturn(cbInstr - 1U <= 14U, VERR_IEM_INVALID_INSTR_LENGTH);
11176
11177	/*
11178	* State init.
11179	*/
11180	PIEMCPU pIemCpu = &pVCpu->iem.s;
11181	iemInitExec(pIemCpu, false /fBypassHandlers/);
11182
11183	/*
11184	* Switch orgy for getting to the right handler.
11185	*/
11186	VBOXSTRICTRC rcStrict;
11187	if (fRepPrefix)
11188	{
11189	switch (enmAddrMode)
11190	{
11191	case IEMMODE_16BIT:
11192	switch (cbValue)
11193	{
11194	case 1: rcStrict = iemCImpl_rep_ins_op8_addr16(pIemCpu, cbInstr, true /fIoChecked/); break;
11195	case 2: rcStrict = iemCImpl_rep_ins_op16_addr16(pIemCpu, cbInstr, true /fIoChecked/); break;
11196	case 4: rcStrict = iemCImpl_rep_ins_op32_addr16(pIemCpu, cbInstr, true /fIoChecked/); break;
11197	default:
11198	AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_IEM_INVALID_OPERAND_SIZE);
11199	}
11200	break;
11201
11202	case IEMMODE_32BIT:
11203	switch (cbValue)
11204	{
11205	case 1: rcStrict = iemCImpl_rep_ins_op8_addr32(pIemCpu, cbInstr, true /fIoChecked/); break;
11206	case 2: rcStrict = iemCImpl_rep_ins_op16_addr32(pIemCpu, cbInstr, true /fIoChecked/); break;
11207	case 4: rcStrict = iemCImpl_rep_ins_op32_addr32(pIemCpu, cbInstr, true /fIoChecked/); break;
11208	default:
11209	AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_IEM_INVALID_OPERAND_SIZE);
11210	}
11211	break;
11212
11213	case IEMMODE_64BIT:
11214	switch (cbValue)
11215	{
11216	case 1: rcStrict = iemCImpl_rep_ins_op8_addr64(pIemCpu, cbInstr, true /fIoChecked/); break;
11217	case 2: rcStrict = iemCImpl_rep_ins_op16_addr64(pIemCpu, cbInstr, true /fIoChecked/); break;
11218	case 4: rcStrict = iemCImpl_rep_ins_op32_addr64(pIemCpu, cbInstr, true /fIoChecked/); break;
11219	default:
11220	AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_IEM_INVALID_OPERAND_SIZE);
11221	}
11222	break;
11223
11224	default:
11225	AssertMsgFailedReturn(("enmAddrMode=%d\n", enmAddrMode), VERR_IEM_INVALID_ADDRESS_MODE);
11226	}
11227	}
11228	else
11229	{
11230	switch (enmAddrMode)
11231	{
11232	case IEMMODE_16BIT:
11233	switch (cbValue)
11234	{
11235	case 1: rcStrict = iemCImpl_ins_op8_addr16(pIemCpu, cbInstr, true /fIoChecked/); break;
11236	case 2: rcStrict = iemCImpl_ins_op16_addr16(pIemCpu, cbInstr, true /fIoChecked/); break;
11237	case 4: rcStrict = iemCImpl_ins_op32_addr16(pIemCpu, cbInstr, true /fIoChecked/); break;
11238	default:
11239	AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_IEM_INVALID_OPERAND_SIZE);
11240	}
11241	break;
11242
11243	case IEMMODE_32BIT:
11244	switch (cbValue)
11245	{
11246	case 1: rcStrict = iemCImpl_ins_op8_addr32(pIemCpu, cbInstr, true /fIoChecked/); break;
11247	case 2: rcStrict = iemCImpl_ins_op16_addr32(pIemCpu, cbInstr, true /fIoChecked/); break;
11248	case 4: rcStrict = iemCImpl_ins_op32_addr32(pIemCpu, cbInstr, true /fIoChecked/); break;
11249	default:
11250	AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_IEM_INVALID_OPERAND_SIZE);
11251	}
11252	break;
11253
11254	case IEMMODE_64BIT:
11255	switch (cbValue)
11256	{
11257	case 1: rcStrict = iemCImpl_ins_op8_addr64(pIemCpu, cbInstr, true /fIoChecked/); break;
11258	case 2: rcStrict = iemCImpl_ins_op16_addr64(pIemCpu, cbInstr, true /fIoChecked/); break;
11259	case 4: rcStrict = iemCImpl_ins_op32_addr64(pIemCpu, cbInstr, true /fIoChecked/); break;
11260	default:
11261	AssertMsgFailedReturn(("cbValue=%#x\n", cbValue), VERR_IEM_INVALID_OPERAND_SIZE);
11262	}
11263	break;
11264
11265	default:
11266	AssertMsgFailedReturn(("enmAddrMode=%d\n", enmAddrMode), VERR_IEM_INVALID_ADDRESS_MODE);
11267	}
11268	}
11269
11270	return iemExecStatusCodeFiddling(pIemCpu, rcStrict);
11271	}
11272

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAll.cpp@ 53466

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