VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h@ 60034

Last change on this file since 60034 was 59563, checked in by vboxsync, 9 years ago

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1/* $Id: IEMAllCImpl.cpp.h 59563 2016-02-02 18:26:24Z vboxsync $ */
2/** @file
3 * IEM - Instruction Implementation in C/C++ (code include).
4 */
5
6/*
7 * Copyright (C) 2011-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/** @name Misc Helpers
20 * @{
21 */
22
23
24/**
25 * Worker function for iemHlpCheckPortIOPermission, don't call directly.
26 *
27 * @returns Strict VBox status code.
28 *
29 * @param pIemCpu The IEM per CPU data.
30 * @param pCtx The register context.
31 * @param u16Port The port number.
32 * @param cbOperand The operand size.
33 */
34static VBOXSTRICTRC iemHlpCheckPortIOPermissionBitmap(PIEMCPU pIemCpu, PCCPUMCTX pCtx, uint16_t u16Port, uint8_t cbOperand)
35{
36 /* The TSS bits we're interested in are the same on 386 and AMD64. */
37 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_BUSY == X86_SEL_TYPE_SYS_386_TSS_BUSY);
38 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_AVAIL == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
39 AssertCompileMembersAtSameOffset(X86TSS32, offIoBitmap, X86TSS64, offIoBitmap);
40 AssertCompile(sizeof(X86TSS32) == sizeof(X86TSS64));
41
42 /*
43 * Check the TSS type, 16-bit TSSes doesn't have any I/O permission bitmap.
44 */
45 Assert(!pCtx->tr.Attr.n.u1DescType);
46 if (RT_UNLIKELY( pCtx->tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_BUSY
47 && pCtx->tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_AVAIL))
48 {
49 Log(("iemHlpCheckPortIOPermissionBitmap: Port=%#x cb=%d - TSS type %#x (attr=%#x) has no I/O bitmap -> #GP(0)\n",
50 u16Port, cbOperand, pCtx->tr.Attr.n.u4Type, pCtx->tr.Attr.u));
51 return iemRaiseGeneralProtectionFault0(pIemCpu);
52 }
53
54 /*
55 * Read the bitmap offset (may #PF).
56 */
57 uint16_t offBitmap;
58 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pIemCpu, &offBitmap, UINT8_MAX,
59 pCtx->tr.u64Base + RT_OFFSETOF(X86TSS64, offIoBitmap));
60 if (rcStrict != VINF_SUCCESS)
61 {
62 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading offIoBitmap (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
63 return rcStrict;
64 }
65
66 /*
67 * The bit range from u16Port to (u16Port + cbOperand - 1), however intel
68 * describes the CPU actually reading two bytes regardless of whether the
69 * bit range crosses a byte boundrary. Thus the + 1 in the test below.
70 */
71 uint32_t offFirstBit = (uint32_t)u16Port / 8 + offBitmap;
72 /** @todo check if real CPUs ensures that offBitmap has a minimum value of
73 * for instance sizeof(X86TSS32). */
74 if (offFirstBit + 1 > pCtx->tr.u32Limit) /* the limit is inclusive */
75 {
76 Log(("iemHlpCheckPortIOPermissionBitmap: offFirstBit=%#x + 1 is beyond u32Limit=%#x -> #GP(0)\n",
77 offFirstBit, pCtx->tr.u32Limit));
78 return iemRaiseGeneralProtectionFault0(pIemCpu);
79 }
80
81 /*
82 * Read the necessary bits.
83 */
84 /** @todo Test the assertion in the intel manual that the CPU reads two
85 * bytes. The question is how this works wrt to #PF and #GP on the
86 * 2nd byte when it's not required. */
87 uint16_t bmBytes = UINT16_MAX;
88 rcStrict = iemMemFetchSysU16(pIemCpu, &bmBytes, UINT8_MAX, pCtx->tr.u64Base + offFirstBit);
89 if (rcStrict != VINF_SUCCESS)
90 {
91 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading I/O bitmap @%#x (%Rrc)\n", offFirstBit, VBOXSTRICTRC_VAL(rcStrict)));
92 return rcStrict;
93 }
94
95 /*
96 * Perform the check.
97 */
98 uint16_t fPortMask = (1 << cbOperand) - 1;
99 bmBytes >>= (u16Port & 7);
100 if (bmBytes & fPortMask)
101 {
102 Log(("iemHlpCheckPortIOPermissionBitmap: u16Port=%#x LB %u - access denied (bm=%#x mask=%#x) -> #GP(0)\n",
103 u16Port, cbOperand, bmBytes, fPortMask));
104 return iemRaiseGeneralProtectionFault0(pIemCpu);
105 }
106
107 return VINF_SUCCESS;
108}
109
110
111/**
112 * Checks if we are allowed to access the given I/O port, raising the
113 * appropriate exceptions if we aren't (or if the I/O bitmap is not
114 * accessible).
115 *
116 * @returns Strict VBox status code.
117 *
118 * @param pIemCpu The IEM per CPU data.
119 * @param pCtx The register context.
120 * @param u16Port The port number.
121 * @param cbOperand The operand size.
122 */
123DECLINLINE(VBOXSTRICTRC) iemHlpCheckPortIOPermission(PIEMCPU pIemCpu, PCCPUMCTX pCtx, uint16_t u16Port, uint8_t cbOperand)
124{
125 X86EFLAGS Efl;
126 Efl.u = IEMMISC_GET_EFL(pIemCpu, pCtx);
127 if ( (pCtx->cr0 & X86_CR0_PE)
128 && ( pIemCpu->uCpl > Efl.Bits.u2IOPL
129 || Efl.Bits.u1VM) )
130 return iemHlpCheckPortIOPermissionBitmap(pIemCpu, pCtx, u16Port, cbOperand);
131 return VINF_SUCCESS;
132}
133
134
135#if 0
136/**
137 * Calculates the parity bit.
138 *
139 * @returns true if the bit is set, false if not.
140 * @param u8Result The least significant byte of the result.
141 */
142static bool iemHlpCalcParityFlag(uint8_t u8Result)
143{
144 /*
145 * Parity is set if the number of bits in the least significant byte of
146 * the result is even.
147 */
148 uint8_t cBits;
149 cBits = u8Result & 1; /* 0 */
150 u8Result >>= 1;
151 cBits += u8Result & 1;
152 u8Result >>= 1;
153 cBits += u8Result & 1;
154 u8Result >>= 1;
155 cBits += u8Result & 1;
156 u8Result >>= 1;
157 cBits += u8Result & 1; /* 4 */
158 u8Result >>= 1;
159 cBits += u8Result & 1;
160 u8Result >>= 1;
161 cBits += u8Result & 1;
162 u8Result >>= 1;
163 cBits += u8Result & 1;
164 return !(cBits & 1);
165}
166#endif /* not used */
167
168
169/**
170 * Updates the specified flags according to a 8-bit result.
171 *
172 * @param pIemCpu The IEM state of the calling EMT.
173 * @param u8Result The result to set the flags according to.
174 * @param fToUpdate The flags to update.
175 * @param fUndefined The flags that are specified as undefined.
176 */
177static void iemHlpUpdateArithEFlagsU8(PIEMCPU pIemCpu, uint8_t u8Result, uint32_t fToUpdate, uint32_t fUndefined)
178{
179 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
180
181 uint32_t fEFlags = pCtx->eflags.u;
182 iemAImpl_test_u8(&u8Result, u8Result, &fEFlags);
183 pCtx->eflags.u &= ~(fToUpdate | fUndefined);
184 pCtx->eflags.u |= (fToUpdate | fUndefined) & fEFlags;
185#ifdef IEM_VERIFICATION_MODE_FULL
186 pIemCpu->fUndefinedEFlags |= fUndefined;
187#endif
188}
189
190
191/**
192 * Helper used by iret.
193 *
194 * @param uCpl The new CPL.
195 * @param pSReg Pointer to the segment register.
196 */
197static void iemHlpAdjustSelectorForNewCpl(PIEMCPU pIemCpu, uint8_t uCpl, PCPUMSELREG pSReg)
198{
199#ifdef VBOX_WITH_RAW_MODE_NOT_R0
200 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(IEMCPU_TO_VMCPU(pIemCpu), pSReg))
201 CPUMGuestLazyLoadHiddenSelectorReg(IEMCPU_TO_VMCPU(pIemCpu), pSReg);
202#else
203 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(IEMCPU_TO_VMCPU(pIemCpu), pSReg));
204#endif
205
206 if ( uCpl > pSReg->Attr.n.u2Dpl
207 && pSReg->Attr.n.u1DescType /* code or data, not system */
208 && (pSReg->Attr.n.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
209 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) /* not conforming code */
210 iemHlpLoadNullDataSelectorProt(pIemCpu, pSReg, 0);
211}
212
213
214/**
215 * Indicates that we have modified the FPU state.
216 *
217 * @param pIemCpu The IEM state of the calling EMT.
218 */
219DECLINLINE(void) iemHlpUsedFpu(PIEMCPU pIemCpu)
220{
221 CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_FPU_REM);
222}
223
224/** @} */
225
226/** @name C Implementations
227 * @{
228 */
229
230/**
231 * Implements a 16-bit popa.
232 */
233IEM_CIMPL_DEF_0(iemCImpl_popa_16)
234{
235 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
236 RTGCPTR GCPtrStart = iemRegGetEffRsp(pIemCpu, pCtx);
237 RTGCPTR GCPtrLast = GCPtrStart + 15;
238 VBOXSTRICTRC rcStrict;
239
240 /*
241 * The docs are a bit hard to comprehend here, but it looks like we wrap
242 * around in real mode as long as none of the individual "popa" crosses the
243 * end of the stack segment. In protected mode we check the whole access
244 * in one go. For efficiency, only do the word-by-word thing if we're in
245 * danger of wrapping around.
246 */
247 /** @todo do popa boundary / wrap-around checks. */
248 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pIemCpu)
249 && (pCtx->cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
250 {
251 /* word-by-word */
252 RTUINT64U TmpRsp;
253 TmpRsp.u = pCtx->rsp;
254 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->di, &TmpRsp);
255 if (rcStrict == VINF_SUCCESS)
256 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->si, &TmpRsp);
257 if (rcStrict == VINF_SUCCESS)
258 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->bp, &TmpRsp);
259 if (rcStrict == VINF_SUCCESS)
260 {
261 iemRegAddToRspEx(pIemCpu, pCtx, &TmpRsp, 2); /* sp */
262 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->bx, &TmpRsp);
263 }
264 if (rcStrict == VINF_SUCCESS)
265 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->dx, &TmpRsp);
266 if (rcStrict == VINF_SUCCESS)
267 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->cx, &TmpRsp);
268 if (rcStrict == VINF_SUCCESS)
269 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->ax, &TmpRsp);
270 if (rcStrict == VINF_SUCCESS)
271 {
272 pCtx->rsp = TmpRsp.u;
273 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
274 }
275 }
276 else
277 {
278 uint16_t const *pa16Mem = NULL;
279 rcStrict = iemMemMap(pIemCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R);
280 if (rcStrict == VINF_SUCCESS)
281 {
282 pCtx->di = pa16Mem[7 - X86_GREG_xDI];
283 pCtx->si = pa16Mem[7 - X86_GREG_xSI];
284 pCtx->bp = pa16Mem[7 - X86_GREG_xBP];
285 /* skip sp */
286 pCtx->bx = pa16Mem[7 - X86_GREG_xBX];
287 pCtx->dx = pa16Mem[7 - X86_GREG_xDX];
288 pCtx->cx = pa16Mem[7 - X86_GREG_xCX];
289 pCtx->ax = pa16Mem[7 - X86_GREG_xAX];
290 rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)pa16Mem, IEM_ACCESS_STACK_R);
291 if (rcStrict == VINF_SUCCESS)
292 {
293 iemRegAddToRsp(pIemCpu, pCtx, 16);
294 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
295 }
296 }
297 }
298 return rcStrict;
299}
300
301
302/**
303 * Implements a 32-bit popa.
304 */
305IEM_CIMPL_DEF_0(iemCImpl_popa_32)
306{
307 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
308 RTGCPTR GCPtrStart = iemRegGetEffRsp(pIemCpu, pCtx);
309 RTGCPTR GCPtrLast = GCPtrStart + 31;
310 VBOXSTRICTRC rcStrict;
311
312 /*
313 * The docs are a bit hard to comprehend here, but it looks like we wrap
314 * around in real mode as long as none of the individual "popa" crosses the
315 * end of the stack segment. In protected mode we check the whole access
316 * in one go. For efficiency, only do the word-by-word thing if we're in
317 * danger of wrapping around.
318 */
319 /** @todo do popa boundary / wrap-around checks. */
320 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pIemCpu)
321 && (pCtx->cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
322 {
323 /* word-by-word */
324 RTUINT64U TmpRsp;
325 TmpRsp.u = pCtx->rsp;
326 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->edi, &TmpRsp);
327 if (rcStrict == VINF_SUCCESS)
328 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->esi, &TmpRsp);
329 if (rcStrict == VINF_SUCCESS)
330 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->ebp, &TmpRsp);
331 if (rcStrict == VINF_SUCCESS)
332 {
333 iemRegAddToRspEx(pIemCpu, pCtx, &TmpRsp, 2); /* sp */
334 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->ebx, &TmpRsp);
335 }
336 if (rcStrict == VINF_SUCCESS)
337 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->edx, &TmpRsp);
338 if (rcStrict == VINF_SUCCESS)
339 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->ecx, &TmpRsp);
340 if (rcStrict == VINF_SUCCESS)
341 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->eax, &TmpRsp);
342 if (rcStrict == VINF_SUCCESS)
343 {
344#if 1 /** @todo what actually happens with the high bits when we're in 16-bit mode? */
345 pCtx->rdi &= UINT32_MAX;
346 pCtx->rsi &= UINT32_MAX;
347 pCtx->rbp &= UINT32_MAX;
348 pCtx->rbx &= UINT32_MAX;
349 pCtx->rdx &= UINT32_MAX;
350 pCtx->rcx &= UINT32_MAX;
351 pCtx->rax &= UINT32_MAX;
352#endif
353 pCtx->rsp = TmpRsp.u;
354 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
355 }
356 }
357 else
358 {
359 uint32_t const *pa32Mem;
360 rcStrict = iemMemMap(pIemCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R);
361 if (rcStrict == VINF_SUCCESS)
362 {
363 pCtx->rdi = pa32Mem[7 - X86_GREG_xDI];
364 pCtx->rsi = pa32Mem[7 - X86_GREG_xSI];
365 pCtx->rbp = pa32Mem[7 - X86_GREG_xBP];
366 /* skip esp */
367 pCtx->rbx = pa32Mem[7 - X86_GREG_xBX];
368 pCtx->rdx = pa32Mem[7 - X86_GREG_xDX];
369 pCtx->rcx = pa32Mem[7 - X86_GREG_xCX];
370 pCtx->rax = pa32Mem[7 - X86_GREG_xAX];
371 rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)pa32Mem, IEM_ACCESS_STACK_R);
372 if (rcStrict == VINF_SUCCESS)
373 {
374 iemRegAddToRsp(pIemCpu, pCtx, 32);
375 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
376 }
377 }
378 }
379 return rcStrict;
380}
381
382
383/**
384 * Implements a 16-bit pusha.
385 */
386IEM_CIMPL_DEF_0(iemCImpl_pusha_16)
387{
388 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
389 RTGCPTR GCPtrTop = iemRegGetEffRsp(pIemCpu, pCtx);
390 RTGCPTR GCPtrBottom = GCPtrTop - 15;
391 VBOXSTRICTRC rcStrict;
392
393 /*
394 * The docs are a bit hard to comprehend here, but it looks like we wrap
395 * around in real mode as long as none of the individual "pushd" crosses the
396 * end of the stack segment. In protected mode we check the whole access
397 * in one go. For efficiency, only do the word-by-word thing if we're in
398 * danger of wrapping around.
399 */
400 /** @todo do pusha boundary / wrap-around checks. */
401 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
402 && IEM_IS_REAL_OR_V86_MODE(pIemCpu) ) )
403 {
404 /* word-by-word */
405 RTUINT64U TmpRsp;
406 TmpRsp.u = pCtx->rsp;
407 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->ax, &TmpRsp);
408 if (rcStrict == VINF_SUCCESS)
409 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->cx, &TmpRsp);
410 if (rcStrict == VINF_SUCCESS)
411 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->dx, &TmpRsp);
412 if (rcStrict == VINF_SUCCESS)
413 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->bx, &TmpRsp);
414 if (rcStrict == VINF_SUCCESS)
415 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->sp, &TmpRsp);
416 if (rcStrict == VINF_SUCCESS)
417 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->bp, &TmpRsp);
418 if (rcStrict == VINF_SUCCESS)
419 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->si, &TmpRsp);
420 if (rcStrict == VINF_SUCCESS)
421 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->di, &TmpRsp);
422 if (rcStrict == VINF_SUCCESS)
423 {
424 pCtx->rsp = TmpRsp.u;
425 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
426 }
427 }
428 else
429 {
430 GCPtrBottom--;
431 uint16_t *pa16Mem = NULL;
432 rcStrict = iemMemMap(pIemCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W);
433 if (rcStrict == VINF_SUCCESS)
434 {
435 pa16Mem[7 - X86_GREG_xDI] = pCtx->di;
436 pa16Mem[7 - X86_GREG_xSI] = pCtx->si;
437 pa16Mem[7 - X86_GREG_xBP] = pCtx->bp;
438 pa16Mem[7 - X86_GREG_xSP] = pCtx->sp;
439 pa16Mem[7 - X86_GREG_xBX] = pCtx->bx;
440 pa16Mem[7 - X86_GREG_xDX] = pCtx->dx;
441 pa16Mem[7 - X86_GREG_xCX] = pCtx->cx;
442 pa16Mem[7 - X86_GREG_xAX] = pCtx->ax;
443 rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)pa16Mem, IEM_ACCESS_STACK_W);
444 if (rcStrict == VINF_SUCCESS)
445 {
446 iemRegSubFromRsp(pIemCpu, pCtx, 16);
447 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
448 }
449 }
450 }
451 return rcStrict;
452}
453
454
455/**
456 * Implements a 32-bit pusha.
457 */
458IEM_CIMPL_DEF_0(iemCImpl_pusha_32)
459{
460 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
461 RTGCPTR GCPtrTop = iemRegGetEffRsp(pIemCpu, pCtx);
462 RTGCPTR GCPtrBottom = GCPtrTop - 31;
463 VBOXSTRICTRC rcStrict;
464
465 /*
466 * The docs are a bit hard to comprehend here, but it looks like we wrap
467 * around in real mode as long as none of the individual "pusha" crosses the
468 * end of the stack segment. In protected mode we check the whole access
469 * in one go. For efficiency, only do the word-by-word thing if we're in
470 * danger of wrapping around.
471 */
472 /** @todo do pusha boundary / wrap-around checks. */
473 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
474 && IEM_IS_REAL_OR_V86_MODE(pIemCpu) ) )
475 {
476 /* word-by-word */
477 RTUINT64U TmpRsp;
478 TmpRsp.u = pCtx->rsp;
479 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->eax, &TmpRsp);
480 if (rcStrict == VINF_SUCCESS)
481 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->ecx, &TmpRsp);
482 if (rcStrict == VINF_SUCCESS)
483 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->edx, &TmpRsp);
484 if (rcStrict == VINF_SUCCESS)
485 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->ebx, &TmpRsp);
486 if (rcStrict == VINF_SUCCESS)
487 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->esp, &TmpRsp);
488 if (rcStrict == VINF_SUCCESS)
489 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->ebp, &TmpRsp);
490 if (rcStrict == VINF_SUCCESS)
491 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->esi, &TmpRsp);
492 if (rcStrict == VINF_SUCCESS)
493 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->edi, &TmpRsp);
494 if (rcStrict == VINF_SUCCESS)
495 {
496 pCtx->rsp = TmpRsp.u;
497 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
498 }
499 }
500 else
501 {
502 GCPtrBottom--;
503 uint32_t *pa32Mem;
504 rcStrict = iemMemMap(pIemCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W);
505 if (rcStrict == VINF_SUCCESS)
506 {
507 pa32Mem[7 - X86_GREG_xDI] = pCtx->edi;
508 pa32Mem[7 - X86_GREG_xSI] = pCtx->esi;
509 pa32Mem[7 - X86_GREG_xBP] = pCtx->ebp;
510 pa32Mem[7 - X86_GREG_xSP] = pCtx->esp;
511 pa32Mem[7 - X86_GREG_xBX] = pCtx->ebx;
512 pa32Mem[7 - X86_GREG_xDX] = pCtx->edx;
513 pa32Mem[7 - X86_GREG_xCX] = pCtx->ecx;
514 pa32Mem[7 - X86_GREG_xAX] = pCtx->eax;
515 rcStrict = iemMemCommitAndUnmap(pIemCpu, pa32Mem, IEM_ACCESS_STACK_W);
516 if (rcStrict == VINF_SUCCESS)
517 {
518 iemRegSubFromRsp(pIemCpu, pCtx, 32);
519 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
520 }
521 }
522 }
523 return rcStrict;
524}
525
526
527/**
528 * Implements pushf.
529 *
530 *
531 * @param enmEffOpSize The effective operand size.
532 */
533IEM_CIMPL_DEF_1(iemCImpl_pushf, IEMMODE, enmEffOpSize)
534{
535 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
536
537 /*
538 * If we're in V8086 mode some care is required (which is why we're in
539 * doing this in a C implementation).
540 */
541 uint32_t fEfl = IEMMISC_GET_EFL(pIemCpu, pCtx);
542 if ( (fEfl & X86_EFL_VM)
543 && X86_EFL_GET_IOPL(fEfl) != 3 )
544 {
545 Assert(pCtx->cr0 & X86_CR0_PE);
546 if ( enmEffOpSize != IEMMODE_16BIT
547 || !(pCtx->cr4 & X86_CR4_VME))
548 return iemRaiseGeneralProtectionFault0(pIemCpu);
549 fEfl &= ~X86_EFL_IF; /* (RF and VM are out of range) */
550 fEfl |= (fEfl & X86_EFL_VIF) >> (19 - 9);
551 return iemMemStackPushU16(pIemCpu, (uint16_t)fEfl);
552 }
553
554 /*
555 * Ok, clear RF and VM and push the flags.
556 */
557 fEfl &= ~(X86_EFL_RF | X86_EFL_VM);
558
559 VBOXSTRICTRC rcStrict;
560 switch (enmEffOpSize)
561 {
562 case IEMMODE_16BIT:
563 rcStrict = iemMemStackPushU16(pIemCpu, (uint16_t)fEfl);
564 break;
565 case IEMMODE_32BIT:
566 rcStrict = iemMemStackPushU32(pIemCpu, fEfl);
567 break;
568 case IEMMODE_64BIT:
569 rcStrict = iemMemStackPushU64(pIemCpu, fEfl);
570 break;
571 IEM_NOT_REACHED_DEFAULT_CASE_RET();
572 }
573 if (rcStrict != VINF_SUCCESS)
574 return rcStrict;
575
576 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
577 return VINF_SUCCESS;
578}
579
580
581/**
582 * Implements popf.
583 *
584 * @param enmEffOpSize The effective operand size.
585 */
586IEM_CIMPL_DEF_1(iemCImpl_popf, IEMMODE, enmEffOpSize)
587{
588 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
589 uint32_t const fEflOld = IEMMISC_GET_EFL(pIemCpu, pCtx);
590 VBOXSTRICTRC rcStrict;
591 uint32_t fEflNew;
592
593 /*
594 * V8086 is special as usual.
595 */
596 if (fEflOld & X86_EFL_VM)
597 {
598 /*
599 * Almost anything goes if IOPL is 3.
600 */
601 if (X86_EFL_GET_IOPL(fEflOld) == 3)
602 {
603 switch (enmEffOpSize)
604 {
605 case IEMMODE_16BIT:
606 {
607 uint16_t u16Value;
608 rcStrict = iemMemStackPopU16(pIemCpu, &u16Value);
609 if (rcStrict != VINF_SUCCESS)
610 return rcStrict;
611 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
612 break;
613 }
614 case IEMMODE_32BIT:
615 rcStrict = iemMemStackPopU32(pIemCpu, &fEflNew);
616 if (rcStrict != VINF_SUCCESS)
617 return rcStrict;
618 break;
619 IEM_NOT_REACHED_DEFAULT_CASE_RET();
620 }
621
622 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL);
623 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL)) & fEflOld;
624 }
625 /*
626 * Interrupt flag virtualization with CR4.VME=1.
627 */
628 else if ( enmEffOpSize == IEMMODE_16BIT
629 && (pCtx->cr4 & X86_CR4_VME) )
630 {
631 uint16_t u16Value;
632 RTUINT64U TmpRsp;
633 TmpRsp.u = pCtx->rsp;
634 rcStrict = iemMemStackPopU16Ex(pIemCpu, &u16Value, &TmpRsp);
635 if (rcStrict != VINF_SUCCESS)
636 return rcStrict;
637
638 /** @todo Is the popf VME #GP(0) delivered after updating RSP+RIP
639 * or before? */
640 if ( ( (u16Value & X86_EFL_IF)
641 && (fEflOld & X86_EFL_VIP))
642 || (u16Value & X86_EFL_TF) )
643 return iemRaiseGeneralProtectionFault0(pIemCpu);
644
645 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000) & ~X86_EFL_VIF);
646 fEflNew |= (fEflNew & X86_EFL_IF) << (19 - 9);
647 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF);
648 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
649
650 pCtx->rsp = TmpRsp.u;
651 }
652 else
653 return iemRaiseGeneralProtectionFault0(pIemCpu);
654
655 }
656 /*
657 * Not in V8086 mode.
658 */
659 else
660 {
661 /* Pop the flags. */
662 switch (enmEffOpSize)
663 {
664 case IEMMODE_16BIT:
665 {
666 uint16_t u16Value;
667 rcStrict = iemMemStackPopU16(pIemCpu, &u16Value);
668 if (rcStrict != VINF_SUCCESS)
669 return rcStrict;
670 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
671 break;
672 }
673 case IEMMODE_32BIT:
674 rcStrict = iemMemStackPopU32(pIemCpu, &fEflNew);
675 if (rcStrict != VINF_SUCCESS)
676 return rcStrict;
677 break;
678 case IEMMODE_64BIT:
679 {
680 uint64_t u64Value;
681 rcStrict = iemMemStackPopU64(pIemCpu, &u64Value);
682 if (rcStrict != VINF_SUCCESS)
683 return rcStrict;
684 fEflNew = u64Value; /** @todo testcase: Check exactly what happens if high bits are set. */
685 break;
686 }
687 IEM_NOT_REACHED_DEFAULT_CASE_RET();
688 }
689
690 /* Merge them with the current flags. */
691 if ( (fEflNew & (X86_EFL_IOPL | X86_EFL_IF)) == (fEflOld & (X86_EFL_IOPL | X86_EFL_IF))
692 || pIemCpu->uCpl == 0)
693 {
694 fEflNew &= X86_EFL_POPF_BITS;
695 fEflNew |= ~X86_EFL_POPF_BITS & fEflOld;
696 }
697 else if (pIemCpu->uCpl <= X86_EFL_GET_IOPL(fEflOld))
698 {
699 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL);
700 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL)) & fEflOld;
701 }
702 else
703 {
704 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF);
705 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
706 }
707 }
708
709 /*
710 * Commit the flags.
711 */
712 Assert(fEflNew & RT_BIT_32(1));
713 IEMMISC_SET_EFL(pIemCpu, pCtx, fEflNew);
714 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
715
716 return VINF_SUCCESS;
717}
718
719
720/**
721 * Implements an indirect call.
722 *
723 * @param uNewPC The new program counter (RIP) value (loaded from the
724 * operand).
725 * @param enmEffOpSize The effective operand size.
726 */
727IEM_CIMPL_DEF_1(iemCImpl_call_16, uint16_t, uNewPC)
728{
729 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
730 uint16_t uOldPC = pCtx->ip + cbInstr;
731 if (uNewPC > pCtx->cs.u32Limit)
732 return iemRaiseGeneralProtectionFault0(pIemCpu);
733
734 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pIemCpu, uOldPC);
735 if (rcStrict != VINF_SUCCESS)
736 return rcStrict;
737
738 pCtx->rip = uNewPC;
739 pCtx->eflags.Bits.u1RF = 0;
740 return VINF_SUCCESS;
741}
742
743
744/**
745 * Implements a 16-bit relative call.
746 *
747 * @param offDisp The displacment offset.
748 */
749IEM_CIMPL_DEF_1(iemCImpl_call_rel_16, int16_t, offDisp)
750{
751 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
752 uint16_t uOldPC = pCtx->ip + cbInstr;
753 uint16_t uNewPC = uOldPC + offDisp;
754 if (uNewPC > pCtx->cs.u32Limit)
755 return iemRaiseGeneralProtectionFault0(pIemCpu);
756
757 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pIemCpu, uOldPC);
758 if (rcStrict != VINF_SUCCESS)
759 return rcStrict;
760
761 pCtx->rip = uNewPC;
762 pCtx->eflags.Bits.u1RF = 0;
763 return VINF_SUCCESS;
764}
765
766
767/**
768 * Implements a 32-bit indirect call.
769 *
770 * @param uNewPC The new program counter (RIP) value (loaded from the
771 * operand).
772 * @param enmEffOpSize The effective operand size.
773 */
774IEM_CIMPL_DEF_1(iemCImpl_call_32, uint32_t, uNewPC)
775{
776 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
777 uint32_t uOldPC = pCtx->eip + cbInstr;
778 if (uNewPC > pCtx->cs.u32Limit)
779 return iemRaiseGeneralProtectionFault0(pIemCpu);
780
781 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pIemCpu, uOldPC);
782 if (rcStrict != VINF_SUCCESS)
783 return rcStrict;
784
785#if defined(IN_RING3) && defined(VBOX_WITH_RAW_MODE) && defined(VBOX_WITH_CALL_RECORD)
786 /*
787 * CASM hook for recording interesting indirect calls.
788 */
789 if ( !pCtx->eflags.Bits.u1IF
790 && (pCtx->cr0 & X86_CR0_PG)
791 && !CSAMIsEnabled(IEMCPU_TO_VM(pIemCpu))
792 && pIemCpu->uCpl == 0)
793 {
794 EMSTATE enmState = EMGetState(IEMCPU_TO_VMCPU(pIemCpu));
795 if ( enmState == EMSTATE_IEM_THEN_REM
796 || enmState == EMSTATE_IEM
797 || enmState == EMSTATE_REM)
798 CSAMR3RecordCallAddress(IEMCPU_TO_VM(pIemCpu), pCtx->eip);
799 }
800#endif
801
802 pCtx->rip = uNewPC;
803 pCtx->eflags.Bits.u1RF = 0;
804 return VINF_SUCCESS;
805}
806
807
808/**
809 * Implements a 32-bit relative call.
810 *
811 * @param offDisp The displacment offset.
812 */
813IEM_CIMPL_DEF_1(iemCImpl_call_rel_32, int32_t, offDisp)
814{
815 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
816 uint32_t uOldPC = pCtx->eip + cbInstr;
817 uint32_t uNewPC = uOldPC + offDisp;
818 if (uNewPC > pCtx->cs.u32Limit)
819 return iemRaiseGeneralProtectionFault0(pIemCpu);
820
821 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pIemCpu, uOldPC);
822 if (rcStrict != VINF_SUCCESS)
823 return rcStrict;
824
825 pCtx->rip = uNewPC;
826 pCtx->eflags.Bits.u1RF = 0;
827 return VINF_SUCCESS;
828}
829
830
831/**
832 * Implements a 64-bit indirect call.
833 *
834 * @param uNewPC The new program counter (RIP) value (loaded from the
835 * operand).
836 * @param enmEffOpSize The effective operand size.
837 */
838IEM_CIMPL_DEF_1(iemCImpl_call_64, uint64_t, uNewPC)
839{
840 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
841 uint64_t uOldPC = pCtx->rip + cbInstr;
842 if (!IEM_IS_CANONICAL(uNewPC))
843 return iemRaiseGeneralProtectionFault0(pIemCpu);
844
845 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pIemCpu, uOldPC);
846 if (rcStrict != VINF_SUCCESS)
847 return rcStrict;
848
849 pCtx->rip = uNewPC;
850 pCtx->eflags.Bits.u1RF = 0;
851 return VINF_SUCCESS;
852}
853
854
855/**
856 * Implements a 64-bit relative call.
857 *
858 * @param offDisp The displacment offset.
859 */
860IEM_CIMPL_DEF_1(iemCImpl_call_rel_64, int64_t, offDisp)
861{
862 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
863 uint64_t uOldPC = pCtx->rip + cbInstr;
864 uint64_t uNewPC = uOldPC + offDisp;
865 if (!IEM_IS_CANONICAL(uNewPC))
866 return iemRaiseNotCanonical(pIemCpu);
867
868 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pIemCpu, uOldPC);
869 if (rcStrict != VINF_SUCCESS)
870 return rcStrict;
871
872 pCtx->rip = uNewPC;
873 pCtx->eflags.Bits.u1RF = 0;
874 return VINF_SUCCESS;
875}
876
877
878/**
879 * Implements far jumps and calls thru task segments (TSS).
880 *
881 * @param uSel The selector.
882 * @param enmBranch The kind of branching we're performing.
883 * @param enmEffOpSize The effective operand size.
884 * @param pDesc The descriptor corresponding to @a uSel. The type is
885 * task gate.
886 */
887IEM_CIMPL_DEF_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
888{
889#ifndef IEM_IMPLEMENTS_TASKSWITCH
890 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
891#else
892 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
893 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL
894 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
895
896 if ( pDesc->Legacy.Gate.u2Dpl < pIemCpu->uCpl
897 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
898 {
899 Log(("BranchTaskSegment invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
900 pIemCpu->uCpl, (uSel & X86_SEL_RPL)));
901 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel & X86_SEL_MASK_OFF_RPL);
902 }
903
904 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
905 * far calls (see iemCImpl_callf). Most likely in both cases it should be
906 * checked here, need testcases. */
907 if (!pDesc->Legacy.Gen.u1Present)
908 {
909 Log(("BranchTaskSegment TSS not present uSel=%04x -> #NP\n", uSel));
910 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uSel & X86_SEL_MASK_OFF_RPL);
911 }
912
913 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
914 uint32_t uNextEip = pCtx->eip + cbInstr;
915 return iemTaskSwitch(pIemCpu, pIemCpu->CTX_SUFF(pCtx), enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
916 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSel, pDesc);
917#endif
918}
919
920
921/**
922 * Implements far jumps and calls thru task gates.
923 *
924 * @param uSel The selector.
925 * @param enmBranch The kind of branching we're performing.
926 * @param enmEffOpSize The effective operand size.
927 * @param pDesc The descriptor corresponding to @a uSel. The type is
928 * task gate.
929 */
930IEM_CIMPL_DEF_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
931{
932#ifndef IEM_IMPLEMENTS_TASKSWITCH
933 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
934#else
935 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
936
937 if ( pDesc->Legacy.Gate.u2Dpl < pIemCpu->uCpl
938 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
939 {
940 Log(("BranchTaskGate invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
941 pIemCpu->uCpl, (uSel & X86_SEL_RPL)));
942 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel & X86_SEL_MASK_OFF_RPL);
943 }
944
945 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
946 * far calls (see iemCImpl_callf). Most likely in both cases it should be
947 * checked here, need testcases. */
948 if (!pDesc->Legacy.Gen.u1Present)
949 {
950 Log(("BranchTaskSegment segment not present uSel=%04x -> #NP\n", uSel));
951 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uSel & X86_SEL_MASK_OFF_RPL);
952 }
953
954 /*
955 * Fetch the new TSS descriptor from the GDT.
956 */
957 RTSEL uSelTss = pDesc->Legacy.Gate.u16Sel;
958 if (uSelTss & X86_SEL_LDT)
959 {
960 Log(("BranchTaskGate TSS is in LDT. uSel=%04x uSelTss=%04x -> #GP\n", uSel, uSelTss));
961 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel & X86_SEL_MASK_OFF_RPL);
962 }
963
964 IEMSELDESC TssDesc;
965 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pIemCpu, &TssDesc, uSelTss, X86_XCPT_GP);
966 if (rcStrict != VINF_SUCCESS)
967 return rcStrict;
968
969 if (TssDesc.Legacy.Gate.u4Type & X86_SEL_TYPE_SYS_TSS_BUSY_MASK)
970 {
971 Log(("BranchTaskGate TSS is busy. uSel=%04x uSelTss=%04x DescType=%#x -> #GP\n", uSel, uSelTss,
972 TssDesc.Legacy.Gate.u4Type));
973 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel & X86_SEL_MASK_OFF_RPL);
974 }
975
976 if (!TssDesc.Legacy.Gate.u1Present)
977 {
978 Log(("BranchTaskGate TSS is not present. uSel=%04x uSelTss=%04x -> #NP\n", uSel, uSelTss));
979 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uSelTss & X86_SEL_MASK_OFF_RPL);
980 }
981
982 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
983 uint32_t uNextEip = pCtx->eip + cbInstr;
984 return iemTaskSwitch(pIemCpu, pIemCpu->CTX_SUFF(pCtx), enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
985 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSelTss, &TssDesc);
986#endif
987}
988
989
990/**
991 * Implements far jumps and calls thru call gates.
992 *
993 * @param uSel The selector.
994 * @param enmBranch The kind of branching we're performing.
995 * @param enmEffOpSize The effective operand size.
996 * @param pDesc The descriptor corresponding to @a uSel. The type is
997 * call gate.
998 */
999IEM_CIMPL_DEF_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1000{
1001#ifndef IEM_IMPLEMENTS_CALLGATE
1002 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
1003#else
1004 /* NB: Far jumps can only do intra-privilege transfers. Far calls support
1005 * inter-privilege calls and are much more complex.
1006 *
1007 * NB: 64-bit call gate has the same type as a 32-bit call gate! If
1008 * EFER.LMA=1, the gate must be 64-bit. Conversely if EFER.LMA=0, the gate
1009 * must be 16-bit or 32-bit.
1010 */
1011 /** @todo: effective operand size is probably irrelevant here, only the
1012 * call gate bitness matters??
1013 */
1014 VBOXSTRICTRC rcStrict;
1015 RTPTRUNION uPtrRet;
1016 uint64_t uNewRsp;
1017 uint64_t uNewRip;
1018 uint64_t u64Base;
1019 uint32_t cbLimit;
1020 RTSEL uNewCS;
1021 IEMSELDESC DescCS;
1022 PCPUMCTX pCtx;
1023
1024 AssertCompile(X86_SEL_TYPE_SYS_386_CALL_GATE == AMD64_SEL_TYPE_SYS_CALL_GATE);
1025 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1026 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE
1027 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE);
1028
1029 /* Determine the new instruction pointer from the gate descriptor. */
1030 uNewRip = pDesc->Legacy.Gate.u16OffsetLow
1031 | ((uint32_t)pDesc->Legacy.Gate.u16OffsetHigh << 16)
1032 | ((uint64_t)pDesc->Long.Gate.u32OffsetTop << 32);
1033
1034 /* Perform DPL checks on the gate descriptor. */
1035 if ( pDesc->Legacy.Gate.u2Dpl < pIemCpu->uCpl
1036 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1037 {
1038 Log(("BranchCallGate invalid priv. uSel=%04x Gate DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1039 pIemCpu->uCpl, (uSel & X86_SEL_RPL)));
1040 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1041 }
1042
1043 /** @todo does this catch NULL selectors, too? */
1044 if (!pDesc->Legacy.Gen.u1Present)
1045 {
1046 Log(("BranchCallGate Gate not present uSel=%04x -> #NP\n", uSel));
1047 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uSel);
1048 }
1049
1050 /*
1051 * Fetch the target CS descriptor from the GDT or LDT.
1052 */
1053 uNewCS = pDesc->Legacy.Gate.u16Sel;
1054 rcStrict = iemMemFetchSelDesc(pIemCpu, &DescCS, uNewCS, X86_XCPT_GP);
1055 if (rcStrict != VINF_SUCCESS)
1056 return rcStrict;
1057
1058 /* Target CS must be a code selector. */
1059 if ( !DescCS.Legacy.Gen.u1DescType
1060 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
1061 {
1062 Log(("BranchCallGate %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
1063 uNewCS, uNewRip, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
1064 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCS);
1065 }
1066
1067 /* Privilege checks on target CS. */
1068 if (enmBranch == IEMBRANCH_JUMP)
1069 {
1070 if (DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1071 {
1072 if (DescCS.Legacy.Gen.u2Dpl > pIemCpu->uCpl)
1073 {
1074 Log(("BranchCallGate jump (conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1075 uNewCS, DescCS.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
1076 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCS);
1077 }
1078 }
1079 else
1080 {
1081 if (DescCS.Legacy.Gen.u2Dpl != pIemCpu->uCpl)
1082 {
1083 Log(("BranchCallGate jump (non-conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1084 uNewCS, DescCS.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
1085 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCS);
1086 }
1087 }
1088 }
1089 else
1090 {
1091 Assert(enmBranch == IEMBRANCH_CALL);
1092 if (DescCS.Legacy.Gen.u2Dpl > pIemCpu->uCpl)
1093 {
1094 Log(("BranchCallGate call invalid priv. uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1095 uNewCS, DescCS.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
1096 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCS & X86_SEL_MASK_OFF_RPL);
1097 }
1098 }
1099
1100 /* Additional long mode checks. */
1101 if (IEM_IS_LONG_MODE(pIemCpu))
1102 {
1103 if (!DescCS.Legacy.Gen.u1Long)
1104 {
1105 Log(("BranchCallGate uNewCS %04x -> not a 64-bit code segment.\n", uNewCS));
1106 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCS);
1107 }
1108
1109 /* L vs D. */
1110 if ( DescCS.Legacy.Gen.u1Long
1111 && DescCS.Legacy.Gen.u1DefBig)
1112 {
1113 Log(("BranchCallGate uNewCS %04x -> both L and D are set.\n", uNewCS));
1114 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCS);
1115 }
1116 }
1117
1118 if (!DescCS.Legacy.Gate.u1Present)
1119 {
1120 Log(("BranchCallGate target CS is not present. uSel=%04x uNewCS=%04x -> #NP(CS)\n", uSel, uNewCS));
1121 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uNewCS);
1122 }
1123
1124 pCtx = pIemCpu->CTX_SUFF(pCtx);
1125
1126 if (enmBranch == IEMBRANCH_JUMP)
1127 {
1128 /** @todo: This is very similar to regular far jumps; merge! */
1129 /* Jumps are fairly simple... */
1130
1131 /* Chop the high bits off if 16-bit gate (Intel says so). */
1132 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1133 uNewRip = (uint16_t)uNewRip;
1134
1135 /* Limit check for non-long segments. */
1136 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1137 if (DescCS.Legacy.Gen.u1Long)
1138 u64Base = 0;
1139 else
1140 {
1141 if (uNewRip > cbLimit)
1142 {
1143 Log(("BranchCallGate jump %04x:%08RX64 -> out of bounds (%#x) -> #GP(0)\n", uNewCS, uNewRip, cbLimit));
1144 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, 0);
1145 }
1146 u64Base = X86DESC_BASE(&DescCS.Legacy);
1147 }
1148
1149 /* Canonical address check. */
1150 if (!IEM_IS_CANONICAL(uNewRip))
1151 {
1152 Log(("BranchCallGate jump %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1153 return iemRaiseNotCanonical(pIemCpu);
1154 }
1155
1156 /*
1157 * Ok, everything checked out fine. Now set the accessed bit before
1158 * committing the result into CS, CSHID and RIP.
1159 */
1160 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1161 {
1162 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewCS);
1163 if (rcStrict != VINF_SUCCESS)
1164 return rcStrict;
1165 /** @todo check what VT-x and AMD-V does. */
1166 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1167 }
1168
1169 /* commit */
1170 pCtx->rip = uNewRip;
1171 pCtx->cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1172 pCtx->cs.Sel |= pIemCpu->uCpl; /** @todo is this right for conforming segs? or in general? */
1173 pCtx->cs.ValidSel = pCtx->cs.Sel;
1174 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1175 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1176 pCtx->cs.u32Limit = cbLimit;
1177 pCtx->cs.u64Base = u64Base;
1178 }
1179 else
1180 {
1181 Assert(enmBranch == IEMBRANCH_CALL);
1182 /* Calls are much more complicated. */
1183
1184 if (DescCS.Legacy.Gen.u2Dpl < pIemCpu->uCpl)
1185 {
1186 uint16_t offNewStack; /* Offset of new stack in TSS. */
1187 uint16_t cbNewStack; /* Number of bytes the stack information takes up in TSS. */
1188 uint8_t uNewCSDpl;
1189 uint8_t cbWords;
1190 RTSEL uNewSS;
1191 RTSEL uOldSS;
1192 uint64_t uOldRsp;
1193 IEMSELDESC DescSS;
1194 RTPTRUNION uPtrTSS;
1195 RTGCPTR GCPtrTSS;
1196 RTPTRUNION uPtrParmWds;
1197 RTGCPTR GCPtrParmWds;
1198
1199 /* More privilege. This is the fun part. */
1200 Assert(!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)); /* Filtered out above. */
1201
1202 /*
1203 * Determine new SS:rSP from the TSS.
1204 */
1205 Assert(!pCtx->tr.Attr.n.u1DescType);
1206
1207 /* Figure out where the new stack pointer is stored in the TSS. */
1208 uNewCSDpl = uNewCS & X86_SEL_RPL;
1209 if (!IEM_IS_LONG_MODE(pIemCpu))
1210 {
1211 if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1212 {
1213 offNewStack = RT_OFFSETOF(X86TSS32, esp0) + uNewCSDpl * 8;
1214 cbNewStack = RT_SIZEOFMEMB(X86TSS32, esp0) + RT_SIZEOFMEMB(X86TSS32, ss0);
1215 }
1216 else
1217 {
1218 Assert(pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1219 offNewStack = RT_OFFSETOF(X86TSS16, sp0) + uNewCSDpl * 4;
1220 cbNewStack = RT_SIZEOFMEMB(X86TSS16, sp0) + RT_SIZEOFMEMB(X86TSS16, ss0);
1221 }
1222 }
1223 else
1224 {
1225 Assert(pCtx->tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1226 offNewStack = RT_OFFSETOF(X86TSS64, rsp0) + uNewCSDpl * RT_SIZEOFMEMB(X86TSS64, rsp0);
1227 cbNewStack = RT_SIZEOFMEMB(X86TSS64, rsp0);
1228 }
1229
1230 /* Check against TSS limit. */
1231 if ((uint16_t)(offNewStack + cbNewStack - 1) > pCtx->tr.u32Limit)
1232 {
1233 Log(("BranchCallGate inner stack past TSS limit - %u > %u -> #TS(TSS)\n", offNewStack + cbNewStack - 1, pCtx->tr.u32Limit));
1234 return iemRaiseTaskSwitchFaultBySelector(pIemCpu, pCtx->tr.Sel);
1235 }
1236
1237 GCPtrTSS = pCtx->tr.u64Base + offNewStack;
1238 rcStrict = iemMemMap(pIemCpu, &uPtrTSS.pv, cbNewStack, UINT8_MAX, GCPtrTSS, IEM_ACCESS_SYS_R);
1239 if (rcStrict != VINF_SUCCESS)
1240 {
1241 Log(("BranchCallGate: TSS mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1242 return rcStrict;
1243 }
1244
1245 if (!IEM_IS_LONG_MODE(pIemCpu))
1246 {
1247 if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1248 {
1249 uNewRsp = uPtrTSS.pu32[0];
1250 uNewSS = uPtrTSS.pu16[2];
1251 }
1252 else
1253 {
1254 Assert(pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1255 uNewRsp = uPtrTSS.pu16[0];
1256 uNewSS = uPtrTSS.pu16[1];
1257 }
1258 }
1259 else
1260 {
1261 Assert(pCtx->tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1262 /* SS will be a NULL selector, but that's valid. */
1263 uNewRsp = uPtrTSS.pu64[0];
1264 uNewSS = uNewCSDpl;
1265 }
1266
1267 /* Done with the TSS now. */
1268 rcStrict = iemMemCommitAndUnmap(pIemCpu, uPtrTSS.pv, IEM_ACCESS_SYS_R);
1269 if (rcStrict != VINF_SUCCESS)
1270 {
1271 Log(("BranchCallGate: TSS unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1272 return rcStrict;
1273 }
1274
1275 /* Only used outside of long mode. */
1276 cbWords = pDesc->Legacy.Gate.u4ParmCount;
1277
1278 /* If EFER.LMA is 0, there's extra work to do. */
1279 if (!IEM_IS_LONG_MODE(pIemCpu))
1280 {
1281 if ((uNewSS & X86_SEL_MASK_OFF_RPL) == 0)
1282 {
1283 Log(("BranchCallGate new SS NULL -> #TS(NewSS)\n"));
1284 return iemRaiseTaskSwitchFaultBySelector(pIemCpu, uNewSS);
1285 }
1286
1287 /* Grab the new SS descriptor. */
1288 rcStrict = iemMemFetchSelDesc(pIemCpu, &DescSS, uNewSS, X86_XCPT_SS);
1289 if (rcStrict != VINF_SUCCESS)
1290 return rcStrict;
1291
1292 /* Ensure that CS.DPL == SS.RPL == SS.DPL. */
1293 if ( (DescCS.Legacy.Gen.u2Dpl != (uNewSS & X86_SEL_RPL))
1294 || (DescCS.Legacy.Gen.u2Dpl != DescSS.Legacy.Gen.u2Dpl))
1295 {
1296 Log(("BranchCallGate call bad RPL/DPL uNewSS=%04x SS DPL=%d CS DPL=%u -> #TS(NewSS)\n",
1297 uNewSS, DescCS.Legacy.Gen.u2Dpl, DescCS.Legacy.Gen.u2Dpl));
1298 return iemRaiseTaskSwitchFaultBySelector(pIemCpu, uNewSS);
1299 }
1300
1301 /* Ensure new SS is a writable data segment. */
1302 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
1303 {
1304 Log(("BranchCallGate call new SS -> not a writable data selector (u4Type=%#x)\n", DescSS.Legacy.Gen.u4Type));
1305 return iemRaiseTaskSwitchFaultBySelector(pIemCpu, uNewSS);
1306 }
1307
1308 if (!DescSS.Legacy.Gen.u1Present)
1309 {
1310 Log(("BranchCallGate New stack not present uSel=%04x -> #SS(NewSS)\n", uNewSS));
1311 return iemRaiseStackSelectorNotPresentBySelector(pIemCpu, uNewSS);
1312 }
1313 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1314 cbNewStack = (uint16_t)sizeof(uint32_t) * (4 + cbWords);
1315 else
1316 cbNewStack = (uint16_t)sizeof(uint16_t) * (4 + cbWords);
1317 }
1318 else
1319 {
1320 /* Just grab the new (NULL) SS descriptor. */
1321 rcStrict = iemMemFetchSelDesc(pIemCpu, &DescSS, uNewSS, X86_XCPT_SS);
1322 if (rcStrict != VINF_SUCCESS)
1323 return rcStrict;
1324
1325 cbNewStack = sizeof(uint64_t) * 4;
1326 }
1327
1328 /** @todo: According to Intel, new stack is checked for enough space first,
1329 * then switched. According to AMD, the stack is switched first and
1330 * then pushes might fault!
1331 */
1332
1333 /** @todo: According to AMD, CS is loaded first, then SS.
1334 * According to Intel, it's the other way around!?
1335 */
1336
1337 /** @todo: Intel and AMD disagree on when exactly the CPL changes! */
1338
1339 /* Set the accessed bit before committing new SS. */
1340 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1341 {
1342 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewSS);
1343 if (rcStrict != VINF_SUCCESS)
1344 return rcStrict;
1345 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1346 }
1347
1348 /* Remember the old SS:rSP and their linear address. */
1349 uOldSS = pCtx->ss.Sel;
1350 uOldRsp = pCtx->rsp;
1351
1352 GCPtrParmWds = pCtx->ss.u64Base + pCtx->rsp;
1353
1354 /* Commit new SS:rSP. */
1355 pCtx->ss.Sel = uNewSS;
1356 pCtx->ss.ValidSel = uNewSS;
1357 pCtx->ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
1358 pCtx->ss.u32Limit = X86DESC_LIMIT_G(&DescSS.Legacy);
1359 pCtx->ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
1360 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1361 pCtx->rsp = uNewRsp;
1362 pIemCpu->uCpl = uNewCSDpl;
1363 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(IEMCPU_TO_VMCPU(pIemCpu), &pCtx->ss));
1364 CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_HIDDEN_SEL_REGS);
1365
1366 /* Check new stack - may #SS(NewSS). */
1367 rcStrict = iemMemStackPushBeginSpecial(pIemCpu, cbNewStack,
1368 &uPtrRet.pv, &uNewRsp);
1369 if (rcStrict != VINF_SUCCESS)
1370 {
1371 Log(("BranchCallGate: New stack mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1372 return rcStrict;
1373 }
1374
1375 if (!IEM_IS_LONG_MODE(pIemCpu))
1376 {
1377 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1378 {
1379 /* Push the old CS:rIP. */
1380 uPtrRet.pu32[0] = pCtx->eip + cbInstr;
1381 uPtrRet.pu32[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1382
1383 /* Map the relevant chunk of the old stack. */
1384 rcStrict = iemMemMap(pIemCpu, &uPtrParmWds.pv, cbWords * 4, UINT8_MAX, GCPtrParmWds, IEM_ACCESS_DATA_R);
1385 if (rcStrict != VINF_SUCCESS)
1386 {
1387 Log(("BranchCallGate: Old stack mapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1388 return rcStrict;
1389 }
1390
1391 /* Copy the parameter (d)words. */
1392 for (int i = 0; i < cbWords; ++i)
1393 uPtrRet.pu32[2 + i] = uPtrParmWds.pu32[i];
1394
1395 /* Unmap the old stack. */
1396 rcStrict = iemMemCommitAndUnmap(pIemCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1397 if (rcStrict != VINF_SUCCESS)
1398 {
1399 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1400 return rcStrict;
1401 }
1402
1403 /* Push the old SS:rSP. */
1404 uPtrRet.pu32[2 + cbWords + 0] = uOldRsp;
1405 uPtrRet.pu32[2 + cbWords + 1] = uOldSS;
1406 }
1407 else
1408 {
1409 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1410
1411 /* Push the old CS:rIP. */
1412 uPtrRet.pu16[0] = pCtx->ip + cbInstr;
1413 uPtrRet.pu16[1] = pCtx->cs.Sel;
1414
1415 /* Map the relevant chunk of the old stack. */
1416 rcStrict = iemMemMap(pIemCpu, &uPtrParmWds.pv, cbWords * 2, UINT8_MAX, GCPtrParmWds, IEM_ACCESS_DATA_R);
1417 if (rcStrict != VINF_SUCCESS)
1418 {
1419 Log(("BranchCallGate: Old stack mapping (16-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1420 return rcStrict;
1421 }
1422
1423 /* Copy the parameter words. */
1424 for (int i = 0; i < cbWords; ++i)
1425 uPtrRet.pu16[2 + i] = uPtrParmWds.pu16[i];
1426
1427 /* Unmap the old stack. */
1428 rcStrict = iemMemCommitAndUnmap(pIemCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1429 if (rcStrict != VINF_SUCCESS)
1430 {
1431 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1432 return rcStrict;
1433 }
1434
1435 /* Push the old SS:rSP. */
1436 uPtrRet.pu16[2 + cbWords + 0] = uOldRsp;
1437 uPtrRet.pu16[2 + cbWords + 1] = uOldSS;
1438 }
1439 }
1440 else
1441 {
1442 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1443
1444 /* For 64-bit gates, no parameters are copied. Just push old SS:rSP and CS:rIP. */
1445 uPtrRet.pu64[0] = pCtx->rip + cbInstr;
1446 uPtrRet.pu64[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1447 uPtrRet.pu64[2] = uOldRsp;
1448 uPtrRet.pu64[3] = uOldSS; /** @todo Testcase: What is written to the high words when pushing SS? */
1449 }
1450
1451 rcStrict = iemMemStackPushCommitSpecial(pIemCpu, uPtrRet.pv, uNewRsp);
1452 if (rcStrict != VINF_SUCCESS)
1453 {
1454 Log(("BranchCallGate: New stack unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1455 return rcStrict;
1456 }
1457
1458 /* Chop the high bits off if 16-bit gate (Intel says so). */
1459 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1460 uNewRip = (uint16_t)uNewRip;
1461
1462 /* Limit / canonical check. */
1463 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1464 if (!IEM_IS_LONG_MODE(pIemCpu))
1465 {
1466 if (uNewRip > cbLimit)
1467 {
1468 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1469 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, 0);
1470 }
1471 u64Base = X86DESC_BASE(&DescCS.Legacy);
1472 }
1473 else
1474 {
1475 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1476 if (!IEM_IS_CANONICAL(uNewRip))
1477 {
1478 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1479 return iemRaiseNotCanonical(pIemCpu);
1480 }
1481 u64Base = 0;
1482 }
1483
1484 /*
1485 * Now set the accessed bit before
1486 * writing the return address to the stack and committing the result into
1487 * CS, CSHID and RIP.
1488 */
1489 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1490 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1491 {
1492 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewCS);
1493 if (rcStrict != VINF_SUCCESS)
1494 return rcStrict;
1495 /** @todo check what VT-x and AMD-V does. */
1496 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1497 }
1498
1499 /* Commit new CS:rIP. */
1500 pCtx->rip = uNewRip;
1501 pCtx->cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1502 pCtx->cs.Sel |= pIemCpu->uCpl;
1503 pCtx->cs.ValidSel = pCtx->cs.Sel;
1504 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1505 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1506 pCtx->cs.u32Limit = cbLimit;
1507 pCtx->cs.u64Base = u64Base;
1508 }
1509 else
1510 {
1511 /* Same privilege. */
1512 /** @todo: This is very similar to regular far calls; merge! */
1513
1514 /* Check stack first - may #SS(0). */
1515 /** @todo check how gate size affects pushing of CS! Does callf 16:32 in
1516 * 16-bit code cause a two or four byte CS to be pushed? */
1517 rcStrict = iemMemStackPushBeginSpecial(pIemCpu,
1518 IEM_IS_LONG_MODE(pIemCpu) ? 8+8
1519 : pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE ? 4+4 : 2+2,
1520 &uPtrRet.pv, &uNewRsp);
1521 if (rcStrict != VINF_SUCCESS)
1522 return rcStrict;
1523
1524 /* Chop the high bits off if 16-bit gate (Intel says so). */
1525 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1526 uNewRip = (uint16_t)uNewRip;
1527
1528 /* Limit / canonical check. */
1529 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1530 if (!IEM_IS_LONG_MODE(pIemCpu))
1531 {
1532 if (uNewRip > cbLimit)
1533 {
1534 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1535 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, 0);
1536 }
1537 u64Base = X86DESC_BASE(&DescCS.Legacy);
1538 }
1539 else
1540 {
1541 if (!IEM_IS_CANONICAL(uNewRip))
1542 {
1543 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1544 return iemRaiseNotCanonical(pIemCpu);
1545 }
1546 u64Base = 0;
1547 }
1548
1549 /*
1550 * Now set the accessed bit before
1551 * writing the return address to the stack and committing the result into
1552 * CS, CSHID and RIP.
1553 */
1554 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1555 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1556 {
1557 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewCS);
1558 if (rcStrict != VINF_SUCCESS)
1559 return rcStrict;
1560 /** @todo check what VT-x and AMD-V does. */
1561 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1562 }
1563
1564 /* stack */
1565 if (!IEM_IS_LONG_MODE(pIemCpu))
1566 {
1567 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1568 {
1569 uPtrRet.pu32[0] = pCtx->eip + cbInstr;
1570 uPtrRet.pu32[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1571 }
1572 else
1573 {
1574 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1575 uPtrRet.pu16[0] = pCtx->ip + cbInstr;
1576 uPtrRet.pu16[1] = pCtx->cs.Sel;
1577 }
1578 }
1579 else
1580 {
1581 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1582 uPtrRet.pu64[0] = pCtx->rip + cbInstr;
1583 uPtrRet.pu64[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1584 }
1585
1586 rcStrict = iemMemStackPushCommitSpecial(pIemCpu, uPtrRet.pv, uNewRsp);
1587 if (rcStrict != VINF_SUCCESS)
1588 return rcStrict;
1589
1590 /* commit */
1591 pCtx->rip = uNewRip;
1592 pCtx->cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1593 pCtx->cs.Sel |= pIemCpu->uCpl;
1594 pCtx->cs.ValidSel = pCtx->cs.Sel;
1595 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1596 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1597 pCtx->cs.u32Limit = cbLimit;
1598 pCtx->cs.u64Base = u64Base;
1599 }
1600 }
1601 pCtx->eflags.Bits.u1RF = 0;
1602 return VINF_SUCCESS;
1603#endif
1604}
1605
1606
1607/**
1608 * Implements far jumps and calls thru system selectors.
1609 *
1610 * @param uSel The selector.
1611 * @param enmBranch The kind of branching we're performing.
1612 * @param enmEffOpSize The effective operand size.
1613 * @param pDesc The descriptor corresponding to @a uSel.
1614 */
1615IEM_CIMPL_DEF_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1616{
1617 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1618 Assert((uSel & X86_SEL_MASK_OFF_RPL));
1619
1620 if (IEM_IS_LONG_MODE(pIemCpu))
1621 switch (pDesc->Legacy.Gen.u4Type)
1622 {
1623 case AMD64_SEL_TYPE_SYS_CALL_GATE:
1624 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1625
1626 default:
1627 case AMD64_SEL_TYPE_SYS_LDT:
1628 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
1629 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
1630 case AMD64_SEL_TYPE_SYS_TRAP_GATE:
1631 case AMD64_SEL_TYPE_SYS_INT_GATE:
1632 Log(("branch %04x -> wrong sys selector (64-bit): %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1633 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1634 }
1635
1636 switch (pDesc->Legacy.Gen.u4Type)
1637 {
1638 case X86_SEL_TYPE_SYS_286_CALL_GATE:
1639 case X86_SEL_TYPE_SYS_386_CALL_GATE:
1640 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1641
1642 case X86_SEL_TYPE_SYS_TASK_GATE:
1643 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskGate, uSel, enmBranch, enmEffOpSize, pDesc);
1644
1645 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
1646 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
1647 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskSegment, uSel, enmBranch, enmEffOpSize, pDesc);
1648
1649 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
1650 Log(("branch %04x -> busy 286 TSS\n", uSel));
1651 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1652
1653 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
1654 Log(("branch %04x -> busy 386 TSS\n", uSel));
1655 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1656
1657 default:
1658 case X86_SEL_TYPE_SYS_LDT:
1659 case X86_SEL_TYPE_SYS_286_INT_GATE:
1660 case X86_SEL_TYPE_SYS_286_TRAP_GATE:
1661 case X86_SEL_TYPE_SYS_386_INT_GATE:
1662 case X86_SEL_TYPE_SYS_386_TRAP_GATE:
1663 Log(("branch %04x -> wrong sys selector: %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1664 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1665 }
1666}
1667
1668
1669/**
1670 * Implements far jumps.
1671 *
1672 * @param uSel The selector.
1673 * @param offSeg The segment offset.
1674 * @param enmEffOpSize The effective operand size.
1675 */
1676IEM_CIMPL_DEF_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
1677{
1678 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1679 NOREF(cbInstr);
1680 Assert(offSeg <= UINT32_MAX);
1681
1682 /*
1683 * Real mode and V8086 mode are easy. The only snag seems to be that
1684 * CS.limit doesn't change and the limit check is done against the current
1685 * limit.
1686 */
1687 if ( pIemCpu->enmCpuMode == IEMMODE_16BIT
1688 && IEM_IS_REAL_OR_V86_MODE(pIemCpu))
1689 {
1690 if (offSeg > pCtx->cs.u32Limit)
1691 return iemRaiseGeneralProtectionFault0(pIemCpu);
1692
1693 if (enmEffOpSize == IEMMODE_16BIT) /** @todo WRONG, must pass this. */
1694 pCtx->rip = offSeg;
1695 else
1696 pCtx->rip = offSeg & UINT16_MAX;
1697 pCtx->cs.Sel = uSel;
1698 pCtx->cs.ValidSel = uSel;
1699 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1700 pCtx->cs.u64Base = (uint32_t)uSel << 4;
1701 pCtx->eflags.Bits.u1RF = 0;
1702 return VINF_SUCCESS;
1703 }
1704
1705 /*
1706 * Protected mode. Need to parse the specified descriptor...
1707 */
1708 if (!(uSel & X86_SEL_MASK_OFF_RPL))
1709 {
1710 Log(("jmpf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
1711 return iemRaiseGeneralProtectionFault0(pIemCpu);
1712 }
1713
1714 /* Fetch the descriptor. */
1715 IEMSELDESC Desc;
1716 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pIemCpu, &Desc, uSel, X86_XCPT_GP);
1717 if (rcStrict != VINF_SUCCESS)
1718 return rcStrict;
1719
1720 /* Is it there? */
1721 if (!Desc.Legacy.Gen.u1Present) /** @todo this is probably checked too early. Testcase! */
1722 {
1723 Log(("jmpf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
1724 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uSel);
1725 }
1726
1727 /*
1728 * Deal with it according to its type. We do the standard code selectors
1729 * here and dispatch the system selectors to worker functions.
1730 */
1731 if (!Desc.Legacy.Gen.u1DescType)
1732 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_JUMP, enmEffOpSize, &Desc);
1733
1734 /* Only code segments. */
1735 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
1736 {
1737 Log(("jmpf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
1738 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1739 }
1740
1741 /* L vs D. */
1742 if ( Desc.Legacy.Gen.u1Long
1743 && Desc.Legacy.Gen.u1DefBig
1744 && IEM_IS_LONG_MODE(pIemCpu))
1745 {
1746 Log(("jmpf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
1747 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1748 }
1749
1750 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
1751 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1752 {
1753 if (pIemCpu->uCpl < Desc.Legacy.Gen.u2Dpl)
1754 {
1755 Log(("jmpf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
1756 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
1757 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1758 }
1759 }
1760 else
1761 {
1762 if (pIemCpu->uCpl != Desc.Legacy.Gen.u2Dpl)
1763 {
1764 Log(("jmpf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
1765 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1766 }
1767 if ((uSel & X86_SEL_RPL) > pIemCpu->uCpl)
1768 {
1769 Log(("jmpf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pIemCpu->uCpl));
1770 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1771 }
1772 }
1773
1774 /* Chop the high bits if 16-bit (Intel says so). */
1775 if (enmEffOpSize == IEMMODE_16BIT)
1776 offSeg &= UINT16_MAX;
1777
1778 /* Limit check. (Should alternatively check for non-canonical addresses
1779 here, but that is ruled out by offSeg being 32-bit, right?) */
1780 uint64_t u64Base;
1781 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
1782 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
1783 u64Base = 0;
1784 else
1785 {
1786 if (offSeg > cbLimit)
1787 {
1788 Log(("jmpf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
1789 /** @todo: Intel says this is #GP(0)! */
1790 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1791 }
1792 u64Base = X86DESC_BASE(&Desc.Legacy);
1793 }
1794
1795 /*
1796 * Ok, everything checked out fine. Now set the accessed bit before
1797 * committing the result into CS, CSHID and RIP.
1798 */
1799 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1800 {
1801 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uSel);
1802 if (rcStrict != VINF_SUCCESS)
1803 return rcStrict;
1804 /** @todo check what VT-x and AMD-V does. */
1805 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1806 }
1807
1808 /* commit */
1809 pCtx->rip = offSeg;
1810 pCtx->cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
1811 pCtx->cs.Sel |= pIemCpu->uCpl; /** @todo is this right for conforming segs? or in general? */
1812 pCtx->cs.ValidSel = pCtx->cs.Sel;
1813 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1814 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
1815 pCtx->cs.u32Limit = cbLimit;
1816 pCtx->cs.u64Base = u64Base;
1817 pCtx->eflags.Bits.u1RF = 0;
1818 /** @todo check if the hidden bits are loaded correctly for 64-bit
1819 * mode. */
1820 return VINF_SUCCESS;
1821}
1822
1823
1824/**
1825 * Implements far calls.
1826 *
1827 * This very similar to iemCImpl_FarJmp.
1828 *
1829 * @param uSel The selector.
1830 * @param offSeg The segment offset.
1831 * @param enmEffOpSize The operand size (in case we need it).
1832 */
1833IEM_CIMPL_DEF_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
1834{
1835 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1836 VBOXSTRICTRC rcStrict;
1837 uint64_t uNewRsp;
1838 RTPTRUNION uPtrRet;
1839
1840 /*
1841 * Real mode and V8086 mode are easy. The only snag seems to be that
1842 * CS.limit doesn't change and the limit check is done against the current
1843 * limit.
1844 */
1845 if ( pIemCpu->enmCpuMode == IEMMODE_16BIT
1846 && IEM_IS_REAL_OR_V86_MODE(pIemCpu))
1847 {
1848 Assert(enmEffOpSize == IEMMODE_16BIT || enmEffOpSize == IEMMODE_32BIT);
1849
1850 /* Check stack first - may #SS(0). */
1851 rcStrict = iemMemStackPushBeginSpecial(pIemCpu, enmEffOpSize == IEMMODE_32BIT ? 6 : 4,
1852 &uPtrRet.pv, &uNewRsp);
1853 if (rcStrict != VINF_SUCCESS)
1854 return rcStrict;
1855
1856 /* Check the target address range. */
1857 if (offSeg > UINT32_MAX)
1858 return iemRaiseGeneralProtectionFault0(pIemCpu);
1859
1860 /* Everything is fine, push the return address. */
1861 if (enmEffOpSize == IEMMODE_16BIT)
1862 {
1863 uPtrRet.pu16[0] = pCtx->ip + cbInstr;
1864 uPtrRet.pu16[1] = pCtx->cs.Sel;
1865 }
1866 else
1867 {
1868 uPtrRet.pu32[0] = pCtx->eip + cbInstr;
1869 uPtrRet.pu16[3] = pCtx->cs.Sel;
1870 }
1871 rcStrict = iemMemStackPushCommitSpecial(pIemCpu, uPtrRet.pv, uNewRsp);
1872 if (rcStrict != VINF_SUCCESS)
1873 return rcStrict;
1874
1875 /* Branch. */
1876 pCtx->rip = offSeg;
1877 pCtx->cs.Sel = uSel;
1878 pCtx->cs.ValidSel = uSel;
1879 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1880 pCtx->cs.u64Base = (uint32_t)uSel << 4;
1881 pCtx->eflags.Bits.u1RF = 0;
1882 return VINF_SUCCESS;
1883 }
1884
1885 /*
1886 * Protected mode. Need to parse the specified descriptor...
1887 */
1888 if (!(uSel & X86_SEL_MASK_OFF_RPL))
1889 {
1890 Log(("callf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
1891 return iemRaiseGeneralProtectionFault0(pIemCpu);
1892 }
1893
1894 /* Fetch the descriptor. */
1895 IEMSELDESC Desc;
1896 rcStrict = iemMemFetchSelDesc(pIemCpu, &Desc, uSel, X86_XCPT_GP);
1897 if (rcStrict != VINF_SUCCESS)
1898 return rcStrict;
1899
1900 /*
1901 * Deal with it according to its type. We do the standard code selectors
1902 * here and dispatch the system selectors to worker functions.
1903 */
1904 if (!Desc.Legacy.Gen.u1DescType)
1905 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_CALL, enmEffOpSize, &Desc);
1906
1907 /* Only code segments. */
1908 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
1909 {
1910 Log(("callf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
1911 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1912 }
1913
1914 /* L vs D. */
1915 if ( Desc.Legacy.Gen.u1Long
1916 && Desc.Legacy.Gen.u1DefBig
1917 && IEM_IS_LONG_MODE(pIemCpu))
1918 {
1919 Log(("callf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
1920 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1921 }
1922
1923 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
1924 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1925 {
1926 if (pIemCpu->uCpl < Desc.Legacy.Gen.u2Dpl)
1927 {
1928 Log(("callf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
1929 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
1930 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1931 }
1932 }
1933 else
1934 {
1935 if (pIemCpu->uCpl != Desc.Legacy.Gen.u2Dpl)
1936 {
1937 Log(("callf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
1938 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1939 }
1940 if ((uSel & X86_SEL_RPL) > pIemCpu->uCpl)
1941 {
1942 Log(("callf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pIemCpu->uCpl));
1943 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1944 }
1945 }
1946
1947 /* Is it there? */
1948 if (!Desc.Legacy.Gen.u1Present)
1949 {
1950 Log(("callf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
1951 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uSel);
1952 }
1953
1954 /* Check stack first - may #SS(0). */
1955 /** @todo check how operand prefix affects pushing of CS! Does callf 16:32 in
1956 * 16-bit code cause a two or four byte CS to be pushed? */
1957 rcStrict = iemMemStackPushBeginSpecial(pIemCpu,
1958 enmEffOpSize == IEMMODE_64BIT ? 8+8
1959 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 2+2,
1960 &uPtrRet.pv, &uNewRsp);
1961 if (rcStrict != VINF_SUCCESS)
1962 return rcStrict;
1963
1964 /* Chop the high bits if 16-bit (Intel says so). */
1965 if (enmEffOpSize == IEMMODE_16BIT)
1966 offSeg &= UINT16_MAX;
1967
1968 /* Limit / canonical check. */
1969 uint64_t u64Base;
1970 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
1971 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
1972 {
1973 if (!IEM_IS_CANONICAL(offSeg))
1974 {
1975 Log(("callf %04x:%016RX64 - not canonical -> #GP\n", uSel, offSeg));
1976 return iemRaiseNotCanonical(pIemCpu);
1977 }
1978 u64Base = 0;
1979 }
1980 else
1981 {
1982 if (offSeg > cbLimit)
1983 {
1984 Log(("callf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
1985 /** @todo: Intel says this is #GP(0)! */
1986 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1987 }
1988 u64Base = X86DESC_BASE(&Desc.Legacy);
1989 }
1990
1991 /*
1992 * Now set the accessed bit before
1993 * writing the return address to the stack and committing the result into
1994 * CS, CSHID and RIP.
1995 */
1996 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1997 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1998 {
1999 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uSel);
2000 if (rcStrict != VINF_SUCCESS)
2001 return rcStrict;
2002 /** @todo check what VT-x and AMD-V does. */
2003 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2004 }
2005
2006 /* stack */
2007 if (enmEffOpSize == IEMMODE_16BIT)
2008 {
2009 uPtrRet.pu16[0] = pCtx->ip + cbInstr;
2010 uPtrRet.pu16[1] = pCtx->cs.Sel;
2011 }
2012 else if (enmEffOpSize == IEMMODE_32BIT)
2013 {
2014 uPtrRet.pu32[0] = pCtx->eip + cbInstr;
2015 uPtrRet.pu32[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high word when callf is pushing CS? */
2016 }
2017 else
2018 {
2019 uPtrRet.pu64[0] = pCtx->rip + cbInstr;
2020 uPtrRet.pu64[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high words when callf is pushing CS? */
2021 }
2022 rcStrict = iemMemStackPushCommitSpecial(pIemCpu, uPtrRet.pv, uNewRsp);
2023 if (rcStrict != VINF_SUCCESS)
2024 return rcStrict;
2025
2026 /* commit */
2027 pCtx->rip = offSeg;
2028 pCtx->cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
2029 pCtx->cs.Sel |= pIemCpu->uCpl;
2030 pCtx->cs.ValidSel = pCtx->cs.Sel;
2031 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2032 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
2033 pCtx->cs.u32Limit = cbLimit;
2034 pCtx->cs.u64Base = u64Base;
2035 pCtx->eflags.Bits.u1RF = 0;
2036 /** @todo check if the hidden bits are loaded correctly for 64-bit
2037 * mode. */
2038 return VINF_SUCCESS;
2039}
2040
2041
2042/**
2043 * Implements retf.
2044 *
2045 * @param enmEffOpSize The effective operand size.
2046 * @param cbPop The amount of arguments to pop from the stack
2047 * (bytes).
2048 */
2049IEM_CIMPL_DEF_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2050{
2051 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2052 VBOXSTRICTRC rcStrict;
2053 RTCPTRUNION uPtrFrame;
2054 uint64_t uNewRsp;
2055 uint64_t uNewRip;
2056 uint16_t uNewCs;
2057 NOREF(cbInstr);
2058
2059 /*
2060 * Read the stack values first.
2061 */
2062 uint32_t cbRetPtr = enmEffOpSize == IEMMODE_16BIT ? 2+2
2063 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 8+8;
2064 rcStrict = iemMemStackPopBeginSpecial(pIemCpu, cbRetPtr, &uPtrFrame.pv, &uNewRsp);
2065 if (rcStrict != VINF_SUCCESS)
2066 return rcStrict;
2067 if (enmEffOpSize == IEMMODE_16BIT)
2068 {
2069 uNewRip = uPtrFrame.pu16[0];
2070 uNewCs = uPtrFrame.pu16[1];
2071 }
2072 else if (enmEffOpSize == IEMMODE_32BIT)
2073 {
2074 uNewRip = uPtrFrame.pu32[0];
2075 uNewCs = uPtrFrame.pu16[2];
2076 }
2077 else
2078 {
2079 uNewRip = uPtrFrame.pu64[0];
2080 uNewCs = uPtrFrame.pu16[4];
2081 }
2082
2083 /*
2084 * Real mode and V8086 mode are easy.
2085 */
2086 if ( pIemCpu->enmCpuMode == IEMMODE_16BIT
2087 && IEM_IS_REAL_OR_V86_MODE(pIemCpu))
2088 {
2089 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2090 /** @todo check how this is supposed to work if sp=0xfffe. */
2091
2092 /* Check the limit of the new EIP. */
2093 /** @todo Intel pseudo code only does the limit check for 16-bit
2094 * operands, AMD does not make any distinction. What is right? */
2095 if (uNewRip > pCtx->cs.u32Limit)
2096 return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2097
2098 /* commit the operation. */
2099 rcStrict = iemMemStackPopCommitSpecial(pIemCpu, uPtrFrame.pv, uNewRsp);
2100 if (rcStrict != VINF_SUCCESS)
2101 return rcStrict;
2102 pCtx->rip = uNewRip;
2103 pCtx->cs.Sel = uNewCs;
2104 pCtx->cs.ValidSel = uNewCs;
2105 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2106 pCtx->cs.u64Base = (uint32_t)uNewCs << 4;
2107 pCtx->eflags.Bits.u1RF = 0;
2108 /** @todo do we load attribs and limit as well? */
2109 if (cbPop)
2110 iemRegAddToRsp(pIemCpu, pCtx, cbPop);
2111 return VINF_SUCCESS;
2112 }
2113
2114 /*
2115 * Protected mode is complicated, of course.
2116 */
2117 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
2118 {
2119 Log(("retf %04x:%08RX64 -> invalid selector, #GP(0)\n", uNewCs, uNewRip));
2120 return iemRaiseGeneralProtectionFault0(pIemCpu);
2121 }
2122
2123 /* Fetch the descriptor. */
2124 IEMSELDESC DescCs;
2125 rcStrict = iemMemFetchSelDesc(pIemCpu, &DescCs, uNewCs, X86_XCPT_GP);
2126 if (rcStrict != VINF_SUCCESS)
2127 return rcStrict;
2128
2129 /* Can only return to a code selector. */
2130 if ( !DescCs.Legacy.Gen.u1DescType
2131 || !(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
2132 {
2133 Log(("retf %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
2134 uNewCs, uNewRip, DescCs.Legacy.Gen.u1DescType, DescCs.Legacy.Gen.u4Type));
2135 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
2136 }
2137
2138 /* L vs D. */
2139 if ( DescCs.Legacy.Gen.u1Long /** @todo Testcase: far return to a selector with both L and D set. */
2140 && DescCs.Legacy.Gen.u1DefBig
2141 && IEM_IS_LONG_MODE(pIemCpu))
2142 {
2143 Log(("retf %04x:%08RX64 -> both L & D set.\n", uNewCs, uNewRip));
2144 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
2145 }
2146
2147 /* DPL/RPL/CPL checks. */
2148 if ((uNewCs & X86_SEL_RPL) < pIemCpu->uCpl)
2149 {
2150 Log(("retf %04x:%08RX64 -> RPL < CPL(%d).\n", uNewCs, uNewRip, pIemCpu->uCpl));
2151 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
2152 }
2153
2154 if (DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
2155 {
2156 if ((uNewCs & X86_SEL_RPL) < DescCs.Legacy.Gen.u2Dpl)
2157 {
2158 Log(("retf %04x:%08RX64 -> DPL violation (conforming); DPL=%u RPL=%u\n",
2159 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2160 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
2161 }
2162 }
2163 else
2164 {
2165 if ((uNewCs & X86_SEL_RPL) != DescCs.Legacy.Gen.u2Dpl)
2166 {
2167 Log(("retf %04x:%08RX64 -> RPL != DPL; DPL=%u RPL=%u\n",
2168 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2169 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
2170 }
2171 }
2172
2173 /* Is it there? */
2174 if (!DescCs.Legacy.Gen.u1Present)
2175 {
2176 Log(("retf %04x:%08RX64 -> segment not present\n", uNewCs, uNewRip));
2177 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uNewCs);
2178 }
2179
2180 /*
2181 * Return to outer privilege? (We'll typically have entered via a call gate.)
2182 */
2183 if ((uNewCs & X86_SEL_RPL) != pIemCpu->uCpl)
2184 {
2185 /* Read the outer stack pointer stored *after* the parameters. */
2186 RTCPTRUNION uPtrStack;
2187 rcStrict = iemMemStackPopContinueSpecial(pIemCpu, cbPop + cbRetPtr, &uPtrStack.pv, &uNewRsp);
2188 if (rcStrict != VINF_SUCCESS)
2189 return rcStrict;
2190
2191 uPtrStack.pu8 += cbPop; /* Skip the parameters. */
2192
2193 uint16_t uNewOuterSs;
2194 uint64_t uNewOuterRsp;
2195 if (enmEffOpSize == IEMMODE_16BIT)
2196 {
2197 uNewOuterRsp = uPtrStack.pu16[0];
2198 uNewOuterSs = uPtrStack.pu16[1];
2199 }
2200 else if (enmEffOpSize == IEMMODE_32BIT)
2201 {
2202 uNewOuterRsp = uPtrStack.pu32[0];
2203 uNewOuterSs = uPtrStack.pu16[2];
2204 }
2205 else
2206 {
2207 uNewOuterRsp = uPtrStack.pu64[0];
2208 uNewOuterSs = uPtrStack.pu16[4];
2209 }
2210
2211 /* Check for NULL stack selector (invalid in ring-3 and non-long mode)
2212 and read the selector. */
2213 IEMSELDESC DescSs;
2214 if (!(uNewOuterSs & X86_SEL_MASK_OFF_RPL))
2215 {
2216 if ( !DescCs.Legacy.Gen.u1Long
2217 || (uNewOuterSs & X86_SEL_RPL) == 3)
2218 {
2219 Log(("retf %04x:%08RX64 %04x:%08RX64 -> invalid stack selector, #GP\n",
2220 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2221 return iemRaiseGeneralProtectionFault0(pIemCpu);
2222 }
2223 /** @todo Testcase: Return far to ring-1 or ring-2 with SS=0. */
2224 iemMemFakeStackSelDesc(&DescSs, (uNewOuterSs & X86_SEL_RPL));
2225 }
2226 else
2227 {
2228 /* Fetch the descriptor for the new stack segment. */
2229 rcStrict = iemMemFetchSelDesc(pIemCpu, &DescSs, uNewOuterSs, X86_XCPT_GP);
2230 if (rcStrict != VINF_SUCCESS)
2231 return rcStrict;
2232 }
2233
2234 /* Check that RPL of stack and code selectors match. */
2235 if ((uNewCs & X86_SEL_RPL) != (uNewOuterSs & X86_SEL_RPL))
2236 {
2237 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.RPL != CS.RPL -> #GP(SS)\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2238 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewOuterSs);
2239 }
2240
2241 /* Must be a writable data segment. */
2242 if ( !DescSs.Legacy.Gen.u1DescType
2243 || (DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
2244 || !(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
2245 {
2246 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not a writable data segment (u1DescType=%u u4Type=%#x) -> #GP(SS).\n",
2247 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u1DescType, DescSs.Legacy.Gen.u4Type));
2248 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewOuterSs);
2249 }
2250
2251 /* L vs D. (Not mentioned by intel.) */
2252 if ( DescSs.Legacy.Gen.u1Long /** @todo Testcase: far return to a stack selector with both L and D set. */
2253 && DescSs.Legacy.Gen.u1DefBig
2254 && IEM_IS_LONG_MODE(pIemCpu))
2255 {
2256 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS has both L & D set -> #GP(SS).\n",
2257 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2258 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewOuterSs);
2259 }
2260
2261 /* DPL/RPL/CPL checks. */
2262 if (DescSs.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
2263 {
2264 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.DPL(%u) != CS.RPL (%u) -> #GP(SS).\n",
2265 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u2Dpl, uNewCs & X86_SEL_RPL));
2266 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewOuterSs);
2267 }
2268
2269 /* Is it there? */
2270 if (!DescSs.Legacy.Gen.u1Present)
2271 {
2272 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not present -> #NP(SS).\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2273 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uNewCs);
2274 }
2275
2276 /* Calc SS limit.*/
2277 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSs.Legacy);
2278
2279 /* Is RIP canonical or within CS.limit? */
2280 uint64_t u64Base;
2281 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2282
2283 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
2284 {
2285 if (!IEM_IS_CANONICAL(uNewRip))
2286 {
2287 Log(("retf %04x:%08RX64 %04x:%08RX64 - not canonical -> #GP.\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2288 return iemRaiseNotCanonical(pIemCpu);
2289 }
2290 u64Base = 0;
2291 }
2292 else
2293 {
2294 if (uNewRip > cbLimitCs)
2295 {
2296 Log(("retf %04x:%08RX64 %04x:%08RX64 - out of bounds (%#x)-> #GP(CS).\n",
2297 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, cbLimitCs));
2298 /** @todo: Intel says this is #GP(0)! */
2299 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
2300 }
2301 u64Base = X86DESC_BASE(&DescCs.Legacy);
2302 }
2303
2304 /*
2305 * Now set the accessed bit before
2306 * writing the return address to the stack and committing the result into
2307 * CS, CSHID and RIP.
2308 */
2309 /** @todo Testcase: Need to check WHEN exactly the CS accessed bit is set. */
2310 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2311 {
2312 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewCs);
2313 if (rcStrict != VINF_SUCCESS)
2314 return rcStrict;
2315 /** @todo check what VT-x and AMD-V does. */
2316 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2317 }
2318 /** @todo Testcase: Need to check WHEN exactly the SS accessed bit is set. */
2319 if (!(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2320 {
2321 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewOuterSs);
2322 if (rcStrict != VINF_SUCCESS)
2323 return rcStrict;
2324 /** @todo check what VT-x and AMD-V does. */
2325 DescSs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2326 }
2327
2328 /* commit */
2329 rcStrict = iemMemStackPopCommitSpecial(pIemCpu, uPtrFrame.pv, uNewRsp);
2330 if (rcStrict != VINF_SUCCESS)
2331 return rcStrict;
2332 if (enmEffOpSize == IEMMODE_16BIT)
2333 pCtx->rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2334 else
2335 pCtx->rip = uNewRip;
2336 pCtx->cs.Sel = uNewCs;
2337 pCtx->cs.ValidSel = uNewCs;
2338 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2339 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2340 pCtx->cs.u32Limit = cbLimitCs;
2341 pCtx->cs.u64Base = u64Base;
2342 pCtx->rsp = uNewOuterRsp;
2343 pCtx->ss.Sel = uNewOuterSs;
2344 pCtx->ss.ValidSel = uNewOuterSs;
2345 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2346 pCtx->ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSs.Legacy);
2347 pCtx->ss.u32Limit = cbLimitSs;
2348 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
2349 pCtx->ss.u64Base = 0;
2350 else
2351 pCtx->ss.u64Base = X86DESC_BASE(&DescSs.Legacy);
2352
2353 pIemCpu->uCpl = (uNewCs & X86_SEL_RPL);
2354 iemHlpAdjustSelectorForNewCpl(pIemCpu, uNewCs & X86_SEL_RPL, &pCtx->ds);
2355 iemHlpAdjustSelectorForNewCpl(pIemCpu, uNewCs & X86_SEL_RPL, &pCtx->es);
2356 iemHlpAdjustSelectorForNewCpl(pIemCpu, uNewCs & X86_SEL_RPL, &pCtx->fs);
2357 iemHlpAdjustSelectorForNewCpl(pIemCpu, uNewCs & X86_SEL_RPL, &pCtx->gs);
2358
2359 /** @todo check if the hidden bits are loaded correctly for 64-bit
2360 * mode. */
2361
2362 if (cbPop)
2363 iemRegAddToRsp(pIemCpu, pCtx, cbPop);
2364 pCtx->eflags.Bits.u1RF = 0;
2365
2366 /* Done! */
2367 }
2368 /*
2369 * Return to the same privilege level
2370 */
2371 else
2372 {
2373 /* Limit / canonical check. */
2374 uint64_t u64Base;
2375 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2376
2377 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
2378 {
2379 if (!IEM_IS_CANONICAL(uNewRip))
2380 {
2381 Log(("retf %04x:%08RX64 - not canonical -> #GP\n", uNewCs, uNewRip));
2382 return iemRaiseNotCanonical(pIemCpu);
2383 }
2384 u64Base = 0;
2385 }
2386 else
2387 {
2388 if (uNewRip > cbLimitCs)
2389 {
2390 Log(("retf %04x:%08RX64 -> out of bounds (%#x)\n", uNewCs, uNewRip, cbLimitCs));
2391 /** @todo: Intel says this is #GP(0)! */
2392 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
2393 }
2394 u64Base = X86DESC_BASE(&DescCs.Legacy);
2395 }
2396
2397 /*
2398 * Now set the accessed bit before
2399 * writing the return address to the stack and committing the result into
2400 * CS, CSHID and RIP.
2401 */
2402 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
2403 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2404 {
2405 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewCs);
2406 if (rcStrict != VINF_SUCCESS)
2407 return rcStrict;
2408 /** @todo check what VT-x and AMD-V does. */
2409 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2410 }
2411
2412 /* commit */
2413 rcStrict = iemMemStackPopCommitSpecial(pIemCpu, uPtrFrame.pv, uNewRsp);
2414 if (rcStrict != VINF_SUCCESS)
2415 return rcStrict;
2416 if (enmEffOpSize == IEMMODE_16BIT)
2417 pCtx->rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2418 else
2419 pCtx->rip = uNewRip;
2420 pCtx->cs.Sel = uNewCs;
2421 pCtx->cs.ValidSel = uNewCs;
2422 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2423 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2424 pCtx->cs.u32Limit = cbLimitCs;
2425 pCtx->cs.u64Base = u64Base;
2426 /** @todo check if the hidden bits are loaded correctly for 64-bit
2427 * mode. */
2428 if (cbPop)
2429 iemRegAddToRsp(pIemCpu, pCtx, cbPop);
2430 pCtx->eflags.Bits.u1RF = 0;
2431 }
2432 return VINF_SUCCESS;
2433}
2434
2435
2436/**
2437 * Implements retn.
2438 *
2439 * We're doing this in C because of the \#GP that might be raised if the popped
2440 * program counter is out of bounds.
2441 *
2442 * @param enmEffOpSize The effective operand size.
2443 * @param cbPop The amount of arguments to pop from the stack
2444 * (bytes).
2445 */
2446IEM_CIMPL_DEF_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2447{
2448 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2449 NOREF(cbInstr);
2450
2451 /* Fetch the RSP from the stack. */
2452 VBOXSTRICTRC rcStrict;
2453 RTUINT64U NewRip;
2454 RTUINT64U NewRsp;
2455 NewRsp.u = pCtx->rsp;
2456 switch (enmEffOpSize)
2457 {
2458 case IEMMODE_16BIT:
2459 NewRip.u = 0;
2460 rcStrict = iemMemStackPopU16Ex(pIemCpu, &NewRip.Words.w0, &NewRsp);
2461 break;
2462 case IEMMODE_32BIT:
2463 NewRip.u = 0;
2464 rcStrict = iemMemStackPopU32Ex(pIemCpu, &NewRip.DWords.dw0, &NewRsp);
2465 break;
2466 case IEMMODE_64BIT:
2467 rcStrict = iemMemStackPopU64Ex(pIemCpu, &NewRip.u, &NewRsp);
2468 break;
2469 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2470 }
2471 if (rcStrict != VINF_SUCCESS)
2472 return rcStrict;
2473
2474 /* Check the new RSP before loading it. */
2475 /** @todo Should test this as the intel+amd pseudo code doesn't mention half
2476 * of it. The canonical test is performed here and for call. */
2477 if (enmEffOpSize != IEMMODE_64BIT)
2478 {
2479 if (NewRip.DWords.dw0 > pCtx->cs.u32Limit)
2480 {
2481 Log(("retn newrip=%llx - out of bounds (%x) -> #GP\n", NewRip.u, pCtx->cs.u32Limit));
2482 return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2483 }
2484 }
2485 else
2486 {
2487 if (!IEM_IS_CANONICAL(NewRip.u))
2488 {
2489 Log(("retn newrip=%llx - not canonical -> #GP\n", NewRip.u));
2490 return iemRaiseNotCanonical(pIemCpu);
2491 }
2492 }
2493
2494 /* Commit it. */
2495 pCtx->rip = NewRip.u;
2496 pCtx->rsp = NewRsp.u;
2497 if (cbPop)
2498 iemRegAddToRsp(pIemCpu, pCtx, cbPop);
2499 pCtx->eflags.Bits.u1RF = 0;
2500
2501 return VINF_SUCCESS;
2502}
2503
2504
2505/**
2506 * Implements enter.
2507 *
2508 * We're doing this in C because the instruction is insane, even for the
2509 * u8NestingLevel=0 case dealing with the stack is tedious.
2510 *
2511 * @param enmEffOpSize The effective operand size.
2512 */
2513IEM_CIMPL_DEF_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters)
2514{
2515 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2516
2517 /* Push RBP, saving the old value in TmpRbp. */
2518 RTUINT64U NewRsp; NewRsp.u = pCtx->rsp;
2519 RTUINT64U TmpRbp; TmpRbp.u = pCtx->rbp;
2520 RTUINT64U NewRbp;
2521 VBOXSTRICTRC rcStrict;
2522 if (enmEffOpSize == IEMMODE_64BIT)
2523 {
2524 rcStrict = iemMemStackPushU64Ex(pIemCpu, TmpRbp.u, &NewRsp);
2525 NewRbp = NewRsp;
2526 }
2527 else if (enmEffOpSize == IEMMODE_32BIT)
2528 {
2529 rcStrict = iemMemStackPushU32Ex(pIemCpu, TmpRbp.DWords.dw0, &NewRsp);
2530 NewRbp = NewRsp;
2531 }
2532 else
2533 {
2534 rcStrict = iemMemStackPushU16Ex(pIemCpu, TmpRbp.Words.w0, &NewRsp);
2535 NewRbp = TmpRbp;
2536 NewRbp.Words.w0 = NewRsp.Words.w0;
2537 }
2538 if (rcStrict != VINF_SUCCESS)
2539 return rcStrict;
2540
2541 /* Copy the parameters (aka nesting levels by Intel). */
2542 cParameters &= 0x1f;
2543 if (cParameters > 0)
2544 {
2545 switch (enmEffOpSize)
2546 {
2547 case IEMMODE_16BIT:
2548 if (pCtx->ss.Attr.n.u1DefBig)
2549 TmpRbp.DWords.dw0 -= 2;
2550 else
2551 TmpRbp.Words.w0 -= 2;
2552 do
2553 {
2554 uint16_t u16Tmp;
2555 rcStrict = iemMemStackPopU16Ex(pIemCpu, &u16Tmp, &TmpRbp);
2556 if (rcStrict != VINF_SUCCESS)
2557 break;
2558 rcStrict = iemMemStackPushU16Ex(pIemCpu, u16Tmp, &NewRsp);
2559 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2560 break;
2561
2562 case IEMMODE_32BIT:
2563 if (pCtx->ss.Attr.n.u1DefBig)
2564 TmpRbp.DWords.dw0 -= 4;
2565 else
2566 TmpRbp.Words.w0 -= 4;
2567 do
2568 {
2569 uint32_t u32Tmp;
2570 rcStrict = iemMemStackPopU32Ex(pIemCpu, &u32Tmp, &TmpRbp);
2571 if (rcStrict != VINF_SUCCESS)
2572 break;
2573 rcStrict = iemMemStackPushU32Ex(pIemCpu, u32Tmp, &NewRsp);
2574 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2575 break;
2576
2577 case IEMMODE_64BIT:
2578 TmpRbp.u -= 8;
2579 do
2580 {
2581 uint64_t u64Tmp;
2582 rcStrict = iemMemStackPopU64Ex(pIemCpu, &u64Tmp, &TmpRbp);
2583 if (rcStrict != VINF_SUCCESS)
2584 break;
2585 rcStrict = iemMemStackPushU64Ex(pIemCpu, u64Tmp, &NewRsp);
2586 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2587 break;
2588
2589 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2590 }
2591 if (rcStrict != VINF_SUCCESS)
2592 return VINF_SUCCESS;
2593
2594 /* Push the new RBP */
2595 if (enmEffOpSize == IEMMODE_64BIT)
2596 rcStrict = iemMemStackPushU64Ex(pIemCpu, NewRbp.u, &NewRsp);
2597 else if (enmEffOpSize == IEMMODE_32BIT)
2598 rcStrict = iemMemStackPushU32Ex(pIemCpu, NewRbp.DWords.dw0, &NewRsp);
2599 else
2600 rcStrict = iemMemStackPushU16Ex(pIemCpu, NewRbp.Words.w0, &NewRsp);
2601 if (rcStrict != VINF_SUCCESS)
2602 return rcStrict;
2603
2604 }
2605
2606 /* Recalc RSP. */
2607 iemRegSubFromRspEx(pIemCpu, pCtx, &NewRsp, cbFrame);
2608
2609 /** @todo Should probe write access at the new RSP according to AMD. */
2610
2611 /* Commit it. */
2612 pCtx->rbp = NewRbp.u;
2613 pCtx->rsp = NewRsp.u;
2614 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
2615
2616 return VINF_SUCCESS;
2617}
2618
2619
2620
2621/**
2622 * Implements leave.
2623 *
2624 * We're doing this in C because messing with the stack registers is annoying
2625 * since they depends on SS attributes.
2626 *
2627 * @param enmEffOpSize The effective operand size.
2628 */
2629IEM_CIMPL_DEF_1(iemCImpl_leave, IEMMODE, enmEffOpSize)
2630{
2631 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2632
2633 /* Calculate the intermediate RSP from RBP and the stack attributes. */
2634 RTUINT64U NewRsp;
2635 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
2636 NewRsp.u = pCtx->rbp;
2637 else if (pCtx->ss.Attr.n.u1DefBig)
2638 NewRsp.u = pCtx->ebp;
2639 else
2640 {
2641 /** @todo Check that LEAVE actually preserve the high EBP bits. */
2642 NewRsp.u = pCtx->rsp;
2643 NewRsp.Words.w0 = pCtx->bp;
2644 }
2645
2646 /* Pop RBP according to the operand size. */
2647 VBOXSTRICTRC rcStrict;
2648 RTUINT64U NewRbp;
2649 switch (enmEffOpSize)
2650 {
2651 case IEMMODE_16BIT:
2652 NewRbp.u = pCtx->rbp;
2653 rcStrict = iemMemStackPopU16Ex(pIemCpu, &NewRbp.Words.w0, &NewRsp);
2654 break;
2655 case IEMMODE_32BIT:
2656 NewRbp.u = 0;
2657 rcStrict = iemMemStackPopU32Ex(pIemCpu, &NewRbp.DWords.dw0, &NewRsp);
2658 break;
2659 case IEMMODE_64BIT:
2660 rcStrict = iemMemStackPopU64Ex(pIemCpu, &NewRbp.u, &NewRsp);
2661 break;
2662 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2663 }
2664 if (rcStrict != VINF_SUCCESS)
2665 return rcStrict;
2666
2667
2668 /* Commit it. */
2669 pCtx->rbp = NewRbp.u;
2670 pCtx->rsp = NewRsp.u;
2671 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
2672
2673 return VINF_SUCCESS;
2674}
2675
2676
2677/**
2678 * Implements int3 and int XX.
2679 *
2680 * @param u8Int The interrupt vector number.
2681 * @param fIsBpInstr Is it the breakpoint instruction.
2682 */
2683IEM_CIMPL_DEF_2(iemCImpl_int, uint8_t, u8Int, bool, fIsBpInstr)
2684{
2685 Assert(pIemCpu->cXcptRecursions == 0);
2686 return iemRaiseXcptOrInt(pIemCpu,
2687 cbInstr,
2688 u8Int,
2689 (fIsBpInstr ? IEM_XCPT_FLAGS_BP_INSTR : 0) | IEM_XCPT_FLAGS_T_SOFT_INT,
2690 0,
2691 0);
2692}
2693
2694
2695/**
2696 * Implements iret for real mode and V8086 mode.
2697 *
2698 * @param enmEffOpSize The effective operand size.
2699 */
2700IEM_CIMPL_DEF_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize)
2701{
2702 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2703 X86EFLAGS Efl;
2704 Efl.u = IEMMISC_GET_EFL(pIemCpu, pCtx);
2705 NOREF(cbInstr);
2706
2707 /*
2708 * iret throws an exception if VME isn't enabled.
2709 */
2710 if ( Efl.Bits.u1VM
2711 && Efl.Bits.u2IOPL != 3
2712 && !(pCtx->cr4 & X86_CR4_VME))
2713 return iemRaiseGeneralProtectionFault0(pIemCpu);
2714
2715 /*
2716 * Do the stack bits, but don't commit RSP before everything checks
2717 * out right.
2718 */
2719 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2720 VBOXSTRICTRC rcStrict;
2721 RTCPTRUNION uFrame;
2722 uint16_t uNewCs;
2723 uint32_t uNewEip;
2724 uint32_t uNewFlags;
2725 uint64_t uNewRsp;
2726 if (enmEffOpSize == IEMMODE_32BIT)
2727 {
2728 rcStrict = iemMemStackPopBeginSpecial(pIemCpu, 12, &uFrame.pv, &uNewRsp);
2729 if (rcStrict != VINF_SUCCESS)
2730 return rcStrict;
2731 uNewEip = uFrame.pu32[0];
2732 if (uNewEip > UINT16_MAX)
2733 return iemRaiseGeneralProtectionFault0(pIemCpu);
2734
2735 uNewCs = (uint16_t)uFrame.pu32[1];
2736 uNewFlags = uFrame.pu32[2];
2737 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2738 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT
2739 | X86_EFL_RF /*| X86_EFL_VM*/ | X86_EFL_AC /*|X86_EFL_VIF*/ /*|X86_EFL_VIP*/
2740 | X86_EFL_ID;
2741 uNewFlags |= Efl.u & (X86_EFL_VM | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_1);
2742 }
2743 else
2744 {
2745 rcStrict = iemMemStackPopBeginSpecial(pIemCpu, 6, &uFrame.pv, &uNewRsp);
2746 if (rcStrict != VINF_SUCCESS)
2747 return rcStrict;
2748 uNewEip = uFrame.pu16[0];
2749 uNewCs = uFrame.pu16[1];
2750 uNewFlags = uFrame.pu16[2];
2751 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2752 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT;
2753 uNewFlags |= Efl.u & ((UINT32_C(0xffff0000) | X86_EFL_1) & ~X86_EFL_RF);
2754 /** @todo The intel pseudo code does not indicate what happens to
2755 * reserved flags. We just ignore them. */
2756 }
2757 /** @todo Check how this is supposed to work if sp=0xfffe. */
2758 Log7(("iemCImpl_iret_real_v8086: uNewCs=%#06x uNewRip=%#010x uNewFlags=%#x uNewRsp=%#18llx\n",
2759 uNewCs, uNewEip, uNewFlags, uNewRsp));
2760
2761 /*
2762 * Check the limit of the new EIP.
2763 */
2764 /** @todo Only the AMD pseudo code check the limit here, what's
2765 * right? */
2766 if (uNewEip > pCtx->cs.u32Limit)
2767 return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2768
2769 /*
2770 * V8086 checks and flag adjustments
2771 */
2772 if (Efl.Bits.u1VM)
2773 {
2774 if (Efl.Bits.u2IOPL == 3)
2775 {
2776 /* Preserve IOPL and clear RF. */
2777 uNewFlags &= ~(X86_EFL_IOPL | X86_EFL_RF);
2778 uNewFlags |= Efl.u & (X86_EFL_IOPL);
2779 }
2780 else if ( enmEffOpSize == IEMMODE_16BIT
2781 && ( !(uNewFlags & X86_EFL_IF)
2782 || !Efl.Bits.u1VIP )
2783 && !(uNewFlags & X86_EFL_TF) )
2784 {
2785 /* Move IF to VIF, clear RF and preserve IF and IOPL.*/
2786 uNewFlags &= ~X86_EFL_VIF;
2787 uNewFlags |= (uNewFlags & X86_EFL_IF) << (19 - 9);
2788 uNewFlags &= ~(X86_EFL_IF | X86_EFL_IOPL | X86_EFL_RF);
2789 uNewFlags |= Efl.u & (X86_EFL_IF | X86_EFL_IOPL);
2790 }
2791 else
2792 return iemRaiseGeneralProtectionFault0(pIemCpu);
2793 Log7(("iemCImpl_iret_real_v8086: u1VM=1: adjusted uNewFlags=%#x\n", uNewFlags));
2794 }
2795
2796 /*
2797 * Commit the operation.
2798 */
2799 rcStrict = iemMemStackPopCommitSpecial(pIemCpu, uFrame.pv, uNewRsp);
2800 if (rcStrict != VINF_SUCCESS)
2801 return rcStrict;
2802#ifdef DBGFTRACE_ENABLED
2803 RTTraceBufAddMsgF(IEMCPU_TO_VM(pIemCpu)->CTX_SUFF(hTraceBuf), "iret/rm %04x:%04x -> %04x:%04x %x %04llx",
2804 pCtx->cs.Sel, pCtx->eip, uNewCs, uNewEip, uNewFlags, uNewRsp);
2805#endif
2806
2807 pCtx->rip = uNewEip;
2808 pCtx->cs.Sel = uNewCs;
2809 pCtx->cs.ValidSel = uNewCs;
2810 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2811 pCtx->cs.u64Base = (uint32_t)uNewCs << 4;
2812 /** @todo do we load attribs and limit as well? */
2813 Assert(uNewFlags & X86_EFL_1);
2814 IEMMISC_SET_EFL(pIemCpu, pCtx, uNewFlags);
2815
2816 return VINF_SUCCESS;
2817}
2818
2819
2820/**
2821 * Loads a segment register when entering V8086 mode.
2822 *
2823 * @param pSReg The segment register.
2824 * @param uSeg The segment to load.
2825 */
2826static void iemCImplCommonV8086LoadSeg(PCPUMSELREG pSReg, uint16_t uSeg)
2827{
2828 pSReg->Sel = uSeg;
2829 pSReg->ValidSel = uSeg;
2830 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
2831 pSReg->u64Base = (uint32_t)uSeg << 4;
2832 pSReg->u32Limit = 0xffff;
2833 pSReg->Attr.u = X86_SEL_TYPE_RW_ACC | RT_BIT(4) /*!sys*/ | RT_BIT(7) /*P*/ | (3 /*DPL*/ << 5); /* VT-x wants 0xf3 */
2834 /** @todo Testcase: Check if VT-x really needs this and what it does itself when
2835 * IRET'ing to V8086. */
2836}
2837
2838
2839/**
2840 * Implements iret for protected mode returning to V8086 mode.
2841 *
2842 * @param pCtx Pointer to the CPU context.
2843 * @param uNewEip The new EIP.
2844 * @param uNewCs The new CS.
2845 * @param uNewFlags The new EFLAGS.
2846 * @param uNewRsp The RSP after the initial IRET frame.
2847 *
2848 * @note This can only be a 32-bit iret du to the X86_EFL_VM position.
2849 */
2850IEM_CIMPL_DEF_5(iemCImpl_iret_prot_v8086, PCPUMCTX, pCtx, uint32_t, uNewEip, uint16_t, uNewCs,
2851 uint32_t, uNewFlags, uint64_t, uNewRsp)
2852{
2853 /*
2854 * Pop the V8086 specific frame bits off the stack.
2855 */
2856 VBOXSTRICTRC rcStrict;
2857 RTCPTRUNION uFrame;
2858 rcStrict = iemMemStackPopContinueSpecial(pIemCpu, 24, &uFrame.pv, &uNewRsp);
2859 if (rcStrict != VINF_SUCCESS)
2860 return rcStrict;
2861 uint32_t uNewEsp = uFrame.pu32[0];
2862 uint16_t uNewSs = uFrame.pu32[1];
2863 uint16_t uNewEs = uFrame.pu32[2];
2864 uint16_t uNewDs = uFrame.pu32[3];
2865 uint16_t uNewFs = uFrame.pu32[4];
2866 uint16_t uNewGs = uFrame.pu32[5];
2867 rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R); /* don't use iemMemStackPopCommitSpecial here. */
2868 if (rcStrict != VINF_SUCCESS)
2869 return rcStrict;
2870
2871 /*
2872 * Commit the operation.
2873 */
2874 uNewFlags &= X86_EFL_LIVE_MASK;
2875 uNewFlags |= X86_EFL_RA1_MASK;
2876#ifdef DBGFTRACE_ENABLED
2877 RTTraceBufAddMsgF(IEMCPU_TO_VM(pIemCpu)->CTX_SUFF(hTraceBuf), "iret/p/v %04x:%08x -> %04x:%04x %x %04x:%04x",
2878 pCtx->cs.Sel, pCtx->eip, uNewCs, uNewEip, uNewFlags, uNewSs, uNewEsp);
2879#endif
2880
2881 IEMMISC_SET_EFL(pIemCpu, pCtx, uNewFlags);
2882 iemCImplCommonV8086LoadSeg(&pCtx->cs, uNewCs);
2883 iemCImplCommonV8086LoadSeg(&pCtx->ss, uNewSs);
2884 iemCImplCommonV8086LoadSeg(&pCtx->es, uNewEs);
2885 iemCImplCommonV8086LoadSeg(&pCtx->ds, uNewDs);
2886 iemCImplCommonV8086LoadSeg(&pCtx->fs, uNewFs);
2887 iemCImplCommonV8086LoadSeg(&pCtx->gs, uNewGs);
2888 pCtx->rip = uNewEip;
2889 pCtx->rsp = uNewEsp;
2890 pIemCpu->uCpl = 3;
2891
2892 return VINF_SUCCESS;
2893}
2894
2895
2896/**
2897 * Implements iret for protected mode returning via a nested task.
2898 *
2899 * @param enmEffOpSize The effective operand size.
2900 */
2901IEM_CIMPL_DEF_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize)
2902{
2903 Log7(("iemCImpl_iret_prot_NestedTask:\n"));
2904#ifndef IEM_IMPLEMENTS_TASKSWITCH
2905 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
2906#else
2907 /*
2908 * Read the segment selector in the link-field of the current TSS.
2909 */
2910 RTSEL uSelRet;
2911 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2912 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pIemCpu, &uSelRet, UINT8_MAX, pCtx->tr.u64Base);
2913 if (rcStrict != VINF_SUCCESS)
2914 return rcStrict;
2915
2916 /*
2917 * Fetch the returning task's TSS descriptor from the GDT.
2918 */
2919 if (uSelRet & X86_SEL_LDT)
2920 {
2921 Log(("iret_prot_NestedTask TSS not in LDT. uSelRet=%04x -> #TS\n", uSelRet));
2922 return iemRaiseTaskSwitchFaultBySelector(pIemCpu, uSelRet);
2923 }
2924
2925 IEMSELDESC TssDesc;
2926 rcStrict = iemMemFetchSelDesc(pIemCpu, &TssDesc, uSelRet, X86_XCPT_GP);
2927 if (rcStrict != VINF_SUCCESS)
2928 return rcStrict;
2929
2930 if (TssDesc.Legacy.Gate.u1DescType)
2931 {
2932 Log(("iret_prot_NestedTask Invalid TSS type. uSelRet=%04x -> #TS\n", uSelRet));
2933 return iemRaiseTaskSwitchFaultBySelector(pIemCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
2934 }
2935
2936 if ( TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_286_TSS_BUSY
2937 && TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2938 {
2939 Log(("iret_prot_NestedTask TSS is not busy. uSelRet=%04x DescType=%#x -> #TS\n", uSelRet, TssDesc.Legacy.Gate.u4Type));
2940 return iemRaiseTaskSwitchFaultBySelector(pIemCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
2941 }
2942
2943 if (!TssDesc.Legacy.Gate.u1Present)
2944 {
2945 Log(("iret_prot_NestedTask TSS is not present. uSelRet=%04x -> #NP\n", uSelRet));
2946 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
2947 }
2948
2949 uint32_t uNextEip = pCtx->eip + cbInstr;
2950 return iemTaskSwitch(pIemCpu, pIemCpu->CTX_SUFF(pCtx), IEMTASKSWITCH_IRET, uNextEip, 0 /* fFlags */, 0 /* uErr */,
2951 0 /* uCr2 */, uSelRet, &TssDesc);
2952#endif
2953}
2954
2955
2956/**
2957 * Implements iret for protected mode
2958 *
2959 * @param enmEffOpSize The effective operand size.
2960 */
2961IEM_CIMPL_DEF_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize)
2962{
2963 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2964 NOREF(cbInstr);
2965
2966 /*
2967 * Nested task return.
2968 */
2969 if (pCtx->eflags.Bits.u1NT)
2970 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot_NestedTask, enmEffOpSize);
2971
2972 /*
2973 * Normal return.
2974 *
2975 * Do the stack bits, but don't commit RSP before everything checks
2976 * out right.
2977 */
2978 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2979 VBOXSTRICTRC rcStrict;
2980 RTCPTRUNION uFrame;
2981 uint16_t uNewCs;
2982 uint32_t uNewEip;
2983 uint32_t uNewFlags;
2984 uint64_t uNewRsp;
2985 if (enmEffOpSize == IEMMODE_32BIT)
2986 {
2987 rcStrict = iemMemStackPopBeginSpecial(pIemCpu, 12, &uFrame.pv, &uNewRsp);
2988 if (rcStrict != VINF_SUCCESS)
2989 return rcStrict;
2990 uNewEip = uFrame.pu32[0];
2991 uNewCs = (uint16_t)uFrame.pu32[1];
2992 uNewFlags = uFrame.pu32[2];
2993 }
2994 else
2995 {
2996 rcStrict = iemMemStackPopBeginSpecial(pIemCpu, 6, &uFrame.pv, &uNewRsp);
2997 if (rcStrict != VINF_SUCCESS)
2998 return rcStrict;
2999 uNewEip = uFrame.pu16[0];
3000 uNewCs = uFrame.pu16[1];
3001 uNewFlags = uFrame.pu16[2];
3002 }
3003 rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R); /* don't use iemMemStackPopCommitSpecial here. */
3004 if (rcStrict != VINF_SUCCESS)
3005 return rcStrict;
3006 Log7(("iemCImpl_iret_prot: uNewCs=%#06x uNewEip=%#010x uNewFlags=%#x uNewRsp=%#18llx\n", uNewCs, uNewEip, uNewFlags, uNewRsp));
3007
3008 /*
3009 * We're hopefully not returning to V8086 mode...
3010 */
3011 if ( (uNewFlags & X86_EFL_VM)
3012 && pIemCpu->uCpl == 0)
3013 {
3014 Assert(enmEffOpSize == IEMMODE_32BIT);
3015 return IEM_CIMPL_CALL_5(iemCImpl_iret_prot_v8086, pCtx, uNewEip, uNewCs, uNewFlags, uNewRsp);
3016 }
3017
3018 /*
3019 * Protected mode.
3020 */
3021 /* Read the CS descriptor. */
3022 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3023 {
3024 Log(("iret %04x:%08x -> invalid CS selector, #GP(0)\n", uNewCs, uNewEip));
3025 return iemRaiseGeneralProtectionFault0(pIemCpu);
3026 }
3027
3028 IEMSELDESC DescCS;
3029 rcStrict = iemMemFetchSelDesc(pIemCpu, &DescCS, uNewCs, X86_XCPT_GP);
3030 if (rcStrict != VINF_SUCCESS)
3031 {
3032 Log(("iret %04x:%08x - rcStrict=%Rrc when fetching CS\n", uNewCs, uNewEip, VBOXSTRICTRC_VAL(rcStrict)));
3033 return rcStrict;
3034 }
3035
3036 /* Must be a code descriptor. */
3037 if (!DescCS.Legacy.Gen.u1DescType)
3038 {
3039 Log(("iret %04x:%08x - CS is system segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3040 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
3041 }
3042 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3043 {
3044 Log(("iret %04x:%08x - not code segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3045 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
3046 }
3047
3048#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3049 /* Raw ring-0 and ring-1 compression adjustments for PATM performance tricks and other CS leaks. */
3050 PVM pVM = IEMCPU_TO_VM(pIemCpu);
3051 if (EMIsRawRing0Enabled(pVM) && !HMIsEnabled(pVM))
3052 {
3053 if ((uNewCs & X86_SEL_RPL) == 1)
3054 {
3055 if ( pIemCpu->uCpl == 0
3056 && ( !EMIsRawRing1Enabled(pVM)
3057 || pCtx->cs.Sel == (uNewCs & X86_SEL_MASK_OFF_RPL)) )
3058 {
3059 Log(("iret: Ring-0 compression fix: uNewCS=%#x -> %#x\n", uNewCs, uNewCs & X86_SEL_MASK_OFF_RPL));
3060 uNewCs &= X86_SEL_MASK_OFF_RPL;
3061 }
3062# ifdef LOG_ENABLED
3063 else if (pIemCpu->uCpl <= 1 && EMIsRawRing1Enabled(pVM))
3064 Log(("iret: uNewCs=%#x genuine return to ring-1.\n", uNewCs));
3065# endif
3066 }
3067 else if ( (uNewCs & X86_SEL_RPL) == 2
3068 && EMIsRawRing1Enabled(pVM)
3069 && pIemCpu->uCpl <= 1)
3070 {
3071 Log(("iret: Ring-1 compression fix: uNewCS=%#x -> %#x\n", uNewCs, (uNewCs & X86_SEL_MASK_OFF_RPL) | 1));
3072 uNewCs = (uNewCs & X86_SEL_MASK_OFF_RPL) | 2;
3073 }
3074 }
3075#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
3076
3077
3078 /* Privilege checks. */
3079 if ((uNewCs & X86_SEL_RPL) < pIemCpu->uCpl)
3080 {
3081 Log(("iret %04x:%08x - RPL < CPL (%d) -> #GP\n", uNewCs, uNewEip, pIemCpu->uCpl));
3082 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
3083 }
3084 if ( (DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
3085 && (uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3086 {
3087 Log(("iret %04x:%08x - RPL < DPL (%d) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u2Dpl));
3088 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
3089 }
3090
3091 /* Present? */
3092 if (!DescCS.Legacy.Gen.u1Present)
3093 {
3094 Log(("iret %04x:%08x - CS not present -> #NP\n", uNewCs, uNewEip));
3095 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uNewCs);
3096 }
3097
3098 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3099
3100 /*
3101 * Return to outer level?
3102 */
3103 if ((uNewCs & X86_SEL_RPL) != pIemCpu->uCpl)
3104 {
3105 uint16_t uNewSS;
3106 uint32_t uNewESP;
3107 if (enmEffOpSize == IEMMODE_32BIT)
3108 {
3109 rcStrict = iemMemStackPopContinueSpecial(pIemCpu, 8, &uFrame.pv, &uNewRsp);
3110 if (rcStrict != VINF_SUCCESS)
3111 return rcStrict;
3112 uNewESP = uFrame.pu32[0];
3113 uNewSS = (uint16_t)uFrame.pu32[1];
3114 }
3115 else
3116 {
3117 rcStrict = iemMemStackPopContinueSpecial(pIemCpu, 4, &uFrame.pv, &uNewRsp);
3118 if (rcStrict != VINF_SUCCESS)
3119 return rcStrict;
3120 uNewESP = uFrame.pu16[0];
3121 uNewSS = uFrame.pu16[1];
3122 }
3123 rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R);
3124 if (rcStrict != VINF_SUCCESS)
3125 return rcStrict;
3126 Log7(("iemCImpl_iret_prot: uNewSS=%#06x uNewESP=%#010x\n", uNewSS, uNewESP));
3127
3128 /* Read the SS descriptor. */
3129 if (!(uNewSS & X86_SEL_MASK_OFF_RPL))
3130 {
3131 Log(("iret %04x:%08x/%04x:%08x -> invalid SS selector, #GP(0)\n", uNewCs, uNewEip, uNewSS, uNewESP));
3132 return iemRaiseGeneralProtectionFault0(pIemCpu);
3133 }
3134
3135 IEMSELDESC DescSS;
3136 rcStrict = iemMemFetchSelDesc(pIemCpu, &DescSS, uNewSS, X86_XCPT_GP); /** @todo Correct exception? */
3137 if (rcStrict != VINF_SUCCESS)
3138 {
3139 Log(("iret %04x:%08x/%04x:%08x - %Rrc when fetching SS\n",
3140 uNewCs, uNewEip, uNewSS, uNewESP, VBOXSTRICTRC_VAL(rcStrict)));
3141 return rcStrict;
3142 }
3143
3144 /* Privilege checks. */
3145 if ((uNewSS & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3146 {
3147 Log(("iret %04x:%08x/%04x:%08x -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewEip, uNewSS, uNewESP));
3148 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewSS);
3149 }
3150 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3151 {
3152 Log(("iret %04x:%08x/%04x:%08x -> SS.DPL (%d) != CS.RPL -> #GP\n",
3153 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u2Dpl));
3154 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewSS);
3155 }
3156
3157 /* Must be a writeable data segment descriptor. */
3158 if (!DescSS.Legacy.Gen.u1DescType)
3159 {
3160 Log(("iret %04x:%08x/%04x:%08x -> SS is system segment (%#x) -> #GP\n",
3161 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3162 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewSS);
3163 }
3164 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3165 {
3166 Log(("iret %04x:%08x/%04x:%08x - not writable data segment (%#x) -> #GP\n",
3167 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3168 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewSS);
3169 }
3170
3171 /* Present? */
3172 if (!DescSS.Legacy.Gen.u1Present)
3173 {
3174 Log(("iret %04x:%08x/%04x:%08x -> SS not present -> #SS\n", uNewCs, uNewEip, uNewSS, uNewESP));
3175 return iemRaiseStackSelectorNotPresentBySelector(pIemCpu, uNewSS);
3176 }
3177
3178 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3179
3180 /* Check EIP. */
3181 if (uNewEip > cbLimitCS)
3182 {
3183 Log(("iret %04x:%08x/%04x:%08x -> EIP is out of bounds (%#x) -> #GP(0)\n",
3184 uNewCs, uNewEip, uNewSS, uNewESP, cbLimitCS));
3185 /** @todo: Which is it, #GP(0) or #GP(sel)? */
3186 return iemRaiseSelectorBoundsBySelector(pIemCpu, uNewCs);
3187 }
3188
3189 /*
3190 * Commit the changes, marking CS and SS accessed first since
3191 * that may fail.
3192 */
3193 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3194 {
3195 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewCs);
3196 if (rcStrict != VINF_SUCCESS)
3197 return rcStrict;
3198 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3199 }
3200 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3201 {
3202 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewSS);
3203 if (rcStrict != VINF_SUCCESS)
3204 return rcStrict;
3205 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3206 }
3207
3208 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3209 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3210 if (enmEffOpSize != IEMMODE_16BIT)
3211 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3212 if (pIemCpu->uCpl == 0)
3213 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3214 else if (pIemCpu->uCpl <= pCtx->eflags.Bits.u2IOPL)
3215 fEFlagsMask |= X86_EFL_IF;
3216 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pIemCpu, pCtx);
3217 fEFlagsNew &= ~fEFlagsMask;
3218 fEFlagsNew |= uNewFlags & fEFlagsMask;
3219#ifdef DBGFTRACE_ENABLED
3220 RTTraceBufAddMsgF(IEMCPU_TO_VM(pIemCpu)->CTX_SUFF(hTraceBuf), "iret/%up%u %04x:%08x -> %04x:%04x %x %04x:%04x",
3221 pIemCpu->uCpl, uNewCs & X86_SEL_RPL, pCtx->cs.Sel, pCtx->eip,
3222 uNewCs, uNewEip, uNewFlags, uNewSS, uNewESP);
3223#endif
3224
3225 IEMMISC_SET_EFL(pIemCpu, pCtx, fEFlagsNew);
3226 pCtx->rip = uNewEip;
3227 pCtx->cs.Sel = uNewCs;
3228 pCtx->cs.ValidSel = uNewCs;
3229 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
3230 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3231 pCtx->cs.u32Limit = cbLimitCS;
3232 pCtx->cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3233 if (!pCtx->ss.Attr.n.u1DefBig)
3234 pCtx->sp = (uint16_t)uNewESP;
3235 else
3236 pCtx->rsp = uNewESP;
3237 pCtx->ss.Sel = uNewSS;
3238 pCtx->ss.ValidSel = uNewSS;
3239 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
3240 pCtx->ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3241 pCtx->ss.u32Limit = cbLimitSs;
3242 pCtx->ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3243
3244 pIemCpu->uCpl = uNewCs & X86_SEL_RPL;
3245 iemHlpAdjustSelectorForNewCpl(pIemCpu, uNewCs & X86_SEL_RPL, &pCtx->ds);
3246 iemHlpAdjustSelectorForNewCpl(pIemCpu, uNewCs & X86_SEL_RPL, &pCtx->es);
3247 iemHlpAdjustSelectorForNewCpl(pIemCpu, uNewCs & X86_SEL_RPL, &pCtx->fs);
3248 iemHlpAdjustSelectorForNewCpl(pIemCpu, uNewCs & X86_SEL_RPL, &pCtx->gs);
3249
3250 /* Done! */
3251
3252 }
3253 /*
3254 * Return to the same level.
3255 */
3256 else
3257 {
3258 /* Check EIP. */
3259 if (uNewEip > cbLimitCS)
3260 {
3261 Log(("iret %04x:%08x - EIP is out of bounds (%#x) -> #GP(0)\n", uNewCs, uNewEip, cbLimitCS));
3262 /** @todo: Which is it, #GP(0) or #GP(sel)? */
3263 return iemRaiseSelectorBoundsBySelector(pIemCpu, uNewCs);
3264 }
3265
3266 /*
3267 * Commit the changes, marking CS first since it may fail.
3268 */
3269 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3270 {
3271 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewCs);
3272 if (rcStrict != VINF_SUCCESS)
3273 return rcStrict;
3274 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3275 }
3276
3277 X86EFLAGS NewEfl;
3278 NewEfl.u = IEMMISC_GET_EFL(pIemCpu, pCtx);
3279 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3280 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3281 if (enmEffOpSize != IEMMODE_16BIT)
3282 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3283 if (pIemCpu->uCpl == 0)
3284 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3285 else if (pIemCpu->uCpl <= NewEfl.Bits.u2IOPL)
3286 fEFlagsMask |= X86_EFL_IF;
3287 NewEfl.u &= ~fEFlagsMask;
3288 NewEfl.u |= fEFlagsMask & uNewFlags;
3289#ifdef DBGFTRACE_ENABLED
3290 RTTraceBufAddMsgF(IEMCPU_TO_VM(pIemCpu)->CTX_SUFF(hTraceBuf), "iret/%up %04x:%08x -> %04x:%04x %x %04x:%04llx",
3291 pIemCpu->uCpl, pCtx->cs.Sel, pCtx->eip,
3292 uNewCs, uNewEip, uNewFlags, pCtx->ss.Sel, uNewRsp);
3293#endif
3294
3295 IEMMISC_SET_EFL(pIemCpu, pCtx, NewEfl.u);
3296 pCtx->rip = uNewEip;
3297 pCtx->cs.Sel = uNewCs;
3298 pCtx->cs.ValidSel = uNewCs;
3299 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
3300 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3301 pCtx->cs.u32Limit = cbLimitCS;
3302 pCtx->cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3303 pCtx->rsp = uNewRsp;
3304 /* Done! */
3305 }
3306 return VINF_SUCCESS;
3307}
3308
3309
3310/**
3311 * Implements iret for long mode
3312 *
3313 * @param enmEffOpSize The effective operand size.
3314 */
3315IEM_CIMPL_DEF_1(iemCImpl_iret_long, IEMMODE, enmEffOpSize)
3316{
3317 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
3318 NOREF(cbInstr);
3319
3320 /*
3321 * Nested task return is not supported in long mode.
3322 */
3323 if (pCtx->eflags.Bits.u1NT)
3324 {
3325 Log(("iretq with NT=1 (eflags=%#x) -> #GP(0)\n", pCtx->eflags.u));
3326 return iemRaiseGeneralProtectionFault0(pIemCpu);
3327 }
3328
3329 /*
3330 * Normal return.
3331 *
3332 * Do the stack bits, but don't commit RSP before everything checks
3333 * out right.
3334 */
3335 VBOXSTRICTRC rcStrict;
3336 RTCPTRUNION uFrame;
3337 uint64_t uNewRip;
3338 uint16_t uNewCs;
3339 uint16_t uNewSs;
3340 uint32_t uNewFlags;
3341 uint64_t uNewRsp;
3342 if (enmEffOpSize == IEMMODE_64BIT)
3343 {
3344 rcStrict = iemMemStackPopBeginSpecial(pIemCpu, 5*8, &uFrame.pv, &uNewRsp);
3345 if (rcStrict != VINF_SUCCESS)
3346 return rcStrict;
3347 uNewRip = uFrame.pu64[0];
3348 uNewCs = (uint16_t)uFrame.pu64[1];
3349 uNewFlags = (uint32_t)uFrame.pu64[2];
3350 uNewRsp = uFrame.pu64[3];
3351 uNewSs = (uint16_t)uFrame.pu64[4];
3352 }
3353 else if (enmEffOpSize == IEMMODE_32BIT)
3354 {
3355 rcStrict = iemMemStackPopBeginSpecial(pIemCpu, 5*4, &uFrame.pv, &uNewRsp);
3356 if (rcStrict != VINF_SUCCESS)
3357 return rcStrict;
3358 uNewRip = uFrame.pu32[0];
3359 uNewCs = (uint16_t)uFrame.pu32[1];
3360 uNewFlags = uFrame.pu32[2];
3361 uNewRsp = uFrame.pu32[3];
3362 uNewSs = (uint16_t)uFrame.pu32[4];
3363 }
3364 else
3365 {
3366 Assert(enmEffOpSize == IEMMODE_16BIT);
3367 rcStrict = iemMemStackPopBeginSpecial(pIemCpu, 5*2, &uFrame.pv, &uNewRsp);
3368 if (rcStrict != VINF_SUCCESS)
3369 return rcStrict;
3370 uNewRip = uFrame.pu16[0];
3371 uNewCs = uFrame.pu16[1];
3372 uNewFlags = uFrame.pu16[2];
3373 uNewRsp = uFrame.pu16[3];
3374 uNewSs = uFrame.pu16[4];
3375 }
3376 rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R); /* don't use iemMemStackPopCommitSpecial here. */
3377 if (rcStrict != VINF_SUCCESS)
3378 return rcStrict;
3379 Log7(("iretq stack: cs:rip=%04x:%016RX64 rflags=%016RX64 ss:rsp=%04x:%016RX64\n", uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp));
3380
3381 /*
3382 * Check stuff.
3383 */
3384 /* Read the CS descriptor. */
3385 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3386 {
3387 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid CS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3388 return iemRaiseGeneralProtectionFault0(pIemCpu);
3389 }
3390
3391 IEMSELDESC DescCS;
3392 rcStrict = iemMemFetchSelDesc(pIemCpu, &DescCS, uNewCs, X86_XCPT_GP);
3393 if (rcStrict != VINF_SUCCESS)
3394 {
3395 Log(("iret %04x:%016RX64/%04x:%016RX64 - rcStrict=%Rrc when fetching CS\n",
3396 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3397 return rcStrict;
3398 }
3399
3400 /* Must be a code descriptor. */
3401 if ( !DescCS.Legacy.Gen.u1DescType
3402 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3403 {
3404 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS is not a code segment T=%u T=%#xu -> #GP\n",
3405 uNewCs, uNewRip, uNewSs, uNewRsp, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
3406 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
3407 }
3408
3409 /* Privilege checks. */
3410 uint8_t const uNewCpl = uNewCs & X86_SEL_RPL;
3411 if ((uNewCs & X86_SEL_RPL) < pIemCpu->uCpl)
3412 {
3413 Log(("iret %04x:%016RX64/%04x:%016RX64 - RPL < CPL (%d) -> #GP\n", uNewCs, uNewRip, uNewSs, uNewRsp, pIemCpu->uCpl));
3414 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
3415 }
3416 if ( (DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
3417 && (uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3418 {
3419 Log(("iret %04x:%016RX64/%04x:%016RX64 - RPL < DPL (%d) -> #GP\n",
3420 uNewCs, uNewRip, uNewSs, uNewRsp, DescCS.Legacy.Gen.u2Dpl));
3421 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCs);
3422 }
3423
3424 /* Present? */
3425 if (!DescCS.Legacy.Gen.u1Present)
3426 {
3427 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS not present -> #NP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3428 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uNewCs);
3429 }
3430
3431 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3432
3433 /* Read the SS descriptor. */
3434 IEMSELDESC DescSS;
3435 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3436 {
3437 if ( !DescCS.Legacy.Gen.u1Long
3438 || DescCS.Legacy.Gen.u1DefBig /** @todo exactly how does iret (and others) behave with u1Long=1 and u1DefBig=1? \#GP(sel)? */
3439 || uNewCpl > 2) /** @todo verify SS=0 impossible for ring-3. */
3440 {
3441 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid SS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3442 return iemRaiseGeneralProtectionFault0(pIemCpu);
3443 }
3444 DescSS.Legacy.u = 0;
3445 }
3446 else
3447 {
3448 rcStrict = iemMemFetchSelDesc(pIemCpu, &DescSS, uNewSs, X86_XCPT_GP); /** @todo Correct exception? */
3449 if (rcStrict != VINF_SUCCESS)
3450 {
3451 Log(("iret %04x:%016RX64/%04x:%016RX64 - %Rrc when fetching SS\n",
3452 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3453 return rcStrict;
3454 }
3455 }
3456
3457 /* Privilege checks. */
3458 if ((uNewSs & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3459 {
3460 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3461 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewSs);
3462 }
3463
3464 uint32_t cbLimitSs;
3465 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3466 cbLimitSs = UINT32_MAX;
3467 else
3468 {
3469 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3470 {
3471 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.DPL (%d) != CS.RPL -> #GP\n",
3472 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u2Dpl));
3473 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewSs);
3474 }
3475
3476 /* Must be a writeable data segment descriptor. */
3477 if (!DescSS.Legacy.Gen.u1DescType)
3478 {
3479 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS is system segment (%#x) -> #GP\n",
3480 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3481 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewSs);
3482 }
3483 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3484 {
3485 Log(("iret %04x:%016RX64/%04x:%016RX64 - not writable data segment (%#x) -> #GP\n",
3486 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3487 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewSs);
3488 }
3489
3490 /* Present? */
3491 if (!DescSS.Legacy.Gen.u1Present)
3492 {
3493 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS not present -> #SS\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3494 return iemRaiseStackSelectorNotPresentBySelector(pIemCpu, uNewSs);
3495 }
3496 cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3497 }
3498
3499 /* Check EIP. */
3500 if (DescCS.Legacy.Gen.u1Long)
3501 {
3502 if (!IEM_IS_CANONICAL(uNewRip))
3503 {
3504 Log(("iret %04x:%016RX64/%04x:%016RX64 -> RIP is not canonical -> #GP(0)\n",
3505 uNewCs, uNewRip, uNewSs, uNewRsp));
3506 return iemRaiseSelectorBoundsBySelector(pIemCpu, uNewCs);
3507 }
3508 }
3509 else
3510 {
3511 if (uNewRip > cbLimitCS)
3512 {
3513 Log(("iret %04x:%016RX64/%04x:%016RX64 -> EIP is out of bounds (%#x) -> #GP(0)\n",
3514 uNewCs, uNewRip, uNewSs, uNewRsp, cbLimitCS));
3515 /** @todo: Which is it, #GP(0) or #GP(sel)? */
3516 return iemRaiseSelectorBoundsBySelector(pIemCpu, uNewCs);
3517 }
3518 }
3519
3520 /*
3521 * Commit the changes, marking CS and SS accessed first since
3522 * that may fail.
3523 */
3524 /** @todo where exactly are these actually marked accessed by a real CPU? */
3525 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3526 {
3527 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewCs);
3528 if (rcStrict != VINF_SUCCESS)
3529 return rcStrict;
3530 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3531 }
3532 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3533 {
3534 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewSs);
3535 if (rcStrict != VINF_SUCCESS)
3536 return rcStrict;
3537 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3538 }
3539
3540 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3541 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3542 if (enmEffOpSize != IEMMODE_16BIT)
3543 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3544 if (pIemCpu->uCpl == 0)
3545 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is ignored */
3546 else if (pIemCpu->uCpl <= pCtx->eflags.Bits.u2IOPL)
3547 fEFlagsMask |= X86_EFL_IF;
3548 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pIemCpu, pCtx);
3549 fEFlagsNew &= ~fEFlagsMask;
3550 fEFlagsNew |= uNewFlags & fEFlagsMask;
3551#ifdef DBGFTRACE_ENABLED
3552 RTTraceBufAddMsgF(IEMCPU_TO_VM(pIemCpu)->CTX_SUFF(hTraceBuf), "iret/%ul%u %08llx -> %04x:%04llx %llx %04x:%04llx",
3553 pIemCpu->uCpl, uNewCpl, pCtx->rip, uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp);
3554#endif
3555
3556 IEMMISC_SET_EFL(pIemCpu, pCtx, fEFlagsNew);
3557 pCtx->rip = uNewRip;
3558 pCtx->cs.Sel = uNewCs;
3559 pCtx->cs.ValidSel = uNewCs;
3560 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
3561 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3562 pCtx->cs.u32Limit = cbLimitCS;
3563 pCtx->cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3564 if (pCtx->cs.Attr.n.u1Long || pCtx->cs.Attr.n.u1DefBig)
3565 pCtx->rsp = uNewRsp;
3566 else
3567 pCtx->sp = (uint16_t)uNewRsp;
3568 pCtx->ss.Sel = uNewSs;
3569 pCtx->ss.ValidSel = uNewSs;
3570 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3571 {
3572 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
3573 pCtx->ss.Attr.u = X86DESCATTR_UNUSABLE | (uNewCpl << X86DESCATTR_DPL_SHIFT);
3574 pCtx->ss.u32Limit = UINT32_MAX;
3575 pCtx->ss.u64Base = 0;
3576 Log2(("iretq new SS: NULL\n"));
3577 }
3578 else
3579 {
3580 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
3581 pCtx->ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3582 pCtx->ss.u32Limit = cbLimitSs;
3583 pCtx->ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3584 Log2(("iretq new SS: base=%#RX64 lim=%#x attr=%#x\n", pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u));
3585 }
3586
3587 if (pIemCpu->uCpl != uNewCpl)
3588 {
3589 pIemCpu->uCpl = uNewCpl;
3590 iemHlpAdjustSelectorForNewCpl(pIemCpu, uNewCpl, &pCtx->ds);
3591 iemHlpAdjustSelectorForNewCpl(pIemCpu, uNewCpl, &pCtx->es);
3592 iemHlpAdjustSelectorForNewCpl(pIemCpu, uNewCpl, &pCtx->fs);
3593 iemHlpAdjustSelectorForNewCpl(pIemCpu, uNewCpl, &pCtx->gs);
3594 }
3595
3596 return VINF_SUCCESS;
3597}
3598
3599
3600/**
3601 * Implements iret.
3602 *
3603 * @param enmEffOpSize The effective operand size.
3604 */
3605IEM_CIMPL_DEF_1(iemCImpl_iret, IEMMODE, enmEffOpSize)
3606{
3607 /*
3608 * First, clear NMI blocking, if any, before causing any exceptions.
3609 */
3610 PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu);
3611 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
3612
3613 /*
3614 * Call a mode specific worker.
3615 */
3616 if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
3617 return IEM_CIMPL_CALL_1(iemCImpl_iret_real_v8086, enmEffOpSize);
3618 if (IEM_IS_LONG_MODE(pIemCpu))
3619 return IEM_CIMPL_CALL_1(iemCImpl_iret_long, enmEffOpSize);
3620 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot, enmEffOpSize);
3621}
3622
3623
3624/**
3625 * Implements SYSCALL (AMD and Intel64).
3626 *
3627 * @param enmEffOpSize The effective operand size.
3628 */
3629IEM_CIMPL_DEF_0(iemCImpl_syscall)
3630{
3631 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
3632
3633 /*
3634 * Check preconditions.
3635 *
3636 * Note that CPUs described in the documentation may load a few odd values
3637 * into CS and SS than we allow here. This has yet to be checked on real
3638 * hardware.
3639 */
3640 if (!(pCtx->msrEFER & MSR_K6_EFER_SCE))
3641 {
3642 Log(("syscall: Not enabled in EFER -> #UD\n"));
3643 return iemRaiseUndefinedOpcode(pIemCpu);
3644 }
3645 if (!(pCtx->cr0 & X86_CR0_PE))
3646 {
3647 Log(("syscall: Protected mode is required -> #GP(0)\n"));
3648 return iemRaiseGeneralProtectionFault0(pIemCpu);
3649 }
3650 if (IEM_IS_GUEST_CPU_INTEL(pIemCpu) && !CPUMIsGuestInLongModeEx(pCtx))
3651 {
3652 Log(("syscall: Only available in long mode on intel -> #UD\n"));
3653 return iemRaiseUndefinedOpcode(pIemCpu);
3654 }
3655
3656 /** @todo verify RPL ignoring and CS=0xfff8 (i.e. SS == 0). */
3657 /** @todo what about LDT selectors? Shouldn't matter, really. */
3658 uint16_t uNewCs = (pCtx->msrSTAR >> MSR_K6_STAR_SYSCALL_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
3659 uint16_t uNewSs = uNewCs + 8;
3660 if (uNewCs == 0 || uNewSs == 0)
3661 {
3662 Log(("syscall: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
3663 return iemRaiseGeneralProtectionFault0(pIemCpu);
3664 }
3665
3666 /* Long mode and legacy mode differs. */
3667 if (CPUMIsGuestInLongModeEx(pCtx))
3668 {
3669 uint64_t uNewRip = pIemCpu->enmCpuMode == IEMMODE_64BIT ? pCtx->msrLSTAR : pCtx-> msrCSTAR;
3670
3671 /* This test isn't in the docs, but I'm not trusting the guys writing
3672 the MSRs to have validated the values as canonical like they should. */
3673 if (!IEM_IS_CANONICAL(uNewRip))
3674 {
3675 Log(("syscall: Only available in long mode on intel -> #UD\n"));
3676 return iemRaiseUndefinedOpcode(pIemCpu);
3677 }
3678
3679 /*
3680 * Commit it.
3681 */
3682 Log(("syscall: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pCtx->cs, pCtx->rip, pCtx->rflags.u, uNewCs, uNewRip));
3683 pCtx->rcx = pCtx->rip + cbInstr;
3684 pCtx->rip = uNewRip;
3685
3686 pCtx->rflags.u &= ~X86_EFL_RF;
3687 pCtx->r11 = pCtx->rflags.u;
3688 pCtx->rflags.u &= ~pCtx->msrSFMASK;
3689 pCtx->rflags.u |= X86_EFL_1;
3690
3691 pCtx->cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
3692 pCtx->ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
3693 }
3694 else
3695 {
3696 /*
3697 * Commit it.
3698 */
3699 Log(("syscall: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n",
3700 pCtx->cs, pCtx->eip, pCtx->eflags.u, uNewCs, (uint32_t)(pCtx->msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK)));
3701 pCtx->rcx = pCtx->eip + cbInstr;
3702 pCtx->rip = pCtx->msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK;
3703 pCtx->rflags.u &= ~(X86_EFL_VM | X86_EFL_IF | X86_EFL_RF);
3704
3705 pCtx->cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
3706 pCtx->ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
3707 }
3708 pCtx->cs.Sel = uNewCs;
3709 pCtx->cs.ValidSel = uNewCs;
3710 pCtx->cs.u64Base = 0;
3711 pCtx->cs.u32Limit = UINT32_MAX;
3712 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
3713
3714 pCtx->ss.Sel = uNewSs;
3715 pCtx->ss.ValidSel = uNewSs;
3716 pCtx->ss.u64Base = 0;
3717 pCtx->ss.u32Limit = UINT32_MAX;
3718 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
3719
3720 return VINF_SUCCESS;
3721}
3722
3723
3724/**
3725 * Implements SYSRET (AMD and Intel64).
3726 */
3727IEM_CIMPL_DEF_0(iemCImpl_sysret)
3728
3729{
3730 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
3731
3732 /*
3733 * Check preconditions.
3734 *
3735 * Note that CPUs described in the documentation may load a few odd values
3736 * into CS and SS than we allow here. This has yet to be checked on real
3737 * hardware.
3738 */
3739 if (!(pCtx->msrEFER & MSR_K6_EFER_SCE))
3740 {
3741 Log(("sysret: Not enabled in EFER -> #UD\n"));
3742 return iemRaiseUndefinedOpcode(pIemCpu);
3743 }
3744 if (IEM_IS_GUEST_CPU_INTEL(pIemCpu) && !CPUMIsGuestInLongModeEx(pCtx))
3745 {
3746 Log(("sysret: Only available in long mode on intel -> #UD\n"));
3747 return iemRaiseUndefinedOpcode(pIemCpu);
3748 }
3749 if (!(pCtx->cr0 & X86_CR0_PE))
3750 {
3751 Log(("sysret: Protected mode is required -> #GP(0)\n"));
3752 return iemRaiseGeneralProtectionFault0(pIemCpu);
3753 }
3754 if (pIemCpu->uCpl != 0)
3755 {
3756 Log(("sysret: CPL must be 0 not %u -> #GP(0)\n", pIemCpu->uCpl));
3757 return iemRaiseGeneralProtectionFault0(pIemCpu);
3758 }
3759
3760 /** @todo Does SYSRET verify CS != 0 and SS != 0? Neither is valid in ring-3. */
3761 uint16_t uNewCs = (pCtx->msrSTAR >> MSR_K6_STAR_SYSRET_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
3762 uint16_t uNewSs = uNewCs + 8;
3763 if (pIemCpu->enmEffOpSize == IEMMODE_64BIT)
3764 uNewCs += 16;
3765 if (uNewCs == 0 || uNewSs == 0)
3766 {
3767 Log(("sysret: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
3768 return iemRaiseGeneralProtectionFault0(pIemCpu);
3769 }
3770
3771 /*
3772 * Commit it.
3773 */
3774 if (CPUMIsGuestInLongModeEx(pCtx))
3775 {
3776 if (pIemCpu->enmEffOpSize == IEMMODE_64BIT)
3777 {
3778 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64 [r11=%#llx]\n",
3779 pCtx->cs, pCtx->rip, pCtx->rflags.u, uNewCs, pCtx->rcx, pCtx->r11));
3780 /* Note! We disregard intel manual regarding the RCX cananonical
3781 check, ask intel+xen why AMD doesn't do it. */
3782 pCtx->rip = pCtx->rcx;
3783 pCtx->cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
3784 | (3 << X86DESCATTR_DPL_SHIFT);
3785 }
3786 else
3787 {
3788 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%08RX32 [r11=%#llx]\n",
3789 pCtx->cs, pCtx->rip, pCtx->rflags.u, uNewCs, pCtx->ecx, pCtx->r11));
3790 pCtx->rip = pCtx->ecx;
3791 pCtx->cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
3792 | (3 << X86DESCATTR_DPL_SHIFT);
3793 }
3794 /** @todo testcase: See what kind of flags we can make SYSRET restore and
3795 * what it really ignores. RF and VM are hinted at being zero, by AMD. */
3796 pCtx->rflags.u = pCtx->r11 & (X86_EFL_POPF_BITS | X86_EFL_VIF | X86_EFL_VIP);
3797 pCtx->rflags.u |= X86_EFL_1;
3798 }
3799 else
3800 {
3801 Log(("sysret: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n", pCtx->cs, pCtx->eip, pCtx->eflags.u, uNewCs, pCtx->ecx));
3802 pCtx->rip = pCtx->rcx;
3803 pCtx->rflags.u |= X86_EFL_IF;
3804 pCtx->cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
3805 | (3 << X86DESCATTR_DPL_SHIFT);
3806 }
3807 pCtx->cs.Sel = uNewCs | 3;
3808 pCtx->cs.ValidSel = uNewCs | 3;
3809 pCtx->cs.u64Base = 0;
3810 pCtx->cs.u32Limit = UINT32_MAX;
3811 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
3812
3813 pCtx->ss.Sel = uNewSs | 3;
3814 pCtx->ss.ValidSel = uNewSs | 3;
3815 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
3816 /* The SS hidden bits remains unchanged says AMD. To that I say "Yeah, right!". */
3817 pCtx->ss.Attr.u |= (3 << X86DESCATTR_DPL_SHIFT);
3818 /** @todo Testcase: verify that SS.u1Long and SS.u1DefBig are left unchanged
3819 * on sysret. */
3820
3821 return VINF_SUCCESS;
3822}
3823
3824
3825/**
3826 * Common worker for 'pop SReg', 'mov SReg, GReg' and 'lXs GReg, reg/mem'.
3827 *
3828 * @param iSegReg The segment register number (valid).
3829 * @param uSel The new selector value.
3830 */
3831IEM_CIMPL_DEF_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel)
3832{
3833 /*PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);*/
3834 uint16_t *pSel = iemSRegRef(pIemCpu, iSegReg);
3835 PCPUMSELREGHID pHid = iemSRegGetHid(pIemCpu, iSegReg);
3836
3837 Assert(iSegReg <= X86_SREG_GS && iSegReg != X86_SREG_CS);
3838
3839 /*
3840 * Real mode and V8086 mode are easy.
3841 */
3842 if ( pIemCpu->enmCpuMode == IEMMODE_16BIT
3843 && IEM_IS_REAL_OR_V86_MODE(pIemCpu))
3844 {
3845 *pSel = uSel;
3846 pHid->u64Base = (uint32_t)uSel << 4;
3847 pHid->ValidSel = uSel;
3848 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
3849#if 0 /* AMD Volume 2, chapter 4.1 - "real mode segmentation" - states that limit and attributes are untouched. */
3850 /** @todo Does the CPU actually load limits and attributes in the
3851 * real/V8086 mode segment load case? It doesn't for CS in far
3852 * jumps... Affects unreal mode. */
3853 pHid->u32Limit = 0xffff;
3854 pHid->Attr.u = 0;
3855 pHid->Attr.n.u1Present = 1;
3856 pHid->Attr.n.u1DescType = 1;
3857 pHid->Attr.n.u4Type = iSegReg != X86_SREG_CS
3858 ? X86_SEL_TYPE_RW
3859 : X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
3860#endif
3861 CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_HIDDEN_SEL_REGS);
3862 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
3863 return VINF_SUCCESS;
3864 }
3865
3866 /*
3867 * Protected mode.
3868 *
3869 * Check if it's a null segment selector value first, that's OK for DS, ES,
3870 * FS and GS. If not null, then we have to load and parse the descriptor.
3871 */
3872 if (!(uSel & X86_SEL_MASK_OFF_RPL))
3873 {
3874 Assert(iSegReg != X86_SREG_CS); /** @todo testcase for \#UD on MOV CS, ax! */
3875 if (iSegReg == X86_SREG_SS)
3876 {
3877 /* In 64-bit kernel mode, the stack can be 0 because of the way
3878 interrupts are dispatched. AMD seems to have a slighly more
3879 relaxed relationship to SS.RPL than intel does. */
3880 /** @todo We cannot 'mov ss, 3' in 64-bit kernel mode, can we? There is a testcase (bs-cpu-xcpt-1), but double check this! */
3881 if ( pIemCpu->enmCpuMode != IEMMODE_64BIT
3882 || pIemCpu->uCpl > 2
3883 || ( uSel != pIemCpu->uCpl
3884 && !IEM_IS_GUEST_CPU_AMD(pIemCpu)) )
3885 {
3886 Log(("load sreg %#x -> invalid stack selector, #GP(0)\n", uSel));
3887 return iemRaiseGeneralProtectionFault0(pIemCpu);
3888 }
3889 }
3890
3891 *pSel = uSel; /* Not RPL, remember :-) */
3892 iemHlpLoadNullDataSelectorProt(pIemCpu, pHid, uSel);
3893 if (iSegReg == X86_SREG_SS)
3894 pHid->Attr.u |= pIemCpu->uCpl << X86DESCATTR_DPL_SHIFT;
3895
3896 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(IEMCPU_TO_VMCPU(pIemCpu), pHid));
3897 CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_HIDDEN_SEL_REGS);
3898
3899 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
3900 return VINF_SUCCESS;
3901 }
3902
3903 /* Fetch the descriptor. */
3904 IEMSELDESC Desc;
3905 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pIemCpu, &Desc, uSel, X86_XCPT_GP); /** @todo Correct exception? */
3906 if (rcStrict != VINF_SUCCESS)
3907 return rcStrict;
3908
3909 /* Check GPs first. */
3910 if (!Desc.Legacy.Gen.u1DescType)
3911 {
3912 Log(("load sreg %d (=%#x) - system selector (%#x) -> #GP\n", iSegReg, uSel, Desc.Legacy.Gen.u4Type));
3913 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
3914 }
3915 if (iSegReg == X86_SREG_SS) /* SS gets different treatment */
3916 {
3917 if ( (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
3918 || !(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
3919 {
3920 Log(("load sreg SS, %#x - code or read only (%#x) -> #GP\n", uSel, Desc.Legacy.Gen.u4Type));
3921 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
3922 }
3923 if ((uSel & X86_SEL_RPL) != pIemCpu->uCpl)
3924 {
3925 Log(("load sreg SS, %#x - RPL and CPL (%d) differs -> #GP\n", uSel, pIemCpu->uCpl));
3926 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
3927 }
3928 if (Desc.Legacy.Gen.u2Dpl != pIemCpu->uCpl)
3929 {
3930 Log(("load sreg SS, %#x - DPL (%d) and CPL (%d) differs -> #GP\n", uSel, Desc.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
3931 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
3932 }
3933 }
3934 else
3935 {
3936 if ((Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
3937 {
3938 Log(("load sreg%u, %#x - execute only segment -> #GP\n", iSegReg, uSel));
3939 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
3940 }
3941 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
3942 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
3943 {
3944#if 0 /* this is what intel says. */
3945 if ( (uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl
3946 && pIemCpu->uCpl > Desc.Legacy.Gen.u2Dpl)
3947 {
3948 Log(("load sreg%u, %#x - both RPL (%d) and CPL (%d) are greater than DPL (%d) -> #GP\n",
3949 iSegReg, uSel, (uSel & X86_SEL_RPL), pIemCpu->uCpl, Desc.Legacy.Gen.u2Dpl));
3950 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
3951 }
3952#else /* this is what makes more sense. */
3953 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
3954 {
3955 Log(("load sreg%u, %#x - RPL (%d) is greater than DPL (%d) -> #GP\n",
3956 iSegReg, uSel, (uSel & X86_SEL_RPL), Desc.Legacy.Gen.u2Dpl));
3957 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
3958 }
3959 if (pIemCpu->uCpl > Desc.Legacy.Gen.u2Dpl)
3960 {
3961 Log(("load sreg%u, %#x - CPL (%d) is greater than DPL (%d) -> #GP\n",
3962 iSegReg, uSel, pIemCpu->uCpl, Desc.Legacy.Gen.u2Dpl));
3963 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
3964 }
3965#endif
3966 }
3967 }
3968
3969 /* Is it there? */
3970 if (!Desc.Legacy.Gen.u1Present)
3971 {
3972 Log(("load sreg%d,%#x - segment not present -> #NP\n", iSegReg, uSel));
3973 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uSel);
3974 }
3975
3976 /* The base and limit. */
3977 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
3978 uint64_t u64Base;
3979 if ( pIemCpu->enmCpuMode == IEMMODE_64BIT
3980 && iSegReg < X86_SREG_FS)
3981 u64Base = 0;
3982 else
3983 u64Base = X86DESC_BASE(&Desc.Legacy);
3984
3985 /*
3986 * Ok, everything checked out fine. Now set the accessed bit before
3987 * committing the result into the registers.
3988 */
3989 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3990 {
3991 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uSel);
3992 if (rcStrict != VINF_SUCCESS)
3993 return rcStrict;
3994 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3995 }
3996
3997 /* commit */
3998 *pSel = uSel;
3999 pHid->Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
4000 pHid->u32Limit = cbLimit;
4001 pHid->u64Base = u64Base;
4002 pHid->ValidSel = uSel;
4003 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
4004
4005 /** @todo check if the hidden bits are loaded correctly for 64-bit
4006 * mode. */
4007 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(IEMCPU_TO_VMCPU(pIemCpu), pHid));
4008
4009 CPUMSetChangedFlags(IEMCPU_TO_VMCPU(pIemCpu), CPUM_CHANGED_HIDDEN_SEL_REGS);
4010 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
4011 return VINF_SUCCESS;
4012}
4013
4014
4015/**
4016 * Implements 'mov SReg, r/m'.
4017 *
4018 * @param iSegReg The segment register number (valid).
4019 * @param uSel The new selector value.
4020 */
4021IEM_CIMPL_DEF_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel)
4022{
4023 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4024 if (rcStrict == VINF_SUCCESS)
4025 {
4026 if (iSegReg == X86_SREG_SS)
4027 {
4028 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4029 EMSetInhibitInterruptsPC(IEMCPU_TO_VMCPU(pIemCpu), pCtx->rip);
4030 }
4031 }
4032 return rcStrict;
4033}
4034
4035
4036/**
4037 * Implements 'pop SReg'.
4038 *
4039 * @param iSegReg The segment register number (valid).
4040 * @param enmEffOpSize The efficient operand size (valid).
4041 */
4042IEM_CIMPL_DEF_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize)
4043{
4044 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4045 VBOXSTRICTRC rcStrict;
4046
4047 /*
4048 * Read the selector off the stack and join paths with mov ss, reg.
4049 */
4050 RTUINT64U TmpRsp;
4051 TmpRsp.u = pCtx->rsp;
4052 switch (enmEffOpSize)
4053 {
4054 case IEMMODE_16BIT:
4055 {
4056 uint16_t uSel;
4057 rcStrict = iemMemStackPopU16Ex(pIemCpu, &uSel, &TmpRsp);
4058 if (rcStrict == VINF_SUCCESS)
4059 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4060 break;
4061 }
4062
4063 case IEMMODE_32BIT:
4064 {
4065 uint32_t u32Value;
4066 rcStrict = iemMemStackPopU32Ex(pIemCpu, &u32Value, &TmpRsp);
4067 if (rcStrict == VINF_SUCCESS)
4068 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u32Value);
4069 break;
4070 }
4071
4072 case IEMMODE_64BIT:
4073 {
4074 uint64_t u64Value;
4075 rcStrict = iemMemStackPopU64Ex(pIemCpu, &u64Value, &TmpRsp);
4076 if (rcStrict == VINF_SUCCESS)
4077 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u64Value);
4078 break;
4079 }
4080 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4081 }
4082
4083 /*
4084 * Commit the stack on success.
4085 */
4086 if (rcStrict == VINF_SUCCESS)
4087 {
4088 pCtx->rsp = TmpRsp.u;
4089 if (iSegReg == X86_SREG_SS)
4090 EMSetInhibitInterruptsPC(IEMCPU_TO_VMCPU(pIemCpu), pCtx->rip);
4091 }
4092 return rcStrict;
4093}
4094
4095
4096/**
4097 * Implements lgs, lfs, les, lds & lss.
4098 */
4099IEM_CIMPL_DEF_5(iemCImpl_load_SReg_Greg,
4100 uint16_t, uSel,
4101 uint64_t, offSeg,
4102 uint8_t, iSegReg,
4103 uint8_t, iGReg,
4104 IEMMODE, enmEffOpSize)
4105{
4106 /*PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);*/
4107 VBOXSTRICTRC rcStrict;
4108
4109 /*
4110 * Use iemCImpl_LoadSReg to do the tricky segment register loading.
4111 */
4112 /** @todo verify and test that mov, pop and lXs works the segment
4113 * register loading in the exact same way. */
4114 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4115 if (rcStrict == VINF_SUCCESS)
4116 {
4117 switch (enmEffOpSize)
4118 {
4119 case IEMMODE_16BIT:
4120 *(uint16_t *)iemGRegRef(pIemCpu, iGReg) = offSeg;
4121 break;
4122 case IEMMODE_32BIT:
4123 *(uint64_t *)iemGRegRef(pIemCpu, iGReg) = offSeg;
4124 break;
4125 case IEMMODE_64BIT:
4126 *(uint64_t *)iemGRegRef(pIemCpu, iGReg) = offSeg;
4127 break;
4128 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4129 }
4130 }
4131
4132 return rcStrict;
4133}
4134
4135
4136/**
4137 * Helper for VERR, VERW, LAR, and LSL and loads the descriptor into memory.
4138 *
4139 * @retval VINF_SUCCESS on success.
4140 * @retval VINF_IEM_SELECTOR_NOT_OK if the selector isn't ok.
4141 * @retval iemMemFetchSysU64 return value.
4142 *
4143 * @param pIemCpu The IEM state of the calling EMT.
4144 * @param uSel The selector value.
4145 * @param fAllowSysDesc Whether system descriptors are OK or not.
4146 * @param pDesc Where to return the descriptor on success.
4147 */
4148static VBOXSTRICTRC iemCImpl_LoadDescHelper(PIEMCPU pIemCpu, uint16_t uSel, bool fAllowSysDesc, PIEMSELDESC pDesc)
4149{
4150 pDesc->Long.au64[0] = 0;
4151 pDesc->Long.au64[1] = 0;
4152
4153 if (!(uSel & X86_SEL_MASK_OFF_RPL)) /** @todo test this on 64-bit. */
4154 return VINF_IEM_SELECTOR_NOT_OK;
4155
4156 /* Within the table limits? */
4157 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4158 RTGCPTR GCPtrBase;
4159 if (uSel & X86_SEL_LDT)
4160 {
4161 if ( !pCtx->ldtr.Attr.n.u1Present
4162 || (uSel | X86_SEL_RPL_LDT) > pCtx->ldtr.u32Limit )
4163 return VINF_IEM_SELECTOR_NOT_OK;
4164 GCPtrBase = pCtx->ldtr.u64Base;
4165 }
4166 else
4167 {
4168 if ((uSel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
4169 return VINF_IEM_SELECTOR_NOT_OK;
4170 GCPtrBase = pCtx->gdtr.pGdt;
4171 }
4172
4173 /* Fetch the descriptor. */
4174 VBOXSTRICTRC rcStrict = iemMemFetchSysU64(pIemCpu, &pDesc->Legacy.u, UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK));
4175 if (rcStrict != VINF_SUCCESS)
4176 return rcStrict;
4177 if (!pDesc->Legacy.Gen.u1DescType)
4178 {
4179 if (!fAllowSysDesc)
4180 return VINF_IEM_SELECTOR_NOT_OK;
4181 if (CPUMIsGuestInLongModeEx(pCtx))
4182 {
4183 rcStrict = iemMemFetchSysU64(pIemCpu, &pDesc->Long.au64[1], UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK) + 8);
4184 if (rcStrict != VINF_SUCCESS)
4185 return rcStrict;
4186 }
4187
4188 }
4189
4190 return VINF_SUCCESS;
4191}
4192
4193
4194/**
4195 * Implements verr (fWrite = false) and verw (fWrite = true).
4196 */
4197IEM_CIMPL_DEF_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite)
4198{
4199 Assert(!IEM_IS_REAL_OR_V86_MODE(pIemCpu));
4200
4201 /** @todo figure whether the accessed bit is set or not. */
4202
4203 bool fAccessible = true;
4204 IEMSELDESC Desc;
4205 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pIemCpu, uSel, false /*fAllowSysDesc*/, &Desc);
4206 if (rcStrict == VINF_SUCCESS)
4207 {
4208 /* Check the descriptor, order doesn't matter much here. */
4209 if ( !Desc.Legacy.Gen.u1DescType
4210 || !Desc.Legacy.Gen.u1Present)
4211 fAccessible = false;
4212 else
4213 {
4214 if ( fWrite
4215 ? (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE
4216 : (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
4217 fAccessible = false;
4218
4219 /** @todo testcase for the conforming behavior. */
4220 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4221 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4222 {
4223 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4224 fAccessible = false;
4225 else if (pIemCpu->uCpl > Desc.Legacy.Gen.u2Dpl)
4226 fAccessible = false;
4227 }
4228 }
4229
4230 }
4231 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
4232 fAccessible = false;
4233 else
4234 return rcStrict;
4235
4236 /* commit */
4237 pIemCpu->CTX_SUFF(pCtx)->eflags.Bits.u1ZF = fAccessible;
4238
4239 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
4240 return VINF_SUCCESS;
4241}
4242
4243
4244/**
4245 * Implements LAR and LSL with 64-bit operand size.
4246 *
4247 * @returns VINF_SUCCESS.
4248 * @param pu16Dst Pointer to the destination register.
4249 * @param uSel The selector to load details for.
4250 * @param pEFlags Pointer to the eflags register.
4251 * @param fIsLar true = LAR, false = LSL.
4252 */
4253IEM_CIMPL_DEF_4(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, uint32_t *, pEFlags, bool, fIsLar)
4254{
4255 Assert(!IEM_IS_REAL_OR_V86_MODE(pIemCpu));
4256
4257 /** @todo figure whether the accessed bit is set or not. */
4258
4259 bool fDescOk = true;
4260 IEMSELDESC Desc;
4261 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pIemCpu, uSel, false /*fAllowSysDesc*/, &Desc);
4262 if (rcStrict == VINF_SUCCESS)
4263 {
4264 /*
4265 * Check the descriptor type.
4266 */
4267 if (!Desc.Legacy.Gen.u1DescType)
4268 {
4269 if (CPUMIsGuestInLongModeEx(pIemCpu->CTX_SUFF(pCtx)))
4270 {
4271 if (Desc.Long.Gen.u5Zeros)
4272 fDescOk = false;
4273 else
4274 switch (Desc.Long.Gen.u4Type)
4275 {
4276 /** @todo Intel lists 0 as valid for LSL, verify whether that's correct */
4277 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
4278 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
4279 case AMD64_SEL_TYPE_SYS_LDT: /** @todo Intel lists this as invalid for LAR, AMD and 32-bit does otherwise. */
4280 break;
4281 case AMD64_SEL_TYPE_SYS_CALL_GATE:
4282 fDescOk = fIsLar;
4283 break;
4284 default:
4285 fDescOk = false;
4286 break;
4287 }
4288 }
4289 else
4290 {
4291 switch (Desc.Long.Gen.u4Type)
4292 {
4293 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
4294 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
4295 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
4296 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
4297 case X86_SEL_TYPE_SYS_LDT:
4298 break;
4299 case X86_SEL_TYPE_SYS_286_CALL_GATE:
4300 case X86_SEL_TYPE_SYS_TASK_GATE:
4301 case X86_SEL_TYPE_SYS_386_CALL_GATE:
4302 fDescOk = fIsLar;
4303 break;
4304 default:
4305 fDescOk = false;
4306 break;
4307 }
4308 }
4309 }
4310 if (fDescOk)
4311 {
4312 /*
4313 * Check the RPL/DPL/CPL interaction..
4314 */
4315 /** @todo testcase for the conforming behavior. */
4316 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)
4317 || !Desc.Legacy.Gen.u1DescType)
4318 {
4319 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4320 fDescOk = false;
4321 else if (pIemCpu->uCpl > Desc.Legacy.Gen.u2Dpl)
4322 fDescOk = false;
4323 }
4324 }
4325
4326 if (fDescOk)
4327 {
4328 /*
4329 * All fine, start committing the result.
4330 */
4331 if (fIsLar)
4332 *pu64Dst = Desc.Legacy.au32[1] & UINT32_C(0x00ffff00);
4333 else
4334 *pu64Dst = X86DESC_LIMIT_G(&Desc.Legacy);
4335 }
4336
4337 }
4338 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
4339 fDescOk = false;
4340 else
4341 return rcStrict;
4342
4343 /* commit flags value and advance rip. */
4344 pIemCpu->CTX_SUFF(pCtx)->eflags.Bits.u1ZF = fDescOk;
4345 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
4346
4347 return VINF_SUCCESS;
4348}
4349
4350
4351/**
4352 * Implements LAR and LSL with 16-bit operand size.
4353 *
4354 * @returns VINF_SUCCESS.
4355 * @param pu16Dst Pointer to the destination register.
4356 * @param u16Sel The selector to load details for.
4357 * @param pEFlags Pointer to the eflags register.
4358 * @param fIsLar true = LAR, false = LSL.
4359 */
4360IEM_CIMPL_DEF_4(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, uint32_t *, pEFlags, bool, fIsLar)
4361{
4362 uint64_t u64TmpDst = *pu16Dst;
4363 IEM_CIMPL_CALL_4(iemCImpl_LarLsl_u64, &u64TmpDst, uSel, pEFlags, fIsLar);
4364 *pu16Dst = (uint16_t)u64TmpDst;
4365 return VINF_SUCCESS;
4366}
4367
4368
4369/**
4370 * Implements lgdt.
4371 *
4372 * @param iEffSeg The segment of the new gdtr contents
4373 * @param GCPtrEffSrc The address of the new gdtr contents.
4374 * @param enmEffOpSize The effective operand size.
4375 */
4376IEM_CIMPL_DEF_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
4377{
4378 if (pIemCpu->uCpl != 0)
4379 return iemRaiseGeneralProtectionFault0(pIemCpu);
4380 Assert(!pIemCpu->CTX_SUFF(pCtx)->eflags.Bits.u1VM);
4381
4382 /*
4383 * Fetch the limit and base address.
4384 */
4385 uint16_t cbLimit;
4386 RTGCPTR GCPtrBase;
4387 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pIemCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
4388 if (rcStrict == VINF_SUCCESS)
4389 {
4390 if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
4391 rcStrict = CPUMSetGuestGDTR(IEMCPU_TO_VMCPU(pIemCpu), GCPtrBase, cbLimit);
4392 else
4393 {
4394 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4395 pCtx->gdtr.cbGdt = cbLimit;
4396 pCtx->gdtr.pGdt = GCPtrBase;
4397 }
4398 if (rcStrict == VINF_SUCCESS)
4399 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
4400 }
4401 return rcStrict;
4402}
4403
4404
4405/**
4406 * Implements sgdt.
4407 *
4408 * @param iEffSeg The segment where to store the gdtr content.
4409 * @param GCPtrEffDst The address where to store the gdtr content.
4410 * @param enmEffOpSize The effective operand size.
4411 */
4412IEM_CIMPL_DEF_3(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, IEMMODE, enmEffOpSize)
4413{
4414 /*
4415 * Join paths with sidt.
4416 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
4417 * you really must know.
4418 */
4419 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4420 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pIemCpu, pCtx->gdtr.cbGdt, pCtx->gdtr.pGdt, iEffSeg, GCPtrEffDst, enmEffOpSize);
4421 if (rcStrict == VINF_SUCCESS)
4422 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
4423 return rcStrict;
4424}
4425
4426
4427/**
4428 * Implements lidt.
4429 *
4430 * @param iEffSeg The segment of the new idtr contents
4431 * @param GCPtrEffSrc The address of the new idtr contents.
4432 * @param enmEffOpSize The effective operand size.
4433 */
4434IEM_CIMPL_DEF_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
4435{
4436 if (pIemCpu->uCpl != 0)
4437 return iemRaiseGeneralProtectionFault0(pIemCpu);
4438 Assert(!pIemCpu->CTX_SUFF(pCtx)->eflags.Bits.u1VM);
4439
4440 /*
4441 * Fetch the limit and base address.
4442 */
4443 uint16_t cbLimit;
4444 RTGCPTR GCPtrBase;
4445 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pIemCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
4446 if (rcStrict == VINF_SUCCESS)
4447 {
4448 if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
4449 CPUMSetGuestIDTR(IEMCPU_TO_VMCPU(pIemCpu), GCPtrBase, cbLimit);
4450 else
4451 {
4452 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4453 pCtx->idtr.cbIdt = cbLimit;
4454 pCtx->idtr.pIdt = GCPtrBase;
4455 }
4456 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
4457 }
4458 return rcStrict;
4459}
4460
4461
4462/**
4463 * Implements sidt.
4464 *
4465 * @param iEffSeg The segment where to store the idtr content.
4466 * @param GCPtrEffDst The address where to store the idtr content.
4467 * @param enmEffOpSize The effective operand size.
4468 */
4469IEM_CIMPL_DEF_3(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, IEMMODE, enmEffOpSize)
4470{
4471 /*
4472 * Join paths with sgdt.
4473 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
4474 * you really must know.
4475 */
4476 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4477 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pIemCpu, pCtx->idtr.cbIdt, pCtx->idtr.pIdt, iEffSeg, GCPtrEffDst, enmEffOpSize);
4478 if (rcStrict == VINF_SUCCESS)
4479 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
4480 return rcStrict;
4481}
4482
4483
4484/**
4485 * Implements lldt.
4486 *
4487 * @param uNewLdt The new LDT selector value.
4488 */
4489IEM_CIMPL_DEF_1(iemCImpl_lldt, uint16_t, uNewLdt)
4490{
4491 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4492
4493 /*
4494 * Check preconditions.
4495 */
4496 if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
4497 {
4498 Log(("lldt %04x - real or v8086 mode -> #GP(0)\n", uNewLdt));
4499 return iemRaiseUndefinedOpcode(pIemCpu);
4500 }
4501 if (pIemCpu->uCpl != 0)
4502 {
4503 Log(("lldt %04x - CPL is %d -> #GP(0)\n", uNewLdt, pIemCpu->uCpl));
4504 return iemRaiseGeneralProtectionFault0(pIemCpu);
4505 }
4506 if (uNewLdt & X86_SEL_LDT)
4507 {
4508 Log(("lldt %04x - LDT selector -> #GP\n", uNewLdt));
4509 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewLdt);
4510 }
4511
4512 /*
4513 * Now, loading a NULL selector is easy.
4514 */
4515 if (!(uNewLdt & X86_SEL_MASK_OFF_RPL))
4516 {
4517 Log(("lldt %04x: Loading NULL selector.\n", uNewLdt));
4518 if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
4519 CPUMSetGuestLDTR(IEMCPU_TO_VMCPU(pIemCpu), uNewLdt);
4520 else
4521 pCtx->ldtr.Sel = uNewLdt;
4522 pCtx->ldtr.ValidSel = uNewLdt;
4523 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
4524 if (IEM_FULL_VERIFICATION_REM_ENABLED(pIemCpu))
4525 {
4526 pCtx->ldtr.Attr.u = X86DESCATTR_UNUSABLE;
4527 pCtx->ldtr.u64Base = pCtx->ldtr.u32Limit = 0; /* For verfication against REM. */
4528 }
4529 else if (IEM_IS_GUEST_CPU_AMD(pIemCpu))
4530 {
4531 /* AMD-V seems to leave the base and limit alone. */
4532 pCtx->ldtr.Attr.u = X86DESCATTR_UNUSABLE;
4533 }
4534 else if (!IEM_FULL_VERIFICATION_REM_ENABLED(pIemCpu))
4535 {
4536 /* VT-x (Intel 3960x) seems to be doing the following. */
4537 pCtx->ldtr.Attr.u = X86DESCATTR_UNUSABLE | X86DESCATTR_G | X86DESCATTR_D;
4538 pCtx->ldtr.u64Base = 0;
4539 pCtx->ldtr.u32Limit = UINT32_MAX;
4540 }
4541
4542 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
4543 return VINF_SUCCESS;
4544 }
4545
4546 /*
4547 * Read the descriptor.
4548 */
4549 IEMSELDESC Desc;
4550 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pIemCpu, &Desc, uNewLdt, X86_XCPT_GP); /** @todo Correct exception? */
4551 if (rcStrict != VINF_SUCCESS)
4552 return rcStrict;
4553
4554 /* Check GPs first. */
4555 if (Desc.Legacy.Gen.u1DescType)
4556 {
4557 Log(("lldt %#x - not system selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
4558 return iemRaiseGeneralProtectionFault(pIemCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4559 }
4560 if (Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
4561 {
4562 Log(("lldt %#x - not LDT selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
4563 return iemRaiseGeneralProtectionFault(pIemCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4564 }
4565 uint64_t u64Base;
4566 if (!IEM_IS_LONG_MODE(pIemCpu))
4567 u64Base = X86DESC_BASE(&Desc.Legacy);
4568 else
4569 {
4570 if (Desc.Long.Gen.u5Zeros)
4571 {
4572 Log(("lldt %#x - u5Zeros=%#x -> #GP\n", uNewLdt, Desc.Long.Gen.u5Zeros));
4573 return iemRaiseGeneralProtectionFault(pIemCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4574 }
4575
4576 u64Base = X86DESC64_BASE(&Desc.Long);
4577 if (!IEM_IS_CANONICAL(u64Base))
4578 {
4579 Log(("lldt %#x - non-canonical base address %#llx -> #GP\n", uNewLdt, u64Base));
4580 return iemRaiseGeneralProtectionFault(pIemCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4581 }
4582 }
4583
4584 /* NP */
4585 if (!Desc.Legacy.Gen.u1Present)
4586 {
4587 Log(("lldt %#x - segment not present -> #NP\n", uNewLdt));
4588 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uNewLdt);
4589 }
4590
4591 /*
4592 * It checks out alright, update the registers.
4593 */
4594/** @todo check if the actual value is loaded or if the RPL is dropped */
4595 if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
4596 CPUMSetGuestLDTR(IEMCPU_TO_VMCPU(pIemCpu), uNewLdt & X86_SEL_MASK_OFF_RPL);
4597 else
4598 pCtx->ldtr.Sel = uNewLdt & X86_SEL_MASK_OFF_RPL;
4599 pCtx->ldtr.ValidSel = uNewLdt & X86_SEL_MASK_OFF_RPL;
4600 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
4601 pCtx->ldtr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
4602 pCtx->ldtr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
4603 pCtx->ldtr.u64Base = u64Base;
4604
4605 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
4606 return VINF_SUCCESS;
4607}
4608
4609
4610/**
4611 * Implements lldt.
4612 *
4613 * @param uNewLdt The new LDT selector value.
4614 */
4615IEM_CIMPL_DEF_1(iemCImpl_ltr, uint16_t, uNewTr)
4616{
4617 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4618
4619 /*
4620 * Check preconditions.
4621 */
4622 if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
4623 {
4624 Log(("ltr %04x - real or v8086 mode -> #GP(0)\n", uNewTr));
4625 return iemRaiseUndefinedOpcode(pIemCpu);
4626 }
4627 if (pIemCpu->uCpl != 0)
4628 {
4629 Log(("ltr %04x - CPL is %d -> #GP(0)\n", uNewTr, pIemCpu->uCpl));
4630 return iemRaiseGeneralProtectionFault0(pIemCpu);
4631 }
4632 if (uNewTr & X86_SEL_LDT)
4633 {
4634 Log(("ltr %04x - LDT selector -> #GP\n", uNewTr));
4635 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewTr);
4636 }
4637 if (!(uNewTr & X86_SEL_MASK_OFF_RPL))
4638 {
4639 Log(("ltr %04x - NULL selector -> #GP(0)\n", uNewTr));
4640 return iemRaiseGeneralProtectionFault0(pIemCpu);
4641 }
4642
4643 /*
4644 * Read the descriptor.
4645 */
4646 IEMSELDESC Desc;
4647 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pIemCpu, &Desc, uNewTr, X86_XCPT_GP); /** @todo Correct exception? */
4648 if (rcStrict != VINF_SUCCESS)
4649 return rcStrict;
4650
4651 /* Check GPs first. */
4652 if (Desc.Legacy.Gen.u1DescType)
4653 {
4654 Log(("ltr %#x - not system selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
4655 return iemRaiseGeneralProtectionFault(pIemCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
4656 }
4657 if ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL /* same as AMD64_SEL_TYPE_SYS_TSS_AVAIL */
4658 && ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_286_TSS_AVAIL
4659 || IEM_IS_LONG_MODE(pIemCpu)) )
4660 {
4661 Log(("ltr %#x - not an available TSS selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
4662 return iemRaiseGeneralProtectionFault(pIemCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
4663 }
4664 uint64_t u64Base;
4665 if (!IEM_IS_LONG_MODE(pIemCpu))
4666 u64Base = X86DESC_BASE(&Desc.Legacy);
4667 else
4668 {
4669 if (Desc.Long.Gen.u5Zeros)
4670 {
4671 Log(("ltr %#x - u5Zeros=%#x -> #GP\n", uNewTr, Desc.Long.Gen.u5Zeros));
4672 return iemRaiseGeneralProtectionFault(pIemCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
4673 }
4674
4675 u64Base = X86DESC64_BASE(&Desc.Long);
4676 if (!IEM_IS_CANONICAL(u64Base))
4677 {
4678 Log(("ltr %#x - non-canonical base address %#llx -> #GP\n", uNewTr, u64Base));
4679 return iemRaiseGeneralProtectionFault(pIemCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
4680 }
4681 }
4682
4683 /* NP */
4684 if (!Desc.Legacy.Gen.u1Present)
4685 {
4686 Log(("ltr %#x - segment not present -> #NP\n", uNewTr));
4687 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uNewTr);
4688 }
4689
4690 /*
4691 * Set it busy.
4692 * Note! Intel says this should lock down the whole descriptor, but we'll
4693 * restrict our selves to 32-bit for now due to lack of inline
4694 * assembly and such.
4695 */
4696 void *pvDesc;
4697 rcStrict = iemMemMap(pIemCpu, &pvDesc, 8, UINT8_MAX, pCtx->gdtr.pGdt + (uNewTr & X86_SEL_MASK_OFF_RPL), IEM_ACCESS_DATA_RW);
4698 if (rcStrict != VINF_SUCCESS)
4699 return rcStrict;
4700 switch ((uintptr_t)pvDesc & 3)
4701 {
4702 case 0: ASMAtomicBitSet(pvDesc, 40 + 1); break;
4703 case 1: ASMAtomicBitSet((uint8_t *)pvDesc + 3, 40 + 1 - 24); break;
4704 case 2: ASMAtomicBitSet((uint8_t *)pvDesc + 2, 40 + 1 - 16); break;
4705 case 3: ASMAtomicBitSet((uint8_t *)pvDesc + 1, 40 + 1 - 8); break;
4706 }
4707 rcStrict = iemMemCommitAndUnmap(pIemCpu, pvDesc, IEM_ACCESS_DATA_RW);
4708 if (rcStrict != VINF_SUCCESS)
4709 return rcStrict;
4710 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
4711
4712 /*
4713 * It checks out alright, update the registers.
4714 */
4715/** @todo check if the actual value is loaded or if the RPL is dropped */
4716 if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
4717 CPUMSetGuestTR(IEMCPU_TO_VMCPU(pIemCpu), uNewTr & X86_SEL_MASK_OFF_RPL);
4718 else
4719 pCtx->tr.Sel = uNewTr & X86_SEL_MASK_OFF_RPL;
4720 pCtx->tr.ValidSel = uNewTr & X86_SEL_MASK_OFF_RPL;
4721 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
4722 pCtx->tr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
4723 pCtx->tr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
4724 pCtx->tr.u64Base = u64Base;
4725
4726 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
4727 return VINF_SUCCESS;
4728}
4729
4730
4731/**
4732 * Implements mov GReg,CRx.
4733 *
4734 * @param iGReg The general register to store the CRx value in.
4735 * @param iCrReg The CRx register to read (valid).
4736 */
4737IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg)
4738{
4739 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4740 if (pIemCpu->uCpl != 0)
4741 return iemRaiseGeneralProtectionFault0(pIemCpu);
4742 Assert(!pCtx->eflags.Bits.u1VM);
4743
4744 /* read it */
4745 uint64_t crX;
4746 switch (iCrReg)
4747 {
4748 case 0: crX = pCtx->cr0; break;
4749 case 2: crX = pCtx->cr2; break;
4750 case 3: crX = pCtx->cr3; break;
4751 case 4: crX = pCtx->cr4; break;
4752 case 8:
4753 {
4754 uint8_t uTpr;
4755 int rc = PDMApicGetTPR(IEMCPU_TO_VMCPU(pIemCpu), &uTpr, NULL, NULL);
4756 if (RT_SUCCESS(rc))
4757 crX = uTpr >> 4;
4758 else
4759 crX = 0;
4760 break;
4761 }
4762 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
4763 }
4764
4765 /* store it */
4766 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
4767 *(uint64_t *)iemGRegRef(pIemCpu, iGReg) = crX;
4768 else
4769 *(uint64_t *)iemGRegRef(pIemCpu, iGReg) = (uint32_t)crX;
4770
4771 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
4772 return VINF_SUCCESS;
4773}
4774
4775
4776/**
4777 * Used to implemented 'mov CRx,GReg' and 'lmsw r/m16'.
4778 *
4779 * @param iCrReg The CRx register to write (valid).
4780 * @param uNewCrX The new value.
4781 */
4782IEM_CIMPL_DEF_2(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX)
4783{
4784 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
4785 PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu);
4786 VBOXSTRICTRC rcStrict;
4787 int rc;
4788
4789 /*
4790 * Try store it.
4791 * Unfortunately, CPUM only does a tiny bit of the work.
4792 */
4793 switch (iCrReg)
4794 {
4795 case 0:
4796 {
4797 /*
4798 * Perform checks.
4799 */
4800 uint64_t const uOldCrX = pCtx->cr0;
4801 uNewCrX |= X86_CR0_ET; /* hardcoded */
4802
4803 /* Check for reserved bits. */
4804 uint32_t const fValid = X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS
4805 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM
4806 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG;
4807 if (uNewCrX & ~(uint64_t)fValid)
4808 {
4809 Log(("Trying to set reserved CR0 bits: NewCR0=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
4810 return iemRaiseGeneralProtectionFault0(pIemCpu);
4811 }
4812
4813 /* Check for invalid combinations. */
4814 if ( (uNewCrX & X86_CR0_PG)
4815 && !(uNewCrX & X86_CR0_PE) )
4816 {
4817 Log(("Trying to set CR0.PG without CR0.PE\n"));
4818 return iemRaiseGeneralProtectionFault0(pIemCpu);
4819 }
4820
4821 if ( !(uNewCrX & X86_CR0_CD)
4822 && (uNewCrX & X86_CR0_NW) )
4823 {
4824 Log(("Trying to clear CR0.CD while leaving CR0.NW set\n"));
4825 return iemRaiseGeneralProtectionFault0(pIemCpu);
4826 }
4827
4828 /* Long mode consistency checks. */
4829 if ( (uNewCrX & X86_CR0_PG)
4830 && !(uOldCrX & X86_CR0_PG)
4831 && (pCtx->msrEFER & MSR_K6_EFER_LME) )
4832 {
4833 if (!(pCtx->cr4 & X86_CR4_PAE))
4834 {
4835 Log(("Trying to enabled long mode paging without CR4.PAE set\n"));
4836 return iemRaiseGeneralProtectionFault0(pIemCpu);
4837 }
4838 if (pCtx->cs.Attr.n.u1Long)
4839 {
4840 Log(("Trying to enabled long mode paging with a long CS descriptor loaded.\n"));
4841 return iemRaiseGeneralProtectionFault0(pIemCpu);
4842 }
4843 }
4844
4845 /** @todo check reserved PDPTR bits as AMD states. */
4846
4847 /*
4848 * Change CR0.
4849 */
4850 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
4851 CPUMSetGuestCR0(pVCpu, uNewCrX);
4852 else
4853 pCtx->cr0 = uNewCrX;
4854 Assert(pCtx->cr0 == uNewCrX);
4855
4856 /*
4857 * Change EFER.LMA if entering or leaving long mode.
4858 */
4859 if ( (uNewCrX & X86_CR0_PG) != (uOldCrX & X86_CR0_PG)
4860 && (pCtx->msrEFER & MSR_K6_EFER_LME) )
4861 {
4862 uint64_t NewEFER = pCtx->msrEFER;
4863 if (uNewCrX & X86_CR0_PG)
4864 NewEFER |= MSR_K6_EFER_LMA;
4865 else
4866 NewEFER &= ~MSR_K6_EFER_LMA;
4867
4868 if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
4869 CPUMSetGuestEFER(pVCpu, NewEFER);
4870 else
4871 pCtx->msrEFER = NewEFER;
4872 Assert(pCtx->msrEFER == NewEFER);
4873 }
4874
4875 /*
4876 * Inform PGM.
4877 */
4878 if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
4879 {
4880 if ( (uNewCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
4881 != (uOldCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) )
4882 {
4883 rc = PGMFlushTLB(pVCpu, pCtx->cr3, true /* global */);
4884 AssertRCReturn(rc, rc);
4885 /* ignore informational status codes */
4886 }
4887 rcStrict = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
4888 }
4889 else
4890 rcStrict = VINF_SUCCESS;
4891
4892#ifdef IN_RC
4893 /* Return to ring-3 for rescheduling if WP or AM changes. */
4894 if ( rcStrict == VINF_SUCCESS
4895 && ( (uNewCrX & (X86_CR0_WP | X86_CR0_AM))
4896 != (uOldCrX & (X86_CR0_WP | X86_CR0_AM))) )
4897 rcStrict = VINF_EM_RESCHEDULE;
4898#endif
4899 break;
4900 }
4901
4902 /*
4903 * CR2 can be changed without any restrictions.
4904 */
4905 case 2:
4906 pCtx->cr2 = uNewCrX;
4907 rcStrict = VINF_SUCCESS;
4908 break;
4909
4910 /*
4911 * CR3 is relatively simple, although AMD and Intel have different
4912 * accounts of how setting reserved bits are handled. We take intel's
4913 * word for the lower bits and AMD's for the high bits (63:52). The
4914 * lower reserved bits are ignored and left alone; OpenBSD 5.8 relies
4915 * on this.
4916 */
4917 /** @todo Testcase: Setting reserved bits in CR3, especially before
4918 * enabling paging. */
4919 case 3:
4920 {
4921 /* check / mask the value. */
4922 if (uNewCrX & UINT64_C(0xfff0000000000000))
4923 {
4924 Log(("Trying to load CR3 with invalid high bits set: %#llx\n", uNewCrX));
4925 return iemRaiseGeneralProtectionFault0(pIemCpu);
4926 }
4927
4928 uint64_t fValid;
4929 if ( (pCtx->cr4 & X86_CR4_PAE)
4930 && (pCtx->msrEFER & MSR_K6_EFER_LME))
4931 fValid = UINT64_C(0x000fffffffffffff);
4932 else
4933 fValid = UINT64_C(0xffffffff);
4934 if (uNewCrX & ~fValid)
4935 {
4936 Log(("Automatically clearing reserved MBZ bits in CR3 load: NewCR3=%#llx ClearedBits=%#llx\n",
4937 uNewCrX, uNewCrX & ~fValid));
4938 uNewCrX &= fValid;
4939 }
4940
4941 /** @todo If we're in PAE mode we should check the PDPTRs for
4942 * invalid bits. */
4943
4944 /* Make the change. */
4945 if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
4946 {
4947 rc = CPUMSetGuestCR3(pVCpu, uNewCrX);
4948 AssertRCSuccessReturn(rc, rc);
4949 }
4950 else
4951 pCtx->cr3 = uNewCrX;
4952
4953 /* Inform PGM. */
4954 if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
4955 {
4956 if (pCtx->cr0 & X86_CR0_PG)
4957 {
4958 rc = PGMFlushTLB(pVCpu, pCtx->cr3, !(pCtx->cr4 & X86_CR4_PGE));
4959 AssertRCReturn(rc, rc);
4960 /* ignore informational status codes */
4961 }
4962 }
4963 rcStrict = VINF_SUCCESS;
4964 break;
4965 }
4966
4967 /*
4968 * CR4 is a bit more tedious as there are bits which cannot be cleared
4969 * under some circumstances and such.
4970 */
4971 case 4:
4972 {
4973 uint64_t const uOldCrX = pCtx->cr4;
4974
4975 /** @todo Shouldn't this look at the guest CPUID bits to determine
4976 * valid bits? e.g. if guest CPUID doesn't allow X86_CR4_OSXMMEEXCPT, we
4977 * should #GP(0). */
4978 /* reserved bits */
4979 uint32_t fValid = X86_CR4_VME | X86_CR4_PVI
4980 | X86_CR4_TSD | X86_CR4_DE
4981 | X86_CR4_PSE | X86_CR4_PAE
4982 | X86_CR4_MCE | X86_CR4_PGE
4983 | X86_CR4_PCE | X86_CR4_OSFXSR
4984 | X86_CR4_OSXMMEEXCPT;
4985 //if (xxx)
4986 // fValid |= X86_CR4_VMXE;
4987 if (IEM_GET_GUEST_CPU_FEATURES(pIemCpu)->fXSaveRstor)
4988 fValid |= X86_CR4_OSXSAVE;
4989 if (uNewCrX & ~(uint64_t)fValid)
4990 {
4991 Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
4992 return iemRaiseGeneralProtectionFault0(pIemCpu);
4993 }
4994
4995 /* long mode checks. */
4996 if ( (uOldCrX & X86_CR4_PAE)
4997 && !(uNewCrX & X86_CR4_PAE)
4998 && CPUMIsGuestInLongModeEx(pCtx) )
4999 {
5000 Log(("Trying to set clear CR4.PAE while long mode is active\n"));
5001 return iemRaiseGeneralProtectionFault0(pIemCpu);
5002 }
5003
5004
5005 /*
5006 * Change it.
5007 */
5008 if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
5009 {
5010 rc = CPUMSetGuestCR4(pVCpu, uNewCrX);
5011 AssertRCSuccessReturn(rc, rc);
5012 }
5013 else
5014 pCtx->cr4 = uNewCrX;
5015 Assert(pCtx->cr4 == uNewCrX);
5016
5017 /*
5018 * Notify SELM and PGM.
5019 */
5020 if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
5021 {
5022 /* SELM - VME may change things wrt to the TSS shadowing. */
5023 if ((uNewCrX ^ uOldCrX) & X86_CR4_VME)
5024 {
5025 Log(("iemCImpl_load_CrX: VME %d -> %d => Setting VMCPU_FF_SELM_SYNC_TSS\n",
5026 RT_BOOL(uOldCrX & X86_CR4_VME), RT_BOOL(uNewCrX & X86_CR4_VME) ));
5027#ifdef VBOX_WITH_RAW_MODE
5028 if (!HMIsEnabled(IEMCPU_TO_VM(pIemCpu)))
5029 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
5030#endif
5031 }
5032
5033 /* PGM - flushing and mode. */
5034 if ((uNewCrX ^ uOldCrX) & (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE))
5035 {
5036 rc = PGMFlushTLB(pVCpu, pCtx->cr3, true /* global */);
5037 AssertRCReturn(rc, rc);
5038 /* ignore informational status codes */
5039 }
5040 rcStrict = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
5041 }
5042 else
5043 rcStrict = VINF_SUCCESS;
5044 break;
5045 }
5046
5047 /*
5048 * CR8 maps to the APIC TPR.
5049 */
5050 case 8:
5051 if (uNewCrX & ~(uint64_t)0xf)
5052 {
5053 Log(("Trying to set reserved CR8 bits (%#RX64)\n", uNewCrX));
5054 return iemRaiseGeneralProtectionFault0(pIemCpu);
5055 }
5056
5057 if (!IEM_FULL_VERIFICATION_ENABLED(pIemCpu))
5058 PDMApicSetTPR(IEMCPU_TO_VMCPU(pIemCpu), (uint8_t)uNewCrX << 4);
5059 rcStrict = VINF_SUCCESS;
5060 break;
5061
5062 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5063 }
5064
5065 /*
5066 * Advance the RIP on success.
5067 */
5068 if (RT_SUCCESS(rcStrict))
5069 {
5070 if (rcStrict != VINF_SUCCESS)
5071 rcStrict = iemSetPassUpStatus(pIemCpu, rcStrict);
5072 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5073 }
5074
5075 return rcStrict;
5076}
5077
5078
5079/**
5080 * Implements mov CRx,GReg.
5081 *
5082 * @param iCrReg The CRx register to write (valid).
5083 * @param iGReg The general register to load the DRx value from.
5084 */
5085IEM_CIMPL_DEF_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg)
5086{
5087 if (pIemCpu->uCpl != 0)
5088 return iemRaiseGeneralProtectionFault0(pIemCpu);
5089 Assert(!pIemCpu->CTX_SUFF(pCtx)->eflags.Bits.u1VM);
5090
5091 /*
5092 * Read the new value from the source register and call common worker.
5093 */
5094 uint64_t uNewCrX;
5095 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
5096 uNewCrX = iemGRegFetchU64(pIemCpu, iGReg);
5097 else
5098 uNewCrX = iemGRegFetchU32(pIemCpu, iGReg);
5099 return IEM_CIMPL_CALL_2(iemCImpl_load_CrX, iCrReg, uNewCrX);
5100}
5101
5102
5103/**
5104 * Implements 'LMSW r/m16'
5105 *
5106 * @param u16NewMsw The new value.
5107 */
5108IEM_CIMPL_DEF_1(iemCImpl_lmsw, uint16_t, u16NewMsw)
5109{
5110 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5111
5112 if (pIemCpu->uCpl != 0)
5113 return iemRaiseGeneralProtectionFault0(pIemCpu);
5114 Assert(!pCtx->eflags.Bits.u1VM);
5115
5116 /*
5117 * Compose the new CR0 value and call common worker.
5118 */
5119 uint64_t uNewCr0 = pCtx->cr0 & ~(X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
5120 uNewCr0 |= u16NewMsw & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
5121 return IEM_CIMPL_CALL_2(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0);
5122}
5123
5124
5125/**
5126 * Implements 'CLTS'.
5127 */
5128IEM_CIMPL_DEF_0(iemCImpl_clts)
5129{
5130 if (pIemCpu->uCpl != 0)
5131 return iemRaiseGeneralProtectionFault0(pIemCpu);
5132
5133 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5134 uint64_t uNewCr0 = pCtx->cr0;
5135 uNewCr0 &= ~X86_CR0_TS;
5136 return IEM_CIMPL_CALL_2(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0);
5137}
5138
5139
5140/**
5141 * Implements mov GReg,DRx.
5142 *
5143 * @param iGReg The general register to store the DRx value in.
5144 * @param iDrReg The DRx register to read (0-7).
5145 */
5146IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg)
5147{
5148 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5149
5150 /*
5151 * Check preconditions.
5152 */
5153
5154 /* Raise GPs. */
5155 if (pIemCpu->uCpl != 0)
5156 return iemRaiseGeneralProtectionFault0(pIemCpu);
5157 Assert(!pCtx->eflags.Bits.u1VM);
5158
5159 if ( (iDrReg == 4 || iDrReg == 5)
5160 && (pCtx->cr4 & X86_CR4_DE) )
5161 {
5162 Log(("mov r%u,dr%u: CR4.DE=1 -> #GP(0)\n", iGReg, iDrReg));
5163 return iemRaiseGeneralProtectionFault0(pIemCpu);
5164 }
5165
5166 /* Raise #DB if general access detect is enabled. */
5167 if (pCtx->dr[7] & X86_DR7_GD)
5168 {
5169 Log(("mov r%u,dr%u: DR7.GD=1 -> #DB\n", iGReg, iDrReg));
5170 return iemRaiseDebugException(pIemCpu);
5171 }
5172
5173 /*
5174 * Read the debug register and store it in the specified general register.
5175 */
5176 uint64_t drX;
5177 switch (iDrReg)
5178 {
5179 case 0: drX = pCtx->dr[0]; break;
5180 case 1: drX = pCtx->dr[1]; break;
5181 case 2: drX = pCtx->dr[2]; break;
5182 case 3: drX = pCtx->dr[3]; break;
5183 case 6:
5184 case 4:
5185 drX = pCtx->dr[6];
5186 drX |= X86_DR6_RA1_MASK;
5187 drX &= ~X86_DR6_RAZ_MASK;
5188 break;
5189 case 7:
5190 case 5:
5191 drX = pCtx->dr[7];
5192 drX |=X86_DR7_RA1_MASK;
5193 drX &= ~X86_DR7_RAZ_MASK;
5194 break;
5195 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5196 }
5197
5198 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
5199 *(uint64_t *)iemGRegRef(pIemCpu, iGReg) = drX;
5200 else
5201 *(uint64_t *)iemGRegRef(pIemCpu, iGReg) = (uint32_t)drX;
5202
5203 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5204 return VINF_SUCCESS;
5205}
5206
5207
5208/**
5209 * Implements mov DRx,GReg.
5210 *
5211 * @param iDrReg The DRx register to write (valid).
5212 * @param iGReg The general register to load the DRx value from.
5213 */
5214IEM_CIMPL_DEF_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg)
5215{
5216 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5217
5218 /*
5219 * Check preconditions.
5220 */
5221 if (pIemCpu->uCpl != 0)
5222 return iemRaiseGeneralProtectionFault0(pIemCpu);
5223 Assert(!pCtx->eflags.Bits.u1VM);
5224
5225 if (iDrReg == 4 || iDrReg == 5)
5226 {
5227 if (pCtx->cr4 & X86_CR4_DE)
5228 {
5229 Log(("mov dr%u,r%u: CR4.DE=1 -> #GP(0)\n", iDrReg, iGReg));
5230 return iemRaiseGeneralProtectionFault0(pIemCpu);
5231 }
5232 iDrReg += 2;
5233 }
5234
5235 /* Raise #DB if general access detect is enabled. */
5236 /** @todo is \#DB/DR7.GD raised before any reserved high bits in DR7/DR6
5237 * \#GP? */
5238 if (pCtx->dr[7] & X86_DR7_GD)
5239 {
5240 Log(("mov dr%u,r%u: DR7.GD=1 -> #DB\n", iDrReg, iGReg));
5241 return iemRaiseDebugException(pIemCpu);
5242 }
5243
5244 /*
5245 * Read the new value from the source register.
5246 */
5247 uint64_t uNewDrX;
5248 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
5249 uNewDrX = iemGRegFetchU64(pIemCpu, iGReg);
5250 else
5251 uNewDrX = iemGRegFetchU32(pIemCpu, iGReg);
5252
5253 /*
5254 * Adjust it.
5255 */
5256 switch (iDrReg)
5257 {
5258 case 0:
5259 case 1:
5260 case 2:
5261 case 3:
5262 /* nothing to adjust */
5263 break;
5264
5265 case 6:
5266 if (uNewDrX & X86_DR6_MBZ_MASK)
5267 {
5268 Log(("mov dr%u,%#llx: DR6 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
5269 return iemRaiseGeneralProtectionFault0(pIemCpu);
5270 }
5271 uNewDrX |= X86_DR6_RA1_MASK;
5272 uNewDrX &= ~X86_DR6_RAZ_MASK;
5273 break;
5274
5275 case 7:
5276 if (uNewDrX & X86_DR7_MBZ_MASK)
5277 {
5278 Log(("mov dr%u,%#llx: DR7 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
5279 return iemRaiseGeneralProtectionFault0(pIemCpu);
5280 }
5281 uNewDrX |= X86_DR7_RA1_MASK;
5282 uNewDrX &= ~X86_DR7_RAZ_MASK;
5283 break;
5284
5285 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5286 }
5287
5288 /*
5289 * Do the actual setting.
5290 */
5291 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
5292 {
5293 int rc = CPUMSetGuestDRx(IEMCPU_TO_VMCPU(pIemCpu), iDrReg, uNewDrX);
5294 AssertRCSuccessReturn(rc, RT_SUCCESS_NP(rc) ? VERR_IEM_IPE_1 : rc);
5295 }
5296 else
5297 pCtx->dr[iDrReg] = uNewDrX;
5298
5299 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5300 return VINF_SUCCESS;
5301}
5302
5303
5304/**
5305 * Implements 'INVLPG m'.
5306 *
5307 * @param GCPtrPage The effective address of the page to invalidate.
5308 * @remarks Updates the RIP.
5309 */
5310IEM_CIMPL_DEF_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage)
5311{
5312 /* ring-0 only. */
5313 if (pIemCpu->uCpl != 0)
5314 return iemRaiseGeneralProtectionFault0(pIemCpu);
5315 Assert(!pIemCpu->CTX_SUFF(pCtx)->eflags.Bits.u1VM);
5316
5317 int rc = PGMInvalidatePage(IEMCPU_TO_VMCPU(pIemCpu), GCPtrPage);
5318 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5319
5320 if (rc == VINF_SUCCESS)
5321 return VINF_SUCCESS;
5322 if (rc == VINF_PGM_SYNC_CR3)
5323 return iemSetPassUpStatus(pIemCpu, rc);
5324
5325 AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR || RT_FAILURE_NP(rc), ("%Rrc\n", rc));
5326 Log(("PGMInvalidatePage(%RGv) -> %Rrc\n", GCPtrPage, rc));
5327 return rc;
5328}
5329
5330
5331/**
5332 * Implements RDTSC.
5333 */
5334IEM_CIMPL_DEF_0(iemCImpl_rdtsc)
5335{
5336 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5337
5338 /*
5339 * Check preconditions.
5340 */
5341 if (!IEM_GET_GUEST_CPU_FEATURES(pIemCpu)->fTsc)
5342 return iemRaiseUndefinedOpcode(pIemCpu);
5343
5344 if ( (pCtx->cr4 & X86_CR4_TSD)
5345 && pIemCpu->uCpl != 0)
5346 {
5347 Log(("rdtsc: CR4.TSD and CPL=%u -> #GP(0)\n", pIemCpu->uCpl));
5348 return iemRaiseGeneralProtectionFault0(pIemCpu);
5349 }
5350
5351 /*
5352 * Do the job.
5353 */
5354 uint64_t uTicks = TMCpuTickGet(IEMCPU_TO_VMCPU(pIemCpu));
5355 pCtx->rax = (uint32_t)uTicks;
5356 pCtx->rdx = uTicks >> 32;
5357#ifdef IEM_VERIFICATION_MODE_FULL
5358 pIemCpu->fIgnoreRaxRdx = true;
5359#endif
5360
5361 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5362 return VINF_SUCCESS;
5363}
5364
5365
5366/**
5367 * Implements RDMSR.
5368 */
5369IEM_CIMPL_DEF_0(iemCImpl_rdmsr)
5370{
5371 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5372
5373 /*
5374 * Check preconditions.
5375 */
5376 if (!IEM_GET_GUEST_CPU_FEATURES(pIemCpu)->fMsr)
5377 return iemRaiseUndefinedOpcode(pIemCpu);
5378 if (pIemCpu->uCpl != 0)
5379 return iemRaiseGeneralProtectionFault0(pIemCpu);
5380
5381 /*
5382 * Do the job.
5383 */
5384 RTUINT64U uValue;
5385 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(IEMCPU_TO_VMCPU(pIemCpu), pCtx->ecx, &uValue.u);
5386 if (rcStrict == VINF_SUCCESS)
5387 {
5388 pCtx->rax = uValue.s.Lo;
5389 pCtx->rdx = uValue.s.Hi;
5390
5391 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5392 return VINF_SUCCESS;
5393 }
5394
5395#ifndef IN_RING3
5396 /* Deferred to ring-3. */
5397 if (rcStrict == VINF_CPUM_R3_MSR_READ)
5398 {
5399 Log(("IEM: rdmsr(%#x) -> ring-3\n", pCtx->ecx));
5400 return rcStrict;
5401 }
5402#else /* IN_RING3 */
5403 /* Often a unimplemented MSR or MSR bit, so worth logging. */
5404 static uint32_t s_cTimes = 0;
5405 if (s_cTimes++ < 10)
5406 LogRel(("IEM: rdmsr(%#x) -> #GP(0)\n", pCtx->ecx));
5407 else
5408#endif
5409 Log(("IEM: rdmsr(%#x) -> #GP(0)\n", pCtx->ecx));
5410 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
5411 return iemRaiseGeneralProtectionFault0(pIemCpu);
5412}
5413
5414
5415/**
5416 * Implements WRMSR.
5417 */
5418IEM_CIMPL_DEF_0(iemCImpl_wrmsr)
5419{
5420 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5421
5422 /*
5423 * Check preconditions.
5424 */
5425 if (!IEM_GET_GUEST_CPU_FEATURES(pIemCpu)->fMsr)
5426 return iemRaiseUndefinedOpcode(pIemCpu);
5427 if (pIemCpu->uCpl != 0)
5428 return iemRaiseGeneralProtectionFault0(pIemCpu);
5429
5430 /*
5431 * Do the job.
5432 */
5433 RTUINT64U uValue;
5434 uValue.s.Lo = pCtx->eax;
5435 uValue.s.Hi = pCtx->edx;
5436
5437 VBOXSTRICTRC rcStrict;
5438 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
5439 rcStrict = CPUMSetGuestMsr(IEMCPU_TO_VMCPU(pIemCpu), pCtx->ecx, uValue.u);
5440 else
5441 {
5442#ifdef IN_RING3
5443 CPUMCTX CtxTmp = *pCtx;
5444 rcStrict = CPUMSetGuestMsr(IEMCPU_TO_VMCPU(pIemCpu), pCtx->ecx, uValue.u);
5445 PCPUMCTX pCtx2 = CPUMQueryGuestCtxPtr(IEMCPU_TO_VMCPU(pIemCpu));
5446 *pCtx = *pCtx2;
5447 *pCtx2 = CtxTmp;
5448#else
5449 AssertReleaseFailedReturn(VERR_IEM_IPE_2);
5450#endif
5451 }
5452 if (rcStrict == VINF_SUCCESS)
5453 {
5454 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5455 return VINF_SUCCESS;
5456 }
5457
5458#ifndef IN_RING3
5459 /* Deferred to ring-3. */
5460 if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
5461 {
5462 Log(("IEM: rdmsr(%#x) -> ring-3\n", pCtx->ecx));
5463 return rcStrict;
5464 }
5465#else /* IN_RING3 */
5466 /* Often a unimplemented MSR or MSR bit, so worth logging. */
5467 static uint32_t s_cTimes = 0;
5468 if (s_cTimes++ < 10)
5469 LogRel(("IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", pCtx->ecx, uValue.s.Hi, uValue.s.Lo));
5470 else
5471#endif
5472 Log(("IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", pCtx->ecx, uValue.s.Hi, uValue.s.Lo));
5473 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
5474 return iemRaiseGeneralProtectionFault0(pIemCpu);
5475}
5476
5477
5478/**
5479 * Implements 'IN eAX, port'.
5480 *
5481 * @param u16Port The source port.
5482 * @param cbReg The register size.
5483 */
5484IEM_CIMPL_DEF_2(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg)
5485{
5486 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5487
5488 /*
5489 * CPL check
5490 */
5491 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pIemCpu, pCtx, u16Port, cbReg);
5492 if (rcStrict != VINF_SUCCESS)
5493 return rcStrict;
5494
5495 /*
5496 * Perform the I/O.
5497 */
5498 uint32_t u32Value;
5499 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
5500 rcStrict = IOMIOPortRead(IEMCPU_TO_VM(pIemCpu), IEMCPU_TO_VMCPU(pIemCpu), u16Port, &u32Value, cbReg);
5501 else
5502 rcStrict = iemVerifyFakeIOPortRead(pIemCpu, u16Port, &u32Value, cbReg);
5503 if (IOM_SUCCESS(rcStrict))
5504 {
5505 switch (cbReg)
5506 {
5507 case 1: pCtx->al = (uint8_t)u32Value; break;
5508 case 2: pCtx->ax = (uint16_t)u32Value; break;
5509 case 4: pCtx->rax = u32Value; break;
5510 default: AssertFailedReturn(VERR_IEM_IPE_3);
5511 }
5512 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5513 pIemCpu->cPotentialExits++;
5514 if (rcStrict != VINF_SUCCESS)
5515 rcStrict = iemSetPassUpStatus(pIemCpu, rcStrict);
5516 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
5517
5518 /*
5519 * Check for I/O breakpoints.
5520 */
5521 uint32_t const uDr7 = pCtx->dr[7];
5522 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
5523 && X86_DR7_ANY_RW_IO(uDr7)
5524 && (pCtx->cr4 & X86_CR4_DE))
5525 || DBGFBpIsHwIoArmed(IEMCPU_TO_VM(pIemCpu))))
5526 {
5527 rcStrict = DBGFBpCheckIo(IEMCPU_TO_VM(pIemCpu), IEMCPU_TO_VMCPU(pIemCpu), pCtx, u16Port, cbReg);
5528 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
5529 rcStrict = iemRaiseDebugException(pIemCpu);
5530 }
5531 }
5532
5533 return rcStrict;
5534}
5535
5536
5537/**
5538 * Implements 'IN eAX, DX'.
5539 *
5540 * @param cbReg The register size.
5541 */
5542IEM_CIMPL_DEF_1(iemCImpl_in_eAX_DX, uint8_t, cbReg)
5543{
5544 return IEM_CIMPL_CALL_2(iemCImpl_in, pIemCpu->CTX_SUFF(pCtx)->dx, cbReg);
5545}
5546
5547
5548/**
5549 * Implements 'OUT port, eAX'.
5550 *
5551 * @param u16Port The destination port.
5552 * @param cbReg The register size.
5553 */
5554IEM_CIMPL_DEF_2(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg)
5555{
5556 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5557
5558 /*
5559 * CPL check
5560 */
5561 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pIemCpu, pCtx, u16Port, cbReg);
5562 if (rcStrict != VINF_SUCCESS)
5563 return rcStrict;
5564
5565 /*
5566 * Perform the I/O.
5567 */
5568 uint32_t u32Value;
5569 switch (cbReg)
5570 {
5571 case 1: u32Value = pCtx->al; break;
5572 case 2: u32Value = pCtx->ax; break;
5573 case 4: u32Value = pCtx->eax; break;
5574 default: AssertFailedReturn(VERR_IEM_IPE_4);
5575 }
5576 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
5577 rcStrict = IOMIOPortWrite(IEMCPU_TO_VM(pIemCpu), IEMCPU_TO_VMCPU(pIemCpu), u16Port, u32Value, cbReg);
5578 else
5579 rcStrict = iemVerifyFakeIOPortWrite(pIemCpu, u16Port, u32Value, cbReg);
5580 if (IOM_SUCCESS(rcStrict))
5581 {
5582 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5583 pIemCpu->cPotentialExits++;
5584 if (rcStrict != VINF_SUCCESS)
5585 rcStrict = iemSetPassUpStatus(pIemCpu, rcStrict);
5586 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
5587
5588 /*
5589 * Check for I/O breakpoints.
5590 */
5591 uint32_t const uDr7 = pCtx->dr[7];
5592 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
5593 && X86_DR7_ANY_RW_IO(uDr7)
5594 && (pCtx->cr4 & X86_CR4_DE))
5595 || DBGFBpIsHwIoArmed(IEMCPU_TO_VM(pIemCpu))))
5596 {
5597 rcStrict = DBGFBpCheckIo(IEMCPU_TO_VM(pIemCpu), IEMCPU_TO_VMCPU(pIemCpu), pCtx, u16Port, cbReg);
5598 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
5599 rcStrict = iemRaiseDebugException(pIemCpu);
5600 }
5601 }
5602 return rcStrict;
5603}
5604
5605
5606/**
5607 * Implements 'OUT DX, eAX'.
5608 *
5609 * @param cbReg The register size.
5610 */
5611IEM_CIMPL_DEF_1(iemCImpl_out_DX_eAX, uint8_t, cbReg)
5612{
5613 return IEM_CIMPL_CALL_2(iemCImpl_out, pIemCpu->CTX_SUFF(pCtx)->dx, cbReg);
5614}
5615
5616
5617/**
5618 * Implements 'CLI'.
5619 */
5620IEM_CIMPL_DEF_0(iemCImpl_cli)
5621{
5622 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5623 uint32_t fEfl = IEMMISC_GET_EFL(pIemCpu, pCtx);
5624 uint32_t const fEflOld = fEfl;
5625 if (pCtx->cr0 & X86_CR0_PE)
5626 {
5627 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
5628 if (!(fEfl & X86_EFL_VM))
5629 {
5630 if (pIemCpu->uCpl <= uIopl)
5631 fEfl &= ~X86_EFL_IF;
5632 else if ( pIemCpu->uCpl == 3
5633 && (pCtx->cr4 & X86_CR4_PVI) )
5634 fEfl &= ~X86_EFL_VIF;
5635 else
5636 return iemRaiseGeneralProtectionFault0(pIemCpu);
5637 }
5638 /* V8086 */
5639 else if (uIopl == 3)
5640 fEfl &= ~X86_EFL_IF;
5641 else if ( uIopl < 3
5642 && (pCtx->cr4 & X86_CR4_VME) )
5643 fEfl &= ~X86_EFL_VIF;
5644 else
5645 return iemRaiseGeneralProtectionFault0(pIemCpu);
5646 }
5647 /* real mode */
5648 else
5649 fEfl &= ~X86_EFL_IF;
5650
5651 /* Commit. */
5652 IEMMISC_SET_EFL(pIemCpu, pCtx, fEfl);
5653 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5654 Log2(("CLI: %#x -> %#x\n", fEflOld, fEfl)); NOREF(fEflOld);
5655 return VINF_SUCCESS;
5656}
5657
5658
5659/**
5660 * Implements 'STI'.
5661 */
5662IEM_CIMPL_DEF_0(iemCImpl_sti)
5663{
5664 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5665 uint32_t fEfl = IEMMISC_GET_EFL(pIemCpu, pCtx);
5666 uint32_t const fEflOld = fEfl;
5667
5668 if (pCtx->cr0 & X86_CR0_PE)
5669 {
5670 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
5671 if (!(fEfl & X86_EFL_VM))
5672 {
5673 if (pIemCpu->uCpl <= uIopl)
5674 fEfl |= X86_EFL_IF;
5675 else if ( pIemCpu->uCpl == 3
5676 && (pCtx->cr4 & X86_CR4_PVI)
5677 && !(fEfl & X86_EFL_VIP) )
5678 fEfl |= X86_EFL_VIF;
5679 else
5680 return iemRaiseGeneralProtectionFault0(pIemCpu);
5681 }
5682 /* V8086 */
5683 else if (uIopl == 3)
5684 fEfl |= X86_EFL_IF;
5685 else if ( uIopl < 3
5686 && (pCtx->cr4 & X86_CR4_VME)
5687 && !(fEfl & X86_EFL_VIP) )
5688 fEfl |= X86_EFL_VIF;
5689 else
5690 return iemRaiseGeneralProtectionFault0(pIemCpu);
5691 }
5692 /* real mode */
5693 else
5694 fEfl |= X86_EFL_IF;
5695
5696 /* Commit. */
5697 IEMMISC_SET_EFL(pIemCpu, pCtx, fEfl);
5698 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5699 if ((!(fEflOld & X86_EFL_IF) && (fEfl & X86_EFL_IF)) || IEM_FULL_VERIFICATION_REM_ENABLED(pIemCpu))
5700 EMSetInhibitInterruptsPC(IEMCPU_TO_VMCPU(pIemCpu), pCtx->rip);
5701 Log2(("STI: %#x -> %#x\n", fEflOld, fEfl));
5702 return VINF_SUCCESS;
5703}
5704
5705
5706/**
5707 * Implements 'HLT'.
5708 */
5709IEM_CIMPL_DEF_0(iemCImpl_hlt)
5710{
5711 if (pIemCpu->uCpl != 0)
5712 return iemRaiseGeneralProtectionFault0(pIemCpu);
5713 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5714 return VINF_EM_HALT;
5715}
5716
5717
5718/**
5719 * Implements 'MONITOR'.
5720 */
5721IEM_CIMPL_DEF_1(iemCImpl_monitor, uint8_t, iEffSeg)
5722{
5723 /*
5724 * Permission checks.
5725 */
5726 if (pIemCpu->uCpl != 0)
5727 {
5728 Log2(("monitor: CPL != 0\n"));
5729 return iemRaiseUndefinedOpcode(pIemCpu); /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. */
5730 }
5731 if (!IEM_GET_GUEST_CPU_FEATURES(pIemCpu)->fMonitorMWait)
5732 {
5733 Log2(("monitor: Not in CPUID\n"));
5734 return iemRaiseUndefinedOpcode(pIemCpu);
5735 }
5736
5737 /*
5738 * Gather the operands and validate them.
5739 */
5740 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5741 RTGCPTR GCPtrMem = pIemCpu->enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
5742 uint32_t uEcx = pCtx->ecx;
5743 uint32_t uEdx = pCtx->edx;
5744/** @todo Test whether EAX or ECX is processed first, i.e. do we get \#PF or
5745 * \#GP first. */
5746 if (uEcx != 0)
5747 {
5748 Log2(("monitor rax=%RX64, ecx=%RX32, edx=%RX32; ECX != 0 -> #GP(0)\n", GCPtrMem, uEcx, uEdx)); NOREF(uEdx);
5749 return iemRaiseGeneralProtectionFault0(pIemCpu);
5750 }
5751
5752 VBOXSTRICTRC rcStrict = iemMemApplySegment(pIemCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrMem);
5753 if (rcStrict != VINF_SUCCESS)
5754 return rcStrict;
5755
5756 RTGCPHYS GCPhysMem;
5757 rcStrict = iemMemPageTranslateAndCheckAccess(pIemCpu, GCPtrMem, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
5758 if (rcStrict != VINF_SUCCESS)
5759 return rcStrict;
5760
5761 /*
5762 * Call EM to prepare the monitor/wait.
5763 */
5764 rcStrict = EMMonitorWaitPrepare(IEMCPU_TO_VMCPU(pIemCpu), pCtx->rax, pCtx->rcx, pCtx->rdx, GCPhysMem);
5765 Assert(rcStrict == VINF_SUCCESS);
5766
5767 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5768 return rcStrict;
5769}
5770
5771
5772/**
5773 * Implements 'MWAIT'.
5774 */
5775IEM_CIMPL_DEF_0(iemCImpl_mwait)
5776{
5777 /*
5778 * Permission checks.
5779 */
5780 if (pIemCpu->uCpl != 0)
5781 {
5782 Log2(("mwait: CPL != 0\n"));
5783 /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. (Remember to check
5784 * EFLAGS.VM then.) */
5785 return iemRaiseUndefinedOpcode(pIemCpu);
5786 }
5787 if (!IEM_GET_GUEST_CPU_FEATURES(pIemCpu)->fMonitorMWait)
5788 {
5789 Log2(("mwait: Not in CPUID\n"));
5790 return iemRaiseUndefinedOpcode(pIemCpu);
5791 }
5792
5793 /*
5794 * Gather the operands and validate them.
5795 */
5796 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5797 uint32_t uEax = pCtx->eax;
5798 uint32_t uEcx = pCtx->ecx;
5799 if (uEcx != 0)
5800 {
5801 /* Only supported extension is break on IRQ when IF=0. */
5802 if (uEcx > 1)
5803 {
5804 Log2(("mwait eax=%RX32, ecx=%RX32; ECX > 1 -> #GP(0)\n", uEax, uEcx));
5805 return iemRaiseGeneralProtectionFault0(pIemCpu);
5806 }
5807 uint32_t fMWaitFeatures = 0;
5808 uint32_t uIgnore = 0;
5809 CPUMGetGuestCpuId(IEMCPU_TO_VMCPU(pIemCpu), 5, 0, &uIgnore, &uIgnore, &fMWaitFeatures, &uIgnore);
5810 if ( (fMWaitFeatures & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
5811 != (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
5812 {
5813 Log2(("mwait eax=%RX32, ecx=%RX32; break-on-IRQ-IF=0 extension not enabled -> #GP(0)\n", uEax, uEcx));
5814 return iemRaiseGeneralProtectionFault0(pIemCpu);
5815 }
5816 }
5817
5818 /*
5819 * Call EM to prepare the monitor/wait.
5820 */
5821 VBOXSTRICTRC rcStrict = EMMonitorWaitPerform(IEMCPU_TO_VMCPU(pIemCpu), uEax, uEcx);
5822
5823 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5824 return rcStrict;
5825}
5826
5827
5828/**
5829 * Implements 'SWAPGS'.
5830 */
5831IEM_CIMPL_DEF_0(iemCImpl_swapgs)
5832{
5833 Assert(pIemCpu->enmCpuMode == IEMMODE_64BIT); /* Caller checks this. */
5834
5835 /*
5836 * Permission checks.
5837 */
5838 if (pIemCpu->uCpl != 0)
5839 {
5840 Log2(("swapgs: CPL != 0\n"));
5841 return iemRaiseUndefinedOpcode(pIemCpu);
5842 }
5843
5844 /*
5845 * Do the job.
5846 */
5847 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5848 uint64_t uOtherGsBase = pCtx->msrKERNELGSBASE;
5849 pCtx->msrKERNELGSBASE = pCtx->gs.u64Base;
5850 pCtx->gs.u64Base = uOtherGsBase;
5851
5852 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5853 return VINF_SUCCESS;
5854}
5855
5856
5857/**
5858 * Implements 'CPUID'.
5859 */
5860IEM_CIMPL_DEF_0(iemCImpl_cpuid)
5861{
5862 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5863
5864 CPUMGetGuestCpuId(IEMCPU_TO_VMCPU(pIemCpu), pCtx->eax, pCtx->ecx, &pCtx->eax, &pCtx->ebx, &pCtx->ecx, &pCtx->edx);
5865 pCtx->rax &= UINT32_C(0xffffffff);
5866 pCtx->rbx &= UINT32_C(0xffffffff);
5867 pCtx->rcx &= UINT32_C(0xffffffff);
5868 pCtx->rdx &= UINT32_C(0xffffffff);
5869
5870 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5871 return VINF_SUCCESS;
5872}
5873
5874
5875/**
5876 * Implements 'AAD'.
5877 *
5878 * @param bImm The immediate operand.
5879 */
5880IEM_CIMPL_DEF_1(iemCImpl_aad, uint8_t, bImm)
5881{
5882 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5883
5884 uint16_t const ax = pCtx->ax;
5885 uint8_t const al = (uint8_t)ax + (uint8_t)(ax >> 8) * bImm;
5886 pCtx->ax = al;
5887 iemHlpUpdateArithEFlagsU8(pIemCpu, al,
5888 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
5889 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
5890
5891 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5892 return VINF_SUCCESS;
5893}
5894
5895
5896/**
5897 * Implements 'AAM'.
5898 *
5899 * @param bImm The immediate operand. Cannot be 0.
5900 */
5901IEM_CIMPL_DEF_1(iemCImpl_aam, uint8_t, bImm)
5902{
5903 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5904 Assert(bImm != 0); /* #DE on 0 is handled in the decoder. */
5905
5906 uint16_t const ax = pCtx->ax;
5907 uint8_t const al = (uint8_t)ax % bImm;
5908 uint8_t const ah = (uint8_t)ax / bImm;
5909 pCtx->ax = (ah << 8) + al;
5910 iemHlpUpdateArithEFlagsU8(pIemCpu, al,
5911 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
5912 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
5913
5914 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5915 return VINF_SUCCESS;
5916}
5917
5918
5919/**
5920 * Implements 'DAA'.
5921 */
5922IEM_CIMPL_DEF_0(iemCImpl_daa)
5923{
5924 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5925
5926 uint8_t const al = pCtx->al;
5927 bool const fCarry = pCtx->eflags.Bits.u1CF;
5928
5929 if ( pCtx->eflags.Bits.u1AF
5930 || (al & 0xf) >= 10)
5931 {
5932 pCtx->al = al + 6;
5933 pCtx->eflags.Bits.u1AF = 1;
5934 }
5935 else
5936 pCtx->eflags.Bits.u1AF = 0;
5937
5938 if (al >= 0x9a || fCarry)
5939 {
5940 pCtx->al += 0x60;
5941 pCtx->eflags.Bits.u1CF = 1;
5942 }
5943 else
5944 pCtx->eflags.Bits.u1CF = 0;
5945
5946 iemHlpUpdateArithEFlagsU8(pIemCpu, pCtx->al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
5947 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5948 return VINF_SUCCESS;
5949}
5950
5951
5952/**
5953 * Implements 'DAS'.
5954 */
5955IEM_CIMPL_DEF_0(iemCImpl_das)
5956{
5957 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
5958
5959 uint8_t const uInputAL = pCtx->al;
5960 bool const fCarry = pCtx->eflags.Bits.u1CF;
5961
5962 if ( pCtx->eflags.Bits.u1AF
5963 || (uInputAL & 0xf) >= 10)
5964 {
5965 pCtx->eflags.Bits.u1AF = 1;
5966 if (uInputAL < 6)
5967 pCtx->eflags.Bits.u1CF = 1;
5968 pCtx->al = uInputAL - 6;
5969 }
5970 else
5971 {
5972 pCtx->eflags.Bits.u1AF = 0;
5973 pCtx->eflags.Bits.u1CF = 0;
5974 }
5975
5976 if (uInputAL >= 0x9a || fCarry)
5977 {
5978 pCtx->al -= 0x60;
5979 pCtx->eflags.Bits.u1CF = 1;
5980 }
5981
5982 iemHlpUpdateArithEFlagsU8(pIemCpu, pCtx->al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
5983 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
5984 return VINF_SUCCESS;
5985}
5986
5987
5988
5989
5990/*
5991 * Instantiate the various string operation combinations.
5992 */
5993#define OP_SIZE 8
5994#define ADDR_SIZE 16
5995#include "IEMAllCImplStrInstr.cpp.h"
5996#define OP_SIZE 8
5997#define ADDR_SIZE 32
5998#include "IEMAllCImplStrInstr.cpp.h"
5999#define OP_SIZE 8
6000#define ADDR_SIZE 64
6001#include "IEMAllCImplStrInstr.cpp.h"
6002
6003#define OP_SIZE 16
6004#define ADDR_SIZE 16
6005#include "IEMAllCImplStrInstr.cpp.h"
6006#define OP_SIZE 16
6007#define ADDR_SIZE 32
6008#include "IEMAllCImplStrInstr.cpp.h"
6009#define OP_SIZE 16
6010#define ADDR_SIZE 64
6011#include "IEMAllCImplStrInstr.cpp.h"
6012
6013#define OP_SIZE 32
6014#define ADDR_SIZE 16
6015#include "IEMAllCImplStrInstr.cpp.h"
6016#define OP_SIZE 32
6017#define ADDR_SIZE 32
6018#include "IEMAllCImplStrInstr.cpp.h"
6019#define OP_SIZE 32
6020#define ADDR_SIZE 64
6021#include "IEMAllCImplStrInstr.cpp.h"
6022
6023#define OP_SIZE 64
6024#define ADDR_SIZE 32
6025#include "IEMAllCImplStrInstr.cpp.h"
6026#define OP_SIZE 64
6027#define ADDR_SIZE 64
6028#include "IEMAllCImplStrInstr.cpp.h"
6029
6030
6031/**
6032 * Implements 'XGETBV'.
6033 */
6034IEM_CIMPL_DEF_0(iemCImpl_xgetbv)
6035{
6036 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
6037 if (pCtx->cr4 & X86_CR4_OSXSAVE)
6038 {
6039 uint32_t uEcx = pCtx->ecx;
6040 switch (uEcx)
6041 {
6042 case 0:
6043 break;
6044
6045 case 1: /** @todo Implement XCR1 support. */
6046 default:
6047 Log(("xgetbv ecx=%RX32 -> #GP(0)\n", uEcx));
6048 return iemRaiseGeneralProtectionFault0(pIemCpu);
6049
6050 }
6051 pCtx->rax = RT_LO_U32(pCtx->aXcr[uEcx]);
6052 pCtx->rdx = RT_HI_U32(pCtx->aXcr[uEcx]);
6053
6054 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
6055 return VINF_SUCCESS;
6056 }
6057 Log(("xgetbv CR4.OSXSAVE=0 -> UD\n"));
6058 return iemRaiseUndefinedOpcode(pIemCpu);
6059}
6060
6061
6062/**
6063 * Implements 'XSETBV'.
6064 */
6065IEM_CIMPL_DEF_0(iemCImpl_xsetbv)
6066{
6067 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
6068 if (pCtx->cr4 & X86_CR4_OSXSAVE)
6069 {
6070 if (pIemCpu->uCpl == 0)
6071 {
6072 uint32_t uEcx = pCtx->ecx;
6073 uint64_t uNewValue = RT_MAKE_U64(pCtx->eax, pCtx->edx);
6074 switch (uEcx)
6075 {
6076 case 0:
6077 {
6078 int rc = CPUMSetGuestXcr0(IEMCPU_TO_VMCPU(pIemCpu), uNewValue);
6079 if (rc == VINF_SUCCESS)
6080 break;
6081 Assert(rc == VERR_CPUM_RAISE_GP_0);
6082 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
6083 return iemRaiseGeneralProtectionFault0(pIemCpu);
6084 }
6085
6086 case 1: /** @todo Implement XCR1 support. */
6087 default:
6088 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
6089 return iemRaiseGeneralProtectionFault0(pIemCpu);
6090
6091 }
6092
6093 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
6094 return VINF_SUCCESS;
6095 }
6096
6097 Log(("xsetbv cpl=%u -> GP(0)\n", pIemCpu->uCpl));
6098 return iemRaiseGeneralProtectionFault0(pIemCpu);
6099 }
6100 Log(("xsetbv CR4.OSXSAVE=0 -> UD\n"));
6101 return iemRaiseUndefinedOpcode(pIemCpu);
6102}
6103
6104
6105
6106/**
6107 * Implements 'FINIT' and 'FNINIT'.
6108 *
6109 * @param fCheckXcpts Whether to check for umasked pending exceptions or
6110 * not.
6111 */
6112IEM_CIMPL_DEF_1(iemCImpl_finit, bool, fCheckXcpts)
6113{
6114 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
6115
6116 if (pCtx->cr0 & (X86_CR0_EM | X86_CR0_TS))
6117 return iemRaiseDeviceNotAvailable(pIemCpu);
6118
6119 NOREF(fCheckXcpts); /** @todo trigger pending exceptions:
6120 if (fCheckXcpts && TODO )
6121 return iemRaiseMathFault(pIemCpu);
6122 */
6123
6124 PX86XSAVEAREA pXState = pCtx->CTX_SUFF(pXState);
6125 pXState->x87.FCW = 0x37f;
6126 pXState->x87.FSW = 0;
6127 pXState->x87.FTW = 0x00; /* 0 - empty. */
6128 pXState->x87.FPUDP = 0;
6129 pXState->x87.DS = 0; //??
6130 pXState->x87.Rsrvd2= 0;
6131 pXState->x87.FPUIP = 0;
6132 pXState->x87.CS = 0; //??
6133 pXState->x87.Rsrvd1= 0;
6134 pXState->x87.FOP = 0;
6135
6136 iemHlpUsedFpu(pIemCpu);
6137 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
6138 return VINF_SUCCESS;
6139}
6140
6141
6142/**
6143 * Implements 'FXSAVE'.
6144 *
6145 * @param iEffSeg The effective segment.
6146 * @param GCPtrEff The address of the image.
6147 * @param enmEffOpSize The operand size (only REX.W really matters).
6148 */
6149IEM_CIMPL_DEF_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
6150{
6151 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
6152
6153 /*
6154 * Raise exceptions.
6155 */
6156 if (pCtx->cr0 & X86_CR0_EM)
6157 return iemRaiseUndefinedOpcode(pIemCpu);
6158 if (pCtx->cr0 & (X86_CR0_TS | X86_CR0_EM))
6159 return iemRaiseDeviceNotAvailable(pIemCpu);
6160 if (GCPtrEff & 15)
6161 {
6162 /** @todo CPU/VM detection possible! \#AC might not be signal for
6163 * all/any misalignment sizes, intel says its an implementation detail. */
6164 if ( (pCtx->cr0 & X86_CR0_AM)
6165 && pCtx->eflags.Bits.u1AC
6166 && pIemCpu->uCpl == 3)
6167 return iemRaiseAlignmentCheckException(pIemCpu);
6168 return iemRaiseGeneralProtectionFault0(pIemCpu);
6169 }
6170
6171 /*
6172 * Access the memory.
6173 */
6174 void *pvMem512;
6175 VBOXSTRICTRC rcStrict = iemMemMap(pIemCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
6176 if (rcStrict != VINF_SUCCESS)
6177 return rcStrict;
6178 PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
6179 PCX86FXSTATE pSrc = &pCtx->CTX_SUFF(pXState)->x87;
6180
6181 /*
6182 * Store the registers.
6183 */
6184 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
6185 * implementation specific whether MXCSR and XMM0-XMM7 are saved. */
6186
6187 /* common for all formats */
6188 pDst->FCW = pSrc->FCW;
6189 pDst->FSW = pSrc->FSW;
6190 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
6191 pDst->FOP = pSrc->FOP;
6192 pDst->MXCSR = pSrc->MXCSR;
6193 pDst->MXCSR_MASK = pSrc->MXCSR_MASK;
6194 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
6195 {
6196 /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
6197 * them for now... */
6198 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
6199 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
6200 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
6201 pDst->aRegs[i].au32[3] = 0;
6202 }
6203
6204 /* FPU IP, CS, DP and DS. */
6205 pDst->FPUIP = pSrc->FPUIP;
6206 pDst->CS = pSrc->CS;
6207 pDst->FPUDP = pSrc->FPUDP;
6208 pDst->DS = pSrc->DS;
6209 if (enmEffOpSize == IEMMODE_64BIT)
6210 {
6211 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
6212 pDst->Rsrvd1 = pSrc->Rsrvd1;
6213 pDst->Rsrvd2 = pSrc->Rsrvd2;
6214 pDst->au32RsrvdForSoftware[0] = 0;
6215 }
6216 else
6217 {
6218 pDst->Rsrvd1 = 0;
6219 pDst->Rsrvd2 = 0;
6220 pDst->au32RsrvdForSoftware[0] = X86_FXSTATE_RSVD_32BIT_MAGIC;
6221 }
6222
6223 /* XMM registers. */
6224 if ( !(pCtx->msrEFER & MSR_K6_EFER_FFXSR)
6225 || pIemCpu->enmCpuMode != IEMMODE_64BIT
6226 || pIemCpu->uCpl != 0)
6227 {
6228 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
6229 for (uint32_t i = 0; i < cXmmRegs; i++)
6230 pDst->aXMM[i] = pSrc->aXMM[i];
6231 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
6232 * right? */
6233 }
6234
6235 /*
6236 * Commit the memory.
6237 */
6238 rcStrict = iemMemCommitAndUnmap(pIemCpu, pvMem512, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
6239 if (rcStrict != VINF_SUCCESS)
6240 return rcStrict;
6241
6242 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
6243 return VINF_SUCCESS;
6244}
6245
6246
6247/**
6248 * Implements 'FXRSTOR'.
6249 *
6250 * @param GCPtrEff The address of the image.
6251 * @param enmEffOpSize The operand size (only REX.W really matters).
6252 */
6253IEM_CIMPL_DEF_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
6254{
6255 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
6256
6257 /*
6258 * Raise exceptions.
6259 */
6260 if (pCtx->cr0 & X86_CR0_EM)
6261 return iemRaiseUndefinedOpcode(pIemCpu);
6262 if (pCtx->cr0 & (X86_CR0_TS | X86_CR0_EM))
6263 return iemRaiseDeviceNotAvailable(pIemCpu);
6264 if (GCPtrEff & 15)
6265 {
6266 /** @todo CPU/VM detection possible! \#AC might not be signal for
6267 * all/any misalignment sizes, intel says its an implementation detail. */
6268 if ( (pCtx->cr0 & X86_CR0_AM)
6269 && pCtx->eflags.Bits.u1AC
6270 && pIemCpu->uCpl == 3)
6271 return iemRaiseAlignmentCheckException(pIemCpu);
6272 return iemRaiseGeneralProtectionFault0(pIemCpu);
6273 }
6274
6275 /*
6276 * Access the memory.
6277 */
6278 void *pvMem512;
6279 VBOXSTRICTRC rcStrict = iemMemMap(pIemCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R);
6280 if (rcStrict != VINF_SUCCESS)
6281 return rcStrict;
6282 PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
6283 PX86FXSTATE pDst = &pCtx->CTX_SUFF(pXState)->x87;
6284
6285 /*
6286 * Check the state for stuff which will #GP(0).
6287 */
6288 uint32_t const fMXCSR = pSrc->MXCSR;
6289 uint32_t const fMXCSR_MASK = pDst->MXCSR_MASK ? pDst->MXCSR_MASK : UINT32_C(0xffbf);
6290 if (fMXCSR & ~fMXCSR_MASK)
6291 {
6292 Log(("fxrstor: MXCSR=%#x (MXCSR_MASK=%#x) -> #GP(0)\n", fMXCSR, fMXCSR_MASK));
6293 return iemRaiseGeneralProtectionFault0(pIemCpu);
6294 }
6295
6296 /*
6297 * Load the registers.
6298 */
6299 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
6300 * implementation specific whether MXCSR and XMM0-XMM7 are restored. */
6301
6302 /* common for all formats */
6303 pDst->FCW = pSrc->FCW;
6304 pDst->FSW = pSrc->FSW;
6305 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
6306 pDst->FOP = pSrc->FOP;
6307 pDst->MXCSR = fMXCSR;
6308 /* (MXCSR_MASK is read-only) */
6309 for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
6310 {
6311 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
6312 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
6313 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
6314 pDst->aRegs[i].au32[3] = 0;
6315 }
6316
6317 /* FPU IP, CS, DP and DS. */
6318 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
6319 {
6320 pDst->FPUIP = pSrc->FPUIP;
6321 pDst->CS = pSrc->CS;
6322 pDst->Rsrvd1 = pSrc->Rsrvd1;
6323 pDst->FPUDP = pSrc->FPUDP;
6324 pDst->DS = pSrc->DS;
6325 pDst->Rsrvd2 = pSrc->Rsrvd2;
6326 }
6327 else
6328 {
6329 pDst->FPUIP = pSrc->FPUIP;
6330 pDst->CS = pSrc->CS;
6331 pDst->Rsrvd1 = 0;
6332 pDst->FPUDP = pSrc->FPUDP;
6333 pDst->DS = pSrc->DS;
6334 pDst->Rsrvd2 = 0;
6335 }
6336
6337 /* XMM registers. */
6338 if ( !(pCtx->msrEFER & MSR_K6_EFER_FFXSR)
6339 || pIemCpu->enmCpuMode != IEMMODE_64BIT
6340 || pIemCpu->uCpl != 0)
6341 {
6342 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
6343 for (uint32_t i = 0; i < cXmmRegs; i++)
6344 pDst->aXMM[i] = pSrc->aXMM[i];
6345 }
6346
6347 /*
6348 * Commit the memory.
6349 */
6350 rcStrict = iemMemCommitAndUnmap(pIemCpu, pvMem512, IEM_ACCESS_DATA_R);
6351 if (rcStrict != VINF_SUCCESS)
6352 return rcStrict;
6353
6354 iemHlpUsedFpu(pIemCpu);
6355 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
6356 return VINF_SUCCESS;
6357}
6358
6359
6360/**
6361 * Commmon routine for fnstenv and fnsave.
6362 *
6363 * @param uPtr Where to store the state.
6364 * @param pCtx The CPU context.
6365 */
6366static void iemCImplCommonFpuStoreEnv(PIEMCPU pIemCpu, IEMMODE enmEffOpSize, RTPTRUNION uPtr, PCCPUMCTX pCtx)
6367{
6368 PCX86FXSTATE pSrcX87 = &pCtx->CTX_SUFF(pXState)->x87;
6369 if (enmEffOpSize == IEMMODE_16BIT)
6370 {
6371 uPtr.pu16[0] = pSrcX87->FCW;
6372 uPtr.pu16[1] = pSrcX87->FSW;
6373 uPtr.pu16[2] = iemFpuCalcFullFtw(pSrcX87);
6374 if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
6375 {
6376 /** @todo Testcase: How does this work when the FPUIP/CS was saved in
6377 * protected mode or long mode and we save it in real mode? And vice
6378 * versa? And with 32-bit operand size? I think CPU is storing the
6379 * effective address ((CS << 4) + IP) in the offset register and not
6380 * doing any address calculations here. */
6381 uPtr.pu16[3] = (uint16_t)pSrcX87->FPUIP;
6382 uPtr.pu16[4] = ((pSrcX87->FPUIP >> 4) & UINT16_C(0xf000)) | pSrcX87->FOP;
6383 uPtr.pu16[5] = (uint16_t)pSrcX87->FPUDP;
6384 uPtr.pu16[6] = (pSrcX87->FPUDP >> 4) & UINT16_C(0xf000);
6385 }
6386 else
6387 {
6388 uPtr.pu16[3] = pSrcX87->FPUIP;
6389 uPtr.pu16[4] = pSrcX87->CS;
6390 uPtr.pu16[5] = pSrcX87->FPUDP;
6391 uPtr.pu16[6] = pSrcX87->DS;
6392 }
6393 }
6394 else
6395 {
6396 /** @todo Testcase: what is stored in the "gray" areas? (figure 8-9 and 8-10) */
6397 uPtr.pu16[0*2] = pSrcX87->FCW;
6398 uPtr.pu16[1*2] = pSrcX87->FSW;
6399 uPtr.pu16[2*2] = iemFpuCalcFullFtw(pSrcX87);
6400 if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
6401 {
6402 uPtr.pu16[3*2] = (uint16_t)pSrcX87->FPUIP;
6403 uPtr.pu32[4] = ((pSrcX87->FPUIP & UINT32_C(0xffff0000)) >> 4) | pSrcX87->FOP;
6404 uPtr.pu16[5*2] = (uint16_t)pSrcX87->FPUDP;
6405 uPtr.pu32[6] = (pSrcX87->FPUDP & UINT32_C(0xffff0000)) >> 4;
6406 }
6407 else
6408 {
6409 uPtr.pu32[3] = pSrcX87->FPUIP;
6410 uPtr.pu16[4*2] = pSrcX87->CS;
6411 uPtr.pu16[4*2+1]= pSrcX87->FOP;
6412 uPtr.pu32[5] = pSrcX87->FPUDP;
6413 uPtr.pu16[6*2] = pSrcX87->DS;
6414 }
6415 }
6416}
6417
6418
6419/**
6420 * Commmon routine for fldenv and frstor
6421 *
6422 * @param uPtr Where to store the state.
6423 * @param pCtx The CPU context.
6424 */
6425static void iemCImplCommonFpuRestoreEnv(PIEMCPU pIemCpu, IEMMODE enmEffOpSize, RTCPTRUNION uPtr, PCPUMCTX pCtx)
6426{
6427 PX86FXSTATE pDstX87 = &pCtx->CTX_SUFF(pXState)->x87;
6428 if (enmEffOpSize == IEMMODE_16BIT)
6429 {
6430 pDstX87->FCW = uPtr.pu16[0];
6431 pDstX87->FSW = uPtr.pu16[1];
6432 pDstX87->FTW = uPtr.pu16[2];
6433 if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
6434 {
6435 pDstX87->FPUIP = uPtr.pu16[3] | ((uint32_t)(uPtr.pu16[4] & UINT16_C(0xf000)) << 4);
6436 pDstX87->FPUDP = uPtr.pu16[5] | ((uint32_t)(uPtr.pu16[6] & UINT16_C(0xf000)) << 4);
6437 pDstX87->FOP = uPtr.pu16[4] & UINT16_C(0x07ff);
6438 pDstX87->CS = 0;
6439 pDstX87->Rsrvd1= 0;
6440 pDstX87->DS = 0;
6441 pDstX87->Rsrvd2= 0;
6442 }
6443 else
6444 {
6445 pDstX87->FPUIP = uPtr.pu16[3];
6446 pDstX87->CS = uPtr.pu16[4];
6447 pDstX87->Rsrvd1= 0;
6448 pDstX87->FPUDP = uPtr.pu16[5];
6449 pDstX87->DS = uPtr.pu16[6];
6450 pDstX87->Rsrvd2= 0;
6451 /** @todo Testcase: Is FOP cleared when doing 16-bit protected mode fldenv? */
6452 }
6453 }
6454 else
6455 {
6456 pDstX87->FCW = uPtr.pu16[0*2];
6457 pDstX87->FSW = uPtr.pu16[1*2];
6458 pDstX87->FTW = uPtr.pu16[2*2];
6459 if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
6460 {
6461 pDstX87->FPUIP = uPtr.pu16[3*2] | ((uPtr.pu32[4] & UINT32_C(0x0ffff000)) << 4);
6462 pDstX87->FOP = uPtr.pu32[4] & UINT16_C(0x07ff);
6463 pDstX87->FPUDP = uPtr.pu16[5*2] | ((uPtr.pu32[6] & UINT32_C(0x0ffff000)) << 4);
6464 pDstX87->CS = 0;
6465 pDstX87->Rsrvd1= 0;
6466 pDstX87->DS = 0;
6467 pDstX87->Rsrvd2= 0;
6468 }
6469 else
6470 {
6471 pDstX87->FPUIP = uPtr.pu32[3];
6472 pDstX87->CS = uPtr.pu16[4*2];
6473 pDstX87->Rsrvd1= 0;
6474 pDstX87->FOP = uPtr.pu16[4*2+1];
6475 pDstX87->FPUDP = uPtr.pu32[5];
6476 pDstX87->DS = uPtr.pu16[6*2];
6477 pDstX87->Rsrvd2= 0;
6478 }
6479 }
6480
6481 /* Make adjustments. */
6482 pDstX87->FTW = iemFpuCompressFtw(pDstX87->FTW);
6483 pDstX87->FCW &= ~X86_FCW_ZERO_MASK;
6484 iemFpuRecalcExceptionStatus(pDstX87);
6485 /** @todo Testcase: Check if ES and/or B are automatically cleared if no
6486 * exceptions are pending after loading the saved state? */
6487}
6488
6489
6490/**
6491 * Implements 'FNSTENV'.
6492 *
6493 * @param enmEffOpSize The operand size (only REX.W really matters).
6494 * @param iEffSeg The effective segment register for @a GCPtrEff.
6495 * @param GCPtrEffDst The address of the image.
6496 */
6497IEM_CIMPL_DEF_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
6498{
6499 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
6500 RTPTRUNION uPtr;
6501 VBOXSTRICTRC rcStrict = iemMemMap(pIemCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
6502 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
6503 if (rcStrict != VINF_SUCCESS)
6504 return rcStrict;
6505
6506 iemCImplCommonFpuStoreEnv(pIemCpu, enmEffOpSize, uPtr, pCtx);
6507
6508 rcStrict = iemMemCommitAndUnmap(pIemCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
6509 if (rcStrict != VINF_SUCCESS)
6510 return rcStrict;
6511
6512 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
6513 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
6514 return VINF_SUCCESS;
6515}
6516
6517
6518/**
6519 * Implements 'FNSAVE'.
6520 *
6521 * @param GCPtrEffDst The address of the image.
6522 * @param enmEffOpSize The operand size.
6523 */
6524IEM_CIMPL_DEF_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
6525{
6526 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
6527 RTPTRUNION uPtr;
6528 VBOXSTRICTRC rcStrict = iemMemMap(pIemCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
6529 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
6530 if (rcStrict != VINF_SUCCESS)
6531 return rcStrict;
6532
6533 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
6534 iemCImplCommonFpuStoreEnv(pIemCpu, enmEffOpSize, uPtr, pCtx);
6535 PRTFLOAT80U paRegs = (PRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
6536 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
6537 {
6538 paRegs[i].au32[0] = pFpuCtx->aRegs[i].au32[0];
6539 paRegs[i].au32[1] = pFpuCtx->aRegs[i].au32[1];
6540 paRegs[i].au16[4] = pFpuCtx->aRegs[i].au16[4];
6541 }
6542
6543 rcStrict = iemMemCommitAndUnmap(pIemCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
6544 if (rcStrict != VINF_SUCCESS)
6545 return rcStrict;
6546
6547 /*
6548 * Re-initialize the FPU context.
6549 */
6550 pFpuCtx->FCW = 0x37f;
6551 pFpuCtx->FSW = 0;
6552 pFpuCtx->FTW = 0x00; /* 0 - empty */
6553 pFpuCtx->FPUDP = 0;
6554 pFpuCtx->DS = 0;
6555 pFpuCtx->Rsrvd2= 0;
6556 pFpuCtx->FPUIP = 0;
6557 pFpuCtx->CS = 0;
6558 pFpuCtx->Rsrvd1= 0;
6559 pFpuCtx->FOP = 0;
6560
6561 iemHlpUsedFpu(pIemCpu);
6562 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
6563 return VINF_SUCCESS;
6564}
6565
6566
6567
6568/**
6569 * Implements 'FLDENV'.
6570 *
6571 * @param enmEffOpSize The operand size (only REX.W really matters).
6572 * @param iEffSeg The effective segment register for @a GCPtrEff.
6573 * @param GCPtrEffSrc The address of the image.
6574 */
6575IEM_CIMPL_DEF_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
6576{
6577 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
6578 RTCPTRUNION uPtr;
6579 VBOXSTRICTRC rcStrict = iemMemMap(pIemCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
6580 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R);
6581 if (rcStrict != VINF_SUCCESS)
6582 return rcStrict;
6583
6584 iemCImplCommonFpuRestoreEnv(pIemCpu, enmEffOpSize, uPtr, pCtx);
6585
6586 rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
6587 if (rcStrict != VINF_SUCCESS)
6588 return rcStrict;
6589
6590 iemHlpUsedFpu(pIemCpu);
6591 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
6592 return VINF_SUCCESS;
6593}
6594
6595
6596/**
6597 * Implements 'FRSTOR'.
6598 *
6599 * @param GCPtrEffSrc The address of the image.
6600 * @param enmEffOpSize The operand size.
6601 */
6602IEM_CIMPL_DEF_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
6603{
6604 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
6605 RTCPTRUNION uPtr;
6606 VBOXSTRICTRC rcStrict = iemMemMap(pIemCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
6607 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R);
6608 if (rcStrict != VINF_SUCCESS)
6609 return rcStrict;
6610
6611 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
6612 iemCImplCommonFpuRestoreEnv(pIemCpu, enmEffOpSize, uPtr, pCtx);
6613 PCRTFLOAT80U paRegs = (PCRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
6614 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
6615 {
6616 pFpuCtx->aRegs[i].au32[0] = paRegs[i].au32[0];
6617 pFpuCtx->aRegs[i].au32[1] = paRegs[i].au32[1];
6618 pFpuCtx->aRegs[i].au32[2] = paRegs[i].au16[4];
6619 pFpuCtx->aRegs[i].au32[3] = 0;
6620 }
6621
6622 rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
6623 if (rcStrict != VINF_SUCCESS)
6624 return rcStrict;
6625
6626 iemHlpUsedFpu(pIemCpu);
6627 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
6628 return VINF_SUCCESS;
6629}
6630
6631
6632/**
6633 * Implements 'FLDCW'.
6634 *
6635 * @param u16Fcw The new FCW.
6636 */
6637IEM_CIMPL_DEF_1(iemCImpl_fldcw, uint16_t, u16Fcw)
6638{
6639 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
6640
6641 /** @todo Testcase: Check what happens when trying to load X86_FCW_PC_RSVD. */
6642 /** @todo Testcase: Try see what happens when trying to set undefined bits
6643 * (other than 6 and 7). Currently ignoring them. */
6644 /** @todo Testcase: Test that it raises and loweres the FPU exception bits
6645 * according to FSW. (This is was is currently implemented.) */
6646 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
6647 pFpuCtx->FCW = u16Fcw & ~X86_FCW_ZERO_MASK;
6648 iemFpuRecalcExceptionStatus(pFpuCtx);
6649
6650 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
6651 iemHlpUsedFpu(pIemCpu);
6652 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
6653 return VINF_SUCCESS;
6654}
6655
6656
6657
6658/**
6659 * Implements the underflow case of fxch.
6660 *
6661 * @param iStReg The other stack register.
6662 */
6663IEM_CIMPL_DEF_1(iemCImpl_fxch_underflow, uint8_t, iStReg)
6664{
6665 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
6666
6667 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
6668 unsigned const iReg1 = X86_FSW_TOP_GET(pFpuCtx->FSW);
6669 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
6670 Assert(!(RT_BIT(iReg1) & pFpuCtx->FTW) || !(RT_BIT(iReg2) & pFpuCtx->FTW));
6671
6672 /** @todo Testcase: fxch underflow. Making assumptions that underflowed
6673 * registers are read as QNaN and then exchanged. This could be
6674 * wrong... */
6675 if (pFpuCtx->FCW & X86_FCW_IM)
6676 {
6677 if (RT_BIT(iReg1) & pFpuCtx->FTW)
6678 {
6679 if (RT_BIT(iReg2) & pFpuCtx->FTW)
6680 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
6681 else
6682 pFpuCtx->aRegs[0].r80 = pFpuCtx->aRegs[iStReg].r80;
6683 iemFpuStoreQNan(&pFpuCtx->aRegs[iStReg].r80);
6684 }
6685 else
6686 {
6687 pFpuCtx->aRegs[iStReg].r80 = pFpuCtx->aRegs[0].r80;
6688 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
6689 }
6690 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
6691 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
6692 }
6693 else
6694 {
6695 /* raise underflow exception, don't change anything. */
6696 pFpuCtx->FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_XCPT_MASK);
6697 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
6698 }
6699
6700 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
6701 iemHlpUsedFpu(pIemCpu);
6702 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
6703 return VINF_SUCCESS;
6704}
6705
6706
6707/**
6708 * Implements 'FCOMI', 'FCOMIP', 'FUCOMI', and 'FUCOMIP'.
6709 *
6710 * @param cToAdd 1 or 7.
6711 */
6712IEM_CIMPL_DEF_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop)
6713{
6714 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
6715 Assert(iStReg < 8);
6716
6717 /*
6718 * Raise exceptions.
6719 */
6720 if (pCtx->cr0 & (X86_CR0_EM | X86_CR0_TS))
6721 return iemRaiseDeviceNotAvailable(pIemCpu);
6722
6723 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
6724 uint16_t u16Fsw = pFpuCtx->FSW;
6725 if (u16Fsw & X86_FSW_ES)
6726 return iemRaiseMathFault(pIemCpu);
6727
6728 /*
6729 * Check if any of the register accesses causes #SF + #IA.
6730 */
6731 unsigned const iReg1 = X86_FSW_TOP_GET(u16Fsw);
6732 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
6733 if ((pFpuCtx->FTW & (RT_BIT(iReg1) | RT_BIT(iReg2))) == (RT_BIT(iReg1) | RT_BIT(iReg2)))
6734 {
6735 uint32_t u32Eflags = pfnAImpl(pFpuCtx, &u16Fsw, &pFpuCtx->aRegs[0].r80, &pFpuCtx->aRegs[iStReg].r80);
6736 NOREF(u32Eflags);
6737
6738 pFpuCtx->FSW &= ~X86_FSW_C1;
6739 pFpuCtx->FSW |= u16Fsw & ~X86_FSW_TOP_MASK;
6740 if ( !(u16Fsw & X86_FSW_IE)
6741 || (pFpuCtx->FCW & X86_FCW_IM) )
6742 {
6743 pCtx->eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
6744 pCtx->eflags.u |= pCtx->eflags.u & (X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
6745 }
6746 }
6747 else if (pFpuCtx->FCW & X86_FCW_IM)
6748 {
6749 /* Masked underflow. */
6750 pFpuCtx->FSW &= ~X86_FSW_C1;
6751 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF;
6752 pCtx->eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
6753 pCtx->eflags.u |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF;
6754 }
6755 else
6756 {
6757 /* Raise underflow - don't touch EFLAGS or TOP. */
6758 pFpuCtx->FSW &= ~X86_FSW_C1;
6759 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
6760 fPop = false;
6761 }
6762
6763 /*
6764 * Pop if necessary.
6765 */
6766 if (fPop)
6767 {
6768 pFpuCtx->FTW &= ~RT_BIT(iReg1);
6769 pFpuCtx->FSW &= X86_FSW_TOP_MASK;
6770 pFpuCtx->FSW |= ((iReg1 + 7) & X86_FSW_TOP_SMASK) << X86_FSW_TOP_SHIFT;
6771 }
6772
6773 iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx, pFpuCtx);
6774 iemHlpUsedFpu(pIemCpu);
6775 iemRegAddToRipAndClearRF(pIemCpu, cbInstr);
6776 return VINF_SUCCESS;
6777}
6778
6779/** @} */
6780
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