VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h@ 77577

Last change on this file since 77577 was 77569, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 On-demand importing of externally kept guest-CPU state for VM-exits and tightening of importing externally kept guest-CPU state on VMLAUNCH/VMRESUME.
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File size: 351.5 KB
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1/* $Id: IEMAllCImplVmxInstr.cpp.h 77569 2019-03-06 08:18:51Z vboxsync $ */
2/** @file
3 * IEM - VT-x instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Defined Constants And Macros *
21*********************************************************************************************************************************/
22#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
23/**
24 * Gets the ModR/M, SIB and displacement byte(s) from decoded opcodes given their
25 * relative offsets.
26 */
27# ifdef IEM_WITH_CODE_TLB
28# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) do { } while (0)
29# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) do { } while (0)
30# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
31# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) do { } while (0)
32# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
33# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) do { } while (0)
34# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
35# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) do { } while (0)
36# error "Implement me: Getting ModR/M, SIB, displacement needs to work even when instruction crosses a page boundary."
37# else /* !IEM_WITH_CODE_TLB */
38# define IEM_MODRM_GET_U8(a_pVCpu, a_bModRm, a_offModRm) \
39 do \
40 { \
41 Assert((a_offModRm) < (a_pVCpu)->iem.s.cbOpcode); \
42 (a_bModRm) = (a_pVCpu)->iem.s.abOpcode[(a_offModRm)]; \
43 } while (0)
44
45# define IEM_SIB_GET_U8(a_pVCpu, a_bSib, a_offSib) IEM_MODRM_GET_U8(a_pVCpu, a_bSib, a_offSib)
46
47# define IEM_DISP_GET_U16(a_pVCpu, a_u16Disp, a_offDisp) \
48 do \
49 { \
50 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
51 uint8_t const bTmpLo = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
52 uint8_t const bTmpHi = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
53 (a_u16Disp) = RT_MAKE_U16(bTmpLo, bTmpHi); \
54 } while (0)
55
56# define IEM_DISP_GET_S8_SX_U16(a_pVCpu, a_u16Disp, a_offDisp) \
57 do \
58 { \
59 Assert((a_offDisp) < (a_pVCpu)->iem.s.cbOpcode); \
60 (a_u16Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
61 } while (0)
62
63# define IEM_DISP_GET_U32(a_pVCpu, a_u32Disp, a_offDisp) \
64 do \
65 { \
66 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
67 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
68 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
69 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
70 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
71 (a_u32Disp) = RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
72 } while (0)
73
74# define IEM_DISP_GET_S8_SX_U32(a_pVCpu, a_u32Disp, a_offDisp) \
75 do \
76 { \
77 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
78 (a_u32Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
79 } while (0)
80
81# define IEM_DISP_GET_S8_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
82 do \
83 { \
84 Assert((a_offDisp) + 1 < (a_pVCpu)->iem.s.cbOpcode); \
85 (a_u64Disp) = (int8_t)((a_pVCpu)->iem.s.abOpcode[(a_offDisp)]); \
86 } while (0)
87
88# define IEM_DISP_GET_S32_SX_U64(a_pVCpu, a_u64Disp, a_offDisp) \
89 do \
90 { \
91 Assert((a_offDisp) + 3 < (a_pVCpu)->iem.s.cbOpcode); \
92 uint8_t const bTmp0 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp)]; \
93 uint8_t const bTmp1 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 1]; \
94 uint8_t const bTmp2 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 2]; \
95 uint8_t const bTmp3 = (a_pVCpu)->iem.s.abOpcode[(a_offDisp) + 3]; \
96 (a_u64Disp) = (int32_t)RT_MAKE_U32_FROM_U8(bTmp0, bTmp1, bTmp2, bTmp3); \
97 } while (0)
98# endif /* !IEM_WITH_CODE_TLB */
99
100/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
101# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
102
103/** Whether a shadow VMCS is present for the given VCPU. */
104# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
105
106/** Gets the VMXON region pointer. */
107# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
108
109/** Gets the guest-physical address of the current VMCS for the given VCPU. */
110# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
111
112/** Whether a current VMCS is present for the given VCPU. */
113# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
114
115/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
116# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
117 do \
118 { \
119 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
120 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
121 } while (0)
122
123/** Clears any current VMCS for the given VCPU. */
124# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
125 do \
126 { \
127 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
128 } while (0)
129
130/** Check for VMX instructions requiring to be in VMX operation.
131 * @note Any changes here, check if IEMOP_HLP_IN_VMX_OPERATION needs updating. */
132# define IEM_VMX_IN_VMX_OPERATION(a_pVCpu, a_szInstr, a_InsDiagPrefix) \
133 do \
134 { \
135 if (IEM_VMX_IS_ROOT_MODE(a_pVCpu)) \
136 { /* likely */ } \
137 else \
138 { \
139 Log((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
140 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
141 return iemRaiseUndefinedOpcode(a_pVCpu); \
142 } \
143 } while (0)
144
145/** Marks a VM-entry failure with a diagnostic reason, logs and returns. */
146# define IEM_VMX_VMENTRY_FAILED_RET(a_pVCpu, a_pszInstr, a_pszFailure, a_VmxDiag) \
147 do \
148 { \
149 Log(("%s: VM-entry failed! enmDiag=%u (%s) -> %s\n", (a_pszInstr), (a_VmxDiag), \
150 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
151 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
152 return VERR_VMX_VMENTRY_FAILED; \
153 } while (0)
154
155/** Marks a VM-exit failure with a diagnostic reason, logs and returns. */
156# define IEM_VMX_VMEXIT_FAILED_RET(a_pVCpu, a_uExitReason, a_pszFailure, a_VmxDiag) \
157 do \
158 { \
159 Log(("VM-exit failed! uExitReason=%u enmDiag=%u (%s) -> %s\n", (a_uExitReason), (a_VmxDiag), \
160 HMGetVmxDiagDesc(a_VmxDiag), (a_pszFailure))); \
161 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.enmDiag = (a_VmxDiag); \
162 return VERR_VMX_VMEXIT_FAILED; \
163 } while (0)
164
165/** Enables/disables IEM-only EM execution policy in and from ring-3. */
166# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
167# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) \
168 do { \
169 Log(("%s: Enabling IEM-only EM execution policy!\n", (a_pszLogPrefix))); \
170 int rcSched = EMR3SetExecutionPolicy((a_pVCpu)->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true); \
171 if (rcSched != VINF_SUCCESS) \
172 iemSetPassUpStatus(pVCpu, rcSched); \
173 return (a_rcStrictRet); \
174 } while (0)
175
176# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) \
177 do { \
178 Log(("%s: Disabling IEM-only EM execution policy!\n", (a_pszLogPrefix))); \
179 int rcSched = EMR3SetExecutionPolicy((a_pVCpu)->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false); \
180 if (rcSched != VINF_SUCCESS) \
181 iemSetPassUpStatus(pVCpu, rcSched); \
182 return (a_rcStrictRet); \
183 } while (0)
184# else
185# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) do { return (a_rcRet); } while (0)
186# define IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(a_pVCpu, a_pszLogPrefix, a_rcStrictRet) do { return (a_rcRet); } while (0)
187# endif
188
189
190/*********************************************************************************************************************************
191* Global Variables *
192*********************************************************************************************************************************/
193/** @todo NSTVMX: The following VM-exit intercepts are pending:
194 * VMX_EXIT_IO_SMI
195 * VMX_EXIT_SMI
196 * VMX_EXIT_INT_WINDOW
197 * VMX_EXIT_NMI_WINDOW
198 * VMX_EXIT_GETSEC
199 * VMX_EXIT_RSM
200 * VMX_EXIT_MTF
201 * VMX_EXIT_MONITOR (APIC access VM-exit caused by MONITOR pending)
202 * VMX_EXIT_ERR_MACHINE_CHECK
203 * VMX_EXIT_TPR_BELOW_THRESHOLD
204 * VMX_EXIT_APIC_ACCESS
205 * VMX_EXIT_VIRTUALIZED_EOI
206 * VMX_EXIT_EPT_VIOLATION
207 * VMX_EXIT_EPT_MISCONFIG
208 * VMX_EXIT_INVEPT
209 * VMX_EXIT_PREEMPT_TIMER
210 * VMX_EXIT_INVVPID
211 * VMX_EXIT_APIC_WRITE
212 * VMX_EXIT_RDRAND
213 * VMX_EXIT_VMFUNC
214 * VMX_EXIT_ENCLS
215 * VMX_EXIT_RDSEED
216 * VMX_EXIT_PML_FULL
217 * VMX_EXIT_XSAVES
218 * VMX_EXIT_XRSTORS
219 */
220/**
221 * Map of VMCS field encodings to their virtual-VMCS structure offsets.
222 *
223 * The first array dimension is VMCS field encoding of Width OR'ed with Type and the
224 * second dimension is the Index, see VMXVMCSFIELDENC.
225 */
226uint16_t const g_aoffVmcsMap[16][VMX_V_VMCS_MAX_INDEX + 1] =
227{
228 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
229 {
230 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u16Vpid),
231 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u16PostIntNotifyVector),
232 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u16EptpIndex),
233 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
234 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
235 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
236 },
237 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
238 {
239 /* 0-7 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
240 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
241 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
242 /* 24-25 */ UINT16_MAX, UINT16_MAX
243 },
244 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
245 {
246 /* 0 */ RT_UOFFSETOF(VMXVVMCS, GuestEs),
247 /* 1 */ RT_UOFFSETOF(VMXVVMCS, GuestCs),
248 /* 2 */ RT_UOFFSETOF(VMXVVMCS, GuestSs),
249 /* 3 */ RT_UOFFSETOF(VMXVVMCS, GuestDs),
250 /* 4 */ RT_UOFFSETOF(VMXVVMCS, GuestFs),
251 /* 5 */ RT_UOFFSETOF(VMXVVMCS, GuestGs),
252 /* 6 */ RT_UOFFSETOF(VMXVVMCS, GuestLdtr),
253 /* 7 */ RT_UOFFSETOF(VMXVVMCS, GuestTr),
254 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u16GuestIntStatus),
255 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u16PmlIndex),
256 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
257 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
258 },
259 /* VMX_VMCS_ENC_WIDTH_16BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
260 {
261 /* 0 */ RT_UOFFSETOF(VMXVVMCS, HostEs),
262 /* 1 */ RT_UOFFSETOF(VMXVVMCS, HostCs),
263 /* 2 */ RT_UOFFSETOF(VMXVVMCS, HostSs),
264 /* 3 */ RT_UOFFSETOF(VMXVVMCS, HostDs),
265 /* 4 */ RT_UOFFSETOF(VMXVVMCS, HostFs),
266 /* 5 */ RT_UOFFSETOF(VMXVVMCS, HostGs),
267 /* 6 */ RT_UOFFSETOF(VMXVVMCS, HostTr),
268 /* 7-14 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
269 /* 15-22 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
270 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
271 },
272 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
273 {
274 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapA),
275 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64AddrIoBitmapB),
276 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64AddrMsrBitmap),
277 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrStore),
278 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64AddrExitMsrLoad),
279 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEntryMsrLoad),
280 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64ExecVmcsPtr),
281 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPml),
282 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64TscOffset),
283 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVirtApic),
284 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64AddrApicAccess),
285 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64AddrPostedIntDesc),
286 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64VmFuncCtls),
287 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64EptpPtr),
288 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap0),
289 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap1),
290 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap2),
291 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64EoiExitBitmap3),
292 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEptpList),
293 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmreadBitmap),
294 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u64AddrVmwriteBitmap),
295 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u64AddrXcptVeInfo),
296 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u64XssBitmap),
297 /* 23 */ RT_UOFFSETOF(VMXVVMCS, u64AddrEnclsBitmap),
298 /* 24 */ UINT16_MAX,
299 /* 25 */ RT_UOFFSETOF(VMXVVMCS, u64TscMultiplier)
300 },
301 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
302 {
303 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestPhysAddr),
304 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
305 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
306 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
307 /* 25 */ UINT16_MAX
308 },
309 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
310 {
311 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64VmcsLinkPtr),
312 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDebugCtlMsr),
313 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPatMsr),
314 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEferMsr),
315 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPerfGlobalCtlMsr),
316 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte0),
317 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte1),
318 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte2),
319 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPdpte3),
320 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestBndcfgsMsr),
321 /* 10-17 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
322 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
323 },
324 /* VMX_VMCS_ENC_WIDTH_64BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
325 {
326 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostPatMsr),
327 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostEferMsr),
328 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostPerfGlobalCtlMsr),
329 /* 3-10 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
330 /* 11-18 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
331 /* 19-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
332 },
333 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_CONTROL: */
334 {
335 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32PinCtls),
336 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls),
337 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32XcptBitmap),
338 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMask),
339 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32XcptPFMatch),
340 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32Cr3TargetCount),
341 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32ExitCtls),
342 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrStoreCount),
343 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32ExitMsrLoadCount),
344 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32EntryCtls),
345 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32EntryMsrLoadCount),
346 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32EntryIntInfo),
347 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32EntryXcptErrCode),
348 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32EntryInstrLen),
349 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32TprThreshold),
350 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32ProcCtls2),
351 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32PleGap),
352 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32PleWindow),
353 /* 18-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
354 },
355 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
356 {
357 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32RoVmInstrError),
358 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitReason),
359 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntInfo),
360 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitIntErrCode),
361 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringInfo),
362 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32RoIdtVectoringErrCode),
363 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrLen),
364 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32RoExitInstrInfo),
365 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
366 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
367 /* 24-25 */ UINT16_MAX, UINT16_MAX
368 },
369 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
370 {
371 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsLimit),
372 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsLimit),
373 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsLimit),
374 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsLimit),
375 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsLimit),
376 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsLimit),
377 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrLimit),
378 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrLimit),
379 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGdtrLimit),
380 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIdtrLimit),
381 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u32GuestEsAttr),
382 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u32GuestCsAttr),
383 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSsAttr),
384 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u32GuestDsAttr),
385 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u32GuestFsAttr),
386 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u32GuestGsAttr),
387 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u32GuestLdtrAttr),
388 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u32GuestTrAttr),
389 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u32GuestIntrState),
390 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u32GuestActivityState),
391 /* 20 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSmBase),
392 /* 21 */ RT_UOFFSETOF(VMXVVMCS, u32GuestSysenterCS),
393 /* 22 */ RT_UOFFSETOF(VMXVVMCS, u32PreemptTimer),
394 /* 23-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX
395 },
396 /* VMX_VMCS_ENC_WIDTH_32BIT | VMX_VMCS_ENC_TYPE_HOST_STATE: */
397 {
398 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u32HostSysenterCs),
399 /* 1-8 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
400 /* 9-16 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
401 /* 17-24 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
402 /* 25 */ UINT16_MAX
403 },
404 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_CONTROL: */
405 {
406 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0Mask),
407 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4Mask),
408 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64Cr0ReadShadow),
409 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64Cr4ReadShadow),
410 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target0),
411 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target1),
412 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target2),
413 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64Cr3Target3),
414 /* 8-15 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
415 /* 16-23 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
416 /* 24-25 */ UINT16_MAX, UINT16_MAX
417 },
418 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_VMEXIT_INFO: */
419 {
420 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64RoExitQual),
421 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRcx),
422 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRsi),
423 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRdi),
424 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64RoIoRip),
425 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64RoGuestLinearAddr),
426 /* 6-13 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
427 /* 14-21 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
428 /* 22-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
429 },
430 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_GUEST_STATE: */
431 {
432 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr0),
433 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr3),
434 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCr4),
435 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64GuestEsBase),
436 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64GuestCsBase),
437 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSsBase),
438 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDsBase),
439 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64GuestFsBase),
440 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGsBase),
441 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64GuestLdtrBase),
442 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64GuestTrBase),
443 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64GuestGdtrBase),
444 /* 12 */ RT_UOFFSETOF(VMXVVMCS, u64GuestIdtrBase),
445 /* 13 */ RT_UOFFSETOF(VMXVVMCS, u64GuestDr7),
446 /* 14 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRsp),
447 /* 15 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRip),
448 /* 16 */ RT_UOFFSETOF(VMXVVMCS, u64GuestRFlags),
449 /* 17 */ RT_UOFFSETOF(VMXVVMCS, u64GuestPendingDbgXcpt),
450 /* 18 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEsp),
451 /* 19 */ RT_UOFFSETOF(VMXVVMCS, u64GuestSysenterEip),
452 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
453 },
454 /* VMX_VMCS_ENC_WIDTH_NATURAL | VMX_VMCS_ENC_TYPE_HOST_STATE: */
455 {
456 /* 0 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr0),
457 /* 1 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr3),
458 /* 2 */ RT_UOFFSETOF(VMXVVMCS, u64HostCr4),
459 /* 3 */ RT_UOFFSETOF(VMXVVMCS, u64HostFsBase),
460 /* 4 */ RT_UOFFSETOF(VMXVVMCS, u64HostGsBase),
461 /* 5 */ RT_UOFFSETOF(VMXVVMCS, u64HostTrBase),
462 /* 6 */ RT_UOFFSETOF(VMXVVMCS, u64HostGdtrBase),
463 /* 7 */ RT_UOFFSETOF(VMXVVMCS, u64HostIdtrBase),
464 /* 8 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEsp),
465 /* 9 */ RT_UOFFSETOF(VMXVVMCS, u64HostSysenterEip),
466 /* 10 */ RT_UOFFSETOF(VMXVVMCS, u64HostRsp),
467 /* 11 */ RT_UOFFSETOF(VMXVVMCS, u64HostRip),
468 /* 12-19 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX,
469 /* 20-25 */ UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX, UINT16_MAX
470 }
471};
472
473
474/**
475 * Returns whether the given VMCS field is valid and supported by our emulation.
476 *
477 * @param pVCpu The cross context virtual CPU structure.
478 * @param u64FieldEnc The VMCS field encoding.
479 *
480 * @remarks This takes into account the CPU features exposed to the guest.
481 */
482IEM_STATIC bool iemVmxIsVmcsFieldValid(PVMCPU pVCpu, uint64_t u64FieldEnc)
483{
484 uint32_t const uFieldEncHi = RT_HI_U32(u64FieldEnc);
485 uint32_t const uFieldEncLo = RT_LO_U32(u64FieldEnc);
486 if (!uFieldEncHi)
487 { /* likely */ }
488 else
489 return false;
490
491 PCCPUMFEATURES pFeat = IEM_GET_GUEST_CPU_FEATURES(pVCpu);
492 switch (uFieldEncLo)
493 {
494 /*
495 * 16-bit fields.
496 */
497 /* Control fields. */
498 case VMX_VMCS16_VPID: return pFeat->fVmxVpid;
499 case VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR: return pFeat->fVmxPostedInt;
500 case VMX_VMCS16_EPTP_INDEX: return pFeat->fVmxEptXcptVe;
501
502 /* Guest-state fields. */
503 case VMX_VMCS16_GUEST_ES_SEL:
504 case VMX_VMCS16_GUEST_CS_SEL:
505 case VMX_VMCS16_GUEST_SS_SEL:
506 case VMX_VMCS16_GUEST_DS_SEL:
507 case VMX_VMCS16_GUEST_FS_SEL:
508 case VMX_VMCS16_GUEST_GS_SEL:
509 case VMX_VMCS16_GUEST_LDTR_SEL:
510 case VMX_VMCS16_GUEST_TR_SEL: return true;
511 case VMX_VMCS16_GUEST_INTR_STATUS: return pFeat->fVmxVirtIntDelivery;
512 case VMX_VMCS16_GUEST_PML_INDEX: return pFeat->fVmxPml;
513
514 /* Host-state fields. */
515 case VMX_VMCS16_HOST_ES_SEL:
516 case VMX_VMCS16_HOST_CS_SEL:
517 case VMX_VMCS16_HOST_SS_SEL:
518 case VMX_VMCS16_HOST_DS_SEL:
519 case VMX_VMCS16_HOST_FS_SEL:
520 case VMX_VMCS16_HOST_GS_SEL:
521 case VMX_VMCS16_HOST_TR_SEL: return true;
522
523 /*
524 * 64-bit fields.
525 */
526 /* Control fields. */
527 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
528 case VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH:
529 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
530 case VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH: return pFeat->fVmxUseIoBitmaps;
531 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
532 case VMX_VMCS64_CTRL_MSR_BITMAP_HIGH: return pFeat->fVmxUseMsrBitmaps;
533 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
534 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH:
535 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
536 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH:
537 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
538 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH:
539 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
540 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH: return true;
541 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL:
542 case VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH: return pFeat->fVmxPml;
543 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
544 case VMX_VMCS64_CTRL_TSC_OFFSET_HIGH: return true;
545 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
546 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH: return pFeat->fVmxUseTprShadow;
547 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
548 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH: return pFeat->fVmxVirtApicAccess;
549 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL:
550 case VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH: return pFeat->fVmxPostedInt;
551 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
552 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH: return pFeat->fVmxVmFunc;
553 case VMX_VMCS64_CTRL_EPTP_FULL:
554 case VMX_VMCS64_CTRL_EPTP_HIGH: return pFeat->fVmxEpt;
555 case VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL:
556 case VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH:
557 case VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL:
558 case VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH:
559 case VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL:
560 case VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH:
561 case VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL:
562 case VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH: return pFeat->fVmxVirtIntDelivery;
563 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
564 case VMX_VMCS64_CTRL_EPTP_LIST_HIGH:
565 {
566 uint64_t const uVmFuncMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64VmFunc;
567 return RT_BOOL(RT_BF_GET(uVmFuncMsr, VMX_BF_VMFUNC_EPTP_SWITCHING));
568 }
569 case VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL:
570 case VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH:
571 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL:
572 case VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH: return pFeat->fVmxVmcsShadowing;
573 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL:
574 case VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH: return pFeat->fVmxEptXcptVe;
575 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL:
576 case VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH: return pFeat->fVmxXsavesXrstors;
577 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL:
578 case VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH: return false;
579 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL:
580 case VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH: return pFeat->fVmxUseTscScaling;
581
582 /* Read-only data fields. */
583 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL:
584 case VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH: return pFeat->fVmxEpt;
585
586 /* Guest-state fields. */
587 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
588 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH:
589 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
590 case VMX_VMCS64_GUEST_DEBUGCTL_HIGH: return true;
591 case VMX_VMCS64_GUEST_PAT_FULL:
592 case VMX_VMCS64_GUEST_PAT_HIGH: return pFeat->fVmxEntryLoadPatMsr || pFeat->fVmxExitSavePatMsr;
593 case VMX_VMCS64_GUEST_EFER_FULL:
594 case VMX_VMCS64_GUEST_EFER_HIGH: return pFeat->fVmxEntryLoadEferMsr || pFeat->fVmxExitSaveEferMsr;
595 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
596 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH: return false;
597 case VMX_VMCS64_GUEST_PDPTE0_FULL:
598 case VMX_VMCS64_GUEST_PDPTE0_HIGH:
599 case VMX_VMCS64_GUEST_PDPTE1_FULL:
600 case VMX_VMCS64_GUEST_PDPTE1_HIGH:
601 case VMX_VMCS64_GUEST_PDPTE2_FULL:
602 case VMX_VMCS64_GUEST_PDPTE2_HIGH:
603 case VMX_VMCS64_GUEST_PDPTE3_FULL:
604 case VMX_VMCS64_GUEST_PDPTE3_HIGH: return pFeat->fVmxEpt;
605 case VMX_VMCS64_GUEST_BNDCFGS_FULL:
606 case VMX_VMCS64_GUEST_BNDCFGS_HIGH: return false;
607
608 /* Host-state fields. */
609 case VMX_VMCS64_HOST_PAT_FULL:
610 case VMX_VMCS64_HOST_PAT_HIGH: return pFeat->fVmxExitLoadPatMsr;
611 case VMX_VMCS64_HOST_EFER_FULL:
612 case VMX_VMCS64_HOST_EFER_HIGH: return pFeat->fVmxExitLoadEferMsr;
613 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
614 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH: return false;
615
616 /*
617 * 32-bit fields.
618 */
619 /* Control fields. */
620 case VMX_VMCS32_CTRL_PIN_EXEC:
621 case VMX_VMCS32_CTRL_PROC_EXEC:
622 case VMX_VMCS32_CTRL_EXCEPTION_BITMAP:
623 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK:
624 case VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH:
625 case VMX_VMCS32_CTRL_CR3_TARGET_COUNT:
626 case VMX_VMCS32_CTRL_EXIT:
627 case VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT:
628 case VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT:
629 case VMX_VMCS32_CTRL_ENTRY:
630 case VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT:
631 case VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO:
632 case VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE:
633 case VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH: return true;
634 case VMX_VMCS32_CTRL_TPR_THRESHOLD: return pFeat->fVmxUseTprShadow;
635 case VMX_VMCS32_CTRL_PROC_EXEC2: return pFeat->fVmxSecondaryExecCtls;
636 case VMX_VMCS32_CTRL_PLE_GAP:
637 case VMX_VMCS32_CTRL_PLE_WINDOW: return pFeat->fVmxPauseLoopExit;
638
639 /* Read-only data fields. */
640 case VMX_VMCS32_RO_VM_INSTR_ERROR:
641 case VMX_VMCS32_RO_EXIT_REASON:
642 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
643 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE:
644 case VMX_VMCS32_RO_IDT_VECTORING_INFO:
645 case VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE:
646 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
647 case VMX_VMCS32_RO_EXIT_INSTR_INFO: return true;
648
649 /* Guest-state fields. */
650 case VMX_VMCS32_GUEST_ES_LIMIT:
651 case VMX_VMCS32_GUEST_CS_LIMIT:
652 case VMX_VMCS32_GUEST_SS_LIMIT:
653 case VMX_VMCS32_GUEST_DS_LIMIT:
654 case VMX_VMCS32_GUEST_FS_LIMIT:
655 case VMX_VMCS32_GUEST_GS_LIMIT:
656 case VMX_VMCS32_GUEST_LDTR_LIMIT:
657 case VMX_VMCS32_GUEST_TR_LIMIT:
658 case VMX_VMCS32_GUEST_GDTR_LIMIT:
659 case VMX_VMCS32_GUEST_IDTR_LIMIT:
660 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
661 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
662 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
663 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
664 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
665 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
666 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
667 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
668 case VMX_VMCS32_GUEST_INT_STATE:
669 case VMX_VMCS32_GUEST_ACTIVITY_STATE:
670 case VMX_VMCS32_GUEST_SMBASE:
671 case VMX_VMCS32_GUEST_SYSENTER_CS: return true;
672 case VMX_VMCS32_PREEMPT_TIMER_VALUE: return pFeat->fVmxPreemptTimer;
673
674 /* Host-state fields. */
675 case VMX_VMCS32_HOST_SYSENTER_CS: return true;
676
677 /*
678 * Natural-width fields.
679 */
680 /* Control fields. */
681 case VMX_VMCS_CTRL_CR0_MASK:
682 case VMX_VMCS_CTRL_CR4_MASK:
683 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
684 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
685 case VMX_VMCS_CTRL_CR3_TARGET_VAL0:
686 case VMX_VMCS_CTRL_CR3_TARGET_VAL1:
687 case VMX_VMCS_CTRL_CR3_TARGET_VAL2:
688 case VMX_VMCS_CTRL_CR3_TARGET_VAL3: return true;
689
690 /* Read-only data fields. */
691 case VMX_VMCS_RO_EXIT_QUALIFICATION:
692 case VMX_VMCS_RO_IO_RCX:
693 case VMX_VMCS_RO_IO_RSX:
694 case VMX_VMCS_RO_IO_RDI:
695 case VMX_VMCS_RO_IO_RIP:
696 case VMX_VMCS_RO_GUEST_LINEAR_ADDR: return true;
697
698 /* Guest-state fields. */
699 case VMX_VMCS_GUEST_CR0:
700 case VMX_VMCS_GUEST_CR3:
701 case VMX_VMCS_GUEST_CR4:
702 case VMX_VMCS_GUEST_ES_BASE:
703 case VMX_VMCS_GUEST_CS_BASE:
704 case VMX_VMCS_GUEST_SS_BASE:
705 case VMX_VMCS_GUEST_DS_BASE:
706 case VMX_VMCS_GUEST_FS_BASE:
707 case VMX_VMCS_GUEST_GS_BASE:
708 case VMX_VMCS_GUEST_LDTR_BASE:
709 case VMX_VMCS_GUEST_TR_BASE:
710 case VMX_VMCS_GUEST_GDTR_BASE:
711 case VMX_VMCS_GUEST_IDTR_BASE:
712 case VMX_VMCS_GUEST_DR7:
713 case VMX_VMCS_GUEST_RSP:
714 case VMX_VMCS_GUEST_RIP:
715 case VMX_VMCS_GUEST_RFLAGS:
716 case VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS:
717 case VMX_VMCS_GUEST_SYSENTER_ESP:
718 case VMX_VMCS_GUEST_SYSENTER_EIP: return true;
719
720 /* Host-state fields. */
721 case VMX_VMCS_HOST_CR0:
722 case VMX_VMCS_HOST_CR3:
723 case VMX_VMCS_HOST_CR4:
724 case VMX_VMCS_HOST_FS_BASE:
725 case VMX_VMCS_HOST_GS_BASE:
726 case VMX_VMCS_HOST_TR_BASE:
727 case VMX_VMCS_HOST_GDTR_BASE:
728 case VMX_VMCS_HOST_IDTR_BASE:
729 case VMX_VMCS_HOST_SYSENTER_ESP:
730 case VMX_VMCS_HOST_SYSENTER_EIP:
731 case VMX_VMCS_HOST_RSP:
732 case VMX_VMCS_HOST_RIP: return true;
733 }
734
735 return false;
736}
737
738
739/**
740 * Gets a host selector from the VMCS.
741 *
742 * @param pVmcs Pointer to the virtual VMCS.
743 * @param iSelReg The index of the segment register (X86_SREG_XXX).
744 */
745DECLINLINE(RTSEL) iemVmxVmcsGetHostSelReg(PCVMXVVMCS pVmcs, uint8_t iSegReg)
746{
747 Assert(iSegReg < X86_SREG_COUNT);
748 RTSEL HostSel;
749 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
750 uint8_t const uType = VMX_VMCS_ENC_TYPE_HOST_STATE;
751 uint8_t const uWidthType = (uWidth << 2) | uType;
752 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_HOST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
753 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
754 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
755 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
756 uint8_t const *pbField = pbVmcs + offField;
757 HostSel = *(uint16_t *)pbField;
758 return HostSel;
759}
760
761
762/**
763 * Sets a guest segment register in the VMCS.
764 *
765 * @param pVmcs Pointer to the virtual VMCS.
766 * @param iSegReg The index of the segment register (X86_SREG_XXX).
767 * @param pSelReg Pointer to the segment register.
768 */
769IEM_STATIC void iemVmxVmcsSetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCCPUMSELREG pSelReg)
770{
771 Assert(pSelReg);
772 Assert(iSegReg < X86_SREG_COUNT);
773
774 /* Selector. */
775 {
776 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
777 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
778 uint8_t const uWidthType = (uWidth << 2) | uType;
779 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
780 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
781 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
782 uint8_t *pbVmcs = (uint8_t *)pVmcs;
783 uint8_t *pbField = pbVmcs + offField;
784 *(uint16_t *)pbField = pSelReg->Sel;
785 }
786
787 /* Limit. */
788 {
789 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
790 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
791 uint8_t const uWidthType = (uWidth << 2) | uType;
792 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
793 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
794 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
795 uint8_t *pbVmcs = (uint8_t *)pVmcs;
796 uint8_t *pbField = pbVmcs + offField;
797 *(uint32_t *)pbField = pSelReg->u32Limit;
798 }
799
800 /* Base. */
801 {
802 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
803 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
804 uint8_t const uWidthType = (uWidth << 2) | uType;
805 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
806 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
807 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
808 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
809 uint8_t const *pbField = pbVmcs + offField;
810 *(uint64_t *)pbField = pSelReg->u64Base;
811 }
812
813 /* Attributes. */
814 {
815 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
816 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
817 | X86DESCATTR_UNUSABLE;
818 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
819 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
820 uint8_t const uWidthType = (uWidth << 2) | uType;
821 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
822 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
823 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
824 uint8_t *pbVmcs = (uint8_t *)pVmcs;
825 uint8_t *pbField = pbVmcs + offField;
826 *(uint32_t *)pbField = pSelReg->Attr.u & fValidAttrMask;
827 }
828}
829
830
831/**
832 * Gets a guest segment register from the VMCS.
833 *
834 * @returns VBox status code.
835 * @param pVmcs Pointer to the virtual VMCS.
836 * @param iSegReg The index of the segment register (X86_SREG_XXX).
837 * @param pSelReg Where to store the segment register (only updated when
838 * VINF_SUCCESS is returned).
839 *
840 * @remarks Warning! This does not validate the contents of the retrieved segment
841 * register.
842 */
843IEM_STATIC int iemVmxVmcsGetGuestSegReg(PCVMXVVMCS pVmcs, uint8_t iSegReg, PCPUMSELREG pSelReg)
844{
845 Assert(pSelReg);
846 Assert(iSegReg < X86_SREG_COUNT);
847
848 /* Selector. */
849 uint16_t u16Sel;
850 {
851 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_16BIT;
852 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
853 uint8_t const uWidthType = (uWidth << 2) | uType;
854 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS16_GUEST_ES_SEL, VMX_BF_VMCS_ENC_INDEX);
855 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
856 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
857 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
858 uint8_t const *pbField = pbVmcs + offField;
859 u16Sel = *(uint16_t *)pbField;
860 }
861
862 /* Limit. */
863 uint32_t u32Limit;
864 {
865 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
866 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
867 uint8_t const uWidthType = (uWidth << 2) | uType;
868 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_LIMIT, VMX_BF_VMCS_ENC_INDEX);
869 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
870 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
871 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
872 uint8_t const *pbField = pbVmcs + offField;
873 u32Limit = *(uint32_t *)pbField;
874 }
875
876 /* Base. */
877 uint64_t u64Base;
878 {
879 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
880 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
881 uint8_t const uWidthType = (uWidth << 2) | uType;
882 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS_GUEST_ES_BASE, VMX_BF_VMCS_ENC_INDEX);
883 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
884 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
885 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
886 uint8_t const *pbField = pbVmcs + offField;
887 u64Base = *(uint64_t *)pbField;
888 /** @todo NSTVMX: Should we zero out high bits here for 32-bit virtual CPUs? */
889 }
890
891 /* Attributes. */
892 uint32_t u32Attr;
893 {
894 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_32BIT;
895 uint8_t const uType = VMX_VMCS_ENC_TYPE_GUEST_STATE;
896 uint8_t const uWidthType = (uWidth << 2) | uType;
897 uint8_t const uIndex = iSegReg + RT_BF_GET(VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, VMX_BF_VMCS_ENC_INDEX);
898 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_3);
899 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
900 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
901 uint8_t const *pbField = pbVmcs + offField;
902 u32Attr = *(uint32_t *)pbField;
903 }
904
905 pSelReg->Sel = u16Sel;
906 pSelReg->ValidSel = u16Sel;
907 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
908 pSelReg->u32Limit = u32Limit;
909 pSelReg->u64Base = u64Base;
910 pSelReg->Attr.u = u32Attr;
911 return VINF_SUCCESS;
912}
913
914
915/**
916 * Gets a CR3 target value from the VMCS.
917 *
918 * @returns VBox status code.
919 * @param pVmcs Pointer to the virtual VMCS.
920 * @param idxCr3Target The index of the CR3-target value to retrieve.
921 * @param puValue Where to store the CR3-target value.
922 */
923IEM_STATIC uint64_t iemVmxVmcsGetCr3TargetValue(PCVMXVVMCS pVmcs, uint8_t idxCr3Target)
924{
925 Assert(idxCr3Target < VMX_V_CR3_TARGET_COUNT);
926 uint8_t const uWidth = VMX_VMCS_ENC_WIDTH_NATURAL;
927 uint8_t const uType = VMX_VMCS_ENC_TYPE_CONTROL;
928 uint8_t const uWidthType = (uWidth << 2) | uType;
929 uint8_t const uIndex = idxCr3Target + RT_BF_GET(VMX_VMCS_CTRL_CR3_TARGET_VAL0, VMX_BF_VMCS_ENC_INDEX);
930 Assert(uIndex <= VMX_V_VMCS_MAX_INDEX);
931 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
932 uint8_t const *pbVmcs = (uint8_t *)pVmcs;
933 uint8_t const *pbField = pbVmcs + offField;
934 uint64_t const uCr3TargetValue = *(uint64_t *)pbField;
935 return uCr3TargetValue;
936}
937
938
939/**
940 * Converts an IEM exception event type to a VMX event type.
941 *
942 * @returns The VMX event type.
943 * @param uVector The interrupt / exception vector.
944 * @param fFlags The IEM event flag (see IEM_XCPT_FLAGS_XXX).
945 */
946DECLINLINE(uint8_t) iemVmxGetEventType(uint32_t uVector, uint32_t fFlags)
947{
948 /* Paranoia (callers may use these interchangeably). */
949 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_IDT_VECTORING_INFO_TYPE_NMI);
950 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT);
951 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
952 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT);
953 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_IDT_VECTORING_INFO_TYPE_SW_INT);
954 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
955 AssertCompile(VMX_EXIT_INT_INFO_TYPE_NMI == VMX_ENTRY_INT_INFO_TYPE_NMI);
956 AssertCompile(VMX_EXIT_INT_INFO_TYPE_HW_XCPT == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT);
957 AssertCompile(VMX_EXIT_INT_INFO_TYPE_EXT_INT == VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
958 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT);
959 AssertCompile(VMX_EXIT_INT_INFO_TYPE_SW_INT == VMX_ENTRY_INT_INFO_TYPE_SW_INT);
960 AssertCompile(VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT);
961
962 if (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
963 {
964 if (uVector == X86_XCPT_NMI)
965 return VMX_EXIT_INT_INFO_TYPE_NMI;
966 return VMX_EXIT_INT_INFO_TYPE_HW_XCPT;
967 }
968
969 if (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
970 {
971 if (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
972 return VMX_EXIT_INT_INFO_TYPE_SW_XCPT;
973 if (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
974 return VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT;
975 return VMX_EXIT_INT_INFO_TYPE_SW_INT;
976 }
977
978 Assert(fFlags & IEM_XCPT_FLAGS_T_EXT_INT);
979 return VMX_EXIT_INT_INFO_TYPE_EXT_INT;
980}
981
982
983/**
984 * Sets the VM-exit qualification VMCS field.
985 *
986 * @param pVCpu The cross context virtual CPU structure.
987 * @param uExitQual The VM-exit qualification.
988 */
989DECL_FORCE_INLINE(void) iemVmxVmcsSetExitQual(PVMCPU pVCpu, uint64_t uExitQual)
990{
991 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
992 pVmcs->u64RoExitQual.u = uExitQual;
993}
994
995
996/**
997 * Sets the VM-exit interruption information field.
998 *
999 * @param pVCpu The cross context virtual CPU structure.
1000 * @param uExitQual The VM-exit interruption information.
1001 */
1002DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntInfo(PVMCPU pVCpu, uint32_t uExitIntInfo)
1003{
1004 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1005 pVmcs->u32RoExitIntInfo = uExitIntInfo;
1006}
1007
1008
1009/**
1010 * Sets the VM-exit interruption error code.
1011 *
1012 * @param pVCpu The cross context virtual CPU structure.
1013 * @param uErrCode The error code.
1014 */
1015DECL_FORCE_INLINE(void) iemVmxVmcsSetExitIntErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1016{
1017 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1018 pVmcs->u32RoExitIntErrCode = uErrCode;
1019}
1020
1021
1022/**
1023 * Sets the IDT-vectoring information field.
1024 *
1025 * @param pVCpu The cross context virtual CPU structure.
1026 * @param uIdtVectorInfo The IDT-vectoring information.
1027 */
1028DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringInfo(PVMCPU pVCpu, uint32_t uIdtVectorInfo)
1029{
1030 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1031 pVmcs->u32RoIdtVectoringInfo = uIdtVectorInfo;
1032}
1033
1034
1035/**
1036 * Sets the IDT-vectoring error code field.
1037 *
1038 * @param pVCpu The cross context virtual CPU structure.
1039 * @param uErrCode The error code.
1040 */
1041DECL_FORCE_INLINE(void) iemVmxVmcsSetIdtVectoringErrCode(PVMCPU pVCpu, uint32_t uErrCode)
1042{
1043 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1044 pVmcs->u32RoIdtVectoringErrCode = uErrCode;
1045}
1046
1047
1048/**
1049 * Sets the VM-exit guest-linear address VMCS field.
1050 *
1051 * @param pVCpu The cross context virtual CPU structure.
1052 * @param uGuestLinearAddr The VM-exit guest-linear address.
1053 */
1054DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestLinearAddr(PVMCPU pVCpu, uint64_t uGuestLinearAddr)
1055{
1056 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1057 pVmcs->u64RoGuestLinearAddr.u = uGuestLinearAddr;
1058}
1059
1060
1061/**
1062 * Sets the VM-exit guest-physical address VMCS field.
1063 *
1064 * @param pVCpu The cross context virtual CPU structure.
1065 * @param uGuestPhysAddr The VM-exit guest-physical address.
1066 */
1067DECL_FORCE_INLINE(void) iemVmxVmcsSetExitGuestPhysAddr(PVMCPU pVCpu, uint64_t uGuestPhysAddr)
1068{
1069 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1070 pVmcs->u64RoGuestPhysAddr.u = uGuestPhysAddr;
1071}
1072
1073
1074/**
1075 * Sets the VM-exit instruction length VMCS field.
1076 *
1077 * @param pVCpu The cross context virtual CPU structure.
1078 * @param cbInstr The VM-exit instruction length in bytes.
1079 *
1080 * @remarks Callers may clear this field to 0. Hence, this function does not check
1081 * the validity of the instruction length.
1082 */
1083DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrLen(PVMCPU pVCpu, uint32_t cbInstr)
1084{
1085 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1086 pVmcs->u32RoExitInstrLen = cbInstr;
1087}
1088
1089
1090/**
1091 * Sets the VM-exit instruction info. VMCS field.
1092 *
1093 * @param pVCpu The cross context virtual CPU structure.
1094 * @param uExitInstrInfo The VM-exit instruction information.
1095 */
1096DECL_FORCE_INLINE(void) iemVmxVmcsSetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitInstrInfo)
1097{
1098 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1099 pVmcs->u32RoExitInstrInfo = uExitInstrInfo;
1100}
1101
1102
1103/**
1104 * Implements VMSucceed for VMX instruction success.
1105 *
1106 * @param pVCpu The cross context virtual CPU structure.
1107 */
1108DECL_FORCE_INLINE(void) iemVmxVmSucceed(PVMCPU pVCpu)
1109{
1110 return CPUMSetGuestVmxVmSucceed(IEM_GET_CTX(pVCpu));
1111}
1112
1113
1114/**
1115 * Implements VMFailInvalid for VMX instruction failure.
1116 *
1117 * @param pVCpu The cross context virtual CPU structure.
1118 */
1119DECL_FORCE_INLINE(void) iemVmxVmFailInvalid(PVMCPU pVCpu)
1120{
1121 return CPUMSetGuestVmxVmFailInvalid(IEM_GET_CTX(pVCpu));
1122}
1123
1124
1125/**
1126 * Implements VMFailValid for VMX instruction failure.
1127 *
1128 * @param pVCpu The cross context virtual CPU structure.
1129 * @param enmInsErr The VM instruction error.
1130 */
1131DECL_FORCE_INLINE(void) iemVmxVmFailValid(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1132{
1133 return CPUMSetGuestVmxVmFailValid(IEM_GET_CTX(pVCpu), enmInsErr);
1134}
1135
1136
1137/**
1138 * Implements VMFail for VMX instruction failure.
1139 *
1140 * @param pVCpu The cross context virtual CPU structure.
1141 * @param enmInsErr The VM instruction error.
1142 */
1143DECL_FORCE_INLINE(void) iemVmxVmFail(PVMCPU pVCpu, VMXINSTRERR enmInsErr)
1144{
1145 return CPUMSetGuestVmxVmFail(IEM_GET_CTX(pVCpu), enmInsErr);
1146}
1147
1148
1149/**
1150 * Checks if the given auto-load/store MSR area count is valid for the
1151 * implementation.
1152 *
1153 * @returns @c true if it's within the valid limit, @c false otherwise.
1154 * @param pVCpu The cross context virtual CPU structure.
1155 * @param uMsrCount The MSR area count to check.
1156 */
1157DECL_FORCE_INLINE(bool) iemVmxIsAutoMsrCountValid(PVMCPU pVCpu, uint32_t uMsrCount)
1158{
1159 uint64_t const u64VmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
1160 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(u64VmxMiscMsr);
1161 Assert(cMaxSupportedMsrs <= VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
1162 if (uMsrCount <= cMaxSupportedMsrs)
1163 return true;
1164 return false;
1165}
1166
1167
1168/**
1169 * Flushes the current VMCS contents back to guest memory.
1170 *
1171 * @returns VBox status code.
1172 * @param pVCpu The cross context virtual CPU structure.
1173 */
1174DECL_FORCE_INLINE(int) iemVmxCommitCurrentVmcsToMemory(PVMCPU pVCpu)
1175{
1176 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
1177 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), IEM_VMX_GET_CURRENT_VMCS(pVCpu),
1178 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), sizeof(VMXVVMCS));
1179 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
1180 return rc;
1181}
1182
1183
1184/**
1185 * Implements VMSucceed for the VMREAD instruction and increments the guest RIP.
1186 *
1187 * @param pVCpu The cross context virtual CPU structure.
1188 */
1189DECL_FORCE_INLINE(void) iemVmxVmreadSuccess(PVMCPU pVCpu, uint8_t cbInstr)
1190{
1191 iemVmxVmSucceed(pVCpu);
1192 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1193}
1194
1195
1196/**
1197 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1198 * nested-guest.
1199 *
1200 * @param iSegReg The segment index (X86_SREG_XXX).
1201 */
1202IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBase(unsigned iSegReg)
1203{
1204 switch (iSegReg)
1205 {
1206 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseCs;
1207 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseDs;
1208 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseEs;
1209 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseFs;
1210 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseGs;
1211 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseSs;
1212 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_1);
1213 }
1214}
1215
1216
1217/**
1218 * Gets the instruction diagnostic for segment base checks during VM-entry of a
1219 * nested-guest that is in Virtual-8086 mode.
1220 *
1221 * @param iSegReg The segment index (X86_SREG_XXX).
1222 */
1223IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegBaseV86(unsigned iSegReg)
1224{
1225 switch (iSegReg)
1226 {
1227 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegBaseV86Cs;
1228 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ds;
1229 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegBaseV86Es;
1230 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegBaseV86Fs;
1231 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegBaseV86Gs;
1232 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegBaseV86Ss;
1233 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_2);
1234 }
1235}
1236
1237
1238/**
1239 * Gets the instruction diagnostic for segment limit checks during VM-entry of a
1240 * nested-guest that is in Virtual-8086 mode.
1241 *
1242 * @param iSegReg The segment index (X86_SREG_XXX).
1243 */
1244IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegLimitV86(unsigned iSegReg)
1245{
1246 switch (iSegReg)
1247 {
1248 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegLimitV86Cs;
1249 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ds;
1250 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegLimitV86Es;
1251 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegLimitV86Fs;
1252 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegLimitV86Gs;
1253 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegLimitV86Ss;
1254 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_3);
1255 }
1256}
1257
1258
1259/**
1260 * Gets the instruction diagnostic for segment attribute checks during VM-entry of a
1261 * nested-guest that is in Virtual-8086 mode.
1262 *
1263 * @param iSegReg The segment index (X86_SREG_XXX).
1264 */
1265IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrV86(unsigned iSegReg)
1266{
1267 switch (iSegReg)
1268 {
1269 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrV86Cs;
1270 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ds;
1271 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrV86Es;
1272 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrV86Fs;
1273 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrV86Gs;
1274 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrV86Ss;
1275 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_4);
1276 }
1277}
1278
1279
1280/**
1281 * Gets the instruction diagnostic for segment attributes reserved bits failure
1282 * during VM-entry of a nested-guest.
1283 *
1284 * @param iSegReg The segment index (X86_SREG_XXX).
1285 */
1286IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrRsvd(unsigned iSegReg)
1287{
1288 switch (iSegReg)
1289 {
1290 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdCs;
1291 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdDs;
1292 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrRsvdEs;
1293 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdFs;
1294 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdGs;
1295 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrRsvdSs;
1296 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_5);
1297 }
1298}
1299
1300
1301/**
1302 * Gets the instruction diagnostic for segment attributes descriptor-type
1303 * (code/segment or system) failure during VM-entry of a nested-guest.
1304 *
1305 * @param iSegReg The segment index (X86_SREG_XXX).
1306 */
1307IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDescType(unsigned iSegReg)
1308{
1309 switch (iSegReg)
1310 {
1311 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs;
1312 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs;
1313 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs;
1314 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs;
1315 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs;
1316 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs;
1317 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_6);
1318 }
1319}
1320
1321
1322/**
1323 * Gets the instruction diagnostic for segment attributes descriptor-type
1324 * (code/segment or system) failure during VM-entry of a nested-guest.
1325 *
1326 * @param iSegReg The segment index (X86_SREG_XXX).
1327 */
1328IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrPresent(unsigned iSegReg)
1329{
1330 switch (iSegReg)
1331 {
1332 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrPresentCs;
1333 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrPresentDs;
1334 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrPresentEs;
1335 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrPresentFs;
1336 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrPresentGs;
1337 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrPresentSs;
1338 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_7);
1339 }
1340}
1341
1342
1343/**
1344 * Gets the instruction diagnostic for segment attribute granularity failure during
1345 * VM-entry of a nested-guest.
1346 *
1347 * @param iSegReg The segment index (X86_SREG_XXX).
1348 */
1349IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrGran(unsigned iSegReg)
1350{
1351 switch (iSegReg)
1352 {
1353 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrGranCs;
1354 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrGranDs;
1355 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrGranEs;
1356 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrGranFs;
1357 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrGranGs;
1358 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrGranSs;
1359 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_8);
1360 }
1361}
1362
1363/**
1364 * Gets the instruction diagnostic for segment attribute DPL/RPL failure during
1365 * VM-entry of a nested-guest.
1366 *
1367 * @param iSegReg The segment index (X86_SREG_XXX).
1368 */
1369IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrDplRpl(unsigned iSegReg)
1370{
1371 switch (iSegReg)
1372 {
1373 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplCs;
1374 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplDs;
1375 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrDplRplEs;
1376 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplFs;
1377 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplGs;
1378 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrDplRplSs;
1379 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_9);
1380 }
1381}
1382
1383
1384/**
1385 * Gets the instruction diagnostic for segment attribute type accessed failure
1386 * during VM-entry of a nested-guest.
1387 *
1388 * @param iSegReg The segment index (X86_SREG_XXX).
1389 */
1390IEM_STATIC VMXVDIAG iemVmxGetDiagVmentrySegAttrTypeAcc(unsigned iSegReg)
1391{
1392 switch (iSegReg)
1393 {
1394 case X86_SREG_CS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs;
1395 case X86_SREG_DS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs;
1396 case X86_SREG_ES: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs;
1397 case X86_SREG_FS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs;
1398 case X86_SREG_GS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs;
1399 case X86_SREG_SS: return kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs;
1400 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_10);
1401 }
1402}
1403
1404
1405/**
1406 * Gets the instruction diagnostic for guest CR3 referenced PDPTE reserved bits
1407 * failure during VM-entry of a nested-guest.
1408 *
1409 * @param iSegReg The PDPTE entry index.
1410 */
1411IEM_STATIC VMXVDIAG iemVmxGetDiagVmentryPdpteRsvd(unsigned iPdpte)
1412{
1413 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1414 switch (iPdpte)
1415 {
1416 case 0: return kVmxVDiag_Vmentry_GuestPdpte0Rsvd;
1417 case 1: return kVmxVDiag_Vmentry_GuestPdpte1Rsvd;
1418 case 2: return kVmxVDiag_Vmentry_GuestPdpte2Rsvd;
1419 case 3: return kVmxVDiag_Vmentry_GuestPdpte3Rsvd;
1420 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_11);
1421 }
1422}
1423
1424
1425/**
1426 * Gets the instruction diagnostic for host CR3 referenced PDPTE reserved bits
1427 * failure during VM-exit of a nested-guest.
1428 *
1429 * @param iSegReg The PDPTE entry index.
1430 */
1431IEM_STATIC VMXVDIAG iemVmxGetDiagVmexitPdpteRsvd(unsigned iPdpte)
1432{
1433 Assert(iPdpte < X86_PG_PAE_PDPE_ENTRIES);
1434 switch (iPdpte)
1435 {
1436 case 0: return kVmxVDiag_Vmexit_HostPdpte0Rsvd;
1437 case 1: return kVmxVDiag_Vmexit_HostPdpte1Rsvd;
1438 case 2: return kVmxVDiag_Vmexit_HostPdpte2Rsvd;
1439 case 3: return kVmxVDiag_Vmexit_HostPdpte3Rsvd;
1440 IEM_NOT_REACHED_DEFAULT_CASE_RET2(kVmxVDiag_Ipe_12);
1441 }
1442}
1443
1444
1445/**
1446 * Masks the nested-guest CR0/CR4 mask subjected to the corresponding guest/host
1447 * mask and the read-shadow (CR0/CR4 read).
1448 *
1449 * @returns The masked CR0/CR4.
1450 * @param pVCpu The cross context virtual CPU structure.
1451 * @param iCrReg The control register (either CR0 or CR4).
1452 * @param uGuestCrX The current guest CR0 or guest CR4.
1453 */
1454IEM_STATIC uint64_t iemVmxMaskCr0CR4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
1455{
1456 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
1457 Assert(iCrReg == 0 || iCrReg == 4);
1458
1459 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1460 Assert(pVmcs);
1461
1462 /*
1463 * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
1464 * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
1465 * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
1466 *
1467 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
1468 */
1469 uint64_t fGstHostMask;
1470 uint64_t fReadShadow;
1471 if (iCrReg == 0)
1472 {
1473 fGstHostMask = pVmcs->u64Cr0Mask.u;
1474 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
1475 }
1476 else
1477 {
1478 fGstHostMask = pVmcs->u64Cr4Mask.u;
1479 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
1480 }
1481
1482 uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
1483 return fMaskedCrX;
1484}
1485
1486
1487/**
1488 * Saves the guest control registers, debug registers and some MSRs are part of
1489 * VM-exit.
1490 *
1491 * @param pVCpu The cross context virtual CPU structure.
1492 */
1493IEM_STATIC void iemVmxVmexitSaveGuestControlRegsMsrs(PVMCPU pVCpu)
1494{
1495 /*
1496 * Saves the guest control registers, debug registers and some MSRs.
1497 * See Intel spec. 27.3.1 "Saving Control Registers, Debug Registers and MSRs".
1498 */
1499 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1500
1501 /* Save control registers. */
1502 pVmcs->u64GuestCr0.u = pVCpu->cpum.GstCtx.cr0;
1503 pVmcs->u64GuestCr3.u = pVCpu->cpum.GstCtx.cr3;
1504 pVmcs->u64GuestCr4.u = pVCpu->cpum.GstCtx.cr4;
1505
1506 /* Save SYSENTER CS, ESP, EIP. */
1507 pVmcs->u32GuestSysenterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1508 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1509 {
1510 pVmcs->u64GuestSysenterEsp.u = pVCpu->cpum.GstCtx.SysEnter.esp;
1511 pVmcs->u64GuestSysenterEip.u = pVCpu->cpum.GstCtx.SysEnter.eip;
1512 }
1513 else
1514 {
1515 pVmcs->u64GuestSysenterEsp.s.Lo = pVCpu->cpum.GstCtx.SysEnter.esp;
1516 pVmcs->u64GuestSysenterEip.s.Lo = pVCpu->cpum.GstCtx.SysEnter.eip;
1517 }
1518
1519 /* Save debug registers (DR7 and IA32_DEBUGCTL MSR). */
1520 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG)
1521 {
1522 pVmcs->u64GuestDr7.u = pVCpu->cpum.GstCtx.dr[7];
1523 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
1524 }
1525
1526 /* Save PAT MSR. */
1527 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR)
1528 pVmcs->u64GuestPatMsr.u = pVCpu->cpum.GstCtx.msrPAT;
1529
1530 /* Save EFER MSR. */
1531 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR)
1532 pVmcs->u64GuestEferMsr.u = pVCpu->cpum.GstCtx.msrEFER;
1533
1534 /* We don't support clearing IA32_BNDCFGS MSR yet. */
1535 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR));
1536
1537 /* Nothing to do for SMBASE register - We don't support SMM yet. */
1538}
1539
1540
1541/**
1542 * Saves the guest force-flags in preparation of entering the nested-guest.
1543 *
1544 * @param pVCpu The cross context virtual CPU structure.
1545 */
1546IEM_STATIC void iemVmxVmentrySaveNmiBlockingFF(PVMCPU pVCpu)
1547{
1548 /* We shouldn't be called multiple times during VM-entry. */
1549 Assert(pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions == 0);
1550
1551 /* MTF should not be set outside VMX non-root mode. */
1552 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
1553
1554 /*
1555 * Preserve the required force-flags.
1556 *
1557 * We cache and clear force-flags that would affect the execution of the
1558 * nested-guest. Cached flags are then restored while returning to the guest
1559 * if necessary.
1560 *
1561 * - VMCPU_FF_INHIBIT_INTERRUPTS need not be cached as it only affects
1562 * interrupts until the completion of the current VMLAUNCH/VMRESUME
1563 * instruction. Interrupt inhibition for any nested-guest instruction
1564 * is supplied by the guest-interruptibility state VMCS field and will
1565 * be set up as part of loading the guest state.
1566 *
1567 * - VMCPU_FF_BLOCK_NMIS needs to be cached as VM-exits caused before
1568 * successful VM-entry (due to invalid guest-state) need to continue
1569 * blocking NMIs if it was in effect before VM-entry.
1570 *
1571 * - MTF need not be preserved as it's used only in VMX non-root mode and
1572 * is supplied through the VM-execution controls.
1573 *
1574 * The remaining FFs (e.g. timers, APIC updates) can stay in place so that
1575 * we will be able to generate interrupts that may cause VM-exits for
1576 * the nested-guest.
1577 */
1578 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
1579}
1580
1581
1582/**
1583 * Restores the guest force-flags in preparation of exiting the nested-guest.
1584 *
1585 * @param pVCpu The cross context virtual CPU structure.
1586 */
1587IEM_STATIC void iemVmxVmexitRestoreNmiBlockingFF(PVMCPU pVCpu)
1588{
1589 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
1590 {
1591 VMCPU_FF_SET_MASK(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
1592 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
1593 }
1594}
1595
1596
1597/**
1598 * Perform a VMX transition updated PGM, IEM and CPUM.
1599 *
1600 * @param pVCpu The cross context virtual CPU structure.
1601 */
1602IEM_STATIC int iemVmxWorldSwitch(PVMCPU pVCpu)
1603{
1604 /*
1605 * Inform PGM about paging mode changes.
1606 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
1607 * see comment in iemMemPageTranslateAndCheckAccess().
1608 */
1609 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1610# ifdef IN_RING3
1611 Assert(rc != VINF_PGM_CHANGE_MODE);
1612# endif
1613 AssertRCReturn(rc, rc);
1614
1615 /* Inform CPUM (recompiler), can later be removed. */
1616 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1617
1618 /*
1619 * Flush the TLB with new CR3. This is required in case the PGM mode change
1620 * above doesn't actually change anything.
1621 */
1622 if (rc == VINF_SUCCESS)
1623 {
1624 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
1625 AssertRCReturn(rc, rc);
1626 }
1627
1628 /* Re-initialize IEM cache/state after the drastic mode switch. */
1629 iemReInitExec(pVCpu);
1630 return rc;
1631}
1632
1633
1634/**
1635 * Calculates the current VMX-preemption timer value.
1636 *
1637 * @param pVCpu The cross context virtual CPU structure.
1638 */
1639IEM_STATIC uint32_t iemVmxCalcPreemptTimer(PVMCPU pVCpu)
1640{
1641 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1642 Assert(pVmcs);
1643
1644 /*
1645 * Assume the following:
1646 * PreemptTimerShift = 5
1647 * VmcsPreemptTimer = 2 (i.e. need to decrement by 1 every 2 * RT_BIT(5) = 20000 TSC ticks)
1648 * VmentryTick = 50000 (TSC at time of VM-entry)
1649 *
1650 * CurTick Delta PreemptTimerVal
1651 * ----------------------------------
1652 * 60000 10000 2
1653 * 80000 30000 1
1654 * 90000 40000 0 -> VM-exit.
1655 *
1656 * If Delta >= VmcsPreemptTimer * RT_BIT(PreemptTimerShift) cause a VMX-preemption timer VM-exit.
1657 * The saved VMX-preemption timer value is calculated as follows:
1658 * PreemptTimerVal = VmcsPreemptTimer - (Delta / (VmcsPreemptTimer * RT_BIT(PreemptTimerShift)))
1659 * E.g.:
1660 * Delta = 10000
1661 * Tmp = 10000 / (2 * 10000) = 0.5
1662 * NewPt = 2 - 0.5 = 2
1663 * Delta = 30000
1664 * Tmp = 30000 / (2 * 10000) = 1.5
1665 * NewPt = 2 - 1.5 = 1
1666 * Delta = 40000
1667 * Tmp = 40000 / 20000 = 2
1668 * NewPt = 2 - 2 = 0
1669 */
1670 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
1671 uint64_t const uCurTick = TMCpuTickGetNoCheck(pVCpu);
1672 uint64_t const uVmentryTick = pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick;
1673 uint64_t const uDelta = uCurTick - uVmentryTick;
1674 uint32_t const uVmcsPreemptVal = pVmcs->u32PreemptTimer;
1675 uint32_t const uPreemptTimer = uVmcsPreemptVal
1676 - ASMDivU64ByU32RetU32(uDelta, uVmcsPreemptVal * RT_BIT(VMX_V_PREEMPT_TIMER_SHIFT));
1677 return uPreemptTimer;
1678}
1679
1680
1681/**
1682 * Saves guest segment registers, GDTR, IDTR, LDTR, TR as part of VM-exit.
1683 *
1684 * @param pVCpu The cross context virtual CPU structure.
1685 */
1686IEM_STATIC void iemVmxVmexitSaveGuestSegRegs(PVMCPU pVCpu)
1687{
1688 /*
1689 * Save guest segment registers, GDTR, IDTR, LDTR, TR.
1690 * See Intel spec 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
1691 */
1692 /* CS, SS, ES, DS, FS, GS. */
1693 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1694 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
1695 {
1696 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1697 if (!pSelReg->Attr.n.u1Unusable)
1698 iemVmxVmcsSetGuestSegReg(pVmcs, iSegReg, pSelReg);
1699 else
1700 {
1701 /*
1702 * For unusable segments the attributes are undefined except for CS and SS.
1703 * For the rest we don't bother preserving anything but the unusable bit.
1704 */
1705 switch (iSegReg)
1706 {
1707 case X86_SREG_CS:
1708 pVmcs->GuestCs = pSelReg->Sel;
1709 pVmcs->u64GuestCsBase.u = pSelReg->u64Base;
1710 pVmcs->u32GuestCsLimit = pSelReg->u32Limit;
1711 pVmcs->u32GuestCsAttr = pSelReg->Attr.u & ( X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1712 | X86DESCATTR_UNUSABLE);
1713 break;
1714
1715 case X86_SREG_SS:
1716 pVmcs->GuestSs = pSelReg->Sel;
1717 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1718 pVmcs->u64GuestSsBase.u &= UINT32_C(0xffffffff);
1719 pVmcs->u32GuestSsAttr = pSelReg->Attr.u & (X86DESCATTR_DPL | X86DESCATTR_UNUSABLE);
1720 break;
1721
1722 case X86_SREG_DS:
1723 pVmcs->GuestDs = pSelReg->Sel;
1724 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1725 pVmcs->u64GuestDsBase.u &= UINT32_C(0xffffffff);
1726 pVmcs->u32GuestDsAttr = X86DESCATTR_UNUSABLE;
1727 break;
1728
1729 case X86_SREG_ES:
1730 pVmcs->GuestEs = pSelReg->Sel;
1731 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
1732 pVmcs->u64GuestEsBase.u &= UINT32_C(0xffffffff);
1733 pVmcs->u32GuestEsAttr = X86DESCATTR_UNUSABLE;
1734 break;
1735
1736 case X86_SREG_FS:
1737 pVmcs->GuestFs = pSelReg->Sel;
1738 pVmcs->u64GuestFsBase.u = pSelReg->u64Base;
1739 pVmcs->u32GuestFsAttr = X86DESCATTR_UNUSABLE;
1740 break;
1741
1742 case X86_SREG_GS:
1743 pVmcs->GuestGs = pSelReg->Sel;
1744 pVmcs->u64GuestGsBase.u = pSelReg->u64Base;
1745 pVmcs->u32GuestGsAttr = X86DESCATTR_UNUSABLE;
1746 break;
1747 }
1748 }
1749 }
1750
1751 /* Segment attribute bits 31:17 and 11:8 MBZ. */
1752 uint32_t const fValidAttrMask = X86DESCATTR_TYPE | X86DESCATTR_DT | X86DESCATTR_DPL | X86DESCATTR_P
1753 | X86DESCATTR_AVL | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
1754 | X86DESCATTR_UNUSABLE;
1755 /* LDTR. */
1756 {
1757 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.ldtr;
1758 pVmcs->GuestLdtr = pSelReg->Sel;
1759 pVmcs->u64GuestLdtrBase.u = pSelReg->u64Base;
1760 Assert(X86_IS_CANONICAL(pSelReg->u64Base));
1761 pVmcs->u32GuestLdtrLimit = pSelReg->u32Limit;
1762 pVmcs->u32GuestLdtrAttr = pSelReg->Attr.u & fValidAttrMask;
1763 }
1764
1765 /* TR. */
1766 {
1767 PCCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.tr;
1768 pVmcs->GuestTr = pSelReg->Sel;
1769 pVmcs->u64GuestTrBase.u = pSelReg->u64Base;
1770 pVmcs->u32GuestTrLimit = pSelReg->u32Limit;
1771 pVmcs->u32GuestTrAttr = pSelReg->Attr.u & fValidAttrMask;
1772 }
1773
1774 /* GDTR. */
1775 pVmcs->u64GuestGdtrBase.u = pVCpu->cpum.GstCtx.gdtr.pGdt;
1776 pVmcs->u32GuestGdtrLimit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
1777
1778 /* IDTR. */
1779 pVmcs->u64GuestIdtrBase.u = pVCpu->cpum.GstCtx.idtr.pIdt;
1780 pVmcs->u32GuestIdtrLimit = pVCpu->cpum.GstCtx.idtr.cbIdt;
1781}
1782
1783
1784/**
1785 * Saves guest non-register state as part of VM-exit.
1786 *
1787 * @param pVCpu The cross context virtual CPU structure.
1788 * @param uExitReason The VM-exit reason.
1789 */
1790IEM_STATIC void iemVmxVmexitSaveGuestNonRegState(PVMCPU pVCpu, uint32_t uExitReason)
1791{
1792 /*
1793 * Save guest non-register state.
1794 * See Intel spec. 27.3.4 "Saving Non-Register State".
1795 */
1796 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1797
1798 /*
1799 * Activity state.
1800 * Most VM-exits will occur in the active state. However, if the first instruction
1801 * following the VM-entry is a HLT instruction, and the MTF VM-execution control is set,
1802 * the VM-exit will be from the HLT activity state.
1803 *
1804 * See Intel spec. 25.5.2 "Monitor Trap Flag".
1805 */
1806 /** @todo NSTVMX: Does triple-fault VM-exit reflect a shutdown activity state or
1807 * not? */
1808 EMSTATE enmActivityState = EMGetState(pVCpu);
1809 switch (enmActivityState)
1810 {
1811 case EMSTATE_HALTED: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_HLT; break;
1812 default: pVmcs->u32GuestActivityState = VMX_VMCS_GUEST_ACTIVITY_ACTIVE; break;
1813 }
1814
1815 /* Interruptibility-state. */
1816 pVmcs->u32GuestIntrState = 0;
1817 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1818 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
1819
1820 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1821 && pVCpu->cpum.GstCtx.rip == EMGetInhibitInterruptsPC(pVCpu))
1822 {
1823 /** @todo NSTVMX: We can't distinguish between blocking-by-MovSS and blocking-by-STI
1824 * currently. */
1825 pVmcs->u32GuestIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
1826 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1827 }
1828 /* Nothing to do for SMI/enclave. We don't support enclaves or SMM yet. */
1829
1830 /*
1831 * Pending debug exceptions.
1832 */
1833 if ( uExitReason != VMX_EXIT_INIT_SIGNAL
1834 && uExitReason != VMX_EXIT_SMI
1835 && uExitReason != VMX_EXIT_ERR_MACHINE_CHECK
1836 && !HMVmxIsVmexitTrapLike(uExitReason))
1837 {
1838 /** @todo NSTVMX: also must exclude VM-exits caused by debug exceptions when
1839 * block-by-MovSS is in effect. */
1840 pVmcs->u64GuestPendingDbgXcpt.u = 0;
1841 }
1842 else
1843 {
1844 /*
1845 * Pending debug exception field is identical to DR6 except the RTM bit (16) which needs to be flipped.
1846 * The "enabled breakpoint" bit (12) is not present in DR6, so we need to update it here.
1847 *
1848 * See Intel spec. 24.4.2 "Guest Non-Register State".
1849 */
1850 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
1851 uint64_t fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
1852 uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
1853 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3;
1854 if (fPendingDbgMask & fBpHitMask)
1855 fPendingDbgMask |= VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP;
1856 fPendingDbgMask ^= VMX_VMCS_GUEST_PENDING_DEBUG_RTM;
1857 pVmcs->u64GuestPendingDbgXcpt.u = fPendingDbgMask;
1858 }
1859
1860 /*
1861 * Save the VMX-preemption timer value back into the VMCS if the feature is enabled.
1862 *
1863 * For VMX-preemption timer VM-exits, we should have already written back 0 if the
1864 * feature is supported back into the VMCS, and thus there is nothing further to do here.
1865 */
1866 if ( uExitReason != VMX_EXIT_PREEMPT_TIMER
1867 && (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
1868 pVmcs->u32PreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
1869
1870 /* PDPTEs. */
1871 /* We don't support EPT yet. */
1872 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
1873 pVmcs->u64GuestPdpte0.u = 0;
1874 pVmcs->u64GuestPdpte1.u = 0;
1875 pVmcs->u64GuestPdpte2.u = 0;
1876 pVmcs->u64GuestPdpte3.u = 0;
1877}
1878
1879
1880/**
1881 * Saves the guest-state as part of VM-exit.
1882 *
1883 * @returns VBox status code.
1884 * @param pVCpu The cross context virtual CPU structure.
1885 * @param uExitReason The VM-exit reason.
1886 */
1887IEM_STATIC void iemVmxVmexitSaveGuestState(PVMCPU pVCpu, uint32_t uExitReason)
1888{
1889 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1890 Assert(pVmcs);
1891
1892 iemVmxVmexitSaveGuestControlRegsMsrs(pVCpu);
1893 iemVmxVmexitSaveGuestSegRegs(pVCpu);
1894
1895 pVmcs->u64GuestRip.u = pVCpu->cpum.GstCtx.rip;
1896 pVmcs->u64GuestRsp.u = pVCpu->cpum.GstCtx.rsp;
1897 pVmcs->u64GuestRFlags.u = pVCpu->cpum.GstCtx.rflags.u; /** @todo NSTVMX: Check RFLAGS.RF handling. */
1898
1899 iemVmxVmexitSaveGuestNonRegState(pVCpu, uExitReason);
1900}
1901
1902
1903/**
1904 * Saves the guest MSRs into the VM-exit auto-store MSRs area as part of VM-exit.
1905 *
1906 * @returns VBox status code.
1907 * @param pVCpu The cross context virtual CPU structure.
1908 * @param uExitReason The VM-exit reason (for diagnostic purposes).
1909 */
1910IEM_STATIC int iemVmxVmexitSaveGuestAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
1911{
1912 /*
1913 * Save guest MSRs.
1914 * See Intel spec. 27.4 "Saving MSRs".
1915 */
1916 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1917 const char *const pszFailure = "VMX-abort";
1918
1919 /*
1920 * The VM-exit MSR-store area address need not be a valid guest-physical address if the
1921 * VM-exit MSR-store count is 0. If this is the case, bail early without reading it.
1922 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
1923 */
1924 uint32_t const cMsrs = pVmcs->u32ExitMsrStoreCount;
1925 if (!cMsrs)
1926 return VINF_SUCCESS;
1927
1928 /*
1929 * Verify the MSR auto-store count. Physical CPUs can behave unpredictably if the count
1930 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
1931 * implementation causes a VMX-abort followed by a triple-fault.
1932 */
1933 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
1934 if (fIsMsrCountValid)
1935 { /* likely */ }
1936 else
1937 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreCount);
1938
1939 PVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
1940 Assert(pMsr);
1941 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
1942 {
1943 if ( !pMsr->u32Reserved
1944 && pMsr->u32Msr != MSR_IA32_SMBASE
1945 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
1946 {
1947 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pMsr->u32Msr, &pMsr->u64Value);
1948 if (rcStrict == VINF_SUCCESS)
1949 continue;
1950
1951 /*
1952 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
1953 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
1954 * recording the MSR index in the auxiliary info. field and indicated further by our
1955 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
1956 * if possible, or come up with a better, generic solution.
1957 */
1958 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1959 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_READ
1960 ? kVmxVDiag_Vmexit_MsrStoreRing3
1961 : kVmxVDiag_Vmexit_MsrStore;
1962 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
1963 }
1964 else
1965 {
1966 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
1967 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStoreRsvd);
1968 }
1969 }
1970
1971 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrStore.u;
1972 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysAutoMsrArea,
1973 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea), cMsrs * sizeof(VMXAUTOMSR));
1974 if (RT_SUCCESS(rc))
1975 { /* likely */ }
1976 else
1977 {
1978 AssertMsgFailed(("VM-exit: Failed to write MSR auto-store area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
1979 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrStorePtrWritePhys);
1980 }
1981
1982 NOREF(uExitReason);
1983 NOREF(pszFailure);
1984 return VINF_SUCCESS;
1985}
1986
1987
1988/**
1989 * Performs a VMX abort (due to an fatal error during VM-exit).
1990 *
1991 * @returns Strict VBox status code.
1992 * @param pVCpu The cross context virtual CPU structure.
1993 * @param enmAbort The VMX abort reason.
1994 */
1995IEM_STATIC VBOXSTRICTRC iemVmxAbort(PVMCPU pVCpu, VMXABORT enmAbort)
1996{
1997 /*
1998 * Perform the VMX abort.
1999 * See Intel spec. 27.7 "VMX Aborts".
2000 */
2001 LogFunc(("enmAbort=%u (%s) -> RESET\n", enmAbort, HMGetVmxAbortDesc(enmAbort)));
2002
2003 /* We don't support SMX yet. */
2004 pVCpu->cpum.GstCtx.hwvirt.vmx.enmAbort = enmAbort;
2005 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
2006 {
2007 RTGCPHYS const GCPhysVmcs = IEM_VMX_GET_CURRENT_VMCS(pVCpu);
2008 uint32_t const offVmxAbort = RT_UOFFSETOF(VMXVVMCS, enmVmxAbort);
2009 PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + offVmxAbort, &enmAbort, sizeof(enmAbort));
2010 }
2011
2012 return VINF_EM_TRIPLE_FAULT;
2013}
2014
2015
2016/**
2017 * Loads host control registers, debug registers and MSRs as part of VM-exit.
2018 *
2019 * @param pVCpu The cross context virtual CPU structure.
2020 */
2021IEM_STATIC void iemVmxVmexitLoadHostControlRegsMsrs(PVMCPU pVCpu)
2022{
2023 /*
2024 * Load host control registers, debug registers and MSRs.
2025 * See Intel spec. 27.5.1 "Loading Host Control Registers, Debug Registers, MSRs".
2026 */
2027 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2028 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2029
2030 /* CR0. */
2031 {
2032 /* Bits 63:32, 28:19, 17, 15:6, ET, CD, NW and CR0 MB1 bits are not modified. */
2033 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
2034 uint64_t const fCr0IgnMask = UINT64_C(0xffffffff1ff8ffc0) | X86_CR0_ET | X86_CR0_CD | X86_CR0_NW | uCr0Fixed0;
2035 uint64_t const uHostCr0 = pVmcs->u64HostCr0.u;
2036 uint64_t const uGuestCr0 = pVCpu->cpum.GstCtx.cr0;
2037 uint64_t const uValidCr0 = (uHostCr0 & ~fCr0IgnMask) | (uGuestCr0 & fCr0IgnMask);
2038 CPUMSetGuestCR0(pVCpu, uValidCr0);
2039 }
2040
2041 /* CR4. */
2042 {
2043 /* CR4 MB1 bits are not modified. */
2044 uint64_t const fCr4IgnMask = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
2045 uint64_t const uHostCr4 = pVmcs->u64HostCr4.u;
2046 uint64_t const uGuestCr4 = pVCpu->cpum.GstCtx.cr4;
2047 uint64_t uValidCr4 = (uHostCr4 & ~fCr4IgnMask) | (uGuestCr4 & fCr4IgnMask);
2048 if (fHostInLongMode)
2049 uValidCr4 |= X86_CR4_PAE;
2050 else
2051 uValidCr4 &= ~X86_CR4_PCIDE;
2052 CPUMSetGuestCR4(pVCpu, uValidCr4);
2053 }
2054
2055 /* CR3 (host value validated while checking host-state during VM-entry). */
2056 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64HostCr3.u;
2057
2058 /* DR7. */
2059 pVCpu->cpum.GstCtx.dr[7] = X86_DR7_INIT_VAL;
2060
2061 /** @todo NSTVMX: Support IA32_DEBUGCTL MSR */
2062
2063 /* Save SYSENTER CS, ESP, EIP (host value validated while checking host-state during VM-entry). */
2064 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64HostSysenterEip.u;
2065 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64HostSysenterEsp.u;
2066 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32HostSysenterCs;
2067
2068 /* FS, GS bases are loaded later while we load host segment registers. */
2069
2070 /* EFER MSR (host value validated while checking host-state during VM-entry). */
2071 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2072 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64HostEferMsr.u;
2073 else if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
2074 {
2075 if (fHostInLongMode)
2076 pVCpu->cpum.GstCtx.msrEFER |= (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2077 else
2078 pVCpu->cpum.GstCtx.msrEFER &= ~(MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
2079 }
2080
2081 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
2082
2083 /* PAT MSR (host value is validated while checking host-state during VM-entry). */
2084 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
2085 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64HostPatMsr.u;
2086
2087 /* We don't support IA32_BNDCFGS MSR yet. */
2088}
2089
2090
2091/**
2092 * Loads host segment registers, GDTR, IDTR, LDTR and TR as part of VM-exit.
2093 *
2094 * @param pVCpu The cross context virtual CPU structure.
2095 */
2096IEM_STATIC void iemVmxVmexitLoadHostSegRegs(PVMCPU pVCpu)
2097{
2098 /*
2099 * Load host segment registers, GDTR, IDTR, LDTR and TR.
2100 * See Intel spec. 27.5.2 "Loading Host Segment and Descriptor-Table Registers".
2101 *
2102 * Warning! Be careful to not touch fields that are reserved by VT-x,
2103 * e.g. segment limit high bits stored in segment attributes (in bits 11:8).
2104 */
2105 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2106 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2107
2108 /* CS, SS, ES, DS, FS, GS. */
2109 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
2110 {
2111 RTSEL const HostSel = iemVmxVmcsGetHostSelReg(pVmcs, iSegReg);
2112 bool const fUnusable = RT_BOOL(HostSel == 0);
2113 PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
2114
2115 /* Selector. */
2116 pSelReg->Sel = HostSel;
2117 pSelReg->ValidSel = HostSel;
2118 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
2119
2120 /* Limit. */
2121 pSelReg->u32Limit = 0xffffffff;
2122
2123 /* Base. */
2124 pSelReg->u64Base = 0;
2125
2126 /* Attributes. */
2127 if (iSegReg == X86_SREG_CS)
2128 {
2129 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED;
2130 pSelReg->Attr.n.u1DescType = 1;
2131 pSelReg->Attr.n.u2Dpl = 0;
2132 pSelReg->Attr.n.u1Present = 1;
2133 pSelReg->Attr.n.u1Long = fHostInLongMode;
2134 pSelReg->Attr.n.u1DefBig = !fHostInLongMode;
2135 pSelReg->Attr.n.u1Granularity = 1;
2136 Assert(!pSelReg->Attr.n.u1Unusable);
2137 Assert(!fUnusable);
2138 }
2139 else
2140 {
2141 pSelReg->Attr.n.u4Type = X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED;
2142 pSelReg->Attr.n.u1DescType = 1;
2143 pSelReg->Attr.n.u2Dpl = 0;
2144 pSelReg->Attr.n.u1Present = 1;
2145 pSelReg->Attr.n.u1DefBig = 1;
2146 pSelReg->Attr.n.u1Granularity = 1;
2147 pSelReg->Attr.n.u1Unusable = fUnusable;
2148 }
2149 }
2150
2151 /* FS base. */
2152 if ( !pVCpu->cpum.GstCtx.fs.Attr.n.u1Unusable
2153 || fHostInLongMode)
2154 {
2155 Assert(X86_IS_CANONICAL(pVmcs->u64HostFsBase.u));
2156 pVCpu->cpum.GstCtx.fs.u64Base = pVmcs->u64HostFsBase.u;
2157 }
2158
2159 /* GS base. */
2160 if ( !pVCpu->cpum.GstCtx.gs.Attr.n.u1Unusable
2161 || fHostInLongMode)
2162 {
2163 Assert(X86_IS_CANONICAL(pVmcs->u64HostGsBase.u));
2164 pVCpu->cpum.GstCtx.gs.u64Base = pVmcs->u64HostGsBase.u;
2165 }
2166
2167 /* TR. */
2168 Assert(X86_IS_CANONICAL(pVmcs->u64HostTrBase.u));
2169 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1Unusable);
2170 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->HostTr;
2171 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->HostTr;
2172 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2173 pVCpu->cpum.GstCtx.tr.u32Limit = X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN;
2174 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64HostTrBase.u;
2175 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2176 pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType = 0;
2177 pVCpu->cpum.GstCtx.tr.Attr.n.u2Dpl = 0;
2178 pVCpu->cpum.GstCtx.tr.Attr.n.u1Present = 1;
2179 pVCpu->cpum.GstCtx.tr.Attr.n.u1DefBig = 0;
2180 pVCpu->cpum.GstCtx.tr.Attr.n.u1Granularity = 0;
2181
2182 /* LDTR (Warning! do not touch the base and limits here). */
2183 pVCpu->cpum.GstCtx.ldtr.Sel = 0;
2184 pVCpu->cpum.GstCtx.ldtr.ValidSel = 0;
2185 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2186 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
2187
2188 /* GDTR. */
2189 Assert(X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u));
2190 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64HostGdtrBase.u;
2191 pVCpu->cpum.GstCtx.gdtr.cbGdt = 0xffff;
2192
2193 /* IDTR.*/
2194 Assert(X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u));
2195 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64HostIdtrBase.u;
2196 pVCpu->cpum.GstCtx.idtr.cbIdt = 0xffff;
2197}
2198
2199
2200/**
2201 * Checks host PDPTes as part of VM-exit.
2202 *
2203 * @param pVCpu The cross context virtual CPU structure.
2204 * @param uExitReason The VM-exit reason (for logging purposes).
2205 */
2206IEM_STATIC int iemVmxVmexitCheckHostPdptes(PVMCPU pVCpu, uint32_t uExitReason)
2207{
2208 /*
2209 * Check host PDPTEs.
2210 * See Intel spec. 27.5.4 "Checking and Loading Host Page-Directory-Pointer-Table Entries".
2211 */
2212 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2213 const char *const pszFailure = "VMX-abort";
2214 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2215
2216 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
2217 && !fHostInLongMode)
2218 {
2219 uint64_t const uHostCr3 = pVCpu->cpum.GstCtx.cr3 & X86_CR3_PAE_PAGE_MASK;
2220 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
2221 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uHostCr3, sizeof(aPdptes));
2222 if (RT_SUCCESS(rc))
2223 {
2224 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
2225 {
2226 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
2227 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
2228 { /* likely */ }
2229 else
2230 {
2231 VMXVDIAG const enmDiag = iemVmxGetDiagVmexitPdpteRsvd(iPdpte);
2232 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2233 }
2234 }
2235 }
2236 else
2237 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys);
2238 }
2239
2240 NOREF(pszFailure);
2241 NOREF(uExitReason);
2242 return VINF_SUCCESS;
2243}
2244
2245
2246/**
2247 * Loads the host MSRs from the VM-exit auto-load MSRs area as part of VM-exit.
2248 *
2249 * @returns VBox status code.
2250 * @param pVCpu The cross context virtual CPU structure.
2251 * @param pszInstr The VMX instruction name (for logging purposes).
2252 */
2253IEM_STATIC int iemVmxVmexitLoadHostAutoMsrs(PVMCPU pVCpu, uint32_t uExitReason)
2254{
2255 /*
2256 * Load host MSRs.
2257 * See Intel spec. 27.6 "Loading MSRs".
2258 */
2259 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2260 const char *const pszFailure = "VMX-abort";
2261
2262 /*
2263 * The VM-exit MSR-load area address need not be a valid guest-physical address if the
2264 * VM-exit MSR load count is 0. If this is the case, bail early without reading it.
2265 * See Intel spec. 24.7.2 "VM-Exit Controls for MSRs".
2266 */
2267 uint32_t const cMsrs = pVmcs->u32ExitMsrLoadCount;
2268 if (!cMsrs)
2269 return VINF_SUCCESS;
2270
2271 /*
2272 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count
2273 * is exceeded including possibly raising #MC exceptions during VMX transition. Our
2274 * implementation causes a VMX-abort followed by a triple-fault.
2275 */
2276 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
2277 if (fIsMsrCountValid)
2278 { /* likely */ }
2279 else
2280 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadCount);
2281
2282 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea));
2283 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrExitMsrLoad.u;
2284 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
2285 GCPhysAutoMsrArea, cMsrs * sizeof(VMXAUTOMSR));
2286 if (RT_SUCCESS(rc))
2287 {
2288 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
2289 Assert(pMsr);
2290 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
2291 {
2292 if ( !pMsr->u32Reserved
2293 && pMsr->u32Msr != MSR_K8_FS_BASE
2294 && pMsr->u32Msr != MSR_K8_GS_BASE
2295 && pMsr->u32Msr != MSR_K6_EFER
2296 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
2297 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
2298 {
2299 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
2300 if (rcStrict == VINF_SUCCESS)
2301 continue;
2302
2303 /*
2304 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-exit.
2305 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VMX-abort
2306 * recording the MSR index in the auxiliary info. field and indicated further by our
2307 * own, specific diagnostic code. Later, we can try implement handling of the MSR in ring-0
2308 * if possible, or come up with a better, generic solution.
2309 */
2310 pVCpu->cpum.GstCtx.hwvirt.vmx.uAbortAux = pMsr->u32Msr;
2311 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
2312 ? kVmxVDiag_Vmexit_MsrLoadRing3
2313 : kVmxVDiag_Vmexit_MsrLoad;
2314 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, enmDiag);
2315 }
2316 else
2317 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadRsvd);
2318 }
2319 }
2320 else
2321 {
2322 AssertMsgFailed(("VM-exit: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", GCPhysAutoMsrArea, rc));
2323 IEM_VMX_VMEXIT_FAILED_RET(pVCpu, uExitReason, pszFailure, kVmxVDiag_Vmexit_MsrLoadPtrReadPhys);
2324 }
2325
2326 NOREF(uExitReason);
2327 NOREF(pszFailure);
2328 return VINF_SUCCESS;
2329}
2330
2331
2332/**
2333 * Loads the host state as part of VM-exit.
2334 *
2335 * @returns Strict VBox status code.
2336 * @param pVCpu The cross context virtual CPU structure.
2337 * @param uExitReason The VM-exit reason (for logging purposes).
2338 */
2339IEM_STATIC VBOXSTRICTRC iemVmxVmexitLoadHostState(PVMCPU pVCpu, uint32_t uExitReason)
2340{
2341 /*
2342 * Load host state.
2343 * See Intel spec. 27.5 "Loading Host State".
2344 */
2345 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2346 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
2347
2348 /* We cannot return from a long-mode guest to a host that is not in long mode. */
2349 if ( CPUMIsGuestInLongMode(pVCpu)
2350 && !fHostInLongMode)
2351 {
2352 Log(("VM-exit from long-mode guest to host not in long-mode -> VMX-Abort\n"));
2353 return iemVmxAbort(pVCpu, VMXABORT_HOST_NOT_IN_LONG_MODE);
2354 }
2355
2356 iemVmxVmexitLoadHostControlRegsMsrs(pVCpu);
2357 iemVmxVmexitLoadHostSegRegs(pVCpu);
2358
2359 /*
2360 * Load host RIP, RSP and RFLAGS.
2361 * See Intel spec. 27.5.3 "Loading Host RIP, RSP and RFLAGS"
2362 */
2363 pVCpu->cpum.GstCtx.rip = pVmcs->u64HostRip.u;
2364 pVCpu->cpum.GstCtx.rsp = pVmcs->u64HostRsp.u;
2365 pVCpu->cpum.GstCtx.rflags.u = X86_EFL_1;
2366
2367 /* Clear address range monitoring. */
2368 EMMonitorWaitClear(pVCpu);
2369
2370 /* Perform the VMX transition (PGM updates). */
2371 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
2372 if (rcStrict == VINF_SUCCESS)
2373 {
2374 /* Check host PDPTEs (only when we've fully switched page tables_. */
2375 /** @todo r=ramshankar: I don't know if PGM does this for us already or not... */
2376 int rc = iemVmxVmexitCheckHostPdptes(pVCpu, uExitReason);
2377 if (RT_FAILURE(rc))
2378 {
2379 Log(("VM-exit failed while restoring host PDPTEs -> VMX-Abort\n"));
2380 return iemVmxAbort(pVCpu, VMXBOART_HOST_PDPTE);
2381 }
2382 }
2383 else if (RT_SUCCESS(rcStrict))
2384 {
2385 Log3(("VM-exit: iemVmxWorldSwitch returns %Rrc (uExitReason=%u) -> Setting passup status\n", VBOXSTRICTRC_VAL(rcStrict),
2386 uExitReason));
2387 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
2388 }
2389 else
2390 {
2391 Log3(("VM-exit: iemVmxWorldSwitch failed! rc=%Rrc (uExitReason=%u)\n", VBOXSTRICTRC_VAL(rcStrict), uExitReason));
2392 return VBOXSTRICTRC_VAL(rcStrict);
2393 }
2394
2395 Assert(rcStrict == VINF_SUCCESS);
2396
2397 /* Load MSRs from the VM-exit auto-load MSR area. */
2398 int rc = iemVmxVmexitLoadHostAutoMsrs(pVCpu, uExitReason);
2399 if (RT_FAILURE(rc))
2400 {
2401 Log(("VM-exit failed while loading host MSRs -> VMX-Abort\n"));
2402 return iemVmxAbort(pVCpu, VMXABORT_LOAD_HOST_MSR);
2403 }
2404 return VINF_SUCCESS;
2405}
2406
2407
2408/**
2409 * Gets VM-exit instruction information along with any displacement for an
2410 * instruction VM-exit.
2411 *
2412 * @returns The VM-exit instruction information.
2413 * @param pVCpu The cross context virtual CPU structure.
2414 * @param uExitReason The VM-exit reason.
2415 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_XXX).
2416 * @param pGCPtrDisp Where to store the displacement field. Optional, can be
2417 * NULL.
2418 */
2419IEM_STATIC uint32_t iemVmxGetExitInstrInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, PRTGCPTR pGCPtrDisp)
2420{
2421 RTGCPTR GCPtrDisp;
2422 VMXEXITINSTRINFO ExitInstrInfo;
2423 ExitInstrInfo.u = 0;
2424
2425 /*
2426 * Get and parse the ModR/M byte from our decoded opcodes.
2427 */
2428 uint8_t bRm;
2429 uint8_t const offModRm = pVCpu->iem.s.offModRm;
2430 IEM_MODRM_GET_U8(pVCpu, bRm, offModRm);
2431 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2432 {
2433 /*
2434 * ModR/M indicates register addressing.
2435 *
2436 * The primary/secondary register operands are reported in the iReg1 or iReg2
2437 * fields depending on whether it is a read/write form.
2438 */
2439 uint8_t idxReg1;
2440 uint8_t idxReg2;
2441 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2442 {
2443 idxReg1 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2444 idxReg2 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2445 }
2446 else
2447 {
2448 idxReg1 = (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB;
2449 idxReg2 = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg;
2450 }
2451 ExitInstrInfo.All.u2Scaling = 0;
2452 ExitInstrInfo.All.iReg1 = idxReg1;
2453 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2454 ExitInstrInfo.All.fIsRegOperand = 1;
2455 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2456 ExitInstrInfo.All.iSegReg = 0;
2457 ExitInstrInfo.All.iIdxReg = 0;
2458 ExitInstrInfo.All.fIdxRegInvalid = 1;
2459 ExitInstrInfo.All.iBaseReg = 0;
2460 ExitInstrInfo.All.fBaseRegInvalid = 1;
2461 ExitInstrInfo.All.iReg2 = idxReg2;
2462
2463 /* Displacement not applicable for register addressing. */
2464 GCPtrDisp = 0;
2465 }
2466 else
2467 {
2468 /*
2469 * ModR/M indicates memory addressing.
2470 */
2471 uint8_t uScale = 0;
2472 bool fBaseRegValid = false;
2473 bool fIdxRegValid = false;
2474 uint8_t iBaseReg = 0;
2475 uint8_t iIdxReg = 0;
2476 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
2477 {
2478 /*
2479 * Parse the ModR/M, displacement for 16-bit addressing mode.
2480 * See Intel instruction spec. Table 2-1. "16-Bit Addressing Forms with the ModR/M Byte".
2481 */
2482 uint16_t u16Disp = 0;
2483 uint8_t const offDisp = offModRm + sizeof(bRm);
2484 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
2485 {
2486 /* Displacement without any registers. */
2487 IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp);
2488 }
2489 else
2490 {
2491 /* Register (index and base). */
2492 switch (bRm & X86_MODRM_RM_MASK)
2493 {
2494 case 0: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2495 case 1: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2496 case 2: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2497 case 3: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2498 case 4: fIdxRegValid = true; iIdxReg = X86_GREG_xSI; break;
2499 case 5: fIdxRegValid = true; iIdxReg = X86_GREG_xDI; break;
2500 case 6: fBaseRegValid = true; iBaseReg = X86_GREG_xBP; break;
2501 case 7: fBaseRegValid = true; iBaseReg = X86_GREG_xBX; break;
2502 }
2503
2504 /* Register + displacement. */
2505 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2506 {
2507 case 0: break;
2508 case 1: IEM_DISP_GET_S8_SX_U16(pVCpu, u16Disp, offDisp); break;
2509 case 2: IEM_DISP_GET_U16(pVCpu, u16Disp, offDisp); break;
2510 default:
2511 {
2512 /* Register addressing, handled at the beginning. */
2513 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2514 break;
2515 }
2516 }
2517 }
2518
2519 Assert(!uScale); /* There's no scaling/SIB byte for 16-bit addressing. */
2520 GCPtrDisp = (int16_t)u16Disp; /* Sign-extend the displacement. */
2521 }
2522 else if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT)
2523 {
2524 /*
2525 * Parse the ModR/M, SIB, displacement for 32-bit addressing mode.
2526 * See Intel instruction spec. Table 2-2. "32-Bit Addressing Forms with the ModR/M Byte".
2527 */
2528 uint32_t u32Disp = 0;
2529 if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
2530 {
2531 /* Displacement without any registers. */
2532 uint8_t const offDisp = offModRm + sizeof(bRm);
2533 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2534 }
2535 else
2536 {
2537 /* Register (and perhaps scale, index and base). */
2538 uint8_t offDisp = offModRm + sizeof(bRm);
2539 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2540 if (iBaseReg == 4)
2541 {
2542 /* An SIB byte follows the ModR/M byte, parse it. */
2543 uint8_t bSib;
2544 uint8_t const offSib = offModRm + sizeof(bRm);
2545 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2546
2547 /* A displacement may follow SIB, update its offset. */
2548 offDisp += sizeof(bSib);
2549
2550 /* Get the scale. */
2551 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2552
2553 /* Get the index register. */
2554 iIdxReg = (bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK;
2555 fIdxRegValid = RT_BOOL(iIdxReg != 4);
2556
2557 /* Get the base register. */
2558 iBaseReg = bSib & X86_SIB_BASE_MASK;
2559 fBaseRegValid = true;
2560 if (iBaseReg == 5)
2561 {
2562 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2563 {
2564 /* Mod is 0 implies a 32-bit displacement with no base. */
2565 fBaseRegValid = false;
2566 IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp);
2567 }
2568 else
2569 {
2570 /* Mod is not 0 implies an 8-bit/32-bit displacement (handled below) with an EBP base. */
2571 iBaseReg = X86_GREG_xBP;
2572 }
2573 }
2574 }
2575
2576 /* Register + displacement. */
2577 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2578 {
2579 case 0: /* Handled above */ break;
2580 case 1: IEM_DISP_GET_S8_SX_U32(pVCpu, u32Disp, offDisp); break;
2581 case 2: IEM_DISP_GET_U32(pVCpu, u32Disp, offDisp); break;
2582 default:
2583 {
2584 /* Register addressing, handled at the beginning. */
2585 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2586 break;
2587 }
2588 }
2589 }
2590
2591 GCPtrDisp = (int32_t)u32Disp; /* Sign-extend the displacement. */
2592 }
2593 else
2594 {
2595 Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT);
2596
2597 /*
2598 * Parse the ModR/M, SIB, displacement for 64-bit addressing mode.
2599 * See Intel instruction spec. 2.2 "IA-32e Mode".
2600 */
2601 uint64_t u64Disp = 0;
2602 bool const fRipRelativeAddr = RT_BOOL((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5);
2603 if (fRipRelativeAddr)
2604 {
2605 /*
2606 * RIP-relative addressing mode.
2607 *
2608 * The displacement is 32-bit signed implying an offset range of +/-2G.
2609 * See Intel instruction spec. 2.2.1.6 "RIP-Relative Addressing".
2610 */
2611 uint8_t const offDisp = offModRm + sizeof(bRm);
2612 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2613 }
2614 else
2615 {
2616 uint8_t offDisp = offModRm + sizeof(bRm);
2617
2618 /*
2619 * Register (and perhaps scale, index and base).
2620 *
2621 * REX.B extends the most-significant bit of the base register. However, REX.B
2622 * is ignored while determining whether an SIB follows the opcode. Hence, we
2623 * shall OR any REX.B bit -after- inspecting for an SIB byte below.
2624 *
2625 * See Intel instruction spec. Table 2-5. "Special Cases of REX Encodings".
2626 */
2627 iBaseReg = (bRm & X86_MODRM_RM_MASK);
2628 if (iBaseReg == 4)
2629 {
2630 /* An SIB byte follows the ModR/M byte, parse it. Displacement (if any) follows SIB. */
2631 uint8_t bSib;
2632 uint8_t const offSib = offModRm + sizeof(bRm);
2633 IEM_SIB_GET_U8(pVCpu, bSib, offSib);
2634
2635 /* Displacement may follow SIB, update its offset. */
2636 offDisp += sizeof(bSib);
2637
2638 /* Get the scale. */
2639 uScale = (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
2640
2641 /* Get the index. */
2642 iIdxReg = ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex;
2643 fIdxRegValid = RT_BOOL(iIdxReg != 4); /* R12 -can- be used as an index register. */
2644
2645 /* Get the base. */
2646 iBaseReg = (bSib & X86_SIB_BASE_MASK);
2647 fBaseRegValid = true;
2648 if (iBaseReg == 5)
2649 {
2650 if ((bRm & X86_MODRM_MOD_MASK) == 0)
2651 {
2652 /* Mod is 0 implies a signed 32-bit displacement with no base. */
2653 IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp);
2654 }
2655 else
2656 {
2657 /* Mod is non-zero implies an 8-bit/32-bit displacement (handled below) with RBP or R13 as base. */
2658 iBaseReg = pVCpu->iem.s.uRexB ? X86_GREG_x13 : X86_GREG_xBP;
2659 }
2660 }
2661 }
2662 iBaseReg |= pVCpu->iem.s.uRexB;
2663
2664 /* Register + displacement. */
2665 switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
2666 {
2667 case 0: /* Handled above */ break;
2668 case 1: IEM_DISP_GET_S8_SX_U64(pVCpu, u64Disp, offDisp); break;
2669 case 2: IEM_DISP_GET_S32_SX_U64(pVCpu, u64Disp, offDisp); break;
2670 default:
2671 {
2672 /* Register addressing, handled at the beginning. */
2673 AssertMsgFailed(("ModR/M %#x implies register addressing, memory addressing expected!", bRm));
2674 break;
2675 }
2676 }
2677 }
2678
2679 GCPtrDisp = fRipRelativeAddr ? pVCpu->cpum.GstCtx.rip + u64Disp : u64Disp;
2680 }
2681
2682 /*
2683 * The primary or secondary register operand is reported in iReg2 depending
2684 * on whether the primary operand is in read/write form.
2685 */
2686 uint8_t idxReg2;
2687 if (!VMXINSTRID_IS_MODRM_PRIMARY_OP_W(uInstrId))
2688 {
2689 idxReg2 = bRm & X86_MODRM_RM_MASK;
2690 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2691 idxReg2 |= pVCpu->iem.s.uRexB;
2692 }
2693 else
2694 {
2695 idxReg2 = (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK;
2696 if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
2697 idxReg2 |= pVCpu->iem.s.uRexReg;
2698 }
2699 ExitInstrInfo.All.u2Scaling = uScale;
2700 ExitInstrInfo.All.iReg1 = 0; /* Not applicable for memory addressing. */
2701 ExitInstrInfo.All.u3AddrSize = pVCpu->iem.s.enmEffAddrMode;
2702 ExitInstrInfo.All.fIsRegOperand = 0;
2703 ExitInstrInfo.All.uOperandSize = pVCpu->iem.s.enmEffOpSize;
2704 ExitInstrInfo.All.iSegReg = pVCpu->iem.s.iEffSeg;
2705 ExitInstrInfo.All.iIdxReg = iIdxReg;
2706 ExitInstrInfo.All.fIdxRegInvalid = !fIdxRegValid;
2707 ExitInstrInfo.All.iBaseReg = iBaseReg;
2708 ExitInstrInfo.All.iIdxReg = !fBaseRegValid;
2709 ExitInstrInfo.All.iReg2 = idxReg2;
2710 }
2711
2712 /*
2713 * Handle exceptions to the norm for certain instructions.
2714 * (e.g. some instructions convey an instruction identity in place of iReg2).
2715 */
2716 switch (uExitReason)
2717 {
2718 case VMX_EXIT_GDTR_IDTR_ACCESS:
2719 {
2720 Assert(VMXINSTRID_IS_VALID(uInstrId));
2721 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2722 ExitInstrInfo.GdtIdt.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2723 ExitInstrInfo.GdtIdt.u2Undef0 = 0;
2724 break;
2725 }
2726
2727 case VMX_EXIT_LDTR_TR_ACCESS:
2728 {
2729 Assert(VMXINSTRID_IS_VALID(uInstrId));
2730 Assert(VMXINSTRID_GET_ID(uInstrId) == (uInstrId & 0x3));
2731 ExitInstrInfo.LdtTr.u2InstrId = VMXINSTRID_GET_ID(uInstrId);
2732 ExitInstrInfo.LdtTr.u2Undef0 = 0;
2733 break;
2734 }
2735
2736 case VMX_EXIT_RDRAND:
2737 case VMX_EXIT_RDSEED:
2738 {
2739 Assert(ExitInstrInfo.RdrandRdseed.u2OperandSize != 3);
2740 break;
2741 }
2742 }
2743
2744 /* Update displacement and return the constructed VM-exit instruction information field. */
2745 if (pGCPtrDisp)
2746 *pGCPtrDisp = GCPtrDisp;
2747
2748 return ExitInstrInfo.u;
2749}
2750
2751
2752/**
2753 * VMX VM-exit handler.
2754 *
2755 * @returns Strict VBox status code.
2756 * @retval VINF_VMX_VMEXIT when the VM-exit is successful.
2757 * @retval VINF_EM_TRIPLE_FAULT when VM-exit is unsuccessful and leads to a
2758 * triple-fault.
2759 *
2760 * @param pVCpu The cross context virtual CPU structure.
2761 * @param uExitReason The VM-exit reason.
2762 *
2763 * @remarks Make sure VM-exit qualification is updated before calling this
2764 * function!
2765 */
2766IEM_STATIC VBOXSTRICTRC iemVmxVmexit(PVMCPU pVCpu, uint32_t uExitReason)
2767{
2768# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
2769 RT_NOREF2(pVCpu, uExitReason);
2770 return VINF_EM_RAW_EMULATE_INSTR;
2771# else
2772 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 /* Control registers */
2773 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 /* Debug registers */
2774 | CPUMCTX_EXTRN_EFER /* MSRs */
2775 | CPUMCTX_EXTRN_SYSENTER_MSRS
2776 | CPUMCTX_EXTRN_OTHER_MSRS /* PAT */
2777 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS /* GPRs */
2778 | CPUMCTX_EXTRN_SREG_MASK /* Segment registers */
2779 | CPUMCTX_EXTRN_TR /* Task register */
2780 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR /* Table registers */
2781 | CPUMCTX_EXTRN_HWVIRT); /* Hardware virtualization state */
2782
2783 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
2784 Assert(pVmcs);
2785
2786 /* Update the VM-exit reason, the other relevant data fields are expected to be updated by the caller already. */
2787 pVmcs->u32RoExitReason = uExitReason;
2788 Log3(("vmexit: uExitReason=%#RX32 uExitQual=%#RX64 cs:rip=%04x:%#RX64\n", uExitReason, pVmcs->u64RoExitQual,
2789 IEM_GET_CTX(pVCpu)->cs.Sel, IEM_GET_CTX(pVCpu)->rip));
2790
2791 /*
2792 * We need to clear the VM-entry interruption information field's valid bit on VM-exit.
2793 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
2794 */
2795 pVmcs->u32EntryIntInfo &= ~VMX_ENTRY_INT_INFO_VALID;
2796
2797 /*
2798 * Clear IDT-vectoring information fields if the VM-exit was not triggered during delivery of an event.
2799 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
2800 */
2801 {
2802 uint8_t uVector;
2803 uint32_t fFlags;
2804 uint32_t uErrCode;
2805 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, &uVector, &fFlags, &uErrCode, NULL /* uCr2 */);
2806 if (!fInEventDelivery)
2807 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
2808 /* else: Caller would have updated IDT-vectoring information already, see iemVmxVmexitEvent(). */
2809 }
2810
2811 /*
2812 * Save the guest state back into the VMCS.
2813 * We only need to save the state when the VM-entry was successful.
2814 */
2815 bool const fVmentryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
2816 if (!fVmentryFailed)
2817 {
2818 /*
2819 * If we support storing EFER.LMA into IA32e-mode guest field on VM-exit, we need to do that now.
2820 * See Intel spec. 27.2 "Recording VM-exit Information And Updating VM-entry Control".
2821 *
2822 * It is not clear from the Intel spec. if this is done only when VM-entry succeeds.
2823 * If a VM-exit happens before loading guest EFER, we risk restoring the host EFER.LMA
2824 * as guest-CPU state would not been modified. Hence for now, we do this only when
2825 * the VM-entry succeeded.
2826 */
2827 /** @todo r=ramshankar: Figure out if this bit gets set to host EFER.LMA on real
2828 * hardware when VM-exit fails during VM-entry (e.g. VERR_VMX_INVALID_GUEST_STATE). */
2829 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxExitSaveEferLma)
2830 {
2831 if (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA)
2832 pVmcs->u32EntryCtls |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2833 else
2834 pVmcs->u32EntryCtls &= ~VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
2835 }
2836
2837 /*
2838 * The rest of the high bits of the VM-exit reason are only relevant when the VM-exit
2839 * occurs in enclave mode/SMM which we don't support yet.
2840 *
2841 * If we ever add support for it, we can pass just the lower bits to the functions
2842 * below, till then an assert should suffice.
2843 */
2844 Assert(!RT_HI_U16(uExitReason));
2845
2846 /* Save the guest state into the VMCS and restore guest MSRs from the auto-store guest MSR area. */
2847 iemVmxVmexitSaveGuestState(pVCpu, uExitReason);
2848 int rc = iemVmxVmexitSaveGuestAutoMsrs(pVCpu, uExitReason);
2849 if (RT_SUCCESS(rc))
2850 { /* likely */ }
2851 else
2852 return iemVmxAbort(pVCpu, VMXABORT_SAVE_GUEST_MSRS);
2853
2854 /* Clear any saved NMI-blocking state so we don't assert on next VM-entry (if it was in effect on the previous one). */
2855 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions &= ~VMCPU_FF_BLOCK_NMIS;
2856 }
2857 else
2858 {
2859 /* Restore the NMI-blocking state if VM-entry failed due to invalid guest state or while loading MSRs. */
2860 uint32_t const uExitReasonBasic = VMX_EXIT_REASON_BASIC(uExitReason);
2861 if ( uExitReasonBasic == VMX_EXIT_ERR_INVALID_GUEST_STATE
2862 || uExitReasonBasic == VMX_EXIT_ERR_MSR_LOAD)
2863 iemVmxVmexitRestoreNmiBlockingFF(pVCpu);
2864 }
2865
2866 /* Restore the host (outer guest) state. */
2867 VBOXSTRICTRC rcStrict = iemVmxVmexitLoadHostState(pVCpu, uExitReason);
2868 if (RT_SUCCESS(rcStrict))
2869 {
2870 Assert(rcStrict == VINF_SUCCESS);
2871 rcStrict = VINF_VMX_VMEXIT;
2872 }
2873 else
2874 Log3(("vmexit: Loading host-state failed. uExitReason=%u rc=%Rrc\n", uExitReason, VBOXSTRICTRC_VAL(rcStrict)));
2875
2876 /* We're no longer in nested-guest execution mode. */
2877 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = false;
2878
2879 /* Revert any IEM-only nested-guest execution policy if it was set earlier, otherwise return rcStrict. */
2880 IEM_VMX_R3_EXECPOLICY_IEM_ALL_DISABLE_RET(pVCpu, "VM-exit", rcStrict);
2881# endif
2882}
2883
2884
2885/**
2886 * VMX VM-exit handler for VM-exits due to instruction execution.
2887 *
2888 * This is intended for instructions where the caller provides all the relevant
2889 * VM-exit information.
2890 *
2891 * @returns Strict VBox status code.
2892 * @param pVCpu The cross context virtual CPU structure.
2893 * @param pExitInfo Pointer to the VM-exit instruction information struct.
2894 */
2895DECLINLINE(VBOXSTRICTRC) iemVmxVmexitInstrWithInfo(PVMCPU pVCpu, PCVMXVEXITINFO pExitInfo)
2896{
2897 /*
2898 * For instructions where any of the following fields are not applicable:
2899 * - VM-exit instruction info. is undefined.
2900 * - VM-exit qualification must be cleared.
2901 * - VM-exit guest-linear address is undefined.
2902 * - VM-exit guest-physical address is undefined.
2903 *
2904 * The VM-exit instruction length is mandatory for all VM-exits that are caused by
2905 * instruction execution. For VM-exits that are not due to instruction execution this
2906 * field is undefined.
2907 *
2908 * In our implementation in IEM, all undefined fields are generally cleared. However,
2909 * if the caller supplies information (from say the physical CPU directly) it is
2910 * then possible that the undefined fields are not cleared.
2911 *
2912 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
2913 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
2914 */
2915 Assert(pExitInfo);
2916 AssertMsg(pExitInfo->uReason <= VMX_EXIT_MAX, ("uReason=%u\n", pExitInfo->uReason));
2917 AssertMsg(pExitInfo->cbInstr >= 1 && pExitInfo->cbInstr <= 15,
2918 ("uReason=%u cbInstr=%u\n", pExitInfo->uReason, pExitInfo->cbInstr));
2919
2920 /* Update all the relevant fields from the VM-exit instruction information struct. */
2921 iemVmxVmcsSetExitInstrInfo(pVCpu, pExitInfo->InstrInfo.u);
2922 iemVmxVmcsSetExitQual(pVCpu, pExitInfo->u64Qual);
2923 iemVmxVmcsSetExitGuestLinearAddr(pVCpu, pExitInfo->u64GuestLinearAddr);
2924 iemVmxVmcsSetExitGuestPhysAddr(pVCpu, pExitInfo->u64GuestPhysAddr);
2925 iemVmxVmcsSetExitInstrLen(pVCpu, pExitInfo->cbInstr);
2926
2927 /* Perform the VM-exit. */
2928 return iemVmxVmexit(pVCpu, pExitInfo->uReason);
2929}
2930
2931
2932/**
2933 * VMX VM-exit handler for VM-exits due to instruction execution.
2934 *
2935 * This is intended for instructions that only provide the VM-exit instruction
2936 * length.
2937 *
2938 * @param pVCpu The cross context virtual CPU structure.
2939 * @param uExitReason The VM-exit reason.
2940 * @param cbInstr The instruction length in bytes.
2941 */
2942IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstr(PVMCPU pVCpu, uint32_t uExitReason, uint8_t cbInstr)
2943{
2944 VMXVEXITINFO ExitInfo;
2945 RT_ZERO(ExitInfo);
2946 ExitInfo.uReason = uExitReason;
2947 ExitInfo.cbInstr = cbInstr;
2948
2949#ifdef VBOX_STRICT
2950 /* To prevent us from shooting ourselves in the foot. Maybe remove later. */
2951 switch (uExitReason)
2952 {
2953 case VMX_EXIT_INVEPT:
2954 case VMX_EXIT_INVPCID:
2955 case VMX_EXIT_LDTR_TR_ACCESS:
2956 case VMX_EXIT_GDTR_IDTR_ACCESS:
2957 case VMX_EXIT_VMCLEAR:
2958 case VMX_EXIT_VMPTRLD:
2959 case VMX_EXIT_VMPTRST:
2960 case VMX_EXIT_VMREAD:
2961 case VMX_EXIT_VMWRITE:
2962 case VMX_EXIT_VMXON:
2963 case VMX_EXIT_XRSTORS:
2964 case VMX_EXIT_XSAVES:
2965 case VMX_EXIT_RDRAND:
2966 case VMX_EXIT_RDSEED:
2967 case VMX_EXIT_IO_INSTR:
2968 AssertMsgFailedReturn(("Use iemVmxVmexitInstrNeedsInfo for uExitReason=%u\n", uExitReason), VERR_IEM_IPE_5);
2969 break;
2970 }
2971#endif
2972
2973 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
2974}
2975
2976
2977/**
2978 * VMX VM-exit handler for VM-exits due to instruction execution.
2979 *
2980 * This is intended for instructions that have a ModR/M byte and update the VM-exit
2981 * instruction information and VM-exit qualification fields.
2982 *
2983 * @param pVCpu The cross context virtual CPU structure.
2984 * @param uExitReason The VM-exit reason.
2985 * @param uInstrid The instruction identity (VMXINSTRID_XXX).
2986 * @param cbInstr The instruction length in bytes.
2987 *
2988 * @remarks Do not use this for INS/OUTS instruction.
2989 */
2990IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPU pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr)
2991{
2992 VMXVEXITINFO ExitInfo;
2993 RT_ZERO(ExitInfo);
2994 ExitInfo.uReason = uExitReason;
2995 ExitInfo.cbInstr = cbInstr;
2996
2997 /*
2998 * Update the VM-exit qualification field with displacement bytes.
2999 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3000 */
3001 switch (uExitReason)
3002 {
3003 case VMX_EXIT_INVEPT:
3004 case VMX_EXIT_INVPCID:
3005 case VMX_EXIT_LDTR_TR_ACCESS:
3006 case VMX_EXIT_GDTR_IDTR_ACCESS:
3007 case VMX_EXIT_VMCLEAR:
3008 case VMX_EXIT_VMPTRLD:
3009 case VMX_EXIT_VMPTRST:
3010 case VMX_EXIT_VMREAD:
3011 case VMX_EXIT_VMWRITE:
3012 case VMX_EXIT_VMXON:
3013 case VMX_EXIT_XRSTORS:
3014 case VMX_EXIT_XSAVES:
3015 case VMX_EXIT_RDRAND:
3016 case VMX_EXIT_RDSEED:
3017 {
3018 /* Construct the VM-exit instruction information. */
3019 RTGCPTR GCPtrDisp;
3020 uint32_t const uInstrInfo = iemVmxGetExitInstrInfo(pVCpu, uExitReason, uInstrId, &GCPtrDisp);
3021
3022 /* Update the VM-exit instruction information. */
3023 ExitInfo.InstrInfo.u = uInstrInfo;
3024
3025 /* Update the VM-exit qualification. */
3026 ExitInfo.u64Qual = GCPtrDisp;
3027 break;
3028 }
3029
3030 default:
3031 AssertMsgFailedReturn(("Use instruction-specific handler\n"), VERR_IEM_IPE_5);
3032 break;
3033 }
3034
3035 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3036}
3037
3038
3039/**
3040 * Checks whether an I/O instruction for the given port is intercepted (causes a
3041 * VM-exit) or not.
3042 *
3043 * @returns @c true if the instruction is intercepted, @c false otherwise.
3044 * @param pVCpu The cross context virtual CPU structure.
3045 * @param u16Port The I/O port being accessed by the instruction.
3046 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3047 */
3048IEM_STATIC bool iemVmxIsIoInterceptSet(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbAccess)
3049{
3050 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3051 Assert(pVmcs);
3052
3053 /*
3054 * Check whether the I/O instruction must cause a VM-exit or not.
3055 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3056 */
3057 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT)
3058 return true;
3059
3060 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
3061 {
3062 uint8_t const *pbIoBitmapA = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap);
3063 uint8_t const *pbIoBitmapB = (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvIoBitmap) + VMX_V_IO_BITMAP_A_SIZE;
3064 Assert(pbIoBitmapA);
3065 Assert(pbIoBitmapB);
3066 return HMGetVmxIoBitmapPermission(pbIoBitmapA, pbIoBitmapB, u16Port, cbAccess);
3067 }
3068
3069 return false;
3070}
3071
3072
3073/**
3074 * VMX VM-exit handler for VM-exits due to Monitor-Trap Flag (MTF).
3075 *
3076 * @returns Strict VBox status code.
3077 * @param pVCpu The cross context virtual CPU structure.
3078 */
3079IEM_STATIC VBOXSTRICTRC iemVmxVmexitMtf(PVMCPU pVCpu)
3080{
3081 /*
3082 * The MTF VM-exit can occur even when the MTF VM-execution control is
3083 * not set (e.g. when VM-entry injects an MTF pending event), so do not
3084 * check for it here.
3085 */
3086
3087 /* Clear the force-flag indicating that monitor-trap flag is no longer active. */
3088 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_MTF);
3089
3090 /* Cause the MTF VM-exit. The VM-exit qualification MBZ. */
3091 return iemVmxVmexit(pVCpu, VMX_EXIT_MTF);
3092}
3093
3094
3095/**
3096 * VMX VM-exit handler for VM-exits due to INVLPG.
3097 *
3098 * @returns Strict VBox status code.
3099 * @param pVCpu The cross context virtual CPU structure.
3100 * @param GCPtrPage The guest-linear address of the page being invalidated.
3101 * @param cbInstr The instruction length in bytes.
3102 */
3103IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPU pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr)
3104{
3105 VMXVEXITINFO ExitInfo;
3106 RT_ZERO(ExitInfo);
3107 ExitInfo.uReason = VMX_EXIT_INVLPG;
3108 ExitInfo.cbInstr = cbInstr;
3109 ExitInfo.u64Qual = GCPtrPage;
3110 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(ExitInfo.u64Qual));
3111
3112 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3113}
3114
3115
3116/**
3117 * VMX VM-exit handler for VM-exits due to LMSW.
3118 *
3119 * @returns Strict VBox status code.
3120 * @param pVCpu The cross context virtual CPU structure.
3121 * @param uGuestCr0 The current guest CR0.
3122 * @param pu16NewMsw The machine-status word specified in LMSW's source
3123 * operand. This will be updated depending on the VMX
3124 * guest/host CR0 mask if LMSW is not intercepted.
3125 * @param GCPtrEffDst The guest-linear address of the source operand in case
3126 * of a memory operand. For register operand, pass
3127 * NIL_RTGCPTR.
3128 * @param cbInstr The instruction length in bytes.
3129 */
3130IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPU pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw, RTGCPTR GCPtrEffDst,
3131 uint8_t cbInstr)
3132{
3133 /*
3134 * LMSW VM-exits are subject to the CR0 guest/host mask and the CR0 read shadow.
3135 *
3136 * See Intel spec. 24.6.6 "Guest/Host Masks and Read Shadows for CR0 and CR4".
3137 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3138 */
3139 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3140 Assert(pVmcs);
3141 Assert(pu16NewMsw);
3142
3143 bool fIntercept = false;
3144 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3145 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3146
3147 /*
3148 * LMSW can never clear CR0.PE but it may set it. Hence, we handle the
3149 * CR0.PE case first, before the rest of the bits in the MSW.
3150 *
3151 * If CR0.PE is owned by the host and CR0.PE differs between the
3152 * MSW (source operand) and the read-shadow, we must cause a VM-exit.
3153 */
3154 if ( (fGstHostMask & X86_CR0_PE)
3155 && (*pu16NewMsw & X86_CR0_PE)
3156 && !(fReadShadow & X86_CR0_PE))
3157 fIntercept = true;
3158
3159 /*
3160 * If CR0.MP, CR0.EM or CR0.TS is owned by the host, and the corresponding
3161 * bits differ between the MSW (source operand) and the read-shadow, we must
3162 * cause a VM-exit.
3163 */
3164 uint32_t fGstHostLmswMask = fGstHostMask & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3165 if ((fReadShadow & fGstHostLmswMask) != (*pu16NewMsw & fGstHostLmswMask))
3166 fIntercept = true;
3167
3168 if (fIntercept)
3169 {
3170 Log2(("lmsw: Guest intercept -> VM-exit\n"));
3171
3172 VMXVEXITINFO ExitInfo;
3173 RT_ZERO(ExitInfo);
3174 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3175 ExitInfo.cbInstr = cbInstr;
3176
3177 bool const fMemOperand = RT_BOOL(GCPtrEffDst != NIL_RTGCPTR);
3178 if (fMemOperand)
3179 {
3180 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode || !RT_HI_U32(GCPtrEffDst));
3181 ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
3182 }
3183
3184 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3185 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_LMSW)
3186 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_OP, fMemOperand)
3187 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_LMSW_DATA, *pu16NewMsw);
3188
3189 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3190 }
3191
3192 /*
3193 * If LMSW did not cause a VM-exit, any CR0 bits in the range 0:3 that is set in the
3194 * CR0 guest/host mask must be left unmodified.
3195 *
3196 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3197 */
3198 fGstHostLmswMask = fGstHostMask & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3199 *pu16NewMsw = (uGuestCr0 & fGstHostLmswMask) | (*pu16NewMsw & ~fGstHostLmswMask);
3200
3201 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3202}
3203
3204
3205/**
3206 * VMX VM-exit handler for VM-exits due to CLTS.
3207 *
3208 * @returns Strict VBox status code.
3209 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the CLTS instruction did not cause a
3210 * VM-exit but must not modify the guest CR0.TS bit.
3211 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the CLTS instruction did not cause a
3212 * VM-exit and modification to the guest CR0.TS bit is allowed (subject to
3213 * CR0 fixed bits in VMX operation).
3214 * @param pVCpu The cross context virtual CPU structure.
3215 * @param cbInstr The instruction length in bytes.
3216 */
3217IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPU pVCpu, uint8_t cbInstr)
3218{
3219 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3220 Assert(pVmcs);
3221
3222 uint32_t const fGstHostMask = pVmcs->u64Cr0Mask.u;
3223 uint32_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3224
3225 /*
3226 * If CR0.TS is owned by the host:
3227 * - If CR0.TS is set in the read-shadow, we must cause a VM-exit.
3228 * - If CR0.TS is cleared in the read-shadow, no VM-exit is caused and the
3229 * CLTS instruction completes without clearing CR0.TS.
3230 *
3231 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3232 */
3233 if (fGstHostMask & X86_CR0_TS)
3234 {
3235 if (fReadShadow & X86_CR0_TS)
3236 {
3237 Log2(("clts: Guest intercept -> VM-exit\n"));
3238
3239 VMXVEXITINFO ExitInfo;
3240 RT_ZERO(ExitInfo);
3241 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3242 ExitInfo.cbInstr = cbInstr;
3243 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 0) /* CR0 */
3244 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_CLTS);
3245 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3246 }
3247
3248 return VINF_VMX_MODIFIES_BEHAVIOR;
3249 }
3250
3251 /*
3252 * If CR0.TS is not owned by the host, the CLTS instructions operates normally
3253 * and may modify CR0.TS (subject to CR0 fixed bits in VMX operation).
3254 */
3255 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3256}
3257
3258
3259/**
3260 * VMX VM-exit handler for VM-exits due to 'Mov CR0,GReg' and 'Mov CR4,GReg'
3261 * (CR0/CR4 write).
3262 *
3263 * @returns Strict VBox status code.
3264 * @param pVCpu The cross context virtual CPU structure.
3265 * @param iCrReg The control register (either CR0 or CR4).
3266 * @param uGuestCrX The current guest CR0/CR4.
3267 * @param puNewCrX Pointer to the new CR0/CR4 value. Will be updated
3268 * if no VM-exit is caused.
3269 * @param iGReg The general register from which the CR0/CR4 value is
3270 * being loaded.
3271 * @param cbInstr The instruction length in bytes.
3272 */
3273IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPU pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg,
3274 uint8_t cbInstr)
3275{
3276 Assert(puNewCrX);
3277 Assert(iCrReg == 0 || iCrReg == 4);
3278 Assert(iGReg < X86_GREG_COUNT);
3279
3280 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3281 Assert(pVmcs);
3282
3283 uint64_t uGuestCrX;
3284 uint64_t fGstHostMask;
3285 uint64_t fReadShadow;
3286 if (iCrReg == 0)
3287 {
3288 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3289 uGuestCrX = pVCpu->cpum.GstCtx.cr0;
3290 fGstHostMask = pVmcs->u64Cr0Mask.u;
3291 fReadShadow = pVmcs->u64Cr0ReadShadow.u;
3292 }
3293 else
3294 {
3295 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3296 uGuestCrX = pVCpu->cpum.GstCtx.cr4;
3297 fGstHostMask = pVmcs->u64Cr4Mask.u;
3298 fReadShadow = pVmcs->u64Cr4ReadShadow.u;
3299 }
3300
3301 /*
3302 * For any CR0/CR4 bit owned by the host (in the CR0/CR4 guest/host mask), if the
3303 * corresponding bits differ between the source operand and the read-shadow,
3304 * we must cause a VM-exit.
3305 *
3306 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3307 */
3308 if ((fReadShadow & fGstHostMask) != (*puNewCrX & fGstHostMask))
3309 {
3310 Assert(fGstHostMask != 0);
3311 Log2(("mov_Cr_Rd: (CR%u) Guest intercept -> VM-exit\n", iCrReg));
3312
3313 VMXVEXITINFO ExitInfo;
3314 RT_ZERO(ExitInfo);
3315 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3316 ExitInfo.cbInstr = cbInstr;
3317 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, iCrReg)
3318 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3319 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3320 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3321 }
3322
3323 /*
3324 * If the Mov-to-CR0/CR4 did not cause a VM-exit, any bits owned by the host
3325 * must not be modified the instruction.
3326 *
3327 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3328 */
3329 *puNewCrX = (uGuestCrX & fGstHostMask) | (*puNewCrX & ~fGstHostMask);
3330
3331 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3332}
3333
3334
3335/**
3336 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR3' (CR3 read).
3337 *
3338 * @returns VBox strict status code.
3339 * @param pVCpu The cross context virtual CPU structure.
3340 * @param iGReg The general register to which the CR3 value is being stored.
3341 * @param cbInstr The instruction length in bytes.
3342 */
3343IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3344{
3345 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3346 Assert(pVmcs);
3347 Assert(iGReg < X86_GREG_COUNT);
3348 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3349
3350 /*
3351 * If the CR3-store exiting control is set, we must cause a VM-exit.
3352 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3353 */
3354 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT)
3355 {
3356 Log2(("mov_Rd_Cr: (CR3) Guest intercept -> VM-exit\n"));
3357
3358 VMXVEXITINFO ExitInfo;
3359 RT_ZERO(ExitInfo);
3360 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3361 ExitInfo.cbInstr = cbInstr;
3362 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3363 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3364 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3365 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3366 }
3367
3368 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3369}
3370
3371
3372/**
3373 * VMX VM-exit handler for VM-exits due to 'Mov CR3,GReg' (CR3 write).
3374 *
3375 * @returns VBox strict status code.
3376 * @param pVCpu The cross context virtual CPU structure.
3377 * @param uNewCr3 The new CR3 value.
3378 * @param iGReg The general register from which the CR3 value is being
3379 * loaded.
3380 * @param cbInstr The instruction length in bytes.
3381 */
3382IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPU pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr)
3383{
3384 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3385 Assert(pVmcs);
3386 Assert(iGReg < X86_GREG_COUNT);
3387
3388 /*
3389 * If the CR3-load exiting control is set and the new CR3 value does not
3390 * match any of the CR3-target values in the VMCS, we must cause a VM-exit.
3391 *
3392 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3393 */
3394 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT)
3395 {
3396 uint32_t const uCr3TargetCount = pVmcs->u32Cr3TargetCount;
3397 Assert(uCr3TargetCount <= VMX_V_CR3_TARGET_COUNT);
3398
3399 /* If the CR3-target count is 0, we must always cause a VM-exit. */
3400 bool fIntercept = RT_BOOL(uCr3TargetCount == 0);
3401 if (!fIntercept)
3402 {
3403 for (uint32_t idxCr3Target = 0; idxCr3Target < uCr3TargetCount; idxCr3Target++)
3404 {
3405 uint64_t const uCr3TargetValue = iemVmxVmcsGetCr3TargetValue(pVmcs, idxCr3Target);
3406 if (uNewCr3 != uCr3TargetValue)
3407 {
3408 fIntercept = true;
3409 break;
3410 }
3411 }
3412 }
3413
3414 if (fIntercept)
3415 {
3416 Log2(("mov_Cr_Rd: (CR3) Guest intercept -> VM-exit\n"));
3417
3418 VMXVEXITINFO ExitInfo;
3419 RT_ZERO(ExitInfo);
3420 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3421 ExitInfo.cbInstr = cbInstr;
3422 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 3) /* CR3 */
3423 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3424 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3425 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3426 }
3427 }
3428
3429 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3430}
3431
3432
3433/**
3434 * VMX VM-exit handler for VM-exits due to 'Mov GReg,CR8' (CR8 read).
3435 *
3436 * @returns VBox strict status code.
3437 * @param pVCpu The cross context virtual CPU structure.
3438 * @param iGReg The general register to which the CR8 value is being stored.
3439 * @param cbInstr The instruction length in bytes.
3440 */
3441IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3442{
3443 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3444 Assert(pVmcs);
3445 Assert(iGReg < X86_GREG_COUNT);
3446
3447 /*
3448 * If the CR8-store exiting control is set, we must cause a VM-exit.
3449 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3450 */
3451 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT)
3452 {
3453 Log2(("mov_Rd_Cr: (CR8) Guest intercept -> VM-exit\n"));
3454
3455 VMXVEXITINFO ExitInfo;
3456 RT_ZERO(ExitInfo);
3457 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3458 ExitInfo.cbInstr = cbInstr;
3459 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3460 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_READ)
3461 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3462 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3463 }
3464
3465 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3466}
3467
3468
3469/**
3470 * VMX VM-exit handler for VM-exits due to 'Mov CR8,GReg' (CR8 write).
3471 *
3472 * @returns VBox strict status code.
3473 * @param pVCpu The cross context virtual CPU structure.
3474 * @param iGReg The general register from which the CR8 value is being
3475 * loaded.
3476 * @param cbInstr The instruction length in bytes.
3477 */
3478IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPU pVCpu, uint8_t iGReg, uint8_t cbInstr)
3479{
3480 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3481 Assert(pVmcs);
3482 Assert(iGReg < X86_GREG_COUNT);
3483
3484 /*
3485 * If the CR8-load exiting control is set, we must cause a VM-exit.
3486 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3487 */
3488 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT)
3489 {
3490 Log2(("mov_Cr_Rd: (CR8) Guest intercept -> VM-exit\n"));
3491
3492 VMXVEXITINFO ExitInfo;
3493 RT_ZERO(ExitInfo);
3494 ExitInfo.uReason = VMX_EXIT_MOV_CRX;
3495 ExitInfo.cbInstr = cbInstr;
3496 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_REGISTER, 8) /* CR8 */
3497 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_ACCESS, VMX_EXIT_QUAL_CRX_ACCESS_WRITE)
3498 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_CRX_GENREG, iGReg);
3499 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3500 }
3501
3502 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3503}
3504
3505
3506/**
3507 * VMX VM-exit handler for VM-exits due to 'Mov DRx,GReg' (DRx write) and 'Mov
3508 * GReg,DRx' (DRx read).
3509 *
3510 * @returns VBox strict status code.
3511 * @param pVCpu The cross context virtual CPU structure.
3512 * @param uInstrid The instruction identity (VMXINSTRID_MOV_TO_DRX or
3513 * VMXINSTRID_MOV_FROM_DRX).
3514 * @param iDrReg The debug register being accessed.
3515 * @param iGReg The general register to/from which the DRx value is being
3516 * store/loaded.
3517 * @param cbInstr The instruction length in bytes.
3518 */
3519IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPU pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg,
3520 uint8_t cbInstr)
3521{
3522 Assert(iDrReg <= 7);
3523 Assert(uInstrId == VMXINSTRID_MOV_TO_DRX || uInstrId == VMXINSTRID_MOV_FROM_DRX);
3524 Assert(iGReg < X86_GREG_COUNT);
3525
3526 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3527 Assert(pVmcs);
3528
3529 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT)
3530 {
3531 uint32_t const uDirection = uInstrId == VMXINSTRID_MOV_TO_DRX ? VMX_EXIT_QUAL_DRX_DIRECTION_WRITE
3532 : VMX_EXIT_QUAL_DRX_DIRECTION_READ;
3533 VMXVEXITINFO ExitInfo;
3534 RT_ZERO(ExitInfo);
3535 ExitInfo.uReason = VMX_EXIT_MOV_DRX;
3536 ExitInfo.cbInstr = cbInstr;
3537 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_REGISTER, iDrReg)
3538 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_DIRECTION, uDirection)
3539 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_DRX_GENREG, iGReg);
3540 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3541 }
3542
3543 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3544}
3545
3546
3547/**
3548 * VMX VM-exit handler for VM-exits due to I/O instructions (IN and OUT).
3549 *
3550 * @returns VBox strict status code.
3551 * @param pVCpu The cross context virtual CPU structure.
3552 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_IN or
3553 * VMXINSTRID_IO_OUT).
3554 * @param u16Port The I/O port being accessed.
3555 * @param fImm Whether the I/O port was encoded using an immediate operand
3556 * or the implicit DX register.
3557 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3558 * @param cbInstr The instruction length in bytes.
3559 */
3560IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, bool fImm, uint8_t cbAccess,
3561 uint8_t cbInstr)
3562{
3563 Assert(uInstrId == VMXINSTRID_IO_IN || uInstrId == VMXINSTRID_IO_OUT);
3564 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3565
3566 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3567 if (fIntercept)
3568 {
3569 uint32_t const uDirection = uInstrId == VMXINSTRID_IO_IN ? VMX_EXIT_QUAL_IO_DIRECTION_IN
3570 : VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3571 VMXVEXITINFO ExitInfo;
3572 RT_ZERO(ExitInfo);
3573 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3574 ExitInfo.cbInstr = cbInstr;
3575 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3576 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3577 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, fImm)
3578 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3579 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3580 }
3581
3582 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3583}
3584
3585
3586/**
3587 * VMX VM-exit handler for VM-exits due to string I/O instructions (INS and OUTS).
3588 *
3589 * @returns VBox strict status code.
3590 * @param pVCpu The cross context virtual CPU structure.
3591 * @param uInstrId The VM-exit instruction identity (VMXINSTRID_IO_INS or
3592 * VMXINSTRID_IO_OUTS).
3593 * @param u16Port The I/O port being accessed.
3594 * @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
3595 * @param fRep Whether the instruction has a REP prefix or not.
3596 * @param ExitInstrInfo The VM-exit instruction info. field.
3597 * @param cbInstr The instruction length in bytes.
3598 */
3599IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPU pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess, bool fRep,
3600 VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr)
3601{
3602 Assert(uInstrId == VMXINSTRID_IO_INS || uInstrId == VMXINSTRID_IO_OUTS);
3603 Assert(cbAccess == 1 || cbAccess == 2 || cbAccess == 4);
3604 Assert(ExitInstrInfo.StrIo.iSegReg < X86_SREG_COUNT);
3605 Assert(ExitInstrInfo.StrIo.u3AddrSize == 0 || ExitInstrInfo.StrIo.u3AddrSize == 1 || ExitInstrInfo.StrIo.u3AddrSize == 2);
3606 Assert(uInstrId != VMXINSTRID_IO_INS || ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES);
3607
3608 bool const fIntercept = iemVmxIsIoInterceptSet(pVCpu, u16Port, cbAccess);
3609 if (fIntercept)
3610 {
3611 /*
3612 * Figure out the guest-linear address and the direction bit (INS/OUTS).
3613 */
3614 /** @todo r=ramshankar: Is there something in IEM that already does this? */
3615 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
3616 uint8_t const iSegReg = ExitInstrInfo.StrIo.iSegReg;
3617 uint8_t const uAddrSize = ExitInstrInfo.StrIo.u3AddrSize;
3618 uint64_t const uAddrSizeMask = s_auAddrSizeMasks[uAddrSize];
3619
3620 uint32_t uDirection;
3621 uint64_t uGuestLinearAddr;
3622 if (uInstrId == VMXINSTRID_IO_INS)
3623 {
3624 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_IN;
3625 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rdi & uAddrSizeMask);
3626 }
3627 else
3628 {
3629 uDirection = VMX_EXIT_QUAL_IO_DIRECTION_OUT;
3630 uGuestLinearAddr = pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base + (pVCpu->cpum.GstCtx.rsi & uAddrSizeMask);
3631 }
3632
3633 /*
3634 * If the segment is ununsable, the guest-linear address in undefined.
3635 * We shall clear it for consistency.
3636 *
3637 * See Intel spec. 27.2.1 "Basic VM-Exit Information".
3638 */
3639 if (pVCpu->cpum.GstCtx.aSRegs[iSegReg].Attr.n.u1Unusable)
3640 uGuestLinearAddr = 0;
3641
3642 VMXVEXITINFO ExitInfo;
3643 RT_ZERO(ExitInfo);
3644 ExitInfo.uReason = VMX_EXIT_IO_INSTR;
3645 ExitInfo.cbInstr = cbInstr;
3646 ExitInfo.InstrInfo = ExitInstrInfo;
3647 ExitInfo.u64GuestLinearAddr = uGuestLinearAddr;
3648 ExitInfo.u64Qual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_WIDTH, cbAccess - 1)
3649 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_DIRECTION, uDirection)
3650 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_STRING, 1)
3651 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_IS_REP, fRep)
3652 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_ENCODING, VMX_EXIT_QUAL_IO_ENCODING_DX)
3653 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_IO_PORT, u16Port);
3654 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3655 }
3656
3657 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3658}
3659
3660
3661/**
3662 * VMX VM-exit handler for VM-exits due to MWAIT.
3663 *
3664 * @returns VBox strict status code.
3665 * @param pVCpu The cross context virtual CPU structure.
3666 * @param fMonitorHwArmed Whether the address-range monitor hardware is armed.
3667 * @param cbInstr The instruction length in bytes.
3668 */
3669IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPU pVCpu, bool fMonitorHwArmed, uint8_t cbInstr)
3670{
3671 VMXVEXITINFO ExitInfo;
3672 RT_ZERO(ExitInfo);
3673 ExitInfo.uReason = VMX_EXIT_MWAIT;
3674 ExitInfo.cbInstr = cbInstr;
3675 ExitInfo.u64Qual = fMonitorHwArmed;
3676 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3677}
3678
3679
3680/**
3681 * VMX VM-exit handler for VM-exits due to PAUSE.
3682 *
3683 * @returns VBox strict status code.
3684 * @param pVCpu The cross context virtual CPU structure.
3685 * @param cbInstr The instruction length in bytes.
3686 */
3687IEM_STATIC VBOXSTRICTRC iemVmxVmexitInstrPause(PVMCPU pVCpu, uint8_t cbInstr)
3688{
3689 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3690 Assert(pVmcs);
3691
3692 /*
3693 * The PAUSE VM-exit is controlled by the "PAUSE exiting" control and the
3694 * "PAUSE-loop exiting" control.
3695 *
3696 * The PLE-Gap is the maximum number of TSC ticks between two successive executions of
3697 * the PAUSE instruction before we cause a VM-exit. The PLE-Window is the maximum amount
3698 * of TSC ticks the guest is allowed to execute in a pause loop before we must cause
3699 * a VM-exit.
3700 *
3701 * See Intel spec. 24.6.13 "Controls for PAUSE-Loop Exiting".
3702 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
3703 */
3704 bool fIntercept = false;
3705 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
3706 fIntercept = true;
3707 else if ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3708 && pVCpu->iem.s.uCpl == 0)
3709 {
3710 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3711
3712 /*
3713 * A previous-PAUSE-tick value of 0 is used to identify the first time
3714 * execution of a PAUSE instruction after VM-entry at CPL 0. We must
3715 * consider this to be the first execution of PAUSE in a loop according
3716 * to the Intel.
3717 *
3718 * All subsequent records for the previous-PAUSE-tick we ensure that it
3719 * cannot be zero by OR'ing 1 to rule out the TSC wrap-around cases at 0.
3720 */
3721 uint64_t *puFirstPauseLoopTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick;
3722 uint64_t *puPrevPauseTick = &pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick;
3723 uint64_t const uTick = TMCpuTickGet(pVCpu);
3724 uint32_t const uPleGap = pVmcs->u32PleGap;
3725 uint32_t const uPleWindow = pVmcs->u32PleWindow;
3726 if ( *puPrevPauseTick == 0
3727 || uTick - *puPrevPauseTick > uPleGap)
3728 *puFirstPauseLoopTick = uTick;
3729 else if (uTick - *puFirstPauseLoopTick > uPleWindow)
3730 fIntercept = true;
3731
3732 *puPrevPauseTick = uTick | 1;
3733 }
3734
3735 if (fIntercept)
3736 {
3737 VMXVEXITINFO ExitInfo;
3738 RT_ZERO(ExitInfo);
3739 ExitInfo.uReason = VMX_EXIT_PAUSE;
3740 ExitInfo.cbInstr = cbInstr;
3741 return iemVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
3742 }
3743
3744 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3745}
3746
3747
3748/**
3749 * VMX VM-exit handler for VM-exits due to task switches.
3750 *
3751 * @returns VBox strict status code.
3752 * @param pVCpu The cross context virtual CPU structure.
3753 * @param enmTaskSwitch The cause of the task switch.
3754 * @param SelNewTss The selector of the new TSS.
3755 * @param cbInstr The instruction length in bytes.
3756 */
3757IEM_STATIC VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPU pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr)
3758{
3759 /*
3760 * Task-switch VM-exits are unconditional and provide the VM-exit qualification.
3761 *
3762 * If the cause of the task switch is due to execution of CALL, IRET or the JMP
3763 * instruction or delivery of the exception generated by one of these instructions
3764 * lead to a task switch through a task gate in the IDT, we need to provide the
3765 * VM-exit instruction length. Any other means of invoking a task switch VM-exit
3766 * leaves the VM-exit instruction length field undefined.
3767 *
3768 * See Intel spec. 25.2 "Other Causes Of VM Exits".
3769 * See Intel spec. 27.2.4 "Information for VM Exits Due to Instruction Execution".
3770 */
3771 Assert(cbInstr <= 15);
3772
3773 uint8_t uType;
3774 switch (enmTaskSwitch)
3775 {
3776 case IEMTASKSWITCH_CALL: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL; break;
3777 case IEMTASKSWITCH_IRET: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET; break;
3778 case IEMTASKSWITCH_JUMP: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP; break;
3779 case IEMTASKSWITCH_INT_XCPT: uType = VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT; break;
3780 IEM_NOT_REACHED_DEFAULT_CASE_RET();
3781 }
3782
3783 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS, SelNewTss)
3784 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE, uType);
3785 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
3786 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
3787 return iemVmxVmexit(pVCpu, VMX_EXIT_TASK_SWITCH);
3788}
3789
3790
3791/**
3792 * VMX VM-exit handler for VM-exits due to expiring of the preemption timer.
3793 *
3794 * @returns VBox strict status code.
3795 * @param pVCpu The cross context virtual CPU structure.
3796 */
3797IEM_STATIC VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPU pVCpu)
3798{
3799 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3800 Assert(pVmcs);
3801
3802 /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
3803 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
3804 {
3805 /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
3806 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
3807
3808 /*
3809 * Calculate the current VMX-preemption timer value.
3810 * Only if the value has reached zero, we cause the VM-exit.
3811 */
3812 uint32_t uPreemptTimer = iemVmxCalcPreemptTimer(pVCpu);
3813 if (!uPreemptTimer)
3814 {
3815 /* Save the VMX-preemption timer value (of 0) back in to the VMCS if the CPU supports this feature. */
3816 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER)
3817 pVmcs->u32PreemptTimer = 0;
3818
3819 /* Clear the force-flag indicating the VMX-preemption timer no longer active. */
3820 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
3821
3822 /* Cause the VMX-preemption timer VM-exit. The VM-exit qualification MBZ. */
3823 return iemVmxVmexit(pVCpu, VMX_EXIT_PREEMPT_TIMER);
3824 }
3825 }
3826
3827 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3828}
3829
3830
3831/**
3832 * VMX VM-exit handler for VM-exits due to external interrupts.
3833 *
3834 * @returns VBox strict status code.
3835 * @param pVCpu The cross context virtual CPU structure.
3836 * @param uVector The external interrupt vector (pass 0 if the interrupt
3837 * is still pending since we typically won't know the
3838 * vector).
3839 * @param fIntPending Whether the external interrupt is pending or
3840 * acknowledged in the interrupt controller.
3841 */
3842IEM_STATIC VBOXSTRICTRC iemVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
3843{
3844 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3845 Assert(pVmcs);
3846 Assert(fIntPending || uVector == 0);
3847
3848 /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
3849 * intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
3850 * functions require prior checking of a blanket intercept and which don't.
3851 * It is better for the caller to check a blanket intercept performance wise
3852 * than making a function call. Leaving this as a todo because it is more
3853 * a performance issue. */
3854
3855 /* The VM-exit is subject to "External interrupt exiting" being set. */
3856 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
3857 {
3858 if (fIntPending)
3859 {
3860 /*
3861 * If the interrupt is pending and we don't need to acknowledge the
3862 * interrupt on VM-exit, cause the VM-exit immediately.
3863 *
3864 * See Intel spec 25.2 "Other Causes Of VM Exits".
3865 */
3866 if (!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT))
3867 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3868
3869 /*
3870 * If the interrupt is pending and we -do- need to acknowledge the interrupt
3871 * on VM-exit, postpone VM-exit till after the interrupt controller has been
3872 * acknowledged that the interrupt has been consumed.
3873 */
3874 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3875 }
3876
3877 /*
3878 * If the interrupt is no longer pending (i.e. it has been acknowledged) and the
3879 * "External interrupt exiting" and "Acknowledge interrupt on VM-exit" controls are
3880 * all set, we cause the VM-exit now. We need to record the external interrupt that
3881 * just occurred in the VM-exit interruption information field.
3882 *
3883 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3884 */
3885 if (pVmcs->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
3886 {
3887 bool const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3888 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
3889 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_EXT_INT)
3890 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3891 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3892 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3893 return iemVmxVmexit(pVCpu, VMX_EXIT_EXT_INT);
3894 }
3895 }
3896
3897 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3898}
3899
3900
3901/**
3902 * VMX VM-exit handler for VM-exits due to startup-IPIs (SIPI).
3903 *
3904 * @returns VBox strict status code.
3905 * @param pVCpu The cross context virtual CPU structure.
3906 * @param uVector The SIPI vector.
3907 */
3908IEM_STATIC VBOXSTRICTRC iemVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
3909{
3910 iemVmxVmcsSetExitQual(pVCpu, uVector);
3911 return iemVmxVmexit(pVCpu, VMX_EXIT_SIPI);
3912}
3913
3914
3915/**
3916 * VMX VM-exit handler for VM-exits due to init-IPIs (INIT).
3917 *
3918 * @returns VBox strict status code.
3919 * @param pVCpu The cross context virtual CPU structure.
3920 */
3921IEM_STATIC VBOXSTRICTRC iemVmxVmexitInitIpi(PVMCPU pVCpu)
3922{
3923 return iemVmxVmexit(pVCpu, VMX_EXIT_INIT_SIGNAL);
3924}
3925
3926
3927/**
3928 * VMX VM-exit handler for interrupt-window VM-exits.
3929 *
3930 * @returns VBox strict status code.
3931 * @param pVCpu The cross context virtual CPU structure.
3932 */
3933IEM_STATIC VBOXSTRICTRC iemVmxVmexitIntWindow(PVMCPU pVCpu)
3934{
3935 return iemVmxVmexit(pVCpu, VMX_EXIT_INT_WINDOW);
3936}
3937
3938
3939/**
3940 * VMX VM-exit handler for VM-exits due to a double fault caused during delivery of
3941 * an event.
3942 *
3943 * @returns VBox strict status code.
3944 * @param pVCpu The cross context virtual CPU structure.
3945 */
3946IEM_STATIC VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPU pVCpu)
3947{
3948 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
3949 Assert(pVmcs);
3950
3951 uint32_t const fXcptBitmap = pVmcs->u32XcptBitmap;
3952 if (fXcptBitmap & RT_BIT(X86_XCPT_DF))
3953 {
3954 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
3955 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)
3956 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
3957 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, 1)
3958 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
3959 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
3960 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
3961 iemVmxVmcsSetExitIntErrCode(pVCpu, 0);
3962 iemVmxVmcsSetExitQual(pVCpu, 0);
3963 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
3964
3965 /*
3966 * A VM-exit is not considered to occur during event delivery when the original
3967 * event results in a double-fault that causes a VM-exit directly (i.e. intercepted
3968 * using the exception bitmap).
3969 *
3970 * Therefore, we must clear the original event from the IDT-vectoring fields which
3971 * would've been recorded before causing the VM-exit.
3972 *
3973 * 27.2.3 "Information for VM Exits During Event Delivery"
3974 */
3975 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
3976 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
3977
3978 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
3979 }
3980
3981 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
3982}
3983
3984
3985/**
3986 * VMX VM-exit handler for VM-exits due to delivery of an event.
3987 *
3988 * @returns VBox strict status code.
3989 * @param pVCpu The cross context virtual CPU structure.
3990 * @param uVector The interrupt / exception vector.
3991 * @param fFlags The flags (see IEM_XCPT_FLAGS_XXX).
3992 * @param uErrCode The error code associated with the event.
3993 * @param uCr2 The CR2 value in case of a \#PF exception.
3994 * @param cbInstr The instruction length in bytes.
3995 */
3996IEM_STATIC VBOXSTRICTRC iemVmxVmexitEvent(PVMCPU pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2,
3997 uint8_t cbInstr)
3998{
3999 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4000 Assert(pVmcs);
4001
4002 /*
4003 * If the event is being injected as part of VM-entry, it isn't subject to event
4004 * intercepts in the nested-guest. However, secondary exceptions that occur during
4005 * injection of any event -are- subject to event interception.
4006 *
4007 * See Intel spec. 26.5.1.2 "VM Exits During Event Injection".
4008 */
4009 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents)
4010 {
4011 /* Update the IDT-vectoring event in the VMCS as the source of the upcoming event. */
4012 uint8_t const uIdtVectoringType = iemVmxGetEventType(uVector, fFlags);
4013 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4014 uint32_t const uIdtVectoringInfo = RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, uVector)
4015 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, uIdtVectoringType)
4016 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID, fErrCodeValid)
4017 | RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1);
4018 iemVmxVmcsSetIdtVectoringInfo(pVCpu, uIdtVectoringInfo);
4019 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, uErrCode);
4020
4021 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = true;
4022 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4023 }
4024
4025 /*
4026 * We are injecting an external interrupt, check if we need to cause a VM-exit now.
4027 * If not, the caller will continue delivery of the external interrupt as it would
4028 * normally. The interrupt is no longer pending in the interrupt controller at this
4029 * point.
4030 */
4031 if (fFlags & IEM_XCPT_FLAGS_T_EXT_INT)
4032 {
4033 Assert(!VMX_IDT_VECTORING_INFO_IS_VALID(pVmcs->u32RoIdtVectoringInfo));
4034 return iemVmxVmexitExtInt(pVCpu, uVector, false /* fIntPending */);
4035 }
4036
4037 /*
4038 * Evaluate intercepts for hardware exceptions including #BP, #DB, #OF
4039 * generated by INT3, INT1 (ICEBP) and INTO respectively.
4040 */
4041 Assert(fFlags & (IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_T_SOFT_INT));
4042 bool fIntercept = false;
4043 bool fIsHwXcpt = false;
4044 if ( !(fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4045 || (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4046 {
4047 fIsHwXcpt = true;
4048 /* NMIs have a dedicated VM-execution control for causing VM-exits. */
4049 if (uVector == X86_XCPT_NMI)
4050 fIntercept = RT_BOOL(pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT);
4051 else
4052 {
4053 /* Page-faults are subject to masking using its error code. */
4054 uint32_t fXcptBitmap = pVmcs->u32XcptBitmap;
4055 if (uVector == X86_XCPT_PF)
4056 {
4057 uint32_t const fXcptPFMask = pVmcs->u32XcptPFMask;
4058 uint32_t const fXcptPFMatch = pVmcs->u32XcptPFMatch;
4059 if ((uErrCode & fXcptPFMask) != fXcptPFMatch)
4060 fXcptBitmap ^= RT_BIT(X86_XCPT_PF);
4061 }
4062
4063 /* Consult the exception bitmap for all hardware exceptions (except NMI). */
4064 if (fXcptBitmap & RT_BIT(uVector))
4065 fIntercept = true;
4066 }
4067 }
4068 /* else: Software interrupts cannot be intercepted and therefore do not cause a VM-exit. */
4069
4070 /*
4071 * Now that we've determined whether the software interrupt or hardware exception
4072 * causes a VM-exit, we need to construct the relevant VM-exit information and
4073 * cause the VM-exit.
4074 */
4075 if (fIntercept)
4076 {
4077 Assert(!(fFlags & IEM_XCPT_FLAGS_T_EXT_INT));
4078
4079 /* Construct the rest of the event related information fields and cause the VM-exit. */
4080 uint64_t uExitQual = 0;
4081 if (fIsHwXcpt)
4082 {
4083 if (uVector == X86_XCPT_PF)
4084 {
4085 Assert(fFlags & IEM_XCPT_FLAGS_CR2);
4086 uExitQual = uCr2;
4087 }
4088 else if (uVector == X86_XCPT_DB)
4089 {
4090 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
4091 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
4092 }
4093 }
4094
4095 uint8_t const fNmiUnblocking = pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret;
4096 bool const fErrCodeValid = RT_BOOL(fFlags & IEM_XCPT_FLAGS_ERR);
4097 uint8_t const uIntInfoType = iemVmxGetEventType(uVector, fFlags);
4098 uint32_t const uExitIntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, uVector)
4099 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, uIntInfoType)
4100 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID, fErrCodeValid)
4101 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET, fNmiUnblocking)
4102 | RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1);
4103 iemVmxVmcsSetExitIntInfo(pVCpu, uExitIntInfo);
4104 iemVmxVmcsSetExitIntErrCode(pVCpu, uErrCode);
4105 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4106
4107 /*
4108 * For VM exits due to software exceptions (those generated by INT3 or INTO) or privileged
4109 * software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
4110 * length.
4111 */
4112 if ( (fFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
4113 && (fFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_OF_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR)))
4114 iemVmxVmcsSetExitInstrLen(pVCpu, cbInstr);
4115 else
4116 iemVmxVmcsSetExitInstrLen(pVCpu, 0);
4117
4118 return iemVmxVmexit(pVCpu, VMX_EXIT_XCPT_OR_NMI);
4119 }
4120
4121 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4122}
4123
4124
4125/**
4126 * VMX VM-exit handler for VM-exits due to a triple fault.
4127 *
4128 * @returns VBox strict status code.
4129 * @param pVCpu The cross context virtual CPU structure.
4130 */
4131IEM_STATIC VBOXSTRICTRC iemVmxVmexitTripleFault(PVMCPU pVCpu)
4132{
4133 /*
4134 * A VM-exit is not considered to occur during event delivery when the original
4135 * event results in a triple-fault.
4136 *
4137 * Therefore, we must clear the original event from the IDT-vectoring fields which
4138 * would've been recorded before causing the VM-exit.
4139 *
4140 * 27.2.3 "Information for VM Exits During Event Delivery"
4141 */
4142 iemVmxVmcsSetIdtVectoringInfo(pVCpu, 0);
4143 iemVmxVmcsSetIdtVectoringErrCode(pVCpu, 0);
4144
4145 return iemVmxVmexit(pVCpu, VMX_EXIT_TRIPLE_FAULT);
4146}
4147
4148
4149/**
4150 * VMX VM-exit handler for APIC-accesses.
4151 *
4152 * @param pVCpu The cross context virtual CPU structure.
4153 * @param offAccess The offset of the register being accessed.
4154 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4155 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4156 */
4157IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicAccess(PVMCPU pVCpu, uint16_t offAccess, uint32_t fAccess)
4158{
4159 Assert((fAccess & IEM_ACCESS_TYPE_READ) || (fAccess & IEM_ACCESS_TYPE_WRITE) || (fAccess & IEM_ACCESS_INSTRUCTION));
4160
4161 VMXAPICACCESS enmAccess;
4162 bool const fInEventDelivery = IEMGetCurrentXcpt(pVCpu, NULL, NULL, NULL, NULL);
4163 if (fInEventDelivery)
4164 enmAccess = VMXAPICACCESS_LINEAR_EVENT_DELIVERY;
4165 else if (fAccess & IEM_ACCESS_INSTRUCTION)
4166 enmAccess = VMXAPICACCESS_LINEAR_INSTR_FETCH;
4167 else if (fAccess & IEM_ACCESS_TYPE_WRITE)
4168 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4169 else
4170 enmAccess = VMXAPICACCESS_LINEAR_WRITE;
4171
4172 uint64_t const uExitQual = RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET, offAccess)
4173 | RT_BF_MAKE(VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE, enmAccess);
4174 iemVmxVmcsSetExitQual(pVCpu, uExitQual);
4175 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_ACCESS);
4176}
4177
4178
4179/**
4180 * VMX VM-exit handler for APIC-write VM-exits.
4181 *
4182 * @param pVCpu The cross context virtual CPU structure.
4183 * @param offApic The write to the virtual-APIC page offset that caused this
4184 * VM-exit.
4185 */
4186IEM_STATIC VBOXSTRICTRC iemVmxVmexitApicWrite(PVMCPU pVCpu, uint16_t offApic)
4187{
4188 Assert(offApic < XAPIC_OFF_END + 4);
4189
4190 /* Write only bits 11:0 of the APIC offset into the VM-exit qualification field. */
4191 offApic &= UINT16_C(0xfff);
4192 iemVmxVmcsSetExitQual(pVCpu, offApic);
4193 return iemVmxVmexit(pVCpu, VMX_EXIT_APIC_WRITE);
4194}
4195
4196
4197/**
4198 * VMX VM-exit handler for virtualized-EOIs.
4199 *
4200 * @param pVCpu The cross context virtual CPU structure.
4201 */
4202IEM_STATIC VBOXSTRICTRC iemVmxVmexitVirtEoi(PVMCPU pVCpu, uint8_t uVector)
4203{
4204 iemVmxVmcsSetExitQual(pVCpu, uVector);
4205 return iemVmxVmexit(pVCpu, VMX_EXIT_VIRTUALIZED_EOI);
4206}
4207
4208
4209/**
4210 * Sets virtual-APIC write emulation as pending.
4211 *
4212 * @param pVCpu The cross context virtual CPU structure.
4213 * @param offApic The offset in the virtual-APIC page that was written.
4214 */
4215DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPU pVCpu, uint16_t offApic)
4216{
4217 Assert(offApic < XAPIC_OFF_END + 4);
4218
4219 /*
4220 * Record the currently updated APIC offset, as we need this later for figuring
4221 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4222 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4223 */
4224 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
4225
4226 /*
4227 * Signal that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
4228 * virtualization or APIC-write emulation).
4229 */
4230 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4231 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4232}
4233
4234
4235/**
4236 * Clears any pending virtual-APIC write emulation.
4237 *
4238 * @returns The virtual-APIC offset that was written before clearing it.
4239 * @param pVCpu The cross context virtual CPU structure.
4240 */
4241DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
4242{
4243 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
4244 uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
4245 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
4246 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE));
4247 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
4248 return offVirtApicWrite;
4249}
4250
4251
4252/**
4253 * Reads a 32-bit register from the virtual-APIC page at the given offset.
4254 *
4255 * @returns The register from the virtual-APIC page.
4256 * @param pVCpu The cross context virtual CPU structure.
4257 * @param offReg The offset of the register being read.
4258 */
4259DECLINLINE(uint32_t) iemVmxVirtApicReadRaw32(PVMCPU pVCpu, uint16_t offReg)
4260{
4261 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4262 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4263 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4264 uint32_t const uReg = *(const uint32_t *)(pbVirtApic + offReg);
4265 return uReg;
4266}
4267
4268
4269/**
4270 * Reads a 64-bit register from the virtual-APIC page at the given offset.
4271 *
4272 * @returns The register from the virtual-APIC page.
4273 * @param pVCpu The cross context virtual CPU structure.
4274 * @param offReg The offset of the register being read.
4275 */
4276DECLINLINE(uint64_t) iemVmxVirtApicReadRaw64(PVMCPU pVCpu, uint16_t offReg)
4277{
4278 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4279 uint8_t const *pbVirtApic = (const uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4280 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4281 uint64_t const uReg = *(const uint64_t *)(pbVirtApic + offReg);
4282 return uReg;
4283}
4284
4285
4286/**
4287 * Writes a 32-bit register to the virtual-APIC page at the given offset.
4288 *
4289 * @param pVCpu The cross context virtual CPU structure.
4290 * @param offReg The offset of the register being written.
4291 * @param uReg The register value to write.
4292 */
4293DECLINLINE(void) iemVmxVirtApicWriteRaw32(PVMCPU pVCpu, uint16_t offReg, uint32_t uReg)
4294{
4295 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4296 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4297 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4298 *(uint32_t *)(pbVirtApic + offReg) = uReg;
4299}
4300
4301
4302/**
4303 * Writes a 64-bit register to the virtual-APIC page at the given offset.
4304 *
4305 * @param pVCpu The cross context virtual CPU structure.
4306 * @param offReg The offset of the register being written.
4307 * @param uReg The register value to write.
4308 */
4309DECLINLINE(void) iemVmxVirtApicWriteRaw64(PVMCPU pVCpu, uint16_t offReg, uint64_t uReg)
4310{
4311 Assert(offReg <= VMX_V_VIRT_APIC_SIZE - sizeof(uint32_t));
4312 uint8_t *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
4313 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
4314 *(uint64_t *)(pbVirtApic + offReg) = uReg;
4315}
4316
4317
4318/**
4319 * Sets the vector in a virtual-APIC 256-bit sparse register.
4320 *
4321 * @param pVCpu The cross context virtual CPU structure.
4322 * @param offReg The offset of the 256-bit spare register.
4323 * @param uVector The vector to set.
4324 *
4325 * @remarks This is based on our APIC device code.
4326 */
4327DECLINLINE(void) iemVmxVirtApicSetVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4328{
4329 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4330 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4331 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4332 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4333 ASMAtomicBitSet(pbBitmap + offVector, idxVectorBit);
4334}
4335
4336
4337/**
4338 * Clears the vector in a virtual-APIC 256-bit sparse register.
4339 *
4340 * @param pVCpu The cross context virtual CPU structure.
4341 * @param offReg The offset of the 256-bit spare register.
4342 * @param uVector The vector to clear.
4343 *
4344 * @remarks This is based on our APIC device code.
4345 */
4346DECLINLINE(void) iemVmxVirtApicClearVector(PVMCPU pVCpu, uint16_t offReg, uint8_t uVector)
4347{
4348 Assert(offReg == XAPIC_OFF_ISR0 || offReg == XAPIC_OFF_TMR0 || offReg == XAPIC_OFF_IRR0);
4349 uint8_t *pbBitmap = ((uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage)) + offReg;
4350 uint16_t const offVector = (uVector & UINT32_C(0xe0)) >> 1;
4351 uint16_t const idxVectorBit = uVector & UINT32_C(0x1f);
4352 ASMAtomicBitClear(pbBitmap + offVector, idxVectorBit);
4353}
4354
4355
4356/**
4357 * Checks if a memory access to the APIC-access page must causes an APIC-access
4358 * VM-exit.
4359 *
4360 * @param pVCpu The cross context virtual CPU structure.
4361 * @param offAccess The offset of the register being accessed.
4362 * @param cbAccess The size of the access in bytes.
4363 * @param fAccess The type of access (must be IEM_ACCESS_TYPE_READ or
4364 * IEM_ACCESS_TYPE_WRITE).
4365 *
4366 * @remarks This must not be used for MSR-based APIC-access page accesses!
4367 * @sa iemVmxVirtApicAccessMsrWrite, iemVmxVirtApicAccessMsrRead.
4368 */
4369IEM_STATIC bool iemVmxVirtApicIsMemAccessIntercepted(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, uint32_t fAccess)
4370{
4371 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4372 Assert(pVmcs);
4373 Assert(fAccess == IEM_ACCESS_TYPE_READ || fAccess == IEM_ACCESS_TYPE_WRITE);
4374
4375 /*
4376 * We must cause a VM-exit if any of the following are true:
4377 * - TPR shadowing isn't active.
4378 * - The access size exceeds 32-bits.
4379 * - The access is not contained within low 4 bytes of a 16-byte aligned offset.
4380 *
4381 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4382 * See Intel spec. 29.4.3.1 "Determining Whether a Write Access is Virtualized".
4383 */
4384 if ( !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4385 || cbAccess > sizeof(uint32_t)
4386 || ((offAccess + cbAccess - 1) & 0xc)
4387 || offAccess >= XAPIC_OFF_END + 4)
4388 return true;
4389
4390 /*
4391 * If the access is part of an operation where we have already
4392 * virtualized a virtual-APIC write, we must cause a VM-exit.
4393 */
4394 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
4395 return true;
4396
4397 /*
4398 * Check write accesses to the APIC-access page that cause VM-exits.
4399 */
4400 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4401 {
4402 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4403 {
4404 /*
4405 * With APIC-register virtualization, a write access to any of the
4406 * following registers are virtualized. Accessing any other register
4407 * causes a VM-exit.
4408 */
4409 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4410 switch (offAlignedAccess)
4411 {
4412 case XAPIC_OFF_ID:
4413 case XAPIC_OFF_TPR:
4414 case XAPIC_OFF_EOI:
4415 case XAPIC_OFF_LDR:
4416 case XAPIC_OFF_DFR:
4417 case XAPIC_OFF_SVR:
4418 case XAPIC_OFF_ESR:
4419 case XAPIC_OFF_ICR_LO:
4420 case XAPIC_OFF_ICR_HI:
4421 case XAPIC_OFF_LVT_TIMER:
4422 case XAPIC_OFF_LVT_THERMAL:
4423 case XAPIC_OFF_LVT_PERF:
4424 case XAPIC_OFF_LVT_LINT0:
4425 case XAPIC_OFF_LVT_LINT1:
4426 case XAPIC_OFF_LVT_ERROR:
4427 case XAPIC_OFF_TIMER_ICR:
4428 case XAPIC_OFF_TIMER_DCR:
4429 break;
4430 default:
4431 return true;
4432 }
4433 }
4434 else if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4435 {
4436 /*
4437 * With virtual-interrupt delivery, a write access to any of the
4438 * following registers are virtualized. Accessing any other register
4439 * causes a VM-exit.
4440 *
4441 * Note! The specification does not allow writing to offsets in-between
4442 * these registers (e.g. TPR + 1 byte) unlike read accesses.
4443 */
4444 switch (offAccess)
4445 {
4446 case XAPIC_OFF_TPR:
4447 case XAPIC_OFF_EOI:
4448 case XAPIC_OFF_ICR_LO:
4449 break;
4450 default:
4451 return true;
4452 }
4453 }
4454 else
4455 {
4456 /*
4457 * Without APIC-register virtualization or virtual-interrupt delivery,
4458 * only TPR accesses are virtualized.
4459 */
4460 if (offAccess == XAPIC_OFF_TPR)
4461 { /* likely */ }
4462 else
4463 return true;
4464 }
4465 }
4466 else
4467 {
4468 /*
4469 * Check read accesses to the APIC-access page that cause VM-exits.
4470 */
4471 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4472 {
4473 /*
4474 * With APIC-register virtualization, a read access to any of the
4475 * following registers are virtualized. Accessing any other register
4476 * causes a VM-exit.
4477 */
4478 uint16_t const offAlignedAccess = offAccess & 0xfffc;
4479 switch (offAlignedAccess)
4480 {
4481 /** @todo r=ramshankar: What about XAPIC_OFF_LVT_CMCI? */
4482 case XAPIC_OFF_ID:
4483 case XAPIC_OFF_VERSION:
4484 case XAPIC_OFF_TPR:
4485 case XAPIC_OFF_EOI:
4486 case XAPIC_OFF_LDR:
4487 case XAPIC_OFF_DFR:
4488 case XAPIC_OFF_SVR:
4489 case XAPIC_OFF_ISR0: case XAPIC_OFF_ISR1: case XAPIC_OFF_ISR2: case XAPIC_OFF_ISR3:
4490 case XAPIC_OFF_ISR4: case XAPIC_OFF_ISR5: case XAPIC_OFF_ISR6: case XAPIC_OFF_ISR7:
4491 case XAPIC_OFF_TMR0: case XAPIC_OFF_TMR1: case XAPIC_OFF_TMR2: case XAPIC_OFF_TMR3:
4492 case XAPIC_OFF_TMR4: case XAPIC_OFF_TMR5: case XAPIC_OFF_TMR6: case XAPIC_OFF_TMR7:
4493 case XAPIC_OFF_IRR0: case XAPIC_OFF_IRR1: case XAPIC_OFF_IRR2: case XAPIC_OFF_IRR3:
4494 case XAPIC_OFF_IRR4: case XAPIC_OFF_IRR5: case XAPIC_OFF_IRR6: case XAPIC_OFF_IRR7:
4495 case XAPIC_OFF_ESR:
4496 case XAPIC_OFF_ICR_LO:
4497 case XAPIC_OFF_ICR_HI:
4498 case XAPIC_OFF_LVT_TIMER:
4499 case XAPIC_OFF_LVT_THERMAL:
4500 case XAPIC_OFF_LVT_PERF:
4501 case XAPIC_OFF_LVT_LINT0:
4502 case XAPIC_OFF_LVT_LINT1:
4503 case XAPIC_OFF_LVT_ERROR:
4504 case XAPIC_OFF_TIMER_ICR:
4505 case XAPIC_OFF_TIMER_DCR:
4506 break;
4507 default:
4508 return true;
4509 }
4510 }
4511 else
4512 {
4513 /* Without APIC-register virtualization, only TPR accesses are virtualized. */
4514 if (offAccess == XAPIC_OFF_TPR)
4515 { /* likely */ }
4516 else
4517 return true;
4518 }
4519 }
4520
4521 /* The APIC-access is virtualized, does not cause a VM-exit. */
4522 return false;
4523}
4524
4525
4526/**
4527 * Virtualizes a memory-based APIC-access where the address is not used to access
4528 * memory.
4529 *
4530 * This is for instructions like MONITOR, CLFLUSH, CLFLUSHOPT, ENTER which may cause
4531 * page-faults but do not use the address to access memory.
4532 *
4533 * @param pVCpu The cross context virtual CPU structure.
4534 * @param pGCPhysAccess Pointer to the guest-physical address used.
4535 */
4536IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPU pVCpu, PRTGCPHYS pGCPhysAccess)
4537{
4538 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4539 Assert(pVmcs);
4540 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
4541 Assert(pGCPhysAccess);
4542
4543 RTGCPHYS const GCPhysAccess = *pGCPhysAccess & ~(RTGCPHYS)PAGE_OFFSET_MASK;
4544 RTGCPHYS const GCPhysApic = pVmcs->u64AddrApicAccess.u;
4545 Assert(!(GCPhysApic & PAGE_OFFSET_MASK));
4546
4547 if (GCPhysAccess == GCPhysApic)
4548 {
4549 uint16_t const offAccess = *pGCPhysAccess & PAGE_OFFSET_MASK;
4550 uint32_t const fAccess = IEM_ACCESS_TYPE_READ;
4551 uint16_t const cbAccess = 1;
4552 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4553 if (fIntercept)
4554 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4555
4556 *pGCPhysAccess = GCPhysApic | offAccess;
4557 return VINF_VMX_MODIFIES_BEHAVIOR;
4558 }
4559
4560 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4561}
4562
4563
4564/**
4565 * Virtualizes a memory-based APIC-access.
4566 *
4567 * @returns VBox strict status code.
4568 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
4569 * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
4570 *
4571 * @param pVCpu The cross context virtual CPU structure.
4572 * @param offAccess The offset of the register being accessed (within the
4573 * APIC-access page).
4574 * @param cbAccess The size of the access in bytes.
4575 * @param pvData Pointer to the data being written or where to store the data
4576 * being read.
4577 * @param fAccess The type of access (must contain IEM_ACCESS_TYPE_READ or
4578 * IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
4579 */
4580IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
4581 uint32_t fAccess)
4582{
4583 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4584 Assert(pVmcs);
4585 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS); NOREF(pVmcs);
4586 Assert(pvData);
4587 Assert( (fAccess & IEM_ACCESS_TYPE_READ)
4588 || (fAccess & IEM_ACCESS_TYPE_WRITE)
4589 || (fAccess & IEM_ACCESS_INSTRUCTION));
4590
4591 bool const fIntercept = iemVmxVirtApicIsMemAccessIntercepted(pVCpu, offAccess, cbAccess, fAccess);
4592 if (fIntercept)
4593 return iemVmxVmexitApicAccess(pVCpu, offAccess, fAccess);
4594
4595 if (fAccess & IEM_ACCESS_TYPE_WRITE)
4596 {
4597 /*
4598 * A write access to the APIC-access page that is virtualized (rather than
4599 * causing a VM-exit) writes data to the virtual-APIC page.
4600 */
4601 uint32_t const u32Data = *(uint32_t *)pvData;
4602 iemVmxVirtApicWriteRaw32(pVCpu, offAccess, u32Data);
4603
4604 /*
4605 * Record the currently updated APIC offset, as we need this later for figuring
4606 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4607 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4608 *
4609 * After completion of the current operation, we need to perform TPR virtualization,
4610 * EOI virtualization or APIC-write VM-exit depending on which register was written.
4611 *
4612 * The current operation may be a REP-prefixed string instruction, execution of any
4613 * other instruction, or delivery of an event through the IDT.
4614 *
4615 * Thus things like clearing bytes 3:1 of the VTPR, clearing VEOI are not to be
4616 * performed now but later after completion of the current operation.
4617 *
4618 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
4619 */
4620 iemVmxVirtApicSetPendingWrite(pVCpu, offAccess);
4621 }
4622 else
4623 {
4624 /*
4625 * A read access from the APIC-access page that is virtualized (rather than
4626 * causing a VM-exit) returns data from the virtual-APIC page.
4627 *
4628 * See Intel spec. 29.4.2 "Virtualizing Reads from the APIC-Access Page".
4629 */
4630 Assert(cbAccess <= 4);
4631 Assert(offAccess < XAPIC_OFF_END + 4);
4632 static uint32_t const s_auAccessSizeMasks[] = { 0, 0xff, 0xffff, 0xffffff, 0xffffffff };
4633
4634 uint32_t u32Data = iemVmxVirtApicReadRaw32(pVCpu, offAccess);
4635 u32Data &= s_auAccessSizeMasks[cbAccess];
4636 *(uint32_t *)pvData = u32Data;
4637 }
4638
4639 return VINF_VMX_MODIFIES_BEHAVIOR;
4640}
4641
4642
4643/**
4644 * Virtualizes an MSR-based APIC read access.
4645 *
4646 * @returns VBox strict status code.
4647 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR read was virtualized.
4648 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR read access must be
4649 * handled by the x2APIC device.
4650 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4651 * not within the range of valid MSRs, caller must raise \#GP(0).
4652 * @param pVCpu The cross context virtual CPU structure.
4653 * @param idMsr The x2APIC MSR being read.
4654 * @param pu64Value Where to store the read x2APIC MSR value (only valid when
4655 * VINF_VMX_MODIFIES_BEHAVIOR is returned).
4656 */
4657IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrRead(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value)
4658{
4659 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4660 Assert(pVmcs);
4661 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
4662 Assert(pu64Value);
4663
4664 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
4665 {
4666 /*
4667 * Intel has different ideas in the x2APIC spec. vs the VT-x spec. as to
4668 * what the end of the valid x2APIC MSR range is. Hence the use of different
4669 * macros here.
4670 *
4671 * See Intel spec. 10.12.1.2 "x2APIC Register Address Space".
4672 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4673 */
4674 if ( idMsr >= VMX_V_VIRT_APIC_MSR_START
4675 && idMsr <= VMX_V_VIRT_APIC_MSR_END)
4676 {
4677 uint16_t const offReg = (idMsr & 0xff) << 4;
4678 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4679 *pu64Value = u64Value;
4680 return VINF_VMX_MODIFIES_BEHAVIOR;
4681 }
4682 return VERR_OUT_OF_RANGE;
4683 }
4684
4685 if (idMsr == MSR_IA32_X2APIC_TPR)
4686 {
4687 uint16_t const offReg = (idMsr & 0xff) << 4;
4688 uint64_t const u64Value = iemVmxVirtApicReadRaw64(pVCpu, offReg);
4689 *pu64Value = u64Value;
4690 return VINF_VMX_MODIFIES_BEHAVIOR;
4691 }
4692
4693 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4694}
4695
4696
4697/**
4698 * Virtualizes an MSR-based APIC write access.
4699 *
4700 * @returns VBox strict status code.
4701 * @retval VINF_VMX_MODIFIES_BEHAVIOR if the MSR write was virtualized.
4702 * @retval VERR_OUT_RANGE if the MSR read was supposed to be virtualized but was
4703 * not within the range of valid MSRs, caller must raise \#GP(0).
4704 * @retval VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR must be written normally.
4705 *
4706 * @param pVCpu The cross context virtual CPU structure.
4707 * @param idMsr The x2APIC MSR being written.
4708 * @param u64Value The value of the x2APIC MSR being written.
4709 */
4710IEM_STATIC VBOXSTRICTRC iemVmxVirtApicAccessMsrWrite(PVMCPU pVCpu, uint32_t idMsr, uint64_t u64Value)
4711{
4712 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4713 Assert(pVmcs);
4714
4715 /*
4716 * Check if the access is to be virtualized.
4717 * See Intel spec. 29.5 "Virtualizing MSR-based APIC Accesses".
4718 */
4719 if ( idMsr == MSR_IA32_X2APIC_TPR
4720 || ( (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
4721 && ( idMsr == MSR_IA32_X2APIC_EOI
4722 || idMsr == MSR_IA32_X2APIC_SELF_IPI)))
4723 {
4724 /* Validate the MSR write depending on the register. */
4725 switch (idMsr)
4726 {
4727 case MSR_IA32_X2APIC_TPR:
4728 case MSR_IA32_X2APIC_SELF_IPI:
4729 {
4730 if (u64Value & UINT64_C(0xffffffffffffff00))
4731 return VERR_OUT_OF_RANGE;
4732 break;
4733 }
4734 case MSR_IA32_X2APIC_EOI:
4735 {
4736 if (u64Value != 0)
4737 return VERR_OUT_OF_RANGE;
4738 break;
4739 }
4740 }
4741
4742 /* Write the MSR to the virtual-APIC page. */
4743 uint16_t const offReg = (idMsr & 0xff) << 4;
4744 iemVmxVirtApicWriteRaw64(pVCpu, offReg, u64Value);
4745
4746 /*
4747 * Record the currently updated APIC offset, as we need this later for figuring
4748 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
4749 * as for supplying the exit qualification when causing an APIC-write VM-exit.
4750 */
4751 iemVmxVirtApicSetPendingWrite(pVCpu, offReg);
4752
4753 return VINF_VMX_MODIFIES_BEHAVIOR;
4754 }
4755
4756 return VINF_VMX_INTERCEPT_NOT_ACTIVE;
4757}
4758
4759
4760/**
4761 * Finds the most significant set bit in a virtual-APIC 256-bit sparse register.
4762 *
4763 * @returns VBox status code.
4764 * @retval VINF_SUCCES when the highest set bit is found.
4765 * @retval VERR_NOT_FOUND when no bit is set.
4766 *
4767 * @param pVCpu The cross context virtual CPU structure.
4768 * @param offReg The offset of the APIC 256-bit sparse register.
4769 * @param pidxHighestBit Where to store the highest bit (most significant bit)
4770 * set in the register. Only valid when VINF_SUCCESS is
4771 * returned.
4772 *
4773 * @remarks The format of the 256-bit sparse register here mirrors that found in
4774 * real APIC hardware.
4775 */
4776static int iemVmxVirtApicGetHighestSetBitInReg(PVMCPU pVCpu, uint16_t offReg, uint8_t *pidxHighestBit)
4777{
4778 Assert(offReg < XAPIC_OFF_END + 4);
4779 Assert(pidxHighestBit);
4780
4781 /*
4782 * There are 8 contiguous fragments (of 16-bytes each) in the sparse register.
4783 * However, in each fragment only the first 4 bytes are used.
4784 */
4785 uint8_t const cFrags = 8;
4786 for (int8_t iFrag = cFrags; iFrag >= 0; iFrag--)
4787 {
4788 uint16_t const offFrag = iFrag * 16;
4789 uint32_t const u32Frag = iemVmxVirtApicReadRaw32(pVCpu, offReg + offFrag);
4790 if (!u32Frag)
4791 continue;
4792
4793 unsigned idxHighestBit = ASMBitLastSetU32(u32Frag);
4794 Assert(idxHighestBit > 0);
4795 --idxHighestBit;
4796 Assert(idxHighestBit <= UINT8_MAX);
4797 *pidxHighestBit = idxHighestBit;
4798 return VINF_SUCCESS;
4799 }
4800 return VERR_NOT_FOUND;
4801}
4802
4803
4804/**
4805 * Evaluates pending virtual interrupts.
4806 *
4807 * @param pVCpu The cross context virtual CPU structure.
4808 */
4809IEM_STATIC void iemVmxEvalPendingVirtIntrs(PVMCPU pVCpu)
4810{
4811 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4812 Assert(pVmcs);
4813 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4814
4815 if (!(pVmcs->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
4816 {
4817 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4818 uint8_t const uPpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_PPR);
4819
4820 if ((uRvi >> 4) > (uPpr >> 4))
4821 {
4822 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Signaling pending interrupt\n", uRvi, uPpr));
4823 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
4824 }
4825 else
4826 Log2(("eval_virt_intrs: uRvi=%#x uPpr=%#x - Nothing to do\n", uRvi, uPpr));
4827 }
4828}
4829
4830
4831/**
4832 * Performs PPR virtualization.
4833 *
4834 * @returns VBox strict status code.
4835 * @param pVCpu The cross context virtual CPU structure.
4836 */
4837IEM_STATIC void iemVmxPprVirtualization(PVMCPU pVCpu)
4838{
4839 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4840 Assert(pVmcs);
4841 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4842 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4843
4844 /*
4845 * PPR virtualization is caused in response to a VM-entry, TPR-virtualization,
4846 * or EOI-virtualization.
4847 *
4848 * See Intel spec. 29.1.3 "PPR Virtualization".
4849 */
4850 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4851 uint32_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4852
4853 uint32_t uPpr;
4854 if (((uTpr >> 4) & 0xf) >= ((uSvi >> 4) & 0xf))
4855 uPpr = uTpr & 0xff;
4856 else
4857 uPpr = uSvi & 0xf0;
4858
4859 Log2(("ppr_virt: uTpr=%#x uSvi=%#x uPpr=%#x\n", uTpr, uSvi, uPpr));
4860 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_PPR, uPpr);
4861}
4862
4863
4864/**
4865 * Performs VMX TPR virtualization.
4866 *
4867 * @returns VBox strict status code.
4868 * @param pVCpu The cross context virtual CPU structure.
4869 */
4870IEM_STATIC VBOXSTRICTRC iemVmxTprVirtualization(PVMCPU pVCpu)
4871{
4872 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4873 Assert(pVmcs);
4874 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4875
4876 /*
4877 * We should have already performed the virtual-APIC write to the TPR offset
4878 * in the virtual-APIC page. We now perform TPR virtualization.
4879 *
4880 * See Intel spec. 29.1.2 "TPR Virtualization".
4881 */
4882 if (!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
4883 {
4884 uint32_t const uTprThreshold = pVmcs->u32TprThreshold;
4885 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
4886
4887 /*
4888 * If the VTPR falls below the TPR threshold, we must cause a VM-exit.
4889 * See Intel spec. 29.1.2 "TPR Virtualization".
4890 */
4891 if (((uTpr >> 4) & 0xf) < uTprThreshold)
4892 {
4893 Log2(("tpr_virt: uTpr=%u uTprThreshold=%u -> VM-exit\n", uTpr, uTprThreshold));
4894 return iemVmxVmexit(pVCpu, VMX_EXIT_TPR_BELOW_THRESHOLD);
4895 }
4896 }
4897 else
4898 {
4899 iemVmxPprVirtualization(pVCpu);
4900 iemVmxEvalPendingVirtIntrs(pVCpu);
4901 }
4902
4903 return VINF_SUCCESS;
4904}
4905
4906
4907/**
4908 * Checks whether an EOI write for the given interrupt vector causes a VM-exit or
4909 * not.
4910 *
4911 * @returns @c true if the EOI write is intercepted, @c false otherwise.
4912 * @param pVCpu The cross context virtual CPU structure.
4913 * @param uVector The interrupt that was acknowledged using an EOI.
4914 */
4915IEM_STATIC bool iemVmxIsEoiInterceptSet(PVMCPU pVCpu, uint8_t uVector)
4916{
4917 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4918 Assert(pVmcs);
4919 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4920
4921 if (uVector < 64)
4922 return RT_BOOL(pVmcs->u64EoiExitBitmap0.u & RT_BIT_64(uVector));
4923 if (uVector < 128)
4924 return RT_BOOL(pVmcs->u64EoiExitBitmap1.u & RT_BIT_64(uVector));
4925 if (uVector < 192)
4926 return RT_BOOL(pVmcs->u64EoiExitBitmap2.u & RT_BIT_64(uVector));
4927 return RT_BOOL(pVmcs->u64EoiExitBitmap3.u & RT_BIT_64(uVector));
4928}
4929
4930
4931/**
4932 * Performs EOI virtualization.
4933 *
4934 * @returns VBox strict status code.
4935 * @param pVCpu The cross context virtual CPU structure.
4936 */
4937IEM_STATIC VBOXSTRICTRC iemVmxEoiVirtualization(PVMCPU pVCpu)
4938{
4939 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4940 Assert(pVmcs);
4941 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
4942
4943 /*
4944 * Clear the interrupt guest-interrupt as no longer in-service (ISR)
4945 * and get the next guest-interrupt that's in-service (if any).
4946 *
4947 * See Intel spec. 29.1.4 "EOI Virtualization".
4948 */
4949 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4950 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4951 Log2(("eoi_virt: uRvi=%#x uSvi=%#x\n", uRvi, uSvi));
4952
4953 uint8_t uVector = uSvi;
4954 iemVmxVirtApicClearVector(pVCpu, XAPIC_OFF_ISR0, uVector);
4955
4956 uVector = 0;
4957 iemVmxVirtApicGetHighestSetBitInReg(pVCpu, XAPIC_OFF_ISR0, &uVector);
4958
4959 if (uVector)
4960 Log2(("eoi_virt: next interrupt %#x\n", uVector));
4961 else
4962 Log2(("eoi_virt: no interrupt pending in ISR\n"));
4963
4964 /* Update guest-interrupt status SVI (leave RVI portion as it is) in the VMCS. */
4965 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uRvi, uVector);
4966
4967 iemVmxPprVirtualization(pVCpu);
4968 if (iemVmxIsEoiInterceptSet(pVCpu, uVector))
4969 return iemVmxVmexitVirtEoi(pVCpu, uVector);
4970 iemVmxEvalPendingVirtIntrs(pVCpu);
4971 return VINF_SUCCESS;
4972}
4973
4974
4975/**
4976 * Performs self-IPI virtualization.
4977 *
4978 * @returns VBox strict status code.
4979 * @param pVCpu The cross context virtual CPU structure.
4980 */
4981IEM_STATIC VBOXSTRICTRC iemVmxSelfIpiVirtualization(PVMCPU pVCpu)
4982{
4983 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
4984 Assert(pVmcs);
4985 Assert(pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
4986
4987 /*
4988 * We should have already performed the virtual-APIC write to the self-IPI offset
4989 * in the virtual-APIC page. We now perform self-IPI virtualization.
4990 *
4991 * See Intel spec. 29.1.5 "Self-IPI Virtualization".
4992 */
4993 uint8_t const uVector = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_LO);
4994 Log2(("self_ipi_virt: uVector=%#x\n", uVector));
4995 iemVmxVirtApicSetVector(pVCpu, XAPIC_OFF_IRR0, uVector);
4996 uint8_t const uRvi = RT_LO_U8(pVmcs->u16GuestIntStatus);
4997 uint8_t const uSvi = RT_HI_U8(pVmcs->u16GuestIntStatus);
4998 if (uVector > uRvi)
4999 pVmcs->u16GuestIntStatus = RT_MAKE_U16(uVector, uSvi);
5000 iemVmxEvalPendingVirtIntrs(pVCpu);
5001 return VINF_SUCCESS;
5002}
5003
5004
5005/**
5006 * Performs VMX APIC-write emulation.
5007 *
5008 * @returns VBox strict status code.
5009 * @param pVCpu The cross context virtual CPU structure.
5010 */
5011IEM_STATIC VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPU pVCpu)
5012{
5013 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5014 Assert(pVmcs);
5015
5016 /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
5017 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
5018
5019 /*
5020 * Perform APIC-write emulation based on the virtual-APIC register written.
5021 * See Intel spec. 29.4.3.2 "APIC-Write Emulation".
5022 */
5023 uint16_t const offApicWrite = iemVmxVirtApicClearPendingWrite(pVCpu);
5024 VBOXSTRICTRC rcStrict;
5025 switch (offApicWrite)
5026 {
5027 case XAPIC_OFF_TPR:
5028 {
5029 /* Clear bytes 3:1 of the VTPR and perform TPR virtualization. */
5030 uint32_t uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5031 uTpr &= UINT32_C(0x000000ff);
5032 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
5033 Log2(("iemVmxApicWriteEmulation: TPR write %#x\n", uTpr));
5034 rcStrict = iemVmxTprVirtualization(pVCpu);
5035 break;
5036 }
5037
5038 case XAPIC_OFF_EOI:
5039 {
5040 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5041 {
5042 /* Clear VEOI and perform EOI virtualization. */
5043 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_EOI, 0);
5044 Log2(("iemVmxApicWriteEmulation: EOI write\n"));
5045 rcStrict = iemVmxEoiVirtualization(pVCpu);
5046 }
5047 else
5048 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5049 break;
5050 }
5051
5052 case XAPIC_OFF_ICR_LO:
5053 {
5054 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
5055 {
5056 /* If the ICR_LO is valid, write it and perform self-IPI virtualization. */
5057 uint32_t const uIcrLo = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5058 uint32_t const fIcrLoMb0 = UINT32_C(0xfffbb700);
5059 uint32_t const fIcrLoMb1 = UINT32_C(0x000000f0);
5060 if ( !(uIcrLo & fIcrLoMb0)
5061 && (uIcrLo & fIcrLoMb1))
5062 {
5063 Log2(("iemVmxApicWriteEmulation: Self-IPI virtualization with vector %#x\n", (uIcrLo & 0xff)));
5064 rcStrict = iemVmxSelfIpiVirtualization(pVCpu);
5065 }
5066 else
5067 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5068 }
5069 else
5070 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5071 break;
5072 }
5073
5074 case XAPIC_OFF_ICR_HI:
5075 {
5076 /* Clear bytes 2:0 of VICR_HI. No other virtualization or VM-exit must occur. */
5077 uint32_t uIcrHi = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_ICR_HI);
5078 uIcrHi &= UINT32_C(0xff000000);
5079 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_ICR_HI, uIcrHi);
5080 rcStrict = VINF_SUCCESS;
5081 break;
5082 }
5083
5084 default:
5085 {
5086 /* Writes to any other virtual-APIC register causes an APIC-write VM-exit. */
5087 rcStrict = iemVmxVmexitApicWrite(pVCpu, offApicWrite);
5088 break;
5089 }
5090 }
5091
5092 return rcStrict;
5093}
5094
5095
5096/**
5097 * Checks guest control registers, debug registers and MSRs as part of VM-entry.
5098 *
5099 * @param pVCpu The cross context virtual CPU structure.
5100 * @param pszInstr The VMX instruction name (for logging purposes).
5101 */
5102IEM_STATIC int iemVmxVmentryCheckGuestControlRegsMsrs(PVMCPU pVCpu, const char *pszInstr)
5103{
5104 /*
5105 * Guest Control Registers, Debug Registers, and MSRs.
5106 * See Intel spec. 26.3.1.1 "Checks on Guest Control Registers, Debug Registers, and MSRs".
5107 */
5108 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5109 const char *const pszFailure = "VM-exit";
5110 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5111
5112 /* CR0 reserved bits. */
5113 {
5114 /* CR0 MB1 bits. */
5115 uint64_t u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
5116 Assert(!(u64Cr0Fixed0 & (X86_CR0_NW | X86_CR0_CD)));
5117 if (fUnrestrictedGuest)
5118 u64Cr0Fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
5119 if ((pVmcs->u64GuestCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
5120 { /* likely */ }
5121 else
5122 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed0);
5123
5124 /* CR0 MBZ bits. */
5125 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5126 if (!(pVmcs->u64GuestCr0.u & ~u64Cr0Fixed1))
5127 { /* likely */ }
5128 else
5129 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0Fixed1);
5130
5131 /* Without unrestricted guest support, VT-x supports does not support unpaged protected mode. */
5132 if ( !fUnrestrictedGuest
5133 && (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5134 && !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5135 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr0PgPe);
5136 }
5137
5138 /* CR4 reserved bits. */
5139 {
5140 /* CR4 MB1 bits. */
5141 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
5142 if ((pVmcs->u64GuestCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
5143 { /* likely */ }
5144 else
5145 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed0);
5146
5147 /* CR4 MBZ bits. */
5148 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
5149 if (!(pVmcs->u64GuestCr4.u & ~u64Cr4Fixed1))
5150 { /* likely */ }
5151 else
5152 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr4Fixed1);
5153 }
5154
5155 /* DEBUGCTL MSR. */
5156 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5157 || !(pVmcs->u64GuestDebugCtlMsr.u & ~MSR_IA32_DEBUGCTL_VALID_MASK_INTEL))
5158 { /* likely */ }
5159 else
5160 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDebugCtl);
5161
5162 /* 64-bit CPU checks. */
5163 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5164 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5165 {
5166 if (fGstInLongMode)
5167 {
5168 /* PAE must be set. */
5169 if ( (pVmcs->u64GuestCr0.u & X86_CR0_PG)
5170 && (pVmcs->u64GuestCr0.u & X86_CR4_PAE))
5171 { /* likely */ }
5172 else
5173 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPae);
5174 }
5175 else
5176 {
5177 /* PCIDE should not be set. */
5178 if (!(pVmcs->u64GuestCr4.u & X86_CR4_PCIDE))
5179 { /* likely */ }
5180 else
5181 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPcide);
5182 }
5183
5184 /* CR3. */
5185 if (!(pVmcs->u64GuestCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
5186 { /* likely */ }
5187 else
5188 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestCr3);
5189
5190 /* DR7. */
5191 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
5192 || !(pVmcs->u64GuestDr7.u & X86_DR7_MBZ_MASK))
5193 { /* likely */ }
5194 else
5195 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestDr7);
5196
5197 /* SYSENTER ESP and SYSENTER EIP. */
5198 if ( X86_IS_CANONICAL(pVmcs->u64GuestSysenterEsp.u)
5199 && X86_IS_CANONICAL(pVmcs->u64GuestSysenterEip.u))
5200 { /* likely */ }
5201 else
5202 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSysenterEspEip);
5203 }
5204
5205 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
5206 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
5207
5208 /* PAT MSR. */
5209 if ( !(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
5210 || CPUMIsPatMsrValid(pVmcs->u64GuestPatMsr.u))
5211 { /* likely */ }
5212 else
5213 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPatMsr);
5214
5215 /* EFER MSR. */
5216 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
5217 {
5218 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
5219 if (!(pVmcs->u64GuestEferMsr.u & ~uValidEferMask))
5220 { /* likely */ }
5221 else
5222 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsrRsvd);
5223
5224 bool const fGstLma = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LMA);
5225 bool const fGstLme = RT_BOOL(pVmcs->u64GuestEferMsr.u & MSR_K6_EFER_LME);
5226 if ( fGstLma == fGstInLongMode
5227 && ( !(pVmcs->u64GuestCr0.u & X86_CR0_PG)
5228 || fGstLma == fGstLme))
5229 { /* likely */ }
5230 else
5231 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestEferMsr);
5232 }
5233
5234 /* We don't support IA32_BNDCFGS MSR yet. */
5235 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
5236
5237 NOREF(pszInstr);
5238 NOREF(pszFailure);
5239 return VINF_SUCCESS;
5240}
5241
5242
5243/**
5244 * Checks guest segment registers, LDTR and TR as part of VM-entry.
5245 *
5246 * @param pVCpu The cross context virtual CPU structure.
5247 * @param pszInstr The VMX instruction name (for logging purposes).
5248 */
5249IEM_STATIC int iemVmxVmentryCheckGuestSegRegs(PVMCPU pVCpu, const char *pszInstr)
5250{
5251 /*
5252 * Segment registers.
5253 * See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
5254 */
5255 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5256 const char *const pszFailure = "VM-exit";
5257 bool const fGstInV86Mode = RT_BOOL(pVmcs->u64GuestRFlags.u & X86_EFL_VM);
5258 bool const fUnrestrictedGuest = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
5259 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5260
5261 /* Selectors. */
5262 if ( !fGstInV86Mode
5263 && !fUnrestrictedGuest
5264 && (pVmcs->GuestSs & X86_SEL_RPL) != (pVmcs->GuestCs & X86_SEL_RPL))
5265 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelCsSsRpl);
5266
5267 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
5268 {
5269 CPUMSELREG SelReg;
5270 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &SelReg);
5271 if (RT_LIKELY(rc == VINF_SUCCESS))
5272 { /* likely */ }
5273 else
5274 return rc;
5275
5276 /*
5277 * Virtual-8086 mode checks.
5278 */
5279 if (fGstInV86Mode)
5280 {
5281 /* Base address. */
5282 if (SelReg.u64Base == (uint64_t)SelReg.Sel << 4)
5283 { /* likely */ }
5284 else
5285 {
5286 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBaseV86(iSegReg);
5287 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5288 }
5289
5290 /* Limit. */
5291 if (SelReg.u32Limit == 0xffff)
5292 { /* likely */ }
5293 else
5294 {
5295 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegLimitV86(iSegReg);
5296 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5297 }
5298
5299 /* Attribute. */
5300 if (SelReg.Attr.u == 0xf3)
5301 { /* likely */ }
5302 else
5303 {
5304 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrV86(iSegReg);
5305 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5306 }
5307
5308 /* We're done; move to checking the next segment. */
5309 continue;
5310 }
5311
5312 /* Checks done by 64-bit CPUs. */
5313 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5314 {
5315 /* Base address. */
5316 if ( iSegReg == X86_SREG_FS
5317 || iSegReg == X86_SREG_GS)
5318 {
5319 if (X86_IS_CANONICAL(SelReg.u64Base))
5320 { /* likely */ }
5321 else
5322 {
5323 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5324 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5325 }
5326 }
5327 else if (iSegReg == X86_SREG_CS)
5328 {
5329 if (!RT_HI_U32(SelReg.u64Base))
5330 { /* likely */ }
5331 else
5332 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseCs);
5333 }
5334 else
5335 {
5336 if ( SelReg.Attr.n.u1Unusable
5337 || !RT_HI_U32(SelReg.u64Base))
5338 { /* likely */ }
5339 else
5340 {
5341 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegBase(iSegReg);
5342 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5343 }
5344 }
5345 }
5346
5347 /*
5348 * Checks outside Virtual-8086 mode.
5349 */
5350 uint8_t const uSegType = SelReg.Attr.n.u4Type;
5351 uint8_t const fCodeDataSeg = SelReg.Attr.n.u1DescType;
5352 uint8_t const fUsable = !SelReg.Attr.n.u1Unusable;
5353 uint8_t const uDpl = SelReg.Attr.n.u2Dpl;
5354 uint8_t const fPresent = SelReg.Attr.n.u1Present;
5355 uint8_t const uGranularity = SelReg.Attr.n.u1Granularity;
5356 uint8_t const uDefBig = SelReg.Attr.n.u1DefBig;
5357 uint8_t const fSegLong = SelReg.Attr.n.u1Long;
5358
5359 /* Code or usable segment. */
5360 if ( iSegReg == X86_SREG_CS
5361 || fUsable)
5362 {
5363 /* Reserved bits (bits 31:17 and bits 11:8). */
5364 if (!(SelReg.Attr.u & 0xfffe0f00))
5365 { /* likely */ }
5366 else
5367 {
5368 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrRsvd(iSegReg);
5369 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5370 }
5371
5372 /* Descriptor type. */
5373 if (fCodeDataSeg)
5374 { /* likely */ }
5375 else
5376 {
5377 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDescType(iSegReg);
5378 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5379 }
5380
5381 /* Present. */
5382 if (fPresent)
5383 { /* likely */ }
5384 else
5385 {
5386 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrPresent(iSegReg);
5387 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5388 }
5389
5390 /* Granularity. */
5391 if ( ((SelReg.u32Limit & 0x00000fff) == 0x00000fff || !uGranularity)
5392 && ((SelReg.u32Limit & 0xfff00000) == 0x00000000 || uGranularity))
5393 { /* likely */ }
5394 else
5395 {
5396 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrGran(iSegReg);
5397 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5398 }
5399 }
5400
5401 if (iSegReg == X86_SREG_CS)
5402 {
5403 /* Segment Type and DPL. */
5404 if ( uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5405 && fUnrestrictedGuest)
5406 {
5407 if (uDpl == 0)
5408 { /* likely */ }
5409 else
5410 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplZero);
5411 }
5412 else if ( uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
5413 || uSegType == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5414 {
5415 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5416 if (uDpl == AttrSs.n.u2Dpl)
5417 { /* likely */ }
5418 else
5419 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs);
5420 }
5421 else if ((uSegType & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5422 == (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF | X86_SEL_TYPE_ACCESSED))
5423 {
5424 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5425 if (uDpl <= AttrSs.n.u2Dpl)
5426 { /* likely */ }
5427 else
5428 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs);
5429 }
5430 else
5431 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsType);
5432
5433 /* Def/Big. */
5434 if ( fGstInLongMode
5435 && fSegLong)
5436 {
5437 if (uDefBig == 0)
5438 { /* likely */ }
5439 else
5440 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsDefBig);
5441 }
5442 }
5443 else if (iSegReg == X86_SREG_SS)
5444 {
5445 /* Segment Type. */
5446 if ( !fUsable
5447 || uSegType == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5448 || uSegType == (X86_SEL_TYPE_DOWN | X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED))
5449 { /* likely */ }
5450 else
5451 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsType);
5452
5453 /* DPL. */
5454 if (!fUnrestrictedGuest)
5455 {
5456 if (uDpl == (SelReg.Sel & X86_SEL_RPL))
5457 { /* likely */ }
5458 else
5459 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl);
5460 }
5461 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5462 if ( AttrCs.n.u4Type == (X86_SEL_TYPE_RW | X86_SEL_TYPE_ACCESSED)
5463 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5464 {
5465 if (uDpl == 0)
5466 { /* likely */ }
5467 else
5468 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrSsDplZero);
5469 }
5470 }
5471 else
5472 {
5473 /* DS, ES, FS, GS. */
5474 if (fUsable)
5475 {
5476 /* Segment type. */
5477 if (uSegType & X86_SEL_TYPE_ACCESSED)
5478 { /* likely */ }
5479 else
5480 {
5481 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrTypeAcc(iSegReg);
5482 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5483 }
5484
5485 if ( !(uSegType & X86_SEL_TYPE_CODE)
5486 || (uSegType & X86_SEL_TYPE_READ))
5487 { /* likely */ }
5488 else
5489 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead);
5490
5491 /* DPL. */
5492 if ( !fUnrestrictedGuest
5493 && uSegType <= (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_ACCESSED))
5494 {
5495 if (uDpl >= (SelReg.Sel & X86_SEL_RPL))
5496 { /* likely */ }
5497 else
5498 {
5499 VMXVDIAG const enmDiag = iemVmxGetDiagVmentrySegAttrDplRpl(iSegReg);
5500 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
5501 }
5502 }
5503 }
5504 }
5505 }
5506
5507 /*
5508 * LDTR.
5509 */
5510 {
5511 CPUMSELREG Ldtr;
5512 Ldtr.Sel = pVmcs->GuestLdtr;
5513 Ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
5514 Ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
5515 Ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
5516
5517 if (!Ldtr.Attr.n.u1Unusable)
5518 {
5519 /* Selector. */
5520 if (!(Ldtr.Sel & X86_SEL_LDT))
5521 { /* likely */ }
5522 else
5523 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelLdtr);
5524
5525 /* Base. */
5526 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5527 {
5528 if (X86_IS_CANONICAL(Ldtr.u64Base))
5529 { /* likely */ }
5530 else
5531 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseLdtr);
5532 }
5533
5534 /* Attributes. */
5535 /* Reserved bits (bits 31:17 and bits 11:8). */
5536 if (!(Ldtr.Attr.u & 0xfffe0f00))
5537 { /* likely */ }
5538 else
5539 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd);
5540
5541 if (Ldtr.Attr.n.u4Type == X86_SEL_TYPE_SYS_LDT)
5542 { /* likely */ }
5543 else
5544 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrType);
5545
5546 if (!Ldtr.Attr.n.u1DescType)
5547 { /* likely */ }
5548 else
5549 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType);
5550
5551 if (Ldtr.Attr.n.u1Present)
5552 { /* likely */ }
5553 else
5554 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent);
5555
5556 if ( ((Ldtr.u32Limit & 0x00000fff) == 0x00000fff || !Ldtr.Attr.n.u1Granularity)
5557 && ((Ldtr.u32Limit & 0xfff00000) == 0x00000000 || Ldtr.Attr.n.u1Granularity))
5558 { /* likely */ }
5559 else
5560 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrLdtrGran);
5561 }
5562 }
5563
5564 /*
5565 * TR.
5566 */
5567 {
5568 CPUMSELREG Tr;
5569 Tr.Sel = pVmcs->GuestTr;
5570 Tr.u32Limit = pVmcs->u32GuestTrLimit;
5571 Tr.u64Base = pVmcs->u64GuestTrBase.u;
5572 Tr.Attr.u = pVmcs->u32GuestTrAttr;
5573
5574 /* Selector. */
5575 if (!(Tr.Sel & X86_SEL_LDT))
5576 { /* likely */ }
5577 else
5578 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegSelTr);
5579
5580 /* Base. */
5581 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5582 {
5583 if (X86_IS_CANONICAL(Tr.u64Base))
5584 { /* likely */ }
5585 else
5586 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegBaseTr);
5587 }
5588
5589 /* Attributes. */
5590 /* Reserved bits (bits 31:17 and bits 11:8). */
5591 if (!(Tr.Attr.u & 0xfffe0f00))
5592 { /* likely */ }
5593 else
5594 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrRsvd);
5595
5596 if (!Tr.Attr.n.u1Unusable)
5597 { /* likely */ }
5598 else
5599 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrUnusable);
5600
5601 if ( Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY
5602 || ( !fGstInLongMode
5603 && Tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY))
5604 { /* likely */ }
5605 else
5606 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrType);
5607
5608 if (!Tr.Attr.n.u1DescType)
5609 { /* likely */ }
5610 else
5611 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrDescType);
5612
5613 if (Tr.Attr.n.u1Present)
5614 { /* likely */ }
5615 else
5616 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrPresent);
5617
5618 if ( ((Tr.u32Limit & 0x00000fff) == 0x00000fff || !Tr.Attr.n.u1Granularity)
5619 && ((Tr.u32Limit & 0xfff00000) == 0x00000000 || Tr.Attr.n.u1Granularity))
5620 { /* likely */ }
5621 else
5622 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestSegAttrTrGran);
5623 }
5624
5625 NOREF(pszInstr);
5626 NOREF(pszFailure);
5627 return VINF_SUCCESS;
5628}
5629
5630
5631/**
5632 * Checks guest GDTR and IDTR as part of VM-entry.
5633 *
5634 * @param pVCpu The cross context virtual CPU structure.
5635 * @param pszInstr The VMX instruction name (for logging purposes).
5636 */
5637IEM_STATIC int iemVmxVmentryCheckGuestGdtrIdtr(PVMCPU pVCpu, const char *pszInstr)
5638{
5639 /*
5640 * GDTR and IDTR.
5641 * See Intel spec. 26.3.1.3 "Checks on Guest Descriptor-Table Registers".
5642 */
5643 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5644 const char *const pszFailure = "VM-exit";
5645
5646 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5647 {
5648 /* Base. */
5649 if (X86_IS_CANONICAL(pVmcs->u64GuestGdtrBase.u))
5650 { /* likely */ }
5651 else
5652 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrBase);
5653
5654 if (X86_IS_CANONICAL(pVmcs->u64GuestIdtrBase.u))
5655 { /* likely */ }
5656 else
5657 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrBase);
5658 }
5659
5660 /* Limit. */
5661 if (!RT_HI_U16(pVmcs->u32GuestGdtrLimit))
5662 { /* likely */ }
5663 else
5664 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestGdtrLimit);
5665
5666 if (!RT_HI_U16(pVmcs->u32GuestIdtrLimit))
5667 { /* likely */ }
5668 else
5669 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIdtrLimit);
5670
5671 NOREF(pszInstr);
5672 NOREF(pszFailure);
5673 return VINF_SUCCESS;
5674}
5675
5676
5677/**
5678 * Checks guest RIP and RFLAGS as part of VM-entry.
5679 *
5680 * @param pVCpu The cross context virtual CPU structure.
5681 * @param pszInstr The VMX instruction name (for logging purposes).
5682 */
5683IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
5684{
5685 /*
5686 * RIP and RFLAGS.
5687 * See Intel spec. 26.3.1.4 "Checks on Guest RIP and RFLAGS".
5688 */
5689 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5690 const char *const pszFailure = "VM-exit";
5691 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
5692
5693 /* RIP. */
5694 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
5695 {
5696 X86DESCATTR AttrCs; AttrCs.u = pVmcs->u32GuestCsAttr;
5697 if ( !fGstInLongMode
5698 || !AttrCs.n.u1Long)
5699 {
5700 if (!RT_HI_U32(pVmcs->u64GuestRip.u))
5701 { /* likely */ }
5702 else
5703 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRipRsvd);
5704 }
5705
5706 if ( fGstInLongMode
5707 && AttrCs.n.u1Long)
5708 {
5709 Assert(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth == 48); /* Canonical. */
5710 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxLinearAddrWidth < 64
5711 && X86_IS_CANONICAL(pVmcs->u64GuestRip.u))
5712 { /* likely */ }
5713 else
5714 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRip);
5715 }
5716 }
5717
5718 /* RFLAGS (bits 63:22 (or 31:22), bits 15, 5, 3 are reserved, bit 1 MB1). */
5719 uint64_t const uGuestRFlags = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode ? pVmcs->u64GuestRFlags.u
5720 : pVmcs->u64GuestRFlags.s.Lo;
5721 if ( !(uGuestRFlags & ~(X86_EFL_LIVE_MASK | X86_EFL_RA1_MASK))
5722 && (uGuestRFlags & X86_EFL_RA1_MASK) == X86_EFL_RA1_MASK)
5723 { /* likely */ }
5724 else
5725 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsRsvd);
5726
5727 if ( fGstInLongMode
5728 || !(pVmcs->u64GuestCr0.u & X86_CR0_PE))
5729 {
5730 if (!(uGuestRFlags & X86_EFL_VM))
5731 { /* likely */ }
5732 else
5733 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsVm);
5734 }
5735
5736 if ( VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)
5737 && VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo) == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5738 {
5739 if (uGuestRFlags & X86_EFL_IF)
5740 { /* likely */ }
5741 else
5742 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestRFlagsIf);
5743 }
5744
5745 NOREF(pszInstr);
5746 NOREF(pszFailure);
5747 return VINF_SUCCESS;
5748}
5749
5750
5751/**
5752 * Checks guest non-register state as part of VM-entry.
5753 *
5754 * @param pVCpu The cross context virtual CPU structure.
5755 * @param pszInstr The VMX instruction name (for logging purposes).
5756 */
5757IEM_STATIC int iemVmxVmentryCheckGuestNonRegState(PVMCPU pVCpu, const char *pszInstr)
5758{
5759 /*
5760 * Guest non-register state.
5761 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5762 */
5763 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5764 const char *const pszFailure = "VM-exit";
5765
5766 /*
5767 * Activity state.
5768 */
5769 uint64_t const u64GuestVmxMiscMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Misc;
5770 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES);
5771 if (!(pVmcs->u32GuestActivityState & fActivityStateMask))
5772 { /* likely */ }
5773 else
5774 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateRsvd);
5775
5776 X86DESCATTR AttrSs; AttrSs.u = pVmcs->u32GuestSsAttr;
5777 if ( !AttrSs.n.u2Dpl
5778 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT)
5779 { /* likely */ }
5780 else
5781 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl);
5782
5783 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI
5784 || pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
5785 {
5786 if (pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE)
5787 { /* likely */ }
5788 else
5789 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateStiMovSs);
5790 }
5791
5792 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5793 {
5794 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5795 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
5796 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN));
5797 switch (pVmcs->u32GuestActivityState)
5798 {
5799 case VMX_VMCS_GUEST_ACTIVITY_HLT:
5800 {
5801 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT
5802 || uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5803 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5804 && ( uVector == X86_XCPT_DB
5805 || uVector == X86_XCPT_MC))
5806 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
5807 && uVector == VMX_ENTRY_INT_INFO_VECTOR_MTF))
5808 { /* likely */ }
5809 else
5810 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateHlt);
5811 break;
5812 }
5813
5814 case VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN:
5815 {
5816 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI
5817 || ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
5818 && uVector == X86_XCPT_MC))
5819 { /* likely */ }
5820 else
5821 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateShutdown);
5822 break;
5823 }
5824
5825 case VMX_VMCS_GUEST_ACTIVITY_ACTIVE:
5826 default:
5827 break;
5828 }
5829 }
5830
5831 /*
5832 * Interruptibility state.
5833 */
5834 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK))
5835 { /* likely */ }
5836 else
5837 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd);
5838
5839 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5840 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5841 { /* likely */ }
5842 else
5843 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs);
5844
5845 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF)
5846 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5847 { /* likely */ }
5848 else
5849 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti);
5850
5851 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo))
5852 {
5853 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo);
5854 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
5855 {
5856 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5857 { /* likely */ }
5858 else
5859 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt);
5860 }
5861 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
5862 {
5863 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)))
5864 { /* likely */ }
5865 else
5866 {
5867 /*
5868 * We don't support injecting NMIs when blocking-by-STI would be in effect.
5869 * We update the VM-exit qualification only when blocking-by-STI is set
5870 * without blocking-by-MovSS being set. Although in practise it does not
5871 * make much difference since the order of checks are implementation defined.
5872 */
5873 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
5874 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_NMI_INJECT);
5875 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi);
5876 }
5877
5878 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
5879 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI))
5880 { /* likely */ }
5881 else
5882 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi);
5883 }
5884 }
5885
5886 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */
5887 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI))
5888 { /* likely */ }
5889 else
5890 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi);
5891
5892 /* We don't support SGX yet. So enclave-interruption must not be set. */
5893 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE))
5894 { /* likely */ }
5895 else
5896 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave);
5897
5898 /*
5899 * Pending debug exceptions.
5900 */
5901 uint64_t const uPendingDbgXcpt = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode
5902 ? pVmcs->u64GuestPendingDbgXcpt.u
5903 : pVmcs->u64GuestPendingDbgXcpt.s.Lo;
5904 if (!(uPendingDbgXcpt & ~VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK))
5905 { /* likely */ }
5906 else
5907 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd);
5908
5909 if ( (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
5910 || pVmcs->u32GuestActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
5911 {
5912 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5913 && !(pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF)
5914 && !(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5915 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf);
5916
5917 if ( ( !(pVmcs->u64GuestRFlags.u & X86_EFL_TF)
5918 || (pVmcs->u64GuestDebugCtlMsr.u & MSR_IA32_DEBUGCTL_BTF))
5919 && (uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS))
5920 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf);
5921 }
5922
5923 /* We don't support RTM (Real-time Transactional Memory) yet. */
5924 if (!(uPendingDbgXcpt & VMX_VMCS_GUEST_PENDING_DEBUG_RTM))
5925 { /* likely */ }
5926 else
5927 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPndDbgXcptRtm);
5928
5929 /*
5930 * VMCS link pointer.
5931 */
5932 if (pVmcs->u64VmcsLinkPtr.u != UINT64_C(0xffffffffffffffff))
5933 {
5934 RTGCPHYS const GCPhysShadowVmcs = pVmcs->u64VmcsLinkPtr.u;
5935 /* We don't support SMM yet (so VMCS link pointer cannot be the current VMCS). */
5936 if (GCPhysShadowVmcs != IEM_VMX_GET_CURRENT_VMCS(pVCpu))
5937 { /* likely */ }
5938 else
5939 {
5940 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5941 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs);
5942 }
5943
5944 /* Validate the address. */
5945 if ( !(GCPhysShadowVmcs & X86_PAGE_4K_OFFSET_MASK)
5946 && !(GCPhysShadowVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
5947 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysShadowVmcs))
5948 { /* likely */ }
5949 else
5950 {
5951 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5952 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmcsLinkPtr);
5953 }
5954
5955 /* Read the VMCS-link pointer from guest memory. */
5956 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs));
5957 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs),
5958 GCPhysShadowVmcs, VMX_V_VMCS_SIZE);
5959 if (RT_SUCCESS(rc))
5960 { /* likely */ }
5961 else
5962 {
5963 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5964 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys);
5965 }
5966
5967 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
5968 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID)
5969 { /* likely */ }
5970 else
5971 {
5972 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5973 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrRevId);
5974 }
5975
5976 /* Verify the shadow bit is set if VMCS shadowing is enabled . */
5977 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5978 || pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
5979 { /* likely */ }
5980 else
5981 {
5982 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR);
5983 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmcsLinkPtrShadow);
5984 }
5985
5986 /* Finally update our cache of the guest physical address of the shadow VMCS. */
5987 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs = GCPhysShadowVmcs;
5988 }
5989
5990 NOREF(pszInstr);
5991 NOREF(pszFailure);
5992 return VINF_SUCCESS;
5993}
5994
5995
5996/**
5997 * Checks if the PDPTEs referenced by the nested-guest CR3 are valid as part of
5998 * VM-entry.
5999 *
6000 * @returns @c true if all PDPTEs are valid, @c false otherwise.
6001 * @param pVCpu The cross context virtual CPU structure.
6002 * @param pszInstr The VMX instruction name (for logging purposes).
6003 * @param pVmcs Pointer to the virtual VMCS.
6004 */
6005IEM_STATIC int iemVmxVmentryCheckGuestPdptesForCr3(PVMCPU pVCpu, const char *pszInstr, PVMXVVMCS pVmcs)
6006{
6007 /*
6008 * Check PDPTEs.
6009 * See Intel spec. 4.4.1 "PDPTE Registers".
6010 */
6011 uint64_t const uGuestCr3 = pVmcs->u64GuestCr3.u & X86_CR3_PAE_PAGE_MASK;
6012 const char *const pszFailure = "VM-exit";
6013
6014 X86PDPE aPdptes[X86_PG_PAE_PDPE_ENTRIES];
6015 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)&aPdptes[0], uGuestCr3, sizeof(aPdptes));
6016 if (RT_SUCCESS(rc))
6017 {
6018 for (unsigned iPdpte = 0; iPdpte < RT_ELEMENTS(aPdptes); iPdpte++)
6019 {
6020 if ( !(aPdptes[iPdpte].u & X86_PDPE_P)
6021 || !(aPdptes[iPdpte].u & X86_PDPE_PAE_MBZ_MASK))
6022 { /* likely */ }
6023 else
6024 {
6025 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6026 VMXVDIAG const enmDiag = iemVmxGetDiagVmentryPdpteRsvd(iPdpte);
6027 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
6028 }
6029 }
6030 }
6031 else
6032 {
6033 iemVmxVmcsSetExitQual(pVCpu, VMX_ENTRY_FAIL_QUAL_PDPTE);
6034 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys);
6035 }
6036
6037 NOREF(pszFailure);
6038 NOREF(pszInstr);
6039 return rc;
6040}
6041
6042
6043/**
6044 * Checks guest PDPTEs as part of VM-entry.
6045 *
6046 * @param pVCpu The cross context virtual CPU structure.
6047 * @param pszInstr The VMX instruction name (for logging purposes).
6048 */
6049IEM_STATIC int iemVmxVmentryCheckGuestPdptes(PVMCPU pVCpu, const char *pszInstr)
6050{
6051 /*
6052 * Guest PDPTEs.
6053 * See Intel spec. 26.3.1.5 "Checks on Guest Page-Directory-Pointer-Table Entries".
6054 */
6055 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6056 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6057
6058 /* Check PDPTes if the VM-entry is to a guest using PAE paging. */
6059 int rc;
6060 if ( !fGstInLongMode
6061 && (pVmcs->u64GuestCr4.u & X86_CR4_PAE)
6062 && (pVmcs->u64GuestCr0.u & X86_CR0_PG))
6063 {
6064 /*
6065 * We don't support nested-paging for nested-guests yet.
6066 *
6067 * Without nested-paging for nested-guests, PDPTEs in the VMCS are not used,
6068 * rather we need to check the PDPTEs referenced by the guest CR3.
6069 */
6070 rc = iemVmxVmentryCheckGuestPdptesForCr3(pVCpu, pszInstr, pVmcs);
6071 }
6072 else
6073 rc = VINF_SUCCESS;
6074 return rc;
6075}
6076
6077
6078/**
6079 * Checks guest-state as part of VM-entry.
6080 *
6081 * @returns VBox status code.
6082 * @param pVCpu The cross context virtual CPU structure.
6083 * @param pszInstr The VMX instruction name (for logging purposes).
6084 */
6085IEM_STATIC int iemVmxVmentryCheckGuestState(PVMCPU pVCpu, const char *pszInstr)
6086{
6087 int rc = iemVmxVmentryCheckGuestControlRegsMsrs(pVCpu, pszInstr);
6088 if (RT_SUCCESS(rc))
6089 {
6090 rc = iemVmxVmentryCheckGuestSegRegs(pVCpu, pszInstr);
6091 if (RT_SUCCESS(rc))
6092 {
6093 rc = iemVmxVmentryCheckGuestGdtrIdtr(pVCpu, pszInstr);
6094 if (RT_SUCCESS(rc))
6095 {
6096 rc = iemVmxVmentryCheckGuestRipRFlags(pVCpu, pszInstr);
6097 if (RT_SUCCESS(rc))
6098 {
6099 rc = iemVmxVmentryCheckGuestNonRegState(pVCpu, pszInstr);
6100 if (RT_SUCCESS(rc))
6101 return iemVmxVmentryCheckGuestPdptes(pVCpu, pszInstr);
6102 }
6103 }
6104 }
6105 }
6106 return rc;
6107}
6108
6109
6110/**
6111 * Checks host-state as part of VM-entry.
6112 *
6113 * @returns VBox status code.
6114 * @param pVCpu The cross context virtual CPU structure.
6115 * @param pszInstr The VMX instruction name (for logging purposes).
6116 */
6117IEM_STATIC int iemVmxVmentryCheckHostState(PVMCPU pVCpu, const char *pszInstr)
6118{
6119 /*
6120 * Host Control Registers and MSRs.
6121 * See Intel spec. 26.2.2 "Checks on Host Control Registers and MSRs".
6122 */
6123 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6124 const char * const pszFailure = "VMFail";
6125
6126 /* CR0 reserved bits. */
6127 {
6128 /* CR0 MB1 bits. */
6129 uint64_t const u64Cr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
6130 if ((pVmcs->u64HostCr0.u & u64Cr0Fixed0) == u64Cr0Fixed0)
6131 { /* likely */ }
6132 else
6133 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed0);
6134
6135 /* CR0 MBZ bits. */
6136 uint64_t const u64Cr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
6137 if (!(pVmcs->u64HostCr0.u & ~u64Cr0Fixed1))
6138 { /* likely */ }
6139 else
6140 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr0Fixed1);
6141 }
6142
6143 /* CR4 reserved bits. */
6144 {
6145 /* CR4 MB1 bits. */
6146 uint64_t const u64Cr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6147 if ((pVmcs->u64HostCr4.u & u64Cr4Fixed0) == u64Cr4Fixed0)
6148 { /* likely */ }
6149 else
6150 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed0);
6151
6152 /* CR4 MBZ bits. */
6153 uint64_t const u64Cr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6154 if (!(pVmcs->u64HostCr4.u & ~u64Cr4Fixed1))
6155 { /* likely */ }
6156 else
6157 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Fixed1);
6158 }
6159
6160 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6161 {
6162 /* CR3 reserved bits. */
6163 if (!(pVmcs->u64HostCr3.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth))
6164 { /* likely */ }
6165 else
6166 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr3);
6167
6168 /* SYSENTER ESP and SYSENTER EIP. */
6169 if ( X86_IS_CANONICAL(pVmcs->u64HostSysenterEsp.u)
6170 && X86_IS_CANONICAL(pVmcs->u64HostSysenterEip.u))
6171 { /* likely */ }
6172 else
6173 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSysenterEspEip);
6174 }
6175
6176 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6177 Assert(!(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PERF_MSR));
6178
6179 /* PAT MSR. */
6180 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR)
6181 || CPUMIsPatMsrValid(pVmcs->u64HostPatMsr.u))
6182 { /* likely */ }
6183 else
6184 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostPatMsr);
6185
6186 /* EFER MSR. */
6187 uint64_t const uValidEferMask = CPUMGetGuestEferMsrValidMask(pVCpu->CTX_SUFF(pVM));
6188 if ( !(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
6189 || !(pVmcs->u64HostEferMsr.u & ~uValidEferMask))
6190 { /* likely */ }
6191 else
6192 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsrRsvd);
6193
6194 bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
6195 bool const fHostLma = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LMA);
6196 bool const fHostLme = RT_BOOL(pVmcs->u64HostEferMsr.u & MSR_K6_EFER_LME);
6197 if ( fHostInLongMode == fHostLma
6198 && fHostInLongMode == fHostLme)
6199 { /* likely */ }
6200 else
6201 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostEferMsr);
6202
6203 /*
6204 * Host Segment and Descriptor-Table Registers.
6205 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
6206 */
6207 /* Selector RPL and TI. */
6208 if ( !(pVmcs->HostCs & (X86_SEL_RPL | X86_SEL_LDT))
6209 && !(pVmcs->HostSs & (X86_SEL_RPL | X86_SEL_LDT))
6210 && !(pVmcs->HostDs & (X86_SEL_RPL | X86_SEL_LDT))
6211 && !(pVmcs->HostEs & (X86_SEL_RPL | X86_SEL_LDT))
6212 && !(pVmcs->HostFs & (X86_SEL_RPL | X86_SEL_LDT))
6213 && !(pVmcs->HostGs & (X86_SEL_RPL | X86_SEL_LDT))
6214 && !(pVmcs->HostTr & (X86_SEL_RPL | X86_SEL_LDT)))
6215 { /* likely */ }
6216 else
6217 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSel);
6218
6219 /* CS and TR selectors cannot be 0. */
6220 if ( pVmcs->HostCs
6221 && pVmcs->HostTr)
6222 { /* likely */ }
6223 else
6224 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCsTr);
6225
6226 /* SS cannot be 0 if 32-bit host. */
6227 if ( fHostInLongMode
6228 || pVmcs->HostSs)
6229 { /* likely */ }
6230 else
6231 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSs);
6232
6233 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6234 {
6235 /* FS, GS, GDTR, IDTR, TR base address. */
6236 if ( X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6237 && X86_IS_CANONICAL(pVmcs->u64HostFsBase.u)
6238 && X86_IS_CANONICAL(pVmcs->u64HostGdtrBase.u)
6239 && X86_IS_CANONICAL(pVmcs->u64HostIdtrBase.u)
6240 && X86_IS_CANONICAL(pVmcs->u64HostTrBase.u))
6241 { /* likely */ }
6242 else
6243 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostSegBase);
6244 }
6245
6246 /*
6247 * Host address-space size for 64-bit CPUs.
6248 * See Intel spec. 26.2.4 "Checks Related to Address-Space Size".
6249 */
6250 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6251 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6252 {
6253 bool const fCpuInLongMode = CPUMIsGuestInLongMode(pVCpu);
6254
6255 /* Logical processor in IA-32e mode. */
6256 if (fCpuInLongMode)
6257 {
6258 if (fHostInLongMode)
6259 {
6260 /* PAE must be set. */
6261 if (pVmcs->u64HostCr4.u & X86_CR4_PAE)
6262 { /* likely */ }
6263 else
6264 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pae);
6265
6266 /* RIP must be canonical. */
6267 if (X86_IS_CANONICAL(pVmcs->u64HostRip.u))
6268 { /* likely */ }
6269 else
6270 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRip);
6271 }
6272 else
6273 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostLongMode);
6274 }
6275 else
6276 {
6277 /* Logical processor is outside IA-32e mode. */
6278 if ( !fGstInLongMode
6279 && !fHostInLongMode)
6280 {
6281 /* PCIDE should not be set. */
6282 if (!(pVmcs->u64HostCr4.u & X86_CR4_PCIDE))
6283 { /* likely */ }
6284 else
6285 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostCr4Pcide);
6286
6287 /* The high 32-bits of RIP MBZ. */
6288 if (!pVmcs->u64HostRip.s.Hi)
6289 { /* likely */ }
6290 else
6291 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostRipRsvd);
6292 }
6293 else
6294 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongMode);
6295 }
6296 }
6297 else
6298 {
6299 /* Host address-space size for 32-bit CPUs. */
6300 if ( !fGstInLongMode
6301 && !fHostInLongMode)
6302 { /* likely */ }
6303 else
6304 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_HostGuestLongModeNoCpu);
6305 }
6306
6307 NOREF(pszInstr);
6308 NOREF(pszFailure);
6309 return VINF_SUCCESS;
6310}
6311
6312
6313/**
6314 * Checks VM-entry controls fields as part of VM-entry.
6315 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6316 *
6317 * @returns VBox status code.
6318 * @param pVCpu The cross context virtual CPU structure.
6319 * @param pszInstr The VMX instruction name (for logging purposes).
6320 */
6321IEM_STATIC int iemVmxVmentryCheckEntryCtls(PVMCPU pVCpu, const char *pszInstr)
6322{
6323 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6324 const char * const pszFailure = "VMFail";
6325
6326 /* VM-entry controls. */
6327 VMXCTLSMSR const EntryCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.EntryCtls;
6328 if (!(~pVmcs->u32EntryCtls & EntryCtls.n.allowed0))
6329 { /* likely */ }
6330 else
6331 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsDisallowed0);
6332
6333 if (!(pVmcs->u32EntryCtls & ~EntryCtls.n.allowed1))
6334 { /* likely */ }
6335 else
6336 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryCtlsAllowed1);
6337
6338 /* Event injection. */
6339 uint32_t const uIntInfo = pVmcs->u32EntryIntInfo;
6340 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VALID))
6341 {
6342 /* Type and vector. */
6343 uint8_t const uType = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_TYPE);
6344 uint8_t const uVector = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_VECTOR);
6345 uint8_t const uRsvd = RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_RSVD_12_30);
6346 if ( !uRsvd
6347 && HMVmxIsEntryIntInfoTypeValid(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxMonitorTrapFlag, uType)
6348 && HMVmxIsEntryIntInfoVectorValid(uVector, uType))
6349 { /* likely */ }
6350 else
6351 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd);
6352
6353 /* Exception error code. */
6354 if (RT_BF_GET(uIntInfo, VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID))
6355 {
6356 /* Delivery possible only in Unrestricted-guest mode when CR0.PE is set. */
6357 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
6358 || (pVmcs->u64GuestCr0.s.Lo & X86_CR0_PE))
6359 { /* likely */ }
6360 else
6361 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodePe);
6362
6363 /* Exceptions that provide an error code. */
6364 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
6365 && ( uVector == X86_XCPT_DF
6366 || uVector == X86_XCPT_TS
6367 || uVector == X86_XCPT_NP
6368 || uVector == X86_XCPT_SS
6369 || uVector == X86_XCPT_GP
6370 || uVector == X86_XCPT_PF
6371 || uVector == X86_XCPT_AC))
6372 { /* likely */ }
6373 else
6374 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec);
6375
6376 /* Exception error-code reserved bits. */
6377 if (!(pVmcs->u32EntryXcptErrCode & ~VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK))
6378 { /* likely */ }
6379 else
6380 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd);
6381
6382 /* Injecting a software interrupt, software exception or privileged software exception. */
6383 if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
6384 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
6385 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
6386 {
6387 /* Instruction length must be in the range 0-15. */
6388 if (pVmcs->u32EntryInstrLen <= VMX_ENTRY_INSTR_LEN_MAX)
6389 { /* likely */ }
6390 else
6391 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLen);
6392
6393 /* Instruction length of 0 is allowed only when its CPU feature is present. */
6394 if ( pVmcs->u32EntryInstrLen == 0
6395 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxEntryInjectSoftInt)
6396 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_EntryInstrLenZero);
6397 }
6398 }
6399 }
6400
6401 /* VM-entry MSR-load count and VM-entry MSR-load area address. */
6402 if (pVmcs->u32EntryMsrLoadCount)
6403 {
6404 if ( !(pVmcs->u64AddrEntryMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6405 && !(pVmcs->u64AddrEntryMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6406 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrEntryMsrLoad.u))
6407 { /* likely */ }
6408 else
6409 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrEntryMsrLoad);
6410 }
6411
6412 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)); /* We don't support SMM yet. */
6413 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON)); /* We don't support dual-monitor treatment yet. */
6414
6415 NOREF(pszInstr);
6416 NOREF(pszFailure);
6417 return VINF_SUCCESS;
6418}
6419
6420
6421/**
6422 * Checks VM-exit controls fields as part of VM-entry.
6423 * See Intel spec. 26.2.1.2 "VM-Exit Control Fields".
6424 *
6425 * @returns VBox status code.
6426 * @param pVCpu The cross context virtual CPU structure.
6427 * @param pszInstr The VMX instruction name (for logging purposes).
6428 */
6429IEM_STATIC int iemVmxVmentryCheckExitCtls(PVMCPU pVCpu, const char *pszInstr)
6430{
6431 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6432 const char * const pszFailure = "VMFail";
6433
6434 /* VM-exit controls. */
6435 VMXCTLSMSR const ExitCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ExitCtls;
6436 if (!(~pVmcs->u32ExitCtls & ExitCtls.n.allowed0))
6437 { /* likely */ }
6438 else
6439 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsDisallowed0);
6440
6441 if (!(pVmcs->u32ExitCtls & ~ExitCtls.n.allowed1))
6442 { /* likely */ }
6443 else
6444 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ExitCtlsAllowed1);
6445
6446 /* Save preemption timer without activating it. */
6447 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
6448 || !(pVmcs->u32ProcCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
6449 { /* likely */ }
6450 else
6451 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_SavePreemptTimer);
6452
6453 /* VM-exit MSR-store count and VM-exit MSR-store area address. */
6454 if (pVmcs->u32ExitMsrStoreCount)
6455 {
6456 if ( !(pVmcs->u64AddrExitMsrStore.u & VMX_AUTOMSR_OFFSET_MASK)
6457 && !(pVmcs->u64AddrExitMsrStore.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6458 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrStore.u))
6459 { /* likely */ }
6460 else
6461 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrStore);
6462 }
6463
6464 /* VM-exit MSR-load count and VM-exit MSR-load area address. */
6465 if (pVmcs->u32ExitMsrLoadCount)
6466 {
6467 if ( !(pVmcs->u64AddrExitMsrLoad.u & VMX_AUTOMSR_OFFSET_MASK)
6468 && !(pVmcs->u64AddrExitMsrLoad.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6469 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrExitMsrLoad.u))
6470 { /* likely */ }
6471 else
6472 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrExitMsrLoad);
6473 }
6474
6475 NOREF(pszInstr);
6476 NOREF(pszFailure);
6477 return VINF_SUCCESS;
6478}
6479
6480
6481/**
6482 * Checks VM-execution controls fields as part of VM-entry.
6483 * See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
6484 *
6485 * @returns VBox status code.
6486 * @param pVCpu The cross context virtual CPU structure.
6487 * @param pszInstr The VMX instruction name (for logging purposes).
6488 *
6489 * @remarks This may update secondary-processor based VM-execution control fields
6490 * in the current VMCS if necessary.
6491 */
6492IEM_STATIC int iemVmxVmentryCheckExecCtls(PVMCPU pVCpu, const char *pszInstr)
6493{
6494 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6495 const char * const pszFailure = "VMFail";
6496
6497 /* Pin-based VM-execution controls. */
6498 {
6499 VMXCTLSMSR const PinCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.PinCtls;
6500 if (!(~pVmcs->u32PinCtls & PinCtls.n.allowed0))
6501 { /* likely */ }
6502 else
6503 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsDisallowed0);
6504
6505 if (!(pVmcs->u32PinCtls & ~PinCtls.n.allowed1))
6506 { /* likely */ }
6507 else
6508 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_PinCtlsAllowed1);
6509 }
6510
6511 /* Processor-based VM-execution controls. */
6512 {
6513 VMXCTLSMSR const ProcCtls = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls;
6514 if (!(~pVmcs->u32ProcCtls & ProcCtls.n.allowed0))
6515 { /* likely */ }
6516 else
6517 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsDisallowed0);
6518
6519 if (!(pVmcs->u32ProcCtls & ~ProcCtls.n.allowed1))
6520 { /* likely */ }
6521 else
6522 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtlsAllowed1);
6523 }
6524
6525 /* Secondary processor-based VM-execution controls. */
6526 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
6527 {
6528 VMXCTLSMSR const ProcCtls2 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.ProcCtls2;
6529 if (!(~pVmcs->u32ProcCtls2 & ProcCtls2.n.allowed0))
6530 { /* likely */ }
6531 else
6532 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Disallowed0);
6533
6534 if (!(pVmcs->u32ProcCtls2 & ~ProcCtls2.n.allowed1))
6535 { /* likely */ }
6536 else
6537 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ProcCtls2Allowed1);
6538 }
6539 else
6540 Assert(!pVmcs->u32ProcCtls2);
6541
6542 /* CR3-target count. */
6543 if (pVmcs->u32Cr3TargetCount <= VMX_V_CR3_TARGET_COUNT)
6544 { /* likely */ }
6545 else
6546 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Cr3TargetCount);
6547
6548 /* I/O bitmaps physical addresses. */
6549 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS)
6550 {
6551 if ( !(pVmcs->u64AddrIoBitmapA.u & X86_PAGE_4K_OFFSET_MASK)
6552 && !(pVmcs->u64AddrIoBitmapA.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6553 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapA.u))
6554 { /* likely */ }
6555 else
6556 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapA);
6557
6558 if ( !(pVmcs->u64AddrIoBitmapB.u & X86_PAGE_4K_OFFSET_MASK)
6559 && !(pVmcs->u64AddrIoBitmapB.u >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6560 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), pVmcs->u64AddrIoBitmapB.u))
6561 { /* likely */ }
6562 else
6563 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrIoBitmapB);
6564 }
6565
6566 /* MSR bitmap physical address. */
6567 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
6568 {
6569 RTGCPHYS const GCPhysMsrBitmap = pVmcs->u64AddrMsrBitmap.u;
6570 if ( !(GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
6571 && !(GCPhysMsrBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6572 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysMsrBitmap))
6573 { /* likely */ }
6574 else
6575 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrMsrBitmap);
6576
6577 /* Read the MSR bitmap. */
6578 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
6579 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap),
6580 GCPhysMsrBitmap, VMX_V_MSR_BITMAP_SIZE);
6581 if (RT_SUCCESS(rc))
6582 { /* likely */ }
6583 else
6584 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys);
6585 }
6586
6587 /* TPR shadow related controls. */
6588 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6589 {
6590 /* Virtual-APIC page physical address. */
6591 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6592 if ( !(GCPhysVirtApic & X86_PAGE_4K_OFFSET_MASK)
6593 && !(GCPhysVirtApic >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6594 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVirtApic))
6595 { /* likely */ }
6596 else
6597 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVirtApicPage);
6598
6599 /* Read the Virtual-APIC page. */
6600 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage));
6601 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage),
6602 GCPhysVirtApic, VMX_V_VIRT_APIC_PAGES);
6603 if (RT_SUCCESS(rc))
6604 { /* likely */ }
6605 else
6606 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys);
6607
6608 /* TPR threshold without virtual-interrupt delivery. */
6609 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6610 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK))
6611 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd);
6612
6613 /* TPR threshold and VTPR. */
6614 uint8_t const *pbVirtApic = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVirtApicPage);
6615 uint8_t const u8VTpr = *(pbVirtApic + XAPIC_OFF_TPR);
6616 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6617 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6618 && RT_BF_GET(pVmcs->u32TprThreshold, VMX_BF_TPR_THRESHOLD_TPR) > ((u8VTpr >> 4) & UINT32_C(0xf)) /* Bits 4:7 */)
6619 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdVTpr);
6620 }
6621 else
6622 {
6623 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6624 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6625 && !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY))
6626 { /* likely */ }
6627 else
6628 {
6629 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6630 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicTprShadow);
6631 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT)
6632 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_ApicRegVirt);
6633 Assert(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
6634 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtIntDelivery);
6635 }
6636 }
6637
6638 /* NMI exiting and virtual-NMIs. */
6639 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_NMI_EXIT)
6640 || !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6641 { /* likely */ }
6642 else
6643 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtNmi);
6644
6645 /* Virtual-NMIs and NMI-window exiting. */
6646 if ( (pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
6647 || !(pVmcs->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
6648 { /* likely */ }
6649 else
6650 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_NmiWindowExit);
6651
6652 /* Virtualize APIC accesses. */
6653 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
6654 {
6655 /* APIC-access physical address. */
6656 RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
6657 if ( !(GCPhysApicAccess & X86_PAGE_4K_OFFSET_MASK)
6658 && !(GCPhysApicAccess >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6659 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess))
6660 { /* likely */ }
6661 else
6662 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccess);
6663
6664 /*
6665 * Disallow APIC-access page and virtual-APIC page from being the same address.
6666 * Note! This is not an Intel requirement, but one imposed by our implementation.
6667 */
6668 /** @todo r=ramshankar: This is done primarily to simplify recursion scenarios while
6669 * redirecting accesses between the APIC-access page and the virtual-APIC
6670 * page. If any nested hypervisor requires this, we can implement it later. */
6671 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
6672 {
6673 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
6674 if (GCPhysVirtApic != GCPhysApicAccess)
6675 { /* likely */ }
6676 else
6677 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
6678 }
6679
6680 /*
6681 * Register the handler for the APIC-access page.
6682 *
6683 * We don't deregister the APIC-access page handler during the VM-exit as a different
6684 * nested-VCPU might be using the same guest-physical address for its APIC-access page.
6685 *
6686 * We leave the page registered until the first access that happens outside VMX non-root
6687 * mode. Guest software is allowed to access structures such as the APIC-access page
6688 * only when no logical processor with a current VMCS references it in VMX non-root mode,
6689 * otherwise it can lead to unpredictable behavior including guest triple-faults.
6690 *
6691 * See Intel spec. 24.11.4 "Software Access to Related Structures".
6692 */
6693 int rc = PGMHandlerPhysicalRegister(pVCpu->CTX_SUFF(pVM), GCPhysApicAccess, GCPhysApicAccess,
6694 pVCpu->iem.s.hVmxApicAccessPage, NIL_RTR3PTR /* pvUserR3 */,
6695 NIL_RTR0PTR /* pvUserR0 */, NIL_RTRCPTR /* pvUserRC */, NULL /* pszDesc */);
6696 if (RT_SUCCESS(rc))
6697 { /* likely */ }
6698 else
6699 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
6700 }
6701
6702 /* Virtualize-x2APIC mode is mutually exclusive with virtualize-APIC accesses. */
6703 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE)
6704 || !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
6705 { /* likely */ }
6706 else
6707 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6708
6709 /* Virtual-interrupt delivery requires external interrupt exiting. */
6710 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY)
6711 || (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT))
6712 { /* likely */ }
6713 else
6714 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VirtX2ApicVirtApic);
6715
6716 /* VPID. */
6717 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VPID)
6718 || pVmcs->u16Vpid != 0)
6719 { /* likely */ }
6720 else
6721 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_Vpid);
6722
6723 Assert(!(pVmcs->u32PinCtls & VMX_PIN_CTLS_POSTED_INT)); /* We don't support posted interrupts yet. */
6724 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT)); /* We don't support EPT yet. */
6725 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PML)); /* We don't support PML yet. */
6726 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)); /* We don't support Unrestricted-guests yet. */
6727 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMFUNC)); /* We don't support VM functions yet. */
6728 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT_VE)); /* We don't support EPT-violation #VE yet. */
6729 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)); /* We don't support Pause-loop exiting yet. */
6730
6731 /* VMCS shadowing. */
6732 if (pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
6733 {
6734 /* VMREAD-bitmap physical address. */
6735 RTGCPHYS const GCPhysVmreadBitmap = pVmcs->u64AddrVmreadBitmap.u;
6736 if ( !(GCPhysVmreadBitmap & X86_PAGE_4K_OFFSET_MASK)
6737 && !(GCPhysVmreadBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6738 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmreadBitmap))
6739 { /* likely */ }
6740 else
6741 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmreadBitmap);
6742
6743 /* VMWRITE-bitmap physical address. */
6744 RTGCPHYS const GCPhysVmwriteBitmap = pVmcs->u64AddrVmreadBitmap.u;
6745 if ( !(GCPhysVmwriteBitmap & X86_PAGE_4K_OFFSET_MASK)
6746 && !(GCPhysVmwriteBitmap >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth)
6747 && PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmwriteBitmap))
6748 { /* likely */ }
6749 else
6750 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrVmwriteBitmap);
6751
6752 /* Read the VMREAD-bitmap. */
6753 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
6754 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap),
6755 GCPhysVmreadBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6756 if (RT_SUCCESS(rc))
6757 { /* likely */ }
6758 else
6759 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys);
6760
6761 /* Read the VMWRITE-bitmap. */
6762 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap));
6763 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap),
6764 GCPhysVmwriteBitmap, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
6765 if (RT_SUCCESS(rc))
6766 { /* likely */ }
6767 else
6768 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys);
6769 }
6770
6771 NOREF(pszInstr);
6772 NOREF(pszFailure);
6773 return VINF_SUCCESS;
6774}
6775
6776
6777/**
6778 * Loads the guest control registers, debug register and some MSRs as part of
6779 * VM-entry.
6780 *
6781 * @param pVCpu The cross context virtual CPU structure.
6782 */
6783IEM_STATIC void iemVmxVmentryLoadGuestControlRegsMsrs(PVMCPU pVCpu)
6784{
6785 /*
6786 * Load guest control registers, debug registers and MSRs.
6787 * See Intel spec. 26.3.2.1 "Loading Guest Control Registers, Debug Registers and MSRs".
6788 */
6789 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6790
6791 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6792 uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u & ~VMX_ENTRY_CR0_IGNORE_MASK)
6793 | (pVCpu->cpum.GstCtx.cr0 & VMX_ENTRY_CR0_IGNORE_MASK);
6794 CPUMSetGuestCR0(pVCpu, uGstCr0);
6795 CPUMSetGuestCR4(pVCpu, pVmcs->u64GuestCr4.u);
6796 pVCpu->cpum.GstCtx.cr3 = pVmcs->u64GuestCr3.u;
6797
6798 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6799 pVCpu->cpum.GstCtx.dr[7] = (pVmcs->u64GuestDr7.u & ~VMX_ENTRY_DR7_MBZ_MASK) | VMX_ENTRY_DR7_MB1_MASK;
6800
6801 pVCpu->cpum.GstCtx.SysEnter.eip = pVmcs->u64GuestSysenterEip.s.Lo;
6802 pVCpu->cpum.GstCtx.SysEnter.esp = pVmcs->u64GuestSysenterEsp.s.Lo;
6803 pVCpu->cpum.GstCtx.SysEnter.cs = pVmcs->u32GuestSysenterCS;
6804
6805 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fLongMode)
6806 {
6807 /* FS base and GS base are loaded while loading the rest of the guest segment registers. */
6808
6809 /* EFER MSR. */
6810 if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
6811 {
6812 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6813 uint64_t const uHostEfer = pVCpu->cpum.GstCtx.msrEFER;
6814 bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
6815 bool const fGstPaging = RT_BOOL(uGstCr0 & X86_CR0_PG);
6816 if (fGstInLongMode)
6817 {
6818 /* If the nested-guest is in long mode, LMA and LME are both set. */
6819 Assert(fGstPaging);
6820 pVCpu->cpum.GstCtx.msrEFER = uHostEfer | (MSR_K6_EFER_LMA | MSR_K6_EFER_LME);
6821 }
6822 else
6823 {
6824 /*
6825 * If the nested-guest is outside long mode:
6826 * - With paging: LMA is cleared, LME is cleared.
6827 * - Without paging: LMA is cleared, LME is left unmodified.
6828 */
6829 uint64_t const fLmaLmeMask = MSR_K6_EFER_LMA | (fGstPaging ? MSR_K6_EFER_LME : 0);
6830 pVCpu->cpum.GstCtx.msrEFER = uHostEfer & ~fLmaLmeMask;
6831 }
6832 }
6833 /* else: see below. */
6834 }
6835
6836 /* PAT MSR. */
6837 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
6838 pVCpu->cpum.GstCtx.msrPAT = pVmcs->u64GuestPatMsr.u;
6839
6840 /* EFER MSR. */
6841 if (pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
6842 pVCpu->cpum.GstCtx.msrEFER = pVmcs->u64GuestEferMsr.u;
6843
6844 /* We don't support IA32_PERF_GLOBAL_CTRL MSR yet. */
6845 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR));
6846
6847 /* We don't support IA32_BNDCFGS MSR yet. */
6848 Assert(!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR));
6849
6850 /* Nothing to do for SMBASE register - We don't support SMM yet. */
6851}
6852
6853
6854/**
6855 * Loads the guest segment registers, GDTR, IDTR, LDTR and TR as part of VM-entry.
6856 *
6857 * @param pVCpu The cross context virtual CPU structure.
6858 */
6859IEM_STATIC void iemVmxVmentryLoadGuestSegRegs(PVMCPU pVCpu)
6860{
6861 /*
6862 * Load guest segment registers, GDTR, IDTR, LDTR and TR.
6863 * See Intel spec. 26.3.2.2 "Loading Guest Segment Registers and Descriptor-Table Registers".
6864 */
6865 /* CS, SS, ES, DS, FS, GS. */
6866 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6867 for (unsigned iSegReg = 0; iSegReg < X86_SREG_COUNT; iSegReg++)
6868 {
6869 PCPUMSELREG pGstSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
6870 CPUMSELREG VmcsSelReg;
6871 int rc = iemVmxVmcsGetGuestSegReg(pVmcs, iSegReg, &VmcsSelReg);
6872 AssertRC(rc); NOREF(rc);
6873 if (!(VmcsSelReg.Attr.u & X86DESCATTR_UNUSABLE))
6874 {
6875 pGstSelReg->Sel = VmcsSelReg.Sel;
6876 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6877 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6878 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6879 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6880 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6881 }
6882 else
6883 {
6884 pGstSelReg->Sel = VmcsSelReg.Sel;
6885 pGstSelReg->ValidSel = VmcsSelReg.Sel;
6886 pGstSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6887 switch (iSegReg)
6888 {
6889 case X86_SREG_CS:
6890 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6891 pGstSelReg->u32Limit = VmcsSelReg.u32Limit;
6892 pGstSelReg->Attr.u = VmcsSelReg.Attr.u;
6893 break;
6894
6895 case X86_SREG_SS:
6896 pGstSelReg->u64Base = VmcsSelReg.u64Base & UINT32_C(0xfffffff0);
6897 pGstSelReg->u32Limit = 0;
6898 pGstSelReg->Attr.u = (VmcsSelReg.Attr.u & X86DESCATTR_DPL) | X86DESCATTR_D | X86DESCATTR_UNUSABLE;
6899 break;
6900
6901 case X86_SREG_ES:
6902 case X86_SREG_DS:
6903 pGstSelReg->u64Base = 0;
6904 pGstSelReg->u32Limit = 0;
6905 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6906 break;
6907
6908 case X86_SREG_FS:
6909 case X86_SREG_GS:
6910 pGstSelReg->u64Base = VmcsSelReg.u64Base;
6911 pGstSelReg->u32Limit = 0;
6912 pGstSelReg->Attr.u = X86DESCATTR_UNUSABLE;
6913 break;
6914 }
6915 Assert(pGstSelReg->Attr.n.u1Unusable);
6916 }
6917 }
6918
6919 /* LDTR. */
6920 pVCpu->cpum.GstCtx.ldtr.Sel = pVmcs->GuestLdtr;
6921 pVCpu->cpum.GstCtx.ldtr.ValidSel = pVmcs->GuestLdtr;
6922 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
6923 if (!(pVmcs->u32GuestLdtrAttr & X86DESCATTR_UNUSABLE))
6924 {
6925 pVCpu->cpum.GstCtx.ldtr.u64Base = pVmcs->u64GuestLdtrBase.u;
6926 pVCpu->cpum.GstCtx.ldtr.u32Limit = pVmcs->u32GuestLdtrLimit;
6927 pVCpu->cpum.GstCtx.ldtr.Attr.u = pVmcs->u32GuestLdtrAttr;
6928 }
6929 else
6930 {
6931 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
6932 pVCpu->cpum.GstCtx.ldtr.u32Limit = 0;
6933 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
6934 }
6935
6936 /* TR. */
6937 Assert(!(pVmcs->u32GuestTrAttr & X86DESCATTR_UNUSABLE));
6938 pVCpu->cpum.GstCtx.tr.Sel = pVmcs->GuestTr;
6939 pVCpu->cpum.GstCtx.tr.ValidSel = pVmcs->GuestTr;
6940 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
6941 pVCpu->cpum.GstCtx.tr.u64Base = pVmcs->u64GuestTrBase.u;
6942 pVCpu->cpum.GstCtx.tr.u32Limit = pVmcs->u32GuestTrLimit;
6943 pVCpu->cpum.GstCtx.tr.Attr.u = pVmcs->u32GuestTrAttr;
6944
6945 /* GDTR. */
6946 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcs->u32GuestGdtrLimit;
6947 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcs->u64GuestGdtrBase.u;
6948
6949 /* IDTR. */
6950 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcs->u32GuestIdtrLimit;
6951 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcs->u64GuestIdtrBase.u;
6952}
6953
6954
6955/**
6956 * Loads the guest MSRs from the VM-entry auto-load MSRs as part of VM-entry.
6957 *
6958 * @returns VBox status code.
6959 * @param pVCpu The cross context virtual CPU structure.
6960 * @param pszInstr The VMX instruction name (for logging purposes).
6961 */
6962IEM_STATIC int iemVmxVmentryLoadGuestAutoMsrs(PVMCPU pVCpu, const char *pszInstr)
6963{
6964 /*
6965 * Load guest MSRs.
6966 * See Intel spec. 26.4 "Loading MSRs".
6967 */
6968 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
6969 const char *const pszFailure = "VM-exit";
6970
6971 /*
6972 * The VM-entry MSR-load area address need not be a valid guest-physical address if the
6973 * VM-entry MSR load count is 0. If this is the case, bail early without reading it.
6974 * See Intel spec. 24.8.2 "VM-Entry Controls for MSRs".
6975 */
6976 uint32_t const cMsrs = pVmcs->u32EntryMsrLoadCount;
6977 if (!cMsrs)
6978 return VINF_SUCCESS;
6979
6980 /*
6981 * Verify the MSR auto-load count. Physical CPUs can behave unpredictably if the count is
6982 * exceeded including possibly raising #MC exceptions during VMX transition. Our
6983 * implementation shall fail VM-entry with an VMX_EXIT_ERR_MSR_LOAD VM-exit.
6984 */
6985 bool const fIsMsrCountValid = iemVmxIsAutoMsrCountValid(pVCpu, cMsrs);
6986 if (fIsMsrCountValid)
6987 { /* likely */ }
6988 else
6989 {
6990 iemVmxVmcsSetExitQual(pVCpu, VMX_V_AUTOMSR_AREA_SIZE / sizeof(VMXAUTOMSR));
6991 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadCount);
6992 }
6993
6994 RTGCPHYS const GCPhysAutoMsrArea = pVmcs->u64AddrEntryMsrLoad.u;
6995 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea),
6996 GCPhysAutoMsrArea, cMsrs * sizeof(VMXAUTOMSR));
6997 if (RT_SUCCESS(rc))
6998 {
6999 PCVMXAUTOMSR pMsr = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pAutoMsrArea);
7000 Assert(pMsr);
7001 for (uint32_t idxMsr = 0; idxMsr < cMsrs; idxMsr++, pMsr++)
7002 {
7003 if ( !pMsr->u32Reserved
7004 && pMsr->u32Msr != MSR_K8_FS_BASE
7005 && pMsr->u32Msr != MSR_K8_GS_BASE
7006 && pMsr->u32Msr != MSR_K6_EFER
7007 && pMsr->u32Msr != MSR_IA32_SMM_MONITOR_CTL
7008 && pMsr->u32Msr >> 8 != MSR_IA32_X2APIC_START >> 8)
7009 {
7010 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pMsr->u32Msr, pMsr->u64Value);
7011 if (rcStrict == VINF_SUCCESS)
7012 continue;
7013
7014 /*
7015 * If we're in ring-0, we cannot handle returns to ring-3 at this point and continue VM-entry.
7016 * If any guest hypervisor loads MSRs that require ring-3 handling, we cause a VM-entry failure
7017 * recording the MSR index in the VM-exit qualification (as per the Intel spec.) and indicated
7018 * further by our own, specific diagnostic code. Later, we can try implement handling of the
7019 * MSR in ring-0 if possible, or come up with a better, generic solution.
7020 */
7021 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7022 VMXVDIAG const enmDiag = rcStrict == VINF_CPUM_R3_MSR_WRITE
7023 ? kVmxVDiag_Vmentry_MsrLoadRing3
7024 : kVmxVDiag_Vmentry_MsrLoad;
7025 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, enmDiag);
7026 }
7027 else
7028 {
7029 iemVmxVmcsSetExitQual(pVCpu, idxMsr);
7030 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadRsvd);
7031 }
7032 }
7033 }
7034 else
7035 {
7036 AssertMsgFailed(("%s: Failed to read MSR auto-load area at %#RGp, rc=%Rrc\n", pszInstr, GCPhysAutoMsrArea, rc));
7037 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_MsrLoadPtrReadPhys);
7038 }
7039
7040 NOREF(pszInstr);
7041 NOREF(pszFailure);
7042 return VINF_SUCCESS;
7043}
7044
7045
7046/**
7047 * Loads the guest-state non-register state as part of VM-entry.
7048 *
7049 * @returns VBox status code.
7050 * @param pVCpu The cross context virtual CPU structure.
7051 *
7052 * @remarks This must be called only after loading the nested-guest register state
7053 * (especially nested-guest RIP).
7054 */
7055IEM_STATIC void iemVmxVmentryLoadGuestNonRegState(PVMCPU pVCpu)
7056{
7057 /*
7058 * Load guest non-register state.
7059 * See Intel spec. 26.6 "Special Features of VM Entry"
7060 */
7061 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7062
7063 /*
7064 * If VM-entry is not vectoring, block-by-STI and block-by-MovSS state must be loaded.
7065 * If VM-entry is vectoring, there is no block-by-STI or block-by-MovSS.
7066 *
7067 * See Intel spec. 26.6.1 "Interruptibility State".
7068 */
7069 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, NULL /* puEntryIntInfoType */);
7070 if ( !fEntryVectoring
7071 && (pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)))
7072 EMSetInhibitInterruptsPC(pVCpu, pVmcs->u64GuestRip.u);
7073 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7074 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7075
7076 /* NMI blocking. */
7077 if ( (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
7078 && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7079 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
7080
7081 /* SMI blocking is irrelevant. We don't support SMIs yet. */
7082
7083 /* Loading PDPTEs will be taken care when we switch modes. We don't support EPT yet. */
7084 Assert(!(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_EPT));
7085
7086 /* VPID is irrelevant. We don't support VPID yet. */
7087
7088 /* Clear address-range monitoring. */
7089 EMMonitorWaitClear(pVCpu);
7090}
7091
7092
7093/**
7094 * Loads the guest-state as part of VM-entry.
7095 *
7096 * @returns VBox status code.
7097 * @param pVCpu The cross context virtual CPU structure.
7098 * @param pszInstr The VMX instruction name (for logging purposes).
7099 *
7100 * @remarks This must be done after all the necessary steps prior to loading of
7101 * guest-state (e.g. checking various VMCS state).
7102 */
7103IEM_STATIC int iemVmxVmentryLoadGuestState(PVMCPU pVCpu, const char *pszInstr)
7104{
7105 iemVmxVmentryLoadGuestControlRegsMsrs(pVCpu);
7106 iemVmxVmentryLoadGuestSegRegs(pVCpu);
7107
7108 /*
7109 * Load guest RIP, RSP and RFLAGS.
7110 * See Intel spec. 26.3.2.3 "Loading Guest RIP, RSP and RFLAGS".
7111 */
7112 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7113 pVCpu->cpum.GstCtx.rsp = pVmcs->u64GuestRsp.u;
7114 pVCpu->cpum.GstCtx.rip = pVmcs->u64GuestRip.u;
7115 pVCpu->cpum.GstCtx.rflags.u = pVmcs->u64GuestRFlags.u;
7116
7117 /* Initialize the PAUSE-loop controls as part of VM-entry. */
7118 pVCpu->cpum.GstCtx.hwvirt.vmx.uFirstPauseLoopTick = 0;
7119 pVCpu->cpum.GstCtx.hwvirt.vmx.uPrevPauseTick = 0;
7120
7121 iemVmxVmentryLoadGuestNonRegState(pVCpu);
7122
7123 NOREF(pszInstr);
7124 return VINF_SUCCESS;
7125}
7126
7127
7128/**
7129 * Returns whether there are is a pending debug exception on VM-entry.
7130 *
7131 * @param pVCpu The cross context virtual CPU structure.
7132 * @param pszInstr The VMX instruction name (for logging purposes).
7133 */
7134IEM_STATIC bool iemVmxVmentryIsPendingDebugXcpt(PVMCPU pVCpu, const char *pszInstr)
7135{
7136 /*
7137 * Pending debug exceptions.
7138 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7139 */
7140 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7141 Assert(pVmcs);
7142
7143 bool fPendingDbgXcpt = RT_BOOL(pVmcs->u64GuestPendingDbgXcpt.u & ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS
7144 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP));
7145 if (fPendingDbgXcpt)
7146 {
7147 uint8_t uEntryIntInfoType;
7148 bool const fEntryVectoring = HMVmxIsVmentryVectoring(pVmcs->u32EntryIntInfo, &uEntryIntInfoType);
7149 if (fEntryVectoring)
7150 {
7151 switch (uEntryIntInfoType)
7152 {
7153 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7154 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7155 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7156 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
7157 fPendingDbgXcpt = false;
7158 break;
7159
7160 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
7161 {
7162 /*
7163 * Whether the pending debug exception for software exceptions other than
7164 * #BP and #OF is delivered after injecting the exception or is discard
7165 * is CPU implementation specific. We will discard them (easier).
7166 */
7167 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo);
7168 if ( uVector != X86_XCPT_BP
7169 && uVector != X86_XCPT_OF)
7170 fPendingDbgXcpt = false;
7171 RT_FALL_THRU();
7172 }
7173 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7174 {
7175 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
7176 fPendingDbgXcpt = false;
7177 break;
7178 }
7179 }
7180 }
7181 else
7182 {
7183 /*
7184 * When the VM-entry is not vectoring but there is blocking-by-MovSS, whether the
7185 * pending debug exception is held pending or is discarded is CPU implementation
7186 * specific. We will discard them (easier).
7187 */
7188 if (pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
7189 fPendingDbgXcpt = false;
7190
7191 /* There's no pending debug exception in the shutdown or wait-for-SIPI state. */
7192 if (pVmcs->u32GuestActivityState & (VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN | VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT))
7193 fPendingDbgXcpt = false;
7194 }
7195 }
7196
7197 NOREF(pszInstr);
7198 return fPendingDbgXcpt;
7199}
7200
7201
7202/**
7203 * Set up the monitor-trap flag (MTF).
7204 *
7205 * @param pVCpu The cross context virtual CPU structure.
7206 * @param pszInstr The VMX instruction name (for logging purposes).
7207 */
7208IEM_STATIC void iemVmxVmentrySetupMtf(PVMCPU pVCpu, const char *pszInstr)
7209{
7210 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7211 Assert(pVmcs);
7212 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
7213 {
7214 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7215 Log(("%s: Monitor-trap flag set on VM-entry\n", pszInstr));
7216 }
7217 else
7218 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF));
7219 NOREF(pszInstr);
7220}
7221
7222
7223/**
7224 * Set up the VMX-preemption timer.
7225 *
7226 * @param pVCpu The cross context virtual CPU structure.
7227 * @param pszInstr The VMX instruction name (for logging purposes).
7228 */
7229IEM_STATIC void iemVmxVmentrySetupPreemptTimer(PVMCPU pVCpu, const char *pszInstr)
7230{
7231 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7232 Assert(pVmcs);
7233 if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
7234 {
7235 uint64_t const uVmentryTick = TMCpuTickGetNoCheck(pVCpu);
7236 pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick = uVmentryTick;
7237 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
7238
7239 Log(("%s: VM-entry set up VMX-preemption timer at %#RX64\n", pszInstr, uVmentryTick));
7240 }
7241 else
7242 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER));
7243
7244 NOREF(pszInstr);
7245}
7246
7247
7248/**
7249 * Injects an event using TRPM given a VM-entry interruption info. and related
7250 * fields.
7251 *
7252 * @returns VBox status code.
7253 * @param pVCpu The cross context virtual CPU structure.
7254 * @param uEntryIntInfo The VM-entry interruption info.
7255 * @param uErrCode The error code associated with the event if any.
7256 * @param cbInstr The VM-entry instruction length (for software
7257 * interrupts and software exceptions). Pass 0
7258 * otherwise.
7259 * @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
7260 */
7261IEM_STATIC int iemVmxVmentryInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
7262 RTGCUINTPTR GCPtrFaultAddress)
7263{
7264 Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
7265
7266 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7267 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
7268 bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
7269
7270 TRPMEVENT enmTrapType;
7271 switch (uType)
7272 {
7273 case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
7274 enmTrapType = TRPM_HARDWARE_INT;
7275 break;
7276
7277 case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
7278 enmTrapType = TRPM_SOFTWARE_INT;
7279 break;
7280
7281 case VMX_ENTRY_INT_INFO_TYPE_NMI:
7282 case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* ICEBP. */
7283 case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7284 case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
7285 enmTrapType = TRPM_TRAP;
7286 break;
7287
7288 default:
7289 /* Shouldn't really happen. */
7290 AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
7291 break;
7292 }
7293
7294 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7295 AssertRCReturn(rc, rc);
7296
7297 if (fErrCodeValid)
7298 TRPMSetErrorCode(pVCpu, uErrCode);
7299
7300 if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
7301 && uVector == X86_XCPT_PF)
7302 TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
7303 else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
7304 || uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
7305 || uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
7306 {
7307 AssertMsg( uType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7308 || (uVector == X86_XCPT_BP || uVector == X86_XCPT_OF),
7309 ("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uType));
7310 TRPMSetInstrLength(pVCpu, cbInstr);
7311 }
7312
7313 return VINF_SUCCESS;
7314}
7315
7316
7317/**
7318 * Performs event injection (if any) as part of VM-entry.
7319 *
7320 * @param pVCpu The cross context virtual CPU structure.
7321 * @param pszInstr The VMX instruction name (for logging purposes).
7322 */
7323IEM_STATIC int iemVmxVmentryInjectEvent(PVMCPU pVCpu, const char *pszInstr)
7324{
7325 /*
7326 * Inject events.
7327 * The event that is going to be made pending for injection is not subject to VMX intercepts,
7328 * thus we flag ignoring of intercepts. However, recursive exceptions if any during delivery
7329 * of the current event -are- subject to intercepts, hence this flag will be flipped during
7330 * the actually delivery of this event.
7331 *
7332 * See Intel spec. 26.5 "Event Injection".
7333 */
7334 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7335 uint32_t const uEntryIntInfo = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32EntryIntInfo;
7336 bool const fEntryIntInfoValid = VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo);
7337
7338 pVCpu->cpum.GstCtx.hwvirt.vmx.fInterceptEvents = !fEntryIntInfoValid;
7339 if (fEntryIntInfoValid)
7340 {
7341 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
7342 if (uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT)
7343 {
7344 Assert(VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo) == VMX_ENTRY_INT_INFO_VECTOR_MTF);
7345 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_MTF);
7346 return VINF_SUCCESS;
7347 }
7348
7349 return iemVmxVmentryInjectTrpmEvent(pVCpu, uEntryIntInfo, pVmcs->u32EntryXcptErrCode, pVmcs->u32EntryInstrLen,
7350 pVCpu->cpum.GstCtx.cr2);
7351 }
7352
7353 /*
7354 * Inject any pending guest debug exception.
7355 * Unlike injecting events, this #DB injection on VM-entry is subject to #DB VMX intercept.
7356 * See Intel spec. 26.6.3 "Delivery of Pending Debug Exceptions after VM Entry".
7357 */
7358 bool const fPendingDbgXcpt = iemVmxVmentryIsPendingDebugXcpt(pVCpu, pszInstr);
7359 if (fPendingDbgXcpt)
7360 {
7361 uint32_t const uDbgXcptInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7362 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
7363 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7364 return iemVmxVmentryInjectTrpmEvent(pVCpu, uDbgXcptInfo, 0 /* uErrCode */, pVmcs->u32EntryInstrLen,
7365 0 /* GCPtrFaultAddress */);
7366 }
7367
7368 NOREF(pszInstr);
7369 return VINF_SUCCESS;
7370}
7371
7372
7373/**
7374 * Initializes all read-only VMCS fields as part of VM-entry.
7375 *
7376 * @param pVCpu The cross context virtual CPU structure.
7377 */
7378IEM_STATIC void iemVmxVmentryInitReadOnlyFields(PVMCPU pVCpu)
7379{
7380 /*
7381 * Any VMCS field which we do not establish on every VM-exit but may potentially
7382 * be used on the VM-exit path of a nested hypervisor -and- is not explicitly
7383 * specified to be undefined needs to be initialized here.
7384 *
7385 * Thus, it is especially important to clear the VM-exit qualification field
7386 * since it must be zero for VM-exits where it is not used. Similarly, the
7387 * VM-exit interruption information field's valid bit needs to be cleared for
7388 * the same reasons.
7389 */
7390 PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7391 Assert(pVmcs);
7392
7393 /* 16-bit (none currently). */
7394 /* 32-bit. */
7395 pVmcs->u32RoVmInstrError = 0;
7396 pVmcs->u32RoExitReason = 0;
7397 pVmcs->u32RoExitIntInfo = 0;
7398 pVmcs->u32RoExitIntErrCode = 0;
7399 pVmcs->u32RoIdtVectoringInfo = 0;
7400 pVmcs->u32RoIdtVectoringErrCode = 0;
7401 pVmcs->u32RoExitInstrLen = 0;
7402 pVmcs->u32RoExitInstrInfo = 0;
7403
7404 /* 64-bit. */
7405 pVmcs->u64RoGuestPhysAddr.u = 0;
7406
7407 /* Natural-width. */
7408 pVmcs->u64RoExitQual.u = 0;
7409 pVmcs->u64RoIoRcx.u = 0;
7410 pVmcs->u64RoIoRsi.u = 0;
7411 pVmcs->u64RoIoRdi.u = 0;
7412 pVmcs->u64RoIoRip.u = 0;
7413 pVmcs->u64RoGuestLinearAddr.u = 0;
7414}
7415
7416
7417/**
7418 * VMLAUNCH/VMRESUME instruction execution worker.
7419 *
7420 * @returns Strict VBox status code.
7421 * @param pVCpu The cross context virtual CPU structure.
7422 * @param cbInstr The instruction length in bytes.
7423 * @param uInstrId The instruction identity (VMXINSTRID_VMLAUNCH or
7424 * VMXINSTRID_VMRESUME).
7425 *
7426 * @remarks Common VMX instruction checks are already expected to by the caller,
7427 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
7428 */
7429IEM_STATIC VBOXSTRICTRC iemVmxVmlaunchVmresume(PVMCPU pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId)
7430{
7431# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
7432 RT_NOREF3(pVCpu, cbInstr, uInstrId);
7433 return VINF_EM_RAW_EMULATE_INSTR;
7434# else
7435 Assert( uInstrId == VMXINSTRID_VMLAUNCH
7436 || uInstrId == VMXINSTRID_VMRESUME);
7437 const char *pszInstr = uInstrId == VMXINSTRID_VMRESUME ? "vmresume" : "vmlaunch";
7438
7439 /* Nested-guest intercept. */
7440 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7441 return iemVmxVmexitInstr(pVCpu, uInstrId == VMXINSTRID_VMRESUME ? VMX_EXIT_VMRESUME : VMX_EXIT_VMLAUNCH, cbInstr);
7442
7443 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
7444
7445 /*
7446 * Basic VM-entry checks.
7447 * The order of the CPL, current and shadow VMCS and block-by-MovSS are important.
7448 * The checks following that do not have to follow a specific order.
7449 *
7450 * See Intel spec. 26.1 "Basic VM-entry Checks".
7451 */
7452
7453 /* CPL. */
7454 if (pVCpu->iem.s.uCpl == 0)
7455 { /* likely */ }
7456 else
7457 {
7458 Log(("%s: CPL %u -> #GP(0)\n", pszInstr, pVCpu->iem.s.uCpl));
7459 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_Cpl;
7460 return iemRaiseGeneralProtectionFault0(pVCpu);
7461 }
7462
7463 /* Current VMCS valid. */
7464 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7465 { /* likely */ }
7466 else
7467 {
7468 Log(("%s: VMCS pointer %#RGp invalid -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7469 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrInvalid;
7470 iemVmxVmFailInvalid(pVCpu);
7471 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7472 return VINF_SUCCESS;
7473 }
7474
7475 /* Current VMCS is not a shadow VMCS. */
7476 if (!pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->u32VmcsRevId.n.fIsShadowVmcs)
7477 { /* likely */ }
7478 else
7479 {
7480 Log(("%s: VMCS pointer %#RGp is a shadow VMCS -> VMFailInvalid\n", pszInstr, IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7481 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_PtrShadowVmcs;
7482 iemVmxVmFailInvalid(pVCpu);
7483 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7484 return VINF_SUCCESS;
7485 }
7486
7487 /** @todo Distinguish block-by-MovSS from block-by-STI. Currently we
7488 * use block-by-STI here which is not quite correct. */
7489 if ( !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
7490 || pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
7491 { /* likely */ }
7492 else
7493 {
7494 Log(("%s: VM entry with events blocked by MOV SS -> VMFail\n", pszInstr));
7495 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_BlocKMovSS;
7496 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_BLOCK_MOVSS);
7497 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7498 return VINF_SUCCESS;
7499 }
7500
7501 if (uInstrId == VMXINSTRID_VMLAUNCH)
7502 {
7503 /* VMLAUNCH with non-clear VMCS. */
7504 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_CLEAR)
7505 { /* likely */ }
7506 else
7507 {
7508 Log(("vmlaunch: VMLAUNCH with non-clear VMCS -> VMFail\n"));
7509 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsClear;
7510 iemVmxVmFail(pVCpu, VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS);
7511 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7512 return VINF_SUCCESS;
7513 }
7514 }
7515 else
7516 {
7517 /* VMRESUME with non-launched VMCS. */
7518 if (pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState == VMX_V_VMCS_STATE_LAUNCHED)
7519 { /* likely */ }
7520 else
7521 {
7522 Log(("vmresume: VMRESUME with non-launched VMCS -> VMFail\n"));
7523 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmentry_VmcsLaunch;
7524 iemVmxVmFail(pVCpu, VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS);
7525 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7526 return VINF_SUCCESS;
7527 }
7528 }
7529
7530 /*
7531 * We are allowed to cache VMCS related data structures (such as I/O bitmaps, MSR bitmaps)
7532 * while entering VMX non-root mode. We do some of this while checking VM-execution
7533 * controls. The guest hypervisor should not make assumptions and cannot expect
7534 * predictable behavior if changes to these structures are made in guest memory while
7535 * executing in VMX non-root mode. As far as VirtualBox is concerned, the guest cannot
7536 * modify them anyway as we cache them in host memory. We are trade memory for speed here.
7537 *
7538 * See Intel spec. 24.11.4 "Software Access to Related Structures".
7539 */
7540 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
7541 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
7542 int rc = iemVmxVmentryCheckExecCtls(pVCpu, pszInstr);
7543 if (RT_SUCCESS(rc))
7544 {
7545 rc = iemVmxVmentryCheckExitCtls(pVCpu, pszInstr);
7546 if (RT_SUCCESS(rc))
7547 {
7548 rc = iemVmxVmentryCheckEntryCtls(pVCpu, pszInstr);
7549 if (RT_SUCCESS(rc))
7550 {
7551 rc = iemVmxVmentryCheckHostState(pVCpu, pszInstr);
7552 if (RT_SUCCESS(rc))
7553 {
7554 /* Initialize read-only VMCS fields before VM-entry since we don't update all of them for every VM-exit. */
7555 iemVmxVmentryInitReadOnlyFields(pVCpu);
7556
7557 /*
7558 * Blocking of NMIs need to be restored if VM-entry fails due to invalid-guest state.
7559 * So we save the the VMCPU_FF_BLOCK_NMI force-flag here so we can restore it on
7560 * VM-exit when required.
7561 * See Intel spec. 26.7 "VM-entry Failures During or After Loading Guest State"
7562 */
7563 iemVmxVmentrySaveNmiBlockingFF(pVCpu);
7564
7565 rc = iemVmxVmentryCheckGuestState(pVCpu, pszInstr);
7566 if (RT_SUCCESS(rc))
7567 {
7568 rc = iemVmxVmentryLoadGuestState(pVCpu, pszInstr);
7569 if (RT_SUCCESS(rc))
7570 {
7571 rc = iemVmxVmentryLoadGuestAutoMsrs(pVCpu, pszInstr);
7572 if (RT_SUCCESS(rc))
7573 {
7574 Assert(rc != VINF_CPUM_R3_MSR_WRITE);
7575
7576 /* VMLAUNCH instruction must update the VMCS launch state. */
7577 if (uInstrId == VMXINSTRID_VMLAUNCH)
7578 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = VMX_V_VMCS_STATE_LAUNCHED;
7579
7580 /* Perform the VMX transition (PGM updates). */
7581 VBOXSTRICTRC rcStrict = iemVmxWorldSwitch(pVCpu);
7582 if (rcStrict == VINF_SUCCESS)
7583 { /* likely */ }
7584 else if (RT_SUCCESS(rcStrict))
7585 {
7586 Log3(("%s: iemVmxWorldSwitch returns %Rrc -> Setting passup status\n", pszInstr,
7587 VBOXSTRICTRC_VAL(rcStrict)));
7588 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7589 }
7590 else
7591 {
7592 Log3(("%s: iemVmxWorldSwitch failed! rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7593 return rcStrict;
7594 }
7595
7596 /* We've now entered nested-guest execution. */
7597 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode = true;
7598
7599 /*
7600 * The priority of potential VM-exits during VM-entry is important.
7601 * The priorities of VM-exits and events are listed from highest
7602 * to lowest as follows:
7603 *
7604 * 1. Event injection.
7605 * 2. Trap on task-switch (T flag set in TSS).
7606 * 3. TPR below threshold / APIC-write.
7607 * 4. SMI, INIT.
7608 * 5. MTF exit.
7609 * 6. Debug-trap exceptions (EFLAGS.TF), pending debug exceptions.
7610 * 7. VMX-preemption timer.
7611 * 9. NMI-window exit.
7612 * 10. NMI injection.
7613 * 11. Interrupt-window exit.
7614 * 12. Virtual-interrupt injection.
7615 * 13. Interrupt injection.
7616 * 14. Process next instruction (fetch, decode, execute).
7617 */
7618
7619 /* Setup the VMX-preemption timer. */
7620 iemVmxVmentrySetupPreemptTimer(pVCpu, pszInstr);
7621
7622 /* Setup monitor-trap flag. */
7623 iemVmxVmentrySetupMtf(pVCpu, pszInstr);
7624
7625 /* Now that we've switched page tables, we can go ahead and inject any event. */
7626 rcStrict = iemVmxVmentryInjectEvent(pVCpu, pszInstr);
7627 if (RT_SUCCESS(rcStrict))
7628 {
7629 /* Reschedule to IEM-only execution of the nested-guest or return VINF_SUCCESS. */
7630 IEM_VMX_R3_EXECPOLICY_IEM_ALL_ENABLE_RET(pVCpu, pszInstr, VINF_SUCCESS);
7631 }
7632
7633 Log(("%s: VM-entry event injection failed. rc=%Rrc\n", pszInstr, VBOXSTRICTRC_VAL(rcStrict)));
7634 return rcStrict;
7635 }
7636 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_MSR_LOAD | VMX_EXIT_REASON_ENTRY_FAILED);
7637 }
7638 }
7639 return iemVmxVmexit(pVCpu, VMX_EXIT_ERR_INVALID_GUEST_STATE | VMX_EXIT_REASON_ENTRY_FAILED);
7640 }
7641
7642 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_HOST_STATE);
7643 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7644 return VINF_SUCCESS;
7645 }
7646 }
7647 }
7648
7649 iemVmxVmFail(pVCpu, VMXINSTRERR_VMENTRY_INVALID_CTLS);
7650 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7651 return VINF_SUCCESS;
7652# endif
7653}
7654
7655
7656/**
7657 * Checks whether an RDMSR or WRMSR instruction for the given MSR is intercepted
7658 * (causes a VM-exit) or not.
7659 *
7660 * @returns @c true if the instruction is intercepted, @c false otherwise.
7661 * @param pVCpu The cross context virtual CPU structure.
7662 * @param uExitReason The VM-exit reason (VMX_EXIT_RDMSR or
7663 * VMX_EXIT_WRMSR).
7664 * @param idMsr The MSR.
7665 */
7666IEM_STATIC bool iemVmxIsRdmsrWrmsrInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr)
7667{
7668 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7669 Assert( uExitReason == VMX_EXIT_RDMSR
7670 || uExitReason == VMX_EXIT_WRMSR);
7671
7672 /* Consult the MSR bitmap if the feature is supported. */
7673 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7674 Assert(pVmcs);
7675 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
7676 {
7677 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap));
7678 if (uExitReason == VMX_EXIT_RDMSR)
7679 {
7680 VMXMSREXITREAD enmRead;
7681 int rc = HMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, &enmRead,
7682 NULL /* penmWrite */);
7683 AssertRC(rc);
7684 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
7685 return true;
7686 }
7687 else
7688 {
7689 VMXMSREXITWRITE enmWrite;
7690 int rc = HMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), idMsr, NULL /* penmRead */,
7691 &enmWrite);
7692 AssertRC(rc);
7693 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
7694 return true;
7695 }
7696 return false;
7697 }
7698
7699 /* Without MSR bitmaps, all MSR accesses are intercepted. */
7700 return true;
7701}
7702
7703
7704/**
7705 * Checks whether a VMREAD or VMWRITE instruction for the given VMCS field is
7706 * intercepted (causes a VM-exit) or not.
7707 *
7708 * @returns @c true if the instruction is intercepted, @c false otherwise.
7709 * @param pVCpu The cross context virtual CPU structure.
7710 * @param u64FieldEnc The VMCS field encoding.
7711 * @param uExitReason The VM-exit reason (VMX_EXIT_VMREAD or
7712 * VMX_EXIT_VMREAD).
7713 */
7714IEM_STATIC bool iemVmxIsVmreadVmwriteInterceptSet(PVMCPU pVCpu, uint32_t uExitReason, uint64_t u64FieldEnc)
7715{
7716 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
7717 Assert( uExitReason == VMX_EXIT_VMREAD
7718 || uExitReason == VMX_EXIT_VMWRITE);
7719
7720 /* Without VMCS shadowing, all VMREAD and VMWRITE instructions are intercepted. */
7721 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing)
7722 return true;
7723
7724 /*
7725 * If any reserved bit in the 64-bit VMCS field encoding is set, the VMREAD/VMWRITE is intercepted.
7726 * This excludes any reserved bits in the valid parts of the field encoding (i.e. bit 12).
7727 */
7728 if (u64FieldEnc & VMX_VMCS_ENC_RSVD_MASK)
7729 return true;
7730
7731 /* Finally, consult the VMREAD/VMWRITE bitmap whether to intercept the instruction or not. */
7732 uint32_t const u32FieldEnc = RT_LO_U32(u64FieldEnc);
7733 Assert(u32FieldEnc >> 3 < VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
7734 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap));
7735 uint8_t const *pbBitmap = uExitReason == VMX_EXIT_VMREAD
7736 ? (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmreadBitmap)
7737 : (uint8_t const *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap);
7738 pbBitmap += (u32FieldEnc >> 3);
7739 if (*pbBitmap & RT_BIT(u32FieldEnc & 7))
7740 return true;
7741
7742 return false;
7743}
7744
7745
7746/**
7747 * VMREAD common (memory/register) instruction execution worker
7748 *
7749 * @returns Strict VBox status code.
7750 * @param pVCpu The cross context virtual CPU structure.
7751 * @param cbInstr The instruction length in bytes.
7752 * @param pu64Dst Where to write the VMCS value (only updated when
7753 * VINF_SUCCESS is returned).
7754 * @param u64FieldEnc The VMCS field encoding.
7755 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7756 * be NULL.
7757 */
7758IEM_STATIC VBOXSTRICTRC iemVmxVmreadCommon(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7759 PCVMXVEXITINFO pExitInfo)
7760{
7761 /* Nested-guest intercept. */
7762 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7763 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMREAD, u64FieldEnc))
7764 {
7765 if (pExitInfo)
7766 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7767 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMREAD, VMXINSTRID_VMREAD, cbInstr);
7768 }
7769
7770 /* CPL. */
7771 if (pVCpu->iem.s.uCpl == 0)
7772 { /* likely */ }
7773 else
7774 {
7775 Log(("vmread: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
7776 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_Cpl;
7777 return iemRaiseGeneralProtectionFault0(pVCpu);
7778 }
7779
7780 /* VMCS pointer in root mode. */
7781 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
7782 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
7783 { /* likely */ }
7784 else
7785 {
7786 Log(("vmread: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
7787 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrInvalid;
7788 iemVmxVmFailInvalid(pVCpu);
7789 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7790 return VINF_SUCCESS;
7791 }
7792
7793 /* VMCS-link pointer in non-root mode. */
7794 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7795 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
7796 { /* likely */ }
7797 else
7798 {
7799 Log(("vmread: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
7800 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_LinkPtrInvalid;
7801 iemVmxVmFailInvalid(pVCpu);
7802 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7803 return VINF_SUCCESS;
7804 }
7805
7806 /* Supported VMCS field. */
7807 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
7808 { /* likely */ }
7809 else
7810 {
7811 Log(("vmread: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
7812 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_FieldInvalid;
7813 iemVmxVmFail(pVCpu, VMXINSTRERR_VMREAD_INVALID_COMPONENT);
7814 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7815 return VINF_SUCCESS;
7816 }
7817
7818 /*
7819 * Setup reading from the current or shadow VMCS.
7820 */
7821 uint8_t *pbVmcs;
7822 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7823 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7824 else
7825 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
7826 Assert(pbVmcs);
7827
7828 VMXVMCSFIELDENC FieldEnc;
7829 FieldEnc.u = u64FieldEnc;
7830 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
7831 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
7832 uint8_t const uWidthType = (uWidth << 2) | uType;
7833 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
7834 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
7835 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
7836 Assert(offField < VMX_V_VMCS_SIZE);
7837
7838 /*
7839 * Read the VMCS component based on the field's effective width.
7840 *
7841 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
7842 * indicates high bits (little endian).
7843 *
7844 * Note! The caller is responsible to trim the result and update registers
7845 * or memory locations are required. Here we just zero-extend to the largest
7846 * type (i.e. 64-bits).
7847 */
7848 uint8_t *pbField = pbVmcs + offField;
7849 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
7850 switch (uEffWidth)
7851 {
7852 case VMX_VMCS_ENC_WIDTH_64BIT:
7853 case VMX_VMCS_ENC_WIDTH_NATURAL: *pu64Dst = *(uint64_t *)pbField; break;
7854 case VMX_VMCS_ENC_WIDTH_32BIT: *pu64Dst = *(uint32_t *)pbField; break;
7855 case VMX_VMCS_ENC_WIDTH_16BIT: *pu64Dst = *(uint16_t *)pbField; break;
7856 }
7857 return VINF_SUCCESS;
7858}
7859
7860
7861/**
7862 * VMREAD (64-bit register) instruction execution worker.
7863 *
7864 * @returns Strict VBox status code.
7865 * @param pVCpu The cross context virtual CPU structure.
7866 * @param cbInstr The instruction length in bytes.
7867 * @param pu64Dst Where to store the VMCS field's value.
7868 * @param u64FieldEnc The VMCS field encoding.
7869 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7870 * be NULL.
7871 */
7872IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg64(PVMCPU pVCpu, uint8_t cbInstr, uint64_t *pu64Dst, uint64_t u64FieldEnc,
7873 PCVMXVEXITINFO pExitInfo)
7874{
7875 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, pu64Dst, u64FieldEnc, pExitInfo);
7876 if (rcStrict == VINF_SUCCESS)
7877 {
7878 iemVmxVmreadSuccess(pVCpu, cbInstr);
7879 return VINF_SUCCESS;
7880 }
7881
7882 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7883 return rcStrict;
7884}
7885
7886
7887/**
7888 * VMREAD (32-bit register) instruction execution worker.
7889 *
7890 * @returns Strict VBox status code.
7891 * @param pVCpu The cross context virtual CPU structure.
7892 * @param cbInstr The instruction length in bytes.
7893 * @param pu32Dst Where to store the VMCS field's value.
7894 * @param u32FieldEnc The VMCS field encoding.
7895 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7896 * be NULL.
7897 */
7898IEM_STATIC VBOXSTRICTRC iemVmxVmreadReg32(PVMCPU pVCpu, uint8_t cbInstr, uint32_t *pu32Dst, uint64_t u32FieldEnc,
7899 PCVMXVEXITINFO pExitInfo)
7900{
7901 uint64_t u64Dst;
7902 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u32FieldEnc, pExitInfo);
7903 if (rcStrict == VINF_SUCCESS)
7904 {
7905 *pu32Dst = u64Dst;
7906 iemVmxVmreadSuccess(pVCpu, cbInstr);
7907 return VINF_SUCCESS;
7908 }
7909
7910 Log(("vmread/reg: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7911 return rcStrict;
7912}
7913
7914
7915/**
7916 * VMREAD (memory) instruction execution worker.
7917 *
7918 * @returns Strict VBox status code.
7919 * @param pVCpu The cross context virtual CPU structure.
7920 * @param cbInstr The instruction length in bytes.
7921 * @param iEffSeg The effective segment register to use with @a u64Val.
7922 * Pass UINT8_MAX if it is a register access.
7923 * @param enmEffAddrMode The effective addressing mode (only used with memory
7924 * operand).
7925 * @param GCPtrDst The guest linear address to store the VMCS field's
7926 * value.
7927 * @param u64FieldEnc The VMCS field encoding.
7928 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7929 * be NULL.
7930 */
7931IEM_STATIC VBOXSTRICTRC iemVmxVmreadMem(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode,
7932 RTGCPTR GCPtrDst, uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
7933{
7934 uint64_t u64Dst;
7935 VBOXSTRICTRC rcStrict = iemVmxVmreadCommon(pVCpu, cbInstr, &u64Dst, u64FieldEnc, pExitInfo);
7936 if (rcStrict == VINF_SUCCESS)
7937 {
7938 /*
7939 * Write the VMCS field's value to the location specified in guest-memory.
7940 *
7941 * The pointer size depends on the address size (address-size prefix allowed).
7942 * The operand size depends on IA-32e mode (operand-size prefix not allowed).
7943 */
7944 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
7945 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
7946 GCPtrDst &= s_auAddrSizeMasks[enmEffAddrMode];
7947
7948 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7949 rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7950 else
7951 rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrDst, u64Dst);
7952 if (rcStrict == VINF_SUCCESS)
7953 {
7954 iemVmxVmreadSuccess(pVCpu, cbInstr);
7955 return VINF_SUCCESS;
7956 }
7957
7958 Log(("vmread/mem: Failed to write to memory operand at %#RGv, rc=%Rrc\n", GCPtrDst, VBOXSTRICTRC_VAL(rcStrict)));
7959 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmread_PtrMap;
7960 return rcStrict;
7961 }
7962
7963 Log(("vmread/mem: iemVmxVmreadCommon failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7964 return rcStrict;
7965}
7966
7967
7968/**
7969 * VMWRITE instruction execution worker.
7970 *
7971 * @returns Strict VBox status code.
7972 * @param pVCpu The cross context virtual CPU structure.
7973 * @param cbInstr The instruction length in bytes.
7974 * @param iEffSeg The effective segment register to use with @a u64Val.
7975 * Pass UINT8_MAX if it is a register access.
7976 * @param enmEffAddrMode The effective addressing mode (only used with memory
7977 * operand).
7978 * @param u64Val The value to write (or guest linear address to the
7979 * value), @a iEffSeg will indicate if it's a memory
7980 * operand.
7981 * @param u64FieldEnc The VMCS field encoding.
7982 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
7983 * be NULL.
7984 */
7985IEM_STATIC VBOXSTRICTRC iemVmxVmwrite(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, IEMMODE enmEffAddrMode, uint64_t u64Val,
7986 uint64_t u64FieldEnc, PCVMXVEXITINFO pExitInfo)
7987{
7988 /* Nested-guest intercept. */
7989 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7990 && iemVmxIsVmreadVmwriteInterceptSet(pVCpu, VMX_EXIT_VMWRITE, u64FieldEnc))
7991 {
7992 if (pExitInfo)
7993 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
7994 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMWRITE, VMXINSTRID_VMWRITE, cbInstr);
7995 }
7996
7997 /* CPL. */
7998 if (pVCpu->iem.s.uCpl == 0)
7999 { /* likely */ }
8000 else
8001 {
8002 Log(("vmwrite: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8003 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_Cpl;
8004 return iemRaiseGeneralProtectionFault0(pVCpu);
8005 }
8006
8007 /* VMCS pointer in root mode. */
8008 if ( !IEM_VMX_IS_ROOT_MODE(pVCpu)
8009 || IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8010 { /* likely */ }
8011 else
8012 {
8013 Log(("vmwrite: VMCS pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_CURRENT_VMCS(pVCpu)));
8014 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrInvalid;
8015 iemVmxVmFailInvalid(pVCpu);
8016 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8017 return VINF_SUCCESS;
8018 }
8019
8020 /* VMCS-link pointer in non-root mode. */
8021 if ( !IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8022 || IEM_VMX_HAS_SHADOW_VMCS(pVCpu))
8023 { /* likely */ }
8024 else
8025 {
8026 Log(("vmwrite: VMCS-link pointer %#RGp invalid -> VMFailInvalid\n", IEM_VMX_GET_SHADOW_VMCS(pVCpu)));
8027 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_LinkPtrInvalid;
8028 iemVmxVmFailInvalid(pVCpu);
8029 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8030 return VINF_SUCCESS;
8031 }
8032
8033 /* If the VMWRITE instruction references memory, access the specified memory operand. */
8034 bool const fIsRegOperand = iEffSeg == UINT8_MAX;
8035 if (!fIsRegOperand)
8036 {
8037 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
8038 Assert(enmEffAddrMode < RT_ELEMENTS(s_auAddrSizeMasks));
8039 RTGCPTR const GCPtrVal = u64Val & s_auAddrSizeMasks[enmEffAddrMode];
8040
8041 /* Read the value from the specified guest memory location. */
8042 VBOXSTRICTRC rcStrict;
8043 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8044 rcStrict = iemMemFetchDataU64(pVCpu, &u64Val, iEffSeg, GCPtrVal);
8045 else
8046 {
8047 uint32_t u32Val;
8048 rcStrict = iemMemFetchDataU32(pVCpu, &u32Val, iEffSeg, GCPtrVal);
8049 u64Val = u32Val;
8050 }
8051 if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
8052 {
8053 Log(("vmwrite: Failed to read value from memory operand at %#RGv, rc=%Rrc\n", GCPtrVal, VBOXSTRICTRC_VAL(rcStrict)));
8054 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_PtrMap;
8055 return rcStrict;
8056 }
8057 }
8058 else
8059 Assert(!pExitInfo || pExitInfo->InstrInfo.VmreadVmwrite.fIsRegOperand);
8060
8061 /* Supported VMCS field. */
8062 if (iemVmxIsVmcsFieldValid(pVCpu, u64FieldEnc))
8063 { /* likely */ }
8064 else
8065 {
8066 Log(("vmwrite: VMCS field %#RX64 invalid -> VMFail\n", u64FieldEnc));
8067 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldInvalid;
8068 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_INVALID_COMPONENT);
8069 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8070 return VINF_SUCCESS;
8071 }
8072
8073 /* Read-only VMCS field. */
8074 bool const fIsFieldReadOnly = HMVmxIsVmcsFieldReadOnly(u64FieldEnc);
8075 if ( !fIsFieldReadOnly
8076 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmwriteAll)
8077 { /* likely */ }
8078 else
8079 {
8080 Log(("vmwrite: Write to read-only VMCS component %#RX64 -> VMFail\n", u64FieldEnc));
8081 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmwrite_FieldRo;
8082 iemVmxVmFail(pVCpu, VMXINSTRERR_VMWRITE_RO_COMPONENT);
8083 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8084 return VINF_SUCCESS;
8085 }
8086
8087 /*
8088 * Setup writing to the current or shadow VMCS.
8089 */
8090 uint8_t *pbVmcs;
8091 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8092 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
8093 else
8094 pbVmcs = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pShadowVmcs);
8095 Assert(pbVmcs);
8096
8097 VMXVMCSFIELDENC FieldEnc;
8098 FieldEnc.u = u64FieldEnc;
8099 uint8_t const uWidth = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_WIDTH);
8100 uint8_t const uType = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_TYPE);
8101 uint8_t const uWidthType = (uWidth << 2) | uType;
8102 uint8_t const uIndex = RT_BF_GET(FieldEnc.u, VMX_BF_VMCS_ENC_INDEX);
8103 AssertReturn(uIndex <= VMX_V_VMCS_MAX_INDEX, VERR_IEM_IPE_2);
8104 uint16_t const offField = g_aoffVmcsMap[uWidthType][uIndex];
8105 Assert(offField < VMX_V_VMCS_SIZE);
8106
8107 /*
8108 * Write the VMCS component based on the field's effective width.
8109 *
8110 * The effective width is 64-bit fields adjusted to 32-bits if the access-type
8111 * indicates high bits (little endian).
8112 */
8113 uint8_t *pbField = pbVmcs + offField;
8114 uint8_t const uEffWidth = HMVmxGetVmcsFieldWidthEff(FieldEnc.u);
8115 switch (uEffWidth)
8116 {
8117 case VMX_VMCS_ENC_WIDTH_64BIT:
8118 case VMX_VMCS_ENC_WIDTH_NATURAL: *(uint64_t *)pbField = u64Val; break;
8119 case VMX_VMCS_ENC_WIDTH_32BIT: *(uint32_t *)pbField = u64Val; break;
8120 case VMX_VMCS_ENC_WIDTH_16BIT: *(uint16_t *)pbField = u64Val; break;
8121 }
8122
8123 iemVmxVmSucceed(pVCpu);
8124 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8125 return VINF_SUCCESS;
8126}
8127
8128
8129/**
8130 * VMCLEAR instruction execution worker.
8131 *
8132 * @returns Strict VBox status code.
8133 * @param pVCpu The cross context virtual CPU structure.
8134 * @param cbInstr The instruction length in bytes.
8135 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8136 * @param GCPtrVmcs The linear address of the VMCS pointer.
8137 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8138 * be NULL.
8139 *
8140 * @remarks Common VMX instruction checks are already expected to by the caller,
8141 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8142 */
8143IEM_STATIC VBOXSTRICTRC iemVmxVmclear(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8144 PCVMXVEXITINFO pExitInfo)
8145{
8146 /* Nested-guest intercept. */
8147 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8148 {
8149 if (pExitInfo)
8150 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8151 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMCLEAR, VMXINSTRID_NONE, cbInstr);
8152 }
8153
8154 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8155
8156 /* CPL. */
8157 if (pVCpu->iem.s.uCpl == 0)
8158 { /* likely */ }
8159 else
8160 {
8161 Log(("vmclear: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8162 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_Cpl;
8163 return iemRaiseGeneralProtectionFault0(pVCpu);
8164 }
8165
8166 /* Get the VMCS pointer from the location specified by the source memory operand. */
8167 RTGCPHYS GCPhysVmcs;
8168 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8169 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8170 { /* likely */ }
8171 else
8172 {
8173 Log(("vmclear: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8174 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrMap;
8175 return rcStrict;
8176 }
8177
8178 /* VMCS pointer alignment. */
8179 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8180 { /* likely */ }
8181 else
8182 {
8183 Log(("vmclear: VMCS pointer not page-aligned -> VMFail()\n"));
8184 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAlign;
8185 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8186 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8187 return VINF_SUCCESS;
8188 }
8189
8190 /* VMCS physical-address width limits. */
8191 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8192 { /* likely */ }
8193 else
8194 {
8195 Log(("vmclear: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8196 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrWidth;
8197 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8198 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8199 return VINF_SUCCESS;
8200 }
8201
8202 /* VMCS is not the VMXON region. */
8203 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8204 { /* likely */ }
8205 else
8206 {
8207 Log(("vmclear: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8208 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrVmxon;
8209 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_VMXON_PTR);
8210 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8211 return VINF_SUCCESS;
8212 }
8213
8214 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8215 restriction imposed by our implementation. */
8216 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8217 { /* likely */ }
8218 else
8219 {
8220 Log(("vmclear: VMCS not normal memory -> VMFail()\n"));
8221 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmclear_PtrAbnormal;
8222 iemVmxVmFail(pVCpu, VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR);
8223 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8224 return VINF_SUCCESS;
8225 }
8226
8227 /*
8228 * VMCLEAR allows committing and clearing any valid VMCS pointer.
8229 *
8230 * If the current VMCS is the one being cleared, set its state to 'clear' and commit
8231 * to guest memory. Otherwise, set the state of the VMCS referenced in guest memory
8232 * to 'clear'.
8233 */
8234 uint8_t const fVmcsStateClear = VMX_V_VMCS_STATE_CLEAR;
8235 if ( IEM_VMX_HAS_CURRENT_VMCS(pVCpu)
8236 && IEM_VMX_GET_CURRENT_VMCS(pVCpu) == GCPhysVmcs)
8237 {
8238 Assert(GCPhysVmcs != NIL_RTGCPHYS); /* Paranoia. */
8239 Assert(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs));
8240 pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs)->fVmcsState = fVmcsStateClear;
8241 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8242 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8243 }
8244 else
8245 {
8246 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(fVmcsStateClear));
8247 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcs + RT_UOFFSETOF(VMXVVMCS, fVmcsState),
8248 (const void *)&fVmcsStateClear, sizeof(fVmcsStateClear));
8249 if (RT_FAILURE(rcStrict))
8250 return rcStrict;
8251 }
8252
8253 iemVmxVmSucceed(pVCpu);
8254 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8255 return VINF_SUCCESS;
8256}
8257
8258
8259/**
8260 * VMPTRST instruction execution worker.
8261 *
8262 * @returns Strict VBox status code.
8263 * @param pVCpu The cross context virtual CPU structure.
8264 * @param cbInstr The instruction length in bytes.
8265 * @param iEffSeg The effective segment register to use with @a GCPtrVmcs.
8266 * @param GCPtrVmcs The linear address of where to store the current VMCS
8267 * pointer.
8268 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8269 * be NULL.
8270 *
8271 * @remarks Common VMX instruction checks are already expected to by the caller,
8272 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8273 */
8274IEM_STATIC VBOXSTRICTRC iemVmxVmptrst(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8275 PCVMXVEXITINFO pExitInfo)
8276{
8277 /* Nested-guest intercept. */
8278 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8279 {
8280 if (pExitInfo)
8281 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8282 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRST, VMXINSTRID_NONE, cbInstr);
8283 }
8284
8285 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8286
8287 /* CPL. */
8288 if (pVCpu->iem.s.uCpl == 0)
8289 { /* likely */ }
8290 else
8291 {
8292 Log(("vmptrst: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8293 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_Cpl;
8294 return iemRaiseGeneralProtectionFault0(pVCpu);
8295 }
8296
8297 /* Set the VMCS pointer to the location specified by the destination memory operand. */
8298 AssertCompile(NIL_RTGCPHYS == ~(RTGCPHYS)0U);
8299 VBOXSTRICTRC rcStrict = iemMemStoreDataU64(pVCpu, iEffSeg, GCPtrVmcs, IEM_VMX_GET_CURRENT_VMCS(pVCpu));
8300 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8301 {
8302 iemVmxVmSucceed(pVCpu);
8303 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8304 return rcStrict;
8305 }
8306
8307 Log(("vmptrst: Failed to store VMCS pointer to memory at destination operand %#Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8308 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrst_PtrMap;
8309 return rcStrict;
8310}
8311
8312
8313/**
8314 * VMPTRLD instruction execution worker.
8315 *
8316 * @returns Strict VBox status code.
8317 * @param pVCpu The cross context virtual CPU structure.
8318 * @param cbInstr The instruction length in bytes.
8319 * @param GCPtrVmcs The linear address of the current VMCS pointer.
8320 * @param pExitInfo Pointer to the VM-exit information struct. Optional, can
8321 * be NULL.
8322 *
8323 * @remarks Common VMX instruction checks are already expected to by the caller,
8324 * i.e. VMX operation, CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8325 */
8326IEM_STATIC VBOXSTRICTRC iemVmxVmptrld(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmcs,
8327 PCVMXVEXITINFO pExitInfo)
8328{
8329 /* Nested-guest intercept. */
8330 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8331 {
8332 if (pExitInfo)
8333 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8334 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMPTRLD, VMXINSTRID_NONE, cbInstr);
8335 }
8336
8337 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8338
8339 /* CPL. */
8340 if (pVCpu->iem.s.uCpl == 0)
8341 { /* likely */ }
8342 else
8343 {
8344 Log(("vmptrld: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8345 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_Cpl;
8346 return iemRaiseGeneralProtectionFault0(pVCpu);
8347 }
8348
8349 /* Get the VMCS pointer from the location specified by the source memory operand. */
8350 RTGCPHYS GCPhysVmcs;
8351 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmcs, iEffSeg, GCPtrVmcs);
8352 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8353 { /* likely */ }
8354 else
8355 {
8356 Log(("vmptrld: Failed to read VMCS physaddr from %#RGv, rc=%Rrc\n", GCPtrVmcs, VBOXSTRICTRC_VAL(rcStrict)));
8357 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrMap;
8358 return rcStrict;
8359 }
8360
8361 /* VMCS pointer alignment. */
8362 if (!(GCPhysVmcs & X86_PAGE_4K_OFFSET_MASK))
8363 { /* likely */ }
8364 else
8365 {
8366 Log(("vmptrld: VMCS pointer not page-aligned -> VMFail()\n"));
8367 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAlign;
8368 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8369 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8370 return VINF_SUCCESS;
8371 }
8372
8373 /* VMCS physical-address width limits. */
8374 if (!(GCPhysVmcs >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8375 { /* likely */ }
8376 else
8377 {
8378 Log(("vmptrld: VMCS pointer extends beyond physical-address width -> VMFail()\n"));
8379 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrWidth;
8380 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8381 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8382 return VINF_SUCCESS;
8383 }
8384
8385 /* VMCS is not the VMXON region. */
8386 if (GCPhysVmcs != pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
8387 { /* likely */ }
8388 else
8389 {
8390 Log(("vmptrld: VMCS pointer cannot be identical to VMXON region pointer -> VMFail()\n"));
8391 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrVmxon;
8392 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_VMXON_PTR);
8393 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8394 return VINF_SUCCESS;
8395 }
8396
8397 /* Ensure VMCS is not MMIO, ROM etc. This is not an Intel requirement but a
8398 restriction imposed by our implementation. */
8399 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcs))
8400 { /* likely */ }
8401 else
8402 {
8403 Log(("vmptrld: VMCS not normal memory -> VMFail()\n"));
8404 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrAbnormal;
8405 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR);
8406 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8407 return VINF_SUCCESS;
8408 }
8409
8410 /* Read just the VMCS revision from the VMCS. */
8411 VMXVMCSREVID VmcsRevId;
8412 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmcs, sizeof(VmcsRevId));
8413 if (RT_SUCCESS(rc))
8414 { /* likely */ }
8415 else
8416 {
8417 Log(("vmptrld: Failed to read revision identifier from VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8418 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_RevPtrReadPhys;
8419 return rc;
8420 }
8421
8422 /*
8423 * Verify the VMCS revision specified by the guest matches what we reported to the guest.
8424 * Verify the VMCS is not a shadow VMCS, if the VMCS shadowing feature is supported.
8425 */
8426 if ( VmcsRevId.n.u31RevisionId == VMX_V_VMCS_REVISION_ID
8427 && ( !VmcsRevId.n.fIsShadowVmcs
8428 || IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmxVmcsShadowing))
8429 { /* likely */ }
8430 else
8431 {
8432 if (VmcsRevId.n.u31RevisionId != VMX_V_VMCS_REVISION_ID)
8433 {
8434 Log(("vmptrld: VMCS revision mismatch, expected %#RX32 got %#RX32, GCPtrVmcs=%#RGv GCPhysVmcs=%#RGp -> VMFail()\n",
8435 VMX_V_VMCS_REVISION_ID, VmcsRevId.n.u31RevisionId, GCPtrVmcs, GCPhysVmcs));
8436 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_VmcsRevId;
8437 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8438 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8439 return VINF_SUCCESS;
8440 }
8441
8442 Log(("vmptrld: Shadow VMCS -> VMFail()\n"));
8443 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_ShadowVmcs;
8444 iemVmxVmFail(pVCpu, VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV);
8445 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8446 return VINF_SUCCESS;
8447 }
8448
8449 /*
8450 * We cache only the current VMCS in CPUMCTX. Therefore, VMPTRLD should always flush
8451 * the cache of an existing, current VMCS back to guest memory before loading a new,
8452 * different current VMCS.
8453 */
8454 bool fLoadVmcsFromMem;
8455 if (IEM_VMX_HAS_CURRENT_VMCS(pVCpu))
8456 {
8457 if (IEM_VMX_GET_CURRENT_VMCS(pVCpu) != GCPhysVmcs)
8458 {
8459 iemVmxCommitCurrentVmcsToMemory(pVCpu);
8460 Assert(!IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8461 fLoadVmcsFromMem = true;
8462 }
8463 else
8464 fLoadVmcsFromMem = false;
8465 }
8466 else
8467 fLoadVmcsFromMem = true;
8468
8469 if (fLoadVmcsFromMem)
8470 {
8471 /* Finally, cache the new VMCS from guest memory and mark it as the current VMCS. */
8472 rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), (void *)pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs), GCPhysVmcs,
8473 sizeof(VMXVVMCS));
8474 if (RT_SUCCESS(rc))
8475 { /* likely */ }
8476 else
8477 {
8478 Log(("vmptrld: Failed to read VMCS at %#RGp, rc=%Rrc\n", GCPhysVmcs, rc));
8479 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmptrld_PtrReadPhys;
8480 return rc;
8481 }
8482 IEM_VMX_SET_CURRENT_VMCS(pVCpu, GCPhysVmcs);
8483 }
8484
8485 Assert(IEM_VMX_HAS_CURRENT_VMCS(pVCpu));
8486 iemVmxVmSucceed(pVCpu);
8487 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8488 return VINF_SUCCESS;
8489}
8490
8491
8492/**
8493 * VMXON instruction execution worker.
8494 *
8495 * @returns Strict VBox status code.
8496 * @param pVCpu The cross context virtual CPU structure.
8497 * @param cbInstr The instruction length in bytes.
8498 * @param iEffSeg The effective segment register to use with @a
8499 * GCPtrVmxon.
8500 * @param GCPtrVmxon The linear address of the VMXON pointer.
8501 * @param pExitInfo Pointer to the VM-exit instruction information struct.
8502 * Optional, can be NULL.
8503 *
8504 * @remarks Common VMX instruction checks are already expected to by the caller,
8505 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8506 */
8507IEM_STATIC VBOXSTRICTRC iemVmxVmxon(PVMCPU pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPHYS GCPtrVmxon,
8508 PCVMXVEXITINFO pExitInfo)
8509{
8510 if (!IEM_VMX_IS_ROOT_MODE(pVCpu))
8511 {
8512 /* CPL. */
8513 if (pVCpu->iem.s.uCpl == 0)
8514 { /* likely */ }
8515 else
8516 {
8517 Log(("vmxon: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8518 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cpl;
8519 return iemRaiseGeneralProtectionFault0(pVCpu);
8520 }
8521
8522 /* A20M (A20 Masked) mode. */
8523 if (PGMPhysIsA20Enabled(pVCpu))
8524 { /* likely */ }
8525 else
8526 {
8527 Log(("vmxon: A20M mode -> #GP(0)\n"));
8528 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_A20M;
8529 return iemRaiseGeneralProtectionFault0(pVCpu);
8530 }
8531
8532 /* CR0. */
8533 {
8534 /* CR0 MB1 bits. */
8535 uint64_t const uCr0Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed0;
8536 if ((pVCpu->cpum.GstCtx.cr0 & uCr0Fixed0) == uCr0Fixed0)
8537 { /* likely */ }
8538 else
8539 {
8540 Log(("vmxon: CR0 fixed0 bits cleared -> #GP(0)\n"));
8541 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed0;
8542 return iemRaiseGeneralProtectionFault0(pVCpu);
8543 }
8544
8545 /* CR0 MBZ bits. */
8546 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
8547 if (!(pVCpu->cpum.GstCtx.cr0 & ~uCr0Fixed1))
8548 { /* likely */ }
8549 else
8550 {
8551 Log(("vmxon: CR0 fixed1 bits set -> #GP(0)\n"));
8552 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr0Fixed1;
8553 return iemRaiseGeneralProtectionFault0(pVCpu);
8554 }
8555 }
8556
8557 /* CR4. */
8558 {
8559 /* CR4 MB1 bits. */
8560 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
8561 if ((pVCpu->cpum.GstCtx.cr4 & uCr4Fixed0) == uCr4Fixed0)
8562 { /* likely */ }
8563 else
8564 {
8565 Log(("vmxon: CR4 fixed0 bits cleared -> #GP(0)\n"));
8566 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed0;
8567 return iemRaiseGeneralProtectionFault0(pVCpu);
8568 }
8569
8570 /* CR4 MBZ bits. */
8571 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
8572 if (!(pVCpu->cpum.GstCtx.cr4 & ~uCr4Fixed1))
8573 { /* likely */ }
8574 else
8575 {
8576 Log(("vmxon: CR4 fixed1 bits set -> #GP(0)\n"));
8577 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_Cr4Fixed1;
8578 return iemRaiseGeneralProtectionFault0(pVCpu);
8579 }
8580 }
8581
8582 /* Feature control MSR's LOCK and VMXON bits. */
8583 uint64_t const uMsrFeatCtl = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64FeatCtrl;
8584 if ((uMsrFeatCtl & (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8585 == (MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON))
8586 { /* likely */ }
8587 else
8588 {
8589 Log(("vmxon: Feature control lock bit or VMXON bit cleared -> #GP(0)\n"));
8590 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_MsrFeatCtl;
8591 return iemRaiseGeneralProtectionFault0(pVCpu);
8592 }
8593
8594 /* Get the VMXON pointer from the location specified by the source memory operand. */
8595 RTGCPHYS GCPhysVmxon;
8596 VBOXSTRICTRC rcStrict = iemMemFetchDataU64(pVCpu, &GCPhysVmxon, iEffSeg, GCPtrVmxon);
8597 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8598 { /* likely */ }
8599 else
8600 {
8601 Log(("vmxon: Failed to read VMXON region physaddr from %#RGv, rc=%Rrc\n", GCPtrVmxon, VBOXSTRICTRC_VAL(rcStrict)));
8602 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrMap;
8603 return rcStrict;
8604 }
8605
8606 /* VMXON region pointer alignment. */
8607 if (!(GCPhysVmxon & X86_PAGE_4K_OFFSET_MASK))
8608 { /* likely */ }
8609 else
8610 {
8611 Log(("vmxon: VMXON region pointer not page-aligned -> VMFailInvalid\n"));
8612 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAlign;
8613 iemVmxVmFailInvalid(pVCpu);
8614 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8615 return VINF_SUCCESS;
8616 }
8617
8618 /* VMXON physical-address width limits. */
8619 if (!(GCPhysVmxon >> IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cVmxMaxPhysAddrWidth))
8620 { /* likely */ }
8621 else
8622 {
8623 Log(("vmxon: VMXON region pointer extends beyond physical-address width -> VMFailInvalid\n"));
8624 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrWidth;
8625 iemVmxVmFailInvalid(pVCpu);
8626 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8627 return VINF_SUCCESS;
8628 }
8629
8630 /* Ensure VMXON region is not MMIO, ROM etc. This is not an Intel requirement but a
8631 restriction imposed by our implementation. */
8632 if (PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmxon))
8633 { /* likely */ }
8634 else
8635 {
8636 Log(("vmxon: VMXON region not normal memory -> VMFailInvalid\n"));
8637 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrAbnormal;
8638 iemVmxVmFailInvalid(pVCpu);
8639 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8640 return VINF_SUCCESS;
8641 }
8642
8643 /* Read the VMCS revision ID from the VMXON region. */
8644 VMXVMCSREVID VmcsRevId;
8645 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcsRevId, GCPhysVmxon, sizeof(VmcsRevId));
8646 if (RT_SUCCESS(rc))
8647 { /* likely */ }
8648 else
8649 {
8650 Log(("vmxon: Failed to read VMXON region at %#RGp, rc=%Rrc\n", GCPhysVmxon, rc));
8651 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_PtrReadPhys;
8652 return rc;
8653 }
8654
8655 /* Verify the VMCS revision specified by the guest matches what we reported to the guest. */
8656 if (RT_LIKELY(VmcsRevId.u == VMX_V_VMCS_REVISION_ID))
8657 { /* likely */ }
8658 else
8659 {
8660 /* Revision ID mismatch. */
8661 if (!VmcsRevId.n.fIsShadowVmcs)
8662 {
8663 Log(("vmxon: VMCS revision mismatch, expected %#RX32 got %#RX32 -> VMFailInvalid\n", VMX_V_VMCS_REVISION_ID,
8664 VmcsRevId.n.u31RevisionId));
8665 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmcsRevId;
8666 iemVmxVmFailInvalid(pVCpu);
8667 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8668 return VINF_SUCCESS;
8669 }
8670
8671 /* Shadow VMCS disallowed. */
8672 Log(("vmxon: Shadow VMCS -> VMFailInvalid\n"));
8673 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_ShadowVmcs;
8674 iemVmxVmFailInvalid(pVCpu);
8675 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8676 return VINF_SUCCESS;
8677 }
8678
8679 /*
8680 * Record that we're in VMX operation, block INIT, block and disable A20M.
8681 */
8682 pVCpu->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon = GCPhysVmxon;
8683 IEM_VMX_CLEAR_CURRENT_VMCS(pVCpu);
8684 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = true;
8685
8686 /* Clear address-range monitoring. */
8687 EMMonitorWaitClear(pVCpu);
8688 /** @todo NSTVMX: Intel PT. */
8689
8690 iemVmxVmSucceed(pVCpu);
8691 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8692 return VINF_SUCCESS;
8693 }
8694 else if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8695 {
8696 /* Nested-guest intercept. */
8697 if (pExitInfo)
8698 return iemVmxVmexitInstrWithInfo(pVCpu, pExitInfo);
8699 return iemVmxVmexitInstrNeedsInfo(pVCpu, VMX_EXIT_VMXON, VMXINSTRID_NONE, cbInstr);
8700 }
8701
8702 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
8703
8704 /* CPL. */
8705 if (pVCpu->iem.s.uCpl > 0)
8706 {
8707 Log(("vmxon: In VMX root mode: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8708 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxRootCpl;
8709 return iemRaiseGeneralProtectionFault0(pVCpu);
8710 }
8711
8712 /* VMXON when already in VMX root mode. */
8713 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXON_IN_VMXROOTMODE);
8714 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxon_VmxAlreadyRoot;
8715 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8716 return VINF_SUCCESS;
8717}
8718
8719
8720/**
8721 * Implements 'VMXOFF'.
8722 *
8723 * @remarks Common VMX instruction checks are already expected to by the caller,
8724 * i.e. CR4.VMXE, Real/V86 mode, EFER/CS.L checks.
8725 */
8726IEM_CIMPL_DEF_0(iemCImpl_vmxoff)
8727{
8728 /* Nested-guest intercept. */
8729 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8730 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMXOFF, cbInstr);
8731
8732 /* CPL. */
8733 if (pVCpu->iem.s.uCpl == 0)
8734 { /* likely */ }
8735 else
8736 {
8737 Log(("vmxoff: CPL %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
8738 pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = kVmxVDiag_Vmxoff_Cpl;
8739 return iemRaiseGeneralProtectionFault0(pVCpu);
8740 }
8741
8742 /* Dual monitor treatment of SMIs and SMM. */
8743 uint64_t const fSmmMonitorCtl = CPUMGetGuestIa32SmmMonitorCtl(pVCpu);
8744 if (!(fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VALID))
8745 { /* likely */ }
8746 else
8747 {
8748 iemVmxVmFail(pVCpu, VMXINSTRERR_VMXOFF_DUAL_MON);
8749 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8750 return VINF_SUCCESS;
8751 }
8752
8753 /* Record that we're no longer in VMX root operation, block INIT, block and disable A20M. */
8754 pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxRootMode = false;
8755 Assert(!pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode);
8756
8757 if (fSmmMonitorCtl & MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI)
8758 { /** @todo NSTVMX: Unblock SMI. */ }
8759
8760 EMMonitorWaitClear(pVCpu);
8761 /** @todo NSTVMX: Unblock and enable A20M. */
8762
8763 iemVmxVmSucceed(pVCpu);
8764 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8765 return VINF_SUCCESS;
8766}
8767
8768
8769/**
8770 * Implements 'VMXON'.
8771 */
8772IEM_CIMPL_DEF_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon)
8773{
8774 return iemVmxVmxon(pVCpu, cbInstr, iEffSeg, GCPtrVmxon, NULL /* pExitInfo */);
8775}
8776
8777
8778/**
8779 * Implements 'VMLAUNCH'.
8780 */
8781IEM_CIMPL_DEF_0(iemCImpl_vmlaunch)
8782{
8783 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMLAUNCH);
8784}
8785
8786
8787/**
8788 * Implements 'VMRESUME'.
8789 */
8790IEM_CIMPL_DEF_0(iemCImpl_vmresume)
8791{
8792 return iemVmxVmlaunchVmresume(pVCpu, cbInstr, VMXINSTRID_VMRESUME);
8793}
8794
8795
8796/**
8797 * Implements 'VMPTRLD'.
8798 */
8799IEM_CIMPL_DEF_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8800{
8801 return iemVmxVmptrld(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8802}
8803
8804
8805/**
8806 * Implements 'VMPTRST'.
8807 */
8808IEM_CIMPL_DEF_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8809{
8810 return iemVmxVmptrst(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8811}
8812
8813
8814/**
8815 * Implements 'VMCLEAR'.
8816 */
8817IEM_CIMPL_DEF_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs)
8818{
8819 return iemVmxVmclear(pVCpu, cbInstr, iEffSeg, GCPtrVmcs, NULL /* pExitInfo */);
8820}
8821
8822
8823/**
8824 * Implements 'VMWRITE' register.
8825 */
8826IEM_CIMPL_DEF_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64FieldEnc)
8827{
8828 return iemVmxVmwrite(pVCpu, cbInstr, UINT8_MAX /* iEffSeg */, IEMMODE_64BIT /* N/A */, u64Val, u64FieldEnc,
8829 NULL /* pExitInfo */);
8830}
8831
8832
8833/**
8834 * Implements 'VMWRITE' memory.
8835 */
8836IEM_CIMPL_DEF_4(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrVal, uint32_t, u64FieldEnc)
8837{
8838 return iemVmxVmwrite(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrVal, u64FieldEnc, NULL /* pExitInfo */);
8839}
8840
8841
8842/**
8843 * Implements 'VMREAD' register (64-bit).
8844 */
8845IEM_CIMPL_DEF_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64FieldEnc)
8846{
8847 return iemVmxVmreadReg64(pVCpu, cbInstr, pu64Dst, u64FieldEnc, NULL /* pExitInfo */);
8848}
8849
8850
8851/**
8852 * Implements 'VMREAD' register (32-bit).
8853 */
8854IEM_CIMPL_DEF_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32FieldEnc)
8855{
8856 return iemVmxVmreadReg32(pVCpu, cbInstr, pu32Dst, u32FieldEnc, NULL /* pExitInfo */);
8857}
8858
8859
8860/**
8861 * Implements 'VMREAD' memory, 64-bit register.
8862 */
8863IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u64FieldEnc)
8864{
8865 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u64FieldEnc, NULL /* pExitInfo */);
8866}
8867
8868
8869/**
8870 * Implements 'VMREAD' memory, 32-bit register.
8871 */
8872IEM_CIMPL_DEF_4(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, IEMMODE, enmEffAddrMode, RTGCPTR, GCPtrDst, uint32_t, u32FieldEnc)
8873{
8874 return iemVmxVmreadMem(pVCpu, cbInstr, iEffSeg, enmEffAddrMode, GCPtrDst, u32FieldEnc, NULL /* pExitInfo */);
8875}
8876
8877
8878/**
8879 * Implements VMX's implementation of PAUSE.
8880 */
8881IEM_CIMPL_DEF_0(iemCImpl_vmx_pause)
8882{
8883 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8884 {
8885 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrPause(pVCpu, cbInstr);
8886 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
8887 return rcStrict;
8888 }
8889
8890 /*
8891 * Outside VMX non-root operation or if the PAUSE instruction does not cause
8892 * a VM-exit, the instruction operates normally.
8893 */
8894 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8895 return VINF_SUCCESS;
8896}
8897
8898#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
8899
8900
8901/**
8902 * Implements 'VMCALL'.
8903 */
8904IEM_CIMPL_DEF_0(iemCImpl_vmcall)
8905{
8906#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8907 /* Nested-guest intercept. */
8908 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8909 return iemVmxVmexitInstr(pVCpu, VMX_EXIT_VMCALL, cbInstr);
8910#endif
8911
8912 /* Join forces with vmmcall. */
8913 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMCALL);
8914}
8915
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