IEMAllInstructionsTwoByte0f.cpp.h@ 66334

Last change on this file since 66334 was 66334, checked in by vboxsync, 8 years ago
IEM: Fixed UD1 / grp 10 decoding (intel eats modr/m after it).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 321.8 KB

Line
1	/* $Id: IEMAllInstructionsTwoByte0f.cpp.h 66334 2017-03-29 14:26:23Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Decoding and Emulation.
4	*/
5
6	/*
7	* Copyright (C) 2011-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Global Variables *
21	*******************************************************************************/
22	extern const PFNIEMOP g_apfnOneByteMap[256]; /* not static since we need to forward declare it. */
23
24
25	/** @name ..... opcodes.
26	*
27	* @{
28	*/
29
30	/** @} */
31
32
33	/** @name Two byte opcodes (first byte 0x0f).
34	*
35	* @{
36	*/
37
38	/** Opcode 0x0f 0x00 /0. */
39	FNIEMOPRM_DEF(iemOp_Grp6_sldt)
40	{
41	IEMOP_MNEMONIC(sldt, "sldt Rv/Mw");
42	IEMOP_HLP_MIN_286();
43	IEMOP_HLP_NO_REAL_OR_V86_MODE();
44
45	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
46	{
47	IEMOP_HLP_DECODED_NL_1(OP_SLDT, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS \| DISOPTYPE_PRIVILEGED_NOTRAP);
48	switch (pVCpu->iem.s.enmEffOpSize)
49	{
50	case IEMMODE_16BIT:
51	IEM_MC_BEGIN(0, 1);
52	IEM_MC_LOCAL(uint16_t, u16Ldtr);
53	IEM_MC_FETCH_LDTR_U16(u16Ldtr);
54	IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, u16Ldtr);
55	IEM_MC_ADVANCE_RIP();
56	IEM_MC_END();
57	break;
58
59	case IEMMODE_32BIT:
60	IEM_MC_BEGIN(0, 1);
61	IEM_MC_LOCAL(uint32_t, u32Ldtr);
62	IEM_MC_FETCH_LDTR_U32(u32Ldtr);
63	IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, u32Ldtr);
64	IEM_MC_ADVANCE_RIP();
65	IEM_MC_END();
66	break;
67
68	case IEMMODE_64BIT:
69	IEM_MC_BEGIN(0, 1);
70	IEM_MC_LOCAL(uint64_t, u64Ldtr);
71	IEM_MC_FETCH_LDTR_U64(u64Ldtr);
72	IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, u64Ldtr);
73	IEM_MC_ADVANCE_RIP();
74	IEM_MC_END();
75	break;
76
77	IEM_NOT_REACHED_DEFAULT_CASE_RET();
78	}
79	}
80	else
81	{
82	IEM_MC_BEGIN(0, 2);
83	IEM_MC_LOCAL(uint16_t, u16Ldtr);
84	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
85	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
86	IEMOP_HLP_DECODED_NL_1(OP_SLDT, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS \| DISOPTYPE_PRIVILEGED_NOTRAP);
87	IEM_MC_FETCH_LDTR_U16(u16Ldtr);
88	IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Ldtr);
89	IEM_MC_ADVANCE_RIP();
90	IEM_MC_END();
91	}
92	return VINF_SUCCESS;
93	}
94
95
96	/** Opcode 0x0f 0x00 /1. */
97	FNIEMOPRM_DEF(iemOp_Grp6_str)
98	{
99	IEMOP_MNEMONIC(str, "str Rv/Mw");
100	IEMOP_HLP_MIN_286();
101	IEMOP_HLP_NO_REAL_OR_V86_MODE();
102
103	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
104	{
105	IEMOP_HLP_DECODED_NL_1(OP_STR, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS \| DISOPTYPE_PRIVILEGED_NOTRAP);
106	switch (pVCpu->iem.s.enmEffOpSize)
107	{
108	case IEMMODE_16BIT:
109	IEM_MC_BEGIN(0, 1);
110	IEM_MC_LOCAL(uint16_t, u16Tr);
111	IEM_MC_FETCH_TR_U16(u16Tr);
112	IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, u16Tr);
113	IEM_MC_ADVANCE_RIP();
114	IEM_MC_END();
115	break;
116
117	case IEMMODE_32BIT:
118	IEM_MC_BEGIN(0, 1);
119	IEM_MC_LOCAL(uint32_t, u32Tr);
120	IEM_MC_FETCH_TR_U32(u32Tr);
121	IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, u32Tr);
122	IEM_MC_ADVANCE_RIP();
123	IEM_MC_END();
124	break;
125
126	case IEMMODE_64BIT:
127	IEM_MC_BEGIN(0, 1);
128	IEM_MC_LOCAL(uint64_t, u64Tr);
129	IEM_MC_FETCH_TR_U64(u64Tr);
130	IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, u64Tr);
131	IEM_MC_ADVANCE_RIP();
132	IEM_MC_END();
133	break;
134
135	IEM_NOT_REACHED_DEFAULT_CASE_RET();
136	}
137	}
138	else
139	{
140	IEM_MC_BEGIN(0, 2);
141	IEM_MC_LOCAL(uint16_t, u16Tr);
142	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
143	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
144	IEMOP_HLP_DECODED_NL_1(OP_STR, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS \| DISOPTYPE_PRIVILEGED_NOTRAP);
145	IEM_MC_FETCH_TR_U16(u16Tr);
146	IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Tr);
147	IEM_MC_ADVANCE_RIP();
148	IEM_MC_END();
149	}
150	return VINF_SUCCESS;
151	}
152
153
154	/** Opcode 0x0f 0x00 /2. */
155	FNIEMOPRM_DEF(iemOp_Grp6_lldt)
156	{
157	IEMOP_MNEMONIC(lldt, "lldt Ew");
158	IEMOP_HLP_MIN_286();
159	IEMOP_HLP_NO_REAL_OR_V86_MODE();
160
161	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
162	{
163	IEMOP_HLP_DECODED_NL_1(OP_LLDT, IEMOPFORM_M_REG, OP_PARM_Ew, DISOPTYPE_DANGEROUS);
164	IEM_MC_BEGIN(1, 0);
165	IEM_MC_ARG(uint16_t, u16Sel, 0);
166	IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
167	IEM_MC_CALL_CIMPL_1(iemCImpl_lldt, u16Sel);
168	IEM_MC_END();
169	}
170	else
171	{
172	IEM_MC_BEGIN(1, 1);
173	IEM_MC_ARG(uint16_t, u16Sel, 0);
174	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
175	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
176	IEMOP_HLP_DECODED_NL_1(OP_LLDT, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS);
177	IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO(); /** @todo test order */
178	IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
179	IEM_MC_CALL_CIMPL_1(iemCImpl_lldt, u16Sel);
180	IEM_MC_END();
181	}
182	return VINF_SUCCESS;
183	}
184
185
186	/** Opcode 0x0f 0x00 /3. */
187	FNIEMOPRM_DEF(iemOp_Grp6_ltr)
188	{
189	IEMOP_MNEMONIC(ltr, "ltr Ew");
190	IEMOP_HLP_MIN_286();
191	IEMOP_HLP_NO_REAL_OR_V86_MODE();
192
193	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
194	{
195	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
196	IEM_MC_BEGIN(1, 0);
197	IEM_MC_ARG(uint16_t, u16Sel, 0);
198	IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
199	IEM_MC_CALL_CIMPL_1(iemCImpl_ltr, u16Sel);
200	IEM_MC_END();
201	}
202	else
203	{
204	IEM_MC_BEGIN(1, 1);
205	IEM_MC_ARG(uint16_t, u16Sel, 0);
206	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
207	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
208	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
209	IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO(); /** @todo test ordre */
210	IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
211	IEM_MC_CALL_CIMPL_1(iemCImpl_ltr, u16Sel);
212	IEM_MC_END();
213	}
214	return VINF_SUCCESS;
215	}
216
217
218	/** Opcode 0x0f 0x00 /3. */
219	FNIEMOP_DEF_2(iemOpCommonGrp6VerX, uint8_t, bRm, bool, fWrite)
220	{
221	IEMOP_HLP_MIN_286();
222	IEMOP_HLP_NO_REAL_OR_V86_MODE();
223
224	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
225	{
226	IEMOP_HLP_DECODED_NL_1(fWrite ? OP_VERW : OP_VERR, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS \| DISOPTYPE_PRIVILEGED_NOTRAP);
227	IEM_MC_BEGIN(2, 0);
228	IEM_MC_ARG(uint16_t, u16Sel, 0);
229	IEM_MC_ARG_CONST(bool, fWriteArg, fWrite, 1);
230	IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
231	IEM_MC_CALL_CIMPL_2(iemCImpl_VerX, u16Sel, fWriteArg);
232	IEM_MC_END();
233	}
234	else
235	{
236	IEM_MC_BEGIN(2, 1);
237	IEM_MC_ARG(uint16_t, u16Sel, 0);
238	IEM_MC_ARG_CONST(bool, fWriteArg, fWrite, 1);
239	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
240	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
241	IEMOP_HLP_DECODED_NL_1(fWrite ? OP_VERW : OP_VERR, IEMOPFORM_M_MEM, OP_PARM_Ew, DISOPTYPE_DANGEROUS \| DISOPTYPE_PRIVILEGED_NOTRAP);
242	IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
243	IEM_MC_CALL_CIMPL_2(iemCImpl_VerX, u16Sel, fWriteArg);
244	IEM_MC_END();
245	}
246	return VINF_SUCCESS;
247	}
248
249
250	/** Opcode 0x0f 0x00 /4. */
251	FNIEMOPRM_DEF(iemOp_Grp6_verr)
252	{
253	IEMOP_MNEMONIC(verr, "verr Ew");
254	IEMOP_HLP_MIN_286();
255	return FNIEMOP_CALL_2(iemOpCommonGrp6VerX, bRm, false);
256	}
257
258
259	/** Opcode 0x0f 0x00 /5. */
260	FNIEMOPRM_DEF(iemOp_Grp6_verw)
261	{
262	IEMOP_MNEMONIC(verw, "verw Ew");
263	IEMOP_HLP_MIN_286();
264	return FNIEMOP_CALL_2(iemOpCommonGrp6VerX, bRm, true);
265	}
266
267
268	/**
269	* Group 6 jump table.
270	*/
271	IEM_STATIC const PFNIEMOPRM g_apfnGroup6[8] =
272	{
273	iemOp_Grp6_sldt,
274	iemOp_Grp6_str,
275	iemOp_Grp6_lldt,
276	iemOp_Grp6_ltr,
277	iemOp_Grp6_verr,
278	iemOp_Grp6_verw,
279	iemOp_InvalidWithRM,
280	iemOp_InvalidWithRM
281	};
282
283	/** Opcode 0x0f 0x00. */
284	FNIEMOP_DEF(iemOp_Grp6)
285	{
286	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
287	return FNIEMOP_CALL_1(g_apfnGroup6[(bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK], bRm);
288	}
289
290
291	/** Opcode 0x0f 0x01 /0. */
292	FNIEMOP_DEF_1(iemOp_Grp7_sgdt, uint8_t, bRm)
293	{
294	IEMOP_MNEMONIC(sgdt, "sgdt Ms");
295	IEMOP_HLP_MIN_286();
296	IEMOP_HLP_64BIT_OP_SIZE();
297	IEM_MC_BEGIN(2, 1);
298	IEM_MC_ARG(uint8_t, iEffSeg, 0);
299	IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
300	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
301	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
302	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
303	IEM_MC_CALL_CIMPL_2(iemCImpl_sgdt, iEffSeg, GCPtrEffSrc);
304	IEM_MC_END();
305	return VINF_SUCCESS;
306	}
307
308
309	/** Opcode 0x0f 0x01 /0. */
310	FNIEMOP_DEF(iemOp_Grp7_vmcall)
311	{
312	IEMOP_BITCH_ABOUT_STUB();
313	return IEMOP_RAISE_INVALID_OPCODE();
314	}
315
316
317	/** Opcode 0x0f 0x01 /0. */
318	FNIEMOP_DEF(iemOp_Grp7_vmlaunch)
319	{
320	IEMOP_BITCH_ABOUT_STUB();
321	return IEMOP_RAISE_INVALID_OPCODE();
322	}
323
324
325	/** Opcode 0x0f 0x01 /0. */
326	FNIEMOP_DEF(iemOp_Grp7_vmresume)
327	{
328	IEMOP_BITCH_ABOUT_STUB();
329	return IEMOP_RAISE_INVALID_OPCODE();
330	}
331
332
333	/** Opcode 0x0f 0x01 /0. */
334	FNIEMOP_DEF(iemOp_Grp7_vmxoff)
335	{
336	IEMOP_BITCH_ABOUT_STUB();
337	return IEMOP_RAISE_INVALID_OPCODE();
338	}
339
340
341	/** Opcode 0x0f 0x01 /1. */
342	FNIEMOP_DEF_1(iemOp_Grp7_sidt, uint8_t, bRm)
343	{
344	IEMOP_MNEMONIC(sidt, "sidt Ms");
345	IEMOP_HLP_MIN_286();
346	IEMOP_HLP_64BIT_OP_SIZE();
347	IEM_MC_BEGIN(2, 1);
348	IEM_MC_ARG(uint8_t, iEffSeg, 0);
349	IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
350	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
351	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
352	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
353	IEM_MC_CALL_CIMPL_2(iemCImpl_sidt, iEffSeg, GCPtrEffSrc);
354	IEM_MC_END();
355	return VINF_SUCCESS;
356	}
357
358
359	/** Opcode 0x0f 0x01 /1. */
360	FNIEMOP_DEF(iemOp_Grp7_monitor)
361	{
362	IEMOP_MNEMONIC(monitor, "monitor");
363	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); /** @todo Verify that monitor is allergic to lock prefixes. */
364	return IEM_MC_DEFER_TO_CIMPL_1(iemCImpl_monitor, pVCpu->iem.s.iEffSeg);
365	}
366
367
368	/** Opcode 0x0f 0x01 /1. */
369	FNIEMOP_DEF(iemOp_Grp7_mwait)
370	{
371	IEMOP_MNEMONIC(mwait, "mwait"); /** @todo Verify that mwait is allergic to lock prefixes. */
372	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
373	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_mwait);
374	}
375
376
377	/** Opcode 0x0f 0x01 /2. */
378	FNIEMOP_DEF_1(iemOp_Grp7_lgdt, uint8_t, bRm)
379	{
380	IEMOP_MNEMONIC(lgdt, "lgdt");
381	IEMOP_HLP_64BIT_OP_SIZE();
382	IEM_MC_BEGIN(3, 1);
383	IEM_MC_ARG(uint8_t, iEffSeg, 0);
384	IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
385	IEM_MC_ARG_CONST(IEMMODE, enmEffOpSizeArg,/=/pVCpu->iem.s.enmEffOpSize, 2);
386	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
387	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
388	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
389	IEM_MC_CALL_CIMPL_3(iemCImpl_lgdt, iEffSeg, GCPtrEffSrc, enmEffOpSizeArg);
390	IEM_MC_END();
391	return VINF_SUCCESS;
392	}
393
394
395	/** Opcode 0x0f 0x01 0xd0. */
396	FNIEMOP_DEF(iemOp_Grp7_xgetbv)
397	{
398	IEMOP_MNEMONIC(xgetbv, "xgetbv");
399	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor)
400	{
401	IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES();
402	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_xgetbv);
403	}
404	return IEMOP_RAISE_INVALID_OPCODE();
405	}
406
407
408	/** Opcode 0x0f 0x01 0xd1. */
409	FNIEMOP_DEF(iemOp_Grp7_xsetbv)
410	{
411	IEMOP_MNEMONIC(xsetbv, "xsetbv");
412	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor)
413	{
414	IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES();
415	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_xsetbv);
416	}
417	return IEMOP_RAISE_INVALID_OPCODE();
418	}
419
420
421	/** Opcode 0x0f 0x01 /3. */
422	FNIEMOP_DEF_1(iemOp_Grp7_lidt, uint8_t, bRm)
423	{
424	IEMOP_MNEMONIC(lidt, "lidt");
425	IEMMODE enmEffOpSize = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT
426	? IEMMODE_64BIT
427	: pVCpu->iem.s.enmEffOpSize;
428	IEM_MC_BEGIN(3, 1);
429	IEM_MC_ARG(uint8_t, iEffSeg, 0);
430	IEM_MC_ARG(RTGCPTR, GCPtrEffSrc, 1);
431	IEM_MC_ARG_CONST(IEMMODE, enmEffOpSizeArg,/=/enmEffOpSize, 2);
432	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
433	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
434	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
435	IEM_MC_CALL_CIMPL_3(iemCImpl_lidt, iEffSeg, GCPtrEffSrc, enmEffOpSizeArg);
436	IEM_MC_END();
437	return VINF_SUCCESS;
438	}
439
440
441	#ifdef VBOX_WITH_NESTED_HWVIRT
442	/** Opcode 0x0f 0x01 0xd8. */
443	FNIEMOP_DEF(iemOp_Grp7_Amd_vmrun)
444	{
445	IEMOP_MNEMONIC(vmrun, "vmrun");
446	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmrun);
447	}
448
449	/** Opcode 0x0f 0x01 0xd9. */
450	FNIEMOP_DEF(iemOp_Grp7_Amd_vmmcall)
451	{
452	IEMOP_MNEMONIC(vmmcall, "vmmcall");
453	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmmcall);
454	}
455
456
457	/** Opcode 0x0f 0x01 0xda. */
458	FNIEMOP_DEF(iemOp_Grp7_Amd_vmload)
459	{
460	IEMOP_MNEMONIC(vmload, "vmload");
461	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmload);
462	}
463
464
465	/** Opcode 0x0f 0x01 0xdb. */
466	FNIEMOP_DEF(iemOp_Grp7_Amd_vmsave)
467	{
468	IEMOP_MNEMONIC(vmsave, "vmsave");
469	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_vmsave);
470	}
471
472
473	/** Opcode 0x0f 0x01 0xdc. */
474	FNIEMOP_DEF(iemOp_Grp7_Amd_stgi)
475	{
476	IEMOP_MNEMONIC(stgi, "stgi");
477	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_stgi);
478	}
479
480
481	/** Opcode 0x0f 0x01 0xdd. */
482	FNIEMOP_DEF(iemOp_Grp7_Amd_clgi)
483	{
484	IEMOP_MNEMONIC(clgi, "clgi");
485	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_clgi);
486	}
487
488
489	/** Opcode 0x0f 0x01 0xdf. */
490	FNIEMOP_DEF(iemOp_Grp7_Amd_invlpga)
491	{
492	IEMOP_MNEMONIC(invlpga, "invlpga");
493	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_invlpga);
494	}
495	#else
496	/** Opcode 0x0f 0x01 0xd8. */
497	FNIEMOP_UD_STUB(iemOp_Grp7_Amd_vmrun);
498
499	/** Opcode 0x0f 0x01 0xd9. */
500	FNIEMOP_UD_STUB(iemOp_Grp7_Amd_vmmcall);
501
502	/** Opcode 0x0f 0x01 0xda. */
503	FNIEMOP_UD_STUB(iemOp_Grp7_Amd_vmload);
504
505	/** Opcode 0x0f 0x01 0xdb. */
506	FNIEMOP_UD_STUB(iemOp_Grp7_Amd_vmsave);
507
508	/** Opcode 0x0f 0x01 0xdc. */
509	FNIEMOP_UD_STUB(iemOp_Grp7_Amd_stgi);
510
511	/** Opcode 0x0f 0x01 0xdd. */
512	FNIEMOP_UD_STUB(iemOp_Grp7_Amd_clgi);
513
514	/** Opcode 0x0f 0x01 0xdf. */
515	FNIEMOP_UD_STUB(iemOp_Grp7_Amd_invlpga);
516	#endif /* VBOX_WITH_NESTED_HWVIRT */
517
518	/** Opcode 0x0f 0x01 0xde. */
519	FNIEMOP_UD_STUB(iemOp_Grp7_Amd_skinit);
520
521	/** Opcode 0x0f 0x01 /4. */
522	FNIEMOP_DEF_1(iemOp_Grp7_smsw, uint8_t, bRm)
523	{
524	IEMOP_MNEMONIC(smsw, "smsw");
525	IEMOP_HLP_MIN_286();
526	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
527	{
528	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
529	switch (pVCpu->iem.s.enmEffOpSize)
530	{
531	case IEMMODE_16BIT:
532	IEM_MC_BEGIN(0, 1);
533	IEM_MC_LOCAL(uint16_t, u16Tmp);
534	IEM_MC_FETCH_CR0_U16(u16Tmp);
535	if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
536	{ /* likely */ }
537	else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
538	IEM_MC_OR_LOCAL_U16(u16Tmp, 0xffe0);
539	else
540	IEM_MC_OR_LOCAL_U16(u16Tmp, 0xfff0);
541	IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, u16Tmp);
542	IEM_MC_ADVANCE_RIP();
543	IEM_MC_END();
544	return VINF_SUCCESS;
545
546	case IEMMODE_32BIT:
547	IEM_MC_BEGIN(0, 1);
548	IEM_MC_LOCAL(uint32_t, u32Tmp);
549	IEM_MC_FETCH_CR0_U32(u32Tmp);
550	IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, u32Tmp);
551	IEM_MC_ADVANCE_RIP();
552	IEM_MC_END();
553	return VINF_SUCCESS;
554
555	case IEMMODE_64BIT:
556	IEM_MC_BEGIN(0, 1);
557	IEM_MC_LOCAL(uint64_t, u64Tmp);
558	IEM_MC_FETCH_CR0_U64(u64Tmp);
559	IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, u64Tmp);
560	IEM_MC_ADVANCE_RIP();
561	IEM_MC_END();
562	return VINF_SUCCESS;
563
564	IEM_NOT_REACHED_DEFAULT_CASE_RET();
565	}
566	}
567	else
568	{
569	/* Ignore operand size here, memory refs are always 16-bit. */
570	IEM_MC_BEGIN(0, 2);
571	IEM_MC_LOCAL(uint16_t, u16Tmp);
572	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
573	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
574	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
575	IEM_MC_FETCH_CR0_U16(u16Tmp);
576	if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
577	{ /* likely */ }
578	else if (pVCpu->iem.s.uTargetCpu >= IEMTARGETCPU_386)
579	IEM_MC_OR_LOCAL_U16(u16Tmp, 0xffe0);
580	else
581	IEM_MC_OR_LOCAL_U16(u16Tmp, 0xfff0);
582	IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Tmp);
583	IEM_MC_ADVANCE_RIP();
584	IEM_MC_END();
585	return VINF_SUCCESS;
586	}
587	}
588
589
590	/** Opcode 0x0f 0x01 /6. */
591	FNIEMOP_DEF_1(iemOp_Grp7_lmsw, uint8_t, bRm)
592	{
593	/* The operand size is effectively ignored, all is 16-bit and only the
594	lower 3-bits are used. */
595	IEMOP_MNEMONIC(lmsw, "lmsw");
596	IEMOP_HLP_MIN_286();
597	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
598	{
599	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
600	IEM_MC_BEGIN(1, 0);
601	IEM_MC_ARG(uint16_t, u16Tmp, 0);
602	IEM_MC_FETCH_GREG_U16(u16Tmp, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
603	IEM_MC_CALL_CIMPL_1(iemCImpl_lmsw, u16Tmp);
604	IEM_MC_END();
605	}
606	else
607	{
608	IEM_MC_BEGIN(1, 1);
609	IEM_MC_ARG(uint16_t, u16Tmp, 0);
610	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
611	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
612	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
613	IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
614	IEM_MC_CALL_CIMPL_1(iemCImpl_lmsw, u16Tmp);
615	IEM_MC_END();
616	}
617	return VINF_SUCCESS;
618	}
619
620
621	/** Opcode 0x0f 0x01 /7. */
622	FNIEMOP_DEF_1(iemOp_Grp7_invlpg, uint8_t, bRm)
623	{
624	IEMOP_MNEMONIC(invlpg, "invlpg");
625	IEMOP_HLP_MIN_486();
626	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
627	IEM_MC_BEGIN(1, 1);
628	IEM_MC_ARG(RTGCPTR, GCPtrEffDst, 0);
629	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
630	IEM_MC_CALL_CIMPL_1(iemCImpl_invlpg, GCPtrEffDst);
631	IEM_MC_END();
632	return VINF_SUCCESS;
633	}
634
635
636	/** Opcode 0x0f 0x01 /7. */
637	FNIEMOP_DEF(iemOp_Grp7_swapgs)
638	{
639	IEMOP_MNEMONIC(swapgs, "swapgs");
640	IEMOP_HLP_ONLY_64BIT();
641	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
642	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_swapgs);
643	}
644
645
646	/** Opcode 0x0f 0x01 /7. */
647	FNIEMOP_DEF(iemOp_Grp7_rdtscp)
648	{
649	NOREF(pVCpu);
650	IEMOP_BITCH_ABOUT_STUB();
651	return VERR_IEM_INSTR_NOT_IMPLEMENTED;
652	}
653
654
655	/**
656	* Group 7 jump table, memory variant.
657	*/
658	IEM_STATIC const PFNIEMOPRM g_apfnGroup7Mem[8] =
659	{
660	iemOp_Grp7_sgdt,
661	iemOp_Grp7_sidt,
662	iemOp_Grp7_lgdt,
663	iemOp_Grp7_lidt,
664	iemOp_Grp7_smsw,
665	iemOp_InvalidWithRM,
666	iemOp_Grp7_lmsw,
667	iemOp_Grp7_invlpg
668	};
669
670
671	/** Opcode 0x0f 0x01. */
672	FNIEMOP_DEF(iemOp_Grp7)
673	{
674	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
675	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
676	return FNIEMOP_CALL_1(g_apfnGroup7Mem[(bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK], bRm);
677
678	switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
679	{
680	case 0:
681	switch (bRm & X86_MODRM_RM_MASK)
682	{
683	case 1: return FNIEMOP_CALL(iemOp_Grp7_vmcall);
684	case 2: return FNIEMOP_CALL(iemOp_Grp7_vmlaunch);
685	case 3: return FNIEMOP_CALL(iemOp_Grp7_vmresume);
686	case 4: return FNIEMOP_CALL(iemOp_Grp7_vmxoff);
687	}
688	return IEMOP_RAISE_INVALID_OPCODE();
689
690	case 1:
691	switch (bRm & X86_MODRM_RM_MASK)
692	{
693	case 0: return FNIEMOP_CALL(iemOp_Grp7_monitor);
694	case 1: return FNIEMOP_CALL(iemOp_Grp7_mwait);
695	}
696	return IEMOP_RAISE_INVALID_OPCODE();
697
698	case 2:
699	switch (bRm & X86_MODRM_RM_MASK)
700	{
701	case 0: return FNIEMOP_CALL(iemOp_Grp7_xgetbv);
702	case 1: return FNIEMOP_CALL(iemOp_Grp7_xsetbv);
703	}
704	return IEMOP_RAISE_INVALID_OPCODE();
705
706	case 3:
707	switch (bRm & X86_MODRM_RM_MASK)
708	{
709	case 0: return FNIEMOP_CALL(iemOp_Grp7_Amd_vmrun);
710	case 1: return FNIEMOP_CALL(iemOp_Grp7_Amd_vmmcall);
711	case 2: return FNIEMOP_CALL(iemOp_Grp7_Amd_vmload);
712	case 3: return FNIEMOP_CALL(iemOp_Grp7_Amd_vmsave);
713	case 4: return FNIEMOP_CALL(iemOp_Grp7_Amd_stgi);
714	case 5: return FNIEMOP_CALL(iemOp_Grp7_Amd_clgi);
715	case 6: return FNIEMOP_CALL(iemOp_Grp7_Amd_skinit);
716	case 7: return FNIEMOP_CALL(iemOp_Grp7_Amd_invlpga);
717	IEM_NOT_REACHED_DEFAULT_CASE_RET();
718	}
719
720	case 4:
721	return FNIEMOP_CALL_1(iemOp_Grp7_smsw, bRm);
722
723	case 5:
724	return IEMOP_RAISE_INVALID_OPCODE();
725
726	case 6:
727	return FNIEMOP_CALL_1(iemOp_Grp7_lmsw, bRm);
728
729	case 7:
730	switch (bRm & X86_MODRM_RM_MASK)
731	{
732	case 0: return FNIEMOP_CALL(iemOp_Grp7_swapgs);
733	case 1: return FNIEMOP_CALL(iemOp_Grp7_rdtscp);
734	}
735	return IEMOP_RAISE_INVALID_OPCODE();
736
737	IEM_NOT_REACHED_DEFAULT_CASE_RET();
738	}
739	}
740
741	/** Opcode 0x0f 0x00 /3. */
742	FNIEMOP_DEF_1(iemOpCommonLarLsl_Gv_Ew, bool, fIsLar)
743	{
744	IEMOP_HLP_NO_REAL_OR_V86_MODE();
745	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
746
747	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
748	{
749	IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_REG, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS \| DISOPTYPE_PRIVILEGED_NOTRAP);
750	switch (pVCpu->iem.s.enmEffOpSize)
751	{
752	case IEMMODE_16BIT:
753	{
754	IEM_MC_BEGIN(3, 0);
755	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
756	IEM_MC_ARG(uint16_t, u16Sel, 1);
757	IEM_MC_ARG_CONST(bool, fIsLarArg, fIsLar, 2);
758
759	IEM_MC_REF_GREG_U16(pu16Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
760	IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
761	IEM_MC_CALL_CIMPL_3(iemCImpl_LarLsl_u16, pu16Dst, u16Sel, fIsLarArg);
762
763	IEM_MC_END();
764	return VINF_SUCCESS;
765	}
766
767	case IEMMODE_32BIT:
768	case IEMMODE_64BIT:
769	{
770	IEM_MC_BEGIN(3, 0);
771	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
772	IEM_MC_ARG(uint16_t, u16Sel, 1);
773	IEM_MC_ARG_CONST(bool, fIsLarArg, fIsLar, 2);
774
775	IEM_MC_REF_GREG_U64(pu64Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
776	IEM_MC_FETCH_GREG_U16(u16Sel, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
777	IEM_MC_CALL_CIMPL_3(iemCImpl_LarLsl_u64, pu64Dst, u16Sel, fIsLarArg);
778
779	IEM_MC_END();
780	return VINF_SUCCESS;
781	}
782
783	IEM_NOT_REACHED_DEFAULT_CASE_RET();
784	}
785	}
786	else
787	{
788	switch (pVCpu->iem.s.enmEffOpSize)
789	{
790	case IEMMODE_16BIT:
791	{
792	IEM_MC_BEGIN(3, 1);
793	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
794	IEM_MC_ARG(uint16_t, u16Sel, 1);
795	IEM_MC_ARG_CONST(bool, fIsLarArg, fIsLar, 2);
796	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
797
798	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
799	IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_MEM, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS \| DISOPTYPE_PRIVILEGED_NOTRAP);
800
801	IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
802	IEM_MC_REF_GREG_U16(pu16Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
803	IEM_MC_CALL_CIMPL_3(iemCImpl_LarLsl_u16, pu16Dst, u16Sel, fIsLarArg);
804
805	IEM_MC_END();
806	return VINF_SUCCESS;
807	}
808
809	case IEMMODE_32BIT:
810	case IEMMODE_64BIT:
811	{
812	IEM_MC_BEGIN(3, 1);
813	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
814	IEM_MC_ARG(uint16_t, u16Sel, 1);
815	IEM_MC_ARG_CONST(bool, fIsLarArg, fIsLar, 2);
816	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
817
818	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
819	IEMOP_HLP_DECODED_NL_2(fIsLar ? OP_LAR : OP_LSL, IEMOPFORM_RM_MEM, OP_PARM_Gv, OP_PARM_Ew, DISOPTYPE_DANGEROUS \| DISOPTYPE_PRIVILEGED_NOTRAP);
820	/** @todo testcase: make sure it's a 16-bit read. */
821
822	IEM_MC_FETCH_MEM_U16(u16Sel, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
823	IEM_MC_REF_GREG_U64(pu64Dst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
824	IEM_MC_CALL_CIMPL_3(iemCImpl_LarLsl_u64, pu64Dst, u16Sel, fIsLarArg);
825
826	IEM_MC_END();
827	return VINF_SUCCESS;
828	}
829
830	IEM_NOT_REACHED_DEFAULT_CASE_RET();
831	}
832	}
833	}
834
835
836
837	/** Opcode 0x0f 0x02. */
838	FNIEMOP_DEF(iemOp_lar_Gv_Ew)
839	{
840	IEMOP_MNEMONIC(lar, "lar Gv,Ew");
841	return FNIEMOP_CALL_1(iemOpCommonLarLsl_Gv_Ew, true);
842	}
843
844
845	/** Opcode 0x0f 0x03. */
846	FNIEMOP_DEF(iemOp_lsl_Gv_Ew)
847	{
848	IEMOP_MNEMONIC(lsl, "lsl Gv,Ew");
849	return FNIEMOP_CALL_1(iemOpCommonLarLsl_Gv_Ew, false);
850	}
851
852
853	/** Opcode 0x0f 0x05. */
854	FNIEMOP_DEF(iemOp_syscall)
855	{
856	IEMOP_MNEMONIC(syscall, "syscall"); /** @todo 286 LOADALL */
857	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
858	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_syscall);
859	}
860
861
862	/** Opcode 0x0f 0x06. */
863	FNIEMOP_DEF(iemOp_clts)
864	{
865	IEMOP_MNEMONIC(clts, "clts");
866	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
867	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_clts);
868	}
869
870
871	/** Opcode 0x0f 0x07. */
872	FNIEMOP_DEF(iemOp_sysret)
873	{
874	IEMOP_MNEMONIC(sysret, "sysret"); /** @todo 386 LOADALL */
875	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
876	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_sysret);
877	}
878
879
880	/** Opcode 0x0f 0x08. */
881	FNIEMOP_STUB(iemOp_invd);
882	// IEMOP_HLP_MIN_486();
883
884
885	/** Opcode 0x0f 0x09. */
886	FNIEMOP_DEF(iemOp_wbinvd)
887	{
888	IEMOP_MNEMONIC(wbinvd, "wbinvd");
889	IEMOP_HLP_MIN_486();
890	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
891	IEM_MC_BEGIN(0, 0);
892	IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO();
893	IEM_MC_ADVANCE_RIP();
894	IEM_MC_END();
895	return VINF_SUCCESS; /* ignore for now */
896	}
897
898
899	/** Opcode 0x0f 0x0b. */
900	FNIEMOP_DEF(iemOp_ud2)
901	{
902	IEMOP_MNEMONIC(ud2, "ud2");
903	return IEMOP_RAISE_INVALID_OPCODE();
904	}
905
906	/** Opcode 0x0f 0x0d. */
907	FNIEMOP_DEF(iemOp_nop_Ev_GrpP)
908	{
909	/* AMD prefetch group, Intel implements this as NOP Ev (and so do we). */
910	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->f3DNowPrefetch)
911	{
912	IEMOP_MNEMONIC(GrpPNotSupported, "GrpP");
913	return IEMOP_RAISE_INVALID_OPCODE();
914	}
915
916	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
917	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
918	{
919	IEMOP_MNEMONIC(GrpPInvalid, "GrpP");
920	return IEMOP_RAISE_INVALID_OPCODE();
921	}
922
923	switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
924	{
925	case 2: /* Aliased to /0 for the time being. */
926	case 4: /* Aliased to /0 for the time being. */
927	case 5: /* Aliased to /0 for the time being. */
928	case 6: /* Aliased to /0 for the time being. */
929	case 7: /* Aliased to /0 for the time being. */
930	case 0: IEMOP_MNEMONIC(prefetch, "prefetch"); break;
931	case 1: IEMOP_MNEMONIC(prefetchw_1, "prefetchw"); break;
932	case 3: IEMOP_MNEMONIC(prefetchw_3, "prefetchw"); break;
933	IEM_NOT_REACHED_DEFAULT_CASE_RET();
934	}
935
936	IEM_MC_BEGIN(0, 1);
937	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
938	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
939	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
940	/* Currently a NOP. */
941	NOREF(GCPtrEffSrc);
942	IEM_MC_ADVANCE_RIP();
943	IEM_MC_END();
944	return VINF_SUCCESS;
945	}
946
947
948	/** Opcode 0x0f 0x0e. */
949	FNIEMOP_STUB(iemOp_femms);
950
951
952	/** Opcode 0x0f 0x0f 0x0c. */
953	FNIEMOP_STUB(iemOp_3Dnow_pi2fw_Pq_Qq);
954
955	/** Opcode 0x0f 0x0f 0x0d. */
956	FNIEMOP_STUB(iemOp_3Dnow_pi2fd_Pq_Qq);
957
958	/** Opcode 0x0f 0x0f 0x1c. */
959	FNIEMOP_STUB(iemOp_3Dnow_pf2fw_Pq_Qq);
960
961	/** Opcode 0x0f 0x0f 0x1d. */
962	FNIEMOP_STUB(iemOp_3Dnow_pf2fd_Pq_Qq);
963
964	/** Opcode 0x0f 0x0f 0x8a. */
965	FNIEMOP_STUB(iemOp_3Dnow_pfnacc_Pq_Qq);
966
967	/** Opcode 0x0f 0x0f 0x8e. */
968	FNIEMOP_STUB(iemOp_3Dnow_pfpnacc_Pq_Qq);
969
970	/** Opcode 0x0f 0x0f 0x90. */
971	FNIEMOP_STUB(iemOp_3Dnow_pfcmpge_Pq_Qq);
972
973	/** Opcode 0x0f 0x0f 0x94. */
974	FNIEMOP_STUB(iemOp_3Dnow_pfmin_Pq_Qq);
975
976	/** Opcode 0x0f 0x0f 0x96. */
977	FNIEMOP_STUB(iemOp_3Dnow_pfrcp_Pq_Qq);
978
979	/** Opcode 0x0f 0x0f 0x97. */
980	FNIEMOP_STUB(iemOp_3Dnow_pfrsqrt_Pq_Qq);
981
982	/** Opcode 0x0f 0x0f 0x9a. */
983	FNIEMOP_STUB(iemOp_3Dnow_pfsub_Pq_Qq);
984
985	/** Opcode 0x0f 0x0f 0x9e. */
986	FNIEMOP_STUB(iemOp_3Dnow_pfadd_PQ_Qq);
987
988	/** Opcode 0x0f 0x0f 0xa0. */
989	FNIEMOP_STUB(iemOp_3Dnow_pfcmpgt_Pq_Qq);
990
991	/** Opcode 0x0f 0x0f 0xa4. */
992	FNIEMOP_STUB(iemOp_3Dnow_pfmax_Pq_Qq);
993
994	/** Opcode 0x0f 0x0f 0xa6. */
995	FNIEMOP_STUB(iemOp_3Dnow_pfrcpit1_Pq_Qq);
996
997	/** Opcode 0x0f 0x0f 0xa7. */
998	FNIEMOP_STUB(iemOp_3Dnow_pfrsqit1_Pq_Qq);
999
1000	/** Opcode 0x0f 0x0f 0xaa. */
1001	FNIEMOP_STUB(iemOp_3Dnow_pfsubr_Pq_Qq);
1002
1003	/** Opcode 0x0f 0x0f 0xae. */
1004	FNIEMOP_STUB(iemOp_3Dnow_pfacc_PQ_Qq);
1005
1006	/** Opcode 0x0f 0x0f 0xb0. */
1007	FNIEMOP_STUB(iemOp_3Dnow_pfcmpeq_Pq_Qq);
1008
1009	/** Opcode 0x0f 0x0f 0xb4. */
1010	FNIEMOP_STUB(iemOp_3Dnow_pfmul_Pq_Qq);
1011
1012	/** Opcode 0x0f 0x0f 0xb6. */
1013	FNIEMOP_STUB(iemOp_3Dnow_pfrcpit2_Pq_Qq);
1014
1015	/** Opcode 0x0f 0x0f 0xb7. */
1016	FNIEMOP_STUB(iemOp_3Dnow_pmulhrw_Pq_Qq);
1017
1018	/** Opcode 0x0f 0x0f 0xbb. */
1019	FNIEMOP_STUB(iemOp_3Dnow_pswapd_Pq_Qq);
1020
1021	/** Opcode 0x0f 0x0f 0xbf. */
1022	FNIEMOP_STUB(iemOp_3Dnow_pavgusb_PQ_Qq);
1023
1024
1025	/** Opcode 0x0f 0x0f. */
1026	FNIEMOP_DEF(iemOp_3Dnow)
1027	{
1028	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->f3DNow)
1029	{
1030	IEMOP_MNEMONIC(Inv3Dnow, "3Dnow");
1031	return IEMOP_RAISE_INVALID_OPCODE();
1032	}
1033
1034	/* This is pretty sparse, use switch instead of table. */
1035	uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b);
1036	switch (b)
1037	{
1038	case 0x0c: return FNIEMOP_CALL(iemOp_3Dnow_pi2fw_Pq_Qq);
1039	case 0x0d: return FNIEMOP_CALL(iemOp_3Dnow_pi2fd_Pq_Qq);
1040	case 0x1c: return FNIEMOP_CALL(iemOp_3Dnow_pf2fw_Pq_Qq);
1041	case 0x1d: return FNIEMOP_CALL(iemOp_3Dnow_pf2fd_Pq_Qq);
1042	case 0x8a: return FNIEMOP_CALL(iemOp_3Dnow_pfnacc_Pq_Qq);
1043	case 0x8e: return FNIEMOP_CALL(iemOp_3Dnow_pfpnacc_Pq_Qq);
1044	case 0x90: return FNIEMOP_CALL(iemOp_3Dnow_pfcmpge_Pq_Qq);
1045	case 0x94: return FNIEMOP_CALL(iemOp_3Dnow_pfmin_Pq_Qq);
1046	case 0x96: return FNIEMOP_CALL(iemOp_3Dnow_pfrcp_Pq_Qq);
1047	case 0x97: return FNIEMOP_CALL(iemOp_3Dnow_pfrsqrt_Pq_Qq);
1048	case 0x9a: return FNIEMOP_CALL(iemOp_3Dnow_pfsub_Pq_Qq);
1049	case 0x9e: return FNIEMOP_CALL(iemOp_3Dnow_pfadd_PQ_Qq);
1050	case 0xa0: return FNIEMOP_CALL(iemOp_3Dnow_pfcmpgt_Pq_Qq);
1051	case 0xa4: return FNIEMOP_CALL(iemOp_3Dnow_pfmax_Pq_Qq);
1052	case 0xa6: return FNIEMOP_CALL(iemOp_3Dnow_pfrcpit1_Pq_Qq);
1053	case 0xa7: return FNIEMOP_CALL(iemOp_3Dnow_pfrsqit1_Pq_Qq);
1054	case 0xaa: return FNIEMOP_CALL(iemOp_3Dnow_pfsubr_Pq_Qq);
1055	case 0xae: return FNIEMOP_CALL(iemOp_3Dnow_pfacc_PQ_Qq);
1056	case 0xb0: return FNIEMOP_CALL(iemOp_3Dnow_pfcmpeq_Pq_Qq);
1057	case 0xb4: return FNIEMOP_CALL(iemOp_3Dnow_pfmul_Pq_Qq);
1058	case 0xb6: return FNIEMOP_CALL(iemOp_3Dnow_pfrcpit2_Pq_Qq);
1059	case 0xb7: return FNIEMOP_CALL(iemOp_3Dnow_pmulhrw_Pq_Qq);
1060	case 0xbb: return FNIEMOP_CALL(iemOp_3Dnow_pswapd_Pq_Qq);
1061	case 0xbf: return FNIEMOP_CALL(iemOp_3Dnow_pavgusb_PQ_Qq);
1062	default:
1063	return IEMOP_RAISE_INVALID_OPCODE();
1064	}
1065	}
1066
1067
1068	/** Opcode 0x0f 0x10 - vmovups Vps, Wps */
1069	FNIEMOP_STUB(iemOp_vmovups_Vps_Wps);
1070	/** Opcode 0x66 0x0f 0x10 - vmovupd Vpd, Wpd */
1071	FNIEMOP_STUB(iemOp_vmovupd_Vpd_Wpd);
1072	/** Opcode 0xf3 0x0f 0x10 - vmovss Vx, Hx, Wss */
1073	FNIEMOP_STUB(iemOp_vmovss_Vx_Hx_Wss);
1074	/** Opcode 0xf2 0x0f 0x10 - vmovsd Vx, Hx, Wsd */
1075	FNIEMOP_STUB(iemOp_vmovsd_Vx_Hx_Wsd);
1076
1077
1078	/**
1079	* @opcode 0x11
1080	* @oppfx none
1081	* @opcpuid sse
1082	* @opgroup og_sse_simdfp_datamove
1083	* @opxcpttype 4UA
1084	* @optest op1=1 op2=2 -> op1=2
1085	* @optest op1=0 op2=-42 -> op1=-42
1086	*/
1087	FNIEMOP_DEF(iemOp_vmovups_Wps_Vps)
1088	{
1089	IEMOP_MNEMONIC2(MR, MOVUPS, movups, Wps, Vps, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
1090	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1091	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1092	{
1093	/*
1094	* Register, register.
1095	*/
1096	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1097	IEM_MC_BEGIN(0, 0);
1098	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1099	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1100	IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB,
1101	((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1102	IEM_MC_ADVANCE_RIP();
1103	IEM_MC_END();
1104	}
1105	else
1106	{
1107	/*
1108	* Memory, register.
1109	*/
1110	IEM_MC_BEGIN(0, 2);
1111	IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1112	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1113
1114	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1115	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1116	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1117	IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1118
1119	IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1120	IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1121
1122	IEM_MC_ADVANCE_RIP();
1123	IEM_MC_END();
1124	}
1125	return VINF_SUCCESS;
1126	}
1127
1128
1129	/**
1130	* @opcode 0x11
1131	* @oppfx 0x66
1132	* @opcpuid sse2
1133	* @opgroup og_sse2_pcksclr_datamove
1134	* @opxcpttype 4UA
1135	* @optest op1=1 op2=2 -> op1=2
1136	* @optest op1=0 op2=-42 -> op1=-42
1137	*/
1138	FNIEMOP_DEF(iemOp_vmovupd_Wpd_Vpd)
1139	{
1140	IEMOP_MNEMONIC2(MR, MOVUPD, movupd, Wpd, Vpd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
1141	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1142	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1143	{
1144	/*
1145	* Register, register.
1146	*/
1147	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1148	IEM_MC_BEGIN(0, 0);
1149	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1150	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1151	IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB,
1152	((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1153	IEM_MC_ADVANCE_RIP();
1154	IEM_MC_END();
1155	}
1156	else
1157	{
1158	/*
1159	* Memory, register.
1160	*/
1161	IEM_MC_BEGIN(0, 2);
1162	IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1163	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1164
1165	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1166	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1167	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1168	IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1169
1170	IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1171	IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1172
1173	IEM_MC_ADVANCE_RIP();
1174	IEM_MC_END();
1175	}
1176	return VINF_SUCCESS;
1177	}
1178
1179
1180	/**
1181	* @opcode 0x11
1182	* @oppfx 0xf3
1183	* @opcpuid sse
1184	* @opgroup og_sse_simdfp_datamove
1185	* @opxcpttype 5
1186	* @optest op1=1 op2=2 -> op1=2
1187	* @optest op1=0 op2=-22 -> op1=-22
1188	*/
1189	FNIEMOP_DEF(iemOp_vmovss_Wss_Hx_Vss)
1190	{
1191	IEMOP_MNEMONIC2(MR, MOVSS, movss, Wss, Vss, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
1192	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1193	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1194	{
1195	/*
1196	* Register, register.
1197	*/
1198	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1199	IEM_MC_BEGIN(0, 1);
1200	IEM_MC_LOCAL(uint32_t, uSrc);
1201
1202	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1203	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1204	IEM_MC_FETCH_XREG_U32(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1205	IEM_MC_STORE_XREG_U32((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, uSrc);
1206
1207	IEM_MC_ADVANCE_RIP();
1208	IEM_MC_END();
1209	}
1210	else
1211	{
1212	/*
1213	* Memory, register.
1214	*/
1215	IEM_MC_BEGIN(0, 2);
1216	IEM_MC_LOCAL(uint32_t, uSrc);
1217	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1218
1219	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1220	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1221	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1222	IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1223
1224	IEM_MC_FETCH_XREG_U32(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1225	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1226
1227	IEM_MC_ADVANCE_RIP();
1228	IEM_MC_END();
1229	}
1230	return VINF_SUCCESS;
1231	}
1232
1233
1234	/**
1235	* @opcode 0x11
1236	* @oppfx 0xf2
1237	* @opcpuid sse2
1238	* @opgroup og_sse2_pcksclr_datamove
1239	* @opxcpttype 5
1240	* @optest op1=1 op2=2 -> op1=2
1241	* @optest op1=0 op2=-42 -> op1=-42
1242	*/
1243	FNIEMOP_DEF(iemOp_vmovsd_Wsd_Hx_Vsd)
1244	{
1245	IEMOP_MNEMONIC2(MR, MOVSD, movsd, Wsd, Vsd, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
1246	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1247	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1248	{
1249	/*
1250	* Register, register.
1251	*/
1252	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1253	IEM_MC_BEGIN(0, 1);
1254	IEM_MC_LOCAL(uint64_t, uSrc);
1255
1256	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1257	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1258	IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1259	IEM_MC_STORE_XREG_U64((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, uSrc);
1260
1261	IEM_MC_ADVANCE_RIP();
1262	IEM_MC_END();
1263	}
1264	else
1265	{
1266	/*
1267	* Memory, register.
1268	*/
1269	IEM_MC_BEGIN(0, 2);
1270	IEM_MC_LOCAL(uint64_t, uSrc);
1271	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1272
1273	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1274	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1275	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1276	IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1277
1278	IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1279	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1280
1281	IEM_MC_ADVANCE_RIP();
1282	IEM_MC_END();
1283	}
1284	return VINF_SUCCESS;
1285	}
1286
1287
1288	FNIEMOP_DEF(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps)
1289	{
1290	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1291	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1292	{
1293	/**
1294	* @opcode 0x12
1295	* @opcodesub 11 mr/reg
1296	* @oppfx none
1297	* @opcpuid sse
1298	* @opgroup og_sse_simdfp_datamove
1299	* @opxcpttype 5
1300	* @optest op1=1 op2=2 -> op1=2
1301	* @optest op1=0 op2=-42 -> op1=-42
1302	*/
1303	IEMOP_MNEMONIC2(RM_REG, MOVHLPS, movhlps, Vq, UqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
1304
1305	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1306	IEM_MC_BEGIN(0, 1);
1307	IEM_MC_LOCAL(uint64_t, uSrc);
1308
1309	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1310	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1311	IEM_MC_FETCH_XREG_HI_U64(uSrc, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
1312	IEM_MC_STORE_XREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, uSrc);
1313
1314	IEM_MC_ADVANCE_RIP();
1315	IEM_MC_END();
1316	}
1317	else
1318	{
1319	/**
1320	* @opdone
1321	* @opcode 0x12
1322	* @opcodesub !11 mr/reg
1323	* @oppfx none
1324	* @opcpuid sse
1325	* @opgroup og_sse_simdfp_datamove
1326	* @opxcpttype 5
1327	* @optest op1=1 op2=2 -> op1=2
1328	* @optest op1=0 op2=-42 -> op1=-42
1329	* @opfunction iemOp_vmovlps_Vq_Hq_Mq__vmovhlps
1330	*/
1331	IEMOP_MNEMONIC2(RM_MEM, MOVLPS, movlps, Vq, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
1332
1333	IEM_MC_BEGIN(0, 2);
1334	IEM_MC_LOCAL(uint64_t, uSrc);
1335	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1336
1337	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1338	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1339	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1340	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1341
1342	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1343	IEM_MC_STORE_XREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, uSrc);
1344
1345	IEM_MC_ADVANCE_RIP();
1346	IEM_MC_END();
1347	}
1348	return VINF_SUCCESS;
1349	}
1350
1351
1352	/**
1353	* @opcode 0x12
1354	* @opcodesub !11 mr/reg
1355	* @oppfx 0x66
1356	* @opcpuid sse2
1357	* @opgroup og_sse2_pcksclr_datamove
1358	* @opxcpttype 5
1359	* @optest op1=1 op2=2 -> op1=2
1360	* @optest op1=0 op2=-42 -> op1=-42
1361	*/
1362	FNIEMOP_DEF(iemOp_vmovlpd_Vq_Hq_Mq)
1363	{
1364	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1365	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1366	{
1367	IEMOP_MNEMONIC2(RM_MEM, MOVLPD, movlpd, Vq, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
1368
1369	IEM_MC_BEGIN(0, 2);
1370	IEM_MC_LOCAL(uint64_t, uSrc);
1371	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1372
1373	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1374	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1375	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1376	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1377
1378	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1379	IEM_MC_STORE_XREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, uSrc);
1380
1381	IEM_MC_ADVANCE_RIP();
1382	IEM_MC_END();
1383	return VINF_SUCCESS;
1384	}
1385
1386	/**
1387	* @opdone
1388	* @opmnemonic ud660f12m3
1389	* @opcode 0x12
1390	* @opcodesub 11 mr/reg
1391	* @oppfx 0x66
1392	* @opunused immediate
1393	* @opcpuid sse
1394	* @optest ->
1395	*/
1396	return IEMOP_RAISE_INVALID_OPCODE();
1397	}
1398
1399
1400	/**
1401	* @opcode 0x12
1402	* @oppfx 0xf3
1403	* @opcpuid sse3
1404	* @opgroup og_sse3_pcksclr_datamove
1405	* @opxcpttype 4
1406	* @optest op1=-1 op2=0xdddddddd00000002eeeeeeee00000001 ->
1407	* op1=0x00000002000000020000000100000001
1408	*/
1409	FNIEMOP_DEF(iemOp_vmovsldup_Vx_Wx)
1410	{
1411	IEMOP_MNEMONIC2(RM, MOVSLDUP, movsldup, Vdq, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
1412	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1413	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1414	{
1415	/*
1416	* Register, register.
1417	*/
1418	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1419	IEM_MC_BEGIN(2, 0);
1420	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1421	IEM_MC_ARG(PCRTUINT128U, puSrc, 1);
1422
1423	IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
1424	IEM_MC_PREPARE_SSE_USAGE();
1425
1426	IEM_MC_REF_XREG_U128_CONST(puSrc, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
1427	IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1428	IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
1429
1430	IEM_MC_ADVANCE_RIP();
1431	IEM_MC_END();
1432	}
1433	else
1434	{
1435	/*
1436	* Register, memory.
1437	*/
1438	IEM_MC_BEGIN(2, 2);
1439	IEM_MC_LOCAL(RTUINT128U, uSrc);
1440	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1441	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1442	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc, uSrc, 1);
1443
1444	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1445	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1446	IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
1447	IEM_MC_PREPARE_SSE_USAGE();
1448
1449	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1450	IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1451	IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movsldup, puDst, puSrc);
1452
1453	IEM_MC_ADVANCE_RIP();
1454	IEM_MC_END();
1455	}
1456	return VINF_SUCCESS;
1457	}
1458
1459
1460	/**
1461	* @opcode 0x12
1462	* @oppfx 0xf2
1463	* @opcpuid sse3
1464	* @opgroup og_sse3_pcksclr_datamove
1465	* @opxcpttype 5
1466	* @optest op1=-1 op2=0xddddddddeeeeeeee2222222211111111 ->
1467	* op1=0x22222222111111112222222211111111
1468	*/
1469	FNIEMOP_DEF(iemOp_vmovddup_Vx_Wx)
1470	{
1471	IEMOP_MNEMONIC2(RM, MOVDDUP, movddup, Vdq, Wdq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
1472	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1473	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1474	{
1475	/*
1476	* Register, register.
1477	*/
1478	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1479	IEM_MC_BEGIN(2, 0);
1480	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1481	IEM_MC_ARG(uint64_t, uSrc, 1);
1482
1483	IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
1484	IEM_MC_PREPARE_SSE_USAGE();
1485
1486	IEM_MC_FETCH_XREG_U64(uSrc, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
1487	IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1488	IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
1489
1490	IEM_MC_ADVANCE_RIP();
1491	IEM_MC_END();
1492	}
1493	else
1494	{
1495	/*
1496	* Register, memory.
1497	*/
1498	IEM_MC_BEGIN(2, 2);
1499	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1500	IEM_MC_ARG(PRTUINT128U, puDst, 0);
1501	IEM_MC_ARG(uint64_t, uSrc, 1);
1502
1503	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1504	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1505	IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
1506	IEM_MC_PREPARE_SSE_USAGE();
1507
1508	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1509	IEM_MC_REF_XREG_U128(puDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1510	IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_movddup, puDst, uSrc);
1511
1512	IEM_MC_ADVANCE_RIP();
1513	IEM_MC_END();
1514	}
1515	return VINF_SUCCESS;
1516	}
1517
1518
1519	/** Opcode 0x0f 0x13 - vmovlps Mq, Vq */
1520	FNIEMOP_STUB(iemOp_vmovlps_Mq_Vq);
1521
1522	/** Opcode 0x66 0x0f 0x13 - vmovlpd Mq, Vq */
1523	FNIEMOP_DEF(iemOp_vmovlpd_Mq_Vq)
1524	{
1525	IEMOP_MNEMONIC(movlpd_Mq_Vq, "movlpd Mq,Vq");
1526	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1527	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1528	{
1529	#if 0
1530	/*
1531	* Register, register.
1532	*/
1533	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1534	IEM_MC_BEGIN(0, 1);
1535	IEM_MC_LOCAL(uint64_t, uSrc);
1536	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1537	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1538	IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1539	IEM_MC_STORE_XREG_U64((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, uSrc);
1540	IEM_MC_ADVANCE_RIP();
1541	IEM_MC_END();
1542	#else
1543	return IEMOP_RAISE_INVALID_OPCODE();
1544	#endif
1545	}
1546	else
1547	{
1548	/*
1549	* Memory, register.
1550	*/
1551	IEM_MC_BEGIN(0, 2);
1552	IEM_MC_LOCAL(uint64_t, uSrc);
1553	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1554
1555	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1556	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1557	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1558	IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1559
1560	IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1561	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1562
1563	IEM_MC_ADVANCE_RIP();
1564	IEM_MC_END();
1565	}
1566	return VINF_SUCCESS;
1567	}
1568
1569	/* Opcode 0xf3 0x0f 0x13 - invalid */
1570	/* Opcode 0xf2 0x0f 0x13 - invalid */
1571
1572	/** Opcode 0x0f 0x14 - vunpcklps Vx, Hx, Wx*/
1573	FNIEMOP_STUB(iemOp_vunpcklps_Vx_Hx_Wx);
1574	/** Opcode 0x66 0x0f 0x14 - vunpcklpd Vx,Hx,Wx */
1575	FNIEMOP_STUB(iemOp_vunpcklpd_Vx_Hx_Wx);
1576	/* Opcode 0xf3 0x0f 0x14 - invalid */
1577	/* Opcode 0xf2 0x0f 0x14 - invalid */
1578	/** Opcode 0x0f 0x15 - vunpckhps Vx, Hx, Wx */
1579	FNIEMOP_STUB(iemOp_vunpckhps_Vx_Hx_Wx);
1580	/** Opcode 0x66 0x0f 0x15 - vunpckhpd Vx,Hx,Wx */
1581	FNIEMOP_STUB(iemOp_vunpckhpd_Vx_Hx_Wx);
1582	/* Opcode 0xf3 0x0f 0x15 - invalid */
1583	/* Opcode 0xf2 0x0f 0x15 - invalid */
1584	/** Opcode 0x0f 0x16 - vmovhpsv1 Vdq, Hq, Mq vmovlhps Vdq, Hq, Uq */
1585	FNIEMOP_STUB(iemOp_vmovhpsv1_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq); //NEXT
1586	/** Opcode 0x66 0x0f 0x16 - vmovhpdv1 Vdq, Hq, Mq */
1587	FNIEMOP_STUB(iemOp_vmovhpdv1_Vdq_Hq_Mq); //NEXT
1588	/** Opcode 0xf3 0x0f 0x16 - vmovshdup Vx, Wx */
1589	FNIEMOP_STUB(iemOp_vmovshdup_Vx_Wx); //NEXT
1590	/* Opcode 0xf2 0x0f 0x16 - invalid */
1591	/** Opcode 0x0f 0x17 - vmovhpsv1 Mq, Vq */
1592	FNIEMOP_STUB(iemOp_vmovhpsv1_Mq_Vq); //NEXT
1593	/** Opcode 0x66 0x0f 0x17 - vmovhpdv1 Mq, Vq */
1594	FNIEMOP_STUB(iemOp_vmovhpdv1_Mq_Vq); //NEXT
1595	/* Opcode 0xf3 0x0f 0x17 - invalid */
1596	/* Opcode 0xf2 0x0f 0x17 - invalid */
1597
1598
1599	/** Opcode 0x0f 0x18. */
1600	FNIEMOP_DEF(iemOp_prefetch_Grp16)
1601	{
1602	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1603	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1604	{
1605	switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
1606	{
1607	case 4: /* Aliased to /0 for the time being according to AMD. */
1608	case 5: /* Aliased to /0 for the time being according to AMD. */
1609	case 6: /* Aliased to /0 for the time being according to AMD. */
1610	case 7: /* Aliased to /0 for the time being according to AMD. */
1611	case 0: IEMOP_MNEMONIC(prefetchNTA, "prefetchNTA m8"); break;
1612	case 1: IEMOP_MNEMONIC(prefetchT0, "prefetchT0 m8"); break;
1613	case 2: IEMOP_MNEMONIC(prefetchT1, "prefetchT1 m8"); break;
1614	case 3: IEMOP_MNEMONIC(prefetchT2, "prefetchT2 m8"); break;
1615	IEM_NOT_REACHED_DEFAULT_CASE_RET();
1616	}
1617
1618	IEM_MC_BEGIN(0, 1);
1619	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1620	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1621	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1622	/* Currently a NOP. */
1623	NOREF(GCPtrEffSrc);
1624	IEM_MC_ADVANCE_RIP();
1625	IEM_MC_END();
1626	return VINF_SUCCESS;
1627	}
1628
1629	return IEMOP_RAISE_INVALID_OPCODE();
1630	}
1631
1632
1633	/** Opcode 0x0f 0x19..0x1f. */
1634	FNIEMOP_DEF(iemOp_nop_Ev)
1635	{
1636	IEMOP_MNEMONIC(nop_Ev, "nop Ev");
1637	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1638	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1639	{
1640	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1641	IEM_MC_BEGIN(0, 0);
1642	IEM_MC_ADVANCE_RIP();
1643	IEM_MC_END();
1644	}
1645	else
1646	{
1647	IEM_MC_BEGIN(0, 1);
1648	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1649	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1650	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1651	/* Currently a NOP. */
1652	NOREF(GCPtrEffSrc);
1653	IEM_MC_ADVANCE_RIP();
1654	IEM_MC_END();
1655	}
1656	return VINF_SUCCESS;
1657	}
1658
1659
1660	/** Opcode 0x0f 0x20. */
1661	FNIEMOP_DEF(iemOp_mov_Rd_Cd)
1662	{
1663	/* mod is ignored, as is operand size overrides. */
1664	IEMOP_MNEMONIC(mov_Rd_Cd, "mov Rd,Cd");
1665	IEMOP_HLP_MIN_386();
1666	if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
1667	pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT;
1668	else
1669	pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_32BIT;
1670
1671	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1672	uint8_t iCrReg = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg;
1673	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)
1674	{
1675	/* The lock prefix can be used to encode CR8 accesses on some CPUs. */
1676	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovCr8In32Bit)
1677	return IEMOP_RAISE_INVALID_OPCODE(); /* #UD takes precedence over #GP(), see test. */
1678	iCrReg \|= 8;
1679	}
1680	switch (iCrReg)
1681	{
1682	case 0: case 2: case 3: case 4: case 8:
1683	break;
1684	default:
1685	return IEMOP_RAISE_INVALID_OPCODE();
1686	}
1687	IEMOP_HLP_DONE_DECODING();
1688
1689	return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Rd_Cd, (X86_MODRM_RM_MASK & bRm) \| pVCpu->iem.s.uRexB, iCrReg);
1690	}
1691
1692
1693	/** Opcode 0x0f 0x21. */
1694	FNIEMOP_DEF(iemOp_mov_Rd_Dd)
1695	{
1696	IEMOP_MNEMONIC(mov_Rd_Dd, "mov Rd,Dd");
1697	IEMOP_HLP_MIN_386();
1698	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1699	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1700	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX_R)
1701	return IEMOP_RAISE_INVALID_OPCODE();
1702	return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Rd_Dd,
1703	(X86_MODRM_RM_MASK & bRm) \| pVCpu->iem.s.uRexB,
1704	((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK));
1705	}
1706
1707
1708	/** Opcode 0x0f 0x22. */
1709	FNIEMOP_DEF(iemOp_mov_Cd_Rd)
1710	{
1711	/* mod is ignored, as is operand size overrides. */
1712	IEMOP_MNEMONIC(mov_Cd_Rd, "mov Cd,Rd");
1713	IEMOP_HLP_MIN_386();
1714	if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
1715	pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT;
1716	else
1717	pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_32BIT;
1718
1719	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1720	uint8_t iCrReg = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg;
1721	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)
1722	{
1723	/* The lock prefix can be used to encode CR8 accesses on some CPUs. */
1724	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovCr8In32Bit)
1725	return IEMOP_RAISE_INVALID_OPCODE(); /* #UD takes precedence over #GP(), see test. */
1726	iCrReg \|= 8;
1727	}
1728	switch (iCrReg)
1729	{
1730	case 0: case 2: case 3: case 4: case 8:
1731	break;
1732	default:
1733	return IEMOP_RAISE_INVALID_OPCODE();
1734	}
1735	IEMOP_HLP_DONE_DECODING();
1736
1737	return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Cd_Rd, iCrReg, (X86_MODRM_RM_MASK & bRm) \| pVCpu->iem.s.uRexB);
1738	}
1739
1740
1741	/** Opcode 0x0f 0x23. */
1742	FNIEMOP_DEF(iemOp_mov_Dd_Rd)
1743	{
1744	IEMOP_MNEMONIC(mov_Dd_Rd, "mov Dd,Rd");
1745	IEMOP_HLP_MIN_386();
1746	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1747	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1748	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX_R)
1749	return IEMOP_RAISE_INVALID_OPCODE();
1750	return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_mov_Dd_Rd,
1751	((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK),
1752	(X86_MODRM_RM_MASK & bRm) \| pVCpu->iem.s.uRexB);
1753	}
1754
1755
1756	/** Opcode 0x0f 0x24. */
1757	FNIEMOP_DEF(iemOp_mov_Rd_Td)
1758	{
1759	IEMOP_MNEMONIC(mov_Rd_Td, "mov Rd,Td");
1760	/** @todo works on 386 and 486. */
1761	/* The RM byte is not considered, see testcase. */
1762	return IEMOP_RAISE_INVALID_OPCODE();
1763	}
1764
1765
1766	/** Opcode 0x0f 0x26. */
1767	FNIEMOP_DEF(iemOp_mov_Td_Rd)
1768	{
1769	IEMOP_MNEMONIC(mov_Td_Rd, "mov Td,Rd");
1770	/** @todo works on 386 and 486. */
1771	/* The RM byte is not considered, see testcase. */
1772	return IEMOP_RAISE_INVALID_OPCODE();
1773	}
1774
1775
1776	/** Opcode 0x0f 0x28 - vmovaps Vps, Wps */
1777	FNIEMOP_DEF(iemOp_vmovaps_Vps_Wps)
1778	{
1779	IEMOP_MNEMONIC(movaps_r_mr, "movaps r,mr");
1780	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1781	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1782	{
1783	/*
1784	* Register, register.
1785	*/
1786	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1787	IEM_MC_BEGIN(0, 0);
1788	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1789	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1790	IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg,
1791	(bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
1792	IEM_MC_ADVANCE_RIP();
1793	IEM_MC_END();
1794	}
1795	else
1796	{
1797	/*
1798	* Register, memory.
1799	*/
1800	IEM_MC_BEGIN(0, 2);
1801	IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1802	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1803
1804	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1805	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1806	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1807	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1808
1809	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1810	IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, uSrc);
1811
1812	IEM_MC_ADVANCE_RIP();
1813	IEM_MC_END();
1814	}
1815	return VINF_SUCCESS;
1816	}
1817
1818	/** Opcode 0x66 0x0f 0x28 - vmovapd Vpd, Wpd */
1819	FNIEMOP_DEF(iemOp_vmovapd_Vpd_Wpd)
1820	{
1821	IEMOP_MNEMONIC(movapd_r_mr, "movapd r,mr");
1822	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1823	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1824	{
1825	/*
1826	* Register, register.
1827	*/
1828	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1829	IEM_MC_BEGIN(0, 0);
1830	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1831	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1832	IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg,
1833	(bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
1834	IEM_MC_ADVANCE_RIP();
1835	IEM_MC_END();
1836	}
1837	else
1838	{
1839	/*
1840	* Register, memory.
1841	*/
1842	IEM_MC_BEGIN(0, 2);
1843	IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1844	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1845
1846	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1847	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1848	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1849	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1850
1851	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
1852	IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, uSrc);
1853
1854	IEM_MC_ADVANCE_RIP();
1855	IEM_MC_END();
1856	}
1857	return VINF_SUCCESS;
1858	}
1859
1860	/* Opcode 0xf3 0x0f 0x28 - invalid */
1861	/* Opcode 0xf2 0x0f 0x28 - invalid */
1862
1863	/** Opcode 0x0f 0x29 - vmovaps Wps, Vps */
1864	FNIEMOP_DEF(iemOp_vmovaps_Wps_Vps)
1865	{
1866	IEMOP_MNEMONIC(movaps_mr_r, "movaps Wps,Vps");
1867	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1868	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1869	{
1870	/*
1871	* Register, register.
1872	*/
1873	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1874	IEM_MC_BEGIN(0, 0);
1875	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1876	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1877	IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB,
1878	((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1879	IEM_MC_ADVANCE_RIP();
1880	IEM_MC_END();
1881	}
1882	else
1883	{
1884	/*
1885	* Memory, register.
1886	*/
1887	IEM_MC_BEGIN(0, 2);
1888	IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1889	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1890
1891	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1892	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1893	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1894	IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1895
1896	IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1897	IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1898
1899	IEM_MC_ADVANCE_RIP();
1900	IEM_MC_END();
1901	}
1902	return VINF_SUCCESS;
1903	}
1904
1905	/** Opcode 0x66 0x0f 0x29 - vmovapd Wpd,Vpd */
1906	FNIEMOP_DEF(iemOp_vmovapd_Wpd_Vpd)
1907	{
1908	IEMOP_MNEMONIC(movapd_mr_r, "movapd Wpd,Vpd");
1909	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1910	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
1911	{
1912	/*
1913	* Register, register.
1914	*/
1915	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1916	IEM_MC_BEGIN(0, 0);
1917	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1918	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1919	IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB,
1920	((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1921	IEM_MC_ADVANCE_RIP();
1922	IEM_MC_END();
1923	}
1924	else
1925	{
1926	/*
1927	* Memory, register.
1928	*/
1929	IEM_MC_BEGIN(0, 2);
1930	IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1931	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1932
1933	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1934	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1935	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
1936	IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
1937
1938	IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1939	IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1940
1941	IEM_MC_ADVANCE_RIP();
1942	IEM_MC_END();
1943	}
1944	return VINF_SUCCESS;
1945	}
1946
1947	/* Opcode 0xf3 0x0f 0x29 - invalid */
1948	/* Opcode 0xf2 0x0f 0x29 - invalid */
1949
1950
1951	/** Opcode 0x0f 0x2a - cvtpi2ps Vps, Qpi */
1952	FNIEMOP_STUB(iemOp_cvtpi2ps_Vps_Qpi); //NEXT
1953	/** Opcode 0x66 0x0f 0x2a - cvtpi2pd Vpd, Qpi */
1954	FNIEMOP_STUB(iemOp_cvtpi2pd_Vpd_Qpi); //NEXT
1955	/** Opcode 0xf3 0x0f 0x2a - vcvtsi2ss Vss, Hss, Ey */
1956	FNIEMOP_STUB(iemOp_vcvtsi2ss_Vss_Hss_Ey); //NEXT
1957	/** Opcode 0xf2 0x0f 0x2a - vcvtsi2sd Vsd, Hsd, Ey */
1958	FNIEMOP_STUB(iemOp_vcvtsi2sd_Vsd_Hsd_Ey); //NEXT
1959
1960
1961	/** Opcode 0x0f 0x2b - vmovntps Mps, Vps */
1962	FNIEMOP_DEF(iemOp_vmovntps_Mps_Vps)
1963	{
1964	IEMOP_MNEMONIC(movntps_mr_r, "movntps Mps,Vps");
1965	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1966	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1967	{
1968	/*
1969	* memory, register.
1970	*/
1971	IEM_MC_BEGIN(0, 2);
1972	IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
1973	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
1974
1975	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
1976	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
1977	IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
1978	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
1979
1980	IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
1981	IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
1982
1983	IEM_MC_ADVANCE_RIP();
1984	IEM_MC_END();
1985	}
1986	/* The register, register encoding is invalid. */
1987	else
1988	return IEMOP_RAISE_INVALID_OPCODE();
1989	return VINF_SUCCESS;
1990	}
1991
1992	/** Opcode 0x66 0x0f 0x2b - vmovntpd Mpd, Vpd */
1993	FNIEMOP_DEF(iemOp_vmovntpd_Mpd_Vpd)
1994	{
1995	IEMOP_MNEMONIC(movntpd_mr_r, "movntpd Mdq,Vpd");
1996	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
1997	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
1998	{
1999	/*
2000	* memory, register.
2001	*/
2002	IEM_MC_BEGIN(0, 2);
2003	IEM_MC_LOCAL(RTUINT128U, uSrc); /** @todo optimize this one day... */
2004	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2005
2006	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2007	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2008	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2009	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2010
2011	IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
2012	IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
2013
2014	IEM_MC_ADVANCE_RIP();
2015	IEM_MC_END();
2016	}
2017	/* The register, register encoding is invalid. */
2018	else
2019	return IEMOP_RAISE_INVALID_OPCODE();
2020	return VINF_SUCCESS;
2021	}
2022	/* Opcode 0xf3 0x0f 0x2b - invalid */
2023	/* Opcode 0xf2 0x0f 0x2b - invalid */
2024
2025
2026	/** Opcode 0x0f 0x2c - cvttps2pi Ppi, Wps */
2027	FNIEMOP_STUB(iemOp_cvttps2pi_Ppi_Wps);
2028	/** Opcode 0x66 0x0f 0x2c - cvttpd2pi Ppi, Wpd */
2029	FNIEMOP_STUB(iemOp_cvttpd2pi_Ppi_Wpd);
2030	/** Opcode 0xf3 0x0f 0x2c - vcvttss2si Gy, Wss */
2031	FNIEMOP_STUB(iemOp_vcvttss2si_Gy_Wss);
2032	/** Opcode 0xf2 0x0f 0x2c - vcvttsd2si Gy, Wsd */
2033	FNIEMOP_STUB(iemOp_vcvttsd2si_Gy_Wsd);
2034
2035	/** Opcode 0x0f 0x2d - cvtps2pi Ppi, Wps */
2036	FNIEMOP_STUB(iemOp_cvtps2pi_Ppi_Wps);
2037	/** Opcode 0x66 0x0f 0x2d - cvtpd2pi Qpi, Wpd */
2038	FNIEMOP_STUB(iemOp_cvtpd2pi_Qpi_Wpd);
2039	/** Opcode 0xf3 0x0f 0x2d - vcvtss2si Gy, Wss */
2040	FNIEMOP_STUB(iemOp_vcvtss2si_Gy_Wss);
2041	/** Opcode 0xf2 0x0f 0x2d - vcvtsd2si Gy, Wsd */
2042	FNIEMOP_STUB(iemOp_vcvtsd2si_Gy_Wsd);
2043
2044	/** Opcode 0x0f 0x2e - vucomiss Vss, Wss */
2045	FNIEMOP_STUB(iemOp_vucomiss_Vss_Wss); // NEXT
2046	/** Opcode 0x66 0x0f 0x2e - vucomisd Vsd, Wsd */
2047	FNIEMOP_STUB(iemOp_vucomisd_Vsd_Wsd); // NEXT
2048	/* Opcode 0xf3 0x0f 0x2e - invalid */
2049	/* Opcode 0xf2 0x0f 0x2e - invalid */
2050
2051	/** Opcode 0x0f 0x2f - vcomiss Vss, Wss */
2052	FNIEMOP_STUB(iemOp_vcomiss_Vss_Wss);
2053	/** Opcode 0x66 0x0f 0x2f - vcomisd Vsd, Wsd */
2054	FNIEMOP_STUB(iemOp_vcomisd_Vsd_Wsd);
2055	/* Opcode 0xf3 0x0f 0x2f - invalid */
2056	/* Opcode 0xf2 0x0f 0x2f - invalid */
2057
2058	/** Opcode 0x0f 0x30. */
2059	FNIEMOP_DEF(iemOp_wrmsr)
2060	{
2061	IEMOP_MNEMONIC(wrmsr, "wrmsr");
2062	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2063	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_wrmsr);
2064	}
2065
2066
2067	/** Opcode 0x0f 0x31. */
2068	FNIEMOP_DEF(iemOp_rdtsc)
2069	{
2070	IEMOP_MNEMONIC(rdtsc, "rdtsc");
2071	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2072	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_rdtsc);
2073	}
2074
2075
2076	/** Opcode 0x0f 0x33. */
2077	FNIEMOP_DEF(iemOp_rdmsr)
2078	{
2079	IEMOP_MNEMONIC(rdmsr, "rdmsr");
2080	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2081	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_rdmsr);
2082	}
2083
2084
2085	/** Opcode 0x0f 0x34. */
2086	FNIEMOP_STUB(iemOp_rdpmc);
2087	/** Opcode 0x0f 0x34. */
2088	FNIEMOP_STUB(iemOp_sysenter);
2089	/** Opcode 0x0f 0x35. */
2090	FNIEMOP_STUB(iemOp_sysexit);
2091	/** Opcode 0x0f 0x37. */
2092	FNIEMOP_STUB(iemOp_getsec);
2093	/** Opcode 0x0f 0x38. */
2094	FNIEMOP_UD_STUB(iemOp_3byte_Esc_A4); /* Here there be dragons... */
2095	/** Opcode 0x0f 0x3a. */
2096	FNIEMOP_UD_STUB(iemOp_3byte_Esc_A5); /* Here there be dragons... */
2097
2098
2099	/**
2100	* Implements a conditional move.
2101	*
2102	* Wish there was an obvious way to do this where we could share and reduce
2103	* code bloat.
2104	*
2105	* @param a_Cnd The conditional "microcode" operation.
2106	*/
2107	#define CMOV_X(a_Cnd) \
2108	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \
2109	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) \
2110	{ \
2111	switch (pVCpu->iem.s.enmEffOpSize) \
2112	{ \
2113	case IEMMODE_16BIT: \
2114	IEM_MC_BEGIN(0, 1); \
2115	IEM_MC_LOCAL(uint16_t, u16Tmp); \
2116	a_Cnd { \
2117	IEM_MC_FETCH_GREG_U16(u16Tmp, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB); \
2118	IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u16Tmp); \
2119	} IEM_MC_ENDIF(); \
2120	IEM_MC_ADVANCE_RIP(); \
2121	IEM_MC_END(); \
2122	return VINF_SUCCESS; \
2123	\
2124	case IEMMODE_32BIT: \
2125	IEM_MC_BEGIN(0, 1); \
2126	IEM_MC_LOCAL(uint32_t, u32Tmp); \
2127	a_Cnd { \
2128	IEM_MC_FETCH_GREG_U32(u32Tmp, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB); \
2129	IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u32Tmp); \
2130	} IEM_MC_ELSE() { \
2131	IEM_MC_CLEAR_HIGH_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg); \
2132	} IEM_MC_ENDIF(); \
2133	IEM_MC_ADVANCE_RIP(); \
2134	IEM_MC_END(); \
2135	return VINF_SUCCESS; \
2136	\
2137	case IEMMODE_64BIT: \
2138	IEM_MC_BEGIN(0, 1); \
2139	IEM_MC_LOCAL(uint64_t, u64Tmp); \
2140	a_Cnd { \
2141	IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB); \
2142	IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u64Tmp); \
2143	} IEM_MC_ENDIF(); \
2144	IEM_MC_ADVANCE_RIP(); \
2145	IEM_MC_END(); \
2146	return VINF_SUCCESS; \
2147	\
2148	IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
2149	} \
2150	} \
2151	else \
2152	{ \
2153	switch (pVCpu->iem.s.enmEffOpSize) \
2154	{ \
2155	case IEMMODE_16BIT: \
2156	IEM_MC_BEGIN(0, 2); \
2157	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2158	IEM_MC_LOCAL(uint16_t, u16Tmp); \
2159	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2160	IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2161	a_Cnd { \
2162	IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u16Tmp); \
2163	} IEM_MC_ENDIF(); \
2164	IEM_MC_ADVANCE_RIP(); \
2165	IEM_MC_END(); \
2166	return VINF_SUCCESS; \
2167	\
2168	case IEMMODE_32BIT: \
2169	IEM_MC_BEGIN(0, 2); \
2170	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2171	IEM_MC_LOCAL(uint32_t, u32Tmp); \
2172	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2173	IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2174	a_Cnd { \
2175	IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u32Tmp); \
2176	} IEM_MC_ELSE() { \
2177	IEM_MC_CLEAR_HIGH_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg); \
2178	} IEM_MC_ENDIF(); \
2179	IEM_MC_ADVANCE_RIP(); \
2180	IEM_MC_END(); \
2181	return VINF_SUCCESS; \
2182	\
2183	case IEMMODE_64BIT: \
2184	IEM_MC_BEGIN(0, 2); \
2185	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); \
2186	IEM_MC_LOCAL(uint64_t, u64Tmp); \
2187	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); \
2188	IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); \
2189	a_Cnd { \
2190	IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u64Tmp); \
2191	} IEM_MC_ENDIF(); \
2192	IEM_MC_ADVANCE_RIP(); \
2193	IEM_MC_END(); \
2194	return VINF_SUCCESS; \
2195	\
2196	IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
2197	} \
2198	} do {} while (0)
2199
2200
2201
2202	/** Opcode 0x0f 0x40. */
2203	FNIEMOP_DEF(iemOp_cmovo_Gv_Ev)
2204	{
2205	IEMOP_MNEMONIC(cmovo_Gv_Ev, "cmovo Gv,Ev");
2206	CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF));
2207	}
2208
2209
2210	/** Opcode 0x0f 0x41. */
2211	FNIEMOP_DEF(iemOp_cmovno_Gv_Ev)
2212	{
2213	IEMOP_MNEMONIC(cmovno_Gv_Ev, "cmovno Gv,Ev");
2214	CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_OF));
2215	}
2216
2217
2218	/** Opcode 0x0f 0x42. */
2219	FNIEMOP_DEF(iemOp_cmovc_Gv_Ev)
2220	{
2221	IEMOP_MNEMONIC(cmovc_Gv_Ev, "cmovc Gv,Ev");
2222	CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF));
2223	}
2224
2225
2226	/** Opcode 0x0f 0x43. */
2227	FNIEMOP_DEF(iemOp_cmovnc_Gv_Ev)
2228	{
2229	IEMOP_MNEMONIC(cmovnc_Gv_Ev, "cmovnc Gv,Ev");
2230	CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_CF));
2231	}
2232
2233
2234	/** Opcode 0x0f 0x44. */
2235	FNIEMOP_DEF(iemOp_cmove_Gv_Ev)
2236	{
2237	IEMOP_MNEMONIC(cmove_Gv_Ev, "cmove Gv,Ev");
2238	CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF));
2239	}
2240
2241
2242	/** Opcode 0x0f 0x45. */
2243	FNIEMOP_DEF(iemOp_cmovne_Gv_Ev)
2244	{
2245	IEMOP_MNEMONIC(cmovne_Gv_Ev, "cmovne Gv,Ev");
2246	CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_ZF));
2247	}
2248
2249
2250	/** Opcode 0x0f 0x46. */
2251	FNIEMOP_DEF(iemOp_cmovbe_Gv_Ev)
2252	{
2253	IEMOP_MNEMONIC(cmovbe_Gv_Ev, "cmovbe Gv,Ev");
2254	CMOV_X(IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF \| X86_EFL_ZF));
2255	}
2256
2257
2258	/** Opcode 0x0f 0x47. */
2259	FNIEMOP_DEF(iemOp_cmovnbe_Gv_Ev)
2260	{
2261	IEMOP_MNEMONIC(cmovnbe_Gv_Ev, "cmovnbe Gv,Ev");
2262	CMOV_X(IEM_MC_IF_EFL_NO_BITS_SET(X86_EFL_CF \| X86_EFL_ZF));
2263	}
2264
2265
2266	/** Opcode 0x0f 0x48. */
2267	FNIEMOP_DEF(iemOp_cmovs_Gv_Ev)
2268	{
2269	IEMOP_MNEMONIC(cmovs_Gv_Ev, "cmovs Gv,Ev");
2270	CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF));
2271	}
2272
2273
2274	/** Opcode 0x0f 0x49. */
2275	FNIEMOP_DEF(iemOp_cmovns_Gv_Ev)
2276	{
2277	IEMOP_MNEMONIC(cmovns_Gv_Ev, "cmovns Gv,Ev");
2278	CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_SF));
2279	}
2280
2281
2282	/** Opcode 0x0f 0x4a. */
2283	FNIEMOP_DEF(iemOp_cmovp_Gv_Ev)
2284	{
2285	IEMOP_MNEMONIC(cmovp_Gv_Ev, "cmovp Gv,Ev");
2286	CMOV_X(IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF));
2287	}
2288
2289
2290	/** Opcode 0x0f 0x4b. */
2291	FNIEMOP_DEF(iemOp_cmovnp_Gv_Ev)
2292	{
2293	IEMOP_MNEMONIC(cmovnp_Gv_Ev, "cmovnp Gv,Ev");
2294	CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_PF));
2295	}
2296
2297
2298	/** Opcode 0x0f 0x4c. */
2299	FNIEMOP_DEF(iemOp_cmovl_Gv_Ev)
2300	{
2301	IEMOP_MNEMONIC(cmovl_Gv_Ev, "cmovl Gv,Ev");
2302	CMOV_X(IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF));
2303	}
2304
2305
2306	/** Opcode 0x0f 0x4d. */
2307	FNIEMOP_DEF(iemOp_cmovnl_Gv_Ev)
2308	{
2309	IEMOP_MNEMONIC(cmovnl_Gv_Ev, "cmovnl Gv,Ev");
2310	CMOV_X(IEM_MC_IF_EFL_BITS_EQ(X86_EFL_SF, X86_EFL_OF));
2311	}
2312
2313
2314	/** Opcode 0x0f 0x4e. */
2315	FNIEMOP_DEF(iemOp_cmovle_Gv_Ev)
2316	{
2317	IEMOP_MNEMONIC(cmovle_Gv_Ev, "cmovle Gv,Ev");
2318	CMOV_X(IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF));
2319	}
2320
2321
2322	/** Opcode 0x0f 0x4f. */
2323	FNIEMOP_DEF(iemOp_cmovnle_Gv_Ev)
2324	{
2325	IEMOP_MNEMONIC(cmovnle_Gv_Ev, "cmovnle Gv,Ev");
2326	CMOV_X(IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF));
2327	}
2328
2329	#undef CMOV_X
2330
2331	/** Opcode 0x0f 0x50 - vmovmskps Gy, Ups */
2332	FNIEMOP_STUB(iemOp_vmovmskps_Gy_Ups);
2333	/** Opcode 0x66 0x0f 0x50 - vmovmskpd Gy,Upd */
2334	FNIEMOP_STUB(iemOp_vmovmskpd_Gy_Upd);
2335	/* Opcode 0xf3 0x0f 0x50 - invalid */
2336	/* Opcode 0xf2 0x0f 0x50 - invalid */
2337
2338	/** Opcode 0x0f 0x51 - vsqrtps Vps, Wps */
2339	FNIEMOP_STUB(iemOp_vsqrtps_Vps_Wps);
2340	/** Opcode 0x66 0x0f 0x51 - vsqrtpd Vpd, Wpd */
2341	FNIEMOP_STUB(iemOp_vsqrtpd_Vpd_Wpd);
2342	/** Opcode 0xf3 0x0f 0x51 - vsqrtss Vss, Hss, Wss */
2343	FNIEMOP_STUB(iemOp_vsqrtss_Vss_Hss_Wss);
2344	/** Opcode 0xf2 0x0f 0x51 - vsqrtsd Vsd, Hsd, Wsd */
2345	FNIEMOP_STUB(iemOp_vsqrtsd_Vsd_Hsd_Wsd);
2346
2347	/** Opcode 0x0f 0x52 - vrsqrtps Vps, Wps */
2348	FNIEMOP_STUB(iemOp_vrsqrtps_Vps_Wps);
2349	/* Opcode 0x66 0x0f 0x52 - invalid */
2350	/** Opcode 0xf3 0x0f 0x52 - vrsqrtss Vss, Hss, Wss */
2351	FNIEMOP_STUB(iemOp_vrsqrtss_Vss_Hss_Wss);
2352	/* Opcode 0xf2 0x0f 0x52 - invalid */
2353
2354	/** Opcode 0x0f 0x53 - vrcpps Vps, Wps */
2355	FNIEMOP_STUB(iemOp_vrcpps_Vps_Wps);
2356	/* Opcode 0x66 0x0f 0x53 - invalid */
2357	/** Opcode 0xf3 0x0f 0x53 - vrcpss Vss, Hss, Wss */
2358	FNIEMOP_STUB(iemOp_vrcpss_Vss_Hss_Wss);
2359	/* Opcode 0xf2 0x0f 0x53 - invalid */
2360
2361	/** Opcode 0x0f 0x54 - vandps Vps, Hps, Wps */
2362	FNIEMOP_STUB(iemOp_vandps_Vps_Hps_Wps);
2363	/** Opcode 0x66 0x0f 0x54 - vandpd Vpd, Hpd, Wpd */
2364	FNIEMOP_STUB(iemOp_vandpd_Vpd_Hpd_Wpd);
2365	/* Opcode 0xf3 0x0f 0x54 - invalid */
2366	/* Opcode 0xf2 0x0f 0x54 - invalid */
2367
2368	/** Opcode 0x0f 0x55 - vandnps Vps, Hps, Wps */
2369	FNIEMOP_STUB(iemOp_vandnps_Vps_Hps_Wps);
2370	/** Opcode 0x66 0x0f 0x55 - vandnpd Vpd, Hpd, Wpd */
2371	FNIEMOP_STUB(iemOp_vandnpd_Vpd_Hpd_Wpd);
2372	/* Opcode 0xf3 0x0f 0x55 - invalid */
2373	/* Opcode 0xf2 0x0f 0x55 - invalid */
2374
2375	/** Opcode 0x0f 0x56 - vorps Vps, Hps, Wps */
2376	FNIEMOP_STUB(iemOp_vorps_Vps_Hps_Wps);
2377	/** Opcode 0x66 0x0f 0x56 - vorpd Vpd, Hpd, Wpd */
2378	FNIEMOP_STUB(iemOp_vorpd_Vpd_Hpd_Wpd);
2379	/* Opcode 0xf3 0x0f 0x56 - invalid */
2380	/* Opcode 0xf2 0x0f 0x56 - invalid */
2381
2382	/** Opcode 0x0f 0x57 - vxorps Vps, Hps, Wps */
2383	FNIEMOP_STUB(iemOp_vxorps_Vps_Hps_Wps);
2384	/** Opcode 0x66 0x0f 0x57 - vxorpd Vpd, Hpd, Wpd */
2385	FNIEMOP_STUB(iemOp_vxorpd_Vpd_Hpd_Wpd);
2386	/* Opcode 0xf3 0x0f 0x57 - invalid */
2387	/* Opcode 0xf2 0x0f 0x57 - invalid */
2388
2389	/** Opcode 0x0f 0x58 - vaddps Vps, Hps, Wps */
2390	FNIEMOP_STUB(iemOp_vaddps_Vps_Hps_Wps);
2391	/** Opcode 0x66 0x0f 0x58 - vaddpd Vpd, Hpd, Wpd */
2392	FNIEMOP_STUB(iemOp_vaddpd_Vpd_Hpd_Wpd);
2393	/** Opcode 0xf3 0x0f 0x58 - vaddss Vss, Hss, Wss */
2394	FNIEMOP_STUB(iemOp_vaddss_Vss_Hss_Wss);
2395	/** Opcode 0xf2 0x0f 0x58 - vaddsd Vsd, Hsd, Wsd */
2396	FNIEMOP_STUB(iemOp_vaddsd_Vsd_Hsd_Wsd);
2397
2398	/** Opcode 0x0f 0x59 - vmulps Vps, Hps, Wps */
2399	FNIEMOP_STUB(iemOp_vmulps_Vps_Hps_Wps);
2400	/** Opcode 0x66 0x0f 0x59 - vmulpd Vpd, Hpd, Wpd */
2401	FNIEMOP_STUB(iemOp_vmulpd_Vpd_Hpd_Wpd);
2402	/** Opcode 0xf3 0x0f 0x59 - vmulss Vss, Hss, Wss */
2403	FNIEMOP_STUB(iemOp_vmulss_Vss_Hss_Wss);
2404	/** Opcode 0xf2 0x0f 0x59 - vmulsd Vsd, Hsd, Wsd */
2405	FNIEMOP_STUB(iemOp_vmulsd_Vsd_Hsd_Wsd);
2406
2407	/** Opcode 0x0f 0x5a - vcvtps2pd Vpd, Wps */
2408	FNIEMOP_STUB(iemOp_vcvtps2pd_Vpd_Wps);
2409	/** Opcode 0x66 0x0f 0x5a - vcvtpd2ps Vps, Wpd */
2410	FNIEMOP_STUB(iemOp_vcvtpd2ps_Vps_Wpd);
2411	/** Opcode 0xf3 0x0f 0x5a - vcvtss2sd Vsd, Hx, Wss */
2412	FNIEMOP_STUB(iemOp_vcvtss2sd_Vsd_Hx_Wss);
2413	/** Opcode 0xf2 0x0f 0x5a - vcvtsd2ss Vss, Hx, Wsd */
2414	FNIEMOP_STUB(iemOp_vcvtsd2ss_Vss_Hx_Wsd);
2415
2416	/** Opcode 0x0f 0x5b - vcvtdq2ps Vps, Wdq */
2417	FNIEMOP_STUB(iemOp_vcvtdq2ps_Vps_Wdq);
2418	/** Opcode 0x66 0x0f 0x5b - vcvtps2dq Vdq, Wps */
2419	FNIEMOP_STUB(iemOp_vcvtps2dq_Vdq_Wps);
2420	/** Opcode 0xf3 0x0f 0x5b - vcvttps2dq Vdq, Wps */
2421	FNIEMOP_STUB(iemOp_vcvttps2dq_Vdq_Wps);
2422	/* Opcode 0xf2 0x0f 0x5b - invalid */
2423
2424	/** Opcode 0x0f 0x5c - vsubps Vps, Hps, Wps */
2425	FNIEMOP_STUB(iemOp_vsubps_Vps_Hps_Wps);
2426	/** Opcode 0x66 0x0f 0x5c - vsubpd Vpd, Hpd, Wpd */
2427	FNIEMOP_STUB(iemOp_vsubpd_Vpd_Hpd_Wpd);
2428	/** Opcode 0xf3 0x0f 0x5c - vsubss Vss, Hss, Wss */
2429	FNIEMOP_STUB(iemOp_vsubss_Vss_Hss_Wss);
2430	/** Opcode 0xf2 0x0f 0x5c - vsubsd Vsd, Hsd, Wsd */
2431	FNIEMOP_STUB(iemOp_vsubsd_Vsd_Hsd_Wsd);
2432
2433	/** Opcode 0x0f 0x5d - vminps Vps, Hps, Wps */
2434	FNIEMOP_STUB(iemOp_vminps_Vps_Hps_Wps);
2435	/** Opcode 0x66 0x0f 0x5d - vminpd Vpd, Hpd, Wpd */
2436	FNIEMOP_STUB(iemOp_vminpd_Vpd_Hpd_Wpd);
2437	/** Opcode 0xf3 0x0f 0x5d - vminss Vss, Hss, Wss */
2438	FNIEMOP_STUB(iemOp_vminss_Vss_Hss_Wss);
2439	/** Opcode 0xf2 0x0f 0x5d - vminsd Vsd, Hsd, Wsd */
2440	FNIEMOP_STUB(iemOp_vminsd_Vsd_Hsd_Wsd);
2441
2442	/** Opcode 0x0f 0x5e - vdivps Vps, Hps, Wps */
2443	FNIEMOP_STUB(iemOp_vdivps_Vps_Hps_Wps);
2444	/** Opcode 0x66 0x0f 0x5e - vdivpd Vpd, Hpd, Wpd */
2445	FNIEMOP_STUB(iemOp_vdivpd_Vpd_Hpd_Wpd);
2446	/** Opcode 0xf3 0x0f 0x5e - vdivss Vss, Hss, Wss */
2447	FNIEMOP_STUB(iemOp_vdivss_Vss_Hss_Wss);
2448	/** Opcode 0xf2 0x0f 0x5e - vdivsd Vsd, Hsd, Wsd */
2449	FNIEMOP_STUB(iemOp_vdivsd_Vsd_Hsd_Wsd);
2450
2451	/** Opcode 0x0f 0x5f - vmaxps Vps, Hps, Wps */
2452	FNIEMOP_STUB(iemOp_vmaxps_Vps_Hps_Wps);
2453	/** Opcode 0x66 0x0f 0x5f - vmaxpd Vpd, Hpd, Wpd */
2454	FNIEMOP_STUB(iemOp_vmaxpd_Vpd_Hpd_Wpd);
2455	/** Opcode 0xf3 0x0f 0x5f - vmaxss Vss, Hss, Wss */
2456	FNIEMOP_STUB(iemOp_vmaxss_Vss_Hss_Wss);
2457	/** Opcode 0xf2 0x0f 0x5f - vmaxsd Vsd, Hsd, Wsd */
2458	FNIEMOP_STUB(iemOp_vmaxsd_Vsd_Hsd_Wsd);
2459
2460	/**
2461	* Common worker for MMX instructions on the forms:
2462	* pxxxx mm1, mm2/mem32
2463	*
2464	* The 2nd operand is the first half of a register, which in the memory case
2465	* means a 32-bit memory access for MMX and 128-bit aligned 64-bit or 128-bit
2466	* memory accessed for MMX.
2467	*
2468	* Exceptions type 4.
2469	*/
2470	FNIEMOP_DEF_1(iemOpCommonMmx_LowLow_To_Full, PCIEMOPMEDIAF1L1, pImpl)
2471	{
2472	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2473	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2474	{
2475	/*
2476	* Register, register.
2477	*/
2478	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2479	IEM_MC_BEGIN(2, 0);
2480	IEM_MC_ARG(PRTUINT128U, pDst, 0);
2481	IEM_MC_ARG(uint64_t const *, pSrc, 1);
2482	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2483	IEM_MC_PREPARE_SSE_USAGE();
2484	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
2485	IEM_MC_REF_XREG_U64_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
2486	IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2487	IEM_MC_ADVANCE_RIP();
2488	IEM_MC_END();
2489	}
2490	else
2491	{
2492	/*
2493	* Register, memory.
2494	*/
2495	IEM_MC_BEGIN(2, 2);
2496	IEM_MC_ARG(PRTUINT128U, pDst, 0);
2497	IEM_MC_LOCAL(uint64_t, uSrc);
2498	IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
2499	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2500
2501	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2502	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2503	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2504	IEM_MC_FETCH_MEM_U64_ALIGN_U128(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2505
2506	IEM_MC_PREPARE_SSE_USAGE();
2507	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
2508	IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2509
2510	IEM_MC_ADVANCE_RIP();
2511	IEM_MC_END();
2512	}
2513	return VINF_SUCCESS;
2514	}
2515
2516
2517	/**
2518	* Common worker for SSE2 instructions on the forms:
2519	* pxxxx xmm1, xmm2/mem128
2520	*
2521	* The 2nd operand is the first half of a register, which in the memory case
2522	* means a 32-bit memory access for MMX and 128-bit aligned 64-bit or 128-bit
2523	* memory accessed for MMX.
2524	*
2525	* Exceptions type 4.
2526	*/
2527	FNIEMOP_DEF_1(iemOpCommonSse_LowLow_To_Full, PCIEMOPMEDIAF1L1, pImpl)
2528	{
2529	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2530	if (!pImpl->pfnU64)
2531	return IEMOP_RAISE_INVALID_OPCODE();
2532	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2533	{
2534	/*
2535	* Register, register.
2536	*/
2537	/** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
2538	/** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
2539	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2540	IEM_MC_BEGIN(2, 0);
2541	IEM_MC_ARG(uint64_t *, pDst, 0);
2542	IEM_MC_ARG(uint32_t const *, pSrc, 1);
2543	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
2544	IEM_MC_PREPARE_FPU_USAGE();
2545	IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
2546	IEM_MC_REF_MREG_U32_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
2547	IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
2548	IEM_MC_ADVANCE_RIP();
2549	IEM_MC_END();
2550	}
2551	else
2552	{
2553	/*
2554	* Register, memory.
2555	*/
2556	IEM_MC_BEGIN(2, 2);
2557	IEM_MC_ARG(uint64_t *, pDst, 0);
2558	IEM_MC_LOCAL(uint32_t, uSrc);
2559	IEM_MC_ARG_LOCAL_REF(uint32_t const *, pSrc, uSrc, 1);
2560	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2561
2562	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2563	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2564	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
2565	IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2566
2567	IEM_MC_PREPARE_FPU_USAGE();
2568	IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
2569	IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
2570
2571	IEM_MC_ADVANCE_RIP();
2572	IEM_MC_END();
2573	}
2574	return VINF_SUCCESS;
2575	}
2576
2577
2578	/** Opcode 0x0f 0x60 - punpcklbw Pq, Qd */
2579	FNIEMOP_DEF(iemOp_punpcklbw_Pq_Qd)
2580	{
2581	IEMOP_MNEMONIC(punpcklbw, "punpcklbw Pq, Qd");
2582	return FNIEMOP_CALL_1(iemOpCommonMmx_LowLow_To_Full, &g_iemAImpl_punpcklbw);
2583	}
2584
2585	/** Opcode 0x66 0x0f 0x60 - vpunpcklbw Vx, Hx, W */
2586	FNIEMOP_DEF(iemOp_vpunpcklbw_Vx_Hx_Wx)
2587	{
2588	IEMOP_MNEMONIC(vpunpcklbw, "vpunpcklbw Vx, Hx, Wx");
2589	return FNIEMOP_CALL_1(iemOpCommonMmx_LowLow_To_Full, &g_iemAImpl_punpcklbw);
2590	}
2591
2592	/* Opcode 0xf3 0x0f 0x60 - invalid */
2593
2594
2595	/** Opcode 0x0f 0x61 - punpcklwd Pq, Qd */
2596	FNIEMOP_DEF(iemOp_punpcklwd_Pq_Qd)
2597	{
2598	IEMOP_MNEMONIC(punpcklwd, "punpcklwd Pq, Qd"); /** @todo AMD mark the MMX version as 3DNow!. Intel says MMX CPUID req. */
2599	return FNIEMOP_CALL_1(iemOpCommonMmx_LowLow_To_Full, &g_iemAImpl_punpcklwd);
2600	}
2601
2602	/** Opcode 0x66 0x0f 0x61 - vpunpcklwd Vx, Hx, Wx */
2603	FNIEMOP_DEF(iemOp_vpunpcklwd_Vx_Hx_Wx)
2604	{
2605	IEMOP_MNEMONIC(vpunpcklwd, "vpunpcklwd Vx, Hx, Wx");
2606	return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklwd);
2607	}
2608
2609	/* Opcode 0xf3 0x0f 0x61 - invalid */
2610
2611
2612	/** Opcode 0x0f 0x62 - punpckldq Pq, Qd */
2613	FNIEMOP_DEF(iemOp_punpckldq_Pq_Qd)
2614	{
2615	IEMOP_MNEMONIC(punpckldq, "punpckldq Pq, Qd");
2616	return FNIEMOP_CALL_1(iemOpCommonMmx_LowLow_To_Full, &g_iemAImpl_punpckldq);
2617	}
2618
2619	/** Opcode 0x66 0x0f 0x62 - vpunpckldq Vx, Hx, Wx */
2620	FNIEMOP_DEF(iemOp_vpunpckldq_Vx_Hx_Wx)
2621	{
2622	IEMOP_MNEMONIC(vpunpckldq, "vpunpckldq Vx, Hx, Wx");
2623	return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpckldq);
2624	}
2625
2626	/* Opcode 0xf3 0x0f 0x62 - invalid */
2627
2628
2629
2630	/** Opcode 0x0f 0x63 - packsswb Pq, Qq */
2631	FNIEMOP_STUB(iemOp_packsswb_Pq_Qq);
2632	/** Opcode 0x66 0x0f 0x63 - vpacksswb Vx, Hx, Wx */
2633	FNIEMOP_STUB(iemOp_vpacksswb_Vx_Hx_Wx);
2634	/* Opcode 0xf3 0x0f 0x63 - invalid */
2635
2636	/** Opcode 0x0f 0x64 - pcmpgtb Pq, Qq */
2637	FNIEMOP_STUB(iemOp_pcmpgtb_Pq_Qq);
2638	/** Opcode 0x66 0x0f 0x64 - vpcmpgtb Vx, Hx, Wx */
2639	FNIEMOP_STUB(iemOp_vpcmpgtb_Vx_Hx_Wx);
2640	/* Opcode 0xf3 0x0f 0x64 - invalid */
2641
2642	/** Opcode 0x0f 0x65 - pcmpgtw Pq, Qq */
2643	FNIEMOP_STUB(iemOp_pcmpgtw_Pq_Qq);
2644	/** Opcode 0x66 0x0f 0x65 - vpcmpgtw Vx, Hx, Wx */
2645	FNIEMOP_STUB(iemOp_vpcmpgtw_Vx_Hx_Wx);
2646	/* Opcode 0xf3 0x0f 0x65 - invalid */
2647
2648	/** Opcode 0x0f 0x66 - pcmpgtd Pq, Qq */
2649	FNIEMOP_STUB(iemOp_pcmpgtd_Pq_Qq);
2650	/** Opcode 0x66 0x0f 0x66 - vpcmpgtd Vx, Hx, Wx */
2651	FNIEMOP_STUB(iemOp_vpcmpgtd_Vx_Hx_Wx);
2652	/* Opcode 0xf3 0x0f 0x66 - invalid */
2653
2654	/** Opcode 0x0f 0x67 - packuswb Pq, Qq */
2655	FNIEMOP_STUB(iemOp_packuswb_Pq_Qq);
2656	/** Opcode 0x66 0x0f 0x67 - vpackuswb Vx, Hx, W */
2657	FNIEMOP_STUB(iemOp_vpackuswb_Vx_Hx_W);
2658	/* Opcode 0xf3 0x0f 0x67 - invalid */
2659
2660
2661	/**
2662	* Common worker for MMX instructions on the form:
2663	* pxxxx mm1, mm2/mem64
2664	*
2665	* The 2nd operand is the second half of a register, which in the memory case
2666	* means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
2667	* where it may read the full 128 bits or only the upper 64 bits.
2668	*
2669	* Exceptions type 4.
2670	*/
2671	FNIEMOP_DEF_1(iemOpCommonMmx_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
2672	{
2673	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2674	AssertReturn(pImpl->pfnU64, IEMOP_RAISE_INVALID_OPCODE());
2675	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2676	{
2677	/*
2678	* Register, register.
2679	*/
2680	/** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
2681	/** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
2682	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2683	IEM_MC_BEGIN(2, 0);
2684	IEM_MC_ARG(uint64_t *, pDst, 0);
2685	IEM_MC_ARG(uint64_t const *, pSrc, 1);
2686	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
2687	IEM_MC_PREPARE_FPU_USAGE();
2688	IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
2689	IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
2690	IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
2691	IEM_MC_ADVANCE_RIP();
2692	IEM_MC_END();
2693	}
2694	else
2695	{
2696	/*
2697	* Register, memory.
2698	*/
2699	IEM_MC_BEGIN(2, 2);
2700	IEM_MC_ARG(uint64_t *, pDst, 0);
2701	IEM_MC_LOCAL(uint64_t, uSrc);
2702	IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
2703	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2704
2705	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2706	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2707	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
2708	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2709
2710	IEM_MC_PREPARE_FPU_USAGE();
2711	IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
2712	IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
2713
2714	IEM_MC_ADVANCE_RIP();
2715	IEM_MC_END();
2716	}
2717	return VINF_SUCCESS;
2718	}
2719
2720
2721	/**
2722	* Common worker for SSE2 instructions on the form:
2723	* pxxxx xmm1, xmm2/mem128
2724	*
2725	* The 2nd operand is the second half of a register, which in the memory case
2726	* means a 64-bit memory access for MMX, and for SSE a 128-bit aligned access
2727	* where it may read the full 128 bits or only the upper 64 bits.
2728	*
2729	* Exceptions type 4.
2730	*/
2731	FNIEMOP_DEF_1(iemOpCommonSse_HighHigh_To_Full, PCIEMOPMEDIAF1H1, pImpl)
2732	{
2733	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2734	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2735	{
2736	/*
2737	* Register, register.
2738	*/
2739	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2740	IEM_MC_BEGIN(2, 0);
2741	IEM_MC_ARG(PRTUINT128U, pDst, 0);
2742	IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
2743	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2744	IEM_MC_PREPARE_SSE_USAGE();
2745	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
2746	IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
2747	IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2748	IEM_MC_ADVANCE_RIP();
2749	IEM_MC_END();
2750	}
2751	else
2752	{
2753	/*
2754	* Register, memory.
2755	*/
2756	IEM_MC_BEGIN(2, 2);
2757	IEM_MC_ARG(PRTUINT128U, pDst, 0);
2758	IEM_MC_LOCAL(RTUINT128U, uSrc);
2759	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
2760	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2761
2762	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
2763	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2764	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2765	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); /* Most CPUs probably only right high qword */
2766
2767	IEM_MC_PREPARE_SSE_USAGE();
2768	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
2769	IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
2770
2771	IEM_MC_ADVANCE_RIP();
2772	IEM_MC_END();
2773	}
2774	return VINF_SUCCESS;
2775	}
2776
2777
2778	/** Opcode 0x0f 0x68 - punpckhbw Pq, Qd */
2779	FNIEMOP_DEF(iemOp_punpckhbw_Pq_Qd)
2780	{
2781	IEMOP_MNEMONIC(punpckhbw, "punpckhbw Pq, Qd");
2782	return FNIEMOP_CALL_1(iemOpCommonMmx_HighHigh_To_Full, &g_iemAImpl_punpckhbw);
2783	}
2784
2785	/** Opcode 0x66 0x0f 0x68 - vpunpckhbw Vx, Hx, Wx */
2786	FNIEMOP_DEF(iemOp_vpunpckhbw_Vx_Hx_Wx)
2787	{
2788	IEMOP_MNEMONIC(vpunpckhbw, "vpunpckhbw Vx, Hx, Wx");
2789	return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhbw);
2790	}
2791	/* Opcode 0xf3 0x0f 0x68 - invalid */
2792
2793
2794	/** Opcode 0x0f 0x69 - punpckhwd Pq, Qd */
2795	FNIEMOP_DEF(iemOp_punpckhwd_Pq_Qd)
2796	{
2797	IEMOP_MNEMONIC(punpckhwd, "punpckhwd Pq, Qd");
2798	return FNIEMOP_CALL_1(iemOpCommonMmx_HighHigh_To_Full, &g_iemAImpl_punpckhwd);
2799	}
2800
2801	/** Opcode 0x66 0x0f 0x69 - vpunpckhwd Vx, Hx, Wx */
2802	FNIEMOP_DEF(iemOp_vpunpckhwd_Vx_Hx_Wx)
2803	{
2804	IEMOP_MNEMONIC(vpunpckhwd, "vpunpckhwd Vx, Hx, Wx");
2805	return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhwd);
2806
2807	}
2808	/* Opcode 0xf3 0x0f 0x69 - invalid */
2809
2810
2811	/** Opcode 0x0f 0x6a - punpckhdq Pq, Qd */
2812	FNIEMOP_DEF(iemOp_punpckhdq_Pq_Qd)
2813	{
2814	IEMOP_MNEMONIC(punpckhdq, "punpckhdq Pq, Qd");
2815	return FNIEMOP_CALL_1(iemOpCommonMmx_HighHigh_To_Full, &g_iemAImpl_punpckhdq);
2816	}
2817
2818	/** Opcode 0x66 0x0f 0x6a - vpunpckhdq Vx, Hx, W */
2819	FNIEMOP_DEF(iemOp_vpunpckhdq_Vx_Hx_W)
2820	{
2821	IEMOP_MNEMONIC(vpunpckhdq, "vpunpckhdq Vx, Hx, W");
2822	return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhdq);
2823	}
2824	/* Opcode 0xf3 0x0f 0x6a - invalid */
2825
2826
2827	/** Opcode 0x0f 0x6b - packssdw Pq, Qd */
2828	FNIEMOP_STUB(iemOp_packssdw_Pq_Qd);
2829	/** Opcode 0x66 0x0f 0x6b - vpackssdw Vx, Hx, Wx */
2830	FNIEMOP_STUB(iemOp_vpackssdw_Vx_Hx_Wx);
2831	/* Opcode 0xf3 0x0f 0x6b - invalid */
2832
2833
2834	/* Opcode 0x0f 0x6c - invalid */
2835
2836	/** Opcode 0x66 0x0f 0x6c - vpunpcklqdq Vx, Hx, Wx */
2837	FNIEMOP_DEF(iemOp_vpunpcklqdq_Vx_Hx_Wx)
2838	{
2839	IEMOP_MNEMONIC(vpunpcklqdq, "vpunpcklqdq Vx, Hx, Wx");
2840	return FNIEMOP_CALL_1(iemOpCommonSse_LowLow_To_Full, &g_iemAImpl_punpcklqdq);
2841	}
2842
2843	/* Opcode 0xf3 0x0f 0x6c - invalid */
2844	/* Opcode 0xf2 0x0f 0x6c - invalid */
2845
2846
2847	/* Opcode 0x0f 0x6d - invalid */
2848
2849	/** Opcode 0x66 0x0f 0x6d - vpunpckhqdq Vx, Hx, W */
2850	FNIEMOP_DEF(iemOp_vpunpckhqdq_Vx_Hx_W)
2851	{
2852	IEMOP_MNEMONIC(punpckhqdq, "punpckhqdq");
2853	return FNIEMOP_CALL_1(iemOpCommonSse_HighHigh_To_Full, &g_iemAImpl_punpckhqdq);
2854	}
2855
2856	/* Opcode 0xf3 0x0f 0x6d - invalid */
2857
2858
2859	/** Opcode 0x0f 0x6e - movd/q Pd, Ey */
2860	FNIEMOP_DEF(iemOp_movd_q_Pd_Ey)
2861	{
2862	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2863	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2864	IEMOP_MNEMONIC(movq_Pq_Eq, "movq Pq,Eq");
2865	else
2866	IEMOP_MNEMONIC(movd_Pd_Ed, "movd Pd,Ed");
2867	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2868	{
2869	/* MMX, greg */
2870	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2871	IEM_MC_BEGIN(0, 1);
2872	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
2873	IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
2874	IEM_MC_LOCAL(uint64_t, u64Tmp);
2875	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2876	IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
2877	else
2878	IEM_MC_FETCH_GREG_U32_ZX_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
2879	IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp);
2880	IEM_MC_ADVANCE_RIP();
2881	IEM_MC_END();
2882	}
2883	else
2884	{
2885	/* MMX, [mem] */
2886	IEM_MC_BEGIN(0, 2);
2887	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2888	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
2889	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
2890	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2891	IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
2892	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2893	{
2894	IEM_MC_LOCAL(uint64_t, u64Tmp);
2895	IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2896	IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp);
2897	}
2898	else
2899	{
2900	IEM_MC_LOCAL(uint32_t, u32Tmp);
2901	IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2902	IEM_MC_STORE_MREG_U32_ZX_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u32Tmp);
2903	}
2904	IEM_MC_ADVANCE_RIP();
2905	IEM_MC_END();
2906	}
2907	return VINF_SUCCESS;
2908	}
2909
2910	/** Opcode 0x66 0x0f 0x6e - vmovd/q Vy, Ey */
2911	FNIEMOP_DEF(iemOp_vmovd_q_Vy_Ey)
2912	{
2913	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2914	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2915	IEMOP_MNEMONIC(vmovdq_Wq_Eq, "vmovq Wq,Eq");
2916	else
2917	IEMOP_MNEMONIC(vmovdq_Wd_Ed, "vmovd Wd,Ed");
2918	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2919	{
2920	/* XMM, greg*/
2921	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2922	IEM_MC_BEGIN(0, 1);
2923	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
2924	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2925	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2926	{
2927	IEM_MC_LOCAL(uint64_t, u64Tmp);
2928	IEM_MC_FETCH_GREG_U64(u64Tmp, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
2929	IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u64Tmp);
2930	}
2931	else
2932	{
2933	IEM_MC_LOCAL(uint32_t, u32Tmp);
2934	IEM_MC_FETCH_GREG_U32(u32Tmp, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
2935	IEM_MC_STORE_XREG_U32_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u32Tmp);
2936	}
2937	IEM_MC_ADVANCE_RIP();
2938	IEM_MC_END();
2939	}
2940	else
2941	{
2942	/* XMM, [mem] */
2943	IEM_MC_BEGIN(0, 2);
2944	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
2945	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); /** @todo order */
2946	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
2947	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2948	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
2949	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
2950	{
2951	IEM_MC_LOCAL(uint64_t, u64Tmp);
2952	IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2953	IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u64Tmp);
2954	}
2955	else
2956	{
2957	IEM_MC_LOCAL(uint32_t, u32Tmp);
2958	IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
2959	IEM_MC_STORE_XREG_U32_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u32Tmp);
2960	}
2961	IEM_MC_ADVANCE_RIP();
2962	IEM_MC_END();
2963	}
2964	return VINF_SUCCESS;
2965	}
2966
2967	/* Opcode 0xf3 0x0f 0x6e - invalid */
2968
2969
2970	/** Opcode 0x0f 0x6f - movq Pq, Qq */
2971	FNIEMOP_DEF(iemOp_movq_Pq_Qq)
2972	{
2973	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
2974	IEMOP_MNEMONIC(movq_Pq_Qq, "movq Pq,Qq");
2975	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
2976	{
2977	/*
2978	* Register, register.
2979	*/
2980	/** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
2981	/** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
2982	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
2983	IEM_MC_BEGIN(0, 1);
2984	IEM_MC_LOCAL(uint64_t, u64Tmp);
2985	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
2986	IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
2987	IEM_MC_FETCH_MREG_U64(u64Tmp, bRm & X86_MODRM_RM_MASK);
2988	IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp);
2989	IEM_MC_ADVANCE_RIP();
2990	IEM_MC_END();
2991	}
2992	else
2993	{
2994	/*
2995	* Register, memory.
2996	*/
2997	IEM_MC_BEGIN(0, 2);
2998	IEM_MC_LOCAL(uint64_t, u64Tmp);
2999	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3000
3001	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3002	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3003	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3004	IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
3005	IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3006	IEM_MC_STORE_MREG_U64((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK, u64Tmp);
3007
3008	IEM_MC_ADVANCE_RIP();
3009	IEM_MC_END();
3010	}
3011	return VINF_SUCCESS;
3012	}
3013
3014	/** Opcode 0x66 0x0f 0x6f - vmovdqa Vx, Wx */
3015	FNIEMOP_DEF(iemOp_vmovdqa_Vx_Wx)
3016	{
3017	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3018	IEMOP_MNEMONIC(movdqa_Vdq_Wdq, "movdqa Vdq,Wdq");
3019	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3020	{
3021	/*
3022	* Register, register.
3023	*/
3024	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3025	IEM_MC_BEGIN(0, 0);
3026	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3027	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3028	IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg,
3029	(bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
3030	IEM_MC_ADVANCE_RIP();
3031	IEM_MC_END();
3032	}
3033	else
3034	{
3035	/*
3036	* Register, memory.
3037	*/
3038	IEM_MC_BEGIN(0, 2);
3039	IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3040	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3041
3042	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3043	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3044	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3045	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3046	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3047	IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u128Tmp);
3048
3049	IEM_MC_ADVANCE_RIP();
3050	IEM_MC_END();
3051	}
3052	return VINF_SUCCESS;
3053	}
3054
3055	/** Opcode 0xf3 0x0f 0x6f - vmovdqu Vx, Wx */
3056	FNIEMOP_DEF(iemOp_vmovdqu_Vx_Wx)
3057	{
3058	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3059	IEMOP_MNEMONIC(movdqu_Vdq_Wdq, "movdqu Vdq,Wdq");
3060	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3061	{
3062	/*
3063	* Register, register.
3064	*/
3065	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3066	IEM_MC_BEGIN(0, 0);
3067	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3068	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3069	IEM_MC_COPY_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg,
3070	(bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
3071	IEM_MC_ADVANCE_RIP();
3072	IEM_MC_END();
3073	}
3074	else
3075	{
3076	/*
3077	* Register, memory.
3078	*/
3079	IEM_MC_BEGIN(0, 2);
3080	IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3081	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3082
3083	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3084	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3085	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3086	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3087	IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3088	IEM_MC_STORE_XREG_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u128Tmp);
3089
3090	IEM_MC_ADVANCE_RIP();
3091	IEM_MC_END();
3092	}
3093	return VINF_SUCCESS;
3094	}
3095
3096
3097	/** Opcode 0x0f 0x70 - pshufw Pq, Qq, Ib */
3098	FNIEMOP_DEF(iemOp_pshufw_Pq_Qq_Ib)
3099	{
3100	IEMOP_MNEMONIC(pshufw_Pq_Qq, "pshufw Pq,Qq,Ib");
3101	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3102	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3103	{
3104	/*
3105	* Register, register.
3106	*/
3107	uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3108	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3109
3110	IEM_MC_BEGIN(3, 0);
3111	IEM_MC_ARG(uint64_t *, pDst, 0);
3112	IEM_MC_ARG(uint64_t const *, pSrc, 1);
3113	IEM_MC_ARG_CONST(uint8_t, bEvilArg, /=/ bEvil, 2);
3114	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT();
3115	IEM_MC_PREPARE_FPU_USAGE();
3116	IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3117	IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
3118	IEM_MC_CALL_MMX_AIMPL_3(iemAImpl_pshufw, pDst, pSrc, bEvilArg);
3119	IEM_MC_ADVANCE_RIP();
3120	IEM_MC_END();
3121	}
3122	else
3123	{
3124	/*
3125	* Register, memory.
3126	*/
3127	IEM_MC_BEGIN(3, 2);
3128	IEM_MC_ARG(uint64_t *, pDst, 0);
3129	IEM_MC_LOCAL(uint64_t, uSrc);
3130	IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
3131	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3132
3133	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3134	uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3135	IEM_MC_ARG_CONST(uint8_t, bEvilArg, /=/ bEvil, 2);
3136	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3137	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT();
3138
3139	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3140	IEM_MC_PREPARE_FPU_USAGE();
3141	IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3142	IEM_MC_CALL_MMX_AIMPL_3(iemAImpl_pshufw, pDst, pSrc, bEvilArg);
3143
3144	IEM_MC_ADVANCE_RIP();
3145	IEM_MC_END();
3146	}
3147	return VINF_SUCCESS;
3148	}
3149
3150	/** Opcode 0x66 0x0f 0x70 - vpshufd Vx, Wx, Ib */
3151	FNIEMOP_DEF(iemOp_vpshufd_Vx_Wx_Ib)
3152	{
3153	IEMOP_MNEMONIC(vpshufd_Vx_Wx_Ib, "vpshufd Vx,Wx,Ib");
3154	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3155	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3156	{
3157	/*
3158	* Register, register.
3159	*/
3160	uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3161	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3162
3163	IEM_MC_BEGIN(3, 0);
3164	IEM_MC_ARG(PRTUINT128U, pDst, 0);
3165	IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
3166	IEM_MC_ARG_CONST(uint8_t, bEvilArg, /=/ bEvil, 2);
3167	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3168	IEM_MC_PREPARE_SSE_USAGE();
3169	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3170	IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
3171	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufd, pDst, pSrc, bEvilArg);
3172	IEM_MC_ADVANCE_RIP();
3173	IEM_MC_END();
3174	}
3175	else
3176	{
3177	/*
3178	* Register, memory.
3179	*/
3180	IEM_MC_BEGIN(3, 2);
3181	IEM_MC_ARG(PRTUINT128U, pDst, 0);
3182	IEM_MC_LOCAL(RTUINT128U, uSrc);
3183	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
3184	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3185
3186	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3187	uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3188	IEM_MC_ARG_CONST(uint8_t, bEvilArg, /=/ bEvil, 2);
3189	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3190	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3191
3192	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3193	IEM_MC_PREPARE_SSE_USAGE();
3194	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3195	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufd, pDst, pSrc, bEvilArg);
3196
3197	IEM_MC_ADVANCE_RIP();
3198	IEM_MC_END();
3199	}
3200	return VINF_SUCCESS;
3201	}
3202
3203	/** Opcode 0xf3 0x0f 0x70 - vpshufhw Vx, Wx, Ib */
3204	FNIEMOP_DEF(iemOp_vpshufhw_Vx_Wx_Ib)
3205	{
3206	IEMOP_MNEMONIC(vpshufhw_Vx_Wx_Ib, "vpshufhw Vx,Wx,Ib");
3207	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3208	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3209	{
3210	/*
3211	* Register, register.
3212	*/
3213	uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3214	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3215
3216	IEM_MC_BEGIN(3, 0);
3217	IEM_MC_ARG(PRTUINT128U, pDst, 0);
3218	IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
3219	IEM_MC_ARG_CONST(uint8_t, bEvilArg, /=/ bEvil, 2);
3220	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3221	IEM_MC_PREPARE_SSE_USAGE();
3222	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3223	IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
3224	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufhw, pDst, pSrc, bEvilArg);
3225	IEM_MC_ADVANCE_RIP();
3226	IEM_MC_END();
3227	}
3228	else
3229	{
3230	/*
3231	* Register, memory.
3232	*/
3233	IEM_MC_BEGIN(3, 2);
3234	IEM_MC_ARG(PRTUINT128U, pDst, 0);
3235	IEM_MC_LOCAL(RTUINT128U, uSrc);
3236	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
3237	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3238
3239	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3240	uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3241	IEM_MC_ARG_CONST(uint8_t, bEvilArg, /=/ bEvil, 2);
3242	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3243	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3244
3245	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3246	IEM_MC_PREPARE_SSE_USAGE();
3247	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3248	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshufhw, pDst, pSrc, bEvilArg);
3249
3250	IEM_MC_ADVANCE_RIP();
3251	IEM_MC_END();
3252	}
3253	return VINF_SUCCESS;
3254	}
3255
3256	/** Opcode 0xf2 0x0f 0x70 - vpshuflw Vx, Wx, Ib */
3257	FNIEMOP_DEF(iemOp_vpshuflw_Vx_Wx_Ib)
3258	{
3259	IEMOP_MNEMONIC(vpshuflw_Vx_Wx_Ib, "vpshuflw Vx,Wx,Ib");
3260	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3261	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3262	{
3263	/*
3264	* Register, register.
3265	*/
3266	uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3267	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3268
3269	IEM_MC_BEGIN(3, 0);
3270	IEM_MC_ARG(PRTUINT128U, pDst, 0);
3271	IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
3272	IEM_MC_ARG_CONST(uint8_t, bEvilArg, /=/ bEvil, 2);
3273	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3274	IEM_MC_PREPARE_SSE_USAGE();
3275	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3276	IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
3277	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshuflw, pDst, pSrc, bEvilArg);
3278	IEM_MC_ADVANCE_RIP();
3279	IEM_MC_END();
3280	}
3281	else
3282	{
3283	/*
3284	* Register, memory.
3285	*/
3286	IEM_MC_BEGIN(3, 2);
3287	IEM_MC_ARG(PRTUINT128U, pDst, 0);
3288	IEM_MC_LOCAL(RTUINT128U, uSrc);
3289	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
3290	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3291
3292	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3293	uint8_t bEvil; IEM_OPCODE_GET_NEXT_U8(&bEvil);
3294	IEM_MC_ARG_CONST(uint8_t, bEvilArg, /=/ bEvil, 2);
3295	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3296	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3297
3298	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3299	IEM_MC_PREPARE_SSE_USAGE();
3300	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3301	IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_pshuflw, pDst, pSrc, bEvilArg);
3302
3303	IEM_MC_ADVANCE_RIP();
3304	IEM_MC_END();
3305	}
3306	return VINF_SUCCESS;
3307	}
3308
3309
3310	/** Opcode 0x0f 0x71 11/2. */
3311	FNIEMOP_STUB_1(iemOp_Grp12_psrlw_Nq_Ib, uint8_t, bRm);
3312
3313	/** Opcode 0x66 0x0f 0x71 11/2. */
3314	FNIEMOP_STUB_1(iemOp_Grp12_vpsrlw_Hx_Ux_Ib, uint8_t, bRm);
3315
3316	/** Opcode 0x0f 0x71 11/4. */
3317	FNIEMOP_STUB_1(iemOp_Grp12_psraw_Nq_Ib, uint8_t, bRm);
3318
3319	/** Opcode 0x66 0x0f 0x71 11/4. */
3320	FNIEMOP_STUB_1(iemOp_Grp12_vpsraw_Hx_Ux_Ib, uint8_t, bRm);
3321
3322	/** Opcode 0x0f 0x71 11/6. */
3323	FNIEMOP_STUB_1(iemOp_Grp12_psllw_Nq_Ib, uint8_t, bRm);
3324
3325	/** Opcode 0x66 0x0f 0x71 11/6. */
3326	FNIEMOP_STUB_1(iemOp_Grp12_vpsllw_Hx_Ux_Ib, uint8_t, bRm);
3327
3328
3329	/**
3330	* Group 12 jump table for register variant.
3331	*/
3332	IEM_STATIC const PFNIEMOPRM g_apfnGroup12RegReg[] =
3333	{
3334	/* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3335	/* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3336	/* /2 */ iemOp_Grp12_psrlw_Nq_Ib, iemOp_Grp12_vpsrlw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3337	/* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3338	/* /4 */ iemOp_Grp12_psraw_Nq_Ib, iemOp_Grp12_vpsraw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3339	/* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3340	/* /6 */ iemOp_Grp12_psllw_Nq_Ib, iemOp_Grp12_vpsllw_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3341	/* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3342	};
3343	AssertCompile(RT_ELEMENTS(g_apfnGroup12RegReg) == 8*4);
3344
3345
3346	/** Opcode 0x0f 0x71. */
3347	FNIEMOP_DEF(iemOp_Grp12)
3348	{
3349	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3350	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3351	/* register, register */
3352	return FNIEMOP_CALL_1(g_apfnGroup12RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
3353	+ pVCpu->iem.s.idxPrefix], bRm);
3354	return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3355	}
3356
3357
3358	/** Opcode 0x0f 0x72 11/2. */
3359	FNIEMOP_STUB_1(iemOp_Grp13_psrld_Nq_Ib, uint8_t, bRm);
3360
3361	/** Opcode 0x66 0x0f 0x72 11/2. */
3362	FNIEMOP_STUB_1(iemOp_Grp13_vpsrld_Hx_Ux_Ib, uint8_t, bRm);
3363
3364	/** Opcode 0x0f 0x72 11/4. */
3365	FNIEMOP_STUB_1(iemOp_Grp13_psrad_Nq_Ib, uint8_t, bRm);
3366
3367	/** Opcode 0x66 0x0f 0x72 11/4. */
3368	FNIEMOP_STUB_1(iemOp_Grp13_vpsrad_Hx_Ux_Ib, uint8_t, bRm);
3369
3370	/** Opcode 0x0f 0x72 11/6. */
3371	FNIEMOP_STUB_1(iemOp_Grp13_pslld_Nq_Ib, uint8_t, bRm);
3372
3373	/** Opcode 0x66 0x0f 0x72 11/6. */
3374	FNIEMOP_STUB_1(iemOp_Grp13_vpslld_Hx_Ux_Ib, uint8_t, bRm);
3375
3376
3377	/**
3378	* Group 13 jump table for register variant.
3379	*/
3380	IEM_STATIC const PFNIEMOPRM g_apfnGroup13RegReg[] =
3381	{
3382	/* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3383	/* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3384	/* /2 */ iemOp_Grp13_psrld_Nq_Ib, iemOp_Grp13_vpsrld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3385	/* /3 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3386	/* /4 */ iemOp_Grp13_psrad_Nq_Ib, iemOp_Grp13_vpsrad_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3387	/* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3388	/* /6 */ iemOp_Grp13_pslld_Nq_Ib, iemOp_Grp13_vpslld_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3389	/* /7 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8)
3390	};
3391	AssertCompile(RT_ELEMENTS(g_apfnGroup13RegReg) == 8*4);
3392
3393	/** Opcode 0x0f 0x72. */
3394	FNIEMOP_DEF(iemOp_Grp13)
3395	{
3396	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3397	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3398	/* register, register */
3399	return FNIEMOP_CALL_1(g_apfnGroup13RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
3400	+ pVCpu->iem.s.idxPrefix], bRm);
3401	return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3402	}
3403
3404
3405	/** Opcode 0x0f 0x73 11/2. */
3406	FNIEMOP_STUB_1(iemOp_Grp14_psrlq_Nq_Ib, uint8_t, bRm);
3407
3408	/** Opcode 0x66 0x0f 0x73 11/2. */
3409	FNIEMOP_STUB_1(iemOp_Grp14_vpsrlq_Hx_Ux_Ib, uint8_t, bRm);
3410
3411	/** Opcode 0x66 0x0f 0x73 11/3. */
3412	FNIEMOP_STUB_1(iemOp_Grp14_vpsrldq_Hx_Ux_Ib, uint8_t, bRm); //NEXT
3413
3414	/** Opcode 0x0f 0x73 11/6. */
3415	FNIEMOP_STUB_1(iemOp_Grp14_psllq_Nq_Ib, uint8_t, bRm);
3416
3417	/** Opcode 0x66 0x0f 0x73 11/6. */
3418	FNIEMOP_STUB_1(iemOp_Grp14_vpsllq_Hx_Ux_Ib, uint8_t, bRm);
3419
3420	/** Opcode 0x66 0x0f 0x73 11/7. */
3421	FNIEMOP_STUB_1(iemOp_Grp14_vpslldq_Hx_Ux_Ib, uint8_t, bRm); //NEXT
3422
3423	/**
3424	* Group 14 jump table for register variant.
3425	*/
3426	IEM_STATIC const PFNIEMOPRM g_apfnGroup14RegReg[] =
3427	{
3428	/* /0 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3429	/* /1 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3430	/* /2 */ iemOp_Grp14_psrlq_Nq_Ib, iemOp_Grp14_vpsrlq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3431	/* /3 */ iemOp_InvalidWithRMNeedImm8, iemOp_Grp14_vpsrldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3432	/* /4 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3433	/* /5 */ IEMOP_X4(iemOp_InvalidWithRMNeedImm8),
3434	/* /6 */ iemOp_Grp14_psllq_Nq_Ib, iemOp_Grp14_vpsllq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3435	/* /7 */ iemOp_InvalidWithRMNeedImm8, iemOp_Grp14_vpslldq_Hx_Ux_Ib, iemOp_InvalidWithRMNeedImm8, iemOp_InvalidWithRMNeedImm8,
3436	};
3437	AssertCompile(RT_ELEMENTS(g_apfnGroup14RegReg) == 8*4);
3438
3439
3440	/** Opcode 0x0f 0x73. */
3441	FNIEMOP_DEF(iemOp_Grp14)
3442	{
3443	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3444	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3445	/* register, register */
3446	return FNIEMOP_CALL_1(g_apfnGroup14RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
3447	+ pVCpu->iem.s.idxPrefix], bRm);
3448	return FNIEMOP_CALL_1(iemOp_InvalidWithRMNeedImm8, bRm);
3449	}
3450
3451
3452	/**
3453	* Common worker for MMX instructions on the form:
3454	* pxxx mm1, mm2/mem64
3455	*/
3456	FNIEMOP_DEF_1(iemOpCommonMmx_FullFull_To_Full, PCIEMOPMEDIAF2, pImpl)
3457	{
3458	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3459	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3460	{
3461	/*
3462	* Register, register.
3463	*/
3464	/** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
3465	/** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
3466	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3467	IEM_MC_BEGIN(2, 0);
3468	IEM_MC_ARG(uint64_t *, pDst, 0);
3469	IEM_MC_ARG(uint64_t const *, pSrc, 1);
3470	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3471	IEM_MC_PREPARE_FPU_USAGE();
3472	IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3473	IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
3474	IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
3475	IEM_MC_ADVANCE_RIP();
3476	IEM_MC_END();
3477	}
3478	else
3479	{
3480	/*
3481	* Register, memory.
3482	*/
3483	IEM_MC_BEGIN(2, 2);
3484	IEM_MC_ARG(uint64_t *, pDst, 0);
3485	IEM_MC_LOCAL(uint64_t, uSrc);
3486	IEM_MC_ARG_LOCAL_REF(uint64_t const *, pSrc, uSrc, 1);
3487	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3488
3489	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3490	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3491	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3492	IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3493
3494	IEM_MC_PREPARE_FPU_USAGE();
3495	IEM_MC_REF_MREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3496	IEM_MC_CALL_MMX_AIMPL_2(pImpl->pfnU64, pDst, pSrc);
3497
3498	IEM_MC_ADVANCE_RIP();
3499	IEM_MC_END();
3500	}
3501	return VINF_SUCCESS;
3502	}
3503
3504
3505	/**
3506	* Common worker for SSE2 instructions on the forms:
3507	* pxxx xmm1, xmm2/mem128
3508	*
3509	* Proper alignment of the 128-bit operand is enforced.
3510	* Exceptions type 4. SSE2 cpuid checks.
3511	*/
3512	FNIEMOP_DEF_1(iemOpCommonSse2_FullFull_To_Full, PCIEMOPMEDIAF2, pImpl)
3513	{
3514	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3515	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3516	{
3517	/*
3518	* Register, register.
3519	*/
3520	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3521	IEM_MC_BEGIN(2, 0);
3522	IEM_MC_ARG(PRTUINT128U, pDst, 0);
3523	IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
3524	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3525	IEM_MC_PREPARE_SSE_USAGE();
3526	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3527	IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
3528	IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3529	IEM_MC_ADVANCE_RIP();
3530	IEM_MC_END();
3531	}
3532	else
3533	{
3534	/*
3535	* Register, memory.
3536	*/
3537	IEM_MC_BEGIN(2, 2);
3538	IEM_MC_ARG(PRTUINT128U, pDst, 0);
3539	IEM_MC_LOCAL(RTUINT128U, uSrc);
3540	IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, pSrc, uSrc, 1);
3541	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3542
3543	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3544	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3545	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3546	IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
3547
3548	IEM_MC_PREPARE_SSE_USAGE();
3549	IEM_MC_REF_XREG_U128(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3550	IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc);
3551
3552	IEM_MC_ADVANCE_RIP();
3553	IEM_MC_END();
3554	}
3555	return VINF_SUCCESS;
3556	}
3557
3558
3559	/** Opcode 0x0f 0x74 - pcmpeqb Pq, Qq */
3560	FNIEMOP_DEF(iemOp_pcmpeqb_Pq_Qq)
3561	{
3562	IEMOP_MNEMONIC(pcmpeqb, "pcmpeqb");
3563	return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full, &g_iemAImpl_pcmpeqb);
3564	}
3565
3566	/** Opcode 0x66 0x0f 0x74 - vpcmpeqb Vx, Hx, Wx */
3567	FNIEMOP_DEF(iemOp_vpcmpeqb_Vx_Hx_Wx)
3568	{
3569	IEMOP_MNEMONIC(vpcmpeqb, "vpcmpeqb");
3570	return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqb);
3571	}
3572
3573	/* Opcode 0xf3 0x0f 0x74 - invalid */
3574	/* Opcode 0xf2 0x0f 0x74 - invalid */
3575
3576
3577	/** Opcode 0x0f 0x75 - pcmpeqw Pq, Qq */
3578	FNIEMOP_DEF(iemOp_pcmpeqw_Pq_Qq)
3579	{
3580	IEMOP_MNEMONIC(pcmpeqw, "pcmpeqw");
3581	return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full, &g_iemAImpl_pcmpeqw);
3582	}
3583
3584	/** Opcode 0x66 0x0f 0x75 - vpcmpeqw Vx, Hx, Wx */
3585	FNIEMOP_DEF(iemOp_vpcmpeqw_Vx_Hx_Wx)
3586	{
3587	IEMOP_MNEMONIC(vpcmpeqw, "vpcmpeqw");
3588	return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqw);
3589	}
3590
3591	/* Opcode 0xf3 0x0f 0x75 - invalid */
3592	/* Opcode 0xf2 0x0f 0x75 - invalid */
3593
3594
3595	/** Opcode 0x0f 0x76 - pcmpeqd Pq, Qq */
3596	FNIEMOP_DEF(iemOp_pcmpeqd_Pq_Qq)
3597	{
3598	IEMOP_MNEMONIC(pcmpeqd, "pcmpeqd");
3599	return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full, &g_iemAImpl_pcmpeqd);
3600	}
3601
3602	/** Opcode 0x66 0x0f 0x76 - vpcmpeqd Vx, Hx, Wx */
3603	FNIEMOP_DEF(iemOp_vpcmpeqd_Vx_Hx_Wx)
3604	{
3605	IEMOP_MNEMONIC(vpcmpeqd, "vpcmpeqd");
3606	return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pcmpeqd);
3607	}
3608
3609	/* Opcode 0xf3 0x0f 0x76 - invalid */
3610	/* Opcode 0xf2 0x0f 0x76 - invalid */
3611
3612
3613	/** Opcode 0x0f 0x77 - emms vzeroupperv vzeroallv */
3614	FNIEMOP_STUB(iemOp_emms__vzeroupperv__vzeroallv);
3615	/* Opcode 0x66 0x0f 0x77 - invalid */
3616	/* Opcode 0xf3 0x0f 0x77 - invalid */
3617	/* Opcode 0xf2 0x0f 0x77 - invalid */
3618
3619	/** Opcode 0x0f 0x78 - VMREAD Ey, Gy */
3620	FNIEMOP_STUB(iemOp_vmread_Ey_Gy);
3621	/* Opcode 0x66 0x0f 0x78 - AMD Group 17 */
3622	FNIEMOP_STUB(iemOp_AmdGrp17);
3623	/* Opcode 0xf3 0x0f 0x78 - invalid */
3624	/* Opcode 0xf2 0x0f 0x78 - invalid */
3625
3626	/** Opcode 0x0f 0x79 - VMWRITE Gy, Ey */
3627	FNIEMOP_STUB(iemOp_vmwrite_Gy_Ey);
3628	/* Opcode 0x66 0x0f 0x79 - invalid */
3629	/* Opcode 0xf3 0x0f 0x79 - invalid */
3630	/* Opcode 0xf2 0x0f 0x79 - invalid */
3631
3632	/* Opcode 0x0f 0x7a - invalid */
3633	/* Opcode 0x66 0x0f 0x7a - invalid */
3634	/* Opcode 0xf3 0x0f 0x7a - invalid */
3635	/* Opcode 0xf2 0x0f 0x7a - invalid */
3636
3637	/* Opcode 0x0f 0x7b - invalid */
3638	/* Opcode 0x66 0x0f 0x7b - invalid */
3639	/* Opcode 0xf3 0x0f 0x7b - invalid */
3640	/* Opcode 0xf2 0x0f 0x7b - invalid */
3641
3642	/* Opcode 0x0f 0x7c - invalid */
3643	/** Opcode 0x66 0x0f 0x7c - vhaddpd Vpd, Hpd, Wpd */
3644	FNIEMOP_STUB(iemOp_vhaddpd_Vpd_Hpd_Wpd);
3645	/* Opcode 0xf3 0x0f 0x7c - invalid */
3646	/** Opcode 0xf2 0x0f 0x7c - vhaddps Vps, Hps, Wps */
3647	FNIEMOP_STUB(iemOp_vhaddps_Vps_Hps_Wps);
3648
3649	/* Opcode 0x0f 0x7d - invalid */
3650	/** Opcode 0x66 0x0f 0x7d - vhsubpd Vpd, Hpd, Wpd */
3651	FNIEMOP_STUB(iemOp_vhsubpd_Vpd_Hpd_Wpd);
3652	/* Opcode 0xf3 0x0f 0x7d - invalid */
3653	/** Opcode 0xf2 0x0f 0x7d - vhsubps Vps, Hps, Wps */
3654	FNIEMOP_STUB(iemOp_vhsubps_Vps_Hps_Wps);
3655
3656
3657	/** Opcode 0x0f 0x7e - movd_q Ey, Pd */
3658	FNIEMOP_DEF(iemOp_movd_q_Ey_Pd)
3659	{
3660	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3661	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3662	IEMOP_MNEMONIC(movq_Eq_Pq, "movq Eq,Pq");
3663	else
3664	IEMOP_MNEMONIC(movd_Ed_Pd, "movd Ed,Pd");
3665	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3666	{
3667	/* greg, MMX */
3668	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3669	IEM_MC_BEGIN(0, 1);
3670	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3671	IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
3672	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3673	{
3674	IEM_MC_LOCAL(uint64_t, u64Tmp);
3675	IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3676	IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, u64Tmp);
3677	}
3678	else
3679	{
3680	IEM_MC_LOCAL(uint32_t, u32Tmp);
3681	IEM_MC_FETCH_MREG_U32(u32Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3682	IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, u32Tmp);
3683	}
3684	IEM_MC_ADVANCE_RIP();
3685	IEM_MC_END();
3686	}
3687	else
3688	{
3689	/* [mem], MMX */
3690	IEM_MC_BEGIN(0, 2);
3691	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3692	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3693	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
3694	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3695	IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
3696	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3697	{
3698	IEM_MC_LOCAL(uint64_t, u64Tmp);
3699	IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3700	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
3701	}
3702	else
3703	{
3704	IEM_MC_LOCAL(uint32_t, u32Tmp);
3705	IEM_MC_FETCH_MREG_U32(u32Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3706	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
3707	}
3708	IEM_MC_ADVANCE_RIP();
3709	IEM_MC_END();
3710	}
3711	return VINF_SUCCESS;
3712	}
3713
3714	/** Opcode 0x66 0x0f 0x7e - vmovd_q Ey, Vy */
3715	FNIEMOP_DEF(iemOp_vmovd_q_Ey_Vy)
3716	{
3717	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3718	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3719	IEMOP_MNEMONIC(vmovq_Eq_Wq, "vmovq Eq,Wq");
3720	else
3721	IEMOP_MNEMONIC(vmovd_Ed_Wd, "vmovd Ed,Wd");
3722	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3723	{
3724	/* greg, XMM */
3725	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3726	IEM_MC_BEGIN(0, 1);
3727	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3728	IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
3729	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3730	{
3731	IEM_MC_LOCAL(uint64_t, u64Tmp);
3732	IEM_MC_FETCH_XREG_U64(u64Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3733	IEM_MC_STORE_GREG_U64((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, u64Tmp);
3734	}
3735	else
3736	{
3737	IEM_MC_LOCAL(uint32_t, u32Tmp);
3738	IEM_MC_FETCH_XREG_U32(u32Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3739	IEM_MC_STORE_GREG_U32((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, u32Tmp);
3740	}
3741	IEM_MC_ADVANCE_RIP();
3742	IEM_MC_END();
3743	}
3744	else
3745	{
3746	/* [mem], XMM */
3747	IEM_MC_BEGIN(0, 2);
3748	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3749	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3750	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 1);
3751	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3752	IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
3753	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
3754	{
3755	IEM_MC_LOCAL(uint64_t, u64Tmp);
3756	IEM_MC_FETCH_XREG_U64(u64Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3757	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
3758	}
3759	else
3760	{
3761	IEM_MC_LOCAL(uint32_t, u32Tmp);
3762	IEM_MC_FETCH_XREG_U32(u32Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3763	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp);
3764	}
3765	IEM_MC_ADVANCE_RIP();
3766	IEM_MC_END();
3767	}
3768	return VINF_SUCCESS;
3769	}
3770
3771	/** Opcode 0xf3 0x0f 0x7e - vmovq Vq, Wq */
3772	FNIEMOP_STUB(iemOp_vmovq_Vq_Wq);
3773	/* Opcode 0xf2 0x0f 0x7e - invalid */
3774
3775
3776	/** Opcode 0x0f 0x7f - movq Qq, Pq */
3777	FNIEMOP_DEF(iemOp_movq_Qq_Pq)
3778	{
3779	IEMOP_MNEMONIC(movq_Qq_Pq, "movq Qq,Pq");
3780	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3781	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3782	{
3783	/*
3784	* Register, register.
3785	*/
3786	/** @todo testcase: REX.B / REX.R and MMX register indexing. Ignored? */
3787	/** @todo testcase: REX.B / REX.R and segment register indexing. Ignored? */
3788	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3789	IEM_MC_BEGIN(0, 1);
3790	IEM_MC_LOCAL(uint64_t, u64Tmp);
3791	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3792	IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE();
3793	IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3794	IEM_MC_STORE_MREG_U64(bRm & X86_MODRM_RM_MASK, u64Tmp);
3795	IEM_MC_ADVANCE_RIP();
3796	IEM_MC_END();
3797	}
3798	else
3799	{
3800	/*
3801	* Register, memory.
3802	*/
3803	IEM_MC_BEGIN(0, 2);
3804	IEM_MC_LOCAL(uint64_t, u64Tmp);
3805	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3806
3807	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3808	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3809	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
3810	IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
3811
3812	IEM_MC_FETCH_MREG_U64(u64Tmp, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
3813	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp);
3814
3815	IEM_MC_ADVANCE_RIP();
3816	IEM_MC_END();
3817	}
3818	return VINF_SUCCESS;
3819	}
3820
3821	/** Opcode 0x66 0x0f 0x7f - vmovdqa Wx,Vx */
3822	FNIEMOP_DEF(iemOp_vmovdqa_Wx_Vx)
3823	{
3824	IEMOP_MNEMONIC(vmovdqa_Wdq_Vdq, "vmovdqa Wx,Vx");
3825	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3826	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3827	{
3828	/*
3829	* Register, register.
3830	*/
3831	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3832	IEM_MC_BEGIN(0, 0);
3833	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3834	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3835	IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB,
3836	((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3837	IEM_MC_ADVANCE_RIP();
3838	IEM_MC_END();
3839	}
3840	else
3841	{
3842	/*
3843	* Register, memory.
3844	*/
3845	IEM_MC_BEGIN(0, 2);
3846	IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3847	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3848
3849	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3850	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3851	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3852	IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
3853
3854	IEM_MC_FETCH_XREG_U128(u128Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3855	IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
3856
3857	IEM_MC_ADVANCE_RIP();
3858	IEM_MC_END();
3859	}
3860	return VINF_SUCCESS;
3861	}
3862
3863	/** Opcode 0xf3 0x0f 0x7f - vmovdqu Wx,Vx */
3864	FNIEMOP_DEF(iemOp_vmovdqu_Wx_Vx)
3865	{
3866	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
3867	IEMOP_MNEMONIC(vmovdqu_Wdq_Vdq, "vmovdqu Wx,Vx");
3868	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
3869	{
3870	/*
3871	* Register, register.
3872	*/
3873	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3874	IEM_MC_BEGIN(0, 0);
3875	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3876	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
3877	IEM_MC_COPY_XREG_U128((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB,
3878	((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3879	IEM_MC_ADVANCE_RIP();
3880	IEM_MC_END();
3881	}
3882	else
3883	{
3884	/*
3885	* Register, memory.
3886	*/
3887	IEM_MC_BEGIN(0, 2);
3888	IEM_MC_LOCAL(RTUINT128U, u128Tmp);
3889	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
3890
3891	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
3892	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3893	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
3894	IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
3895
3896	IEM_MC_FETCH_XREG_U128(u128Tmp, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
3897	IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp);
3898
3899	IEM_MC_ADVANCE_RIP();
3900	IEM_MC_END();
3901	}
3902	return VINF_SUCCESS;
3903	}
3904
3905	/* Opcode 0xf2 0x0f 0x7f - invalid */
3906
3907
3908
3909	/** Opcode 0x0f 0x80. */
3910	FNIEMOP_DEF(iemOp_jo_Jv)
3911	{
3912	IEMOP_MNEMONIC(jo_Jv, "jo Jv");
3913	IEMOP_HLP_MIN_386();
3914	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
3915	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
3916	{
3917	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
3918	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3919
3920	IEM_MC_BEGIN(0, 0);
3921	IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
3922	IEM_MC_REL_JMP_S16(i16Imm);
3923	} IEM_MC_ELSE() {
3924	IEM_MC_ADVANCE_RIP();
3925	} IEM_MC_ENDIF();
3926	IEM_MC_END();
3927	}
3928	else
3929	{
3930	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
3931	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3932
3933	IEM_MC_BEGIN(0, 0);
3934	IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
3935	IEM_MC_REL_JMP_S32(i32Imm);
3936	} IEM_MC_ELSE() {
3937	IEM_MC_ADVANCE_RIP();
3938	} IEM_MC_ENDIF();
3939	IEM_MC_END();
3940	}
3941	return VINF_SUCCESS;
3942	}
3943
3944
3945	/** Opcode 0x0f 0x81. */
3946	FNIEMOP_DEF(iemOp_jno_Jv)
3947	{
3948	IEMOP_MNEMONIC(jno_Jv, "jno Jv");
3949	IEMOP_HLP_MIN_386();
3950	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
3951	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
3952	{
3953	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
3954	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3955
3956	IEM_MC_BEGIN(0, 0);
3957	IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
3958	IEM_MC_ADVANCE_RIP();
3959	} IEM_MC_ELSE() {
3960	IEM_MC_REL_JMP_S16(i16Imm);
3961	} IEM_MC_ENDIF();
3962	IEM_MC_END();
3963	}
3964	else
3965	{
3966	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
3967	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3968
3969	IEM_MC_BEGIN(0, 0);
3970	IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
3971	IEM_MC_ADVANCE_RIP();
3972	} IEM_MC_ELSE() {
3973	IEM_MC_REL_JMP_S32(i32Imm);
3974	} IEM_MC_ENDIF();
3975	IEM_MC_END();
3976	}
3977	return VINF_SUCCESS;
3978	}
3979
3980
3981	/** Opcode 0x0f 0x82. */
3982	FNIEMOP_DEF(iemOp_jc_Jv)
3983	{
3984	IEMOP_MNEMONIC(jc_Jv, "jc/jb/jnae Jv");
3985	IEMOP_HLP_MIN_386();
3986	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
3987	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
3988	{
3989	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
3990	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
3991
3992	IEM_MC_BEGIN(0, 0);
3993	IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
3994	IEM_MC_REL_JMP_S16(i16Imm);
3995	} IEM_MC_ELSE() {
3996	IEM_MC_ADVANCE_RIP();
3997	} IEM_MC_ENDIF();
3998	IEM_MC_END();
3999	}
4000	else
4001	{
4002	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4003	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4004
4005	IEM_MC_BEGIN(0, 0);
4006	IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
4007	IEM_MC_REL_JMP_S32(i32Imm);
4008	} IEM_MC_ELSE() {
4009	IEM_MC_ADVANCE_RIP();
4010	} IEM_MC_ENDIF();
4011	IEM_MC_END();
4012	}
4013	return VINF_SUCCESS;
4014	}
4015
4016
4017	/** Opcode 0x0f 0x83. */
4018	FNIEMOP_DEF(iemOp_jnc_Jv)
4019	{
4020	IEMOP_MNEMONIC(jnc_Jv, "jnc/jnb/jae Jv");
4021	IEMOP_HLP_MIN_386();
4022	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4023	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4024	{
4025	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4026	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4027
4028	IEM_MC_BEGIN(0, 0);
4029	IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
4030	IEM_MC_ADVANCE_RIP();
4031	} IEM_MC_ELSE() {
4032	IEM_MC_REL_JMP_S16(i16Imm);
4033	} IEM_MC_ENDIF();
4034	IEM_MC_END();
4035	}
4036	else
4037	{
4038	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4039	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4040
4041	IEM_MC_BEGIN(0, 0);
4042	IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
4043	IEM_MC_ADVANCE_RIP();
4044	} IEM_MC_ELSE() {
4045	IEM_MC_REL_JMP_S32(i32Imm);
4046	} IEM_MC_ENDIF();
4047	IEM_MC_END();
4048	}
4049	return VINF_SUCCESS;
4050	}
4051
4052
4053	/** Opcode 0x0f 0x84. */
4054	FNIEMOP_DEF(iemOp_je_Jv)
4055	{
4056	IEMOP_MNEMONIC(je_Jv, "je/jz Jv");
4057	IEMOP_HLP_MIN_386();
4058	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4059	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4060	{
4061	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4062	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4063
4064	IEM_MC_BEGIN(0, 0);
4065	IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
4066	IEM_MC_REL_JMP_S16(i16Imm);
4067	} IEM_MC_ELSE() {
4068	IEM_MC_ADVANCE_RIP();
4069	} IEM_MC_ENDIF();
4070	IEM_MC_END();
4071	}
4072	else
4073	{
4074	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4075	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4076
4077	IEM_MC_BEGIN(0, 0);
4078	IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
4079	IEM_MC_REL_JMP_S32(i32Imm);
4080	} IEM_MC_ELSE() {
4081	IEM_MC_ADVANCE_RIP();
4082	} IEM_MC_ENDIF();
4083	IEM_MC_END();
4084	}
4085	return VINF_SUCCESS;
4086	}
4087
4088
4089	/** Opcode 0x0f 0x85. */
4090	FNIEMOP_DEF(iemOp_jne_Jv)
4091	{
4092	IEMOP_MNEMONIC(jne_Jv, "jne/jnz Jv");
4093	IEMOP_HLP_MIN_386();
4094	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4095	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4096	{
4097	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4098	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4099
4100	IEM_MC_BEGIN(0, 0);
4101	IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
4102	IEM_MC_ADVANCE_RIP();
4103	} IEM_MC_ELSE() {
4104	IEM_MC_REL_JMP_S16(i16Imm);
4105	} IEM_MC_ENDIF();
4106	IEM_MC_END();
4107	}
4108	else
4109	{
4110	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4111	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4112
4113	IEM_MC_BEGIN(0, 0);
4114	IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
4115	IEM_MC_ADVANCE_RIP();
4116	} IEM_MC_ELSE() {
4117	IEM_MC_REL_JMP_S32(i32Imm);
4118	} IEM_MC_ENDIF();
4119	IEM_MC_END();
4120	}
4121	return VINF_SUCCESS;
4122	}
4123
4124
4125	/** Opcode 0x0f 0x86. */
4126	FNIEMOP_DEF(iemOp_jbe_Jv)
4127	{
4128	IEMOP_MNEMONIC(jbe_Jv, "jbe/jna Jv");
4129	IEMOP_HLP_MIN_386();
4130	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4131	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4132	{
4133	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4134	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4135
4136	IEM_MC_BEGIN(0, 0);
4137	IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF \| X86_EFL_ZF) {
4138	IEM_MC_REL_JMP_S16(i16Imm);
4139	} IEM_MC_ELSE() {
4140	IEM_MC_ADVANCE_RIP();
4141	} IEM_MC_ENDIF();
4142	IEM_MC_END();
4143	}
4144	else
4145	{
4146	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4147	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4148
4149	IEM_MC_BEGIN(0, 0);
4150	IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF \| X86_EFL_ZF) {
4151	IEM_MC_REL_JMP_S32(i32Imm);
4152	} IEM_MC_ELSE() {
4153	IEM_MC_ADVANCE_RIP();
4154	} IEM_MC_ENDIF();
4155	IEM_MC_END();
4156	}
4157	return VINF_SUCCESS;
4158	}
4159
4160
4161	/** Opcode 0x0f 0x87. */
4162	FNIEMOP_DEF(iemOp_jnbe_Jv)
4163	{
4164	IEMOP_MNEMONIC(ja_Jv, "jnbe/ja Jv");
4165	IEMOP_HLP_MIN_386();
4166	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4167	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4168	{
4169	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4170	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4171
4172	IEM_MC_BEGIN(0, 0);
4173	IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF \| X86_EFL_ZF) {
4174	IEM_MC_ADVANCE_RIP();
4175	} IEM_MC_ELSE() {
4176	IEM_MC_REL_JMP_S16(i16Imm);
4177	} IEM_MC_ENDIF();
4178	IEM_MC_END();
4179	}
4180	else
4181	{
4182	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4183	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4184
4185	IEM_MC_BEGIN(0, 0);
4186	IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF \| X86_EFL_ZF) {
4187	IEM_MC_ADVANCE_RIP();
4188	} IEM_MC_ELSE() {
4189	IEM_MC_REL_JMP_S32(i32Imm);
4190	} IEM_MC_ENDIF();
4191	IEM_MC_END();
4192	}
4193	return VINF_SUCCESS;
4194	}
4195
4196
4197	/** Opcode 0x0f 0x88. */
4198	FNIEMOP_DEF(iemOp_js_Jv)
4199	{
4200	IEMOP_MNEMONIC(js_Jv, "js Jv");
4201	IEMOP_HLP_MIN_386();
4202	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4203	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4204	{
4205	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4206	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4207
4208	IEM_MC_BEGIN(0, 0);
4209	IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
4210	IEM_MC_REL_JMP_S16(i16Imm);
4211	} IEM_MC_ELSE() {
4212	IEM_MC_ADVANCE_RIP();
4213	} IEM_MC_ENDIF();
4214	IEM_MC_END();
4215	}
4216	else
4217	{
4218	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4219	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4220
4221	IEM_MC_BEGIN(0, 0);
4222	IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
4223	IEM_MC_REL_JMP_S32(i32Imm);
4224	} IEM_MC_ELSE() {
4225	IEM_MC_ADVANCE_RIP();
4226	} IEM_MC_ENDIF();
4227	IEM_MC_END();
4228	}
4229	return VINF_SUCCESS;
4230	}
4231
4232
4233	/** Opcode 0x0f 0x89. */
4234	FNIEMOP_DEF(iemOp_jns_Jv)
4235	{
4236	IEMOP_MNEMONIC(jns_Jv, "jns Jv");
4237	IEMOP_HLP_MIN_386();
4238	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4239	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4240	{
4241	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4242	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4243
4244	IEM_MC_BEGIN(0, 0);
4245	IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
4246	IEM_MC_ADVANCE_RIP();
4247	} IEM_MC_ELSE() {
4248	IEM_MC_REL_JMP_S16(i16Imm);
4249	} IEM_MC_ENDIF();
4250	IEM_MC_END();
4251	}
4252	else
4253	{
4254	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4255	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4256
4257	IEM_MC_BEGIN(0, 0);
4258	IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
4259	IEM_MC_ADVANCE_RIP();
4260	} IEM_MC_ELSE() {
4261	IEM_MC_REL_JMP_S32(i32Imm);
4262	} IEM_MC_ENDIF();
4263	IEM_MC_END();
4264	}
4265	return VINF_SUCCESS;
4266	}
4267
4268
4269	/** Opcode 0x0f 0x8a. */
4270	FNIEMOP_DEF(iemOp_jp_Jv)
4271	{
4272	IEMOP_MNEMONIC(jp_Jv, "jp Jv");
4273	IEMOP_HLP_MIN_386();
4274	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4275	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4276	{
4277	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4278	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4279
4280	IEM_MC_BEGIN(0, 0);
4281	IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
4282	IEM_MC_REL_JMP_S16(i16Imm);
4283	} IEM_MC_ELSE() {
4284	IEM_MC_ADVANCE_RIP();
4285	} IEM_MC_ENDIF();
4286	IEM_MC_END();
4287	}
4288	else
4289	{
4290	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4291	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4292
4293	IEM_MC_BEGIN(0, 0);
4294	IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
4295	IEM_MC_REL_JMP_S32(i32Imm);
4296	} IEM_MC_ELSE() {
4297	IEM_MC_ADVANCE_RIP();
4298	} IEM_MC_ENDIF();
4299	IEM_MC_END();
4300	}
4301	return VINF_SUCCESS;
4302	}
4303
4304
4305	/** Opcode 0x0f 0x8b. */
4306	FNIEMOP_DEF(iemOp_jnp_Jv)
4307	{
4308	IEMOP_MNEMONIC(jnp_Jv, "jnp Jv");
4309	IEMOP_HLP_MIN_386();
4310	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4311	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4312	{
4313	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4314	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4315
4316	IEM_MC_BEGIN(0, 0);
4317	IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
4318	IEM_MC_ADVANCE_RIP();
4319	} IEM_MC_ELSE() {
4320	IEM_MC_REL_JMP_S16(i16Imm);
4321	} IEM_MC_ENDIF();
4322	IEM_MC_END();
4323	}
4324	else
4325	{
4326	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4327	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4328
4329	IEM_MC_BEGIN(0, 0);
4330	IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
4331	IEM_MC_ADVANCE_RIP();
4332	} IEM_MC_ELSE() {
4333	IEM_MC_REL_JMP_S32(i32Imm);
4334	} IEM_MC_ENDIF();
4335	IEM_MC_END();
4336	}
4337	return VINF_SUCCESS;
4338	}
4339
4340
4341	/** Opcode 0x0f 0x8c. */
4342	FNIEMOP_DEF(iemOp_jl_Jv)
4343	{
4344	IEMOP_MNEMONIC(jl_Jv, "jl/jnge Jv");
4345	IEMOP_HLP_MIN_386();
4346	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4347	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4348	{
4349	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4350	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4351
4352	IEM_MC_BEGIN(0, 0);
4353	IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
4354	IEM_MC_REL_JMP_S16(i16Imm);
4355	} IEM_MC_ELSE() {
4356	IEM_MC_ADVANCE_RIP();
4357	} IEM_MC_ENDIF();
4358	IEM_MC_END();
4359	}
4360	else
4361	{
4362	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4363	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4364
4365	IEM_MC_BEGIN(0, 0);
4366	IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
4367	IEM_MC_REL_JMP_S32(i32Imm);
4368	} IEM_MC_ELSE() {
4369	IEM_MC_ADVANCE_RIP();
4370	} IEM_MC_ENDIF();
4371	IEM_MC_END();
4372	}
4373	return VINF_SUCCESS;
4374	}
4375
4376
4377	/** Opcode 0x0f 0x8d. */
4378	FNIEMOP_DEF(iemOp_jnl_Jv)
4379	{
4380	IEMOP_MNEMONIC(jge_Jv, "jnl/jge Jv");
4381	IEMOP_HLP_MIN_386();
4382	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4383	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4384	{
4385	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4386	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4387
4388	IEM_MC_BEGIN(0, 0);
4389	IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
4390	IEM_MC_ADVANCE_RIP();
4391	} IEM_MC_ELSE() {
4392	IEM_MC_REL_JMP_S16(i16Imm);
4393	} IEM_MC_ENDIF();
4394	IEM_MC_END();
4395	}
4396	else
4397	{
4398	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4399	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4400
4401	IEM_MC_BEGIN(0, 0);
4402	IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
4403	IEM_MC_ADVANCE_RIP();
4404	} IEM_MC_ELSE() {
4405	IEM_MC_REL_JMP_S32(i32Imm);
4406	} IEM_MC_ENDIF();
4407	IEM_MC_END();
4408	}
4409	return VINF_SUCCESS;
4410	}
4411
4412
4413	/** Opcode 0x0f 0x8e. */
4414	FNIEMOP_DEF(iemOp_jle_Jv)
4415	{
4416	IEMOP_MNEMONIC(jle_Jv, "jle/jng Jv");
4417	IEMOP_HLP_MIN_386();
4418	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4419	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4420	{
4421	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4422	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4423
4424	IEM_MC_BEGIN(0, 0);
4425	IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
4426	IEM_MC_REL_JMP_S16(i16Imm);
4427	} IEM_MC_ELSE() {
4428	IEM_MC_ADVANCE_RIP();
4429	} IEM_MC_ENDIF();
4430	IEM_MC_END();
4431	}
4432	else
4433	{
4434	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4435	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4436
4437	IEM_MC_BEGIN(0, 0);
4438	IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
4439	IEM_MC_REL_JMP_S32(i32Imm);
4440	} IEM_MC_ELSE() {
4441	IEM_MC_ADVANCE_RIP();
4442	} IEM_MC_ENDIF();
4443	IEM_MC_END();
4444	}
4445	return VINF_SUCCESS;
4446	}
4447
4448
4449	/** Opcode 0x0f 0x8f. */
4450	FNIEMOP_DEF(iemOp_jnle_Jv)
4451	{
4452	IEMOP_MNEMONIC(jg_Jv, "jnle/jg Jv");
4453	IEMOP_HLP_MIN_386();
4454	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
4455	if (pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT)
4456	{
4457	int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
4458	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4459
4460	IEM_MC_BEGIN(0, 0);
4461	IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
4462	IEM_MC_ADVANCE_RIP();
4463	} IEM_MC_ELSE() {
4464	IEM_MC_REL_JMP_S16(i16Imm);
4465	} IEM_MC_ENDIF();
4466	IEM_MC_END();
4467	}
4468	else
4469	{
4470	int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
4471	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4472
4473	IEM_MC_BEGIN(0, 0);
4474	IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
4475	IEM_MC_ADVANCE_RIP();
4476	} IEM_MC_ELSE() {
4477	IEM_MC_REL_JMP_S32(i32Imm);
4478	} IEM_MC_ENDIF();
4479	IEM_MC_END();
4480	}
4481	return VINF_SUCCESS;
4482	}
4483
4484
4485	/** Opcode 0x0f 0x90. */
4486	FNIEMOP_DEF(iemOp_seto_Eb)
4487	{
4488	IEMOP_MNEMONIC(seto_Eb, "seto Eb");
4489	IEMOP_HLP_MIN_386();
4490	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4491
4492	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
4493	* any way. AMD says it's "unused", whatever that means. We're
4494	* ignoring for now. */
4495	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4496	{
4497	/* register target */
4498	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4499	IEM_MC_BEGIN(0, 0);
4500	IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
4501	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
4502	} IEM_MC_ELSE() {
4503	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
4504	} IEM_MC_ENDIF();
4505	IEM_MC_ADVANCE_RIP();
4506	IEM_MC_END();
4507	}
4508	else
4509	{
4510	/* memory target */
4511	IEM_MC_BEGIN(0, 1);
4512	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
4513	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
4514	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4515	IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
4516	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
4517	} IEM_MC_ELSE() {
4518	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
4519	} IEM_MC_ENDIF();
4520	IEM_MC_ADVANCE_RIP();
4521	IEM_MC_END();
4522	}
4523	return VINF_SUCCESS;
4524	}
4525
4526
4527	/** Opcode 0x0f 0x91. */
4528	FNIEMOP_DEF(iemOp_setno_Eb)
4529	{
4530	IEMOP_MNEMONIC(setno_Eb, "setno Eb");
4531	IEMOP_HLP_MIN_386();
4532	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4533
4534	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
4535	* any way. AMD says it's "unused", whatever that means. We're
4536	* ignoring for now. */
4537	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4538	{
4539	/* register target */
4540	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4541	IEM_MC_BEGIN(0, 0);
4542	IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
4543	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
4544	} IEM_MC_ELSE() {
4545	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
4546	} IEM_MC_ENDIF();
4547	IEM_MC_ADVANCE_RIP();
4548	IEM_MC_END();
4549	}
4550	else
4551	{
4552	/* memory target */
4553	IEM_MC_BEGIN(0, 1);
4554	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
4555	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
4556	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4557	IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
4558	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
4559	} IEM_MC_ELSE() {
4560	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
4561	} IEM_MC_ENDIF();
4562	IEM_MC_ADVANCE_RIP();
4563	IEM_MC_END();
4564	}
4565	return VINF_SUCCESS;
4566	}
4567
4568
4569	/** Opcode 0x0f 0x92. */
4570	FNIEMOP_DEF(iemOp_setc_Eb)
4571	{
4572	IEMOP_MNEMONIC(setc_Eb, "setc Eb");
4573	IEMOP_HLP_MIN_386();
4574	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4575
4576	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
4577	* any way. AMD says it's "unused", whatever that means. We're
4578	* ignoring for now. */
4579	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4580	{
4581	/* register target */
4582	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4583	IEM_MC_BEGIN(0, 0);
4584	IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
4585	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
4586	} IEM_MC_ELSE() {
4587	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
4588	} IEM_MC_ENDIF();
4589	IEM_MC_ADVANCE_RIP();
4590	IEM_MC_END();
4591	}
4592	else
4593	{
4594	/* memory target */
4595	IEM_MC_BEGIN(0, 1);
4596	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
4597	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
4598	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4599	IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
4600	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
4601	} IEM_MC_ELSE() {
4602	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
4603	} IEM_MC_ENDIF();
4604	IEM_MC_ADVANCE_RIP();
4605	IEM_MC_END();
4606	}
4607	return VINF_SUCCESS;
4608	}
4609
4610
4611	/** Opcode 0x0f 0x93. */
4612	FNIEMOP_DEF(iemOp_setnc_Eb)
4613	{
4614	IEMOP_MNEMONIC(setnc_Eb, "setnc Eb");
4615	IEMOP_HLP_MIN_386();
4616	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4617
4618	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
4619	* any way. AMD says it's "unused", whatever that means. We're
4620	* ignoring for now. */
4621	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4622	{
4623	/* register target */
4624	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4625	IEM_MC_BEGIN(0, 0);
4626	IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
4627	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
4628	} IEM_MC_ELSE() {
4629	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
4630	} IEM_MC_ENDIF();
4631	IEM_MC_ADVANCE_RIP();
4632	IEM_MC_END();
4633	}
4634	else
4635	{
4636	/* memory target */
4637	IEM_MC_BEGIN(0, 1);
4638	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
4639	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
4640	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4641	IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
4642	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
4643	} IEM_MC_ELSE() {
4644	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
4645	} IEM_MC_ENDIF();
4646	IEM_MC_ADVANCE_RIP();
4647	IEM_MC_END();
4648	}
4649	return VINF_SUCCESS;
4650	}
4651
4652
4653	/** Opcode 0x0f 0x94. */
4654	FNIEMOP_DEF(iemOp_sete_Eb)
4655	{
4656	IEMOP_MNEMONIC(sete_Eb, "sete Eb");
4657	IEMOP_HLP_MIN_386();
4658	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4659
4660	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
4661	* any way. AMD says it's "unused", whatever that means. We're
4662	* ignoring for now. */
4663	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4664	{
4665	/* register target */
4666	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4667	IEM_MC_BEGIN(0, 0);
4668	IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
4669	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
4670	} IEM_MC_ELSE() {
4671	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
4672	} IEM_MC_ENDIF();
4673	IEM_MC_ADVANCE_RIP();
4674	IEM_MC_END();
4675	}
4676	else
4677	{
4678	/* memory target */
4679	IEM_MC_BEGIN(0, 1);
4680	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
4681	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
4682	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4683	IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
4684	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
4685	} IEM_MC_ELSE() {
4686	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
4687	} IEM_MC_ENDIF();
4688	IEM_MC_ADVANCE_RIP();
4689	IEM_MC_END();
4690	}
4691	return VINF_SUCCESS;
4692	}
4693
4694
4695	/** Opcode 0x0f 0x95. */
4696	FNIEMOP_DEF(iemOp_setne_Eb)
4697	{
4698	IEMOP_MNEMONIC(setne_Eb, "setne Eb");
4699	IEMOP_HLP_MIN_386();
4700	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4701
4702	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
4703	* any way. AMD says it's "unused", whatever that means. We're
4704	* ignoring for now. */
4705	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4706	{
4707	/* register target */
4708	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4709	IEM_MC_BEGIN(0, 0);
4710	IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
4711	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
4712	} IEM_MC_ELSE() {
4713	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
4714	} IEM_MC_ENDIF();
4715	IEM_MC_ADVANCE_RIP();
4716	IEM_MC_END();
4717	}
4718	else
4719	{
4720	/* memory target */
4721	IEM_MC_BEGIN(0, 1);
4722	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
4723	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
4724	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4725	IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
4726	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
4727	} IEM_MC_ELSE() {
4728	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
4729	} IEM_MC_ENDIF();
4730	IEM_MC_ADVANCE_RIP();
4731	IEM_MC_END();
4732	}
4733	return VINF_SUCCESS;
4734	}
4735
4736
4737	/** Opcode 0x0f 0x96. */
4738	FNIEMOP_DEF(iemOp_setbe_Eb)
4739	{
4740	IEMOP_MNEMONIC(setbe_Eb, "setbe Eb");
4741	IEMOP_HLP_MIN_386();
4742	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4743
4744	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
4745	* any way. AMD says it's "unused", whatever that means. We're
4746	* ignoring for now. */
4747	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4748	{
4749	/* register target */
4750	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4751	IEM_MC_BEGIN(0, 0);
4752	IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF \| X86_EFL_ZF) {
4753	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
4754	} IEM_MC_ELSE() {
4755	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
4756	} IEM_MC_ENDIF();
4757	IEM_MC_ADVANCE_RIP();
4758	IEM_MC_END();
4759	}
4760	else
4761	{
4762	/* memory target */
4763	IEM_MC_BEGIN(0, 1);
4764	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
4765	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
4766	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4767	IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF \| X86_EFL_ZF) {
4768	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
4769	} IEM_MC_ELSE() {
4770	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
4771	} IEM_MC_ENDIF();
4772	IEM_MC_ADVANCE_RIP();
4773	IEM_MC_END();
4774	}
4775	return VINF_SUCCESS;
4776	}
4777
4778
4779	/** Opcode 0x0f 0x97. */
4780	FNIEMOP_DEF(iemOp_setnbe_Eb)
4781	{
4782	IEMOP_MNEMONIC(setnbe_Eb, "setnbe Eb");
4783	IEMOP_HLP_MIN_386();
4784	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4785
4786	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
4787	* any way. AMD says it's "unused", whatever that means. We're
4788	* ignoring for now. */
4789	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4790	{
4791	/* register target */
4792	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4793	IEM_MC_BEGIN(0, 0);
4794	IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF \| X86_EFL_ZF) {
4795	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
4796	} IEM_MC_ELSE() {
4797	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
4798	} IEM_MC_ENDIF();
4799	IEM_MC_ADVANCE_RIP();
4800	IEM_MC_END();
4801	}
4802	else
4803	{
4804	/* memory target */
4805	IEM_MC_BEGIN(0, 1);
4806	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
4807	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
4808	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4809	IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF \| X86_EFL_ZF) {
4810	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
4811	} IEM_MC_ELSE() {
4812	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
4813	} IEM_MC_ENDIF();
4814	IEM_MC_ADVANCE_RIP();
4815	IEM_MC_END();
4816	}
4817	return VINF_SUCCESS;
4818	}
4819
4820
4821	/** Opcode 0x0f 0x98. */
4822	FNIEMOP_DEF(iemOp_sets_Eb)
4823	{
4824	IEMOP_MNEMONIC(sets_Eb, "sets Eb");
4825	IEMOP_HLP_MIN_386();
4826	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4827
4828	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
4829	* any way. AMD says it's "unused", whatever that means. We're
4830	* ignoring for now. */
4831	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4832	{
4833	/* register target */
4834	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4835	IEM_MC_BEGIN(0, 0);
4836	IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
4837	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
4838	} IEM_MC_ELSE() {
4839	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
4840	} IEM_MC_ENDIF();
4841	IEM_MC_ADVANCE_RIP();
4842	IEM_MC_END();
4843	}
4844	else
4845	{
4846	/* memory target */
4847	IEM_MC_BEGIN(0, 1);
4848	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
4849	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
4850	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4851	IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
4852	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
4853	} IEM_MC_ELSE() {
4854	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
4855	} IEM_MC_ENDIF();
4856	IEM_MC_ADVANCE_RIP();
4857	IEM_MC_END();
4858	}
4859	return VINF_SUCCESS;
4860	}
4861
4862
4863	/** Opcode 0x0f 0x99. */
4864	FNIEMOP_DEF(iemOp_setns_Eb)
4865	{
4866	IEMOP_MNEMONIC(setns_Eb, "setns Eb");
4867	IEMOP_HLP_MIN_386();
4868	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4869
4870	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
4871	* any way. AMD says it's "unused", whatever that means. We're
4872	* ignoring for now. */
4873	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4874	{
4875	/* register target */
4876	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4877	IEM_MC_BEGIN(0, 0);
4878	IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
4879	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
4880	} IEM_MC_ELSE() {
4881	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
4882	} IEM_MC_ENDIF();
4883	IEM_MC_ADVANCE_RIP();
4884	IEM_MC_END();
4885	}
4886	else
4887	{
4888	/* memory target */
4889	IEM_MC_BEGIN(0, 1);
4890	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
4891	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
4892	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4893	IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
4894	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
4895	} IEM_MC_ELSE() {
4896	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
4897	} IEM_MC_ENDIF();
4898	IEM_MC_ADVANCE_RIP();
4899	IEM_MC_END();
4900	}
4901	return VINF_SUCCESS;
4902	}
4903
4904
4905	/** Opcode 0x0f 0x9a. */
4906	FNIEMOP_DEF(iemOp_setp_Eb)
4907	{
4908	IEMOP_MNEMONIC(setp_Eb, "setp Eb");
4909	IEMOP_HLP_MIN_386();
4910	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4911
4912	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
4913	* any way. AMD says it's "unused", whatever that means. We're
4914	* ignoring for now. */
4915	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4916	{
4917	/* register target */
4918	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4919	IEM_MC_BEGIN(0, 0);
4920	IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
4921	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
4922	} IEM_MC_ELSE() {
4923	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
4924	} IEM_MC_ENDIF();
4925	IEM_MC_ADVANCE_RIP();
4926	IEM_MC_END();
4927	}
4928	else
4929	{
4930	/* memory target */
4931	IEM_MC_BEGIN(0, 1);
4932	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
4933	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
4934	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4935	IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
4936	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
4937	} IEM_MC_ELSE() {
4938	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
4939	} IEM_MC_ENDIF();
4940	IEM_MC_ADVANCE_RIP();
4941	IEM_MC_END();
4942	}
4943	return VINF_SUCCESS;
4944	}
4945
4946
4947	/** Opcode 0x0f 0x9b. */
4948	FNIEMOP_DEF(iemOp_setnp_Eb)
4949	{
4950	IEMOP_MNEMONIC(setnp_Eb, "setnp Eb");
4951	IEMOP_HLP_MIN_386();
4952	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4953
4954	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
4955	* any way. AMD says it's "unused", whatever that means. We're
4956	* ignoring for now. */
4957	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
4958	{
4959	/* register target */
4960	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4961	IEM_MC_BEGIN(0, 0);
4962	IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
4963	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
4964	} IEM_MC_ELSE() {
4965	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
4966	} IEM_MC_ENDIF();
4967	IEM_MC_ADVANCE_RIP();
4968	IEM_MC_END();
4969	}
4970	else
4971	{
4972	/* memory target */
4973	IEM_MC_BEGIN(0, 1);
4974	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
4975	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
4976	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
4977	IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
4978	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
4979	} IEM_MC_ELSE() {
4980	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
4981	} IEM_MC_ENDIF();
4982	IEM_MC_ADVANCE_RIP();
4983	IEM_MC_END();
4984	}
4985	return VINF_SUCCESS;
4986	}
4987
4988
4989	/** Opcode 0x0f 0x9c. */
4990	FNIEMOP_DEF(iemOp_setl_Eb)
4991	{
4992	IEMOP_MNEMONIC(setl_Eb, "setl Eb");
4993	IEMOP_HLP_MIN_386();
4994	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
4995
4996	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
4997	* any way. AMD says it's "unused", whatever that means. We're
4998	* ignoring for now. */
4999	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5000	{
5001	/* register target */
5002	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5003	IEM_MC_BEGIN(0, 0);
5004	IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
5005	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
5006	} IEM_MC_ELSE() {
5007	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
5008	} IEM_MC_ENDIF();
5009	IEM_MC_ADVANCE_RIP();
5010	IEM_MC_END();
5011	}
5012	else
5013	{
5014	/* memory target */
5015	IEM_MC_BEGIN(0, 1);
5016	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5017	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5018	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5019	IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
5020	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5021	} IEM_MC_ELSE() {
5022	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5023	} IEM_MC_ENDIF();
5024	IEM_MC_ADVANCE_RIP();
5025	IEM_MC_END();
5026	}
5027	return VINF_SUCCESS;
5028	}
5029
5030
5031	/** Opcode 0x0f 0x9d. */
5032	FNIEMOP_DEF(iemOp_setnl_Eb)
5033	{
5034	IEMOP_MNEMONIC(setnl_Eb, "setnl Eb");
5035	IEMOP_HLP_MIN_386();
5036	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5037
5038	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5039	* any way. AMD says it's "unused", whatever that means. We're
5040	* ignoring for now. */
5041	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5042	{
5043	/* register target */
5044	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5045	IEM_MC_BEGIN(0, 0);
5046	IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
5047	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
5048	} IEM_MC_ELSE() {
5049	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
5050	} IEM_MC_ENDIF();
5051	IEM_MC_ADVANCE_RIP();
5052	IEM_MC_END();
5053	}
5054	else
5055	{
5056	/* memory target */
5057	IEM_MC_BEGIN(0, 1);
5058	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5059	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5060	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5061	IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
5062	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5063	} IEM_MC_ELSE() {
5064	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5065	} IEM_MC_ENDIF();
5066	IEM_MC_ADVANCE_RIP();
5067	IEM_MC_END();
5068	}
5069	return VINF_SUCCESS;
5070	}
5071
5072
5073	/** Opcode 0x0f 0x9e. */
5074	FNIEMOP_DEF(iemOp_setle_Eb)
5075	{
5076	IEMOP_MNEMONIC(setle_Eb, "setle Eb");
5077	IEMOP_HLP_MIN_386();
5078	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5079
5080	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5081	* any way. AMD says it's "unused", whatever that means. We're
5082	* ignoring for now. */
5083	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5084	{
5085	/* register target */
5086	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5087	IEM_MC_BEGIN(0, 0);
5088	IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
5089	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
5090	} IEM_MC_ELSE() {
5091	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
5092	} IEM_MC_ENDIF();
5093	IEM_MC_ADVANCE_RIP();
5094	IEM_MC_END();
5095	}
5096	else
5097	{
5098	/* memory target */
5099	IEM_MC_BEGIN(0, 1);
5100	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5101	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5102	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5103	IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
5104	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5105	} IEM_MC_ELSE() {
5106	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5107	} IEM_MC_ENDIF();
5108	IEM_MC_ADVANCE_RIP();
5109	IEM_MC_END();
5110	}
5111	return VINF_SUCCESS;
5112	}
5113
5114
5115	/** Opcode 0x0f 0x9f. */
5116	FNIEMOP_DEF(iemOp_setnle_Eb)
5117	{
5118	IEMOP_MNEMONIC(setnle_Eb, "setnle Eb");
5119	IEMOP_HLP_MIN_386();
5120	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5121
5122	/** @todo Encoding test: Check if the 'reg' field is ignored or decoded in
5123	* any way. AMD says it's "unused", whatever that means. We're
5124	* ignoring for now. */
5125	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5126	{
5127	/* register target */
5128	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5129	IEM_MC_BEGIN(0, 0);
5130	IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
5131	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 0);
5132	} IEM_MC_ELSE() {
5133	IEM_MC_STORE_GREG_U8_CONST((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, 1);
5134	} IEM_MC_ENDIF();
5135	IEM_MC_ADVANCE_RIP();
5136	IEM_MC_END();
5137	}
5138	else
5139	{
5140	/* memory target */
5141	IEM_MC_BEGIN(0, 1);
5142	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5143	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5144	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5145	IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
5146	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5147	} IEM_MC_ELSE() {
5148	IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1);
5149	} IEM_MC_ENDIF();
5150	IEM_MC_ADVANCE_RIP();
5151	IEM_MC_END();
5152	}
5153	return VINF_SUCCESS;
5154	}
5155
5156
5157	/**
5158	* Common 'push segment-register' helper.
5159	*/
5160	FNIEMOP_DEF_1(iemOpCommonPushSReg, uint8_t, iReg)
5161	{
5162	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5163	Assert(iReg < X86_SREG_FS \|\| pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT);
5164	IEMOP_HLP_DEFAULT_64BIT_OP_SIZE();
5165
5166	switch (pVCpu->iem.s.enmEffOpSize)
5167	{
5168	case IEMMODE_16BIT:
5169	IEM_MC_BEGIN(0, 1);
5170	IEM_MC_LOCAL(uint16_t, u16Value);
5171	IEM_MC_FETCH_SREG_U16(u16Value, iReg);
5172	IEM_MC_PUSH_U16(u16Value);
5173	IEM_MC_ADVANCE_RIP();
5174	IEM_MC_END();
5175	break;
5176
5177	case IEMMODE_32BIT:
5178	IEM_MC_BEGIN(0, 1);
5179	IEM_MC_LOCAL(uint32_t, u32Value);
5180	IEM_MC_FETCH_SREG_ZX_U32(u32Value, iReg);
5181	IEM_MC_PUSH_U32_SREG(u32Value);
5182	IEM_MC_ADVANCE_RIP();
5183	IEM_MC_END();
5184	break;
5185
5186	case IEMMODE_64BIT:
5187	IEM_MC_BEGIN(0, 1);
5188	IEM_MC_LOCAL(uint64_t, u64Value);
5189	IEM_MC_FETCH_SREG_ZX_U64(u64Value, iReg);
5190	IEM_MC_PUSH_U64(u64Value);
5191	IEM_MC_ADVANCE_RIP();
5192	IEM_MC_END();
5193	break;
5194	}
5195
5196	return VINF_SUCCESS;
5197	}
5198
5199
5200	/** Opcode 0x0f 0xa0. */
5201	FNIEMOP_DEF(iemOp_push_fs)
5202	{
5203	IEMOP_MNEMONIC(push_fs, "push fs");
5204	IEMOP_HLP_MIN_386();
5205	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5206	return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_FS);
5207	}
5208
5209
5210	/** Opcode 0x0f 0xa1. */
5211	FNIEMOP_DEF(iemOp_pop_fs)
5212	{
5213	IEMOP_MNEMONIC(pop_fs, "pop fs");
5214	IEMOP_HLP_MIN_386();
5215	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5216	return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_FS, pVCpu->iem.s.enmEffOpSize);
5217	}
5218
5219
5220	/** Opcode 0x0f 0xa2. */
5221	FNIEMOP_DEF(iemOp_cpuid)
5222	{
5223	IEMOP_MNEMONIC(cpuid, "cpuid");
5224	IEMOP_HLP_MIN_486(); /* not all 486es. */
5225	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5226	return IEM_MC_DEFER_TO_CIMPL_0(iemCImpl_cpuid);
5227	}
5228
5229
5230	/**
5231	* Common worker for iemOp_bt_Ev_Gv, iemOp_btc_Ev_Gv, iemOp_btr_Ev_Gv and
5232	* iemOp_bts_Ev_Gv.
5233	*/
5234	FNIEMOP_DEF_1(iemOpCommonBit_Ev_Gv, PCIEMOPBINSIZES, pImpl)
5235	{
5236	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5237	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF \| X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF);
5238
5239	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5240	{
5241	/* register destination. */
5242	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5243	switch (pVCpu->iem.s.enmEffOpSize)
5244	{
5245	case IEMMODE_16BIT:
5246	IEM_MC_BEGIN(3, 0);
5247	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
5248	IEM_MC_ARG(uint16_t, u16Src, 1);
5249	IEM_MC_ARG(uint32_t *, pEFlags, 2);
5250
5251	IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5252	IEM_MC_AND_LOCAL_U16(u16Src, 0xf);
5253	IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
5254	IEM_MC_REF_EFLAGS(pEFlags);
5255	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
5256
5257	IEM_MC_ADVANCE_RIP();
5258	IEM_MC_END();
5259	return VINF_SUCCESS;
5260
5261	case IEMMODE_32BIT:
5262	IEM_MC_BEGIN(3, 0);
5263	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
5264	IEM_MC_ARG(uint32_t, u32Src, 1);
5265	IEM_MC_ARG(uint32_t *, pEFlags, 2);
5266
5267	IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5268	IEM_MC_AND_LOCAL_U32(u32Src, 0x1f);
5269	IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
5270	IEM_MC_REF_EFLAGS(pEFlags);
5271	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
5272
5273	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
5274	IEM_MC_ADVANCE_RIP();
5275	IEM_MC_END();
5276	return VINF_SUCCESS;
5277
5278	case IEMMODE_64BIT:
5279	IEM_MC_BEGIN(3, 0);
5280	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
5281	IEM_MC_ARG(uint64_t, u64Src, 1);
5282	IEM_MC_ARG(uint32_t *, pEFlags, 2);
5283
5284	IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5285	IEM_MC_AND_LOCAL_U64(u64Src, 0x3f);
5286	IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
5287	IEM_MC_REF_EFLAGS(pEFlags);
5288	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
5289
5290	IEM_MC_ADVANCE_RIP();
5291	IEM_MC_END();
5292	return VINF_SUCCESS;
5293
5294	IEM_NOT_REACHED_DEFAULT_CASE_RET();
5295	}
5296	}
5297	else
5298	{
5299	/* memory destination. */
5300
5301	uint32_t fAccess;
5302	if (pImpl->pfnLockedU16)
5303	fAccess = IEM_ACCESS_DATA_RW;
5304	else /* BT */
5305	fAccess = IEM_ACCESS_DATA_R;
5306
5307	/** @todo test negative bit offsets! */
5308	switch (pVCpu->iem.s.enmEffOpSize)
5309	{
5310	case IEMMODE_16BIT:
5311	IEM_MC_BEGIN(3, 2);
5312	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
5313	IEM_MC_ARG(uint16_t, u16Src, 1);
5314	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
5315	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5316	IEM_MC_LOCAL(int16_t, i16AddrAdj);
5317
5318	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5319	if (pImpl->pfnLockedU16)
5320	IEMOP_HLP_DONE_DECODING();
5321	else
5322	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5323	IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5324	IEM_MC_ASSIGN(i16AddrAdj, u16Src);
5325	IEM_MC_AND_ARG_U16(u16Src, 0x0f);
5326	IEM_MC_SAR_LOCAL_S16(i16AddrAdj, 4);
5327	IEM_MC_SHL_LOCAL_S16(i16AddrAdj, 1);
5328	IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(GCPtrEffDst, i16AddrAdj);
5329	IEM_MC_FETCH_EFLAGS(EFlags);
5330
5331	IEM_MC_MEM_MAP(pu16Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5332	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
5333	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
5334	else
5335	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU16, pu16Dst, u16Src, pEFlags);
5336	IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, fAccess);
5337
5338	IEM_MC_COMMIT_EFLAGS(EFlags);
5339	IEM_MC_ADVANCE_RIP();
5340	IEM_MC_END();
5341	return VINF_SUCCESS;
5342
5343	case IEMMODE_32BIT:
5344	IEM_MC_BEGIN(3, 2);
5345	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
5346	IEM_MC_ARG(uint32_t, u32Src, 1);
5347	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
5348	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5349	IEM_MC_LOCAL(int32_t, i32AddrAdj);
5350
5351	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5352	if (pImpl->pfnLockedU16)
5353	IEMOP_HLP_DONE_DECODING();
5354	else
5355	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5356	IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5357	IEM_MC_ASSIGN(i32AddrAdj, u32Src);
5358	IEM_MC_AND_ARG_U32(u32Src, 0x1f);
5359	IEM_MC_SAR_LOCAL_S32(i32AddrAdj, 5);
5360	IEM_MC_SHL_LOCAL_S32(i32AddrAdj, 2);
5361	IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(GCPtrEffDst, i32AddrAdj);
5362	IEM_MC_FETCH_EFLAGS(EFlags);
5363
5364	IEM_MC_MEM_MAP(pu32Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5365	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
5366	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
5367	else
5368	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU32, pu32Dst, u32Src, pEFlags);
5369	IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, fAccess);
5370
5371	IEM_MC_COMMIT_EFLAGS(EFlags);
5372	IEM_MC_ADVANCE_RIP();
5373	IEM_MC_END();
5374	return VINF_SUCCESS;
5375
5376	case IEMMODE_64BIT:
5377	IEM_MC_BEGIN(3, 2);
5378	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
5379	IEM_MC_ARG(uint64_t, u64Src, 1);
5380	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
5381	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5382	IEM_MC_LOCAL(int64_t, i64AddrAdj);
5383
5384	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5385	if (pImpl->pfnLockedU16)
5386	IEMOP_HLP_DONE_DECODING();
5387	else
5388	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5389	IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5390	IEM_MC_ASSIGN(i64AddrAdj, u64Src);
5391	IEM_MC_AND_ARG_U64(u64Src, 0x3f);
5392	IEM_MC_SAR_LOCAL_S64(i64AddrAdj, 6);
5393	IEM_MC_SHL_LOCAL_S64(i64AddrAdj, 3);
5394	IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(GCPtrEffDst, i64AddrAdj);
5395	IEM_MC_FETCH_EFLAGS(EFlags);
5396
5397	IEM_MC_MEM_MAP(pu64Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5398	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
5399	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
5400	else
5401	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU64, pu64Dst, u64Src, pEFlags);
5402	IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, fAccess);
5403
5404	IEM_MC_COMMIT_EFLAGS(EFlags);
5405	IEM_MC_ADVANCE_RIP();
5406	IEM_MC_END();
5407	return VINF_SUCCESS;
5408
5409	IEM_NOT_REACHED_DEFAULT_CASE_RET();
5410	}
5411	}
5412	}
5413
5414
5415	/** Opcode 0x0f 0xa3. */
5416	FNIEMOP_DEF(iemOp_bt_Ev_Gv)
5417	{
5418	IEMOP_MNEMONIC(bt_Ev_Gv, "bt Ev,Gv");
5419	IEMOP_HLP_MIN_386();
5420	return FNIEMOP_CALL_1(iemOpCommonBit_Ev_Gv, &g_iemAImpl_bt);
5421	}
5422
5423
5424	/**
5425	* Common worker for iemOp_shrd_Ev_Gv_Ib and iemOp_shld_Ev_Gv_Ib.
5426	*/
5427	FNIEMOP_DEF_1(iemOpCommonShldShrd_Ib, PCIEMOPSHIFTDBLSIZES, pImpl)
5428	{
5429	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5430	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_OF);
5431
5432	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5433	{
5434	uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
5435	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5436
5437	switch (pVCpu->iem.s.enmEffOpSize)
5438	{
5439	case IEMMODE_16BIT:
5440	IEM_MC_BEGIN(4, 0);
5441	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
5442	IEM_MC_ARG(uint16_t, u16Src, 1);
5443	IEM_MC_ARG_CONST(uint8_t, cShiftArg, /=/cShift, 2);
5444	IEM_MC_ARG(uint32_t *, pEFlags, 3);
5445
5446	IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5447	IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
5448	IEM_MC_REF_EFLAGS(pEFlags);
5449	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);
5450
5451	IEM_MC_ADVANCE_RIP();
5452	IEM_MC_END();
5453	return VINF_SUCCESS;
5454
5455	case IEMMODE_32BIT:
5456	IEM_MC_BEGIN(4, 0);
5457	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
5458	IEM_MC_ARG(uint32_t, u32Src, 1);
5459	IEM_MC_ARG_CONST(uint8_t, cShiftArg, /=/cShift, 2);
5460	IEM_MC_ARG(uint32_t *, pEFlags, 3);
5461
5462	IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5463	IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
5464	IEM_MC_REF_EFLAGS(pEFlags);
5465	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);
5466
5467	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
5468	IEM_MC_ADVANCE_RIP();
5469	IEM_MC_END();
5470	return VINF_SUCCESS;
5471
5472	case IEMMODE_64BIT:
5473	IEM_MC_BEGIN(4, 0);
5474	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
5475	IEM_MC_ARG(uint64_t, u64Src, 1);
5476	IEM_MC_ARG_CONST(uint8_t, cShiftArg, /=/cShift, 2);
5477	IEM_MC_ARG(uint32_t *, pEFlags, 3);
5478
5479	IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5480	IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
5481	IEM_MC_REF_EFLAGS(pEFlags);
5482	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);
5483
5484	IEM_MC_ADVANCE_RIP();
5485	IEM_MC_END();
5486	return VINF_SUCCESS;
5487
5488	IEM_NOT_REACHED_DEFAULT_CASE_RET();
5489	}
5490	}
5491	else
5492	{
5493	switch (pVCpu->iem.s.enmEffOpSize)
5494	{
5495	case IEMMODE_16BIT:
5496	IEM_MC_BEGIN(4, 2);
5497	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
5498	IEM_MC_ARG(uint16_t, u16Src, 1);
5499	IEM_MC_ARG(uint8_t, cShiftArg, 2);
5500	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
5501	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5502
5503	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
5504	uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
5505	IEM_MC_ASSIGN(cShiftArg, cShift);
5506	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5507	IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5508	IEM_MC_FETCH_EFLAGS(EFlags);
5509	IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5510	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);
5511
5512	IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
5513	IEM_MC_COMMIT_EFLAGS(EFlags);
5514	IEM_MC_ADVANCE_RIP();
5515	IEM_MC_END();
5516	return VINF_SUCCESS;
5517
5518	case IEMMODE_32BIT:
5519	IEM_MC_BEGIN(4, 2);
5520	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
5521	IEM_MC_ARG(uint32_t, u32Src, 1);
5522	IEM_MC_ARG(uint8_t, cShiftArg, 2);
5523	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
5524	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5525
5526	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
5527	uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
5528	IEM_MC_ASSIGN(cShiftArg, cShift);
5529	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5530	IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5531	IEM_MC_FETCH_EFLAGS(EFlags);
5532	IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5533	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);
5534
5535	IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
5536	IEM_MC_COMMIT_EFLAGS(EFlags);
5537	IEM_MC_ADVANCE_RIP();
5538	IEM_MC_END();
5539	return VINF_SUCCESS;
5540
5541	case IEMMODE_64BIT:
5542	IEM_MC_BEGIN(4, 2);
5543	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
5544	IEM_MC_ARG(uint64_t, u64Src, 1);
5545	IEM_MC_ARG(uint8_t, cShiftArg, 2);
5546	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
5547	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5548
5549	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
5550	uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);
5551	IEM_MC_ASSIGN(cShiftArg, cShift);
5552	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5553	IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5554	IEM_MC_FETCH_EFLAGS(EFlags);
5555	IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5556	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);
5557
5558	IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
5559	IEM_MC_COMMIT_EFLAGS(EFlags);
5560	IEM_MC_ADVANCE_RIP();
5561	IEM_MC_END();
5562	return VINF_SUCCESS;
5563
5564	IEM_NOT_REACHED_DEFAULT_CASE_RET();
5565	}
5566	}
5567	}
5568
5569
5570	/**
5571	* Common worker for iemOp_shrd_Ev_Gv_CL and iemOp_shld_Ev_Gv_CL.
5572	*/
5573	FNIEMOP_DEF_1(iemOpCommonShldShrd_CL, PCIEMOPSHIFTDBLSIZES, pImpl)
5574	{
5575	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
5576	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF \| X86_EFL_OF);
5577
5578	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
5579	{
5580	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5581
5582	switch (pVCpu->iem.s.enmEffOpSize)
5583	{
5584	case IEMMODE_16BIT:
5585	IEM_MC_BEGIN(4, 0);
5586	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
5587	IEM_MC_ARG(uint16_t, u16Src, 1);
5588	IEM_MC_ARG(uint8_t, cShiftArg, 2);
5589	IEM_MC_ARG(uint32_t *, pEFlags, 3);
5590
5591	IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5592	IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
5593	IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
5594	IEM_MC_REF_EFLAGS(pEFlags);
5595	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);
5596
5597	IEM_MC_ADVANCE_RIP();
5598	IEM_MC_END();
5599	return VINF_SUCCESS;
5600
5601	case IEMMODE_32BIT:
5602	IEM_MC_BEGIN(4, 0);
5603	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
5604	IEM_MC_ARG(uint32_t, u32Src, 1);
5605	IEM_MC_ARG(uint8_t, cShiftArg, 2);
5606	IEM_MC_ARG(uint32_t *, pEFlags, 3);
5607
5608	IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5609	IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
5610	IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
5611	IEM_MC_REF_EFLAGS(pEFlags);
5612	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);
5613
5614	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
5615	IEM_MC_ADVANCE_RIP();
5616	IEM_MC_END();
5617	return VINF_SUCCESS;
5618
5619	case IEMMODE_64BIT:
5620	IEM_MC_BEGIN(4, 0);
5621	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
5622	IEM_MC_ARG(uint64_t, u64Src, 1);
5623	IEM_MC_ARG(uint8_t, cShiftArg, 2);
5624	IEM_MC_ARG(uint32_t *, pEFlags, 3);
5625
5626	IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5627	IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
5628	IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
5629	IEM_MC_REF_EFLAGS(pEFlags);
5630	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);
5631
5632	IEM_MC_ADVANCE_RIP();
5633	IEM_MC_END();
5634	return VINF_SUCCESS;
5635
5636	IEM_NOT_REACHED_DEFAULT_CASE_RET();
5637	}
5638	}
5639	else
5640	{
5641	switch (pVCpu->iem.s.enmEffOpSize)
5642	{
5643	case IEMMODE_16BIT:
5644	IEM_MC_BEGIN(4, 2);
5645	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
5646	IEM_MC_ARG(uint16_t, u16Src, 1);
5647	IEM_MC_ARG(uint8_t, cShiftArg, 2);
5648	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
5649	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5650
5651	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5652	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5653	IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5654	IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
5655	IEM_MC_FETCH_EFLAGS(EFlags);
5656	IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5657	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);
5658
5659	IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
5660	IEM_MC_COMMIT_EFLAGS(EFlags);
5661	IEM_MC_ADVANCE_RIP();
5662	IEM_MC_END();
5663	return VINF_SUCCESS;
5664
5665	case IEMMODE_32BIT:
5666	IEM_MC_BEGIN(4, 2);
5667	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
5668	IEM_MC_ARG(uint32_t, u32Src, 1);
5669	IEM_MC_ARG(uint8_t, cShiftArg, 2);
5670	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
5671	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5672
5673	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5674	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5675	IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5676	IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
5677	IEM_MC_FETCH_EFLAGS(EFlags);
5678	IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5679	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);
5680
5681	IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
5682	IEM_MC_COMMIT_EFLAGS(EFlags);
5683	IEM_MC_ADVANCE_RIP();
5684	IEM_MC_END();
5685	return VINF_SUCCESS;
5686
5687	case IEMMODE_64BIT:
5688	IEM_MC_BEGIN(4, 2);
5689	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
5690	IEM_MC_ARG(uint64_t, u64Src, 1);
5691	IEM_MC_ARG(uint8_t, cShiftArg, 2);
5692	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
5693	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
5694
5695	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
5696	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5697	IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
5698	IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX);
5699	IEM_MC_FETCH_EFLAGS(EFlags);
5700	IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
5701	IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);
5702
5703	IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
5704	IEM_MC_COMMIT_EFLAGS(EFlags);
5705	IEM_MC_ADVANCE_RIP();
5706	IEM_MC_END();
5707	return VINF_SUCCESS;
5708
5709	IEM_NOT_REACHED_DEFAULT_CASE_RET();
5710	}
5711	}
5712	}
5713
5714
5715
5716	/** Opcode 0x0f 0xa4. */
5717	FNIEMOP_DEF(iemOp_shld_Ev_Gv_Ib)
5718	{
5719	IEMOP_MNEMONIC(shld_Ev_Gv_Ib, "shld Ev,Gv,Ib");
5720	IEMOP_HLP_MIN_386();
5721	return FNIEMOP_CALL_1(iemOpCommonShldShrd_Ib, &g_iemAImpl_shld);
5722	}
5723
5724
5725	/** Opcode 0x0f 0xa5. */
5726	FNIEMOP_DEF(iemOp_shld_Ev_Gv_CL)
5727	{
5728	IEMOP_MNEMONIC(shld_Ev_Gv_CL, "shld Ev,Gv,CL");
5729	IEMOP_HLP_MIN_386();
5730	return FNIEMOP_CALL_1(iemOpCommonShldShrd_CL, &g_iemAImpl_shld);
5731	}
5732
5733
5734	/** Opcode 0x0f 0xa8. */
5735	FNIEMOP_DEF(iemOp_push_gs)
5736	{
5737	IEMOP_MNEMONIC(push_gs, "push gs");
5738	IEMOP_HLP_MIN_386();
5739	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5740	return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_GS);
5741	}
5742
5743
5744	/** Opcode 0x0f 0xa9. */
5745	FNIEMOP_DEF(iemOp_pop_gs)
5746	{
5747	IEMOP_MNEMONIC(pop_gs, "pop gs");
5748	IEMOP_HLP_MIN_386();
5749	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5750	return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_GS, pVCpu->iem.s.enmEffOpSize);
5751	}
5752
5753
5754	/** Opcode 0x0f 0xaa. */
5755	FNIEMOP_STUB(iemOp_rsm);
5756	//IEMOP_HLP_MIN_386();
5757
5758
5759	/** Opcode 0x0f 0xab. */
5760	FNIEMOP_DEF(iemOp_bts_Ev_Gv)
5761	{
5762	IEMOP_MNEMONIC(bts_Ev_Gv, "bts Ev,Gv");
5763	IEMOP_HLP_MIN_386();
5764	return FNIEMOP_CALL_1(iemOpCommonBit_Ev_Gv, &g_iemAImpl_bts);
5765	}
5766
5767
5768	/** Opcode 0x0f 0xac. */
5769	FNIEMOP_DEF(iemOp_shrd_Ev_Gv_Ib)
5770	{
5771	IEMOP_MNEMONIC(shrd_Ev_Gv_Ib, "shrd Ev,Gv,Ib");
5772	IEMOP_HLP_MIN_386();
5773	return FNIEMOP_CALL_1(iemOpCommonShldShrd_Ib, &g_iemAImpl_shrd);
5774	}
5775
5776
5777	/** Opcode 0x0f 0xad. */
5778	FNIEMOP_DEF(iemOp_shrd_Ev_Gv_CL)
5779	{
5780	IEMOP_MNEMONIC(shrd_Ev_Gv_CL, "shrd Ev,Gv,CL");
5781	IEMOP_HLP_MIN_386();
5782	return FNIEMOP_CALL_1(iemOpCommonShldShrd_CL, &g_iemAImpl_shrd);
5783	}
5784
5785
5786	/** Opcode 0x0f 0xae mem/0. */
5787	FNIEMOP_DEF_1(iemOp_Grp15_fxsave, uint8_t, bRm)
5788	{
5789	IEMOP_MNEMONIC(fxsave, "fxsave m512");
5790	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFxSaveRstor)
5791	return IEMOP_RAISE_INVALID_OPCODE();
5792
5793	IEM_MC_BEGIN(3, 1);
5794	IEM_MC_ARG(uint8_t, iEffSeg, 0);
5795	IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
5796	IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/=/pVCpu->iem.s.enmEffOpSize, 2);
5797	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
5798	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5799	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
5800	IEM_MC_CALL_CIMPL_3(iemCImpl_fxsave, iEffSeg, GCPtrEff, enmEffOpSize);
5801	IEM_MC_END();
5802	return VINF_SUCCESS;
5803	}
5804
5805
5806	/** Opcode 0x0f 0xae mem/1. */
5807	FNIEMOP_DEF_1(iemOp_Grp15_fxrstor, uint8_t, bRm)
5808	{
5809	IEMOP_MNEMONIC(fxrstor, "fxrstor m512");
5810	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFxSaveRstor)
5811	return IEMOP_RAISE_INVALID_OPCODE();
5812
5813	IEM_MC_BEGIN(3, 1);
5814	IEM_MC_ARG(uint8_t, iEffSeg, 0);
5815	IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
5816	IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/=/pVCpu->iem.s.enmEffOpSize, 2);
5817	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
5818	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5819	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
5820	IEM_MC_CALL_CIMPL_3(iemCImpl_fxrstor, iEffSeg, GCPtrEff, enmEffOpSize);
5821	IEM_MC_END();
5822	return VINF_SUCCESS;
5823	}
5824
5825
5826	/** Opcode 0x0f 0xae mem/2. */
5827	FNIEMOP_STUB_1(iemOp_Grp15_ldmxcsr, uint8_t, bRm);
5828
5829	/** Opcode 0x0f 0xae mem/3. */
5830	FNIEMOP_STUB_1(iemOp_Grp15_stmxcsr, uint8_t, bRm);
5831
5832	/** Opcode 0x0f 0xae mem/4. */
5833	FNIEMOP_UD_STUB_1(iemOp_Grp15_xsave, uint8_t, bRm);
5834
5835	/** Opcode 0x0f 0xae mem/5. */
5836	FNIEMOP_UD_STUB_1(iemOp_Grp15_xrstor, uint8_t, bRm);
5837
5838	/** Opcode 0x0f 0xae mem/6. */
5839	FNIEMOP_UD_STUB_1(iemOp_Grp15_xsaveopt, uint8_t, bRm);
5840
5841	/**
5842	* @opmaps grp15
5843	* @opcode /7
5844	* @oppfx none
5845	* @opcpuid clfsh
5846	* @opgroup og_cachectl
5847	* @optest op1=1 ->
5848	*/
5849	FNIEMOP_DEF_1(iemOp_Grp15_clflush, uint8_t, bRm)
5850	{
5851	IEMOP_MNEMONIC1(M_MEM, CLFLUSH, clflush, MbRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
5852	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fClFlush)
5853	return IEMOP_RAISE_INVALID_OPCODE();
5854
5855	IEM_MC_BEGIN(2, 0);
5856	IEM_MC_ARG(uint8_t, iEffSeg, 0);
5857	IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
5858	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
5859	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5860	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
5861	IEM_MC_CALL_CIMPL_2(iemCImpl_clflush_clflushopt, iEffSeg, GCPtrEff);
5862	IEM_MC_END();
5863	return VINF_SUCCESS;
5864	}
5865
5866	/**
5867	* @opmaps grp15
5868	* @opcode /7
5869	* @oppfx 0x66
5870	* @opcpuid clflushopt
5871	* @opgroup og_cachectl
5872	* @optest op1=1 ->
5873	*/
5874	FNIEMOP_DEF_1(iemOp_Grp15_clflushopt, uint8_t, bRm)
5875	{
5876	IEMOP_MNEMONIC1(M_MEM, CLFLUSHOPT, clflushopt, MbRO, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
5877	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fClFlushOpt)
5878	return IEMOP_RAISE_INVALID_OPCODE();
5879
5880	IEM_MC_BEGIN(2, 0);
5881	IEM_MC_ARG(uint8_t, iEffSeg, 0);
5882	IEM_MC_ARG(RTGCPTR, GCPtrEff, 1);
5883	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
5884	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5885	IEM_MC_ASSIGN(iEffSeg, pVCpu->iem.s.iEffSeg);
5886	IEM_MC_CALL_CIMPL_2(iemCImpl_clflush_clflushopt, iEffSeg, GCPtrEff);
5887	IEM_MC_END();
5888	return VINF_SUCCESS;
5889	}
5890
5891
5892	/** Opcode 0x0f 0xae 11b/5. */
5893	FNIEMOP_DEF_1(iemOp_Grp15_lfence, uint8_t, bRm)
5894	{
5895	RT_NOREF_PV(bRm);
5896	IEMOP_MNEMONIC(lfence, "lfence");
5897	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5898	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
5899	return IEMOP_RAISE_INVALID_OPCODE();
5900
5901	IEM_MC_BEGIN(0, 0);
5902	if (IEM_GET_HOST_CPU_FEATURES(pVCpu)->fSse2)
5903	IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_lfence);
5904	else
5905	IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_alt_mem_fence);
5906	IEM_MC_ADVANCE_RIP();
5907	IEM_MC_END();
5908	return VINF_SUCCESS;
5909	}
5910
5911
5912	/** Opcode 0x0f 0xae 11b/6. */
5913	FNIEMOP_DEF_1(iemOp_Grp15_mfence, uint8_t, bRm)
5914	{
5915	RT_NOREF_PV(bRm);
5916	IEMOP_MNEMONIC(mfence, "mfence");
5917	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5918	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
5919	return IEMOP_RAISE_INVALID_OPCODE();
5920
5921	IEM_MC_BEGIN(0, 0);
5922	if (IEM_GET_HOST_CPU_FEATURES(pVCpu)->fSse2)
5923	IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_mfence);
5924	else
5925	IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_alt_mem_fence);
5926	IEM_MC_ADVANCE_RIP();
5927	IEM_MC_END();
5928	return VINF_SUCCESS;
5929	}
5930
5931
5932	/** Opcode 0x0f 0xae 11b/7. */
5933	FNIEMOP_DEF_1(iemOp_Grp15_sfence, uint8_t, bRm)
5934	{
5935	RT_NOREF_PV(bRm);
5936	IEMOP_MNEMONIC(sfence, "sfence");
5937	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
5938	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
5939	return IEMOP_RAISE_INVALID_OPCODE();
5940
5941	IEM_MC_BEGIN(0, 0);
5942	if (IEM_GET_HOST_CPU_FEATURES(pVCpu)->fSse2)
5943	IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_sfence);
5944	else
5945	IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_alt_mem_fence);
5946	IEM_MC_ADVANCE_RIP();
5947	IEM_MC_END();
5948	return VINF_SUCCESS;
5949	}
5950
5951
5952	/** Opcode 0xf3 0x0f 0xae 11b/0. */
5953	FNIEMOP_UD_STUB_1(iemOp_Grp15_rdfsbase, uint8_t, bRm);
5954
5955	/** Opcode 0xf3 0x0f 0xae 11b/1. */
5956	FNIEMOP_UD_STUB_1(iemOp_Grp15_rdgsbase, uint8_t, bRm);
5957
5958	/** Opcode 0xf3 0x0f 0xae 11b/2. */
5959	FNIEMOP_UD_STUB_1(iemOp_Grp15_wrfsbase, uint8_t, bRm);
5960
5961	/** Opcode 0xf3 0x0f 0xae 11b/3. */
5962	FNIEMOP_UD_STUB_1(iemOp_Grp15_wrgsbase, uint8_t, bRm);
5963
5964
5965	/**
5966	* Group 15 jump table for register variant.
5967	*/
5968	IEM_STATIC const PFNIEMOPRM g_apfnGroup15RegReg[] =
5969	{ /* pfx: none, 066h, 0f3h, 0f2h */
5970	/* /0 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_Grp15_rdfsbase, iemOp_InvalidWithRM,
5971	/* /1 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_Grp15_rdgsbase, iemOp_InvalidWithRM,
5972	/* /2 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_Grp15_wrfsbase, iemOp_InvalidWithRM,
5973	/* /3 */ iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_Grp15_wrgsbase, iemOp_InvalidWithRM,
5974	/* /4 */ IEMOP_X4(iemOp_InvalidWithRM),
5975	/* /5 */ iemOp_Grp15_lfence, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
5976	/* /6 */ iemOp_Grp15_mfence, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
5977	/* /7 */ iemOp_Grp15_sfence, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
5978	};
5979	AssertCompile(RT_ELEMENTS(g_apfnGroup15RegReg) == 8*4);
5980
5981
5982	/**
5983	* Group 15 jump table for memory variant.
5984	*/
5985	IEM_STATIC const PFNIEMOPRM g_apfnGroup15MemReg[] =
5986	{ /* pfx: none, 066h, 0f3h, 0f2h */
5987	/* /0 */ iemOp_Grp15_fxsave, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
5988	/* /1 */ iemOp_Grp15_fxrstor, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
5989	/* /2 */ iemOp_Grp15_ldmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
5990	/* /3 */ iemOp_Grp15_stmxcsr, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
5991	/* /4 */ iemOp_Grp15_xsave, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
5992	/* /5 */ iemOp_Grp15_xrstor, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
5993	/* /6 */ iemOp_Grp15_xsaveopt, iemOp_InvalidWithRM, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
5994	/* /7 */ iemOp_Grp15_clflush, iemOp_Grp15_clflushopt, iemOp_InvalidWithRM, iemOp_InvalidWithRM,
5995	};
5996	AssertCompile(RT_ELEMENTS(g_apfnGroup15MemReg) == 8*4);
5997
5998
5999	/** Opcode 0x0f 0xae. */
6000	FNIEMOP_DEF(iemOp_Grp15)
6001	{
6002	IEMOP_HLP_MIN_586(); /* Not entirely accurate nor needed, but useful for debugging 286 code. */
6003	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6004	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6005	/* register, register */
6006	return FNIEMOP_CALL_1(g_apfnGroup15RegReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
6007	+ pVCpu->iem.s.idxPrefix], bRm);
6008	/* memory, register */
6009	return FNIEMOP_CALL_1(g_apfnGroup15MemReg[ ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) * 4
6010	+ pVCpu->iem.s.idxPrefix], bRm);
6011	}
6012
6013
6014	/** Opcode 0x0f 0xaf. */
6015	FNIEMOP_DEF(iemOp_imul_Gv_Ev)
6016	{
6017	IEMOP_MNEMONIC(imul_Gv_Ev, "imul Gv,Ev");
6018	IEMOP_HLP_MIN_386();
6019	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF);
6020	return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_imul_two);
6021	}
6022
6023
6024	/** Opcode 0x0f 0xb0. */
6025	FNIEMOP_DEF(iemOp_cmpxchg_Eb_Gb)
6026	{
6027	IEMOP_MNEMONIC(cmpxchg_Eb_Gb, "cmpxchg Eb,Gb");
6028	IEMOP_HLP_MIN_486();
6029	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6030
6031	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6032	{
6033	IEMOP_HLP_DONE_DECODING();
6034	IEM_MC_BEGIN(4, 0);
6035	IEM_MC_ARG(uint8_t *, pu8Dst, 0);
6036	IEM_MC_ARG(uint8_t *, pu8Al, 1);
6037	IEM_MC_ARG(uint8_t, u8Src, 2);
6038	IEM_MC_ARG(uint32_t *, pEFlags, 3);
6039
6040	IEM_MC_FETCH_GREG_U8(u8Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
6041	IEM_MC_REF_GREG_U8(pu8Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6042	IEM_MC_REF_GREG_U8(pu8Al, X86_GREG_xAX);
6043	IEM_MC_REF_EFLAGS(pEFlags);
6044	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6045	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u8, pu8Dst, pu8Al, u8Src, pEFlags);
6046	else
6047	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u8_locked, pu8Dst, pu8Al, u8Src, pEFlags);
6048
6049	IEM_MC_ADVANCE_RIP();
6050	IEM_MC_END();
6051	}
6052	else
6053	{
6054	IEM_MC_BEGIN(4, 3);
6055	IEM_MC_ARG(uint8_t *, pu8Dst, 0);
6056	IEM_MC_ARG(uint8_t *, pu8Al, 1);
6057	IEM_MC_ARG(uint8_t, u8Src, 2);
6058	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
6059	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6060	IEM_MC_LOCAL(uint8_t, u8Al);
6061
6062	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6063	IEMOP_HLP_DONE_DECODING();
6064	IEM_MC_MEM_MAP(pu8Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6065	IEM_MC_FETCH_GREG_U8(u8Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
6066	IEM_MC_FETCH_GREG_U8(u8Al, X86_GREG_xAX);
6067	IEM_MC_FETCH_EFLAGS(EFlags);
6068	IEM_MC_REF_LOCAL(pu8Al, u8Al);
6069	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6070	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u8, pu8Dst, pu8Al, u8Src, pEFlags);
6071	else
6072	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u8_locked, pu8Dst, pu8Al, u8Src, pEFlags);
6073
6074	IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Dst, IEM_ACCESS_DATA_RW);
6075	IEM_MC_COMMIT_EFLAGS(EFlags);
6076	IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Al);
6077	IEM_MC_ADVANCE_RIP();
6078	IEM_MC_END();
6079	}
6080	return VINF_SUCCESS;
6081	}
6082
6083	/** Opcode 0x0f 0xb1. */
6084	FNIEMOP_DEF(iemOp_cmpxchg_Ev_Gv)
6085	{
6086	IEMOP_MNEMONIC(cmpxchg_Ev_Gv, "cmpxchg Ev,Gv");
6087	IEMOP_HLP_MIN_486();
6088	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6089
6090	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6091	{
6092	IEMOP_HLP_DONE_DECODING();
6093	switch (pVCpu->iem.s.enmEffOpSize)
6094	{
6095	case IEMMODE_16BIT:
6096	IEM_MC_BEGIN(4, 0);
6097	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
6098	IEM_MC_ARG(uint16_t *, pu16Ax, 1);
6099	IEM_MC_ARG(uint16_t, u16Src, 2);
6100	IEM_MC_ARG(uint32_t *, pEFlags, 3);
6101
6102	IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
6103	IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6104	IEM_MC_REF_GREG_U16(pu16Ax, X86_GREG_xAX);
6105	IEM_MC_REF_EFLAGS(pEFlags);
6106	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6107	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u16, pu16Dst, pu16Ax, u16Src, pEFlags);
6108	else
6109	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u16_locked, pu16Dst, pu16Ax, u16Src, pEFlags);
6110
6111	IEM_MC_ADVANCE_RIP();
6112	IEM_MC_END();
6113	return VINF_SUCCESS;
6114
6115	case IEMMODE_32BIT:
6116	IEM_MC_BEGIN(4, 0);
6117	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
6118	IEM_MC_ARG(uint32_t *, pu32Eax, 1);
6119	IEM_MC_ARG(uint32_t, u32Src, 2);
6120	IEM_MC_ARG(uint32_t *, pEFlags, 3);
6121
6122	IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
6123	IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6124	IEM_MC_REF_GREG_U32(pu32Eax, X86_GREG_xAX);
6125	IEM_MC_REF_EFLAGS(pEFlags);
6126	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6127	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u32, pu32Dst, pu32Eax, u32Src, pEFlags);
6128	else
6129	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u32_locked, pu32Dst, pu32Eax, u32Src, pEFlags);
6130
6131	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Eax);
6132	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
6133	IEM_MC_ADVANCE_RIP();
6134	IEM_MC_END();
6135	return VINF_SUCCESS;
6136
6137	case IEMMODE_64BIT:
6138	IEM_MC_BEGIN(4, 0);
6139	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
6140	IEM_MC_ARG(uint64_t *, pu64Rax, 1);
6141	#ifdef RT_ARCH_X86
6142	IEM_MC_ARG(uint64_t *, pu64Src, 2);
6143	#else
6144	IEM_MC_ARG(uint64_t, u64Src, 2);
6145	#endif
6146	IEM_MC_ARG(uint32_t *, pEFlags, 3);
6147
6148	IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6149	IEM_MC_REF_GREG_U64(pu64Rax, X86_GREG_xAX);
6150	IEM_MC_REF_EFLAGS(pEFlags);
6151	#ifdef RT_ARCH_X86
6152	IEM_MC_REF_GREG_U64(pu64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
6153	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6154	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64, pu64Dst, pu64Rax, pu64Src, pEFlags);
6155	else
6156	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64_locked, pu64Dst, pu64Rax, pu64Src, pEFlags);
6157	#else
6158	IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
6159	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6160	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64, pu64Dst, pu64Rax, u64Src, pEFlags);
6161	else
6162	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64_locked, pu64Dst, pu64Rax, u64Src, pEFlags);
6163	#endif
6164
6165	IEM_MC_ADVANCE_RIP();
6166	IEM_MC_END();
6167	return VINF_SUCCESS;
6168
6169	IEM_NOT_REACHED_DEFAULT_CASE_RET();
6170	}
6171	}
6172	else
6173	{
6174	switch (pVCpu->iem.s.enmEffOpSize)
6175	{
6176	case IEMMODE_16BIT:
6177	IEM_MC_BEGIN(4, 3);
6178	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
6179	IEM_MC_ARG(uint16_t *, pu16Ax, 1);
6180	IEM_MC_ARG(uint16_t, u16Src, 2);
6181	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
6182	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6183	IEM_MC_LOCAL(uint16_t, u16Ax);
6184
6185	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6186	IEMOP_HLP_DONE_DECODING();
6187	IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6188	IEM_MC_FETCH_GREG_U16(u16Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
6189	IEM_MC_FETCH_GREG_U16(u16Ax, X86_GREG_xAX);
6190	IEM_MC_FETCH_EFLAGS(EFlags);
6191	IEM_MC_REF_LOCAL(pu16Ax, u16Ax);
6192	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6193	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u16, pu16Dst, pu16Ax, u16Src, pEFlags);
6194	else
6195	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u16_locked, pu16Dst, pu16Ax, u16Src, pEFlags);
6196
6197	IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
6198	IEM_MC_COMMIT_EFLAGS(EFlags);
6199	IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Ax);
6200	IEM_MC_ADVANCE_RIP();
6201	IEM_MC_END();
6202	return VINF_SUCCESS;
6203
6204	case IEMMODE_32BIT:
6205	IEM_MC_BEGIN(4, 3);
6206	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
6207	IEM_MC_ARG(uint32_t *, pu32Eax, 1);
6208	IEM_MC_ARG(uint32_t, u32Src, 2);
6209	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
6210	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6211	IEM_MC_LOCAL(uint32_t, u32Eax);
6212
6213	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6214	IEMOP_HLP_DONE_DECODING();
6215	IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6216	IEM_MC_FETCH_GREG_U32(u32Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
6217	IEM_MC_FETCH_GREG_U32(u32Eax, X86_GREG_xAX);
6218	IEM_MC_FETCH_EFLAGS(EFlags);
6219	IEM_MC_REF_LOCAL(pu32Eax, u32Eax);
6220	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6221	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u32, pu32Dst, pu32Eax, u32Src, pEFlags);
6222	else
6223	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u32_locked, pu32Dst, pu32Eax, u32Src, pEFlags);
6224
6225	IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
6226	IEM_MC_COMMIT_EFLAGS(EFlags);
6227	IEM_MC_STORE_GREG_U32(X86_GREG_xAX, u32Eax);
6228	IEM_MC_ADVANCE_RIP();
6229	IEM_MC_END();
6230	return VINF_SUCCESS;
6231
6232	case IEMMODE_64BIT:
6233	IEM_MC_BEGIN(4, 3);
6234	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
6235	IEM_MC_ARG(uint64_t *, pu64Rax, 1);
6236	#ifdef RT_ARCH_X86
6237	IEM_MC_ARG(uint64_t *, pu64Src, 2);
6238	#else
6239	IEM_MC_ARG(uint64_t, u64Src, 2);
6240	#endif
6241	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3);
6242	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6243	IEM_MC_LOCAL(uint64_t, u64Rax);
6244
6245	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6246	IEMOP_HLP_DONE_DECODING();
6247	IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6248	IEM_MC_FETCH_GREG_U64(u64Rax, X86_GREG_xAX);
6249	IEM_MC_FETCH_EFLAGS(EFlags);
6250	IEM_MC_REF_LOCAL(pu64Rax, u64Rax);
6251	#ifdef RT_ARCH_X86
6252	IEM_MC_REF_GREG_U64(pu64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
6253	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6254	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64, pu64Dst, pu64Rax, pu64Src, pEFlags);
6255	else
6256	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64_locked, pu64Dst, pu64Rax, pu64Src, pEFlags);
6257	#else
6258	IEM_MC_FETCH_GREG_U64(u64Src, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
6259	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6260	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64, pu64Dst, pu64Rax, u64Src, pEFlags);
6261	else
6262	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64_locked, pu64Dst, pu64Rax, u64Src, pEFlags);
6263	#endif
6264
6265	IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
6266	IEM_MC_COMMIT_EFLAGS(EFlags);
6267	IEM_MC_STORE_GREG_U64(X86_GREG_xAX, u64Rax);
6268	IEM_MC_ADVANCE_RIP();
6269	IEM_MC_END();
6270	return VINF_SUCCESS;
6271
6272	IEM_NOT_REACHED_DEFAULT_CASE_RET();
6273	}
6274	}
6275	}
6276
6277
6278	FNIEMOP_DEF_2(iemOpCommonLoadSRegAndGreg, uint8_t, iSegReg, uint8_t, bRm)
6279	{
6280	Assert((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT)); /* Caller checks this */
6281	uint8_t const iGReg = ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg;
6282
6283	switch (pVCpu->iem.s.enmEffOpSize)
6284	{
6285	case IEMMODE_16BIT:
6286	IEM_MC_BEGIN(5, 1);
6287	IEM_MC_ARG(uint16_t, uSel, 0);
6288	IEM_MC_ARG(uint16_t, offSeg, 1);
6289	IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/=/iSegReg, 2);
6290	IEM_MC_ARG_CONST(uint8_t, iGRegArg, /=/iGReg, 3);
6291	IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/=/pVCpu->iem.s.enmEffOpSize, 4);
6292	IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
6293	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
6294	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6295	IEM_MC_FETCH_MEM_U16(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
6296	IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 2);
6297	IEM_MC_CALL_CIMPL_5(iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
6298	IEM_MC_END();
6299	return VINF_SUCCESS;
6300
6301	case IEMMODE_32BIT:
6302	IEM_MC_BEGIN(5, 1);
6303	IEM_MC_ARG(uint16_t, uSel, 0);
6304	IEM_MC_ARG(uint32_t, offSeg, 1);
6305	IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/=/iSegReg, 2);
6306	IEM_MC_ARG_CONST(uint8_t, iGRegArg, /=/iGReg, 3);
6307	IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/=/pVCpu->iem.s.enmEffOpSize, 4);
6308	IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
6309	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
6310	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6311	IEM_MC_FETCH_MEM_U32(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
6312	IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 4);
6313	IEM_MC_CALL_CIMPL_5(iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
6314	IEM_MC_END();
6315	return VINF_SUCCESS;
6316
6317	case IEMMODE_64BIT:
6318	IEM_MC_BEGIN(5, 1);
6319	IEM_MC_ARG(uint16_t, uSel, 0);
6320	IEM_MC_ARG(uint64_t, offSeg, 1);
6321	IEM_MC_ARG_CONST(uint8_t, iSegRegArg,/=/iSegReg, 2);
6322	IEM_MC_ARG_CONST(uint8_t, iGRegArg, /=/iGReg, 3);
6323	IEM_MC_ARG_CONST(IEMMODE, enmEffOpSize,/=/pVCpu->iem.s.enmEffOpSize, 4);
6324	IEM_MC_LOCAL(RTGCPTR, GCPtrEff);
6325	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEff, bRm, 0);
6326	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6327	if (IEM_IS_GUEST_CPU_AMD(pVCpu)) /** @todo testcase: rev 3.15 of the amd manuals claims it only loads a 32-bit greg. */
6328	IEM_MC_FETCH_MEM_U32_SX_U64(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
6329	else
6330	IEM_MC_FETCH_MEM_U64(offSeg, pVCpu->iem.s.iEffSeg, GCPtrEff);
6331	IEM_MC_FETCH_MEM_U16_DISP(uSel, pVCpu->iem.s.iEffSeg, GCPtrEff, 8);
6332	IEM_MC_CALL_CIMPL_5(iemCImpl_load_SReg_Greg, uSel, offSeg, iSegRegArg, iGRegArg, enmEffOpSize);
6333	IEM_MC_END();
6334	return VINF_SUCCESS;
6335
6336	IEM_NOT_REACHED_DEFAULT_CASE_RET();
6337	}
6338	}
6339
6340
6341	/** Opcode 0x0f 0xb2. */
6342	FNIEMOP_DEF(iemOp_lss_Gv_Mp)
6343	{
6344	IEMOP_MNEMONIC(lss_Gv_Mp, "lss Gv,Mp");
6345	IEMOP_HLP_MIN_386();
6346	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6347	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6348	return IEMOP_RAISE_INVALID_OPCODE();
6349	return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_SS, bRm);
6350	}
6351
6352
6353	/** Opcode 0x0f 0xb3. */
6354	FNIEMOP_DEF(iemOp_btr_Ev_Gv)
6355	{
6356	IEMOP_MNEMONIC(btr_Ev_Gv, "btr Ev,Gv");
6357	IEMOP_HLP_MIN_386();
6358	return FNIEMOP_CALL_1(iemOpCommonBit_Ev_Gv, &g_iemAImpl_btr);
6359	}
6360
6361
6362	/** Opcode 0x0f 0xb4. */
6363	FNIEMOP_DEF(iemOp_lfs_Gv_Mp)
6364	{
6365	IEMOP_MNEMONIC(lfs_Gv_Mp, "lfs Gv,Mp");
6366	IEMOP_HLP_MIN_386();
6367	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6368	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6369	return IEMOP_RAISE_INVALID_OPCODE();
6370	return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_FS, bRm);
6371	}
6372
6373
6374	/** Opcode 0x0f 0xb5. */
6375	FNIEMOP_DEF(iemOp_lgs_Gv_Mp)
6376	{
6377	IEMOP_MNEMONIC(lgs_Gv_Mp, "lgs Gv,Mp");
6378	IEMOP_HLP_MIN_386();
6379	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6380	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6381	return IEMOP_RAISE_INVALID_OPCODE();
6382	return FNIEMOP_CALL_2(iemOpCommonLoadSRegAndGreg, X86_SREG_GS, bRm);
6383	}
6384
6385
6386	/** Opcode 0x0f 0xb6. */
6387	FNIEMOP_DEF(iemOp_movzx_Gv_Eb)
6388	{
6389	IEMOP_MNEMONIC(movzx_Gv_Eb, "movzx Gv,Eb");
6390	IEMOP_HLP_MIN_386();
6391
6392	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6393
6394	/*
6395	* If rm is denoting a register, no more instruction bytes.
6396	*/
6397	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6398	{
6399	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6400	switch (pVCpu->iem.s.enmEffOpSize)
6401	{
6402	case IEMMODE_16BIT:
6403	IEM_MC_BEGIN(0, 1);
6404	IEM_MC_LOCAL(uint16_t, u16Value);
6405	IEM_MC_FETCH_GREG_U8_ZX_U16(u16Value, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6406	IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u16Value);
6407	IEM_MC_ADVANCE_RIP();
6408	IEM_MC_END();
6409	return VINF_SUCCESS;
6410
6411	case IEMMODE_32BIT:
6412	IEM_MC_BEGIN(0, 1);
6413	IEM_MC_LOCAL(uint32_t, u32Value);
6414	IEM_MC_FETCH_GREG_U8_ZX_U32(u32Value, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6415	IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u32Value);
6416	IEM_MC_ADVANCE_RIP();
6417	IEM_MC_END();
6418	return VINF_SUCCESS;
6419
6420	case IEMMODE_64BIT:
6421	IEM_MC_BEGIN(0, 1);
6422	IEM_MC_LOCAL(uint64_t, u64Value);
6423	IEM_MC_FETCH_GREG_U8_ZX_U64(u64Value, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6424	IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u64Value);
6425	IEM_MC_ADVANCE_RIP();
6426	IEM_MC_END();
6427	return VINF_SUCCESS;
6428
6429	IEM_NOT_REACHED_DEFAULT_CASE_RET();
6430	}
6431	}
6432	else
6433	{
6434	/*
6435	* We're loading a register from memory.
6436	*/
6437	switch (pVCpu->iem.s.enmEffOpSize)
6438	{
6439	case IEMMODE_16BIT:
6440	IEM_MC_BEGIN(0, 2);
6441	IEM_MC_LOCAL(uint16_t, u16Value);
6442	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6443	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6444	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6445	IEM_MC_FETCH_MEM_U8_ZX_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
6446	IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u16Value);
6447	IEM_MC_ADVANCE_RIP();
6448	IEM_MC_END();
6449	return VINF_SUCCESS;
6450
6451	case IEMMODE_32BIT:
6452	IEM_MC_BEGIN(0, 2);
6453	IEM_MC_LOCAL(uint32_t, u32Value);
6454	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6455	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6456	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6457	IEM_MC_FETCH_MEM_U8_ZX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
6458	IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u32Value);
6459	IEM_MC_ADVANCE_RIP();
6460	IEM_MC_END();
6461	return VINF_SUCCESS;
6462
6463	case IEMMODE_64BIT:
6464	IEM_MC_BEGIN(0, 2);
6465	IEM_MC_LOCAL(uint64_t, u64Value);
6466	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6467	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6468	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6469	IEM_MC_FETCH_MEM_U8_ZX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
6470	IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u64Value);
6471	IEM_MC_ADVANCE_RIP();
6472	IEM_MC_END();
6473	return VINF_SUCCESS;
6474
6475	IEM_NOT_REACHED_DEFAULT_CASE_RET();
6476	}
6477	}
6478	}
6479
6480
6481	/** Opcode 0x0f 0xb7. */
6482	FNIEMOP_DEF(iemOp_movzx_Gv_Ew)
6483	{
6484	IEMOP_MNEMONIC(movzx_Gv_Ew, "movzx Gv,Ew");
6485	IEMOP_HLP_MIN_386();
6486
6487	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6488
6489	/** @todo Not entirely sure how the operand size prefix is handled here,
6490	* assuming that it will be ignored. Would be nice to have a few
6491	* test for this. */
6492	/*
6493	* If rm is denoting a register, no more instruction bytes.
6494	*/
6495	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6496	{
6497	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6498	if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
6499	{
6500	IEM_MC_BEGIN(0, 1);
6501	IEM_MC_LOCAL(uint32_t, u32Value);
6502	IEM_MC_FETCH_GREG_U16_ZX_U32(u32Value, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6503	IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u32Value);
6504	IEM_MC_ADVANCE_RIP();
6505	IEM_MC_END();
6506	}
6507	else
6508	{
6509	IEM_MC_BEGIN(0, 1);
6510	IEM_MC_LOCAL(uint64_t, u64Value);
6511	IEM_MC_FETCH_GREG_U16_ZX_U64(u64Value, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6512	IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u64Value);
6513	IEM_MC_ADVANCE_RIP();
6514	IEM_MC_END();
6515	}
6516	}
6517	else
6518	{
6519	/*
6520	* We're loading a register from memory.
6521	*/
6522	if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
6523	{
6524	IEM_MC_BEGIN(0, 2);
6525	IEM_MC_LOCAL(uint32_t, u32Value);
6526	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6527	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6528	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6529	IEM_MC_FETCH_MEM_U16_ZX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
6530	IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u32Value);
6531	IEM_MC_ADVANCE_RIP();
6532	IEM_MC_END();
6533	}
6534	else
6535	{
6536	IEM_MC_BEGIN(0, 2);
6537	IEM_MC_LOCAL(uint64_t, u64Value);
6538	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6539	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6540	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6541	IEM_MC_FETCH_MEM_U16_ZX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
6542	IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u64Value);
6543	IEM_MC_ADVANCE_RIP();
6544	IEM_MC_END();
6545	}
6546	}
6547	return VINF_SUCCESS;
6548	}
6549
6550
6551	/** Opcode 0x0f 0xb8 - JMPE (reserved for emulator on IPF) */
6552	FNIEMOP_UD_STUB(iemOp_jmpe);
6553	/** Opcode 0xf3 0x0f 0xb8 - POPCNT Gv, Ev */
6554	FNIEMOP_STUB(iemOp_popcnt_Gv_Ev);
6555
6556
6557	/**
6558	* @opcode 0xb9
6559	* @opinvalid intel-modrm
6560	* @optest op1=1 op2=2 ->
6561	* @oponlytest
6562	*/
6563	FNIEMOP_DEF(iemOp_Grp10)
6564	{
6565	/*
6566	* AMD does not decode beyond the 0xb9 whereas intel does the modr/m bit
6567	* too. See bs3-cpu-decoder-1.c32. So, we can forward to iemOp_InvalidNeedRM.
6568	*/
6569	/** @todo fix bs3-cpu-generated-1 to deal with this on AMD! */
6570	Log(("iemOp_Grp10 aka UD1 -> #UD\n"));
6571	IEMOP_MNEMONIC2EX(ud1, "ud1", RM, UD1, ud1, Gb, Eb, DISOPTYPE_INVALID, IEMOPHINT_IGNORES_OP_SIZE); /* just picked Gb,Eb here. */
6572	return FNIEMOP_CALL(iemOp_InvalidNeedRM);
6573	}
6574
6575
6576	/** Opcode 0x0f 0xba. */
6577	FNIEMOP_DEF(iemOp_Grp8)
6578	{
6579	IEMOP_HLP_MIN_386();
6580	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6581	PCIEMOPBINSIZES pImpl;
6582	switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
6583	{
6584	case 0: case 1: case 2: case 3:
6585	return IEMOP_RAISE_INVALID_OPCODE();
6586	case 4: pImpl = &g_iemAImpl_bt; IEMOP_MNEMONIC(bt_Ev_Ib, "bt Ev,Ib"); break;
6587	case 5: pImpl = &g_iemAImpl_bts; IEMOP_MNEMONIC(bts_Ev_Ib, "bts Ev,Ib"); break;
6588	case 6: pImpl = &g_iemAImpl_btr; IEMOP_MNEMONIC(btr_Ev_Ib, "btr Ev,Ib"); break;
6589	case 7: pImpl = &g_iemAImpl_btc; IEMOP_MNEMONIC(btc_Ev_Ib, "btc Ev,Ib"); break;
6590	IEM_NOT_REACHED_DEFAULT_CASE_RET();
6591	}
6592	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF \| X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF);
6593
6594	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6595	{
6596	/* register destination. */
6597	uint8_t u8Bit; IEM_OPCODE_GET_NEXT_U8(&u8Bit);
6598	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6599
6600	switch (pVCpu->iem.s.enmEffOpSize)
6601	{
6602	case IEMMODE_16BIT:
6603	IEM_MC_BEGIN(3, 0);
6604	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
6605	IEM_MC_ARG_CONST(uint16_t, u16Src, /=/ u8Bit & 0x0f, 1);
6606	IEM_MC_ARG(uint32_t *, pEFlags, 2);
6607
6608	IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6609	IEM_MC_REF_EFLAGS(pEFlags);
6610	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
6611
6612	IEM_MC_ADVANCE_RIP();
6613	IEM_MC_END();
6614	return VINF_SUCCESS;
6615
6616	case IEMMODE_32BIT:
6617	IEM_MC_BEGIN(3, 0);
6618	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
6619	IEM_MC_ARG_CONST(uint32_t, u32Src, /=/ u8Bit & 0x1f, 1);
6620	IEM_MC_ARG(uint32_t *, pEFlags, 2);
6621
6622	IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6623	IEM_MC_REF_EFLAGS(pEFlags);
6624	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
6625
6626	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
6627	IEM_MC_ADVANCE_RIP();
6628	IEM_MC_END();
6629	return VINF_SUCCESS;
6630
6631	case IEMMODE_64BIT:
6632	IEM_MC_BEGIN(3, 0);
6633	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
6634	IEM_MC_ARG_CONST(uint64_t, u64Src, /=/ u8Bit & 0x3f, 1);
6635	IEM_MC_ARG(uint32_t *, pEFlags, 2);
6636
6637	IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6638	IEM_MC_REF_EFLAGS(pEFlags);
6639	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
6640
6641	IEM_MC_ADVANCE_RIP();
6642	IEM_MC_END();
6643	return VINF_SUCCESS;
6644
6645	IEM_NOT_REACHED_DEFAULT_CASE_RET();
6646	}
6647	}
6648	else
6649	{
6650	/* memory destination. */
6651
6652	uint32_t fAccess;
6653	if (pImpl->pfnLockedU16)
6654	fAccess = IEM_ACCESS_DATA_RW;
6655	else /* BT */
6656	fAccess = IEM_ACCESS_DATA_R;
6657
6658	/** @todo test negative bit offsets! */
6659	switch (pVCpu->iem.s.enmEffOpSize)
6660	{
6661	case IEMMODE_16BIT:
6662	IEM_MC_BEGIN(3, 1);
6663	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
6664	IEM_MC_ARG(uint16_t, u16Src, 1);
6665	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
6666	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6667
6668	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
6669	uint8_t u8Bit; IEM_OPCODE_GET_NEXT_U8(&u8Bit);
6670	IEM_MC_ASSIGN(u16Src, u8Bit & 0x0f);
6671	if (pImpl->pfnLockedU16)
6672	IEMOP_HLP_DONE_DECODING();
6673	else
6674	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6675	IEM_MC_FETCH_EFLAGS(EFlags);
6676	IEM_MC_MEM_MAP(pu16Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6677	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6678	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags);
6679	else
6680	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU16, pu16Dst, u16Src, pEFlags);
6681	IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, fAccess);
6682
6683	IEM_MC_COMMIT_EFLAGS(EFlags);
6684	IEM_MC_ADVANCE_RIP();
6685	IEM_MC_END();
6686	return VINF_SUCCESS;
6687
6688	case IEMMODE_32BIT:
6689	IEM_MC_BEGIN(3, 1);
6690	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
6691	IEM_MC_ARG(uint32_t, u32Src, 1);
6692	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
6693	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6694
6695	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
6696	uint8_t u8Bit; IEM_OPCODE_GET_NEXT_U8(&u8Bit);
6697	IEM_MC_ASSIGN(u32Src, u8Bit & 0x1f);
6698	if (pImpl->pfnLockedU16)
6699	IEMOP_HLP_DONE_DECODING();
6700	else
6701	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6702	IEM_MC_FETCH_EFLAGS(EFlags);
6703	IEM_MC_MEM_MAP(pu32Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6704	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6705	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags);
6706	else
6707	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU32, pu32Dst, u32Src, pEFlags);
6708	IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, fAccess);
6709
6710	IEM_MC_COMMIT_EFLAGS(EFlags);
6711	IEM_MC_ADVANCE_RIP();
6712	IEM_MC_END();
6713	return VINF_SUCCESS;
6714
6715	case IEMMODE_64BIT:
6716	IEM_MC_BEGIN(3, 1);
6717	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
6718	IEM_MC_ARG(uint64_t, u64Src, 1);
6719	IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);
6720	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6721
6722	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);
6723	uint8_t u8Bit; IEM_OPCODE_GET_NEXT_U8(&u8Bit);
6724	IEM_MC_ASSIGN(u64Src, u8Bit & 0x3f);
6725	if (pImpl->pfnLockedU16)
6726	IEMOP_HLP_DONE_DECODING();
6727	else
6728	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6729	IEM_MC_FETCH_EFLAGS(EFlags);
6730	IEM_MC_MEM_MAP(pu64Dst, fAccess, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0);
6731	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6732	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags);
6733	else
6734	IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnLockedU64, pu64Dst, u64Src, pEFlags);
6735	IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, fAccess);
6736
6737	IEM_MC_COMMIT_EFLAGS(EFlags);
6738	IEM_MC_ADVANCE_RIP();
6739	IEM_MC_END();
6740	return VINF_SUCCESS;
6741
6742	IEM_NOT_REACHED_DEFAULT_CASE_RET();
6743	}
6744	}
6745
6746	}
6747
6748
6749	/** Opcode 0x0f 0xbb. */
6750	FNIEMOP_DEF(iemOp_btc_Ev_Gv)
6751	{
6752	IEMOP_MNEMONIC(btc_Ev_Gv, "btc Ev,Gv");
6753	IEMOP_HLP_MIN_386();
6754	return FNIEMOP_CALL_1(iemOpCommonBit_Ev_Gv, &g_iemAImpl_btc);
6755	}
6756
6757
6758	/** Opcode 0x0f 0xbc. */
6759	FNIEMOP_DEF(iemOp_bsf_Gv_Ev)
6760	{
6761	IEMOP_MNEMONIC(bsf_Gv_Ev, "bsf Gv,Ev");
6762	IEMOP_HLP_MIN_386();
6763	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF \| X86_EFL_SF \| X86_EFL_AF \| X86_EFL_PF \| X86_EFL_CF);
6764	return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_bsf);
6765	}
6766
6767
6768	/** Opcode 0xf3 0x0f 0xbc - TZCNT Gv, Ev */
6769	FNIEMOP_STUB(iemOp_tzcnt_Gv_Ev);
6770
6771
6772	/** Opcode 0x0f 0xbd. */
6773	FNIEMOP_DEF(iemOp_bsr_Gv_Ev)
6774	{
6775	IEMOP_MNEMONIC(bsr_Gv_Ev, "bsr Gv,Ev");
6776	IEMOP_HLP_MIN_386();
6777	IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF \| X86_EFL_SF \| X86_EFL_AF \| X86_EFL_PF \| X86_EFL_CF);
6778	return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_bsr);
6779	}
6780
6781
6782	/** Opcode 0xf3 0x0f 0xbd - LZCNT Gv, Ev */
6783	FNIEMOP_STUB(iemOp_lzcnt_Gv_Ev);
6784
6785
6786	/** Opcode 0x0f 0xbe. */
6787	FNIEMOP_DEF(iemOp_movsx_Gv_Eb)
6788	{
6789	IEMOP_MNEMONIC(movsx_Gv_Eb, "movsx Gv,Eb");
6790	IEMOP_HLP_MIN_386();
6791
6792	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6793
6794	/*
6795	* If rm is denoting a register, no more instruction bytes.
6796	*/
6797	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6798	{
6799	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6800	switch (pVCpu->iem.s.enmEffOpSize)
6801	{
6802	case IEMMODE_16BIT:
6803	IEM_MC_BEGIN(0, 1);
6804	IEM_MC_LOCAL(uint16_t, u16Value);
6805	IEM_MC_FETCH_GREG_U8_SX_U16(u16Value, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6806	IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u16Value);
6807	IEM_MC_ADVANCE_RIP();
6808	IEM_MC_END();
6809	return VINF_SUCCESS;
6810
6811	case IEMMODE_32BIT:
6812	IEM_MC_BEGIN(0, 1);
6813	IEM_MC_LOCAL(uint32_t, u32Value);
6814	IEM_MC_FETCH_GREG_U8_SX_U32(u32Value, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6815	IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u32Value);
6816	IEM_MC_ADVANCE_RIP();
6817	IEM_MC_END();
6818	return VINF_SUCCESS;
6819
6820	case IEMMODE_64BIT:
6821	IEM_MC_BEGIN(0, 1);
6822	IEM_MC_LOCAL(uint64_t, u64Value);
6823	IEM_MC_FETCH_GREG_U8_SX_U64(u64Value, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6824	IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u64Value);
6825	IEM_MC_ADVANCE_RIP();
6826	IEM_MC_END();
6827	return VINF_SUCCESS;
6828
6829	IEM_NOT_REACHED_DEFAULT_CASE_RET();
6830	}
6831	}
6832	else
6833	{
6834	/*
6835	* We're loading a register from memory.
6836	*/
6837	switch (pVCpu->iem.s.enmEffOpSize)
6838	{
6839	case IEMMODE_16BIT:
6840	IEM_MC_BEGIN(0, 2);
6841	IEM_MC_LOCAL(uint16_t, u16Value);
6842	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6843	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6844	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6845	IEM_MC_FETCH_MEM_U8_SX_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
6846	IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u16Value);
6847	IEM_MC_ADVANCE_RIP();
6848	IEM_MC_END();
6849	return VINF_SUCCESS;
6850
6851	case IEMMODE_32BIT:
6852	IEM_MC_BEGIN(0, 2);
6853	IEM_MC_LOCAL(uint32_t, u32Value);
6854	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6855	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6856	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6857	IEM_MC_FETCH_MEM_U8_SX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
6858	IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u32Value);
6859	IEM_MC_ADVANCE_RIP();
6860	IEM_MC_END();
6861	return VINF_SUCCESS;
6862
6863	case IEMMODE_64BIT:
6864	IEM_MC_BEGIN(0, 2);
6865	IEM_MC_LOCAL(uint64_t, u64Value);
6866	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6867	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6868	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6869	IEM_MC_FETCH_MEM_U8_SX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
6870	IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u64Value);
6871	IEM_MC_ADVANCE_RIP();
6872	IEM_MC_END();
6873	return VINF_SUCCESS;
6874
6875	IEM_NOT_REACHED_DEFAULT_CASE_RET();
6876	}
6877	}
6878	}
6879
6880
6881	/** Opcode 0x0f 0xbf. */
6882	FNIEMOP_DEF(iemOp_movsx_Gv_Ew)
6883	{
6884	IEMOP_MNEMONIC(movsx_Gv_Ew, "movsx Gv,Ew");
6885	IEMOP_HLP_MIN_386();
6886
6887	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6888
6889	/** @todo Not entirely sure how the operand size prefix is handled here,
6890	* assuming that it will be ignored. Would be nice to have a few
6891	* test for this. */
6892	/*
6893	* If rm is denoting a register, no more instruction bytes.
6894	*/
6895	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6896	{
6897	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6898	if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
6899	{
6900	IEM_MC_BEGIN(0, 1);
6901	IEM_MC_LOCAL(uint32_t, u32Value);
6902	IEM_MC_FETCH_GREG_U16_SX_U32(u32Value, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6903	IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u32Value);
6904	IEM_MC_ADVANCE_RIP();
6905	IEM_MC_END();
6906	}
6907	else
6908	{
6909	IEM_MC_BEGIN(0, 1);
6910	IEM_MC_LOCAL(uint64_t, u64Value);
6911	IEM_MC_FETCH_GREG_U16_SX_U64(u64Value, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6912	IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u64Value);
6913	IEM_MC_ADVANCE_RIP();
6914	IEM_MC_END();
6915	}
6916	}
6917	else
6918	{
6919	/*
6920	* We're loading a register from memory.
6921	*/
6922	if (pVCpu->iem.s.enmEffOpSize != IEMMODE_64BIT)
6923	{
6924	IEM_MC_BEGIN(0, 2);
6925	IEM_MC_LOCAL(uint32_t, u32Value);
6926	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6927	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6928	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6929	IEM_MC_FETCH_MEM_U16_SX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
6930	IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u32Value);
6931	IEM_MC_ADVANCE_RIP();
6932	IEM_MC_END();
6933	}
6934	else
6935	{
6936	IEM_MC_BEGIN(0, 2);
6937	IEM_MC_LOCAL(uint64_t, u64Value);
6938	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6939	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6940	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6941	IEM_MC_FETCH_MEM_U16_SX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
6942	IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u64Value);
6943	IEM_MC_ADVANCE_RIP();
6944	IEM_MC_END();
6945	}
6946	}
6947	return VINF_SUCCESS;
6948	}
6949
6950
6951	/** Opcode 0x0f 0xc0. */
6952	FNIEMOP_DEF(iemOp_xadd_Eb_Gb)
6953	{
6954	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
6955	IEMOP_HLP_MIN_486();
6956	IEMOP_MNEMONIC(xadd_Eb_Gb, "xadd Eb,Gb");
6957
6958	/*
6959	* If rm is denoting a register, no more instruction bytes.
6960	*/
6961	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
6962	{
6963	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
6964
6965	IEM_MC_BEGIN(3, 0);
6966	IEM_MC_ARG(uint8_t *, pu8Dst, 0);
6967	IEM_MC_ARG(uint8_t *, pu8Reg, 1);
6968	IEM_MC_ARG(uint32_t *, pEFlags, 2);
6969
6970	IEM_MC_REF_GREG_U8(pu8Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
6971	IEM_MC_REF_GREG_U8(pu8Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
6972	IEM_MC_REF_EFLAGS(pEFlags);
6973	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u8, pu8Dst, pu8Reg, pEFlags);
6974
6975	IEM_MC_ADVANCE_RIP();
6976	IEM_MC_END();
6977	}
6978	else
6979	{
6980	/*
6981	* We're accessing memory.
6982	*/
6983	IEM_MC_BEGIN(3, 3);
6984	IEM_MC_ARG(uint8_t *, pu8Dst, 0);
6985	IEM_MC_ARG(uint8_t *, pu8Reg, 1);
6986	IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
6987	IEM_MC_LOCAL(uint8_t, u8RegCopy);
6988	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
6989
6990	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
6991	IEM_MC_MEM_MAP(pu8Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /arg/);
6992	IEM_MC_FETCH_GREG_U8(u8RegCopy, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
6993	IEM_MC_REF_LOCAL(pu8Reg, u8RegCopy);
6994	IEM_MC_FETCH_EFLAGS(EFlags);
6995	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
6996	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u8, pu8Dst, pu8Reg, pEFlags);
6997	else
6998	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u8_locked, pu8Dst, pu8Reg, pEFlags);
6999
7000	IEM_MC_MEM_COMMIT_AND_UNMAP(pu8Dst, IEM_ACCESS_DATA_RW);
7001	IEM_MC_COMMIT_EFLAGS(EFlags);
7002	IEM_MC_STORE_GREG_U8(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u8RegCopy);
7003	IEM_MC_ADVANCE_RIP();
7004	IEM_MC_END();
7005	return VINF_SUCCESS;
7006	}
7007	return VINF_SUCCESS;
7008	}
7009
7010
7011	/** Opcode 0x0f 0xc1. */
7012	FNIEMOP_DEF(iemOp_xadd_Ev_Gv)
7013	{
7014	IEMOP_MNEMONIC(xadd_Ev_Gv, "xadd Ev,Gv");
7015	IEMOP_HLP_MIN_486();
7016	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7017
7018	/*
7019	* If rm is denoting a register, no more instruction bytes.
7020	*/
7021	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7022	{
7023	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7024
7025	switch (pVCpu->iem.s.enmEffOpSize)
7026	{
7027	case IEMMODE_16BIT:
7028	IEM_MC_BEGIN(3, 0);
7029	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
7030	IEM_MC_ARG(uint16_t *, pu16Reg, 1);
7031	IEM_MC_ARG(uint32_t *, pEFlags, 2);
7032
7033	IEM_MC_REF_GREG_U16(pu16Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
7034	IEM_MC_REF_GREG_U16(pu16Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
7035	IEM_MC_REF_EFLAGS(pEFlags);
7036	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u16, pu16Dst, pu16Reg, pEFlags);
7037
7038	IEM_MC_ADVANCE_RIP();
7039	IEM_MC_END();
7040	return VINF_SUCCESS;
7041
7042	case IEMMODE_32BIT:
7043	IEM_MC_BEGIN(3, 0);
7044	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
7045	IEM_MC_ARG(uint32_t *, pu32Reg, 1);
7046	IEM_MC_ARG(uint32_t *, pEFlags, 2);
7047
7048	IEM_MC_REF_GREG_U32(pu32Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
7049	IEM_MC_REF_GREG_U32(pu32Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
7050	IEM_MC_REF_EFLAGS(pEFlags);
7051	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u32, pu32Dst, pu32Reg, pEFlags);
7052
7053	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
7054	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Reg);
7055	IEM_MC_ADVANCE_RIP();
7056	IEM_MC_END();
7057	return VINF_SUCCESS;
7058
7059	case IEMMODE_64BIT:
7060	IEM_MC_BEGIN(3, 0);
7061	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
7062	IEM_MC_ARG(uint64_t *, pu64Reg, 1);
7063	IEM_MC_ARG(uint32_t *, pEFlags, 2);
7064
7065	IEM_MC_REF_GREG_U64(pu64Dst, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
7066	IEM_MC_REF_GREG_U64(pu64Reg, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
7067	IEM_MC_REF_EFLAGS(pEFlags);
7068	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u64, pu64Dst, pu64Reg, pEFlags);
7069
7070	IEM_MC_ADVANCE_RIP();
7071	IEM_MC_END();
7072	return VINF_SUCCESS;
7073
7074	IEM_NOT_REACHED_DEFAULT_CASE_RET();
7075	}
7076	}
7077	else
7078	{
7079	/*
7080	* We're accessing memory.
7081	*/
7082	switch (pVCpu->iem.s.enmEffOpSize)
7083	{
7084	case IEMMODE_16BIT:
7085	IEM_MC_BEGIN(3, 3);
7086	IEM_MC_ARG(uint16_t *, pu16Dst, 0);
7087	IEM_MC_ARG(uint16_t *, pu16Reg, 1);
7088	IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
7089	IEM_MC_LOCAL(uint16_t, u16RegCopy);
7090	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7091
7092	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7093	IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /arg/);
7094	IEM_MC_FETCH_GREG_U16(u16RegCopy, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
7095	IEM_MC_REF_LOCAL(pu16Reg, u16RegCopy);
7096	IEM_MC_FETCH_EFLAGS(EFlags);
7097	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7098	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u16, pu16Dst, pu16Reg, pEFlags);
7099	else
7100	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u16_locked, pu16Dst, pu16Reg, pEFlags);
7101
7102	IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW);
7103	IEM_MC_COMMIT_EFLAGS(EFlags);
7104	IEM_MC_STORE_GREG_U16(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u16RegCopy);
7105	IEM_MC_ADVANCE_RIP();
7106	IEM_MC_END();
7107	return VINF_SUCCESS;
7108
7109	case IEMMODE_32BIT:
7110	IEM_MC_BEGIN(3, 3);
7111	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
7112	IEM_MC_ARG(uint32_t *, pu32Reg, 1);
7113	IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
7114	IEM_MC_LOCAL(uint32_t, u32RegCopy);
7115	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7116
7117	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7118	IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /arg/);
7119	IEM_MC_FETCH_GREG_U32(u32RegCopy, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
7120	IEM_MC_REF_LOCAL(pu32Reg, u32RegCopy);
7121	IEM_MC_FETCH_EFLAGS(EFlags);
7122	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7123	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u32, pu32Dst, pu32Reg, pEFlags);
7124	else
7125	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u32_locked, pu32Dst, pu32Reg, pEFlags);
7126
7127	IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW);
7128	IEM_MC_COMMIT_EFLAGS(EFlags);
7129	IEM_MC_STORE_GREG_U32(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u32RegCopy);
7130	IEM_MC_ADVANCE_RIP();
7131	IEM_MC_END();
7132	return VINF_SUCCESS;
7133
7134	case IEMMODE_64BIT:
7135	IEM_MC_BEGIN(3, 3);
7136	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
7137	IEM_MC_ARG(uint64_t *, pu64Reg, 1);
7138	IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2);
7139	IEM_MC_LOCAL(uint64_t, u64RegCopy);
7140	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7141
7142	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7143	IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /arg/);
7144	IEM_MC_FETCH_GREG_U64(u64RegCopy, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
7145	IEM_MC_REF_LOCAL(pu64Reg, u64RegCopy);
7146	IEM_MC_FETCH_EFLAGS(EFlags);
7147	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7148	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u64, pu64Dst, pu64Reg, pEFlags);
7149	else
7150	IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u64_locked, pu64Dst, pu64Reg, pEFlags);
7151
7152	IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW);
7153	IEM_MC_COMMIT_EFLAGS(EFlags);
7154	IEM_MC_STORE_GREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg, u64RegCopy);
7155	IEM_MC_ADVANCE_RIP();
7156	IEM_MC_END();
7157	return VINF_SUCCESS;
7158
7159	IEM_NOT_REACHED_DEFAULT_CASE_RET();
7160	}
7161	}
7162	}
7163
7164
7165	/** Opcode 0x0f 0xc2 - vcmpps Vps,Hps,Wps,Ib */
7166	FNIEMOP_STUB(iemOp_vcmpps_Vps_Hps_Wps_Ib);
7167	/** Opcode 0x66 0x0f 0xc2 - vcmppd Vpd,Hpd,Wpd,Ib */
7168	FNIEMOP_STUB(iemOp_vcmppd_Vpd_Hpd_Wpd_Ib);
7169	/** Opcode 0xf3 0x0f 0xc2 - vcmpss Vss,Hss,Wss,Ib */
7170	FNIEMOP_STUB(iemOp_vcmpss_Vss_Hss_Wss_Ib);
7171	/** Opcode 0xf2 0x0f 0xc2 - vcmpsd Vsd,Hsd,Wsd,Ib */
7172	FNIEMOP_STUB(iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib);
7173
7174
7175	/** Opcode 0x0f 0xc3. */
7176	FNIEMOP_DEF(iemOp_movnti_My_Gy)
7177	{
7178	IEMOP_MNEMONIC(movnti_My_Gy, "movnti My,Gy");
7179
7180	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7181
7182	/* Only the register -> memory form makes sense, assuming #UD for the other form. */
7183	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
7184	{
7185	switch (pVCpu->iem.s.enmEffOpSize)
7186	{
7187	case IEMMODE_32BIT:
7188	IEM_MC_BEGIN(0, 2);
7189	IEM_MC_LOCAL(uint32_t, u32Value);
7190	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7191
7192	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7193	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7194	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
7195	return IEMOP_RAISE_INVALID_OPCODE();
7196
7197	IEM_MC_FETCH_GREG_U32(u32Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
7198	IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u32Value);
7199	IEM_MC_ADVANCE_RIP();
7200	IEM_MC_END();
7201	break;
7202
7203	case IEMMODE_64BIT:
7204	IEM_MC_BEGIN(0, 2);
7205	IEM_MC_LOCAL(uint64_t, u64Value);
7206	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7207
7208	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7209	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7210	if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2)
7211	return IEMOP_RAISE_INVALID_OPCODE();
7212
7213	IEM_MC_FETCH_GREG_U64(u64Value, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
7214	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u64Value);
7215	IEM_MC_ADVANCE_RIP();
7216	IEM_MC_END();
7217	break;
7218
7219	case IEMMODE_16BIT:
7220	/** @todo check this form. */
7221	return IEMOP_RAISE_INVALID_OPCODE();
7222	}
7223	}
7224	else
7225	return IEMOP_RAISE_INVALID_OPCODE();
7226	return VINF_SUCCESS;
7227	}
7228	/* Opcode 0x66 0x0f 0xc3 - invalid */
7229	/* Opcode 0xf3 0x0f 0xc3 - invalid */
7230	/* Opcode 0xf2 0x0f 0xc3 - invalid */
7231
7232	/** Opcode 0x0f 0xc4 - pinsrw Pq,Ry/Mw,Ib */
7233	FNIEMOP_STUB(iemOp_pinsrw_Pq_RyMw_Ib);
7234	/** Opcode 0x66 0x0f 0xc4 - vpinsrw Vdq,Hdq,Ry/Mw,Ib */
7235	FNIEMOP_STUB(iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib);
7236	/* Opcode 0xf3 0x0f 0xc4 - invalid */
7237	/* Opcode 0xf2 0x0f 0xc4 - invalid */
7238
7239	/** Opcode 0x0f 0xc5 - pextrw Gd, Nq, Ib */
7240	FNIEMOP_STUB(iemOp_pextrw_Gd_Nq_Ib);
7241	/** Opcode 0x66 0x0f 0xc5 - vpextrw Gd, Udq, Ib */
7242	FNIEMOP_STUB(iemOp_vpextrw_Gd_Udq_Ib);
7243	/* Opcode 0xf3 0x0f 0xc5 - invalid */
7244	/* Opcode 0xf2 0x0f 0xc5 - invalid */
7245
7246	/** Opcode 0x0f 0xc6 - vshufps Vps,Hps,Wps,Ib */
7247	FNIEMOP_STUB(iemOp_vshufps_Vps_Hps_Wps_Ib);
7248	/** Opcode 0x66 0x0f 0xc6 - vshufpd Vpd,Hpd,Wpd,Ib */
7249	FNIEMOP_STUB(iemOp_vshufpd_Vpd_Hpd_Wpd_Ib);
7250	/* Opcode 0xf3 0x0f 0xc6 - invalid */
7251	/* Opcode 0xf2 0x0f 0xc6 - invalid */
7252
7253
7254	/** Opcode 0x0f 0xc7 !11/1. */
7255	FNIEMOP_DEF_1(iemOp_Grp9_cmpxchg8b_Mq, uint8_t, bRm)
7256	{
7257	IEMOP_MNEMONIC(cmpxchg8b, "cmpxchg8b Mq");
7258
7259	IEM_MC_BEGIN(4, 3);
7260	IEM_MC_ARG(uint64_t *, pu64MemDst, 0);
7261	IEM_MC_ARG(PRTUINT64U, pu64EaxEdx, 1);
7262	IEM_MC_ARG(PRTUINT64U, pu64EbxEcx, 2);
7263	IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 3);
7264	IEM_MC_LOCAL(RTUINT64U, u64EaxEdx);
7265	IEM_MC_LOCAL(RTUINT64U, u64EbxEcx);
7266	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7267
7268	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7269	IEMOP_HLP_DONE_DECODING();
7270	IEM_MC_MEM_MAP(pu64MemDst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /arg/);
7271
7272	IEM_MC_FETCH_GREG_U32(u64EaxEdx.s.Lo, X86_GREG_xAX);
7273	IEM_MC_FETCH_GREG_U32(u64EaxEdx.s.Hi, X86_GREG_xDX);
7274	IEM_MC_REF_LOCAL(pu64EaxEdx, u64EaxEdx);
7275
7276	IEM_MC_FETCH_GREG_U32(u64EbxEcx.s.Lo, X86_GREG_xBX);
7277	IEM_MC_FETCH_GREG_U32(u64EbxEcx.s.Hi, X86_GREG_xCX);
7278	IEM_MC_REF_LOCAL(pu64EbxEcx, u64EbxEcx);
7279
7280	IEM_MC_FETCH_EFLAGS(EFlags);
7281	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7282	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg8b, pu64MemDst, pu64EaxEdx, pu64EbxEcx, pEFlags);
7283	else
7284	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg8b_locked, pu64MemDst, pu64EaxEdx, pu64EbxEcx, pEFlags);
7285
7286	IEM_MC_MEM_COMMIT_AND_UNMAP(pu64MemDst, IEM_ACCESS_DATA_RW);
7287	IEM_MC_COMMIT_EFLAGS(EFlags);
7288	IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_ZF)
7289	/** @todo Testcase: Check effect of cmpxchg8b on bits 63:32 in rax and rdx. */
7290	IEM_MC_STORE_GREG_U32(X86_GREG_xAX, u64EaxEdx.s.Lo);
7291	IEM_MC_STORE_GREG_U32(X86_GREG_xDX, u64EaxEdx.s.Hi);
7292	IEM_MC_ENDIF();
7293	IEM_MC_ADVANCE_RIP();
7294
7295	IEM_MC_END();
7296	return VINF_SUCCESS;
7297	}
7298
7299
7300	/** Opcode REX.W 0x0f 0xc7 !11/1. */
7301	FNIEMOP_DEF_1(iemOp_Grp9_cmpxchg16b_Mdq, uint8_t, bRm)
7302	{
7303	IEMOP_MNEMONIC(cmpxchg16b, "cmpxchg16b Mdq");
7304	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMovCmpXchg16b)
7305	{
7306	#if 0
7307	RT_NOREF(bRm);
7308	IEMOP_BITCH_ABOUT_STUB();
7309	return VERR_IEM_INSTR_NOT_IMPLEMENTED;
7310	#else
7311	IEM_MC_BEGIN(4, 3);
7312	IEM_MC_ARG(PRTUINT128U, pu128MemDst, 0);
7313	IEM_MC_ARG(PRTUINT128U, pu128RaxRdx, 1);
7314	IEM_MC_ARG(PRTUINT128U, pu128RbxRcx, 2);
7315	IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 3);
7316	IEM_MC_LOCAL(RTUINT128U, u128RaxRdx);
7317	IEM_MC_LOCAL(RTUINT128U, u128RbxRcx);
7318	IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);
7319
7320	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0);
7321	IEMOP_HLP_DONE_DECODING();
7322	IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(GCPtrEffDst, 16);
7323	IEM_MC_MEM_MAP(pu128MemDst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /arg/);
7324
7325	IEM_MC_FETCH_GREG_U64(u128RaxRdx.s.Lo, X86_GREG_xAX);
7326	IEM_MC_FETCH_GREG_U64(u128RaxRdx.s.Hi, X86_GREG_xDX);
7327	IEM_MC_REF_LOCAL(pu128RaxRdx, u128RaxRdx);
7328
7329	IEM_MC_FETCH_GREG_U64(u128RbxRcx.s.Lo, X86_GREG_xBX);
7330	IEM_MC_FETCH_GREG_U64(u128RbxRcx.s.Hi, X86_GREG_xCX);
7331	IEM_MC_REF_LOCAL(pu128RbxRcx, u128RbxRcx);
7332
7333	IEM_MC_FETCH_EFLAGS(EFlags);
7334	# ifdef RT_ARCH_AMD64
7335	if (IEM_GET_HOST_CPU_FEATURES(pVCpu)->fMovCmpXchg16b)
7336	{
7337	if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))
7338	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg16b, pu128MemDst, pu128RaxRdx, pu128RbxRcx, pEFlags);
7339	else
7340	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg16b_locked, pu128MemDst, pu128RaxRdx, pu128RbxRcx, pEFlags);
7341	}
7342	else
7343	# endif
7344	{
7345	/* Note! The fallback for 32-bit systems and systems without CX16 is multiple
7346	accesses and not all all atomic, which works fine on in UNI CPU guest
7347	configuration (ignoring DMA). If guest SMP is active we have no choice
7348	but to use a rendezvous callback here. Sigh. */
7349	if (pVCpu->CTX_SUFF(pVM)->cCpus == 1)
7350	IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg16b_fallback, pu128MemDst, pu128RaxRdx, pu128RbxRcx, pEFlags);
7351	else
7352	{
7353	IEM_MC_CALL_CIMPL_4(iemCImpl_cmpxchg16b_fallback_rendezvous, pu128MemDst, pu128RaxRdx, pu128RbxRcx, pEFlags);
7354	/* Does not get here, tail code is duplicated in iemCImpl_cmpxchg16b_fallback_rendezvous. */
7355	}
7356	}
7357
7358	IEM_MC_MEM_COMMIT_AND_UNMAP(pu128MemDst, IEM_ACCESS_DATA_RW);
7359	IEM_MC_COMMIT_EFLAGS(EFlags);
7360	IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_ZF)
7361	IEM_MC_STORE_GREG_U64(X86_GREG_xAX, u128RaxRdx.s.Lo);
7362	IEM_MC_STORE_GREG_U64(X86_GREG_xDX, u128RaxRdx.s.Hi);
7363	IEM_MC_ENDIF();
7364	IEM_MC_ADVANCE_RIP();
7365
7366	IEM_MC_END();
7367	return VINF_SUCCESS;
7368	#endif
7369	}
7370	Log(("cmpxchg16b -> #UD\n"));
7371	return IEMOP_RAISE_INVALID_OPCODE();
7372	}
7373
7374
7375	/** Opcode 0x0f 0xc7 11/6. */
7376	FNIEMOP_UD_STUB_1(iemOp_Grp9_rdrand_Rv, uint8_t, bRm);
7377
7378	/** Opcode 0x0f 0xc7 !11/6. */
7379	FNIEMOP_UD_STUB_1(iemOp_Grp9_vmptrld_Mq, uint8_t, bRm);
7380
7381	/** Opcode 0x66 0x0f 0xc7 !11/6. */
7382	FNIEMOP_UD_STUB_1(iemOp_Grp9_vmclear_Mq, uint8_t, bRm);
7383
7384	/** Opcode 0xf3 0x0f 0xc7 !11/6. */
7385	FNIEMOP_UD_STUB_1(iemOp_Grp9_vmxon_Mq, uint8_t, bRm);
7386
7387	/** Opcode [0xf3] 0x0f 0xc7 !11/7. */
7388	FNIEMOP_UD_STUB_1(iemOp_Grp9_vmptrst_Mq, uint8_t, bRm);
7389
7390
7391	/** Opcode 0x0f 0xc7. */
7392	FNIEMOP_DEF(iemOp_Grp9)
7393	{
7394	/** @todo Testcase: Check mixing 0x66 and 0xf3. Check the effect of 0xf2. */
7395	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7396	switch ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK)
7397	{
7398	case 0: case 2: case 3: case 4: case 5:
7399	return IEMOP_RAISE_INVALID_OPCODE();
7400	case 1:
7401	/** @todo Testcase: Check prefix effects on cmpxchg8b/16b. */
7402	if ( (bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)
7403	\|\| (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REPZ))) /** @todo Testcase: AMD seems to express a different idea here wrt prefixes. */
7404	return IEMOP_RAISE_INVALID_OPCODE();
7405	if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
7406	return FNIEMOP_CALL_1(iemOp_Grp9_cmpxchg16b_Mdq, bRm);
7407	return FNIEMOP_CALL_1(iemOp_Grp9_cmpxchg8b_Mq, bRm);
7408	case 6:
7409	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7410	return FNIEMOP_CALL_1(iemOp_Grp9_rdrand_Rv, bRm);
7411	switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REPZ))
7412	{
7413	case 0:
7414	return FNIEMOP_CALL_1(iemOp_Grp9_vmptrld_Mq, bRm);
7415	case IEM_OP_PRF_SIZE_OP:
7416	return FNIEMOP_CALL_1(iemOp_Grp9_vmclear_Mq, bRm);
7417	case IEM_OP_PRF_REPZ:
7418	return FNIEMOP_CALL_1(iemOp_Grp9_vmxon_Mq, bRm);
7419	default:
7420	return IEMOP_RAISE_INVALID_OPCODE();
7421	}
7422	case 7:
7423	switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REPZ))
7424	{
7425	case 0:
7426	case IEM_OP_PRF_REPZ:
7427	return FNIEMOP_CALL_1(iemOp_Grp9_vmptrst_Mq, bRm);
7428	default:
7429	return IEMOP_RAISE_INVALID_OPCODE();
7430	}
7431	IEM_NOT_REACHED_DEFAULT_CASE_RET();
7432	}
7433	}
7434
7435
7436	/**
7437	* Common 'bswap register' helper.
7438	*/
7439	FNIEMOP_DEF_1(iemOpCommonBswapGReg, uint8_t, iReg)
7440	{
7441	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7442	switch (pVCpu->iem.s.enmEffOpSize)
7443	{
7444	case IEMMODE_16BIT:
7445	IEM_MC_BEGIN(1, 0);
7446	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
7447	IEM_MC_REF_GREG_U32(pu32Dst, iReg); /* Don't clear the high dword! */
7448	IEM_MC_CALL_VOID_AIMPL_1(iemAImpl_bswap_u16, pu32Dst);
7449	IEM_MC_ADVANCE_RIP();
7450	IEM_MC_END();
7451	return VINF_SUCCESS;
7452
7453	case IEMMODE_32BIT:
7454	IEM_MC_BEGIN(1, 0);
7455	IEM_MC_ARG(uint32_t *, pu32Dst, 0);
7456	IEM_MC_REF_GREG_U32(pu32Dst, iReg);
7457	IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst);
7458	IEM_MC_CALL_VOID_AIMPL_1(iemAImpl_bswap_u32, pu32Dst);
7459	IEM_MC_ADVANCE_RIP();
7460	IEM_MC_END();
7461	return VINF_SUCCESS;
7462
7463	case IEMMODE_64BIT:
7464	IEM_MC_BEGIN(1, 0);
7465	IEM_MC_ARG(uint64_t *, pu64Dst, 0);
7466	IEM_MC_REF_GREG_U64(pu64Dst, iReg);
7467	IEM_MC_CALL_VOID_AIMPL_1(iemAImpl_bswap_u64, pu64Dst);
7468	IEM_MC_ADVANCE_RIP();
7469	IEM_MC_END();
7470	return VINF_SUCCESS;
7471
7472	IEM_NOT_REACHED_DEFAULT_CASE_RET();
7473	}
7474	}
7475
7476
7477	/** Opcode 0x0f 0xc8. */
7478	FNIEMOP_DEF(iemOp_bswap_rAX_r8)
7479	{
7480	IEMOP_MNEMONIC(bswap_rAX_r8, "bswap rAX/r8");
7481	/* Note! Intel manuals states that R8-R15 can be accessed by using a REX.X
7482	prefix. REX.B is the correct prefix it appears. For a parallel
7483	case, see iemOp_mov_AL_Ib and iemOp_mov_eAX_Iv. */
7484	IEMOP_HLP_MIN_486();
7485	return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xAX \| pVCpu->iem.s.uRexB);
7486	}
7487
7488
7489	/** Opcode 0x0f 0xc9. */
7490	FNIEMOP_DEF(iemOp_bswap_rCX_r9)
7491	{
7492	IEMOP_MNEMONIC(bswap_rCX_r9, "bswap rCX/r9");
7493	IEMOP_HLP_MIN_486();
7494	return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xCX \| pVCpu->iem.s.uRexB);
7495	}
7496
7497
7498	/** Opcode 0x0f 0xca. */
7499	FNIEMOP_DEF(iemOp_bswap_rDX_r10)
7500	{
7501	IEMOP_MNEMONIC(bswap_rDX_r9, "bswap rDX/r9");
7502	IEMOP_HLP_MIN_486();
7503	return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xDX \| pVCpu->iem.s.uRexB);
7504	}
7505
7506
7507	/** Opcode 0x0f 0xcb. */
7508	FNIEMOP_DEF(iemOp_bswap_rBX_r11)
7509	{
7510	IEMOP_MNEMONIC(bswap_rBX_r9, "bswap rBX/r9");
7511	IEMOP_HLP_MIN_486();
7512	return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xBX \| pVCpu->iem.s.uRexB);
7513	}
7514
7515
7516	/** Opcode 0x0f 0xcc. */
7517	FNIEMOP_DEF(iemOp_bswap_rSP_r12)
7518	{
7519	IEMOP_MNEMONIC(bswap_rSP_r12, "bswap rSP/r12");
7520	IEMOP_HLP_MIN_486();
7521	return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xSP \| pVCpu->iem.s.uRexB);
7522	}
7523
7524
7525	/** Opcode 0x0f 0xcd. */
7526	FNIEMOP_DEF(iemOp_bswap_rBP_r13)
7527	{
7528	IEMOP_MNEMONIC(bswap_rBP_r13, "bswap rBP/r13");
7529	IEMOP_HLP_MIN_486();
7530	return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xBP \| pVCpu->iem.s.uRexB);
7531	}
7532
7533
7534	/** Opcode 0x0f 0xce. */
7535	FNIEMOP_DEF(iemOp_bswap_rSI_r14)
7536	{
7537	IEMOP_MNEMONIC(bswap_rSI_r14, "bswap rSI/r14");
7538	IEMOP_HLP_MIN_486();
7539	return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xSI \| pVCpu->iem.s.uRexB);
7540	}
7541
7542
7543	/** Opcode 0x0f 0xcf. */
7544	FNIEMOP_DEF(iemOp_bswap_rDI_r15)
7545	{
7546	IEMOP_MNEMONIC(bswap_rDI_r15, "bswap rDI/r15");
7547	IEMOP_HLP_MIN_486();
7548	return FNIEMOP_CALL_1(iemOpCommonBswapGReg, X86_GREG_xDI \| pVCpu->iem.s.uRexB);
7549	}
7550
7551
7552	/* Opcode 0x0f 0xd0 - invalid */
7553	/** Opcode 0x66 0x0f 0xd0 - vaddsubpd Vpd, Hpd, Wpd */
7554	FNIEMOP_STUB(iemOp_vaddsubpd_Vpd_Hpd_Wpd);
7555	/* Opcode 0xf3 0x0f 0xd0 - invalid */
7556	/** Opcode 0xf2 0x0f 0xd0 - vaddsubps Vps, Hps, Wps */
7557	FNIEMOP_STUB(iemOp_vaddsubps_Vps_Hps_Wps);
7558
7559	/** Opcode 0x0f 0xd1 - psrlw Pq, Qq */
7560	FNIEMOP_STUB(iemOp_psrlw_Pq_Qq);
7561	/** Opcode 0x66 0x0f 0xd1 - vpsrlw Vx, Hx, W */
7562	FNIEMOP_STUB(iemOp_vpsrlw_Vx_Hx_W);
7563	/* Opcode 0xf3 0x0f 0xd1 - invalid */
7564	/* Opcode 0xf2 0x0f 0xd1 - invalid */
7565
7566	/** Opcode 0x0f 0xd2 - psrld Pq, Qq */
7567	FNIEMOP_STUB(iemOp_psrld_Pq_Qq);
7568	/** Opcode 0x66 0x0f 0xd2 - vpsrld Vx, Hx, Wx */
7569	FNIEMOP_STUB(iemOp_vpsrld_Vx_Hx_Wx);
7570	/* Opcode 0xf3 0x0f 0xd2 - invalid */
7571	/* Opcode 0xf2 0x0f 0xd2 - invalid */
7572
7573	/** Opcode 0x0f 0xd3 - psrlq Pq, Qq */
7574	FNIEMOP_STUB(iemOp_psrlq_Pq_Qq);
7575	/** Opcode 0x66 0x0f 0xd3 - vpsrlq Vx, Hx, Wx */
7576	FNIEMOP_STUB(iemOp_vpsrlq_Vx_Hx_Wx);
7577	/* Opcode 0xf3 0x0f 0xd3 - invalid */
7578	/* Opcode 0xf2 0x0f 0xd3 - invalid */
7579
7580	/** Opcode 0x0f 0xd4 - paddq Pq, Qq */
7581	FNIEMOP_STUB(iemOp_paddq_Pq_Qq);
7582	/** Opcode 0x66 0x0f 0xd4 - vpaddq Vx, Hx, W */
7583	FNIEMOP_STUB(iemOp_vpaddq_Vx_Hx_W);
7584	/* Opcode 0xf3 0x0f 0xd4 - invalid */
7585	/* Opcode 0xf2 0x0f 0xd4 - invalid */
7586
7587	/** Opcode 0x0f 0xd5 - pmullw Pq, Qq */
7588	FNIEMOP_STUB(iemOp_pmullw_Pq_Qq);
7589	/** Opcode 0x66 0x0f 0xd5 - vpmullw Vx, Hx, Wx */
7590	FNIEMOP_STUB(iemOp_vpmullw_Vx_Hx_Wx);
7591	/* Opcode 0xf3 0x0f 0xd5 - invalid */
7592	/* Opcode 0xf2 0x0f 0xd5 - invalid */
7593
7594	/* Opcode 0x0f 0xd6 - invalid */
7595
7596	/**
7597	* @opcode 0xd6
7598	* @oppfx 0x66
7599	* @opcpuid sse2
7600	* @opgroup og_sse2_pcksclr_datamove
7601	* @opxcpttype none
7602	* @optest op1=-1 op2=2 -> op1=2
7603	* @optest op1=0 op2=-42 -> op1=-42
7604	*/
7605	FNIEMOP_DEF(iemOp_vmovq_Wq_Vq)
7606	{
7607	IEMOP_MNEMONIC2(MR, MOVQ, movq, WqZxReg, Vq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
7608	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7609	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
7610	{
7611	/*
7612	* Register, register.
7613	*/
7614	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7615	IEM_MC_BEGIN(0, 2);
7616	IEM_MC_LOCAL(uint64_t, uSrc);
7617
7618	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
7619	IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
7620
7621	IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
7622	IEM_MC_STORE_XREG_U64_ZX_U128((bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB, uSrc);
7623
7624	IEM_MC_ADVANCE_RIP();
7625	IEM_MC_END();
7626	}
7627	else
7628	{
7629	/*
7630	* Memory, register.
7631	*/
7632	IEM_MC_BEGIN(0, 2);
7633	IEM_MC_LOCAL(uint64_t, uSrc);
7634	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
7635
7636	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
7637	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7638	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
7639	IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
7640
7641	IEM_MC_FETCH_XREG_U64(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
7642	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
7643
7644	IEM_MC_ADVANCE_RIP();
7645	IEM_MC_END();
7646	}
7647	return VINF_SUCCESS;
7648	}
7649
7650
7651	/** Opcode 0xf3 0x0f 0xd6 - movq2dq Vdq, Nq */
7652	FNIEMOP_STUB(iemOp_movq2dq_Vdq_Nq);
7653	/** Opcode 0xf2 0x0f 0xd6 - movdq2q Pq, Uq */
7654	FNIEMOP_STUB(iemOp_movdq2q_Pq_Uq);
7655	#if 0
7656	FNIEMOP_DEF(iemOp_movq_Wq_Vq__movq2dq_Vdq_Nq__movdq2q_Pq_Uq)
7657	{
7658	/* Docs says register only. */
7659	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7660
7661	switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REPNZ \| IEM_OP_PRF_REPZ))
7662	{
7663	case IEM_OP_PRF_SIZE_OP: /* SSE */
7664	I E M O P _ M N E M O N I C(movq_Wq_Vq, "movq Wq,Vq");
7665	IEMOP_HLP_DECODED_NL_2(OP_PMOVMSKB, IEMOPFORM_RM_REG, OP_PARM_Gd, OP_PARM_Vdq, DISOPTYPE_SSE \| DISOPTYPE_HARMLESS);
7666	IEM_MC_BEGIN(2, 0);
7667	IEM_MC_ARG(uint64_t *, pDst, 0);
7668	IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
7669	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
7670	IEM_MC_PREPARE_SSE_USAGE();
7671	IEM_MC_REF_GREG_U64(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
7672	IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
7673	IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_pmovmskb_u128, pDst, pSrc);
7674	IEM_MC_ADVANCE_RIP();
7675	IEM_MC_END();
7676	return VINF_SUCCESS;
7677
7678	case 0: /* MMX */
7679	I E M O P _ M N E M O N I C(pmovmskb_Gd_Udq, "pmovmskb Gd,Udq");
7680	IEMOP_HLP_DECODED_NL_2(OP_PMOVMSKB, IEMOPFORM_RM_REG, OP_PARM_Gd, OP_PARM_Vdq, DISOPTYPE_MMX \| DISOPTYPE_HARMLESS);
7681	IEM_MC_BEGIN(2, 0);
7682	IEM_MC_ARG(uint64_t *, pDst, 0);
7683	IEM_MC_ARG(uint64_t const *, pSrc, 1);
7684	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT();
7685	IEM_MC_PREPARE_FPU_USAGE();
7686	IEM_MC_REF_GREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
7687	IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
7688	IEM_MC_CALL_MMX_AIMPL_2(iemAImpl_pmovmskb_u64, pDst, pSrc);
7689	IEM_MC_ADVANCE_RIP();
7690	IEM_MC_END();
7691	return VINF_SUCCESS;
7692
7693	default:
7694	return IEMOP_RAISE_INVALID_OPCODE();
7695	}
7696	}
7697	#endif
7698
7699
7700	/** Opcode 0x0f 0xd7 - pmovmskb Gd, Nq */
7701	FNIEMOP_DEF(iemOp_pmovmskb_Gd_Nq)
7702	{
7703	/* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
7704	/** @todo testcase: Check that the instruction implicitly clears the high
7705	* bits in 64-bit mode. The REX.W is first necessary when VLMAX > 256
7706	* and opcode modifications are made to work with the whole width (not
7707	* just 128). */
7708	IEMOP_MNEMONIC(pmovmskb_Gd_Udq, "pmovmskb Gd,Nq");
7709	/* Docs says register only. */
7710	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7711	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) /** @todo test that this is registers only. */
7712	{
7713	IEMOP_HLP_DECODED_NL_2(OP_PMOVMSKB, IEMOPFORM_RM_REG, OP_PARM_Gd, OP_PARM_Vdq, DISOPTYPE_MMX \| DISOPTYPE_HARMLESS);
7714	IEM_MC_BEGIN(2, 0);
7715	IEM_MC_ARG(uint64_t *, pDst, 0);
7716	IEM_MC_ARG(uint64_t const *, pSrc, 1);
7717	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT();
7718	IEM_MC_PREPARE_FPU_USAGE();
7719	IEM_MC_REF_GREG_U64(pDst, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
7720	IEM_MC_REF_MREG_U64_CONST(pSrc, bRm & X86_MODRM_RM_MASK);
7721	IEM_MC_CALL_MMX_AIMPL_2(iemAImpl_pmovmskb_u64, pDst, pSrc);
7722	IEM_MC_ADVANCE_RIP();
7723	IEM_MC_END();
7724	return VINF_SUCCESS;
7725	}
7726	return IEMOP_RAISE_INVALID_OPCODE();
7727	}
7728
7729	/** Opcode 0x66 0x0f 0xd7 - */
7730	FNIEMOP_DEF(iemOp_vpmovmskb_Gd_Ux)
7731	{
7732	/* Note! Taking the lazy approch here wrt the high 32-bits of the GREG. */
7733	/** @todo testcase: Check that the instruction implicitly clears the high
7734	* bits in 64-bit mode. The REX.W is first necessary when VLMAX > 256
7735	* and opcode modifications are made to work with the whole width (not
7736	* just 128). */
7737	IEMOP_MNEMONIC(pmovmskb_Gd_Nq, "vpmovmskb Gd, Ux");
7738	/* Docs says register only. */
7739	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7740	if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) /** @todo test that this is registers only. */
7741	{
7742	IEMOP_HLP_DECODED_NL_2(OP_PMOVMSKB, IEMOPFORM_RM_REG, OP_PARM_Gd, OP_PARM_Vdq, DISOPTYPE_SSE \| DISOPTYPE_HARMLESS);
7743	IEM_MC_BEGIN(2, 0);
7744	IEM_MC_ARG(uint64_t *, pDst, 0);
7745	IEM_MC_ARG(PCRTUINT128U, pSrc, 1);
7746	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
7747	IEM_MC_PREPARE_SSE_USAGE();
7748	IEM_MC_REF_GREG_U64(pDst, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
7749	IEM_MC_REF_XREG_U128_CONST(pSrc, (bRm & X86_MODRM_RM_MASK) \| pVCpu->iem.s.uRexB);
7750	IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_pmovmskb_u128, pDst, pSrc);
7751	IEM_MC_ADVANCE_RIP();
7752	IEM_MC_END();
7753	return VINF_SUCCESS;
7754	}
7755	return IEMOP_RAISE_INVALID_OPCODE();
7756	}
7757
7758	/* Opcode 0xf3 0x0f 0xd7 - invalid */
7759	/* Opcode 0xf2 0x0f 0xd7 - invalid */
7760
7761
7762	/** Opcode 0x0f 0xd8 - psubusb Pq, Qq */
7763	FNIEMOP_STUB(iemOp_psubusb_Pq_Qq);
7764	/** Opcode 0x66 0x0f 0xd8 - vpsubusb Vx, Hx, W */
7765	FNIEMOP_STUB(iemOp_vpsubusb_Vx_Hx_W);
7766	/* Opcode 0xf3 0x0f 0xd8 - invalid */
7767	/* Opcode 0xf2 0x0f 0xd8 - invalid */
7768
7769	/** Opcode 0x0f 0xd9 - psubusw Pq, Qq */
7770	FNIEMOP_STUB(iemOp_psubusw_Pq_Qq);
7771	/** Opcode 0x66 0x0f 0xd9 - vpsubusw Vx, Hx, Wx */
7772	FNIEMOP_STUB(iemOp_vpsubusw_Vx_Hx_Wx);
7773	/* Opcode 0xf3 0x0f 0xd9 - invalid */
7774	/* Opcode 0xf2 0x0f 0xd9 - invalid */
7775
7776	/** Opcode 0x0f 0xda - pminub Pq, Qq */
7777	FNIEMOP_STUB(iemOp_pminub_Pq_Qq);
7778	/** Opcode 0x66 0x0f 0xda - vpminub Vx, Hx, Wx */
7779	FNIEMOP_STUB(iemOp_vpminub_Vx_Hx_Wx);
7780	/* Opcode 0xf3 0x0f 0xda - invalid */
7781	/* Opcode 0xf2 0x0f 0xda - invalid */
7782
7783	/** Opcode 0x0f 0xdb - pand Pq, Qq */
7784	FNIEMOP_STUB(iemOp_pand_Pq_Qq);
7785	/** Opcode 0x66 0x0f 0xdb - vpand Vx, Hx, W */
7786	FNIEMOP_STUB(iemOp_vpand_Vx_Hx_W);
7787	/* Opcode 0xf3 0x0f 0xdb - invalid */
7788	/* Opcode 0xf2 0x0f 0xdb - invalid */
7789
7790	/** Opcode 0x0f 0xdc - paddusb Pq, Qq */
7791	FNIEMOP_STUB(iemOp_paddusb_Pq_Qq);
7792	/** Opcode 0x66 0x0f 0xdc - vpaddusb Vx, Hx, Wx */
7793	FNIEMOP_STUB(iemOp_vpaddusb_Vx_Hx_Wx);
7794	/* Opcode 0xf3 0x0f 0xdc - invalid */
7795	/* Opcode 0xf2 0x0f 0xdc - invalid */
7796
7797	/** Opcode 0x0f 0xdd - paddusw Pq, Qq */
7798	FNIEMOP_STUB(iemOp_paddusw_Pq_Qq);
7799	/** Opcode 0x66 0x0f 0xdd - vpaddusw Vx, Hx, Wx */
7800	FNIEMOP_STUB(iemOp_vpaddusw_Vx_Hx_Wx);
7801	/* Opcode 0xf3 0x0f 0xdd - invalid */
7802	/* Opcode 0xf2 0x0f 0xdd - invalid */
7803
7804	/** Opcode 0x0f 0xde - pmaxub Pq, Qq */
7805	FNIEMOP_STUB(iemOp_pmaxub_Pq_Qq);
7806	/** Opcode 0x66 0x0f 0xde - vpmaxub Vx, Hx, W */
7807	FNIEMOP_STUB(iemOp_vpmaxub_Vx_Hx_W);
7808	/* Opcode 0xf3 0x0f 0xde - invalid */
7809	/* Opcode 0xf2 0x0f 0xde - invalid */
7810
7811	/** Opcode 0x0f 0xdf - pandn Pq, Qq */
7812	FNIEMOP_STUB(iemOp_pandn_Pq_Qq);
7813	/** Opcode 0x66 0x0f 0xdf - vpandn Vx, Hx, Wx */
7814	FNIEMOP_STUB(iemOp_vpandn_Vx_Hx_Wx);
7815	/* Opcode 0xf3 0x0f 0xdf - invalid */
7816	/* Opcode 0xf2 0x0f 0xdf - invalid */
7817
7818	/** Opcode 0x0f 0xe0 - pavgb Pq, Qq */
7819	FNIEMOP_STUB(iemOp_pavgb_Pq_Qq);
7820	/** Opcode 0x66 0x0f 0xe0 - vpavgb Vx, Hx, Wx */
7821	FNIEMOP_STUB(iemOp_vpavgb_Vx_Hx_Wx);
7822	/* Opcode 0xf3 0x0f 0xe0 - invalid */
7823	/* Opcode 0xf2 0x0f 0xe0 - invalid */
7824
7825	/** Opcode 0x0f 0xe1 - psraw Pq, Qq */
7826	FNIEMOP_STUB(iemOp_psraw_Pq_Qq);
7827	/** Opcode 0x66 0x0f 0xe1 - vpsraw Vx, Hx, W */
7828	FNIEMOP_STUB(iemOp_vpsraw_Vx_Hx_W);
7829	/* Opcode 0xf3 0x0f 0xe1 - invalid */
7830	/* Opcode 0xf2 0x0f 0xe1 - invalid */
7831
7832	/** Opcode 0x0f 0xe2 - psrad Pq, Qq */
7833	FNIEMOP_STUB(iemOp_psrad_Pq_Qq);
7834	/** Opcode 0x66 0x0f 0xe2 - vpsrad Vx, Hx, Wx */
7835	FNIEMOP_STUB(iemOp_vpsrad_Vx_Hx_Wx);
7836	/* Opcode 0xf3 0x0f 0xe2 - invalid */
7837	/* Opcode 0xf2 0x0f 0xe2 - invalid */
7838
7839	/** Opcode 0x0f 0xe3 - pavgw Pq, Qq */
7840	FNIEMOP_STUB(iemOp_pavgw_Pq_Qq);
7841	/** Opcode 0x66 0x0f 0xe3 - vpavgw Vx, Hx, Wx */
7842	FNIEMOP_STUB(iemOp_vpavgw_Vx_Hx_Wx);
7843	/* Opcode 0xf3 0x0f 0xe3 - invalid */
7844	/* Opcode 0xf2 0x0f 0xe3 - invalid */
7845
7846	/** Opcode 0x0f 0xe4 - pmulhuw Pq, Qq */
7847	FNIEMOP_STUB(iemOp_pmulhuw_Pq_Qq);
7848	/** Opcode 0x66 0x0f 0xe4 - vpmulhuw Vx, Hx, W */
7849	FNIEMOP_STUB(iemOp_vpmulhuw_Vx_Hx_W);
7850	/* Opcode 0xf3 0x0f 0xe4 - invalid */
7851	/* Opcode 0xf2 0x0f 0xe4 - invalid */
7852
7853	/** Opcode 0x0f 0xe5 - pmulhw Pq, Qq */
7854	FNIEMOP_STUB(iemOp_pmulhw_Pq_Qq);
7855	/** Opcode 0x66 0x0f 0xe5 - vpmulhw Vx, Hx, Wx */
7856	FNIEMOP_STUB(iemOp_vpmulhw_Vx_Hx_Wx);
7857	/* Opcode 0xf3 0x0f 0xe5 - invalid */
7858	/* Opcode 0xf2 0x0f 0xe5 - invalid */
7859
7860	/* Opcode 0x0f 0xe6 - invalid */
7861	/** Opcode 0x66 0x0f 0xe6 - vcvttpd2dq Vx, Wpd */
7862	FNIEMOP_STUB(iemOp_vcvttpd2dq_Vx_Wpd);
7863	/** Opcode 0xf3 0x0f 0xe6 - vcvtdq2pd Vx, Wpd */
7864	FNIEMOP_STUB(iemOp_vcvtdq2pd_Vx_Wpd);
7865	/** Opcode 0xf2 0x0f 0xe6 - vcvtpd2dq Vx, Wpd */
7866	FNIEMOP_STUB(iemOp_vcvtpd2dq_Vx_Wpd);
7867
7868
7869	/** Opcode 0x0f 0xe7 - movntq Mq, Pq */
7870	FNIEMOP_DEF(iemOp_movntq_Mq_Pq)
7871	{
7872	IEMOP_MNEMONIC(movntq_Mq_Pq, "movntq Mq,Pq");
7873	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7874	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
7875	{
7876	/* Register, memory. */
7877	IEM_MC_BEGIN(0, 2);
7878	IEM_MC_LOCAL(uint64_t, uSrc);
7879	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
7880
7881	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
7882	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7883	IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT();
7884	IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ();
7885
7886	IEM_MC_FETCH_MREG_U64(uSrc, (bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK);
7887	IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
7888
7889	IEM_MC_ADVANCE_RIP();
7890	IEM_MC_END();
7891	return VINF_SUCCESS;
7892	}
7893	/* The register, register encoding is invalid. */
7894	return IEMOP_RAISE_INVALID_OPCODE();
7895	}
7896
7897	/** Opcode 0x66 0x0f 0xe7 - vmovntdq Mx, Vx */
7898	FNIEMOP_DEF(iemOp_vmovntdq_Mx_Vx)
7899	{
7900	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
7901	if ((bRm & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT))
7902	{
7903	/* Register, memory. */
7904	IEMOP_MNEMONIC(vmovntdq_Mx_Vx, "vmovntdq Mx,Vx");
7905	IEM_MC_BEGIN(0, 2);
7906	IEM_MC_LOCAL(RTUINT128U, uSrc);
7907	IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc);
7908
7909	IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
7910	IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
7911	IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
7912	IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ();
7913
7914	IEM_MC_FETCH_XREG_U128(uSrc, ((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| pVCpu->iem.s.uRexReg);
7915	IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc);
7916
7917	IEM_MC_ADVANCE_RIP();
7918	IEM_MC_END();
7919	return VINF_SUCCESS;
7920	}
7921
7922	/* The register, register encoding is invalid. */
7923	return IEMOP_RAISE_INVALID_OPCODE();
7924	}
7925
7926	/* Opcode 0xf3 0x0f 0xe7 - invalid */
7927	/* Opcode 0xf2 0x0f 0xe7 - invalid */
7928
7929
7930	/** Opcode 0x0f 0xe8 - psubsb Pq, Qq */
7931	FNIEMOP_STUB(iemOp_psubsb_Pq_Qq);
7932	/** Opcode 0x66 0x0f 0xe8 - vpsubsb Vx, Hx, W */
7933	FNIEMOP_STUB(iemOp_vpsubsb_Vx_Hx_W);
7934	/* Opcode 0xf3 0x0f 0xe8 - invalid */
7935	/* Opcode 0xf2 0x0f 0xe8 - invalid */
7936
7937	/** Opcode 0x0f 0xe9 - psubsw Pq, Qq */
7938	FNIEMOP_STUB(iemOp_psubsw_Pq_Qq);
7939	/** Opcode 0x66 0x0f 0xe9 - vpsubsw Vx, Hx, Wx */
7940	FNIEMOP_STUB(iemOp_vpsubsw_Vx_Hx_Wx);
7941	/* Opcode 0xf3 0x0f 0xe9 - invalid */
7942	/* Opcode 0xf2 0x0f 0xe9 - invalid */
7943
7944	/** Opcode 0x0f 0xea - pminsw Pq, Qq */
7945	FNIEMOP_STUB(iemOp_pminsw_Pq_Qq);
7946	/** Opcode 0x66 0x0f 0xea - vpminsw Vx, Hx, Wx */
7947	FNIEMOP_STUB(iemOp_vpminsw_Vx_Hx_Wx);
7948	/* Opcode 0xf3 0x0f 0xea - invalid */
7949	/* Opcode 0xf2 0x0f 0xea - invalid */
7950
7951	/** Opcode 0x0f 0xeb - por Pq, Qq */
7952	FNIEMOP_STUB(iemOp_por_Pq_Qq);
7953	/** Opcode 0x66 0x0f 0xeb - vpor Vx, Hx, W */
7954	FNIEMOP_STUB(iemOp_vpor_Vx_Hx_W);
7955	/* Opcode 0xf3 0x0f 0xeb - invalid */
7956	/* Opcode 0xf2 0x0f 0xeb - invalid */
7957
7958	/** Opcode 0x0f 0xec - paddsb Pq, Qq */
7959	FNIEMOP_STUB(iemOp_paddsb_Pq_Qq);
7960	/** Opcode 0x66 0x0f 0xec - vpaddsb Vx, Hx, Wx */
7961	FNIEMOP_STUB(iemOp_vpaddsb_Vx_Hx_Wx);
7962	/* Opcode 0xf3 0x0f 0xec - invalid */
7963	/* Opcode 0xf2 0x0f 0xec - invalid */
7964
7965	/** Opcode 0x0f 0xed - paddsw Pq, Qq */
7966	FNIEMOP_STUB(iemOp_paddsw_Pq_Qq);
7967	/** Opcode 0x66 0x0f 0xed - vpaddsw Vx, Hx, Wx */
7968	FNIEMOP_STUB(iemOp_vpaddsw_Vx_Hx_Wx);
7969	/* Opcode 0xf3 0x0f 0xed - invalid */
7970	/* Opcode 0xf2 0x0f 0xed - invalid */
7971
7972	/** Opcode 0x0f 0xee - pmaxsw Pq, Qq */
7973	FNIEMOP_STUB(iemOp_pmaxsw_Pq_Qq);
7974	/** Opcode 0x66 0x0f 0xee - vpmaxsw Vx, Hx, W */
7975	FNIEMOP_STUB(iemOp_vpmaxsw_Vx_Hx_W);
7976	/* Opcode 0xf3 0x0f 0xee - invalid */
7977	/* Opcode 0xf2 0x0f 0xee - invalid */
7978
7979
7980	/** Opcode 0x0f 0xef - pxor Pq, Qq */
7981	FNIEMOP_DEF(iemOp_pxor_Pq_Qq)
7982	{
7983	IEMOP_MNEMONIC(pxor, "pxor");
7984	return FNIEMOP_CALL_1(iemOpCommonMmx_FullFull_To_Full, &g_iemAImpl_pxor);
7985	}
7986
7987	/** Opcode 0x66 0x0f 0xef - vpxor Vx, Hx, Wx */
7988	FNIEMOP_DEF(iemOp_vpxor_Vx_Hx_Wx)
7989	{
7990	IEMOP_MNEMONIC(vpxor, "vpxor");
7991	return FNIEMOP_CALL_1(iemOpCommonSse2_FullFull_To_Full, &g_iemAImpl_pxor);
7992	}
7993
7994	/* Opcode 0xf3 0x0f 0xef - invalid */
7995	/* Opcode 0xf2 0x0f 0xef - invalid */
7996
7997	/* Opcode 0x0f 0xf0 - invalid */
7998	/* Opcode 0x66 0x0f 0xf0 - invalid */
7999	/** Opcode 0xf2 0x0f 0xf0 - vlddqu Vx, Mx */
8000	FNIEMOP_STUB(iemOp_vlddqu_Vx_Mx);
8001
8002	/** Opcode 0x0f 0xf1 - psllw Pq, Qq */
8003	FNIEMOP_STUB(iemOp_psllw_Pq_Qq);
8004	/** Opcode 0x66 0x0f 0xf1 - vpsllw Vx, Hx, W */
8005	FNIEMOP_STUB(iemOp_vpsllw_Vx_Hx_W);
8006	/* Opcode 0xf2 0x0f 0xf1 - invalid */
8007
8008	/** Opcode 0x0f 0xf2 - pslld Pq, Qq */
8009	FNIEMOP_STUB(iemOp_pslld_Pq_Qq);
8010	/** Opcode 0x66 0x0f 0xf2 - vpslld Vx, Hx, Wx */
8011	FNIEMOP_STUB(iemOp_vpslld_Vx_Hx_Wx);
8012	/* Opcode 0xf2 0x0f 0xf2 - invalid */
8013
8014	/** Opcode 0x0f 0xf3 - psllq Pq, Qq */
8015	FNIEMOP_STUB(iemOp_psllq_Pq_Qq);
8016	/** Opcode 0x66 0x0f 0xf3 - vpsllq Vx, Hx, Wx */
8017	FNIEMOP_STUB(iemOp_vpsllq_Vx_Hx_Wx);
8018	/* Opcode 0xf2 0x0f 0xf3 - invalid */
8019
8020	/** Opcode 0x0f 0xf4 - pmuludq Pq, Qq */
8021	FNIEMOP_STUB(iemOp_pmuludq_Pq_Qq);
8022	/** Opcode 0x66 0x0f 0xf4 - vpmuludq Vx, Hx, W */
8023	FNIEMOP_STUB(iemOp_vpmuludq_Vx_Hx_W);
8024	/* Opcode 0xf2 0x0f 0xf4 - invalid */
8025
8026	/** Opcode 0x0f 0xf5 - pmaddwd Pq, Qq */
8027	FNIEMOP_STUB(iemOp_pmaddwd_Pq_Qq);
8028	/** Opcode 0x66 0x0f 0xf5 - vpmaddwd Vx, Hx, Wx */
8029	FNIEMOP_STUB(iemOp_vpmaddwd_Vx_Hx_Wx);
8030	/* Opcode 0xf2 0x0f 0xf5 - invalid */
8031
8032	/** Opcode 0x0f 0xf6 - psadbw Pq, Qq */
8033	FNIEMOP_STUB(iemOp_psadbw_Pq_Qq);
8034	/** Opcode 0x66 0x0f 0xf6 - vpsadbw Vx, Hx, Wx */
8035	FNIEMOP_STUB(iemOp_vpsadbw_Vx_Hx_Wx);
8036	/* Opcode 0xf2 0x0f 0xf6 - invalid */
8037
8038	/** Opcode 0x0f 0xf7 - maskmovq Pq, Nq */
8039	FNIEMOP_STUB(iemOp_maskmovq_Pq_Nq);
8040	/** Opcode 0x66 0x0f 0xf7 - vmaskmovdqu Vdq, Udq */
8041	FNIEMOP_STUB(iemOp_vmaskmovdqu_Vdq_Udq);
8042	/* Opcode 0xf2 0x0f 0xf7 - invalid */
8043
8044	/** Opcode 0x0f 0xf8 - psubb Pq, Qq */
8045	FNIEMOP_STUB(iemOp_psubb_Pq_Qq);
8046	/** Opcode 0x66 0x0f 0xf8 - vpsubb Vx, Hx, W */
8047	FNIEMOP_STUB(iemOp_vpsubb_Vx_Hx_W);
8048	/* Opcode 0xf2 0x0f 0xf8 - invalid */
8049
8050	/** Opcode 0x0f 0xf9 - psubw Pq, Qq */
8051	FNIEMOP_STUB(iemOp_psubw_Pq_Qq);
8052	/** Opcode 0x66 0x0f 0xf9 - vpsubw Vx, Hx, Wx */
8053	FNIEMOP_STUB(iemOp_vpsubw_Vx_Hx_Wx);
8054	/* Opcode 0xf2 0x0f 0xf9 - invalid */
8055
8056	/** Opcode 0x0f 0xfa - psubd Pq, Qq */
8057	FNIEMOP_STUB(iemOp_psubd_Pq_Qq);
8058	/** Opcode 0x66 0x0f 0xfa - vpsubd Vx, Hx, Wx */
8059	FNIEMOP_STUB(iemOp_vpsubd_Vx_Hx_Wx);
8060	/* Opcode 0xf2 0x0f 0xfa - invalid */
8061
8062	/** Opcode 0x0f 0xfb - psubq Pq, Qq */
8063	FNIEMOP_STUB(iemOp_psubq_Pq_Qq);
8064	/** Opcode 0x66 0x0f 0xfb - vpsubq Vx, Hx, W */
8065	FNIEMOP_STUB(iemOp_vpsubq_Vx_Hx_W);
8066	/* Opcode 0xf2 0x0f 0xfb - invalid */
8067
8068	/** Opcode 0x0f 0xfc - paddb Pq, Qq */
8069	FNIEMOP_STUB(iemOp_paddb_Pq_Qq);
8070	/** Opcode 0x66 0x0f 0xfc - vpaddb Vx, Hx, Wx */
8071	FNIEMOP_STUB(iemOp_vpaddb_Vx_Hx_Wx);
8072	/* Opcode 0xf2 0x0f 0xfc - invalid */
8073
8074	/** Opcode 0x0f 0xfd - paddw Pq, Qq */
8075	FNIEMOP_STUB(iemOp_paddw_Pq_Qq);
8076	/** Opcode 0x66 0x0f 0xfd - vpaddw Vx, Hx, Wx */
8077	FNIEMOP_STUB(iemOp_vpaddw_Vx_Hx_Wx);
8078	/* Opcode 0xf2 0x0f 0xfd - invalid */
8079
8080	/** Opcode 0x0f 0xfe - paddd Pq, Qq */
8081	FNIEMOP_STUB(iemOp_paddd_Pq_Qq);
8082	/** Opcode 0x66 0x0f 0xfe - vpaddd Vx, Hx, W */
8083	FNIEMOP_STUB(iemOp_vpaddd_Vx_Hx_W);
8084	/* Opcode 0xf2 0x0f 0xfe - invalid */
8085
8086
8087	/ Opcode ** 0x0f 0xff - UD0 */
8088	FNIEMOP_DEF(iemOp_ud0)
8089	{
8090	IEMOP_MNEMONIC(ud0, "ud0");
8091	if (pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
8092	{
8093	uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); RT_NOREF(bRm);
8094	#ifndef TST_IEM_CHECK_MC
8095	RTGCPTR GCPtrEff;
8096	VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff);
8097	if (rcStrict != VINF_SUCCESS)
8098	return rcStrict;
8099	#endif
8100	IEMOP_HLP_DONE_DECODING();
8101	}
8102	return IEMOP_RAISE_INVALID_OPCODE();
8103	}
8104
8105
8106
8107	/**
8108	* Two byte opcode map, first byte 0x0f.
8109	*
8110	* @remarks The g_apfnVexMap1 table is currently a subset of this one, so please
8111	* check if it needs updating as well when making changes.
8112	*/
8113	IEM_STATIC const PFNIEMOP g_apfnTwoByteMap[] =
8114	{
8115	/* no prefix, 066h prefix f3h prefix, f2h prefix */
8116	/* 0x00 */ IEMOP_X4(iemOp_Grp6),
8117	/* 0x01 */ IEMOP_X4(iemOp_Grp7),
8118	/* 0x02 */ IEMOP_X4(iemOp_lar_Gv_Ew),
8119	/* 0x03 */ IEMOP_X4(iemOp_lsl_Gv_Ew),
8120	/* 0x04 */ IEMOP_X4(iemOp_Invalid),
8121	/* 0x05 */ IEMOP_X4(iemOp_syscall),
8122	/* 0x06 */ IEMOP_X4(iemOp_clts),
8123	/* 0x07 */ IEMOP_X4(iemOp_sysret),
8124	/* 0x08 */ IEMOP_X4(iemOp_invd),
8125	/* 0x09 */ IEMOP_X4(iemOp_wbinvd),
8126	/* 0x0a */ IEMOP_X4(iemOp_Invalid),
8127	/* 0x0b */ IEMOP_X4(iemOp_ud2),
8128	/* 0x0c */ IEMOP_X4(iemOp_Invalid),
8129	/* 0x0d */ IEMOP_X4(iemOp_nop_Ev_GrpP),
8130	/* 0x0e */ IEMOP_X4(iemOp_femms),
8131	/* 0x0f */ IEMOP_X4(iemOp_3Dnow),
8132
8133	/* 0x10 */ iemOp_vmovups_Vps_Wps, iemOp_vmovupd_Vpd_Wpd, iemOp_vmovss_Vx_Hx_Wss, iemOp_vmovsd_Vx_Hx_Wsd,
8134	/* 0x11 */ iemOp_vmovups_Wps_Vps, iemOp_vmovupd_Wpd_Vpd, iemOp_vmovss_Wss_Hx_Vss, iemOp_vmovsd_Wsd_Hx_Vsd,
8135	/* 0x12 */ iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx, iemOp_vmovddup_Vx_Wx,
8136	/* 0x13 */ iemOp_vmovlps_Mq_Vq, iemOp_vmovlpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8137	/* 0x14 */ iemOp_vunpcklps_Vx_Hx_Wx, iemOp_vunpcklpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8138	/* 0x15 */ iemOp_vunpckhps_Vx_Hx_Wx, iemOp_vunpckhpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8139	/* 0x16 */ iemOp_vmovhpsv1_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq, iemOp_vmovhpdv1_Vdq_Hq_Mq, iemOp_vmovshdup_Vx_Wx, iemOp_InvalidNeedRM,
8140	/* 0x17 */ iemOp_vmovhpsv1_Mq_Vq, iemOp_vmovhpdv1_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8141	/* 0x18 */ IEMOP_X4(iemOp_prefetch_Grp16),
8142	/* 0x19 */ IEMOP_X4(iemOp_nop_Ev),
8143	/* 0x1a */ IEMOP_X4(iemOp_nop_Ev),
8144	/* 0x1b */ IEMOP_X4(iemOp_nop_Ev),
8145	/* 0x1c */ IEMOP_X4(iemOp_nop_Ev),
8146	/* 0x1d */ IEMOP_X4(iemOp_nop_Ev),
8147	/* 0x1e */ IEMOP_X4(iemOp_nop_Ev),
8148	/* 0x1f */ IEMOP_X4(iemOp_nop_Ev),
8149
8150	/* 0x20 */ iemOp_mov_Rd_Cd, iemOp_mov_Rd_Cd, iemOp_mov_Rd_Cd, iemOp_mov_Rd_Cd,
8151	/* 0x21 */ iemOp_mov_Rd_Dd, iemOp_mov_Rd_Dd, iemOp_mov_Rd_Dd, iemOp_mov_Rd_Dd,
8152	/* 0x22 */ iemOp_mov_Cd_Rd, iemOp_mov_Cd_Rd, iemOp_mov_Cd_Rd, iemOp_mov_Cd_Rd,
8153	/* 0x23 */ iemOp_mov_Dd_Rd, iemOp_mov_Dd_Rd, iemOp_mov_Dd_Rd, iemOp_mov_Dd_Rd,
8154	/* 0x24 */ iemOp_mov_Rd_Td, iemOp_mov_Rd_Td, iemOp_mov_Rd_Td, iemOp_mov_Rd_Td,
8155	/* 0x25 */ iemOp_Invalid, iemOp_Invalid, iemOp_Invalid, iemOp_Invalid,
8156	/* 0x26 */ iemOp_mov_Td_Rd, iemOp_mov_Td_Rd, iemOp_mov_Td_Rd, iemOp_mov_Td_Rd,
8157	/* 0x27 */ iemOp_Invalid, iemOp_Invalid, iemOp_Invalid, iemOp_Invalid,
8158	/* 0x28 */ iemOp_vmovaps_Vps_Wps, iemOp_vmovapd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8159	/* 0x29 */ iemOp_vmovaps_Wps_Vps, iemOp_vmovapd_Wpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8160	/* 0x2a */ iemOp_cvtpi2ps_Vps_Qpi, iemOp_cvtpi2pd_Vpd_Qpi, iemOp_vcvtsi2ss_Vss_Hss_Ey, iemOp_vcvtsi2sd_Vsd_Hsd_Ey,
8161	/* 0x2b */ iemOp_vmovntps_Mps_Vps, iemOp_vmovntpd_Mpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8162	/* 0x2c */ iemOp_cvttps2pi_Ppi_Wps, iemOp_cvttpd2pi_Ppi_Wpd, iemOp_vcvttss2si_Gy_Wss, iemOp_vcvttsd2si_Gy_Wsd,
8163	/* 0x2d */ iemOp_cvtps2pi_Ppi_Wps, iemOp_cvtpd2pi_Qpi_Wpd, iemOp_vcvtss2si_Gy_Wss, iemOp_vcvtsd2si_Gy_Wsd,
8164	/* 0x2e */ iemOp_vucomiss_Vss_Wss, iemOp_vucomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8165	/* 0x2f */ iemOp_vcomiss_Vss_Wss, iemOp_vcomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8166
8167	/* 0x30 */ IEMOP_X4(iemOp_wrmsr),
8168	/* 0x31 */ IEMOP_X4(iemOp_rdtsc),
8169	/* 0x32 */ IEMOP_X4(iemOp_rdmsr),
8170	/* 0x33 */ IEMOP_X4(iemOp_rdpmc),
8171	/* 0x34 */ IEMOP_X4(iemOp_sysenter),
8172	/* 0x35 */ IEMOP_X4(iemOp_sysexit),
8173	/* 0x36 */ IEMOP_X4(iemOp_Invalid),
8174	/* 0x37 */ IEMOP_X4(iemOp_getsec),
8175	/* 0x38 */ IEMOP_X4(iemOp_3byte_Esc_A4),
8176	/* 0x39 */ IEMOP_X4(iemOp_InvalidNeed3ByteEscRM),
8177	/* 0x3a */ IEMOP_X4(iemOp_3byte_Esc_A5),
8178	/* 0x3b */ IEMOP_X4(iemOp_InvalidNeed3ByteEscRMImm8),
8179	/* 0x3c */ IEMOP_X4(iemOp_InvalidNeed3ByteEscRM),
8180	/* 0x3d */ IEMOP_X4(iemOp_InvalidNeed3ByteEscRM),
8181	/* 0x3e */ IEMOP_X4(iemOp_InvalidNeed3ByteEscRMImm8),
8182	/* 0x3f */ IEMOP_X4(iemOp_InvalidNeed3ByteEscRMImm8),
8183
8184	/* 0x40 */ IEMOP_X4(iemOp_cmovo_Gv_Ev),
8185	/* 0x41 */ IEMOP_X4(iemOp_cmovno_Gv_Ev),
8186	/* 0x42 */ IEMOP_X4(iemOp_cmovc_Gv_Ev),
8187	/* 0x43 */ IEMOP_X4(iemOp_cmovnc_Gv_Ev),
8188	/* 0x44 */ IEMOP_X4(iemOp_cmove_Gv_Ev),
8189	/* 0x45 */ IEMOP_X4(iemOp_cmovne_Gv_Ev),
8190	/* 0x46 */ IEMOP_X4(iemOp_cmovbe_Gv_Ev),
8191	/* 0x47 */ IEMOP_X4(iemOp_cmovnbe_Gv_Ev),
8192	/* 0x48 */ IEMOP_X4(iemOp_cmovs_Gv_Ev),
8193	/* 0x49 */ IEMOP_X4(iemOp_cmovns_Gv_Ev),
8194	/* 0x4a */ IEMOP_X4(iemOp_cmovp_Gv_Ev),
8195	/* 0x4b */ IEMOP_X4(iemOp_cmovnp_Gv_Ev),
8196	/* 0x4c */ IEMOP_X4(iemOp_cmovl_Gv_Ev),
8197	/* 0x4d */ IEMOP_X4(iemOp_cmovnl_Gv_Ev),
8198	/* 0x4e */ IEMOP_X4(iemOp_cmovle_Gv_Ev),
8199	/* 0x4f */ IEMOP_X4(iemOp_cmovnle_Gv_Ev),
8200
8201	/* 0x50 */ iemOp_vmovmskps_Gy_Ups, iemOp_vmovmskpd_Gy_Upd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8202	/* 0x51 */ iemOp_vsqrtps_Vps_Wps, iemOp_vsqrtpd_Vpd_Wpd, iemOp_vsqrtss_Vss_Hss_Wss, iemOp_vsqrtsd_Vsd_Hsd_Wsd,
8203	/* 0x52 */ iemOp_vrsqrtps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrsqrtss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
8204	/* 0x53 */ iemOp_vrcpps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrcpss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
8205	/* 0x54 */ iemOp_vandps_Vps_Hps_Wps, iemOp_vandpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8206	/* 0x55 */ iemOp_vandnps_Vps_Hps_Wps, iemOp_vandnpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8207	/* 0x56 */ iemOp_vorps_Vps_Hps_Wps, iemOp_vorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8208	/* 0x57 */ iemOp_vxorps_Vps_Hps_Wps, iemOp_vxorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8209	/* 0x58 */ iemOp_vaddps_Vps_Hps_Wps, iemOp_vaddpd_Vpd_Hpd_Wpd, iemOp_vaddss_Vss_Hss_Wss, iemOp_vaddsd_Vsd_Hsd_Wsd,
8210	/* 0x59 */ iemOp_vmulps_Vps_Hps_Wps, iemOp_vmulpd_Vpd_Hpd_Wpd, iemOp_vmulss_Vss_Hss_Wss, iemOp_vmulsd_Vsd_Hsd_Wsd,
8211	/* 0x5a */ iemOp_vcvtps2pd_Vpd_Wps, iemOp_vcvtpd2ps_Vps_Wpd, iemOp_vcvtss2sd_Vsd_Hx_Wss, iemOp_vcvtsd2ss_Vss_Hx_Wsd,
8212	/* 0x5b */ iemOp_vcvtdq2ps_Vps_Wdq, iemOp_vcvtps2dq_Vdq_Wps, iemOp_vcvttps2dq_Vdq_Wps, iemOp_InvalidNeedRM,
8213	/* 0x5c */ iemOp_vsubps_Vps_Hps_Wps, iemOp_vsubpd_Vpd_Hpd_Wpd, iemOp_vsubss_Vss_Hss_Wss, iemOp_vsubsd_Vsd_Hsd_Wsd,
8214	/* 0x5d */ iemOp_vminps_Vps_Hps_Wps, iemOp_vminpd_Vpd_Hpd_Wpd, iemOp_vminss_Vss_Hss_Wss, iemOp_vminsd_Vsd_Hsd_Wsd,
8215	/* 0x5e */ iemOp_vdivps_Vps_Hps_Wps, iemOp_vdivpd_Vpd_Hpd_Wpd, iemOp_vdivss_Vss_Hss_Wss, iemOp_vdivsd_Vsd_Hsd_Wsd,
8216	/* 0x5f */ iemOp_vmaxps_Vps_Hps_Wps, iemOp_vmaxpd_Vpd_Hpd_Wpd, iemOp_vmaxss_Vss_Hss_Wss, iemOp_vmaxsd_Vsd_Hsd_Wsd,
8217
8218	/* 0x60 */ iemOp_punpcklbw_Pq_Qd, iemOp_vpunpcklbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8219	/* 0x61 */ iemOp_punpcklwd_Pq_Qd, iemOp_vpunpcklwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8220	/* 0x62 */ iemOp_punpckldq_Pq_Qd, iemOp_vpunpckldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8221	/* 0x63 */ iemOp_packsswb_Pq_Qq, iemOp_vpacksswb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8222	/* 0x64 */ iemOp_pcmpgtb_Pq_Qq, iemOp_vpcmpgtb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8223	/* 0x65 */ iemOp_pcmpgtw_Pq_Qq, iemOp_vpcmpgtw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8224	/* 0x66 */ iemOp_pcmpgtd_Pq_Qq, iemOp_vpcmpgtd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8225	/* 0x67 */ iemOp_packuswb_Pq_Qq, iemOp_vpackuswb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8226	/* 0x68 */ iemOp_punpckhbw_Pq_Qd, iemOp_vpunpckhbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8227	/* 0x69 */ iemOp_punpckhwd_Pq_Qd, iemOp_vpunpckhwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8228	/* 0x6a */ iemOp_punpckhdq_Pq_Qd, iemOp_vpunpckhdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8229	/* 0x6b */ iemOp_packssdw_Pq_Qd, iemOp_vpackssdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8230	/* 0x6c */ iemOp_InvalidNeedRM, iemOp_vpunpcklqdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8231	/* 0x6d */ iemOp_InvalidNeedRM, iemOp_vpunpckhqdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8232	/* 0x6e */ iemOp_movd_q_Pd_Ey, iemOp_vmovd_q_Vy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8233	/* 0x6f */ iemOp_movq_Pq_Qq, iemOp_vmovdqa_Vx_Wx, iemOp_vmovdqu_Vx_Wx, iemOp_InvalidNeedRM,
8234
8235	/* 0x70 */ iemOp_pshufw_Pq_Qq_Ib, iemOp_vpshufd_Vx_Wx_Ib, iemOp_vpshufhw_Vx_Wx_Ib, iemOp_vpshuflw_Vx_Wx_Ib,
8236	/* 0x71 */ IEMOP_X4(iemOp_Grp12),
8237	/* 0x72 */ IEMOP_X4(iemOp_Grp13),
8238	/* 0x73 */ IEMOP_X4(iemOp_Grp14),
8239	/* 0x74 */ iemOp_pcmpeqb_Pq_Qq, iemOp_vpcmpeqb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8240	/* 0x75 */ iemOp_pcmpeqw_Pq_Qq, iemOp_vpcmpeqw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8241	/* 0x76 */ iemOp_pcmpeqd_Pq_Qq, iemOp_vpcmpeqd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8242	/* 0x77 */ iemOp_emms__vzeroupperv__vzeroallv, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8243
8244	/* 0x78 */ iemOp_vmread_Ey_Gy, iemOp_AmdGrp17, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8245	/* 0x79 */ iemOp_vmwrite_Gy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8246	/* 0x7a */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8247	/* 0x7b */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8248	/* 0x7c */ iemOp_InvalidNeedRM, iemOp_vhaddpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhaddps_Vps_Hps_Wps,
8249	/* 0x7d */ iemOp_InvalidNeedRM, iemOp_vhsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhsubps_Vps_Hps_Wps,
8250	/* 0x7e */ iemOp_movd_q_Ey_Pd, iemOp_vmovd_q_Ey_Vy, iemOp_vmovq_Vq_Wq, iemOp_InvalidNeedRM,
8251	/* 0x7f */ iemOp_movq_Qq_Pq, iemOp_vmovdqa_Wx_Vx, iemOp_vmovdqu_Wx_Vx, iemOp_InvalidNeedRM,
8252
8253	/* 0x80 */ IEMOP_X4(iemOp_jo_Jv),
8254	/* 0x81 */ IEMOP_X4(iemOp_jno_Jv),
8255	/* 0x82 */ IEMOP_X4(iemOp_jc_Jv),
8256	/* 0x83 */ IEMOP_X4(iemOp_jnc_Jv),
8257	/* 0x84 */ IEMOP_X4(iemOp_je_Jv),
8258	/* 0x85 */ IEMOP_X4(iemOp_jne_Jv),
8259	/* 0x86 */ IEMOP_X4(iemOp_jbe_Jv),
8260	/* 0x87 */ IEMOP_X4(iemOp_jnbe_Jv),
8261	/* 0x88 */ IEMOP_X4(iemOp_js_Jv),
8262	/* 0x89 */ IEMOP_X4(iemOp_jns_Jv),
8263	/* 0x8a */ IEMOP_X4(iemOp_jp_Jv),
8264	/* 0x8b */ IEMOP_X4(iemOp_jnp_Jv),
8265	/* 0x8c */ IEMOP_X4(iemOp_jl_Jv),
8266	/* 0x8d */ IEMOP_X4(iemOp_jnl_Jv),
8267	/* 0x8e */ IEMOP_X4(iemOp_jle_Jv),
8268	/* 0x8f */ IEMOP_X4(iemOp_jnle_Jv),
8269
8270	/* 0x90 */ IEMOP_X4(iemOp_seto_Eb),
8271	/* 0x91 */ IEMOP_X4(iemOp_setno_Eb),
8272	/* 0x92 */ IEMOP_X4(iemOp_setc_Eb),
8273	/* 0x93 */ IEMOP_X4(iemOp_setnc_Eb),
8274	/* 0x94 */ IEMOP_X4(iemOp_sete_Eb),
8275	/* 0x95 */ IEMOP_X4(iemOp_setne_Eb),
8276	/* 0x96 */ IEMOP_X4(iemOp_setbe_Eb),
8277	/* 0x97 */ IEMOP_X4(iemOp_setnbe_Eb),
8278	/* 0x98 */ IEMOP_X4(iemOp_sets_Eb),
8279	/* 0x99 */ IEMOP_X4(iemOp_setns_Eb),
8280	/* 0x9a */ IEMOP_X4(iemOp_setp_Eb),
8281	/* 0x9b */ IEMOP_X4(iemOp_setnp_Eb),
8282	/* 0x9c */ IEMOP_X4(iemOp_setl_Eb),
8283	/* 0x9d */ IEMOP_X4(iemOp_setnl_Eb),
8284	/* 0x9e */ IEMOP_X4(iemOp_setle_Eb),
8285	/* 0x9f */ IEMOP_X4(iemOp_setnle_Eb),
8286
8287	/* 0xa0 */ IEMOP_X4(iemOp_push_fs),
8288	/* 0xa1 */ IEMOP_X4(iemOp_pop_fs),
8289	/* 0xa2 */ IEMOP_X4(iemOp_cpuid),
8290	/* 0xa3 */ IEMOP_X4(iemOp_bt_Ev_Gv),
8291	/* 0xa4 */ IEMOP_X4(iemOp_shld_Ev_Gv_Ib),
8292	/* 0xa5 */ IEMOP_X4(iemOp_shld_Ev_Gv_CL),
8293	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
8294	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
8295	/* 0xa8 */ IEMOP_X4(iemOp_push_gs),
8296	/* 0xa9 */ IEMOP_X4(iemOp_pop_gs),
8297	/* 0xaa */ IEMOP_X4(iemOp_rsm),
8298	/* 0xab */ IEMOP_X4(iemOp_bts_Ev_Gv),
8299	/* 0xac */ IEMOP_X4(iemOp_shrd_Ev_Gv_Ib),
8300	/* 0xad */ IEMOP_X4(iemOp_shrd_Ev_Gv_CL),
8301	/* 0xae */ IEMOP_X4(iemOp_Grp15),
8302	/* 0xaf */ IEMOP_X4(iemOp_imul_Gv_Ev),
8303
8304	/* 0xb0 */ IEMOP_X4(iemOp_cmpxchg_Eb_Gb),
8305	/* 0xb1 */ IEMOP_X4(iemOp_cmpxchg_Ev_Gv),
8306	/* 0xb2 */ IEMOP_X4(iemOp_lss_Gv_Mp),
8307	/* 0xb3 */ IEMOP_X4(iemOp_btr_Ev_Gv),
8308	/* 0xb4 */ IEMOP_X4(iemOp_lfs_Gv_Mp),
8309	/* 0xb5 */ IEMOP_X4(iemOp_lgs_Gv_Mp),
8310	/* 0xb6 */ IEMOP_X4(iemOp_movzx_Gv_Eb),
8311	/* 0xb7 */ IEMOP_X4(iemOp_movzx_Gv_Ew),
8312	/* 0xb8 */ iemOp_jmpe, iemOp_InvalidNeedRM, iemOp_popcnt_Gv_Ev, iemOp_InvalidNeedRM,
8313	/* 0xb9 */ IEMOP_X4(iemOp_Grp10),
8314	/* 0xba */ IEMOP_X4(iemOp_Grp8),
8315	/* 0xbb */ IEMOP_X4(iemOp_btc_Ev_Gv), // 0xf3?
8316	/* 0xbc */ iemOp_bsf_Gv_Ev, iemOp_bsf_Gv_Ev, iemOp_tzcnt_Gv_Ev, iemOp_bsf_Gv_Ev,
8317	/* 0xbd */ iemOp_bsr_Gv_Ev, iemOp_bsr_Gv_Ev, iemOp_lzcnt_Gv_Ev, iemOp_bsr_Gv_Ev,
8318	/* 0xbe */ IEMOP_X4(iemOp_movsx_Gv_Eb),
8319	/* 0xbf */ IEMOP_X4(iemOp_movsx_Gv_Ew),
8320
8321	/* 0xc0 */ IEMOP_X4(iemOp_xadd_Eb_Gb),
8322	/* 0xc1 */ IEMOP_X4(iemOp_xadd_Ev_Gv),
8323	/* 0xc2 */ iemOp_vcmpps_Vps_Hps_Wps_Ib, iemOp_vcmppd_Vpd_Hpd_Wpd_Ib, iemOp_vcmpss_Vss_Hss_Wss_Ib, iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib,
8324	/* 0xc3 */ iemOp_movnti_My_Gy, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8325	/* 0xc4 */ iemOp_pinsrw_Pq_RyMw_Ib, iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
8326	/* 0xc5 */ iemOp_pextrw_Gd_Nq_Ib, iemOp_vpextrw_Gd_Udq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
8327	/* 0xc6 */ iemOp_vshufps_Vps_Hps_Wps_Ib, iemOp_vshufpd_Vpd_Hpd_Wpd_Ib, iemOp_InvalidNeedRMImm8,iemOp_InvalidNeedRMImm8,
8328	/* 0xc7 */ IEMOP_X4(iemOp_Grp9),
8329	/* 0xc8 */ IEMOP_X4(iemOp_bswap_rAX_r8),
8330	/* 0xc9 */ IEMOP_X4(iemOp_bswap_rCX_r9),
8331	/* 0xca */ IEMOP_X4(iemOp_bswap_rDX_r10),
8332	/* 0xcb */ IEMOP_X4(iemOp_bswap_rBX_r11),
8333	/* 0xcc */ IEMOP_X4(iemOp_bswap_rSP_r12),
8334	/* 0xcd */ IEMOP_X4(iemOp_bswap_rBP_r13),
8335	/* 0xce */ IEMOP_X4(iemOp_bswap_rSI_r14),
8336	/* 0xcf */ IEMOP_X4(iemOp_bswap_rDI_r15),
8337
8338	/* 0xd0 */ iemOp_InvalidNeedRM, iemOp_vaddsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vaddsubps_Vps_Hps_Wps,
8339	/* 0xd1 */ iemOp_psrlw_Pq_Qq, iemOp_vpsrlw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8340	/* 0xd2 */ iemOp_psrld_Pq_Qq, iemOp_vpsrld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8341	/* 0xd3 */ iemOp_psrlq_Pq_Qq, iemOp_vpsrlq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8342	/* 0xd4 */ iemOp_paddq_Pq_Qq, iemOp_vpaddq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8343	/* 0xd5 */ iemOp_pmullw_Pq_Qq, iemOp_vpmullw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8344	/* 0xd6 */ iemOp_InvalidNeedRM, iemOp_vmovq_Wq_Vq, iemOp_movq2dq_Vdq_Nq, iemOp_movdq2q_Pq_Uq,
8345	/* 0xd7 */ iemOp_pmovmskb_Gd_Nq, iemOp_vpmovmskb_Gd_Ux, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8346	/* 0xd8 */ iemOp_psubusb_Pq_Qq, iemOp_vpsubusb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8347	/* 0xd9 */ iemOp_psubusw_Pq_Qq, iemOp_vpsubusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8348	/* 0xda */ iemOp_pminub_Pq_Qq, iemOp_vpminub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8349	/* 0xdb */ iemOp_pand_Pq_Qq, iemOp_vpand_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8350	/* 0xdc */ iemOp_paddusb_Pq_Qq, iemOp_vpaddusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8351	/* 0xdd */ iemOp_paddusw_Pq_Qq, iemOp_vpaddusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8352	/* 0xde */ iemOp_pmaxub_Pq_Qq, iemOp_vpmaxub_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8353	/* 0xdf */ iemOp_pandn_Pq_Qq, iemOp_vpandn_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8354
8355	/* 0xe0 */ iemOp_pavgb_Pq_Qq, iemOp_vpavgb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8356	/* 0xe1 */ iemOp_psraw_Pq_Qq, iemOp_vpsraw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8357	/* 0xe2 */ iemOp_psrad_Pq_Qq, iemOp_vpsrad_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8358	/* 0xe3 */ iemOp_pavgw_Pq_Qq, iemOp_vpavgw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8359	/* 0xe4 */ iemOp_pmulhuw_Pq_Qq, iemOp_vpmulhuw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8360	/* 0xe5 */ iemOp_pmulhw_Pq_Qq, iemOp_vpmulhw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8361	/* 0xe6 */ iemOp_InvalidNeedRM, iemOp_vcvttpd2dq_Vx_Wpd, iemOp_vcvtdq2pd_Vx_Wpd, iemOp_vcvtpd2dq_Vx_Wpd,
8362	/* 0xe7 */ iemOp_movntq_Mq_Pq, iemOp_vmovntdq_Mx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8363	/* 0xe8 */ iemOp_psubsb_Pq_Qq, iemOp_vpsubsb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8364	/* 0xe9 */ iemOp_psubsw_Pq_Qq, iemOp_vpsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8365	/* 0xea */ iemOp_pminsw_Pq_Qq, iemOp_vpminsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8366	/* 0xeb */ iemOp_por_Pq_Qq, iemOp_vpor_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8367	/* 0xec */ iemOp_paddsb_Pq_Qq, iemOp_vpaddsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8368	/* 0xed */ iemOp_paddsw_Pq_Qq, iemOp_vpaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8369	/* 0xee */ iemOp_pmaxsw_Pq_Qq, iemOp_vpmaxsw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8370	/* 0xef */ iemOp_pxor_Pq_Qq, iemOp_vpxor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8371
8372	/* 0xf0 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vlddqu_Vx_Mx,
8373	/* 0xf1 */ iemOp_psllw_Pq_Qq, iemOp_vpsllw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8374	/* 0xf2 */ iemOp_pslld_Pq_Qq, iemOp_vpslld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8375	/* 0xf3 */ iemOp_psllq_Pq_Qq, iemOp_vpsllq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8376	/* 0xf4 */ iemOp_pmuludq_Pq_Qq, iemOp_vpmuludq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8377	/* 0xf5 */ iemOp_pmaddwd_Pq_Qq, iemOp_vpmaddwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8378	/* 0xf6 */ iemOp_psadbw_Pq_Qq, iemOp_vpsadbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8379	/* 0xf7 */ iemOp_maskmovq_Pq_Nq, iemOp_vmaskmovdqu_Vdq_Udq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8380	/* 0xf8 */ iemOp_psubb_Pq_Qq, iemOp_vpsubb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8381	/* 0xf9 */ iemOp_psubw_Pq_Qq, iemOp_vpsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8382	/* 0xfa */ iemOp_psubd_Pq_Qq, iemOp_vpsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8383	/* 0xfb */ iemOp_psubq_Pq_Qq, iemOp_vpsubq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8384	/* 0xfc */ iemOp_paddb_Pq_Qq, iemOp_vpaddb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8385	/* 0xfd */ iemOp_paddw_Pq_Qq, iemOp_vpaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8386	/* 0xfe */ iemOp_paddd_Pq_Qq, iemOp_vpaddd_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8387	/* 0xff */ IEMOP_X4(iemOp_ud0),
8388	};
8389	AssertCompile(RT_ELEMENTS(g_apfnTwoByteMap) == 1024);
8390
8391
8392	/**
8393	* VEX opcode map \#1.
8394	*
8395	* @remarks This is (currently) a subset of g_apfnTwoByteMap, so please check if
8396	* it it needs updating too when making changes.
8397	*/
8398	IEM_STATIC const PFNIEMOP g_apfnVexMap1[] =
8399	{
8400	/* no prefix, 066h prefix f3h prefix, f2h prefix */
8401	/* 0x00 */ IEMOP_X4(iemOp_InvalidNeedRM),
8402	/* 0x01 */ IEMOP_X4(iemOp_InvalidNeedRM),
8403	/* 0x02 */ IEMOP_X4(iemOp_InvalidNeedRM),
8404	/* 0x03 */ IEMOP_X4(iemOp_InvalidNeedRM),
8405	/* 0x04 */ IEMOP_X4(iemOp_InvalidNeedRM),
8406	/* 0x05 */ IEMOP_X4(iemOp_InvalidNeedRM),
8407	/* 0x06 */ IEMOP_X4(iemOp_InvalidNeedRM),
8408	/* 0x07 */ IEMOP_X4(iemOp_InvalidNeedRM),
8409	/* 0x08 */ IEMOP_X4(iemOp_InvalidNeedRM),
8410	/* 0x09 */ IEMOP_X4(iemOp_InvalidNeedRM),
8411	/* 0x0a */ IEMOP_X4(iemOp_InvalidNeedRM),
8412	/* 0x0b */ IEMOP_X4(iemOp_InvalidNeedRM),
8413	/* 0x0c */ IEMOP_X4(iemOp_InvalidNeedRM),
8414	/* 0x0d */ IEMOP_X4(iemOp_InvalidNeedRM),
8415	/* 0x0e */ IEMOP_X4(iemOp_InvalidNeedRM),
8416	/* 0x0f */ IEMOP_X4(iemOp_InvalidNeedRM),
8417
8418	/* 0x10 */ iemOp_vmovups_Vps_Wps, iemOp_vmovupd_Vpd_Wpd, iemOp_vmovss_Vx_Hx_Wss, iemOp_vmovsd_Vx_Hx_Wsd,
8419	/* 0x11 */ iemOp_vmovups_Wps_Vps, iemOp_vmovupd_Wpd_Vpd, iemOp_vmovss_Wss_Hx_Vss, iemOp_vmovsd_Wsd_Hx_Vsd,
8420	/* 0x12 */ iemOp_vmovlps_Vq_Hq_Mq__vmovhlps, iemOp_vmovlpd_Vq_Hq_Mq, iemOp_vmovsldup_Vx_Wx, iemOp_vmovddup_Vx_Wx,
8421	/* 0x13 */ iemOp_vmovlps_Mq_Vq, iemOp_vmovlpd_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8422	/* 0x14 */ iemOp_vunpcklps_Vx_Hx_Wx, iemOp_vunpcklpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8423	/* 0x15 */ iemOp_vunpckhps_Vx_Hx_Wx, iemOp_vunpckhpd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8424	/* 0x16 */ iemOp_vmovhpsv1_Vdq_Hq_Mq__vmovlhps_Vdq_Hq_Uq, iemOp_vmovhpdv1_Vdq_Hq_Mq, iemOp_vmovshdup_Vx_Wx, iemOp_InvalidNeedRM,
8425	/* 0x17 */ iemOp_vmovhpsv1_Mq_Vq, iemOp_vmovhpdv1_Mq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8426	/* 0x18 */ IEMOP_X4(iemOp_InvalidNeedRM),
8427	/* 0x19 */ IEMOP_X4(iemOp_InvalidNeedRM),
8428	/* 0x1a */ IEMOP_X4(iemOp_InvalidNeedRM),
8429	/* 0x1b */ IEMOP_X4(iemOp_InvalidNeedRM),
8430	/* 0x1c */ IEMOP_X4(iemOp_InvalidNeedRM),
8431	/* 0x1d */ IEMOP_X4(iemOp_InvalidNeedRM),
8432	/* 0x1e */ IEMOP_X4(iemOp_InvalidNeedRM),
8433	/* 0x1f */ IEMOP_X4(iemOp_InvalidNeedRM),
8434
8435	/* 0x20 */ IEMOP_X4(iemOp_InvalidNeedRM),
8436	/* 0x21 */ IEMOP_X4(iemOp_InvalidNeedRM),
8437	/* 0x22 */ IEMOP_X4(iemOp_InvalidNeedRM),
8438	/* 0x23 */ IEMOP_X4(iemOp_InvalidNeedRM),
8439	/* 0x24 */ IEMOP_X4(iemOp_InvalidNeedRM),
8440	/* 0x25 */ IEMOP_X4(iemOp_InvalidNeedRM),
8441	/* 0x26 */ IEMOP_X4(iemOp_InvalidNeedRM),
8442	/* 0x27 */ IEMOP_X4(iemOp_InvalidNeedRM),
8443	/* 0x28 */ iemOp_vmovaps_Vps_Wps, iemOp_vmovapd_Vpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8444	/* 0x29 */ iemOp_vmovaps_Wps_Vps, iemOp_vmovapd_Wpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8445	/* 0x2a */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtsi2ss_Vss_Hss_Ey, iemOp_vcvtsi2sd_Vsd_Hsd_Ey,
8446	/* 0x2b */ iemOp_vmovntps_Mps_Vps, iemOp_vmovntpd_Mpd_Vpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8447	/* 0x2c */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvttss2si_Gy_Wss, iemOp_vcvttsd2si_Gy_Wsd,
8448	/* 0x2d */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vcvtss2si_Gy_Wss, iemOp_vcvtsd2si_Gy_Wsd,
8449	/* 0x2e */ iemOp_vucomiss_Vss_Wss, iemOp_vucomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8450	/* 0x2f */ iemOp_vcomiss_Vss_Wss, iemOp_vcomisd_Vsd_Wsd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8451
8452	/* 0x30 */ IEMOP_X4(iemOp_InvalidNeedRM),
8453	/* 0x31 */ IEMOP_X4(iemOp_InvalidNeedRM),
8454	/* 0x32 */ IEMOP_X4(iemOp_InvalidNeedRM),
8455	/* 0x33 */ IEMOP_X4(iemOp_InvalidNeedRM),
8456	/* 0x34 */ IEMOP_X4(iemOp_InvalidNeedRM),
8457	/* 0x35 */ IEMOP_X4(iemOp_InvalidNeedRM),
8458	/* 0x36 */ IEMOP_X4(iemOp_InvalidNeedRM),
8459	/* 0x37 */ IEMOP_X4(iemOp_InvalidNeedRM),
8460	/* 0x38 / IEMOP_X4(iemOp_InvalidNeedRM), /* @todo check that there is no escape table stuff here */
8461	/* 0x39 / IEMOP_X4(iemOp_InvalidNeedRM), /* @todo check that there is no escape table stuff here */
8462	/* 0x3a / IEMOP_X4(iemOp_InvalidNeedRM), /* @todo check that there is no escape table stuff here */
8463	/* 0x3b / IEMOP_X4(iemOp_InvalidNeedRM), /* @todo check that there is no escape table stuff here */
8464	/* 0x3c / IEMOP_X4(iemOp_InvalidNeedRM), /* @todo check that there is no escape table stuff here */
8465	/* 0x3d / IEMOP_X4(iemOp_InvalidNeedRM), /* @todo check that there is no escape table stuff here */
8466	/* 0x3e / IEMOP_X4(iemOp_InvalidNeedRM), /* @todo check that there is no escape table stuff here */
8467	/* 0x3f / IEMOP_X4(iemOp_InvalidNeedRM), /* @todo check that there is no escape table stuff here */
8468
8469	/* 0x40 */ IEMOP_X4(iemOp_InvalidNeedRM),
8470	/* 0x41 */ IEMOP_X4(iemOp_InvalidNeedRM),
8471	/* 0x42 */ IEMOP_X4(iemOp_InvalidNeedRM),
8472	/* 0x43 */ IEMOP_X4(iemOp_InvalidNeedRM),
8473	/* 0x44 */ IEMOP_X4(iemOp_InvalidNeedRM),
8474	/* 0x45 */ IEMOP_X4(iemOp_InvalidNeedRM),
8475	/* 0x46 */ IEMOP_X4(iemOp_InvalidNeedRM),
8476	/* 0x47 */ IEMOP_X4(iemOp_InvalidNeedRM),
8477	/* 0x48 */ IEMOP_X4(iemOp_InvalidNeedRM),
8478	/* 0x49 */ IEMOP_X4(iemOp_InvalidNeedRM),
8479	/* 0x4a */ IEMOP_X4(iemOp_InvalidNeedRM),
8480	/* 0x4b */ IEMOP_X4(iemOp_InvalidNeedRM),
8481	/* 0x4c */ IEMOP_X4(iemOp_InvalidNeedRM),
8482	/* 0x4d */ IEMOP_X4(iemOp_InvalidNeedRM),
8483	/* 0x4e */ IEMOP_X4(iemOp_InvalidNeedRM),
8484	/* 0x4f */ IEMOP_X4(iemOp_InvalidNeedRM),
8485
8486	/* 0x50 */ iemOp_vmovmskps_Gy_Ups, iemOp_vmovmskpd_Gy_Upd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8487	/* 0x51 */ iemOp_vsqrtps_Vps_Wps, iemOp_vsqrtpd_Vpd_Wpd, iemOp_vsqrtss_Vss_Hss_Wss, iemOp_vsqrtsd_Vsd_Hsd_Wsd,
8488	/* 0x52 */ iemOp_vrsqrtps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrsqrtss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
8489	/* 0x53 */ iemOp_vrcpps_Vps_Wps, iemOp_InvalidNeedRM, iemOp_vrcpss_Vss_Hss_Wss, iemOp_InvalidNeedRM,
8490	/* 0x54 */ iemOp_vandps_Vps_Hps_Wps, iemOp_vandpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8491	/* 0x55 */ iemOp_vandnps_Vps_Hps_Wps, iemOp_vandnpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8492	/* 0x56 */ iemOp_vorps_Vps_Hps_Wps, iemOp_vorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8493	/* 0x57 */ iemOp_vxorps_Vps_Hps_Wps, iemOp_vxorpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8494	/* 0x58 */ iemOp_vaddps_Vps_Hps_Wps, iemOp_vaddpd_Vpd_Hpd_Wpd, iemOp_vaddss_Vss_Hss_Wss, iemOp_vaddsd_Vsd_Hsd_Wsd,
8495	/* 0x59 */ iemOp_vmulps_Vps_Hps_Wps, iemOp_vmulpd_Vpd_Hpd_Wpd, iemOp_vmulss_Vss_Hss_Wss, iemOp_vmulsd_Vsd_Hsd_Wsd,
8496	/* 0x5a */ iemOp_vcvtps2pd_Vpd_Wps, iemOp_vcvtpd2ps_Vps_Wpd, iemOp_vcvtss2sd_Vsd_Hx_Wss, iemOp_vcvtsd2ss_Vss_Hx_Wsd,
8497	/* 0x5b */ iemOp_vcvtdq2ps_Vps_Wdq, iemOp_vcvtps2dq_Vdq_Wps, iemOp_vcvttps2dq_Vdq_Wps, iemOp_InvalidNeedRM,
8498	/* 0x5c */ iemOp_vsubps_Vps_Hps_Wps, iemOp_vsubpd_Vpd_Hpd_Wpd, iemOp_vsubss_Vss_Hss_Wss, iemOp_vsubsd_Vsd_Hsd_Wsd,
8499	/* 0x5d */ iemOp_vminps_Vps_Hps_Wps, iemOp_vminpd_Vpd_Hpd_Wpd, iemOp_vminss_Vss_Hss_Wss, iemOp_vminsd_Vsd_Hsd_Wsd,
8500	/* 0x5e */ iemOp_vdivps_Vps_Hps_Wps, iemOp_vdivpd_Vpd_Hpd_Wpd, iemOp_vdivss_Vss_Hss_Wss, iemOp_vdivsd_Vsd_Hsd_Wsd,
8501	/* 0x5f */ iemOp_vmaxps_Vps_Hps_Wps, iemOp_vmaxpd_Vpd_Hpd_Wpd, iemOp_vmaxss_Vss_Hss_Wss, iemOp_vmaxsd_Vsd_Hsd_Wsd,
8502
8503	/* 0x60 */ iemOp_InvalidNeedRM, iemOp_vpunpcklbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8504	/* 0x61 */ iemOp_InvalidNeedRM, iemOp_vpunpcklwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8505	/* 0x62 */ iemOp_InvalidNeedRM, iemOp_vpunpckldq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8506	/* 0x63 */ iemOp_InvalidNeedRM, iemOp_vpacksswb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8507	/* 0x64 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8508	/* 0x65 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8509	/* 0x66 */ iemOp_InvalidNeedRM, iemOp_vpcmpgtd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8510	/* 0x67 */ iemOp_InvalidNeedRM, iemOp_vpackuswb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8511	/* 0x68 */ iemOp_InvalidNeedRM, iemOp_vpunpckhbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8512	/* 0x69 */ iemOp_InvalidNeedRM, iemOp_vpunpckhwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8513	/* 0x6a */ iemOp_InvalidNeedRM, iemOp_vpunpckhdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8514	/* 0x6b */ iemOp_InvalidNeedRM, iemOp_vpackssdw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8515	/* 0x6c */ iemOp_InvalidNeedRM, iemOp_vpunpcklqdq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8516	/* 0x6d */ iemOp_InvalidNeedRM, iemOp_vpunpckhqdq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8517	/* 0x6e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Vy_Ey, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8518	/* 0x6f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Vx_Wx, iemOp_vmovdqu_Vx_Wx, iemOp_InvalidNeedRM,
8519
8520	/* 0x70 */ iemOp_InvalidNeedRM, iemOp_vpshufd_Vx_Wx_Ib, iemOp_vpshufhw_Vx_Wx_Ib, iemOp_vpshuflw_Vx_Wx_Ib,
8521	/* 0x71 */ iemOp_InvalidNeedRM, iemOp_Grp12, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8522	/* 0x72 */ iemOp_InvalidNeedRM, iemOp_Grp13, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8523	/* 0x73 */ iemOp_InvalidNeedRM, iemOp_Grp14, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8524	/* 0x74 */ iemOp_pcmpeqb_Pq_Qq, iemOp_vpcmpeqb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8525	/* 0x75 */ iemOp_pcmpeqw_Pq_Qq, iemOp_vpcmpeqw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8526	/* 0x76 */ iemOp_pcmpeqd_Pq_Qq, iemOp_vpcmpeqd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8527	/* 0x77 */ iemOp_emms__vzeroupperv__vzeroallv, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8528	/* 0x78 */ IEMOP_X4(iemOp_InvalidNeedRM),
8529	/* 0x79 */ IEMOP_X4(iemOp_InvalidNeedRM),
8530	/* 0x7a */ IEMOP_X4(iemOp_InvalidNeedRM),
8531	/* 0x7b */ IEMOP_X4(iemOp_InvalidNeedRM),
8532	/* 0x7c */ iemOp_InvalidNeedRM, iemOp_vhaddpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhaddps_Vps_Hps_Wps,
8533	/* 0x7d */ iemOp_InvalidNeedRM, iemOp_vhsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vhsubps_Vps_Hps_Wps,
8534	/* 0x7e */ iemOp_InvalidNeedRM, iemOp_vmovd_q_Ey_Vy, iemOp_vmovq_Vq_Wq, iemOp_InvalidNeedRM,
8535	/* 0x7f */ iemOp_InvalidNeedRM, iemOp_vmovdqa_Wx_Vx, iemOp_vmovdqu_Wx_Vx, iemOp_InvalidNeedRM,
8536
8537	/* 0x80 */ IEMOP_X4(iemOp_InvalidNeedRM),
8538	/* 0x81 */ IEMOP_X4(iemOp_InvalidNeedRM),
8539	/* 0x82 */ IEMOP_X4(iemOp_InvalidNeedRM),
8540	/* 0x83 */ IEMOP_X4(iemOp_InvalidNeedRM),
8541	/* 0x84 */ IEMOP_X4(iemOp_InvalidNeedRM),
8542	/* 0x85 */ IEMOP_X4(iemOp_InvalidNeedRM),
8543	/* 0x86 */ IEMOP_X4(iemOp_InvalidNeedRM),
8544	/* 0x87 */ IEMOP_X4(iemOp_InvalidNeedRM),
8545	/* 0x88 */ IEMOP_X4(iemOp_InvalidNeedRM),
8546	/* 0x89 */ IEMOP_X4(iemOp_InvalidNeedRM),
8547	/* 0x8a */ IEMOP_X4(iemOp_InvalidNeedRM),
8548	/* 0x8b */ IEMOP_X4(iemOp_InvalidNeedRM),
8549	/* 0x8c */ IEMOP_X4(iemOp_InvalidNeedRM),
8550	/* 0x8d */ IEMOP_X4(iemOp_InvalidNeedRM),
8551	/* 0x8e */ IEMOP_X4(iemOp_InvalidNeedRM),
8552	/* 0x8f */ IEMOP_X4(iemOp_InvalidNeedRM),
8553	IEMOP_X4(iemOp_InvalidNeedRM),
8554	/* 0x90 */ IEMOP_X4(iemOp_InvalidNeedRM),
8555	/* 0x91 */ IEMOP_X4(iemOp_InvalidNeedRM),
8556	/* 0x92 */ IEMOP_X4(iemOp_InvalidNeedRM),
8557	/* 0x93 */ IEMOP_X4(iemOp_InvalidNeedRM),
8558	/* 0x94 */ IEMOP_X4(iemOp_InvalidNeedRM),
8559	/* 0x95 */ IEMOP_X4(iemOp_InvalidNeedRM),
8560	/* 0x96 */ IEMOP_X4(iemOp_InvalidNeedRM),
8561	/* 0x97 */ IEMOP_X4(iemOp_InvalidNeedRM),
8562	/* 0x98 */ IEMOP_X4(iemOp_InvalidNeedRM),
8563	/* 0x99 */ IEMOP_X4(iemOp_InvalidNeedRM),
8564	/* 0x9a */ IEMOP_X4(iemOp_InvalidNeedRM),
8565	/* 0x9b */ IEMOP_X4(iemOp_InvalidNeedRM),
8566	/* 0x9c */ IEMOP_X4(iemOp_InvalidNeedRM),
8567	/* 0x9d */ IEMOP_X4(iemOp_InvalidNeedRM),
8568	/* 0x9e */ IEMOP_X4(iemOp_InvalidNeedRM),
8569	/* 0x9f */ IEMOP_X4(iemOp_InvalidNeedRM),
8570
8571	/* 0xa0 */ IEMOP_X4(iemOp_InvalidNeedRM),
8572	/* 0xa1 */ IEMOP_X4(iemOp_InvalidNeedRM),
8573	/* 0xa2 */ IEMOP_X4(iemOp_InvalidNeedRM),
8574	/* 0xa3 */ IEMOP_X4(iemOp_InvalidNeedRM),
8575	/* 0xa4 */ IEMOP_X4(iemOp_InvalidNeedRM),
8576	/* 0xa5 */ IEMOP_X4(iemOp_InvalidNeedRM),
8577	/* 0xa6 */ IEMOP_X4(iemOp_InvalidNeedRM),
8578	/* 0xa7 */ IEMOP_X4(iemOp_InvalidNeedRM),
8579	/* 0xa8 */ IEMOP_X4(iemOp_InvalidNeedRM),
8580	/* 0xa9 */ IEMOP_X4(iemOp_InvalidNeedRM),
8581	/* 0xaa */ IEMOP_X4(iemOp_InvalidNeedRM),
8582	/* 0xab */ IEMOP_X4(iemOp_InvalidNeedRM),
8583	/* 0xac */ IEMOP_X4(iemOp_InvalidNeedRM),
8584	/* 0xad */ IEMOP_X4(iemOp_InvalidNeedRM),
8585	/* 0xae / IEMOP_X4(iemOp_Grp15), /* @todo groups and vex */
8586	/* 0xaf */ IEMOP_X4(iemOp_InvalidNeedRM),
8587
8588	/* 0xb0 */ IEMOP_X4(iemOp_InvalidNeedRM),
8589	/* 0xb1 */ IEMOP_X4(iemOp_InvalidNeedRM),
8590	/* 0xb2 */ IEMOP_X4(iemOp_InvalidNeedRM),
8591	/* 0xb3 */ IEMOP_X4(iemOp_InvalidNeedRM),
8592	/* 0xb4 */ IEMOP_X4(iemOp_InvalidNeedRM),
8593	/* 0xb5 */ IEMOP_X4(iemOp_InvalidNeedRM),
8594	/* 0xb6 */ IEMOP_X4(iemOp_InvalidNeedRM),
8595	/* 0xb7 */ IEMOP_X4(iemOp_InvalidNeedRM),
8596	/* 0xb8 */ IEMOP_X4(iemOp_InvalidNeedRM),
8597	/* 0xb9 */ IEMOP_X4(iemOp_InvalidNeedRM),
8598	/* 0xba */ IEMOP_X4(iemOp_InvalidNeedRM),
8599	/* 0xbb */ IEMOP_X4(iemOp_InvalidNeedRM),
8600	/* 0xbc */ IEMOP_X4(iemOp_InvalidNeedRM),
8601	/* 0xbd */ IEMOP_X4(iemOp_InvalidNeedRM),
8602	/* 0xbe */ IEMOP_X4(iemOp_InvalidNeedRM),
8603	/* 0xbf */ IEMOP_X4(iemOp_InvalidNeedRM),
8604
8605	/* 0xc0 */ IEMOP_X4(iemOp_InvalidNeedRM),
8606	/* 0xc1 */ IEMOP_X4(iemOp_InvalidNeedRM),
8607	/* 0xc2 */ iemOp_vcmpps_Vps_Hps_Wps_Ib, iemOp_vcmppd_Vpd_Hpd_Wpd_Ib, iemOp_vcmpss_Vss_Hss_Wss_Ib, iemOp_vcmpsd_Vsd_Hsd_Wsd_Ib,
8608	/* 0xc3 */ IEMOP_X4(iemOp_InvalidNeedRM),
8609	/* 0xc4 */ iemOp_InvalidNeedRM, iemOp_vpinsrw_Vdq_Hdq_RyMw_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
8610	/* 0xc5 */ iemOp_InvalidNeedRM, iemOp_vpextrw_Gd_Udq_Ib, iemOp_InvalidNeedRMImm8, iemOp_InvalidNeedRMImm8,
8611	/* 0xc6 */ iemOp_vshufps_Vps_Hps_Wps_Ib, iemOp_vshufpd_Vpd_Hpd_Wpd_Ib, iemOp_InvalidNeedRMImm8,iemOp_InvalidNeedRMImm8,
8612	/* 0xc7 */ IEMOP_X4(iemOp_InvalidNeedRM),
8613	/* 0xc8 */ IEMOP_X4(iemOp_InvalidNeedRM),
8614	/* 0xc9 */ IEMOP_X4(iemOp_InvalidNeedRM),
8615	/* 0xca */ IEMOP_X4(iemOp_InvalidNeedRM),
8616	/* 0xcb */ IEMOP_X4(iemOp_InvalidNeedRM),
8617	/* 0xcc */ IEMOP_X4(iemOp_InvalidNeedRM),
8618	/* 0xcd */ IEMOP_X4(iemOp_InvalidNeedRM),
8619	/* 0xce */ IEMOP_X4(iemOp_InvalidNeedRM),
8620	/* 0xcf */ IEMOP_X4(iemOp_InvalidNeedRM),
8621
8622	/* 0xd0 */ iemOp_InvalidNeedRM, iemOp_vaddsubpd_Vpd_Hpd_Wpd, iemOp_InvalidNeedRM, iemOp_vaddsubps_Vps_Hps_Wps,
8623	/* 0xd1 */ iemOp_InvalidNeedRM, iemOp_vpsrlw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8624	/* 0xd2 */ iemOp_InvalidNeedRM, iemOp_vpsrld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8625	/* 0xd3 */ iemOp_InvalidNeedRM, iemOp_vpsrlq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8626	/* 0xd4 */ iemOp_InvalidNeedRM, iemOp_vpaddq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8627	/* 0xd5 */ iemOp_InvalidNeedRM, iemOp_vpmullw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8628	/* 0xd6 */ iemOp_InvalidNeedRM, iemOp_vmovq_Wq_Vq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8629	/* 0xd7 */ iemOp_InvalidNeedRM, iemOp_vpmovmskb_Gd_Ux, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8630	/* 0xd8 */ iemOp_InvalidNeedRM, iemOp_vpsubusb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8631	/* 0xd9 */ iemOp_InvalidNeedRM, iemOp_vpsubusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8632	/* 0xda */ iemOp_InvalidNeedRM, iemOp_vpminub_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8633	/* 0xdb */ iemOp_InvalidNeedRM, iemOp_vpand_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8634	/* 0xdc */ iemOp_InvalidNeedRM, iemOp_vpaddusb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8635	/* 0xdd */ iemOp_InvalidNeedRM, iemOp_vpaddusw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8636	/* 0xde */ iemOp_InvalidNeedRM, iemOp_vpmaxub_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8637	/* 0xdf */ iemOp_InvalidNeedRM, iemOp_vpandn_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8638
8639	/* 0xe0 */ iemOp_InvalidNeedRM, iemOp_vpavgb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8640	/* 0xe1 */ iemOp_InvalidNeedRM, iemOp_vpsraw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8641	/* 0xe2 */ iemOp_InvalidNeedRM, iemOp_vpsrad_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8642	/* 0xe3 */ iemOp_InvalidNeedRM, iemOp_vpavgw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8643	/* 0xe4 */ iemOp_InvalidNeedRM, iemOp_vpmulhuw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8644	/* 0xe5 */ iemOp_InvalidNeedRM, iemOp_vpmulhw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8645	/* 0xe6 */ iemOp_InvalidNeedRM, iemOp_vcvttpd2dq_Vx_Wpd, iemOp_vcvtdq2pd_Vx_Wpd, iemOp_vcvtpd2dq_Vx_Wpd,
8646	/* 0xe7 */ iemOp_InvalidNeedRM, iemOp_vmovntdq_Mx_Vx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8647	/* 0xe8 */ iemOp_InvalidNeedRM, iemOp_vpsubsb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8648	/* 0xe9 */ iemOp_InvalidNeedRM, iemOp_vpsubsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8649	/* 0xea */ iemOp_InvalidNeedRM, iemOp_vpminsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8650	/* 0xeb */ iemOp_InvalidNeedRM, iemOp_vpor_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8651	/* 0xec */ iemOp_InvalidNeedRM, iemOp_vpaddsb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8652	/* 0xed */ iemOp_InvalidNeedRM, iemOp_vpaddsw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8653	/* 0xee */ iemOp_InvalidNeedRM, iemOp_vpmaxsw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8654	/* 0xef */ iemOp_InvalidNeedRM, iemOp_vpxor_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8655
8656	/* 0xf0 */ iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM, iemOp_vlddqu_Vx_Mx,
8657	/* 0xf1 */ iemOp_InvalidNeedRM, iemOp_vpsllw_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8658	/* 0xf2 */ iemOp_InvalidNeedRM, iemOp_vpslld_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8659	/* 0xf3 */ iemOp_InvalidNeedRM, iemOp_vpsllq_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8660	/* 0xf4 */ iemOp_InvalidNeedRM, iemOp_vpmuludq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8661	/* 0xf5 */ iemOp_InvalidNeedRM, iemOp_vpmaddwd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8662	/* 0xf6 */ iemOp_InvalidNeedRM, iemOp_vpsadbw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8663	/* 0xf7 */ iemOp_InvalidNeedRM, iemOp_vmaskmovdqu_Vdq_Udq, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8664	/* 0xf8 */ iemOp_InvalidNeedRM, iemOp_vpsubb_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8665	/* 0xf9 */ iemOp_InvalidNeedRM, iemOp_vpsubw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8666	/* 0xfa */ iemOp_InvalidNeedRM, iemOp_vpsubd_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8667	/* 0xfb */ iemOp_InvalidNeedRM, iemOp_vpsubq_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8668	/* 0xfc */ iemOp_InvalidNeedRM, iemOp_vpaddb_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8669	/* 0xfd */ iemOp_InvalidNeedRM, iemOp_vpaddw_Vx_Hx_Wx, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8670	/* 0xfe */ iemOp_InvalidNeedRM, iemOp_vpaddd_Vx_Hx_W, iemOp_InvalidNeedRM, iemOp_InvalidNeedRM,
8671	/* 0xff */ IEMOP_X4(iemOp_ud0),
8672	};
8673	AssertCompile(RT_ELEMENTS(g_apfnTwoByteMap) == 1024);
8674	/** @} */
8675
8676

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h@ 66334

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