PGMAllBth.h@ 55628

Last change on this file since 55628 was 55493, checked in by vboxsync, 10 years ago
PGM,++: Separated physical access handler callback function pointers from the access handler registrations to reduce footprint and simplify adding a couple of more callbacks.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 209.2 KB

Line
1	/* $Id: PGMAllBth.h 55493 2015-04-28 16:51:35Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2013 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29	#ifdef _MSC_VER
30	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31	* real/prot-guest+RC mode. */
32	# pragma warning(disable: 4505)
33	#endif
34
35	/*******************************************************************************
36	* Internal Functions *
37	*******************************************************************************/
38	RT_C_DECLS_BEGIN
39	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	# else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57	RT_C_DECLS_END
58
59
60	/*
61	* Filter out some illegal combinations of guest and shadow paging, so we can
62	* remove redundant checks inside functions.
63	*/
64	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65	# error "Invalid combination; PAE guest implies PAE shadow"
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
74	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
75	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76	#endif
77
78	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81	#endif
82
83	#ifndef IN_RING3
84
85	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86	/**
87	* Deal with a guest page fault.
88	*
89	* @returns Strict VBox status code.
90	* @retval VINF_EM_RAW_GUEST_TRAP
91	* @retval VINF_EM_RAW_EMULATE_INSTR
92	*
93	* @param pVCpu The current CPU.
94	* @param pGstWalk The guest page table walk result.
95	* @param uErr The error code.
96	*/
97	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98	{
99	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
100	/*
101	* Check for write conflicts with our hypervisor mapping.
102	*
103	* If the guest happens to access a non-present page, where our hypervisor
104	* is currently mapped, then we'll create a #PF storm in the guest.
105	*/
106	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
107	&& pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM))
108	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
109	{
110	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
111	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
112	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
113	return VINF_EM_RAW_EMULATE_INSTR;
114	}
115	# endif
116
117	/*
118	* Calc the error code for the guest trap.
119	*/
120	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
121	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
122	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
123	if (pGstWalk->Core.fBadPhysAddr)
124	{
125	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
126	Assert(!pGstWalk->Core.fNotPresent);
127	}
128	else if (!pGstWalk->Core.fNotPresent)
129	uNewErr \|= X86_TRAP_PF_P;
130	TRPMSetErrorCode(pVCpu, uNewErr);
131
132	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
133	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
134	return VINF_EM_RAW_GUEST_TRAP;
135	}
136	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
137
138
139	/**
140	* Deal with a guest page fault.
141	*
142	* The caller has taken the PGM lock.
143	*
144	* @returns Strict VBox status code.
145	*
146	* @param pVCpu The current CPU.
147	* @param uErr The error code.
148	* @param pRegFrame The register frame.
149	* @param pvFault The fault address.
150	* @param pPage The guest page at @a pvFault.
151	* @param pGstWalk The guest page table walk result.
152	* @param pfLockTaken PGM lock taken here or not (out). This is true
153	* when we're called.
154	*/
155	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
156	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
157	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
158	, PGSTPTWALK pGstWalk
159	# endif
160	)
161	{
162	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
164	#endif
165	PVM pVM = pVCpu->CTX_SUFF(pVM);
166	int rc;
167
168	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
169	{
170	/*
171	* Physical page access handler.
172	*/
173	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
174	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
175	# else
176	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
177	# endif
178	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
179	if (pCur)
180	{
181	PPGMPHYSHANDLERTYPEINT pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
182
183	# ifdef PGM_SYNC_N_PAGES
184	/*
185	* If the region is write protected and we got a page not present fault, then sync
186	* the pages. If the fault was caused by a read, then restart the instruction.
187	* In case of write access continue to the GC write handler.
188	*
189	* ASSUMES that there is only one handler per page or that they have similar write properties.
190	*/
191	if ( !(uErr & X86_TRAP_PF_P)
192	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
193	{
194	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
195	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
196	# else
197	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
198	# endif
199	if ( RT_FAILURE(rc)
200	\|\| !(uErr & X86_TRAP_PF_RW)
201	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
202	{
203	AssertRC(rc);
204	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
205	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
206	return rc;
207	}
208	}
209	# endif
210	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
211	/*
212	* If the access was not thru a #PF(RSVD\|...) resync the page.
213	*/
214	if ( !(uErr & X86_TRAP_PF_RSVD)
215	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
216	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
217	&& pGstWalk->Core.fEffectiveRW
218	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
219	# endif
220	)
221	{
222	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
223	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
224	# else
225	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
226	# endif
227	if ( RT_FAILURE(rc)
228	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
229	{
230	AssertRC(rc);
231	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
232	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
233	return rc;
234	}
235	}
236	# endif
237
238	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
239	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
240	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
241	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
242	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
243	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
244	else
245	{
246	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
247	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
248	}
249
250	if (pCurType->CTX_SUFF(pfnHandler))
251	{
252	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
253	void *pvUser = pCur->CTX_SUFF(pvUser);
254	# ifdef IN_RING0
255	PFNPGMR0PHYSHANDLER pfnHandler = pCurType->CTX_SUFF(pfnHandler);
256	# else
257	PFNPGMRCPHYSHANDLER pfnHandler = pCurType->CTX_SUFF(pfnHandler);
258	# endif
259
260	STAM_PROFILE_START(&pCur->Stat, h);
261	if (pCur->hType != pPool->hAccessHandlerType)
262	{
263	pgmUnlock(pVM);
264	*pfLockTaken = false;
265	}
266
267	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
268
269	# ifdef VBOX_WITH_STATISTICS
270	pgmLock(pVM);
271	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
272	if (pCur)
273	STAM_PROFILE_STOP(&pCur->Stat, h);
274	pgmUnlock(pVM);
275	# endif
276	}
277	else
278	rc = VINF_EM_RAW_EMULATE_INSTR;
279
280	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
281	return rc;
282	}
283	}
284	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
285	else
286	{
287	# ifdef PGM_SYNC_N_PAGES
288	/*
289	* If the region is write protected and we got a page not present fault, then sync
290	* the pages. If the fault was caused by a read, then restart the instruction.
291	* In case of write access continue to the GC write handler.
292	*/
293	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
294	&& !(uErr & X86_TRAP_PF_P))
295	{
296	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
297	if ( RT_FAILURE(rc)
298	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
299	\|\| !(uErr & X86_TRAP_PF_RW))
300	{
301	AssertRC(rc);
302	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
303	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
304	return rc;
305	}
306	}
307	# endif
308	/*
309	* Ok, it's an virtual page access handler.
310	*
311	* Since it's faster to search by address, we'll do that first
312	* and then retry by GCPhys if that fails.
313	*/
314	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
315	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
316	* out of sync, because the page was changed without us noticing it (not-present -> present
317	* without invlpg or mov cr3, xxx).
318	*/
319	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
320	if (pCur)
321	{
322	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
323	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
324	\|\| !(uErr & X86_TRAP_PF_P)
325	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
326	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
327	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
328
329	if ( pvFault - pCur->Core.Key < pCur->cb
330	&& ( uErr & X86_TRAP_PF_RW
331	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
332	{
333	# ifdef IN_RC
334	STAM_PROFILE_START(&pCur->Stat, h);
335	RTGCPTR GCPtrStart = pCur->Core.Key;
336	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
337	pgmUnlock(pVM);
338	*pfLockTaken = false;
339
340	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
341
342	# ifdef VBOX_WITH_STATISTICS
343	pgmLock(pVM);
344	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
345	if (pCur)
346	STAM_PROFILE_STOP(&pCur->Stat, h);
347	pgmUnlock(pVM);
348	# endif
349	# else
350	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
351	# endif
352	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
353	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
354	return rc;
355	}
356	/* Unhandled part of a monitored page */
357	Log(("Unhandled part of monitored page %RGv\n", pvFault));
358	}
359	else
360	{
361	/* Check by physical address. */
362	unsigned iPage;
363	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
364	Assert(RT_SUCCESS(rc) \|\| !pCur);
365	if ( pCur
366	&& ( uErr & X86_TRAP_PF_RW
367	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
368	{
369	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
370	# ifdef IN_RC
371	STAM_PROFILE_START(&pCur->Stat, h);
372	RTGCPTR GCPtrStart = pCur->Core.Key;
373	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
374	pgmUnlock(pVM);
375	*pfLockTaken = false;
376
377	RTGCPTR off = (iPage << PAGE_SHIFT)
378	+ (pvFault & PAGE_OFFSET_MASK)
379	- (GCPtrStart & PAGE_OFFSET_MASK);
380	Assert(off < pCur->cb);
381	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
382
383	# ifdef VBOX_WITH_STATISTICS
384	pgmLock(pVM);
385	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
386	if (pCur)
387	STAM_PROFILE_STOP(&pCur->Stat, h);
388	pgmUnlock(pVM);
389	# endif
390	# else
391	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
392	# endif
393	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
394	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
395	return rc;
396	}
397	}
398	}
399	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
400
401	/*
402	* There is a handled area of the page, but this fault doesn't belong to it.
403	* We must emulate the instruction.
404	*
405	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
406	* we first check if this was a page-not-present fault for a page with only
407	* write access handlers. Restart the instruction if it wasn't a write access.
408	*/
409	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
410
411	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
412	&& !(uErr & X86_TRAP_PF_P))
413	{
414	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
415	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
416	# else
417	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
418	# endif
419	if ( RT_FAILURE(rc)
420	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
421	\|\| !(uErr & X86_TRAP_PF_RW))
422	{
423	AssertRC(rc);
424	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
425	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
426	return rc;
427	}
428	}
429
430	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
431	* It's writing to an unhandled part of the LDT page several million times.
432	*/
433	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
434	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
435	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
436	return rc;
437	} /* if any kind of handler */
438
439
440	/**
441	* #PF Handler for raw-mode guest execution.
442	*
443	* @returns VBox status code (appropriate for trap handling and GC return).
444	*
445	* @param pVCpu Pointer to the VMCPU.
446	* @param uErr The trap error code.
447	* @param pRegFrame Trap register frame.
448	* @param pvFault The fault address.
449	* @param pfLockTaken PGM lock taken here or not (out)
450	*/
451	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
452	{
453	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
454
455	*pfLockTaken = false;
456
457	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
458	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
459	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
460	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
461	int rc;
462
463	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
464	/*
465	* Walk the guest page translation tables and check if it's a guest fault.
466	*/
467	GSTPTWALK GstWalk;
468	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
469	if (RT_FAILURE_NP(rc))
470	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
471
472	/* assert some GstWalk sanity. */
473	# if PGM_GST_TYPE == PGM_TYPE_AMD64
474	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
475	# endif
476	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
477	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
478	# endif
479	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
480	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
481	Assert(GstWalk.Core.fSucceeded);
482
483	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
484	{
485	if ( ( (uErr & X86_TRAP_PF_RW)
486	&& !GstWalk.Core.fEffectiveRW
487	&& ( (uErr & X86_TRAP_PF_US)
488	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
489	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
490	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
491	)
492	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
493	}
494
495	/*
496	* Set the accessed and dirty flags.
497	*/
498	# if PGM_GST_TYPE == PGM_TYPE_AMD64
499	GstWalk.Pml4e.u \|= X86_PML4E_A;
500	GstWalk.pPml4e->u \|= X86_PML4E_A;
501	GstWalk.Pdpe.u \|= X86_PDPE_A;
502	GstWalk.pPdpe->u \|= X86_PDPE_A;
503	# endif
504	if (GstWalk.Core.fBigPage)
505	{
506	Assert(GstWalk.Pde.b.u1Size);
507	if (uErr & X86_TRAP_PF_RW)
508	{
509	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
510	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
511	}
512	else
513	{
514	GstWalk.Pde.u \|= X86_PDE4M_A;
515	GstWalk.pPde->u \|= X86_PDE4M_A;
516	}
517	}
518	else
519	{
520	Assert(!GstWalk.Pde.b.u1Size);
521	GstWalk.Pde.u \|= X86_PDE_A;
522	GstWalk.pPde->u \|= X86_PDE_A;
523	if (uErr & X86_TRAP_PF_RW)
524	{
525	# ifdef VBOX_WITH_STATISTICS
526	if (!GstWalk.Pte.n.u1Dirty)
527	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
528	else
529	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
530	# endif
531	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
532	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
533	}
534	else
535	{
536	GstWalk.Pte.u \|= X86_PTE_A;
537	GstWalk.pPte->u \|= X86_PTE_A;
538	}
539	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
540	}
541	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
542	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
543	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
544	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
545	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
546
547	/* Take the big lock now. */
548	*pfLockTaken = true;
549	pgmLock(pVM);
550
551	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
552	/*
553	* If it is a reserved bit fault we know that it is an MMIO (access
554	* handler) related fault and can skip some 200 lines of code.
555	*/
556	if (uErr & X86_TRAP_PF_RSVD)
557	{
558	Assert(uErr & X86_TRAP_PF_P);
559	PPGMPAGE pPage;
560	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
561	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
562	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
563	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
564	pfLockTaken, &GstWalk));
565	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
566	# else
567	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
568	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
569	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
570	pfLockTaken));
571	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
572	# endif
573	AssertRC(rc);
574	PGM_INVL_PG(pVCpu, pvFault);
575	return rc; /* Restart with the corrected entry. */
576	}
577	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
578
579	/*
580	* Fetch the guest PDE, PDPE and PML4E.
581	*/
582	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
583	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
584	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
585
586	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
587	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
588	PX86PDPAE pPDDst;
589	# if PGM_GST_TYPE == PGM_TYPE_PAE
590	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
591	# else
592	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
593	# endif
594	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
595
596	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
597	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
598	PX86PDPAE pPDDst;
599	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
600	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
601	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
602	# else
603	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
604	# endif
605	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
606
607	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
608	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
609	PEPTPD pPDDst;
610	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
611	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
612	# endif
613	Assert(pPDDst);
614
615	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
616	/*
617	* Dirty page handling.
618	*
619	* If we successfully correct the write protection fault due to dirty bit
620	* tracking, then return immediately.
621	*/
622	if (uErr & X86_TRAP_PF_RW) /* write fault? */
623	{
624	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
625	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
626	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
627	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
628	{
629	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
630	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
631	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
632	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
633	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
634	return VINF_SUCCESS;
635	}
636	//AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - triggers with smp w7 guests.
637	//AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto.
638	}
639
640	# if 0 /* rarely useful; leave for debugging. */
641	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
642	# endif
643	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
644
645	/*
646	* A common case is the not-present error caused by lazy page table syncing.
647	*
648	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
649	* here so we can safely assume that the shadow PT is present when calling
650	* SyncPage later.
651	*
652	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
653	* of mapping conflict and defer to SyncCR3 in R3.
654	* (Again, we do NOT support access handlers for non-present guest pages.)
655	*
656	*/
657	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
658	Assert(GstWalk.Pde.n.u1Present);
659	# endif
660	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
661	&& !pPDDst->a[iPDDst].n.u1Present)
662	{
663	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
664	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
665	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
666	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
667	# else
668	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
669	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
670	# endif
671	if (RT_SUCCESS(rc))
672	return rc;
673	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
674	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
675	return VINF_PGM_SYNC_CR3;
676	}
677
678	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
679	/*
680	* Check if this address is within any of our mappings.
681	*
682	* This is very fast and it's gonna save us a bit of effort below and prevent
683	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
684	* (BTW, it's impossible to have physical access handlers in a mapping.)
685	*/
686	if (pgmMapAreMappingsEnabled(pVM))
687	{
688	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
689	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
690	{
691	if (pvFault < pMapping->GCPtr)
692	break;
693	if (pvFault - pMapping->GCPtr < pMapping->cb)
694	{
695	/*
696	* The first thing we check is if we've got an undetected conflict.
697	*/
698	if (pgmMapAreMappingsFloating(pVM))
699	{
700	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
701	while (iPT-- > 0)
702	if (GstWalk.pPde[iPT].n.u1Present)
703	{
704	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
705	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
706	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
707	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
708	return VINF_PGM_SYNC_CR3;
709	}
710	}
711
712	/*
713	* Check if the fault address is in a virtual page access handler range.
714	*/
715	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
716	if ( pCur
717	&& pvFault - pCur->Core.Key < pCur->cb
718	&& uErr & X86_TRAP_PF_RW)
719	{
720	# ifdef IN_RC
721	STAM_PROFILE_START(&pCur->Stat, h);
722	pgmUnlock(pVM);
723	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
724	pgmLock(pVM);
725	STAM_PROFILE_STOP(&pCur->Stat, h);
726	# else
727	AssertFailed();
728	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
729	# endif
730	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
731	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
732	return rc;
733	}
734
735	/*
736	* Pretend we're not here and let the guest handle the trap.
737	*/
738	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
739	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
740	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
741	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
742	return VINF_EM_RAW_GUEST_TRAP;
743	}
744	}
745	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
746	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
747
748	/*
749	* Check if this fault address is flagged for special treatment,
750	* which means we'll have to figure out the physical address and
751	* check flags associated with it.
752	*
753	* ASSUME that we can limit any special access handling to pages
754	* in page tables which the guest believes to be present.
755	*/
756	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
757	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
758	# else
759	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
760	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
761	PPGMPAGE pPage;
762	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
763	if (RT_FAILURE(rc))
764	{
765	/*
766	* When the guest accesses invalid physical memory (e.g. probing
767	* of RAM or accessing a remapped MMIO range), then we'll fall
768	* back to the recompiler to emulate the instruction.
769	*/
770	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
771	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
772	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
773	return VINF_EM_RAW_EMULATE_INSTR;
774	}
775
776	/*
777	* Any handlers for this page?
778	*/
779	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
780	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
781	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
782	&GstWalk));
783	# else
784	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
785	# endif
786
787	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
788
789	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
790	if (uErr & X86_TRAP_PF_P)
791	{
792	/*
793	* The page isn't marked, but it might still be monitored by a virtual page access handler.
794	* (ASSUMES no temporary disabling of virtual handlers.)
795	*/
796	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
797	* we should correct both the shadow page table and physical memory flags, and not only check for
798	* accesses within the handler region but for access to pages with virtual handlers. */
799	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
800	if (pCur)
801	{
802	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
803	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
804	\|\| !(uErr & X86_TRAP_PF_P)
805	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
806	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
807
808	if ( pvFault - pCur->Core.Key < pCur->cb
809	&& ( uErr & X86_TRAP_PF_RW
810	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
811	{
812	# ifdef IN_RC
813	STAM_PROFILE_START(&pCur->Stat, h);
814	pgmUnlock(pVM);
815	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
816	pgmLock(pVM);
817	STAM_PROFILE_STOP(&pCur->Stat, h);
818	# else
819	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
820	# endif
821	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
822	return rc;
823	}
824	}
825	}
826	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
827
828	/*
829	* We are here only if page is present in Guest page tables and
830	* trap is not handled by our handlers.
831	*
832	* Check it for page out-of-sync situation.
833	*/
834	if (!(uErr & X86_TRAP_PF_P))
835	{
836	/*
837	* Page is not present in our page tables. Try to sync it!
838	*/
839	if (uErr & X86_TRAP_PF_US)
840	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
841	else /* supervisor */
842	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
843
844	if (PGM_PAGE_IS_BALLOONED(pPage))
845	{
846	/* Emulate reads from ballooned pages as they are not present in
847	our shadow page tables. (Required for e.g. Solaris guests; soft
848	ecc, random nr generator.) */
849	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
850	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
851	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
852	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
853	return rc;
854	}
855
856	# if defined(LOG_ENABLED) && !defined(IN_RING0)
857	RTGCPHYS GCPhys2;
858	uint64_t fPageGst2;
859	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
860	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
861	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
862	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
863	# else
864	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
865	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
866	# endif
867	# endif /* LOG_ENABLED */
868
869	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
870	if ( !GstWalk.Core.fEffectiveUS
871	&& CSAMIsEnabled(pVM)
872	&& CPUMGetGuestCPL(pVCpu) == 0)
873	{
874	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
875	if ( pvFault == (RTGCPTR)pRegFrame->eip
876	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
877	# ifdef CSAM_DETECT_NEW_CODE_PAGES
878	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
879	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
880	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
881	)
882	{
883	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
884	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
885	if (rc != VINF_SUCCESS)
886	{
887	/*
888	* CSAM needs to perform a job in ring 3.
889	*
890	* Sync the page before going to the host context; otherwise we'll end up in a loop if
891	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
892	*/
893	LogFlow(("CSAM ring 3 job\n"));
894	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
895	AssertRC(rc2);
896
897	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
898	return rc;
899	}
900	}
901	# ifdef CSAM_DETECT_NEW_CODE_PAGES
902	else if ( uErr == X86_TRAP_PF_RW
903	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
904	&& pRegFrame->ecx < 0x10000)
905	{
906	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
907	* to detect loading of new code pages.
908	*/
909
910	/*
911	* Decode the instruction.
912	*/
913	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
914	uint32_t cbOp;
915	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
916
917	/* For now we'll restrict this to rep movsw/d instructions */
918	if ( rc == VINF_SUCCESS
919	&& pDis->pCurInstr->opcode == OP_MOVSWD
920	&& (pDis->prefix & DISPREFIX_REP))
921	{
922	CSAMMarkPossibleCodePage(pVM, pvFault);
923	}
924	}
925	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
926
927	/*
928	* Mark this page as safe.
929	*/
930	/** @todo not correct for pages that contain both code and data!! */
931	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
932	CSAMMarkPage(pVM, pvFault, true);
933	}
934	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
935	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
936	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
937	# else
938	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
939	# endif
940	if (RT_SUCCESS(rc))
941	{
942	/* The page was successfully synced, return to the guest. */
943	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
944	return VINF_SUCCESS;
945	}
946	}
947	else /* uErr & X86_TRAP_PF_P: */
948	{
949	/*
950	* Write protected pages are made writable when the guest makes the
951	* first write to it. This happens for pages that are shared, write
952	* monitored or not yet allocated.
953	*
954	* We may also end up here when CR0.WP=0 in the guest.
955	*
956	* Also, a side effect of not flushing global PDEs are out of sync
957	* pages due to physical monitored regions, that are no longer valid.
958	* Assume for now it only applies to the read/write flag.
959	*/
960	if (uErr & X86_TRAP_PF_RW)
961	{
962	/*
963	* Check if it is a read-only page.
964	*/
965	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
966	{
967	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
968	Assert(!PGM_PAGE_IS_ZERO(pPage));
969	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
970	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
971
972	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
973	if (rc != VINF_SUCCESS)
974	{
975	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
976	return rc;
977	}
978	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
979	return VINF_EM_NO_MEMORY;
980	}
981
982	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
983	/*
984	* Check to see if we need to emulate the instruction if CR0.WP=0.
985	*/
986	if ( !GstWalk.Core.fEffectiveRW
987	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
988	&& CPUMGetGuestCPL(pVCpu) < 3)
989	{
990	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
991
992	/*
993	* The Netware WP0+RO+US hack.
994	*
995	* Netware sometimes(/always?) runs with WP0. It has been observed doing
996	* excessive write accesses to pages which are mapped with US=1 and RW=0
997	* while WP=0. This causes a lot of exits and extremely slow execution.
998	* To avoid trapping and emulating every write here, we change the shadow
999	* page table entry to map it as US=0 and RW=1 until user mode tries to
1000	* access it again (see further below). We count these shadow page table
1001	* changes so we can avoid having to clear the page pool every time the WP
1002	* bit changes to 1 (see PGMCr0WpEnabled()).
1003	*/
1004	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
1005	if ( GstWalk.Core.fEffectiveUS
1006	&& !GstWalk.Core.fEffectiveRW
1007	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1008	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
1009	{
1010	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, GstWalk.Core.fBigPage));
1011	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, GstWalk.Core.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
1012	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
1013	{
1014	PGM_INVL_PG(pVCpu, pvFault);
1015	pVCpu->pgm.s.cNetwareWp0Hacks++;
1016	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsHack; });
1017	return rc;
1018	}
1019	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
1020	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
1021	}
1022	# endif
1023
1024	/* Interpret the access. */
1025	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
1026	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), GstWalk.Core.fBigPage, GstWalk.Core.fEffectiveUS));
1027	if (RT_SUCCESS(rc))
1028	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
1029	else
1030	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
1031	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
1032	return rc;
1033	}
1034	# endif
1035	/// @todo count the above case; else
1036	if (uErr & X86_TRAP_PF_US)
1037	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
1038	else /* supervisor */
1039	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1040
1041	/*
1042	* Sync the page.
1043	*
1044	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1045	* page is not present, which is not true in this case.
1046	*/
1047	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1048	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1049	# else
1050	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1051	# endif
1052	if (RT_SUCCESS(rc))
1053	{
1054	/*
1055	* Page was successfully synced, return to guest but invalidate
1056	* the TLB first as the page is very likely to be in it.
1057	*/
1058	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1059	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1060	# else
1061	PGM_INVL_PG(pVCpu, pvFault);
1062	# endif
1063	# ifdef VBOX_STRICT
1064	RTGCPHYS GCPhys2;
1065	uint64_t fPageGst;
1066	if (!pVM->pgm.s.fNestedPaging)
1067	{
1068	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1069	AssertMsg(RT_SUCCESS(rc) && ((fPageGst & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1070	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1071	}
1072	uint64_t fPageShw;
1073	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1074	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1075	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1076	# endif /* VBOX_STRICT */
1077	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1078	return VINF_SUCCESS;
1079	}
1080	}
1081	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1082	/*
1083	* Check for Netware WP0+RO+US hack from above and undo it when user
1084	* mode accesses the page again.
1085	*/
1086	else if ( GstWalk.Core.fEffectiveUS
1087	&& !GstWalk.Core.fEffectiveRW
1088	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1089	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
1090	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
1091	&& CPUMGetGuestCPL(pVCpu) == 3
1092	&& pVM->cCpus == 1
1093	)
1094	{
1095	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
1096	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1097	if (RT_SUCCESS(rc))
1098	{
1099	PGM_INVL_PG(pVCpu, pvFault);
1100	pVCpu->pgm.s.cNetwareWp0Hacks--;
1101	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsUnhack; });
1102	return VINF_SUCCESS;
1103	}
1104	}
1105	# endif /* PGM_WITH_PAGING */
1106
1107	/** @todo else: why are we here? */
1108
1109	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1110	/*
1111	* Check for VMM page flags vs. Guest page flags consistency.
1112	* Currently only for debug purposes.
1113	*/
1114	if (RT_SUCCESS(rc))
1115	{
1116	/* Get guest page flags. */
1117	uint64_t fPageGst;
1118	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1119	if (RT_SUCCESS(rc))
1120	{
1121	uint64_t fPageShw;
1122	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1123
1124	/*
1125	* Compare page flags.
1126	* Note: we have AVL, A, D bits desynced.
1127	*/
1128	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1129	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1130	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
1131	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1132	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1133	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
1134	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
1135	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1136	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1137	}
1138	else
1139	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1140	}
1141	else
1142	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1143	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1144	}
1145
1146
1147	/*
1148	* If we get here it is because something failed above, i.e. most like guru
1149	* meditiation time.
1150	*/
1151	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1152	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1153	return rc;
1154
1155	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1156	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1157	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1158	return VERR_PGM_NOT_USED_IN_MODE;
1159	# endif
1160	}
1161	#endif /* !IN_RING3 */
1162
1163
1164	/**
1165	* Emulation of the invlpg instruction.
1166	*
1167	*
1168	* @returns VBox status code.
1169	*
1170	* @param pVCpu Pointer to the VMCPU.
1171	* @param GCPtrPage Page to invalidate.
1172	*
1173	* @remark ASSUMES that the guest is updating before invalidating. This order
1174	* isn't required by the CPU, so this is speculative and could cause
1175	* trouble.
1176	* @remark No TLB shootdown is done on any other VCPU as we assume that
1177	* invlpg emulation is the only reason for calling this function.
1178	* (The guest has to shoot down TLB entries on other CPUs itself)
1179	* Currently true, but keep in mind!
1180	*
1181	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1182	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1183	*/
1184	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1185	{
1186	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1187	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1188	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1189	int rc;
1190	PVM pVM = pVCpu->CTX_SUFF(pVM);
1191	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1192
1193	PGM_LOCK_ASSERT_OWNER(pVM);
1194
1195	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1196
1197	/*
1198	* Get the shadow PD entry and skip out if this PD isn't present.
1199	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1200	*/
1201	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1202	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1203	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1204
1205	/* Fetch the pgm pool shadow descriptor. */
1206	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1207	Assert(pShwPde);
1208
1209	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1210	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1211	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1212
1213	/* If the shadow PDPE isn't present, then skip the invalidate. */
1214	if (!pPdptDst->a[iPdpt].n.u1Present)
1215	{
1216	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1217	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1218	PGM_INVL_PG(pVCpu, GCPtrPage);
1219	return VINF_SUCCESS;
1220	}
1221
1222	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1223	PPGMPOOLPAGE pShwPde = NULL;
1224	PX86PDPAE pPDDst;
1225
1226	/* Fetch the pgm pool shadow descriptor. */
1227	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1228	AssertRCSuccessReturn(rc, rc);
1229	Assert(pShwPde);
1230
1231	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1232	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1233
1234	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1235	/* PML4 */
1236	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1237	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1238	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1239	PX86PDPAE pPDDst;
1240	PX86PDPT pPdptDst;
1241	PX86PML4E pPml4eDst;
1242	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1243	if (rc != VINF_SUCCESS)
1244	{
1245	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1246	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1247	PGM_INVL_PG(pVCpu, GCPtrPage);
1248	return VINF_SUCCESS;
1249	}
1250	Assert(pPDDst);
1251
1252	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1253	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1254
1255	if (!pPdpeDst->n.u1Present)
1256	{
1257	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1258	PGM_INVL_PG(pVCpu, GCPtrPage);
1259	return VINF_SUCCESS;
1260	}
1261
1262	/* Fetch the pgm pool shadow descriptor. */
1263	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1264	Assert(pShwPde);
1265
1266	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1267
1268	const SHWPDE PdeDst = *pPdeDst;
1269	if (!PdeDst.n.u1Present)
1270	{
1271	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1272	PGM_INVL_PG(pVCpu, GCPtrPage);
1273	return VINF_SUCCESS;
1274	}
1275
1276	/*
1277	* Get the guest PD entry and calc big page.
1278	*/
1279	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1280	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1281	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1282	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1283	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1284	unsigned iPDSrc = 0;
1285	# if PGM_GST_TYPE == PGM_TYPE_PAE
1286	X86PDPE PdpeSrcIgn;
1287	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1288	# else /* AMD64 */
1289	PX86PML4E pPml4eSrcIgn;
1290	X86PDPE PdpeSrcIgn;
1291	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1292	# endif
1293	GSTPDE PdeSrc;
1294
1295	if (pPDSrc)
1296	PdeSrc = pPDSrc->a[iPDSrc];
1297	else
1298	PdeSrc.u = 0;
1299	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1300	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1301
1302	# ifdef IN_RING3
1303	/*
1304	* If a CR3 Sync is pending we may ignore the invalidate page operation
1305	* depending on the kind of sync and if it's a global page or not.
1306	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1307	*/
1308	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1309	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1310	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1311	&& fIsBigPage
1312	&& PdeSrc.b.u1Global
1313	)
1314	)
1315	# else
1316	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1317	# endif
1318	{
1319	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1320	return VINF_SUCCESS;
1321	}
1322	# endif /* IN_RING3 */
1323
1324	/*
1325	* Deal with the Guest PDE.
1326	*/
1327	rc = VINF_SUCCESS;
1328	if (PdeSrc.n.u1Present)
1329	{
1330	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1331	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1332	# ifndef PGM_WITHOUT_MAPPING
1333	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1334	{
1335	/*
1336	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1337	*/
1338	Assert(pgmMapAreMappingsEnabled(pVM));
1339	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1340	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1341	}
1342	else
1343	# endif /* !PGM_WITHOUT_MAPPING */
1344	if (!fIsBigPage)
1345	{
1346	/*
1347	* 4KB - page.
1348	*/
1349	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1350	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1351
1352	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1353	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1354	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1355	# endif
1356	if (pShwPage->GCPhys == GCPhys)
1357	{
1358	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1359	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1360
1361	PGSTPT pPTSrc;
1362	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1363	if (RT_SUCCESS(rc))
1364	{
1365	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1366	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1367	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1368	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1369	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1370	GCPtrPage, PteSrc.n.u1Present,
1371	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1372	PteSrc.n.u1User & PdeSrc.n.u1User,
1373	(uint64_t)PteSrc.u,
1374	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1375	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1376	}
1377	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1378	PGM_INVL_PG(pVCpu, GCPtrPage);
1379	}
1380	else
1381	{
1382	/*
1383	* The page table address changed.
1384	*/
1385	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1386	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1387	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1388	ASMAtomicWriteSize(pPdeDst, 0);
1389	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1390	PGM_INVL_VCPU_TLBS(pVCpu);
1391	}
1392	}
1393	else
1394	{
1395	/*
1396	* 2/4MB - page.
1397	*/
1398	/* Before freeing the page, check if anything really changed. */
1399	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1400	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1401	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1402	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1403	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1404	# endif
1405	if ( pShwPage->GCPhys == GCPhys
1406	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1407	{
1408	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1409	/** @todo This test is wrong as it cannot check the G bit!
1410	* FIXME */
1411	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1412	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1413	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1414	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1415	{
1416	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1417	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1418	return VINF_SUCCESS;
1419	}
1420	}
1421
1422	/*
1423	* Ok, the page table is present and it's been changed in the guest.
1424	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1425	* We could do this for some flushes in GC too, but we need an algorithm for
1426	* deciding which 4MB pages containing code likely to be executed very soon.
1427	*/
1428	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1429	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1430	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1431	ASMAtomicWriteSize(pPdeDst, 0);
1432	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1433	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1434	}
1435	}
1436	else
1437	{
1438	/*
1439	* Page directory is not present, mark shadow PDE not present.
1440	*/
1441	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1442	{
1443	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1444	ASMAtomicWriteSize(pPdeDst, 0);
1445	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1446	PGM_INVL_PG(pVCpu, GCPtrPage);
1447	}
1448	else
1449	{
1450	Assert(pgmMapAreMappingsEnabled(pVM));
1451	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1452	}
1453	}
1454	return rc;
1455
1456	#else /* guest real and protected mode */
1457	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1458	NOREF(pVCpu); NOREF(GCPtrPage);
1459	return VINF_SUCCESS;
1460	#endif
1461	}
1462
1463
1464	/**
1465	* Update the tracking of shadowed pages.
1466	*
1467	* @param pVCpu Pointer to the VMCPU.
1468	* @param pShwPage The shadow page.
1469	* @param HCPhys The physical page we is being dereferenced.
1470	* @param iPte Shadow PTE index
1471	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1472	*/
1473	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1474	RTGCPHYS GCPhysPage)
1475	{
1476	PVM pVM = pVCpu->CTX_SUFF(pVM);
1477
1478	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1479	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1480	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1481
1482	/* Use the hint we retrieved from the cached guest PT. */
1483	if (pShwPage->fDirty)
1484	{
1485	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1486
1487	Assert(pShwPage->cPresent);
1488	Assert(pPool->cPresent);
1489	pShwPage->cPresent--;
1490	pPool->cPresent--;
1491
1492	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1493	AssertRelease(pPhysPage);
1494	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1495	return;
1496	}
1497	# else
1498	NOREF(GCPhysPage);
1499	# endif
1500
1501	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1502	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1503
1504	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1505	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1506	* 2. write protect all shadowed pages. I.e. implement caching.
1507	*/
1508	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1509
1510	/*
1511	* Find the guest address.
1512	*/
1513	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1514	pRam;
1515	pRam = pRam->CTX_SUFF(pNext))
1516	{
1517	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1518	while (iPage-- > 0)
1519	{
1520	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1521	{
1522	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1523
1524	Assert(pShwPage->cPresent);
1525	Assert(pPool->cPresent);
1526	pShwPage->cPresent--;
1527	pPool->cPresent--;
1528
1529	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1530	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1531	return;
1532	}
1533	}
1534	}
1535
1536	for (;;)
1537	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1538	}
1539
1540
1541	/**
1542	* Update the tracking of shadowed pages.
1543	*
1544	* @param pVCpu Pointer to the VMCPU.
1545	* @param pShwPage The shadow page.
1546	* @param u16 The top 16-bit of the pPage->HCPhys.
1547	* @param pPage Pointer to the guest page. this will be modified.
1548	* @param iPTDst The index into the shadow table.
1549	*/
1550	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1551	{
1552	PVM pVM = pVCpu->CTX_SUFF(pVM);
1553
1554	/*
1555	* Just deal with the simple first time here.
1556	*/
1557	if (!u16)
1558	{
1559	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1560	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1561	/* Save the page table index. */
1562	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1563	}
1564	else
1565	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1566
1567	/* write back */
1568	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1569	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1570
1571	/* update statistics. */
1572	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1573	pShwPage->cPresent++;
1574	if (pShwPage->iFirstPresent > iPTDst)
1575	pShwPage->iFirstPresent = iPTDst;
1576	}
1577
1578
1579	/**
1580	* Modifies a shadow PTE to account for access handlers.
1581	*
1582	* @param pVM Pointer to the VM.
1583	* @param pPage The page in question.
1584	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1585	* A (accessed) bit so it can be emulated correctly.
1586	* @param pPteDst The shadow PTE (output). This is temporary storage and
1587	* does not need to be set atomically.
1588	*/
1589	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1590	{
1591	NOREF(pVM);
1592	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1593	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1594	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1595	{
1596	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1597	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1598	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1599	pPteDst->n.u1Present = 1;
1600	pPteDst->n.u1Execute = 1;
1601	pPteDst->n.u1IgnorePAT = 1;
1602	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1603	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1604	#else
1605	if (fPteSrc & X86_PTE_A)
1606	{
1607	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1608	SHW_PTE_SET_RO(*pPteDst);
1609	}
1610	else
1611	SHW_PTE_SET(*pPteDst, 0);
1612	#endif
1613	}
1614	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1615	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1616	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1617	&& ( BTH_IS_NP_ACTIVE(pVM)
1618	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1619	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1620	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1621	# endif
1622	)
1623	{
1624	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1625	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1626	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1627	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1628	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1629	pPteDst->n.u1Present = 0;
1630	pPteDst->n.u1Write = 1;
1631	pPteDst->n.u1Execute = 0;
1632	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1633	pPteDst->n.u3EMT = 7;
1634	# else
1635	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1636	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1637	# endif
1638	}
1639	# endif
1640	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1641	else
1642	{
1643	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1644	SHW_PTE_SET(*pPteDst, 0);
1645	}
1646	/** @todo count these kinds of entries. */
1647	}
1648
1649
1650	/**
1651	* Creates a 4K shadow page for a guest page.
1652	*
1653	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1654	* physical address. The PdeSrc argument only the flags are used. No page
1655	* structured will be mapped in this function.
1656	*
1657	* @param pVCpu Pointer to the VMCPU.
1658	* @param pPteDst Destination page table entry.
1659	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1660	* Can safely assume that only the flags are being used.
1661	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1662	* @param pShwPage Pointer to the shadow page.
1663	* @param iPTDst The index into the shadow table.
1664	*
1665	* @remark Not used for 2/4MB pages!
1666	*/
1667	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1668	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1669	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1670	#else
1671	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1672	#endif
1673	{
1674	PVM pVM = pVCpu->CTX_SUFF(pVM);
1675	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1676
1677	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1678	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1679	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1680
1681	if (pShwPage->fDirty)
1682	{
1683	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1684	PGSTPT pGstPT;
1685
1686	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1687	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1688	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1689	pGstPT->a[iPTDst].u = PteSrc.u;
1690	}
1691	#else
1692	Assert(!pShwPage->fDirty);
1693	#endif
1694
1695	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1696	if ( PteSrc.n.u1Present
1697	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1698	#endif
1699	{
1700	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1701	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1702	# endif
1703	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1704
1705	/*
1706	* Find the ram range.
1707	*/
1708	PPGMPAGE pPage;
1709	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1710	if (RT_SUCCESS(rc))
1711	{
1712	/* Ignore ballooned pages.
1713	Don't return errors or use a fatal assert here as part of a
1714	shadow sync range might included ballooned pages. */
1715	if (PGM_PAGE_IS_BALLOONED(pPage))
1716	{
1717	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1718	return;
1719	}
1720
1721	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1722	/* Make the page writable if necessary. */
1723	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1724	&& ( PGM_PAGE_IS_ZERO(pPage)
1725	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1726	\|\| ( PteSrc.n.u1Write
1727	# else
1728	\|\| ( 1
1729	# endif
1730	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1731	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1732	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1733	# endif
1734	# ifdef VBOX_WITH_PAGE_SHARING
1735	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1736	# endif
1737	)
1738	)
1739	)
1740	{
1741	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1742	AssertRC(rc);
1743	}
1744	#endif
1745
1746	/*
1747	* Make page table entry.
1748	*/
1749	SHWPTE PteDst;
1750	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1751	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1752	# else
1753	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1754	# endif
1755	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1756	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1757	else
1758	{
1759	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1760	/*
1761	* If the page or page directory entry is not marked accessed,
1762	* we mark the page not present.
1763	*/
1764	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1765	{
1766	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1767	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1768	SHW_PTE_SET(PteDst, 0);
1769	}
1770	/*
1771	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1772	* when the page is modified.
1773	*/
1774	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1775	{
1776	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1777	SHW_PTE_SET(PteDst,
1778	fGstShwPteFlags
1779	\| PGM_PAGE_GET_HCPHYS(pPage)
1780	\| PGM_PTFLAGS_TRACK_DIRTY);
1781	SHW_PTE_SET_RO(PteDst);
1782	}
1783	else
1784	#endif
1785	{
1786	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1787	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1788	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1789	PteDst.n.u1Present = 1;
1790	PteDst.n.u1Write = 1;
1791	PteDst.n.u1Execute = 1;
1792	PteDst.n.u1IgnorePAT = 1;
1793	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1794	/* PteDst.n.u1Size = 0 */
1795	#else
1796	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1797	#endif
1798	}
1799
1800	/*
1801	* Make sure only allocated pages are mapped writable.
1802	*/
1803	if ( SHW_PTE_IS_P_RW(PteDst)
1804	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1805	{
1806	/* Still applies to shared pages. */
1807	Assert(!PGM_PAGE_IS_ZERO(pPage));
1808	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1809	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1810	}
1811	}
1812
1813	/*
1814	* Keep user track up to date.
1815	*/
1816	if (SHW_PTE_IS_P(PteDst))
1817	{
1818	if (!SHW_PTE_IS_P(*pPteDst))
1819	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1820	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1821	{
1822	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1823	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1824	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1825	}
1826	}
1827	else if (SHW_PTE_IS_P(*pPteDst))
1828	{
1829	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1830	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1831	}
1832
1833	/*
1834	* Update statistics and commit the entry.
1835	*/
1836	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1837	if (!PteSrc.n.u1Global)
1838	pShwPage->fSeenNonGlobal = true;
1839	#endif
1840	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1841	return;
1842	}
1843
1844	/** @todo count these three different kinds. */
1845	Log2(("SyncPageWorker: invalid address in Pte\n"));
1846	}
1847	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1848	else if (!PteSrc.n.u1Present)
1849	Log2(("SyncPageWorker: page not present in Pte\n"));
1850	else
1851	Log2(("SyncPageWorker: invalid Pte\n"));
1852	#endif
1853
1854	/*
1855	* The page is not present or the PTE is bad. Replace the shadow PTE by
1856	* an empty entry, making sure to keep the user tracking up to date.
1857	*/
1858	if (SHW_PTE_IS_P(*pPteDst))
1859	{
1860	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1861	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1862	}
1863	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1864	}
1865
1866
1867	/**
1868	* Syncs a guest OS page.
1869	*
1870	* There are no conflicts at this point, neither is there any need for
1871	* page table allocations.
1872	*
1873	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1874	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1875	*
1876	* @returns VBox status code.
1877	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1878	* @param pVCpu Pointer to the VMCPU.
1879	* @param PdeSrc Page directory entry of the guest.
1880	* @param GCPtrPage Guest context page address.
1881	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1882	* @param uErr Fault error (X86_TRAP_PF_*).
1883	*/
1884	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1885	{
1886	PVM pVM = pVCpu->CTX_SUFF(pVM);
1887	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1888	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1889
1890	PGM_LOCK_ASSERT_OWNER(pVM);
1891
1892	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1893	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1894	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1895	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1896	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1897
1898	/*
1899	* Assert preconditions.
1900	*/
1901	Assert(PdeSrc.n.u1Present);
1902	Assert(cPages);
1903	# if 0 /* rarely useful; leave for debugging. */
1904	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1905	# endif
1906
1907	/*
1908	* Get the shadow PDE, find the shadow page table in the pool.
1909	*/
1910	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1911	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1912	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1913
1914	/* Fetch the pgm pool shadow descriptor. */
1915	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1916	Assert(pShwPde);
1917
1918	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1919	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1920	PPGMPOOLPAGE pShwPde = NULL;
1921	PX86PDPAE pPDDst;
1922
1923	/* Fetch the pgm pool shadow descriptor. */
1924	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1925	AssertRCSuccessReturn(rc2, rc2);
1926	Assert(pShwPde);
1927
1928	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1929	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1930
1931	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1932	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1933	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1934	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1935	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1936
1937	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1938	AssertRCSuccessReturn(rc2, rc2);
1939	Assert(pPDDst && pPdptDst);
1940	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1941	# endif
1942	SHWPDE PdeDst = *pPdeDst;
1943
1944	/*
1945	* - In the guest SMP case we could have blocked while another VCPU reused
1946	* this page table.
1947	* - With W7-64 we may also take this path when the A bit is cleared on
1948	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1949	* relevant TLB entries. If we're write monitoring any page mapped by
1950	* the modified entry, we may end up here with a "stale" TLB entry.
1951	*/
1952	if (!PdeDst.n.u1Present)
1953	{
1954	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1955	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1956	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1957	if (uErr & X86_TRAP_PF_P)
1958	PGM_INVL_PG(pVCpu, GCPtrPage);
1959	return VINF_SUCCESS; /* force the instruction to be executed again. */
1960	}
1961
1962	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1963	Assert(pShwPage);
1964
1965	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1966	/* Fetch the pgm pool shadow descriptor. */
1967	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1968	Assert(pShwPde);
1969	# endif
1970
1971	/*
1972	* Check that the page is present and that the shadow PDE isn't out of sync.
1973	*/
1974	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1975	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1976	RTGCPHYS GCPhys;
1977	if (!fBigPage)
1978	{
1979	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1980	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1981	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1982	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1983	# endif
1984	}
1985	else
1986	{
1987	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1988	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1989	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1990	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1991	# endif
1992	}
1993	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1994	if ( fPdeValid
1995	&& pShwPage->GCPhys == GCPhys
1996	&& PdeSrc.n.u1Present
1997	&& PdeSrc.n.u1User == PdeDst.n.u1User
1998	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1999	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2000	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
2001	# endif
2002	)
2003	{
2004	/*
2005	* Check that the PDE is marked accessed already.
2006	* Since we set the accessed bit before getting here on a #PF, this
2007	* check is only meant for dealing with non-#PF'ing paths.
2008	*/
2009	if (PdeSrc.n.u1Accessed)
2010	{
2011	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2012	if (!fBigPage)
2013	{
2014	/*
2015	* 4KB Page - Map the guest page table.
2016	*/
2017	PGSTPT pPTSrc;
2018	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2019	if (RT_SUCCESS(rc))
2020	{
2021	# ifdef PGM_SYNC_N_PAGES
2022	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2023	if ( cPages > 1
2024	&& !(uErr & X86_TRAP_PF_P)
2025	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2026	{
2027	/*
2028	* This code path is currently only taken when the caller is PGMTrap0eHandler
2029	* for non-present pages!
2030	*
2031	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2032	* deal with locality.
2033	*/
2034	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2035	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2036	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2037	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2038	# else
2039	const unsigned offPTSrc = 0;
2040	# endif
2041	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2042	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2043	iPTDst = 0;
2044	else
2045	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2046
2047	for (; iPTDst < iPTDstEnd; iPTDst++)
2048	{
2049	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2050
2051	if ( pPteSrc->n.u1Present
2052	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2053	{
2054	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
2055	NOREF(GCPtrCurPage);
2056	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2057	/*
2058	* Assuming kernel code will be marked as supervisor - and not as user level
2059	* and executed using a conforming code selector - And marked as readonly.
2060	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2061	*/
2062	PPGMPAGE pPage;
2063	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
2064	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
2065	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
2066	\|\| ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
2067	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2068	)
2069	# endif /* else: CSAM not active */
2070	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2071	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2072	GCPtrCurPage, pPteSrc->n.u1Present,
2073	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
2074	pPteSrc->n.u1User & PdeSrc.n.u1User,
2075	(uint64_t)pPteSrc->u,
2076	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2077	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2078	}
2079	}
2080	}
2081	else
2082	# endif /* PGM_SYNC_N_PAGES */
2083	{
2084	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2085	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2086	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2087	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2088	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2089	GCPtrPage, PteSrc.n.u1Present,
2090	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2091	PteSrc.n.u1User & PdeSrc.n.u1User,
2092	(uint64_t)PteSrc.u,
2093	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2094	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2095	}
2096	}
2097	else /* MMIO or invalid page: emulated in #PF handler. */
2098	{
2099	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2100	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2101	}
2102	}
2103	else
2104	{
2105	/*
2106	* 4/2MB page - lazy syncing shadow 4K pages.
2107	* (There are many causes of getting here, it's no longer only CSAM.)
2108	*/
2109	/* Calculate the GC physical address of this 4KB shadow page. */
2110	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2111	/* Find ram range. */
2112	PPGMPAGE pPage;
2113	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2114	if (RT_SUCCESS(rc))
2115	{
2116	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2117
2118	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2119	/* Try to make the page writable if necessary. */
2120	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2121	&& ( PGM_PAGE_IS_ZERO(pPage)
2122	\|\| ( PdeSrc.n.u1Write
2123	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2124	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2125	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2126	# endif
2127	# ifdef VBOX_WITH_PAGE_SHARING
2128	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2129	# endif
2130	)
2131	)
2132	)
2133	{
2134	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2135	AssertRC(rc);
2136	}
2137	# endif
2138
2139	/*
2140	* Make shadow PTE entry.
2141	*/
2142	SHWPTE PteDst;
2143	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2144	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2145	else
2146	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2147
2148	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2149	if ( SHW_PTE_IS_P(PteDst)
2150	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2151	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2152
2153	/* Make sure only allocated pages are mapped writable. */
2154	if ( SHW_PTE_IS_P_RW(PteDst)
2155	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2156	{
2157	/* Still applies to shared pages. */
2158	Assert(!PGM_PAGE_IS_ZERO(pPage));
2159	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2160	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2161	}
2162
2163	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2164
2165	/*
2166	* If the page is not flagged as dirty and is writable, then make it read-only
2167	* at PD level, so we can set the dirty bit when the page is modified.
2168	*
2169	* ASSUMES that page access handlers are implemented on page table entry level.
2170	* Thus we will first catch the dirty access and set PDE.D and restart. If
2171	* there is an access handler, we'll trap again and let it work on the problem.
2172	*/
2173	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2174	* As for invlpg, it simply frees the whole shadow PT.
2175	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2176	if ( !PdeSrc.b.u1Dirty
2177	&& PdeSrc.b.u1Write)
2178	{
2179	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2180	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2181	PdeDst.n.u1Write = 0;
2182	}
2183	else
2184	{
2185	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2186	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2187	}
2188	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2189	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2190	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2191	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2192	}
2193	else
2194	{
2195	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2196	/** @todo must wipe the shadow page table entry in this
2197	* case. */
2198	}
2199	}
2200	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2201	return VINF_SUCCESS;
2202	}
2203
2204	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2205	}
2206	else if (fPdeValid)
2207	{
2208	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2209	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2210	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2211	}
2212	else
2213	{
2214	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2215	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2216	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2217	}
2218
2219	/*
2220	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2221	* Yea, I'm lazy.
2222	*/
2223	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2224	ASMAtomicWriteSize(pPdeDst, 0);
2225
2226	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2227	PGM_INVL_VCPU_TLBS(pVCpu);
2228	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2229
2230
2231	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2232	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2233	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2234	&& !defined(IN_RC)
2235	NOREF(PdeSrc);
2236
2237	# ifdef PGM_SYNC_N_PAGES
2238	/*
2239	* Get the shadow PDE, find the shadow page table in the pool.
2240	*/
2241	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2242	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2243
2244	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2245	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2246
2247	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2248	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2249	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2250	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2251	X86PDEPAE PdeDst;
2252	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2253
2254	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2255	AssertRCSuccessReturn(rc, rc);
2256	Assert(pPDDst && pPdptDst);
2257	PdeDst = pPDDst->a[iPDDst];
2258	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2259	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2260	PEPTPD pPDDst;
2261	EPTPDE PdeDst;
2262
2263	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2264	if (rc != VINF_SUCCESS)
2265	{
2266	AssertRC(rc);
2267	return rc;
2268	}
2269	Assert(pPDDst);
2270	PdeDst = pPDDst->a[iPDDst];
2271	# endif
2272	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2273	if (!PdeDst.n.u1Present)
2274	{
2275	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2276	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2277	return VINF_SUCCESS; /* force the instruction to be executed again. */
2278	}
2279
2280	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2281	if (PdeDst.n.u1Size)
2282	{
2283	Assert(pVM->pgm.s.fNestedPaging);
2284	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2285	return VINF_SUCCESS;
2286	}
2287
2288	/* Mask away the page offset. */
2289	GCPtrPage &= ~((RTGCPTR)0xfff);
2290
2291	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2292	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2293
2294	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2295	if ( cPages > 1
2296	&& !(uErr & X86_TRAP_PF_P)
2297	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2298	{
2299	/*
2300	* This code path is currently only taken when the caller is PGMTrap0eHandler
2301	* for non-present pages!
2302	*
2303	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2304	* deal with locality.
2305	*/
2306	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2307	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2308	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2309	iPTDst = 0;
2310	else
2311	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2312	for (; iPTDst < iPTDstEnd; iPTDst++)
2313	{
2314	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2315	{
2316	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2317	\| (iPTDst << PAGE_SHIFT));
2318
2319	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2320	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2321	GCPtrCurPage,
2322	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2323	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2324
2325	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2326	break;
2327	}
2328	else
2329	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2330	}
2331	}
2332	else
2333	# endif /* PGM_SYNC_N_PAGES */
2334	{
2335	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2336	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2337	\| (iPTDst << PAGE_SHIFT));
2338
2339	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2340
2341	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2342	GCPtrPage,
2343	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2344	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2345	}
2346	return VINF_SUCCESS;
2347
2348	#else
2349	NOREF(PdeSrc);
2350	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2351	return VERR_PGM_NOT_USED_IN_MODE;
2352	#endif
2353	}
2354
2355
2356	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2357
2358	/**
2359	* CheckPageFault helper for returning a page fault indicating a non-present
2360	* (NP) entry in the page translation structures.
2361	*
2362	* @returns VINF_EM_RAW_GUEST_TRAP.
2363	* @param pVCpu Pointer to the VMCPU.
2364	* @param uErr The error code of the shadow fault. Corrections to
2365	* TRPM's copy will be made if necessary.
2366	* @param GCPtrPage For logging.
2367	* @param uPageFaultLevel For logging.
2368	*/
2369	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2370	{
2371	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2372	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2373	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2374	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2375	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2376
2377	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2378	return VINF_EM_RAW_GUEST_TRAP;
2379	}
2380
2381
2382	/**
2383	* CheckPageFault helper for returning a page fault indicating a reserved bit
2384	* (RSVD) error in the page translation structures.
2385	*
2386	* @returns VINF_EM_RAW_GUEST_TRAP.
2387	* @param pVCpu Pointer to the VMCPU.
2388	* @param uErr The error code of the shadow fault. Corrections to
2389	* TRPM's copy will be made if necessary.
2390	* @param GCPtrPage For logging.
2391	* @param uPageFaultLevel For logging.
2392	*/
2393	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2394	{
2395	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2396	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2397	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2398
2399	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2400	return VINF_EM_RAW_GUEST_TRAP;
2401	}
2402
2403
2404	/**
2405	* CheckPageFault helper for returning a page protection fault (P).
2406	*
2407	* @returns VINF_EM_RAW_GUEST_TRAP.
2408	* @param pVCpu Pointer to the VMCPU.
2409	* @param uErr The error code of the shadow fault. Corrections to
2410	* TRPM's copy will be made if necessary.
2411	* @param GCPtrPage For logging.
2412	* @param uPageFaultLevel For logging.
2413	*/
2414	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2415	{
2416	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2417	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2418	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2419	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2420
2421	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2422	return VINF_EM_RAW_GUEST_TRAP;
2423	}
2424
2425
2426	/**
2427	* Handle dirty bit tracking faults.
2428	*
2429	* @returns VBox status code.
2430	* @param pVCpu Pointer to the VMCPU.
2431	* @param uErr Page fault error code.
2432	* @param pPdeSrc Guest page directory entry.
2433	* @param pPdeDst Shadow page directory entry.
2434	* @param GCPtrPage Guest context page address.
2435	*/
2436	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2437	RTGCPTR GCPtrPage)
2438	{
2439	PVM pVM = pVCpu->CTX_SUFF(pVM);
2440	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2441	NOREF(uErr);
2442
2443	PGM_LOCK_ASSERT_OWNER(pVM);
2444
2445	/*
2446	* Handle big page.
2447	*/
2448	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2449	{
2450	if ( pPdeDst->n.u1Present
2451	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2452	{
2453	SHWPDE PdeDst = *pPdeDst;
2454
2455	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2456	Assert(pPdeSrc->b.u1Write);
2457
2458	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2459	* fault again and take this path to only invalidate the entry (see below).
2460	*/
2461	PdeDst.n.u1Write = 1;
2462	PdeDst.n.u1Accessed = 1;
2463	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2464	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2465	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2466	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2467	}
2468
2469	# ifdef IN_RING0
2470	/* Check for stale TLB entry; only applies to the SMP guest case. */
2471	if ( pVM->cCpus > 1
2472	&& pPdeDst->n.u1Write
2473	&& pPdeDst->n.u1Accessed)
2474	{
2475	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2476	if (pShwPage)
2477	{
2478	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2479	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2480	if (SHW_PTE_IS_P_RW(*pPteDst))
2481	{
2482	/* Stale TLB entry. */
2483	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2484	PGM_INVL_PG(pVCpu, GCPtrPage);
2485	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2486	}
2487	}
2488	}
2489	# endif /* IN_RING0 */
2490	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2491	}
2492
2493	/*
2494	* Map the guest page table.
2495	*/
2496	PGSTPT pPTSrc;
2497	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2498	if (RT_FAILURE(rc))
2499	{
2500	AssertRC(rc);
2501	return rc;
2502	}
2503
2504	if (pPdeDst->n.u1Present)
2505	{
2506	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2507	const GSTPTE PteSrc = *pPteSrc;
2508
2509	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2510	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2511	* Our individual shadow handlers will provide more information and force a fatal exit.
2512	*/
2513	if ( !HMIsEnabled(pVM)
2514	&& MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2515	{
2516	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2517	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2518	}
2519	#endif
2520	/*
2521	* Map shadow page table.
2522	*/
2523	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2524	if (pShwPage)
2525	{
2526	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2527	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2528	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2529	{
2530	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2531	{
2532	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2533	SHWPTE PteDst = *pPteDst;
2534
2535	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2536	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2537
2538	Assert(PteSrc.n.u1Write);
2539
2540	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2541	* entry will not harm; write access will simply fault again and
2542	* take this path to only invalidate the entry.
2543	*/
2544	if (RT_LIKELY(pPage))
2545	{
2546	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2547	{
2548	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2549	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2550	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2551	SHW_PTE_SET_RO(PteDst);
2552	}
2553	else
2554	{
2555	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2556	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2557	{
2558	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2559	AssertRC(rc);
2560	}
2561	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2562	SHW_PTE_SET_RW(PteDst);
2563	else
2564	{
2565	/* Still applies to shared pages. */
2566	Assert(!PGM_PAGE_IS_ZERO(pPage));
2567	SHW_PTE_SET_RO(PteDst);
2568	}
2569	}
2570	}
2571	else
2572	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2573
2574	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2575	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2576	PGM_INVL_PG(pVCpu, GCPtrPage);
2577	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2578	}
2579
2580	# ifdef IN_RING0
2581	/* Check for stale TLB entry; only applies to the SMP guest case. */
2582	if ( pVM->cCpus > 1
2583	&& SHW_PTE_IS_RW(*pPteDst)
2584	&& SHW_PTE_IS_A(*pPteDst))
2585	{
2586	/* Stale TLB entry. */
2587	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2588	PGM_INVL_PG(pVCpu, GCPtrPage);
2589	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2590	}
2591	# endif
2592	}
2593	}
2594	else
2595	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2596	}
2597
2598	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2599	}
2600
2601	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2602
2603
2604	/**
2605	* Sync a shadow page table.
2606	*
2607	* The shadow page table is not present in the shadow PDE.
2608	*
2609	* Handles mapping conflicts.
2610	*
2611	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2612	* conflict), and Trap0eHandler.
2613	*
2614	* A precondition for this method is that the shadow PDE is not present. The
2615	* caller must take the PGM lock before checking this and continue to hold it
2616	* when calling this method.
2617	*
2618	* @returns VBox status code.
2619	* @param pVCpu Pointer to the VMCPU.
2620	* @param iPD Page directory index.
2621	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2622	* Assume this is a temporary mapping.
2623	* @param GCPtrPage GC Pointer of the page that caused the fault
2624	*/
2625	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2626	{
2627	PVM pVM = pVCpu->CTX_SUFF(pVM);
2628	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2629
2630	#if 0 /* rarely useful; leave for debugging. */
2631	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2632	#endif
2633	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2634
2635	PGM_LOCK_ASSERT_OWNER(pVM);
2636
2637	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2638	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2639	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2640	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2641	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2642
2643	int rc = VINF_SUCCESS;
2644
2645	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2646
2647	/*
2648	* Some input validation first.
2649	*/
2650	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2651
2652	/*
2653	* Get the relevant shadow PDE entry.
2654	*/
2655	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2656	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2657	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2658
2659	/* Fetch the pgm pool shadow descriptor. */
2660	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2661	Assert(pShwPde);
2662
2663	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2664	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2665	PPGMPOOLPAGE pShwPde = NULL;
2666	PX86PDPAE pPDDst;
2667	PSHWPDE pPdeDst;
2668
2669	/* Fetch the pgm pool shadow descriptor. */
2670	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2671	AssertRCSuccessReturn(rc, rc);
2672	Assert(pShwPde);
2673
2674	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2675	pPdeDst = &pPDDst->a[iPDDst];
2676
2677	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2678	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2679	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2680	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2681	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2682	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2683	AssertRCSuccessReturn(rc, rc);
2684	Assert(pPDDst);
2685	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2686	# endif
2687	SHWPDE PdeDst = *pPdeDst;
2688
2689	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2690	/* Fetch the pgm pool shadow descriptor. */
2691	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2692	Assert(pShwPde);
2693	# endif
2694
2695	# ifndef PGM_WITHOUT_MAPPINGS
2696	/*
2697	* Check for conflicts.
2698	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2699	* R3: Simply resolve the conflict.
2700	*/
2701	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2702	{
2703	Assert(pgmMapAreMappingsEnabled(pVM));
2704	# ifndef IN_RING3
2705	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2706	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2707	return VERR_ADDRESS_CONFLICT;
2708
2709	# else /* IN_RING3 */
2710	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2711	Assert(pMapping);
2712	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2713	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2714	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2715	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2716	# else
2717	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2718	# endif
2719	if (RT_FAILURE(rc))
2720	{
2721	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2722	return rc;
2723	}
2724	PdeDst = *pPdeDst;
2725	# endif /* IN_RING3 */
2726	}
2727	# endif /* !PGM_WITHOUT_MAPPINGS */
2728	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2729
2730	/*
2731	* Sync the page directory entry.
2732	*/
2733	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2734	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2735	if ( PdeSrc.n.u1Present
2736	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2737	{
2738	/*
2739	* Allocate & map the page table.
2740	*/
2741	PSHWPT pPTDst;
2742	PPGMPOOLPAGE pShwPage;
2743	RTGCPHYS GCPhys;
2744	if (fPageTable)
2745	{
2746	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2747	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2748	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2749	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2750	# endif
2751	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2752	pShwPde->idx, iPDDst, false /fLockPage/,
2753	&pShwPage);
2754	}
2755	else
2756	{
2757	PGMPOOLACCESS enmAccess;
2758	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2759	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2760	# else
2761	const bool fNoExecute = false;
2762	# endif
2763
2764	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2765	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2766	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2767	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2768	# endif
2769	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2770	if (PdeSrc.n.u1User)
2771	{
2772	if (PdeSrc.n.u1Write)
2773	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2774	else
2775	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2776	}
2777	else
2778	{
2779	if (PdeSrc.n.u1Write)
2780	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2781	else
2782	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2783	}
2784	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2785	pShwPde->idx, iPDDst, false /fLockPage/,
2786	&pShwPage);
2787	}
2788	if (rc == VINF_SUCCESS)
2789	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2790	else if (rc == VINF_PGM_CACHED_PAGE)
2791	{
2792	/*
2793	* The PT was cached, just hook it up.
2794	*/
2795	if (fPageTable)
2796	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2797	else
2798	{
2799	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2800	/* (see explanation and assumptions further down.) */
2801	if ( !PdeSrc.b.u1Dirty
2802	&& PdeSrc.b.u1Write)
2803	{
2804	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2805	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2806	PdeDst.b.u1Write = 0;
2807	}
2808	}
2809	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2810	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2811	return VINF_SUCCESS;
2812	}
2813	else if (rc == VERR_PGM_POOL_FLUSHED)
2814	{
2815	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2816	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2817	return VINF_PGM_SYNC_CR3;
2818	}
2819	else
2820	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2821	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2822	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2823	* irrelevant at this point. */
2824	PdeDst.u &= X86_PDE_AVL_MASK;
2825	PdeDst.u \|= pShwPage->Core.Key;
2826
2827	/*
2828	* Page directory has been accessed (this is a fault situation, remember).
2829	*/
2830	/** @todo
2831	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2832	* fault situation. What's more, the Trap0eHandler has already set the
2833	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2834	* might need setting the accessed flag.
2835	*
2836	* The best idea is to leave this change to the caller and add an
2837	* assertion that it's set already. */
2838	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2839	if (fPageTable)
2840	{
2841	/*
2842	* Page table - 4KB.
2843	*
2844	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2845	*/
2846	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2847	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2848	PGSTPT pPTSrc;
2849	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2850	if (RT_SUCCESS(rc))
2851	{
2852	/*
2853	* Start by syncing the page directory entry so CSAM's TLB trick works.
2854	*/
2855	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2856	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2857	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2858	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2859
2860	/*
2861	* Directory/page user or supervisor privilege: (same goes for read/write)
2862	*
2863	* Directory Page Combined
2864	* U/S U/S U/S
2865	* 0 0 0
2866	* 0 1 0
2867	* 1 0 0
2868	* 1 1 1
2869	*
2870	* Simple AND operation. Table listed for completeness.
2871	*
2872	*/
2873	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2874	# ifdef PGM_SYNC_N_PAGES
2875	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2876	unsigned iPTDst = iPTBase;
2877	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2878	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2879	iPTDst = 0;
2880	else
2881	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2882	# else /* !PGM_SYNC_N_PAGES */
2883	unsigned iPTDst = 0;
2884	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2885	# endif /* !PGM_SYNC_N_PAGES */
2886	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2887	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2888	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2889	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2890	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2891	# else
2892	const unsigned offPTSrc = 0;
2893	# endif
2894	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2895	{
2896	const unsigned iPTSrc = iPTDst + offPTSrc;
2897	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2898
2899	if (PteSrc.n.u1Present)
2900	{
2901	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2902	/*
2903	* Assuming kernel code will be marked as supervisor - and not as user level
2904	* and executed using a conforming code selector - And marked as readonly.
2905	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2906	*/
2907	PPGMPAGE pPage;
2908	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2909	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2910	\|\| ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2911	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2912	)
2913	# endif
2914	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2915	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2916	GCPtrCur,
2917	PteSrc.n.u1Present,
2918	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2919	PteSrc.n.u1User & PdeSrc.n.u1User,
2920	(uint64_t)PteSrc.u,
2921	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2922	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2923	}
2924	/* else: the page table was cleared by the pool */
2925	} /* for PTEs */
2926	}
2927	}
2928	else
2929	{
2930	/*
2931	* Big page - 2/4MB.
2932	*
2933	* We'll walk the ram range list in parallel and optimize lookups.
2934	* We will only sync one shadow page table at a time.
2935	*/
2936	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2937
2938	/**
2939	* @todo It might be more efficient to sync only a part of the 4MB
2940	* page (similar to what we do for 4KB PDs).
2941	*/
2942
2943	/*
2944	* Start by syncing the page directory entry.
2945	*/
2946	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2947	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2948
2949	/*
2950	* If the page is not flagged as dirty and is writable, then make it read-only
2951	* at PD level, so we can set the dirty bit when the page is modified.
2952	*
2953	* ASSUMES that page access handlers are implemented on page table entry level.
2954	* Thus we will first catch the dirty access and set PDE.D and restart. If
2955	* there is an access handler, we'll trap again and let it work on the problem.
2956	*/
2957	/** @todo move the above stuff to a section in the PGM documentation. */
2958	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2959	if ( !PdeSrc.b.u1Dirty
2960	&& PdeSrc.b.u1Write)
2961	{
2962	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2963	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2964	PdeDst.b.u1Write = 0;
2965	}
2966	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2967	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2968
2969	/*
2970	* Fill the shadow page table.
2971	*/
2972	/* Get address and flags from the source PDE. */
2973	SHWPTE PteDstBase;
2974	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2975
2976	/* Loop thru the entries in the shadow PT. */
2977	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2978	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2979	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2980	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2981	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2982	unsigned iPTDst = 0;
2983	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2984	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2985	{
2986	if (pRam && GCPhys >= pRam->GCPhys)
2987	{
2988	# ifndef PGM_WITH_A20
2989	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2990	# endif
2991	do
2992	{
2993	/* Make shadow PTE. */
2994	# ifdef PGM_WITH_A20
2995	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2996	# else
2997	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2998	# endif
2999	SHWPTE PteDst;
3000
3001	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3002	/* Try to make the page writable if necessary. */
3003	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3004	&& ( PGM_PAGE_IS_ZERO(pPage)
3005	\|\| ( SHW_PTE_IS_RW(PteDstBase)
3006	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3007	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3008	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3009	# endif
3010	# ifdef VBOX_WITH_PAGE_SHARING
3011	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3012	# endif
3013	&& !PGM_PAGE_IS_BALLOONED(pPage))
3014	)
3015	)
3016	{
3017	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3018	AssertRCReturn(rc, rc);
3019	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
3020	break;
3021	}
3022	# endif
3023
3024	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3025	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
3026	else if (PGM_PAGE_IS_BALLOONED(pPage))
3027	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3028	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3029	/*
3030	* Assuming kernel code will be marked as supervisor and not as user level and executed
3031	* using a conforming code selector. Don't check for readonly, as that implies the whole
3032	* 4MB can be code or readonly data. Linux enables write access for its large pages.
3033	*/
3034	else if ( !PdeSrc.n.u1User
3035	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
3036	SHW_PTE_SET(PteDst, 0);
3037	# endif
3038	else
3039	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
3040
3041	/* Only map writable pages writable. */
3042	if ( SHW_PTE_IS_P_RW(PteDst)
3043	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3044	{
3045	/* Still applies to shared pages. */
3046	Assert(!PGM_PAGE_IS_ZERO(pPage));
3047	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3048	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3049	}
3050
3051	if (SHW_PTE_IS_P(PteDst))
3052	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3053
3054	/* commit it (not atomic, new table) */
3055	pPTDst->a[iPTDst] = PteDst;
3056	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3057	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3058	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3059
3060	/* advance */
3061	GCPhys += PAGE_SIZE;
3062	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3063	# ifndef PGM_WITH_A20
3064	iHCPage++;
3065	# endif
3066	iPTDst++;
3067	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3068	&& GCPhys <= pRam->GCPhysLast);
3069
3070	/* Advance ram range list. */
3071	while (pRam && GCPhys > pRam->GCPhysLast)
3072	pRam = pRam->CTX_SUFF(pNext);
3073	}
3074	else if (pRam)
3075	{
3076	Log(("Invalid pages at %RGp\n", GCPhys));
3077	do
3078	{
3079	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3080	GCPhys += PAGE_SIZE;
3081	iPTDst++;
3082	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3083	&& GCPhys < pRam->GCPhys);
3084	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3085	}
3086	else
3087	{
3088	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3089	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3090	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3091	}
3092	} /* while more PTEs */
3093	} /* 4KB / 4MB */
3094	}
3095	else
3096	AssertRelease(!PdeDst.n.u1Present);
3097
3098	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3099	if (RT_FAILURE(rc))
3100	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3101	return rc;
3102
3103	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3104	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3105	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3106	&& !defined(IN_RC)
3107	NOREF(iPDSrc); NOREF(pPDSrc);
3108
3109	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3110
3111	/*
3112	* Validate input a little bit.
3113	*/
3114	int rc = VINF_SUCCESS;
3115	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3116	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3117	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3118
3119	/* Fetch the pgm pool shadow descriptor. */
3120	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3121	Assert(pShwPde);
3122
3123	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3124	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3125	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3126	PX86PDPAE pPDDst;
3127	PSHWPDE pPdeDst;
3128
3129	/* Fetch the pgm pool shadow descriptor. */
3130	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3131	AssertRCSuccessReturn(rc, rc);
3132	Assert(pShwPde);
3133
3134	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3135	pPdeDst = &pPDDst->a[iPDDst];
3136
3137	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3138	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3139	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3140	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3141	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3142	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3143	AssertRCSuccessReturn(rc, rc);
3144	Assert(pPDDst);
3145	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3146
3147	/* Fetch the pgm pool shadow descriptor. */
3148	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3149	Assert(pShwPde);
3150
3151	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3152	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3153	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3154	PEPTPD pPDDst;
3155	PEPTPDPT pPdptDst;
3156
3157	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3158	if (rc != VINF_SUCCESS)
3159	{
3160	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3161	AssertRC(rc);
3162	return rc;
3163	}
3164	Assert(pPDDst);
3165	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3166
3167	/* Fetch the pgm pool shadow descriptor. */
3168	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3169	Assert(pShwPde);
3170	# endif
3171	SHWPDE PdeDst = *pPdeDst;
3172
3173	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3174	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3175
3176	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3177	if (BTH_IS_NP_ACTIVE(pVM))
3178	{
3179	/* Check if we allocated a big page before for this 2 MB range. */
3180	PPGMPAGE pPage;
3181	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3182	if (RT_SUCCESS(rc))
3183	{
3184	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3185	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3186	{
3187	if (PGM_A20_IS_ENABLED(pVCpu))
3188	{
3189	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3190	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3191	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3192	}
3193	else
3194	{
3195	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3196	pVM->pgm.s.cLargePagesDisabled++;
3197	}
3198	}
3199	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3200	&& PGM_A20_IS_ENABLED(pVCpu))
3201	{
3202	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3203	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3204	if (RT_SUCCESS(rc))
3205	{
3206	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3207	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3208	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3209	}
3210	}
3211	else if ( PGMIsUsingLargePages(pVM)
3212	&& PGM_A20_IS_ENABLED(pVCpu))
3213	{
3214	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3215	if (RT_SUCCESS(rc))
3216	{
3217	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3218	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3219	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3220	}
3221	else
3222	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3223	}
3224
3225	if (HCPhys != NIL_RTHCPHYS)
3226	{
3227	PdeDst.u &= X86_PDE_AVL_MASK;
3228	PdeDst.u \|= HCPhys;
3229	PdeDst.n.u1Present = 1;
3230	PdeDst.n.u1Write = 1;
3231	PdeDst.b.u1Size = 1;
3232	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3233	PdeDst.n.u1Execute = 1;
3234	PdeDst.b.u1IgnorePAT = 1;
3235	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3236	# else
3237	PdeDst.n.u1User = 1;
3238	# endif
3239	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3240
3241	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3242	/* Add a reference to the first page only. */
3243	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3244
3245	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3246	return VINF_SUCCESS;
3247	}
3248	}
3249	}
3250	# endif /* HC_ARCH_BITS == 64 */
3251
3252	/*
3253	* Allocate & map the page table.
3254	*/
3255	PSHWPT pPTDst;
3256	PPGMPOOLPAGE pShwPage;
3257	RTGCPHYS GCPhys;
3258
3259	/* Virtual address = physical address */
3260	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3261	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3262	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3263	&pShwPage);
3264	if ( rc == VINF_SUCCESS
3265	\|\| rc == VINF_PGM_CACHED_PAGE)
3266	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3267	else
3268	{
3269	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3270	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3271	}
3272
3273	if (rc == VINF_SUCCESS)
3274	{
3275	/* New page table; fully set it up. */
3276	Assert(pPTDst);
3277
3278	/* Mask away the page offset. */
3279	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3280
3281	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3282	{
3283	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3284	\| (iPTDst << PAGE_SHIFT));
3285
3286	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3287	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3288	GCPtrCurPage,
3289	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3290	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3291
3292	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3293	break;
3294	}
3295	}
3296	else
3297	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3298
3299	/* Save the new PDE. */
3300	PdeDst.u &= X86_PDE_AVL_MASK;
3301	PdeDst.u \|= pShwPage->Core.Key;
3302	PdeDst.n.u1Present = 1;
3303	PdeDst.n.u1Write = 1;
3304	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3305	PdeDst.n.u1Execute = 1;
3306	# else
3307	PdeDst.n.u1User = 1;
3308	PdeDst.n.u1Accessed = 1;
3309	# endif
3310	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3311
3312	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3313	if (RT_FAILURE(rc))
3314	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3315	return rc;
3316
3317	#else
3318	NOREF(iPDSrc); NOREF(pPDSrc);
3319	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3320	return VERR_PGM_NOT_USED_IN_MODE;
3321	#endif
3322	}
3323
3324
3325
3326	/**
3327	* Prefetch a page/set of pages.
3328	*
3329	* Typically used to sync commonly used pages before entering raw mode
3330	* after a CR3 reload.
3331	*
3332	* @returns VBox status code.
3333	* @param pVCpu Pointer to the VMCPU.
3334	* @param GCPtrPage Page to invalidate.
3335	*/
3336	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3337	{
3338	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3339	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3340	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3341	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3342	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3343	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3344	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3345
3346	/*
3347	* Check that all Guest levels thru the PDE are present, getting the
3348	* PD and PDE in the processes.
3349	*/
3350	int rc = VINF_SUCCESS;
3351	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3352	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3353	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3354	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3355	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3356	unsigned iPDSrc;
3357	X86PDPE PdpeSrc;
3358	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3359	if (!pPDSrc)
3360	return VINF_SUCCESS; /* not present */
3361	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3362	unsigned iPDSrc;
3363	PX86PML4E pPml4eSrc;
3364	X86PDPE PdpeSrc;
3365	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3366	if (!pPDSrc)
3367	return VINF_SUCCESS; /* not present */
3368	# endif
3369	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3370	# else
3371	PGSTPD pPDSrc = NULL;
3372	const unsigned iPDSrc = 0;
3373	GSTPDE PdeSrc;
3374
3375	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3376	PdeSrc.n.u1Present = 1;
3377	PdeSrc.n.u1Write = 1;
3378	PdeSrc.n.u1Accessed = 1;
3379	PdeSrc.n.u1User = 1;
3380	# endif
3381
3382	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3383	{
3384	PVM pVM = pVCpu->CTX_SUFF(pVM);
3385	pgmLock(pVM);
3386
3387	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3388	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3389	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3390	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3391	PX86PDPAE pPDDst;
3392	X86PDEPAE PdeDst;
3393	# if PGM_GST_TYPE != PGM_TYPE_PAE
3394	X86PDPE PdpeSrc;
3395
3396	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3397	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3398	# endif
3399	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3400	if (rc != VINF_SUCCESS)
3401	{
3402	pgmUnlock(pVM);
3403	AssertRC(rc);
3404	return rc;
3405	}
3406	Assert(pPDDst);
3407	PdeDst = pPDDst->a[iPDDst];
3408
3409	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3410	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3411	PX86PDPAE pPDDst;
3412	X86PDEPAE PdeDst;
3413
3414	# if PGM_GST_TYPE == PGM_TYPE_PROT
3415	/* AMD-V nested paging */
3416	X86PML4E Pml4eSrc;
3417	X86PDPE PdpeSrc;
3418	PX86PML4E pPml4eSrc = &Pml4eSrc;
3419
3420	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3421	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3422	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3423	# endif
3424
3425	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3426	if (rc != VINF_SUCCESS)
3427	{
3428	pgmUnlock(pVM);
3429	AssertRC(rc);
3430	return rc;
3431	}
3432	Assert(pPDDst);
3433	PdeDst = pPDDst->a[iPDDst];
3434	# endif
3435	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3436	{
3437	if (!PdeDst.n.u1Present)
3438	{
3439	/** @todo r=bird: This guy will set the A bit on the PDE,
3440	* probably harmless. */
3441	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3442	}
3443	else
3444	{
3445	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3446	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3447	* makes no sense to prefetch more than one page.
3448	*/
3449	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3450	if (RT_SUCCESS(rc))
3451	rc = VINF_SUCCESS;
3452	}
3453	}
3454	pgmUnlock(pVM);
3455	}
3456	return rc;
3457
3458	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3459	NOREF(pVCpu); NOREF(GCPtrPage);
3460	return VINF_SUCCESS; /* ignore */
3461	#else
3462	AssertCompile(0);
3463	#endif
3464	}
3465
3466
3467
3468
3469	/**
3470	* Syncs a page during a PGMVerifyAccess() call.
3471	*
3472	* @returns VBox status code (informational included).
3473	* @param pVCpu Pointer to the VMCPU.
3474	* @param GCPtrPage The address of the page to sync.
3475	* @param fPage The effective guest page flags.
3476	* @param uErr The trap error code.
3477	* @remarks This will normally never be called on invalid guest page
3478	* translation entries.
3479	*/
3480	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3481	{
3482	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3483
3484	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3485
3486	Assert(!pVM->pgm.s.fNestedPaging);
3487	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3488	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3489	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3490	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3491	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3492	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3493	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3494
3495	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3496	if (!(fPage & X86_PTE_US))
3497	{
3498	/*
3499	* Mark this page as safe.
3500	*/
3501	/** @todo not correct for pages that contain both code and data!! */
3502	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3503	CSAMMarkPage(pVM, GCPtrPage, true);
3504	}
3505	# endif
3506
3507	/*
3508	* Get guest PD and index.
3509	*/
3510	/** @todo Performance: We've done all this a jiffy ago in the
3511	* PGMGstGetPage call. */
3512	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3513	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3514	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3515	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3516
3517	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3518	unsigned iPDSrc = 0;
3519	X86PDPE PdpeSrc;
3520	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3521	if (RT_UNLIKELY(!pPDSrc))
3522	{
3523	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3524	return VINF_EM_RAW_GUEST_TRAP;
3525	}
3526
3527	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3528	unsigned iPDSrc = 0; /* shut up gcc */
3529	PX86PML4E pPml4eSrc = NULL; /* ditto */
3530	X86PDPE PdpeSrc;
3531	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3532	if (RT_UNLIKELY(!pPDSrc))
3533	{
3534	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3535	return VINF_EM_RAW_GUEST_TRAP;
3536	}
3537	# endif
3538
3539	# else /* !PGM_WITH_PAGING */
3540	PGSTPD pPDSrc = NULL;
3541	const unsigned iPDSrc = 0;
3542	# endif /* !PGM_WITH_PAGING */
3543	int rc = VINF_SUCCESS;
3544
3545	pgmLock(pVM);
3546
3547	/*
3548	* First check if the shadow pd is present.
3549	*/
3550	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3551	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3552
3553	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3554	PX86PDEPAE pPdeDst;
3555	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3556	PX86PDPAE pPDDst;
3557	# if PGM_GST_TYPE != PGM_TYPE_PAE
3558	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3559	X86PDPE PdpeSrc;
3560	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3561	# endif
3562	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3563	if (rc != VINF_SUCCESS)
3564	{
3565	pgmUnlock(pVM);
3566	AssertRC(rc);
3567	return rc;
3568	}
3569	Assert(pPDDst);
3570	pPdeDst = &pPDDst->a[iPDDst];
3571
3572	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3573	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3574	PX86PDPAE pPDDst;
3575	PX86PDEPAE pPdeDst;
3576
3577	# if PGM_GST_TYPE == PGM_TYPE_PROT
3578	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3579	X86PML4E Pml4eSrc;
3580	X86PDPE PdpeSrc;
3581	PX86PML4E pPml4eSrc = &Pml4eSrc;
3582	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3583	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3584	# endif
3585
3586	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3587	if (rc != VINF_SUCCESS)
3588	{
3589	pgmUnlock(pVM);
3590	AssertRC(rc);
3591	return rc;
3592	}
3593	Assert(pPDDst);
3594	pPdeDst = &pPDDst->a[iPDDst];
3595	# endif
3596
3597	if (!pPdeDst->n.u1Present)
3598	{
3599	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3600	if (rc != VINF_SUCCESS)
3601	{
3602	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3603	pgmUnlock(pVM);
3604	AssertRC(rc);
3605	return rc;
3606	}
3607	}
3608
3609	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3610	/* Check for dirty bit fault */
3611	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3612	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3613	Log(("PGMVerifyAccess: success (dirty)\n"));
3614	else
3615	# endif
3616	{
3617	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3618	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3619	# else
3620	GSTPDE PdeSrc;
3621	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3622	PdeSrc.n.u1Present = 1;
3623	PdeSrc.n.u1Write = 1;
3624	PdeSrc.n.u1Accessed = 1;
3625	PdeSrc.n.u1User = 1;
3626	# endif
3627
3628	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3629	if (uErr & X86_TRAP_PF_US)
3630	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3631	else /* supervisor */
3632	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3633
3634	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3635	if (RT_SUCCESS(rc))
3636	{
3637	/* Page was successfully synced */
3638	Log2(("PGMVerifyAccess: success (sync)\n"));
3639	rc = VINF_SUCCESS;
3640	}
3641	else
3642	{
3643	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3644	rc = VINF_EM_RAW_GUEST_TRAP;
3645	}
3646	}
3647	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3648	pgmUnlock(pVM);
3649	return rc;
3650
3651	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3652
3653	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3654	return VERR_PGM_NOT_USED_IN_MODE;
3655	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3656	}
3657
3658
3659	/**
3660	* Syncs the paging hierarchy starting at CR3.
3661	*
3662	* @returns VBox status code, no specials.
3663	* @param pVCpu Pointer to the VMCPU.
3664	* @param cr0 Guest context CR0 register.
3665	* @param cr3 Guest context CR3 register. Not subjected to the A20
3666	* mask.
3667	* @param cr4 Guest context CR4 register.
3668	* @param fGlobal Including global page directories or not
3669	*/
3670	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3671	{
3672	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3673	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3674
3675	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3676
3677	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3678
3679	pgmLock(pVM);
3680
3681	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3682	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3683	if (pPool->cDirtyPages)
3684	pgmPoolResetDirtyPages(pVM);
3685	# endif
3686
3687	/*
3688	* Update page access handlers.
3689	* The virtual are always flushed, while the physical are only on demand.
3690	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3691	* have to look into that later because it will have a bad influence on the performance.
3692	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3693	* bird: Yes, but that won't work for aliases.
3694	*/
3695	/** @todo this MUST go away. See @bugref{1557}. */
3696	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3697	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3698	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3699	pgmUnlock(pVM);
3700	#endif /* !NESTED && !EPT */
3701
3702	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3703	/*
3704	* Nested / EPT - almost no work.
3705	*/
3706	Assert(!pgmMapAreMappingsEnabled(pVM));
3707	return VINF_SUCCESS;
3708
3709	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3710	/*
3711	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3712	* out the shadow parts when the guest modifies its tables.
3713	*/
3714	Assert(!pgmMapAreMappingsEnabled(pVM));
3715	return VINF_SUCCESS;
3716
3717	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3718
3719	# ifndef PGM_WITHOUT_MAPPINGS
3720	/*
3721	* Check for and resolve conflicts with our guest mappings if they
3722	* are enabled and not fixed.
3723	*/
3724	if (pgmMapAreMappingsFloating(pVM))
3725	{
3726	int rc = pgmMapResolveConflicts(pVM);
3727	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3728	if (rc == VINF_PGM_SYNC_CR3)
3729	{
3730	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3731	return VINF_PGM_SYNC_CR3;
3732	}
3733	}
3734	# else
3735	Assert(!pgmMapAreMappingsEnabled(pVM));
3736	# endif
3737	return VINF_SUCCESS;
3738	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3739	}
3740
3741
3742
3743
3744	#ifdef VBOX_STRICT
3745	# ifdef IN_RC
3746	# undef AssertMsgFailed
3747	# define AssertMsgFailed Log
3748	# endif
3749
3750	/**
3751	* Checks that the shadow page table is in sync with the guest one.
3752	*
3753	* @returns The number of errors.
3754	* @param pVM The virtual machine.
3755	* @param pVCpu Pointer to the VMCPU.
3756	* @param cr3 Guest context CR3 register.
3757	* @param cr4 Guest context CR4 register.
3758	* @param GCPtr Where to start. Defaults to 0.
3759	* @param cb How much to check. Defaults to everything.
3760	*/
3761	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3762	{
3763	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3764	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3765	return 0;
3766	#else
3767	unsigned cErrors = 0;
3768	PVM pVM = pVCpu->CTX_SUFF(pVM);
3769	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3770
3771	# if PGM_GST_TYPE == PGM_TYPE_PAE
3772	/** @todo currently broken; crashes below somewhere */
3773	AssertFailed();
3774	# endif
3775
3776	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3777	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3778	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3779
3780	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3781	PPGMCPU pPGM = &pVCpu->pgm.s;
3782	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3783	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3784	# ifndef IN_RING0
3785	RTHCPHYS HCPhys; /* general usage. */
3786	# endif
3787	int rc;
3788
3789	/*
3790	* Check that the Guest CR3 and all its mappings are correct.
3791	*/
3792	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3793	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3794	false);
3795	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3796	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3797	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3798	# else
3799	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3800	# endif
3801	AssertRCReturn(rc, 1);
3802	HCPhys = NIL_RTHCPHYS;
3803	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3804	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3805	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3806	pgmGstGet32bitPDPtr(pVCpu);
3807	RTGCPHYS GCPhys;
3808	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3809	AssertRCReturn(rc, 1);
3810	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3811	# endif
3812	# endif /* !IN_RING0 */
3813
3814	/*
3815	* Get and check the Shadow CR3.
3816	*/
3817	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3818	unsigned cPDEs = X86_PG_ENTRIES;
3819	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3820	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3821	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3822	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3823	# else
3824	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3825	# endif
3826	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3827	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3828	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3829	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3830	# endif
3831	if (cb != ~(RTGCPTR)0)
3832	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3833
3834	/** @todo call the other two PGMAssert() functions. /
3835
3836	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3837	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3838
3839	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3840	{
3841	PPGMPOOLPAGE pShwPdpt = NULL;
3842	PX86PML4E pPml4eSrc;
3843	PX86PML4E pPml4eDst;
3844	RTGCPHYS GCPhysPdptSrc;
3845
3846	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3847	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3848
3849	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3850	if (!pPml4eDst->n.u1Present)
3851	{
3852	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3853	continue;
3854	}
3855
3856	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3857	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3858
3859	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3860	{
3861	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3862	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3863	cErrors++;
3864	continue;
3865	}
3866
3867	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3868	{
3869	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3870	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3871	cErrors++;
3872	continue;
3873	}
3874
3875	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3876	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3877	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3878	{
3879	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3880	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3881	cErrors++;
3882	continue;
3883	}
3884	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3885	{
3886	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3887
3888	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3889	/*
3890	* Check the PDPTEs too.
3891	*/
3892	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3893
3894	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3895	{
3896	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3897	PPGMPOOLPAGE pShwPde = NULL;
3898	PX86PDPE pPdpeDst;
3899	RTGCPHYS GCPhysPdeSrc;
3900	X86PDPE PdpeSrc;
3901	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3902	# if PGM_GST_TYPE == PGM_TYPE_PAE
3903	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3904	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3905	# else
3906	PX86PML4E pPml4eSrcIgn;
3907	PX86PDPT pPdptDst;
3908	PX86PDPAE pPDDst;
3909	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3910
3911	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3912	if (rc != VINF_SUCCESS)
3913	{
3914	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3915	GCPtr += 512 * _2M;
3916	continue; /* next PDPTE */
3917	}
3918	Assert(pPDDst);
3919	# endif
3920	Assert(iPDSrc == 0);
3921
3922	pPdpeDst = &pPdptDst->a[iPdpt];
3923
3924	if (!pPdpeDst->n.u1Present)
3925	{
3926	GCPtr += 512 * _2M;
3927	continue; /* next PDPTE */
3928	}
3929
3930	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3931	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3932
3933	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3934	{
3935	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3936	GCPtr += 512 * _2M;
3937	cErrors++;
3938	continue;
3939	}
3940
3941	if (GCPhysPdeSrc != pShwPde->GCPhys)
3942	{
3943	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3944	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3945	# else
3946	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3947	# endif
3948	GCPtr += 512 * _2M;
3949	cErrors++;
3950	continue;
3951	}
3952
3953	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3954	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3955	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3956	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3957	{
3958	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3959	GCPtr += 512 * _2M;
3960	cErrors++;
3961	continue;
3962	}
3963	# endif
3964
3965	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3966	{
3967	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3968	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3969	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3970	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3971	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3972	# endif
3973	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3974	/*
3975	* Iterate the shadow page directory.
3976	*/
3977	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3978	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3979
3980	for (;
3981	iPDDst < cPDEs;
3982	iPDDst++, GCPtr += cIncrement)
3983	{
3984	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3985	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3986	# else
3987	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3988	# endif
3989	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3990	{
3991	Assert(pgmMapAreMappingsEnabled(pVM));
3992	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3993	{
3994	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3995	cErrors++;
3996	continue;
3997	}
3998	}
3999	else if ( (PdeDst.u & X86_PDE_P)
4000	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
4001	)
4002	{
4003	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4004	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4005	if (!pPoolPage)
4006	{
4007	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4008	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4009	cErrors++;
4010	continue;
4011	}
4012	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4013
4014	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4015	{
4016	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4017	GCPtr, (uint64_t)PdeDst.u));
4018	cErrors++;
4019	}
4020
4021	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4022	{
4023	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4024	GCPtr, (uint64_t)PdeDst.u));
4025	cErrors++;
4026	}
4027
4028	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4029	if (!PdeSrc.n.u1Present)
4030	{
4031	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4032	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4033	cErrors++;
4034	continue;
4035	}
4036
4037	if ( !PdeSrc.b.u1Size
4038	\|\| !fBigPagesSupported)
4039	{
4040	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4041	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4042	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
4043	# endif
4044	}
4045	else
4046	{
4047	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4048	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4049	{
4050	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4051	GCPtr, (uint64_t)PdeSrc.u));
4052	cErrors++;
4053	continue;
4054	}
4055	# endif
4056	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4057	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4058	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4059	# endif
4060	}
4061
4062	if ( pPoolPage->enmKind
4063	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4064	{
4065	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4066	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4067	cErrors++;
4068	}
4069
4070	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4071	if (!pPhysPage)
4072	{
4073	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4074	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4075	cErrors++;
4076	continue;
4077	}
4078
4079	if (GCPhysGst != pPoolPage->GCPhys)
4080	{
4081	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4082	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4083	cErrors++;
4084	continue;
4085	}
4086
4087	if ( !PdeSrc.b.u1Size
4088	\|\| !fBigPagesSupported)
4089	{
4090	/*
4091	* Page Table.
4092	*/
4093	const GSTPT *pPTSrc;
4094	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
4095	&pPTSrc);
4096	if (RT_FAILURE(rc))
4097	{
4098	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4099	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4100	cErrors++;
4101	continue;
4102	}
4103	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4104	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4105	{
4106	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4107	// (This problem will go away when/if we shadow multiple CR3s.)
4108	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4109	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4110	cErrors++;
4111	continue;
4112	}
4113	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4114	{
4115	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4116	GCPtr, (uint64_t)PdeDst.u));
4117	cErrors++;
4118	continue;
4119	}
4120
4121	/* iterate the page table. */
4122	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4123	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4124	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4125	# else
4126	const unsigned offPTSrc = 0;
4127	# endif
4128	for (unsigned iPT = 0, off = 0;
4129	iPT < RT_ELEMENTS(pPTDst->a);
4130	iPT++, off += PAGE_SIZE)
4131	{
4132	const SHWPTE PteDst = pPTDst->a[iPT];
4133
4134	/* skip not-present and dirty tracked entries. */
4135	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4136	continue;
4137	Assert(SHW_PTE_IS_P(PteDst));
4138
4139	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4140	if (!PteSrc.n.u1Present)
4141	{
4142	# ifdef IN_RING3
4143	PGMAssertHandlerAndFlagsInSync(pVM);
4144	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4145	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4146	0, 0, UINT64_MAX, 99, NULL);
4147	# endif
4148	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4149	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4150	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4151	cErrors++;
4152	continue;
4153	}
4154
4155	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4156	# if 1 /** @todo sync accessed bit properly... */
4157	fIgnoreFlags \|= X86_PTE_A;
4158	# endif
4159
4160	/* match the physical addresses */
4161	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4162	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4163
4164	# ifdef IN_RING3
4165	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4166	if (RT_FAILURE(rc))
4167	{
4168	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4169	{
4170	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4171	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4172	cErrors++;
4173	continue;
4174	}
4175	}
4176	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4177	{
4178	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4179	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4180	cErrors++;
4181	continue;
4182	}
4183	# endif
4184
4185	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4186	if (!pPhysPage)
4187	{
4188	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4189	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4190	{
4191	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4192	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4193	cErrors++;
4194	continue;
4195	}
4196	# endif
4197	if (SHW_PTE_IS_RW(PteDst))
4198	{
4199	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4200	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4201	cErrors++;
4202	}
4203	fIgnoreFlags \|= X86_PTE_RW;
4204	}
4205	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4206	{
4207	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4208	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4209	cErrors++;
4210	continue;
4211	}
4212
4213	/* flags */
4214	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4215	{
4216	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4217	{
4218	if (SHW_PTE_IS_RW(PteDst))
4219	{
4220	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4221	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4222	cErrors++;
4223	continue;
4224	}
4225	fIgnoreFlags \|= X86_PTE_RW;
4226	}
4227	else
4228	{
4229	if ( SHW_PTE_IS_P(PteDst)
4230	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4231	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4232	# endif
4233	)
4234	{
4235	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4236	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4237	cErrors++;
4238	continue;
4239	}
4240	fIgnoreFlags \|= X86_PTE_P;
4241	}
4242	}
4243	else
4244	{
4245	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4246	{
4247	if (SHW_PTE_IS_RW(PteDst))
4248	{
4249	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4250	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4251	cErrors++;
4252	continue;
4253	}
4254	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4255	{
4256	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4257	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4258	cErrors++;
4259	continue;
4260	}
4261	if (SHW_PTE_IS_D(PteDst))
4262	{
4263	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4264	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4265	cErrors++;
4266	}
4267	# if 0 /** @todo sync access bit properly... */
4268	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4269	{
4270	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4271	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4272	cErrors++;
4273	}
4274	fIgnoreFlags \|= X86_PTE_RW;
4275	# else
4276	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4277	# endif
4278	}
4279	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4280	{
4281	/* access bit emulation (not implemented). */
4282	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4283	{
4284	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4285	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4286	cErrors++;
4287	continue;
4288	}
4289	if (!SHW_PTE_IS_A(PteDst))
4290	{
4291	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4292	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4293	cErrors++;
4294	}
4295	fIgnoreFlags \|= X86_PTE_P;
4296	}
4297	# ifdef DEBUG_sandervl
4298	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4299	# endif
4300	}
4301
4302	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4303	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4304	)
4305	{
4306	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4307	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4308	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4309	cErrors++;
4310	continue;
4311	}
4312	} /* foreach PTE */
4313	}
4314	else
4315	{
4316	/*
4317	* Big Page.
4318	*/
4319	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4320	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4321	{
4322	if (PdeDst.n.u1Write)
4323	{
4324	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4325	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4326	cErrors++;
4327	continue;
4328	}
4329	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4330	{
4331	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4332	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4333	cErrors++;
4334	continue;
4335	}
4336	# if 0 /** @todo sync access bit properly... */
4337	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4338	{
4339	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4340	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4341	cErrors++;
4342	}
4343	fIgnoreFlags \|= X86_PTE_RW;
4344	# else
4345	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4346	# endif
4347	}
4348	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4349	{
4350	/* access bit emulation (not implemented). */
4351	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4352	{
4353	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4354	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4355	cErrors++;
4356	continue;
4357	}
4358	if (!PdeDst.n.u1Accessed)
4359	{
4360	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4361	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4362	cErrors++;
4363	}
4364	fIgnoreFlags \|= X86_PTE_P;
4365	}
4366
4367	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4368	{
4369	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4370	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4371	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4372	cErrors++;
4373	}
4374
4375	/* iterate the page table. */
4376	for (unsigned iPT = 0, off = 0;
4377	iPT < RT_ELEMENTS(pPTDst->a);
4378	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4379	{
4380	const SHWPTE PteDst = pPTDst->a[iPT];
4381
4382	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4383	{
4384	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4385	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4386	cErrors++;
4387	}
4388
4389	/* skip not-present entries. */
4390	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4391	continue;
4392
4393	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4394
4395	/* match the physical addresses */
4396	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4397
4398	# ifdef IN_RING3
4399	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4400	if (RT_FAILURE(rc))
4401	{
4402	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4403	{
4404	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4405	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4406	cErrors++;
4407	}
4408	}
4409	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4410	{
4411	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4412	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4413	cErrors++;
4414	continue;
4415	}
4416	# endif
4417	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4418	if (!pPhysPage)
4419	{
4420	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4421	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4422	{
4423	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4424	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4425	cErrors++;
4426	continue;
4427	}
4428	# endif
4429	if (SHW_PTE_IS_RW(PteDst))
4430	{
4431	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4432	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4433	cErrors++;
4434	}
4435	fIgnoreFlags \|= X86_PTE_RW;
4436	}
4437	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4438	{
4439	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4440	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4441	cErrors++;
4442	continue;
4443	}
4444
4445	/* flags */
4446	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4447	{
4448	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4449	{
4450	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4451	{
4452	if (SHW_PTE_IS_RW(PteDst))
4453	{
4454	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4455	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4456	cErrors++;
4457	continue;
4458	}
4459	fIgnoreFlags \|= X86_PTE_RW;
4460	}
4461	}
4462	else
4463	{
4464	if ( SHW_PTE_IS_P(PteDst)
4465	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4466	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4467	# endif
4468	)
4469	{
4470	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4471	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4472	cErrors++;
4473	continue;
4474	}
4475	fIgnoreFlags \|= X86_PTE_P;
4476	}
4477	}
4478
4479	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4480	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4481	)
4482	{
4483	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4484	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4485	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4486	cErrors++;
4487	continue;
4488	}
4489	} /* for each PTE */
4490	}
4491	}
4492	/* not present */
4493
4494	} /* for each PDE */
4495
4496	} /* for each PDPTE */
4497
4498	} /* for each PML4E */
4499
4500	# ifdef DEBUG
4501	if (cErrors)
4502	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4503	# endif
4504	# endif /* GST is in {32BIT, PAE, AMD64} */
4505	return cErrors;
4506	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4507	}
4508	#endif /* VBOX_STRICT */
4509
4510
4511	/**
4512	* Sets up the CR3 for shadow paging
4513	*
4514	* @returns Strict VBox status code.
4515	* @retval VINF_SUCCESS.
4516	*
4517	* @param pVCpu Pointer to the VMCPU.
4518	* @param GCPhysCR3 The physical address in the CR3 register. (A20
4519	* mask already applied.)
4520	*/
4521	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4522	{
4523	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4524
4525	/* Update guest paging info. */
4526	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4527	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4528	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4529
4530	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4531	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4532
4533	/*
4534	* Map the page CR3 points at.
4535	*/
4536	RTHCPTR HCPtrGuestCR3;
4537	RTHCPHYS HCPhysGuestCR3;
4538	pgmLock(pVM);
4539	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4540	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4541	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4542	/** @todo this needs some reworking wrt. locking? */
4543	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4544	HCPtrGuestCR3 = NIL_RTHCPTR;
4545	int rc = VINF_SUCCESS;
4546	# else
4547	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4548	# endif
4549	pgmUnlock(pVM);
4550	if (RT_SUCCESS(rc))
4551	{
4552	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4553	if (RT_SUCCESS(rc))
4554	{
4555	# ifdef IN_RC
4556	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4557	# endif
4558	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4559	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4560	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4561	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4562	# endif
4563	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4564
4565	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4566	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4567	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4568	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4569	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4570	# endif
4571	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4572	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4573
4574	/*
4575	* Map the 4 PDs too.
4576	*/
4577	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4578	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4579	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4580	{
4581	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4582	if (pGuestPDPT->a[i].n.u1Present)
4583	{
4584	RTHCPTR HCPtr;
4585	RTHCPHYS HCPhys;
4586	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4587	pgmLock(pVM);
4588	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4589	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4590	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4591	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4592	HCPtr = NIL_RTHCPTR;
4593	int rc2 = VINF_SUCCESS;
4594	# else
4595	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4596	# endif
4597	pgmUnlock(pVM);
4598	if (RT_SUCCESS(rc2))
4599	{
4600	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4601	AssertRCReturn(rc, rc);
4602
4603	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4604	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4605	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4606	# endif
4607	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4608	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4609	# ifdef IN_RC
4610	PGM_INVL_PG(pVCpu, GCPtr);
4611	# endif
4612	continue;
4613	}
4614	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4615	}
4616
4617	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4618	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4619	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4620	# endif
4621	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4622	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4623	# ifdef IN_RC
4624	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4625	# endif
4626	}
4627
4628	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4629	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4630	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4631	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4632	# endif
4633	# endif
4634	}
4635	else
4636	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4637	}
4638	else
4639	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4640
4641	#else /* prot/real stub */
4642	int rc = VINF_SUCCESS;
4643	#endif
4644
4645	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4646	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4647	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4648	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4649	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4650	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4651
4652	Assert(!pVM->pgm.s.fNestedPaging);
4653	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4654
4655	/*
4656	* Update the shadow root page as well since that's not fixed.
4657	*/
4658	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4659	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4660	PPGMPOOLPAGE pNewShwPageCR3;
4661
4662	pgmLock(pVM);
4663
4664	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4665	if (pPool->cDirtyPages)
4666	pgmPoolResetDirtyPages(pVM);
4667	# endif
4668
4669	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4670	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4671	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
4672	&pNewShwPageCR3);
4673	AssertFatalRC(rc);
4674	rc = VINF_SUCCESS;
4675
4676	# ifdef IN_RC
4677	/*
4678	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4679	* state will be inconsistent! Flush important things now while
4680	* we still can and then make sure there are no ring-3 calls.
4681	*/
4682	# ifdef VBOX_WITH_REM
4683	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4684	# endif
4685	VMMRZCallRing3Disable(pVCpu);
4686	# endif
4687
4688	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4689	# ifdef IN_RING0
4690	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4691	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4692	# elif defined(IN_RC)
4693	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4694	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4695	# else
4696	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4697	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4698	# endif
4699
4700	# ifndef PGM_WITHOUT_MAPPINGS
4701	/*
4702	* Apply all hypervisor mappings to the new CR3.
4703	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4704	* make sure we check for conflicts in the new CR3 root.
4705	*/
4706	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4707	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4708	# endif
4709	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4710	AssertRCReturn(rc, rc);
4711	# endif
4712
4713	/* Set the current hypervisor CR3. */
4714	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4715	SELMShadowCR3Changed(pVM, pVCpu);
4716
4717	# ifdef IN_RC
4718	/* NOTE: The state is consistent again. */
4719	VMMRZCallRing3Enable(pVCpu);
4720	# endif
4721
4722	/* Clean up the old CR3 root. */
4723	if ( pOldShwPageCR3
4724	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4725	{
4726	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4727	# ifndef PGM_WITHOUT_MAPPINGS
4728	/* Remove the hypervisor mappings from the shadow page table. */
4729	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4730	# endif
4731	/* Mark the page as unlocked; allow flushing again. */
4732	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4733
4734	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
4735	}
4736	pgmUnlock(pVM);
4737	# else
4738	NOREF(GCPhysCR3);
4739	# endif
4740
4741	return rc;
4742	}
4743
4744	/**
4745	* Unmaps the shadow CR3.
4746	*
4747	* @returns VBox status, no specials.
4748	* @param pVCpu Pointer to the VMCPU.
4749	*/
4750	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4751	{
4752	LogFlow(("UnmapCR3\n"));
4753
4754	int rc = VINF_SUCCESS;
4755	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4756
4757	/*
4758	* Update guest paging info.
4759	*/
4760	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4761	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4762	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4763	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4764	# endif
4765	pVCpu->pgm.s.pGst32BitPdRC = 0;
4766
4767	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4768	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4769	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4770	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4771	# endif
4772	pVCpu->pgm.s.pGstPaePdptRC = 0;
4773	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4774	{
4775	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4776	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4777	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4778	# endif
4779	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4780	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4781	}
4782
4783	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4784	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4785	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4786	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4787	# endif
4788
4789	#else /* prot/real mode stub */
4790	/* nothing to do */
4791	#endif
4792
4793	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4794	/*
4795	* Update shadow paging info.
4796	*/
4797	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4798	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4799	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4800
4801	# if PGM_GST_TYPE != PGM_TYPE_REAL
4802	Assert(!pVM->pgm.s.fNestedPaging);
4803	# endif
4804
4805	pgmLock(pVM);
4806
4807	# ifndef PGM_WITHOUT_MAPPINGS
4808	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4809	/* Remove the hypervisor mappings from the shadow page table. */
4810	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4811	# endif
4812
4813	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4814	{
4815	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4816
4817	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4818	if (pPool->cDirtyPages)
4819	pgmPoolResetDirtyPages(pVM);
4820	# endif
4821
4822	/* Mark the page as unlocked; allow flushing again. */
4823	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4824
4825	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
4826	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4827	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4828	pVCpu->pgm.s.pShwPageCR3RC = 0;
4829	}
4830	pgmUnlock(pVM);
4831	# endif
4832	#endif /* !IN_RC*/
4833
4834	return rc;
4835	}

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 55628

Download in other formats: