PGMAllBth.h@ 13232

Last change on this file since 13232 was 13232, checked in by vboxsync, 16 years ago
#1865: changed some validation into pure assertions or assert-return. added some todos, update a comment or five and adjusted lots of whitespace.
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File size: 193.7 KB

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1	/* $Id: PGMAllBth.h 13232 2008-10-13 20:03:48Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
46	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
47	# error "Invalid combination; PAE guest implies PAE shadow"
48	#endif
49
50	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
51	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
52	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
53	#endif
54
55	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
56	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
57	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
61	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
62	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
63	#endif
64
65	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
66	# define PGM_WITHOUT_MAPPINGS
67	#endif
68
69
70	#ifndef IN_RING3
71	/**
72	* #PF Handler for raw-mode guest execution.
73	*
74	* @returns VBox status code (appropriate for trap handling and GC return).
75	* @param pVM VM Handle.
76	* @param uErr The trap error code.
77	* @param pRegFrame Trap register frame.
78	* @param pvFault The fault address.
79	*/
80	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
81	{
82	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
83	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
84	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
85
86	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
87	/*
88	* Hide the instruction fetch trap indicator for now.
89	*/
90	/** @todo NXE will change this and we must fix NXE in the switcher too! */
91	if (uErr & X86_TRAP_PF_ID)
92	{
93	uErr &= ~X86_TRAP_PF_ID;
94	TRPMSetErrorCode(pVM, uErr);
95	}
96	# endif
97
98	/*
99	* Get PDs.
100	*/
101	int rc;
102	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
103	# if PGM_GST_TYPE == PGM_TYPE_32BIT
104	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
105	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
106
107	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
108
109	# if PGM_GST_TYPE == PGM_TYPE_PAE
110	unsigned iPDSrc;
111	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
112
113	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
114	unsigned iPDSrc;
115	PX86PML4E pPml4eSrc;
116	X86PDPE PdpeSrc;
117	PGSTPD pPDSrc;
118
119	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
120	Assert(pPml4eSrc);
121	# endif
122	/* Quick check for a valid guest trap. */
123	if (!pPDSrc)
124	{
125	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
126	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%VGp\n", (int)(((RTGCUINTPTR)pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
127	# else
128	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%VGp\n", iPDSrc, CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
129	# endif
130	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
131	TRPMSetErrorCode(pVM, uErr);
132	return VINF_EM_RAW_GUEST_TRAP;
133	}
134	# endif
135
136	# else /* !PGM_WITH_PAGING */
137	PGSTPD pPDSrc = NULL;
138	const unsigned iPDSrc = 0;
139	# endif /* !PGM_WITH_PAGING */
140
141
142	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
143	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
144	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
145
146	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
147	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
148	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
149
150	# if PGM_GST_TYPE == PGM_TYPE_PAE
151	/* Did we mark the PDPT as not present in SyncCR3? */
152	unsigned iPdpte = ((RTGCUINTPTR)pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
153	if (!pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
154	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 1;
155
156	# endif
157
158	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
159	const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
160	PX86PDPAE pPDDst;
161	# if PGM_GST_TYPE == PGM_TYPE_PROT
162	/* AMD-V nested paging */
163	X86PML4E Pml4eSrc;
164	X86PDPE PdpeSrc;
165	PX86PML4E pPml4eSrc = &Pml4eSrc;
166
167	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
168	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
169	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
170	# endif
171
172	rc = PGMShwSyncLongModePDPtr(pVM, (RTGCUINTPTR)pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
173	if (rc != VINF_SUCCESS)
174	{
175	AssertRC(rc);
176	return rc;
177	}
178	Assert(pPDDst);
179
180	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
181	const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
182	PEPTPD pPDDst;
183
184	rc = PGMShwGetEPTPDPtr(pVM, (RTGCUINTPTR)pvFault, NULL, &pPDDst);
185	if (rc != VINF_SUCCESS)
186	{
187	AssertRC(rc);
188	return rc;
189	}
190	Assert(pPDDst);
191	# endif
192
193	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
194	/*
195	* If we successfully correct the write protection fault due to dirty bit
196	* tracking, or this page fault is a genuine one, then return immediately.
197	*/
198	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
199	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
200	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
201	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
202	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
203	{
204	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
205	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
206	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
207	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
208	}
209
210	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0ePD[iPDSrc]);
211	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
212
213	/*
214	* A common case is the not-present error caused by lazy page table syncing.
215	*
216	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
217	* so we can safely assume that the shadow PT is present when calling SyncPage later.
218	*
219	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
220	* of mapping conflict and defer to SyncCR3 in R3.
221	* (Again, we do NOT support access handlers for non-present guest pages.)
222	*
223	*/
224	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
225	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
226	# else
227	GSTPDE PdeSrc;
228	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
229	PdeSrc.n.u1Present = 1;
230	PdeSrc.n.u1Write = 1;
231	PdeSrc.n.u1Accessed = 1;
232	PdeSrc.n.u1User = 1;
233	# endif
234	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
235	&& !pPDDst->a[iPDDst].n.u1Present
236	&& PdeSrc.n.u1Present
237	)
238
239	{
240	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2SyncPT; });
241	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
242	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
243	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
244	if (VBOX_SUCCESS(rc))
245	{
246	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
247	return rc;
248	}
249	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
250	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
251	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
252	return VINF_PGM_SYNC_CR3;
253	}
254
255	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
256	/*
257	* Check if this address is within any of our mappings.
258	*
259	* This is very fast and it's gonna save us a bit of effort below and prevent
260	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
261	* (BTW, it's impossible to have physical access handlers in a mapping.)
262	*/
263	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
264	{
265	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
266	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
267	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
268	{
269	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
270	break;
271	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
272	{
273	/*
274	* The first thing we check is if we've got an undetected conflict.
275	*/
276	if (!pVM->pgm.s.fMappingsFixed)
277	{
278	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
279	while (iPT-- > 0)
280	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
281	{
282	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eConflicts);
283	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
284	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
285	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
286	return VINF_PGM_SYNC_CR3;
287	}
288	}
289
290	/*
291	* Check if the fault address is in a virtual page access handler range.
292	*/
293	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
294	if ( pCur
295	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb
296	&& uErr & X86_TRAP_PF_RW)
297	{
298	# ifdef IN_GC
299	STAM_PROFILE_START(&pCur->Stat, h);
300	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key);
301	STAM_PROFILE_STOP(&pCur->Stat, h);
302	# else
303	AssertFailed();
304	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
305	# endif
306	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersMapping);
307	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
308	return rc;
309	}
310
311	/*
312	* Pretend we're not here and let the guest handle the trap.
313	*/
314	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
315	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFMapping);
316	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
317	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
318	return VINF_EM_RAW_GUEST_TRAP;
319	}
320	}
321	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
322	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
323	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
324
325	/*
326	* Check if this fault address is flagged for special treatment,
327	* which means we'll have to figure out the physical address and
328	* check flags associated with it.
329	*
330	* ASSUME that we can limit any special access handling to pages
331	* in page tables which the guest believes to be present.
332	*/
333	if (PdeSrc.n.u1Present)
334	{
335	RTGCPHYS GCPhys = NIL_RTGCPHYS;
336
337	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
338	# if PGM_GST_TYPE == PGM_TYPE_AMD64
339	bool fBigPagesSupported = true;
340	# else
341	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
342	# endif
343	if ( PdeSrc.b.u1Size
344	&& fBigPagesSupported)
345	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
346	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
347	else
348	{
349	PGSTPT pPTSrc;
350	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
351	if (VBOX_SUCCESS(rc))
352	{
353	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
354	if (pPTSrc->a[iPTESrc].n.u1Present)
355	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
356	}
357	}
358	# else
359	/* No paging so the fault address is the physical address */
360	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
361	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
362
363	/*
364	* If we have a GC address we'll check if it has any flags set.
365	*/
366	if (GCPhys != NIL_RTGCPHYS)
367	{
368	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
369
370	PPGMPAGE pPage;
371	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
372	if (VBOX_SUCCESS(rc))
373	{
374	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
375	{
376	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
377	{
378	/*
379	* Physical page access handler.
380	*/
381	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
382	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
383	if (pCur)
384	{
385	# ifdef PGM_SYNC_N_PAGES
386	/*
387	* If the region is write protected and we got a page not present fault, then sync
388	* the pages. If the fault was caused by a read, then restart the instruction.
389	* In case of write access continue to the GC write handler.
390	*
391	* ASSUMES that there is only one handler per page or that they have similar write properties.
392	*/
393	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
394	&& !(uErr & X86_TRAP_PF_P))
395	{
396	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
397	if ( VBOX_FAILURE(rc)
398	\|\| !(uErr & X86_TRAP_PF_RW)
399	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
400	{
401	AssertRC(rc);
402	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
403	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
404	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
405	return rc;
406	}
407	}
408	# endif
409
410	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
411	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
412	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
413
414	# if defined(IN_GC) \|\| defined(IN_RING0)
415	if (pCur->CTX_SUFF(pfnHandler))
416	{
417	STAM_PROFILE_START(&pCur->Stat, h);
418	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
419	STAM_PROFILE_STOP(&pCur->Stat, h);
420	}
421	else
422	# endif
423	rc = VINF_EM_RAW_EMULATE_INSTR;
424	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersPhysical);
425	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
426	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndPhys; });
427	return rc;
428	}
429	}
430	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
431	else
432	{
433	# ifdef PGM_SYNC_N_PAGES
434	/*
435	* If the region is write protected and we got a page not present fault, then sync
436	* the pages. If the fault was caused by a read, then restart the instruction.
437	* In case of write access continue to the GC write handler.
438	*/
439	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
440	&& !(uErr & X86_TRAP_PF_P))
441	{
442	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
443	if ( VBOX_FAILURE(rc)
444	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
445	\|\| !(uErr & X86_TRAP_PF_RW))
446	{
447	AssertRC(rc);
448	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
449	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
450	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
451	return rc;
452	}
453	}
454	# endif
455	/*
456	* Ok, it's an virtual page access handler.
457	*
458	* Since it's faster to search by address, we'll do that first
459	* and then retry by GCPhys if that fails.
460	*/
461	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
462	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
463	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
464	*/
465	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
466	if (pCur)
467	{
468	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb)
469	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
470	\|\| !(uErr & X86_TRAP_PF_P)
471	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
472	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
473
474	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb
475	&& ( uErr & X86_TRAP_PF_RW
476	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
477	{
478	# ifdef IN_GC
479	STAM_PROFILE_START(&pCur->Stat, h);
480	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key);
481	STAM_PROFILE_STOP(&pCur->Stat, h);
482	# else
483	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
484	# endif
485	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtual);
486	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
487	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
488	return rc;
489	}
490	/* Unhandled part of a monitored page */
491	}
492	else
493	{
494	/* Check by physical address. */
495	PPGMVIRTHANDLER pCur;
496	unsigned iPage;
497	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
498	&pCur, &iPage);
499	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
500	if ( pCur
501	&& ( uErr & X86_TRAP_PF_RW
502	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
503	{
504	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
505	# ifdef IN_GC
506	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->Core.Key & PAGE_OFFSET_MASK);
507	Assert(off < pCur->cb);
508	STAM_PROFILE_START(&pCur->Stat, h);
509	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
510	STAM_PROFILE_STOP(&pCur->Stat, h);
511	# else
512	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
513	# endif
514	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
515	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
516	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
517	return rc;
518	}
519	}
520	}
521	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
522
523	/*
524	* There is a handled area of the page, but this fault doesn't belong to it.
525	* We must emulate the instruction.
526	*
527	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
528	* we first check if this was a page-not-present fault for a page with only
529	* write access handlers. Restart the instruction if it wasn't a write access.
530	*/
531	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersUnhandled);
532
533	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
534	&& !(uErr & X86_TRAP_PF_P))
535	{
536	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
537	if ( VBOX_FAILURE(rc)
538	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
539	\|\| !(uErr & X86_TRAP_PF_RW))
540	{
541	AssertRC(rc);
542	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
543	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
544	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
545	return rc;
546	}
547	}
548
549	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
550	* It's writing to an unhandled part of the LDT page several million times.
551	*/
552	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
553	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
554	rc, pPage->HCPhys,
555	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
556	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
557	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
558	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndUnhandled; });
559	return rc;
560	} /* if any kind of handler */
561
562	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
563	if (uErr & X86_TRAP_PF_P)
564	{
565	/*
566	* The page isn't marked, but it might still be monitored by a virtual page access handler.
567	* (ASSUMES no temporary disabling of virtual handlers.)
568	*/
569	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
570	* we should correct both the shadow page table and physical memory flags, and not only check for
571	* accesses within the handler region but for access to pages with virtual handlers. */
572	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
573	if (pCur)
574	{
575	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb)
576	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
577	\|\| !(uErr & X86_TRAP_PF_P)
578	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
579	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
580
581	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb
582	&& ( uErr & X86_TRAP_PF_RW
583	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
584	{
585	# ifdef IN_GC
586	STAM_PROFILE_START(&pCur->Stat, h);
587	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key);
588	STAM_PROFILE_STOP(&pCur->Stat, h);
589	# else
590	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
591	# endif
592	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
593	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
594	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
595	return rc;
596	}
597	}
598	}
599	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
600	}
601	else
602	{
603	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
604	* back to the recompiler to emulate the instruction.
605	*/
606	LogFlow(("pgmPhysGetPageEx %VGp failed with %Vrc\n", GCPhys, rc));
607	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersInvalid);
608	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
609	return VINF_EM_RAW_EMULATE_INSTR;
610	}
611
612	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
613
614	# ifdef PGM_OUT_OF_SYNC_IN_GC
615	/*
616	* We are here only if page is present in Guest page tables and trap is not handled
617	* by our handlers.
618	* Check it for page out-of-sync situation.
619	*/
620	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
621
622	if (!(uErr & X86_TRAP_PF_P))
623	{
624	/*
625	* Page is not present in our page tables.
626	* Try to sync it!
627	* BTW, fPageShw is invalid in this branch!
628	*/
629	if (uErr & X86_TRAP_PF_US)
630	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
631	else /* supervisor */
632	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
633
634	# if defined(LOG_ENABLED) && !defined(IN_RING0)
635	RTGCPHYS GCPhys;
636	uint64_t fPageGst;
637	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
638	Log(("Page out of sync: %VGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
639	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
640	# endif /* LOG_ENABLED */
641
642	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
643	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
644	{
645	uint64_t fPageGst;
646	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
647	if ( VBOX_SUCCESS(rc)
648	&& !(fPageGst & X86_PTE_US))
649	{
650	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
651	if ( pvFault == (RTGCPTR)pRegFrame->eip
652	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
653	# ifdef CSAM_DETECT_NEW_CODE_PAGES
654	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
655	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
656	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
657	)
658	{
659	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
660	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
661	if (rc != VINF_SUCCESS)
662	{
663	/*
664	* CSAM needs to perform a job in ring 3.
665	*
666	* Sync the page before going to the host context; otherwise we'll end up in a loop if
667	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
668	*/
669	LogFlow(("CSAM ring 3 job\n"));
670	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
671	AssertRC(rc2);
672
673	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
674	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2CSAM; });
675	return rc;
676	}
677	}
678	# ifdef CSAM_DETECT_NEW_CODE_PAGES
679	else if ( uErr == X86_TRAP_PF_RW
680	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
681	&& pRegFrame->ecx < 0x10000)
682	{
683	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
684	* to detect loading of new code pages.
685	*/
686
687	/*
688	* Decode the instruction.
689	*/
690	RTGCPTR PC;
691	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
692	if (rc == VINF_SUCCESS)
693	{
694	DISCPUSTATE Cpu;
695	uint32_t cbOp;
696	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
697
698	/* For now we'll restrict this to rep movsw/d instructions */
699	if ( rc == VINF_SUCCESS
700	&& Cpu.pCurInstr->opcode == OP_MOVSWD
701	&& (Cpu.prefix & PREFIX_REP))
702	{
703	CSAMMarkPossibleCodePage(pVM, pvFault);
704	}
705	}
706	}
707	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
708
709	/*
710	* Mark this page as safe.
711	*/
712	/** @todo not correct for pages that contain both code and data!! */
713	Log2(("CSAMMarkPage %VGv; scanned=%d\n", pvFault, true));
714	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
715	}
716	}
717	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
718	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
719	if (VBOX_SUCCESS(rc))
720	{
721	/* The page was successfully synced, return to the guest. */
722	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
723	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSync; });
724	return VINF_SUCCESS;
725	}
726	}
727	else
728	{
729	/*
730	* A side effect of not flushing global PDEs are out of sync pages due
731	* to physical monitored regions, that are no longer valid.
732	* Assume for now it only applies to the read/write flag
733	*/
734	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
735	{
736	if (uErr & X86_TRAP_PF_US)
737	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
738	else /* supervisor */
739	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
740
741
742	/*
743	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
744	*/
745	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
746	if (VBOX_SUCCESS(rc))
747	{
748	/*
749	* Page was successfully synced, return to guest.
750	*/
751	# ifdef VBOX_STRICT
752	RTGCPHYS GCPhys;
753	uint64_t fPageGst;
754	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
755	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
756	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
757
758	uint64_t fPageShw;
759	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
760	AssertMsg(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Vrc fPageShw=%VX64\n", rc, fPageShw));
761	# endif /* VBOX_STRICT */
762	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
763	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
764	return VINF_SUCCESS;
765	}
766
767	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
768	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
769	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
770	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
771	{
772	uint64_t fPageGst;
773	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
774	if ( VBOX_SUCCESS(rc)
775	&& !(fPageGst & X86_PTE_RW))
776	{
777	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
778	if (VBOX_SUCCESS(rc))
779	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulInRZ);
780	else
781	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulToR3);
782	return rc;
783	}
784	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
785	}
786	}
787
788	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
789	# ifdef VBOX_STRICT
790	/*
791	* Check for VMM page flags vs. Guest page flags consistency.
792	* Currently only for debug purposes.
793	*/
794	if (VBOX_SUCCESS(rc))
795	{
796	/* Get guest page flags. */
797	uint64_t fPageGst;
798	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
799	if (VBOX_SUCCESS(rc))
800	{
801	uint64_t fPageShw;
802	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
803
804	/*
805	* Compare page flags.
806	* Note: we have AVL, A, D bits desynched.
807	*/
808	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
809	("Page flags mismatch! pvFault=%VGv GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
810	}
811	else
812	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
813	}
814	else
815	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
816	# endif /* VBOX_STRICT */
817	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
818	}
819	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
820	# endif /* PGM_OUT_OF_SYNC_IN_GC */
821	}
822	else
823	{
824	/*
825	* Page not present in Guest OS or invalid page table address.
826	* This is potential virtual page access handler food.
827	*
828	* For the present we'll say that our access handlers don't
829	* work for this case - we've already discarded the page table
830	* not present case which is identical to this.
831	*
832	* When we perchance find we need this, we will probably have AVL
833	* trees (offset based) to operate on and we can measure their speed
834	* agains mapping a page table and probably rearrange this handling
835	* a bit. (Like, searching virtual ranges before checking the
836	* physical address.)
837	*/
838	}
839	}
840
841
842	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
843	/*
844	* Conclusion, this is a guest trap.
845	*/
846	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
847	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFUnh);
848	return VINF_EM_RAW_GUEST_TRAP;
849	# else
850	/* present, but not a monitored page; perhaps the guest is probing physical memory */
851	return VINF_EM_RAW_EMULATE_INSTR;
852	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
853
854
855	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
856
857	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
858	return VERR_INTERNAL_ERROR;
859	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
860	}
861	#endif /* !IN_RING3 */
862
863
864	/**
865	* Emulation of the invlpg instruction.
866	*
867	*
868	* @returns VBox status code.
869	*
870	* @param pVM VM handle.
871	* @param GCPtrPage Page to invalidate.
872	*
873	* @remark ASSUMES that the guest is updating before invalidating. This order
874	* isn't required by the CPU, so this is speculative and could cause
875	* trouble.
876	*
877	* @todo Flush page or page directory only if necessary!
878	* @todo Add a #define for simply invalidating the page.
879	*/
880	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
881	{
882	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
883	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
884	&& PGM_SHW_TYPE != PGM_TYPE_EPT
885	int rc;
886
887	LogFlow(("InvalidatePage %VGv\n", GCPtrPage));
888	/*
889	* Get the shadow PD entry and skip out if this PD isn't present.
890	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
891	*/
892	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
893	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
894	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
895	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
896	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
897	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte);
898	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
899	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
900
901	/* If the shadow PDPE isn't present, then skip the invalidate. */
902	if (!pPdptDst->a[iPdpte].n.u1Present)
903	{
904	Assert(!(pPdptDst->a[iPdpte].u & PGM_PLXFLAGS_MAPPING));
905	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
906	return VINF_SUCCESS;
907	}
908
909	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
910	/* PML4 */
911	AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
912
913	const unsigned iPml4e = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
914	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
915	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
916	PX86PDPAE pPDDst;
917	PX86PDPT pPdptDst;
918	PX86PML4E pPml4eDst = &pVM->pgm.s.pHCPaePML4->a[iPml4e];
919	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
920	if (rc != VINF_SUCCESS)
921	{
922	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
923	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
924	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
925	PGM_INVL_GUEST_TLBS();
926	return VINF_SUCCESS;
927	}
928	Assert(pPDDst);
929
930	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
931	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpte];
932
933	if (!pPdpeDst->n.u1Present)
934	{
935	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
936	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
937	PGM_INVL_GUEST_TLBS();
938	return VINF_SUCCESS;
939	}
940
941	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
942
943	const SHWPDE PdeDst = *pPdeDst;
944	if (!PdeDst.n.u1Present)
945	{
946	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
947	return VINF_SUCCESS;
948	}
949
950	/*
951	* Get the guest PD entry and calc big page.
952	*/
953	# if PGM_GST_TYPE == PGM_TYPE_32BIT
954	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
955	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
956	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
957	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
958	unsigned iPDSrc;
959	# if PGM_GST_TYPE == PGM_TYPE_PAE
960	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
961	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
962	# else /* AMD64 */
963	PX86PML4E pPml4eSrc;
964	X86PDPE PdpeSrc;
965	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
966	# endif
967	GSTPDE PdeSrc;
968
969	if (pPDSrc)
970	PdeSrc = pPDSrc->a[iPDSrc];
971	else
972	PdeSrc.u = 0;
973	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
974
975	# if PGM_GST_TYPE == PGM_TYPE_AMD64
976	const bool fIsBigPage = PdeSrc.b.u1Size;
977	# else
978	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
979	# endif
980
981	# ifdef IN_RING3
982	/*
983	* If a CR3 Sync is pending we may ignore the invalidate page operation
984	* depending on the kind of sync and if it's a global page or not.
985	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
986	*/
987	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
988	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
989	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
990	&& fIsBigPage
991	&& PdeSrc.b.u1Global
992	)
993	)
994	# else
995	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
996	# endif
997	{
998	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
999	return VINF_SUCCESS;
1000	}
1001	# endif /* IN_RING3 */
1002
1003	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1004	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1005
1006	/* Fetch the pgm pool shadow descriptor. */
1007	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
1008	Assert(pShwPdpt);
1009
1010	/* Fetch the pgm pool shadow descriptor. */
1011	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & SHW_PDPE_PG_MASK);
1012	Assert(pShwPde);
1013
1014	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1015	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1016
1017	if ( !pPml4eSrc->n.u1Present
1018	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1019	{
1020	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1021	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1022	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1023	pPml4eDst->u = 0;
1024	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1025	PGM_INVL_GUEST_TLBS();
1026	return VINF_SUCCESS;
1027	}
1028	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1029	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1030	{
1031	/*
1032	* Mark not present so we can resync the PML4E when it's used.
1033	*/
1034	LogFlow(("InvalidatePage: Out-of-sync PML4E at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1035	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1036	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1037	pPml4eDst->u = 0;
1038	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1039	PGM_INVL_GUEST_TLBS();
1040	}
1041	else if (!pPml4eSrc->n.u1Accessed)
1042	{
1043	/*
1044	* Mark not present so we can set the accessed bit.
1045	*/
1046	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1047	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1048	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1049	pPml4eDst->u = 0;
1050	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1051	PGM_INVL_GUEST_TLBS();
1052	}
1053
1054	/* Check if the PDPT entry has changed. */
1055	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1056	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1057	if ( !PdpeSrc.n.u1Present
1058	\|\| pShwPde->GCPhys != GCPhysPd)
1059	{
1060	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1061	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1062	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1063	pPdpeDst->u = 0;
1064	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1065	PGM_INVL_GUEST_TLBS();
1066	return VINF_SUCCESS;
1067	}
1068	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1069	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1070	{
1071	/*
1072	* Mark not present so we can resync the PDPTE when it's used.
1073	*/
1074	LogFlow(("InvalidatePage: Out-of-sync PDPE at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1075	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1076	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1077	pPdpeDst->u = 0;
1078	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1079	PGM_INVL_GUEST_TLBS();
1080	}
1081	else if (!PdpeSrc.lm.u1Accessed)
1082	{
1083	/*
1084	* Mark not present so we can set the accessed bit.
1085	*/
1086	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1087	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1088	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1089	pPdpeDst->u = 0;
1090	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1091	PGM_INVL_GUEST_TLBS();
1092	}
1093	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1094
1095	# if PGM_GST_TYPE == PGM_TYPE_PAE
1096	/* Note: This shouldn't actually be necessary as we monitor the PDPT page for changes. */
1097	if (!pPDSrc)
1098	{
1099	/* Guest PDPE not present */
1100	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* root of the 2048 PDE array */
1101	PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
1102	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1103
1104	Assert(!(CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte].n.u1Present));
1105	LogFlow(("InvalidatePage: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
1106	/* for each page directory entry */
1107	for (unsigned iPD = 0; iPD < X86_PG_PAE_ENTRIES; iPD++)
1108	{
1109	if ( pPDEDst[iPD].n.u1Present
1110	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
1111	{
1112	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
1113	pPDEDst[iPD].u = 0;
1114	}
1115	}
1116	if (!(pPdptDst->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
1117	pPdptDst->a[iPdpte].n.u1Present = 0;
1118	PGM_INVL_GUEST_TLBS();
1119	}
1120	AssertMsg(pVM->pgm.s.fMappingsFixed \|\| (PdpeSrc.u & X86_PDPE_PG_MASK) == pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpte], ("%VGp vs %VGp (mon)\n", (PdpeSrc.u & X86_PDPE_PG_MASK), pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpte]));
1121	# endif
1122
1123
1124	/*
1125	* Deal with the Guest PDE.
1126	*/
1127	rc = VINF_SUCCESS;
1128	if (PdeSrc.n.u1Present)
1129	{
1130	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1131	{
1132	/*
1133	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1134	*/
1135	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1136	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1137	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1138	}
1139	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1140	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1141	{
1142	/*
1143	* Mark not present so we can resync the PDE when it's used.
1144	*/
1145	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1146	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1147	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1148	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1149	# else
1150	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1151	# endif
1152	pPdeDst->u = 0;
1153	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1154	PGM_INVL_GUEST_TLBS();
1155	}
1156	else if (!PdeSrc.n.u1Accessed)
1157	{
1158	/*
1159	* Mark not present so we can set the accessed bit.
1160	*/
1161	LogFlow(("InvalidatePage: Out-of-sync (A) at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1162	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1163	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1164	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1165	# else
1166	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1167	# endif
1168	pPdeDst->u = 0;
1169	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1170	PGM_INVL_GUEST_TLBS();
1171	}
1172	else if (!fIsBigPage)
1173	{
1174	/*
1175	* 4KB - page.
1176	*/
1177	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1178	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1179	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1180	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1181	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1182	# endif
1183	if (pShwPage->GCPhys == GCPhys)
1184	{
1185	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1186	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1187	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1188	if (pPT->a[iPTEDst].n.u1Present)
1189	{
1190	# ifdef PGMPOOL_WITH_USER_TRACKING
1191	/* This is very unlikely with caching/monitoring enabled. */
1192	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1193	# endif
1194	pPT->a[iPTEDst].u = 0;
1195	}
1196	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1197	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1198	if (VBOX_SUCCESS(rc))
1199	rc = VINF_SUCCESS;
1200	# endif
1201	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1202	PGM_INVL_PG(GCPtrPage);
1203	}
1204	else
1205	{
1206	/*
1207	* The page table address changed.
1208	*/
1209	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
1210	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1211	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1212	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1213	# else
1214	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1215	# endif
1216	pPdeDst->u = 0;
1217	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1218	PGM_INVL_GUEST_TLBS();
1219	}
1220	}
1221	else
1222	{
1223	/*
1224	* 2/4MB - page.
1225	*/
1226	/* Before freeing the page, check if anything really changed. */
1227	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1228	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1229	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1230	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1231	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1232	# endif
1233	if ( pShwPage->GCPhys == GCPhys
1234	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1235	{
1236	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1237	/** @todo PAT */
1238	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1239	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1240	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1241	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1242	{
1243	LogFlow(("Skipping flush for big page containing %VGv (PD=%X .u=%VX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1244	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1245	return VINF_SUCCESS;
1246	}
1247	}
1248
1249	/*
1250	* Ok, the page table is present and it's been changed in the guest.
1251	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1252	* We could do this for some flushes in GC too, but we need an algorithm for
1253	* deciding which 4MB pages containing code likely to be executed very soon.
1254	*/
1255	LogFlow(("InvalidatePage: Out-of-sync PD at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1256	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1257	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1258	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1259	# else
1260	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1261	# endif
1262	pPdeDst->u = 0;
1263	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1264	PGM_INVL_BIG_PG(GCPtrPage);
1265	}
1266	}
1267	else
1268	{
1269	/*
1270	* Page directory is not present, mark shadow PDE not present.
1271	*/
1272	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1273	{
1274	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1275	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1276	# else
1277	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1278	# endif
1279	pPdeDst->u = 0;
1280	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1281	PGM_INVL_PG(GCPtrPage);
1282	}
1283	else
1284	{
1285	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1286	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1287	}
1288	}
1289
1290	return rc;
1291
1292	#else /* guest real and protected mode */
1293	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1294	return VINF_SUCCESS;
1295	#endif
1296	}
1297
1298
1299	#ifdef PGMPOOL_WITH_USER_TRACKING
1300	/**
1301	* Update the tracking of shadowed pages.
1302	*
1303	* @param pVM The VM handle.
1304	* @param pShwPage The shadow page.
1305	* @param HCPhys The physical page we is being dereferenced.
1306	*/
1307	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1308	{
1309	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1310	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1311	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1312
1313	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1314	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1315	* 2. write protect all shadowed pages. I.e. implement caching.
1316	*/
1317	/*
1318	* Find the guest address.
1319	*/
1320	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1321	pRam;
1322	pRam = pRam->CTX_SUFF(pNext))
1323	{
1324	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1325	while (iPage-- > 0)
1326	{
1327	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1328	{
1329	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1330	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1331	pShwPage->cPresent--;
1332	pPool->cPresent--;
1333	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1334	return;
1335	}
1336	}
1337	}
1338
1339	for (;;)
1340	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1341	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1342	pShwPage->cPresent--;
1343	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1344	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1345	}
1346
1347
1348	/**
1349	* Update the tracking of shadowed pages.
1350	*
1351	* @param pVM The VM handle.
1352	* @param pShwPage The shadow page.
1353	* @param u16 The top 16-bit of the pPage->HCPhys.
1354	* @param pPage Pointer to the guest page. this will be modified.
1355	* @param iPTDst The index into the shadow table.
1356	*/
1357	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1358	{
1359	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1360	/*
1361	* We're making certain assumptions about the placement of cRef and idx.
1362	*/
1363	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1364	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1365
1366	/*
1367	* Just deal with the simple first time here.
1368	*/
1369	if (!u16)
1370	{
1371	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1372	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1373	}
1374	else
1375	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1376
1377	/* write back, trying to be clever... */
1378	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1379	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1380	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1381	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1382
1383	/* update statistics. */
1384	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1385	pShwPage->cPresent++;
1386	if (pShwPage->iFirstPresent > iPTDst)
1387	pShwPage->iFirstPresent = iPTDst;
1388	}
1389	#endif /* PGMPOOL_WITH_USER_TRACKING */
1390
1391
1392	/**
1393	* Creates a 4K shadow page for a guest page.
1394	*
1395	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1396	* physical address. The PdeSrc argument only the flags are used. No page structured
1397	* will be mapped in this function.
1398	*
1399	* @param pVM VM handle.
1400	* @param pPteDst Destination page table entry.
1401	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1402	* Can safely assume that only the flags are being used.
1403	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1404	* @param pShwPage Pointer to the shadow page.
1405	* @param iPTDst The index into the shadow table.
1406	*
1407	* @remark Not used for 2/4MB pages!
1408	*/
1409	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1410	{
1411	if (PteSrc.n.u1Present)
1412	{
1413	/*
1414	* Find the ram range.
1415	*/
1416	PPGMPAGE pPage;
1417	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1418	if (VBOX_SUCCESS(rc))
1419	{
1420	/** @todo investiage PWT, PCD and PAT. */
1421	/*
1422	* Make page table entry.
1423	*/
1424	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1425	SHWPTE PteDst;
1426	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1427	{
1428	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1429	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1430	{
1431	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1432	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1433	PteDst.n.u1Present = 1;
1434	PteDst.n.u1Execute = 1;
1435	PteDst.n.u1IgnorePAT = 1;
1436	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1437	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1438	#else
1439	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1440	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1441	#endif
1442	}
1443	else
1444	{
1445	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1446	PteDst.u = 0;
1447	}
1448	/** @todo count these two kinds. */
1449	}
1450	else
1451	{
1452	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1453	/*
1454	* If the page or page directory entry is not marked accessed,
1455	* we mark the page not present.
1456	*/
1457	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1458	{
1459	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1460	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1461	PteDst.u = 0;
1462	}
1463	else
1464	/*
1465	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1466	* when the page is modified.
1467	*/
1468	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1469	{
1470	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1471	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1472	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1473	\| PGM_PTFLAGS_TRACK_DIRTY;
1474	}
1475	else
1476	#endif
1477	{
1478	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1479	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1480	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1481	PteDst.n.u1Present = 1;
1482	PteDst.n.u1Write = 1;
1483	PteDst.n.u1Execute = 1;
1484	PteDst.n.u1IgnorePAT = 1;
1485	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1486	/* PteDst.n.u1Size = 0 */
1487	#else
1488	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1489	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1490	#endif
1491	}
1492	}
1493
1494	#ifdef PGMPOOL_WITH_USER_TRACKING
1495	/*
1496	* Keep user track up to date.
1497	*/
1498	if (PteDst.n.u1Present)
1499	{
1500	if (!pPteDst->n.u1Present)
1501	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1502	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1503	{
1504	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1505	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1506	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1507	}
1508	}
1509	else if (pPteDst->n.u1Present)
1510	{
1511	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1512	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1513	}
1514	#endif /* PGMPOOL_WITH_USER_TRACKING */
1515
1516	/*
1517	* Update statistics and commit the entry.
1518	*/
1519	if (!PteSrc.n.u1Global)
1520	pShwPage->fSeenNonGlobal = true;
1521	*pPteDst = PteDst;
1522	}
1523	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1524	/** @todo count these. */
1525	}
1526	else
1527	{
1528	/*
1529	* Page not-present.
1530	*/
1531	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1532	#ifdef PGMPOOL_WITH_USER_TRACKING
1533	/* Keep user track up to date. */
1534	if (pPteDst->n.u1Present)
1535	{
1536	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1537	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1538	}
1539	#endif /* PGMPOOL_WITH_USER_TRACKING */
1540	pPteDst->u = 0;
1541	/** @todo count these. */
1542	}
1543	}
1544
1545
1546	/**
1547	* Syncs a guest OS page.
1548	*
1549	* There are no conflicts at this point, neither is there any need for
1550	* page table allocations.
1551	*
1552	* @returns VBox status code.
1553	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1554	* @param pVM VM handle.
1555	* @param PdeSrc Page directory entry of the guest.
1556	* @param GCPtrPage Guest context page address.
1557	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1558	* @param uErr Fault error (X86_TRAP_PF_*).
1559	*/
1560	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1561	{
1562	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1563
1564	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1565	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1566	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1567	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1568	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1569
1570	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1571	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1572	# endif
1573
1574	/*
1575	* Assert preconditions.
1576	*/
1577	Assert(PdeSrc.n.u1Present);
1578	Assert(cPages);
1579	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1580
1581	/*
1582	* Get the shadow PDE, find the shadow page table in the pool.
1583	*/
1584	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1585	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1586	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1587	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1588	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1589	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte); /* no mask; flat index into the 2048 entry array. */
1590	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
1591	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1592	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1593	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1594	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1595	PX86PDPAE pPDDst;
1596	X86PDEPAE PdeDst;
1597	PX86PDPT pPdptDst;
1598
1599	int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
1600	AssertRCSuccessReturn(rc, rc);
1601	Assert(pPDDst && pPdptDst);
1602	PdeDst = pPDDst->a[iPDDst];
1603	# endif
1604	Assert(PdeDst.n.u1Present);
1605	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1606
1607	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1608	/* Fetch the pgm pool shadow descriptor. */
1609	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
1610	Assert(pShwPde);
1611	# endif
1612
1613	/*
1614	* Check that the page is present and that the shadow PDE isn't out of sync.
1615	*/
1616	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1617	const bool fBigPage = PdeSrc.b.u1Size;
1618	# else
1619	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1620	# endif
1621	RTGCPHYS GCPhys;
1622	if (!fBigPage)
1623	{
1624	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1625	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1626	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1627	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1628	# endif
1629	}
1630	else
1631	{
1632	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1633	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1634	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1635	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1636	# endif
1637	}
1638	if ( pShwPage->GCPhys == GCPhys
1639	&& PdeSrc.n.u1Present
1640	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1641	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1642	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1643	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1644	# endif
1645	)
1646	{
1647	/*
1648	* Check that the PDE is marked accessed already.
1649	* Since we set the accessed bit before getting here on a #PF, this
1650	* check is only meant for dealing with non-#PF'ing paths.
1651	*/
1652	if (PdeSrc.n.u1Accessed)
1653	{
1654	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1655	if (!fBigPage)
1656	{
1657	/*
1658	* 4KB Page - Map the guest page table.
1659	*/
1660	PGSTPT pPTSrc;
1661	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1662	if (VBOX_SUCCESS(rc))
1663	{
1664	# ifdef PGM_SYNC_N_PAGES
1665	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1666	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1667	{
1668	/*
1669	* This code path is currently only taken when the caller is PGMTrap0eHandler
1670	* for non-present pages!
1671	*
1672	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1673	* deal with locality.
1674	*/
1675	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1676	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1677	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1678	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1679	# else
1680	const unsigned offPTSrc = 0;
1681	# endif
1682	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1683	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1684	iPTDst = 0;
1685	else
1686	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1687	for (; iPTDst < iPTDstEnd; iPTDst++)
1688	{
1689	if (!pPTDst->a[iPTDst].n.u1Present)
1690	{
1691	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1692	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1693	NOREF(GCPtrCurPage);
1694	#ifndef IN_RING0
1695	/*
1696	* Assuming kernel code will be marked as supervisor - and not as user level
1697	* and executed using a conforming code selector - And marked as readonly.
1698	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1699	*/
1700	PPGMPAGE pPage;
1701	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1702	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1703	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1704	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1705	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1706	)
1707	#endif /* else: CSAM not active */
1708	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1709	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1710	GCPtrCurPage, PteSrc.n.u1Present,
1711	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1712	PteSrc.n.u1User & PdeSrc.n.u1User,
1713	(uint64_t)PteSrc.u,
1714	(uint64_t)pPTDst->a[iPTDst].u,
1715	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1716	}
1717	}
1718	}
1719	else
1720	# endif /* PGM_SYNC_N_PAGES */
1721	{
1722	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1723	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1724	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1725	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1726	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1727	GCPtrPage, PteSrc.n.u1Present,
1728	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1729	PteSrc.n.u1User & PdeSrc.n.u1User,
1730	(uint64_t)PteSrc.u,
1731	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1732	}
1733	}
1734	else /* MMIO or invalid page: emulated in #PF handler. */
1735	{
1736	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1737	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1738	}
1739	}
1740	else
1741	{
1742	/*
1743	* 4/2MB page - lazy syncing shadow 4K pages.
1744	* (There are many causes of getting here, it's no longer only CSAM.)
1745	*/
1746	/* Calculate the GC physical address of this 4KB shadow page. */
1747	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1748	/* Find ram range. */
1749	PPGMPAGE pPage;
1750	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1751	if (VBOX_SUCCESS(rc))
1752	{
1753	/*
1754	* Make shadow PTE entry.
1755	*/
1756	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1757	SHWPTE PteDst;
1758	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1759	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1760	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1761	{
1762	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1763	PteDst.n.u1Write = 0;
1764	else
1765	PteDst.u = 0;
1766	}
1767	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1768	# ifdef PGMPOOL_WITH_USER_TRACKING
1769	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1770	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1771	# endif
1772	pPTDst->a[iPTDst] = PteDst;
1773
1774
1775	/*
1776	* If the page is not flagged as dirty and is writable, then make it read-only
1777	* at PD level, so we can set the dirty bit when the page is modified.
1778	*
1779	* ASSUMES that page access handlers are implemented on page table entry level.
1780	* Thus we will first catch the dirty access and set PDE.D and restart. If
1781	* there is an access handler, we'll trap again and let it work on the problem.
1782	*/
1783	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1784	* As for invlpg, it simply frees the whole shadow PT.
1785	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1786	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1787	{
1788	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1789	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1790	PdeDst.n.u1Write = 0;
1791	}
1792	else
1793	{
1794	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1795	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1796	}
1797	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1798	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1799	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1800	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1801	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1802	pPDDst->a[iPDDst] = PdeDst;
1803	# endif
1804	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1805	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1806	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1807	}
1808	else
1809	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1810	}
1811	return VINF_SUCCESS;
1812	}
1813	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1814	}
1815	else
1816	{
1817	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1818	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1819	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1820	}
1821
1822	/*
1823	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1824	* Yea, I'm lazy.
1825	*/
1826	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1827	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1828	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1829	# else
1830	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
1831	# endif
1832
1833	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1834	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1835	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1836	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1837	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1838	pPDDst->a[iPDDst].u = 0;
1839	# endif
1840	PGM_INVL_GUEST_TLBS();
1841	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1842
1843	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1844	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1845	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
1846
1847	# ifdef PGM_SYNC_N_PAGES
1848	/*
1849	* Get the shadow PDE, find the shadow page table in the pool.
1850	*/
1851	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1852	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1853	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1854	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1855	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
1856	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1857	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1858	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1859	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpte);
1860	PX86PDPAE pPDDst;
1861	X86PDEPAE PdeDst;
1862	PX86PDPT pPdptDst;
1863
1864	int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
1865	AssertRCSuccessReturn(rc, rc);
1866	Assert(pPDDst && pPdptDst);
1867	PdeDst = pPDDst->a[iPDDst];
1868	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1869	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1870	PEPTPD pPDDst;
1871	EPTPDE PdeDst;
1872
1873	int rc = PGMShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
1874	if (rc != VINF_SUCCESS)
1875	{
1876	AssertRC(rc);
1877	return rc;
1878	}
1879	Assert(pPDDst);
1880	PdeDst = pPDDst->a[iPDDst];
1881	# endif
1882	Assert(PdeDst.n.u1Present);
1883	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1884	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1885
1886	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1887	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1888	{
1889	/*
1890	* This code path is currently only taken when the caller is PGMTrap0eHandler
1891	* for non-present pages!
1892	*
1893	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1894	* deal with locality.
1895	*/
1896	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1897	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1898	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1899	iPTDst = 0;
1900	else
1901	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1902	for (; iPTDst < iPTDstEnd; iPTDst++)
1903	{
1904	if (!pPTDst->a[iPTDst].n.u1Present)
1905	{
1906	GSTPTE PteSrc;
1907
1908	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1909
1910	/* Fake the page table entry */
1911	PteSrc.u = GCPtrCurPage;
1912	PteSrc.n.u1Present = 1;
1913	PteSrc.n.u1Dirty = 1;
1914	PteSrc.n.u1Accessed = 1;
1915	PteSrc.n.u1Write = 1;
1916	PteSrc.n.u1User = 1;
1917
1918	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1919
1920	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1921	GCPtrCurPage, PteSrc.n.u1Present,
1922	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1923	PteSrc.n.u1User & PdeSrc.n.u1User,
1924	(uint64_t)PteSrc.u,
1925	(uint64_t)pPTDst->a[iPTDst].u,
1926	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1927	}
1928	else
1929	Log4(("%VGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1930	}
1931	}
1932	else
1933	# endif /* PGM_SYNC_N_PAGES */
1934	{
1935	GSTPTE PteSrc;
1936	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1937	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1938
1939	/* Fake the page table entry */
1940	PteSrc.u = GCPtrCurPage;
1941	PteSrc.n.u1Present = 1;
1942	PteSrc.n.u1Dirty = 1;
1943	PteSrc.n.u1Accessed = 1;
1944	PteSrc.n.u1Write = 1;
1945	PteSrc.n.u1User = 1;
1946	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1947
1948	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
1949	GCPtrPage, PteSrc.n.u1Present,
1950	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1951	PteSrc.n.u1User & PdeSrc.n.u1User,
1952	(uint64_t)PteSrc.u,
1953	(uint64_t)pPTDst->a[iPTDst].u,
1954	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1955	}
1956	return VINF_SUCCESS;
1957
1958	#else
1959	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1960	return VERR_INTERNAL_ERROR;
1961	#endif
1962	}
1963
1964
1965	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1966	/**
1967	* Investigate page fault and handle write protection page faults caused by
1968	* dirty bit tracking.
1969	*
1970	* @returns VBox status code.
1971	* @param pVM VM handle.
1972	* @param uErr Page fault error code.
1973	* @param pPdeDst Shadow page directory entry.
1974	* @param pPdeSrc Guest page directory entry.
1975	* @param GCPtrPage Guest context page address.
1976	*/
1977	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1978	{
1979	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1980	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1981	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1982	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1983	bool fBigPagesSupported = true;
1984	# else
1985	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1986	# endif
1987	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1988	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1989	# endif
1990	unsigned uPageFaultLevel;
1991	int rc;
1992
1993	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
1994	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1995
1996	# if PGM_GST_TYPE == PGM_TYPE_PAE \
1997	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
1998
1999	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2000	PX86PML4E pPml4eSrc;
2001	PX86PDPE pPdpeSrc;
2002
2003	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
2004	Assert(pPml4eSrc);
2005
2006	/*
2007	* Real page fault? (PML4E level)
2008	*/
2009	if ( (uErr & X86_TRAP_PF_RSVD)
2010	\|\| !pPml4eSrc->n.u1Present
2011	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2012	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2013	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2014	)
2015	{
2016	uPageFaultLevel = 0;
2017	goto l_UpperLevelPageFault;
2018	}
2019	Assert(pPdpeSrc);
2020
2021	# else /* PAE */
2022	PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
2023	# endif
2024
2025	/*
2026	* Real page fault? (PDPE level)
2027	*/
2028	if ( (uErr & X86_TRAP_PF_RSVD)
2029	\|\| !pPdpeSrc->n.u1Present
2030	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2031	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2032	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2033	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2034	# endif
2035	)
2036	{
2037	uPageFaultLevel = 1;
2038	goto l_UpperLevelPageFault;
2039	}
2040	# endif
2041
2042	/*
2043	* Real page fault? (PDE level)
2044	*/
2045	if ( (uErr & X86_TRAP_PF_RSVD)
2046	\|\| !pPdeSrc->n.u1Present
2047	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2048	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2049	# endif
2050	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2051	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2052	{
2053	uPageFaultLevel = 2;
2054	goto l_UpperLevelPageFault;
2055	}
2056
2057	/*
2058	* First check the easy case where the page directory has been marked read-only to track
2059	* the dirty bit of an emulated BIG page
2060	*/
2061	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2062	{
2063	/* Mark guest page directory as accessed */
2064	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2065	pPml4eSrc->n.u1Accessed = 1;
2066	pPdpeSrc->lm.u1Accessed = 1;
2067	# endif
2068	pPdeSrc->b.u1Accessed = 1;
2069
2070	/*
2071	* Only write protection page faults are relevant here.
2072	*/
2073	if (fWriteFault)
2074	{
2075	/* Mark guest page directory as dirty (BIG page only). */
2076	pPdeSrc->b.u1Dirty = 1;
2077
2078	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2079	{
2080	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2081
2082	Assert(pPdeSrc->b.u1Write);
2083
2084	pPdeDst->n.u1Write = 1;
2085	pPdeDst->n.u1Accessed = 1;
2086	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2087	PGM_INVL_BIG_PG(GCPtrPage);
2088	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2089	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2090	}
2091	}
2092	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2093	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2094	}
2095	/* else: 4KB page table */
2096
2097	/*
2098	* Map the guest page table.
2099	*/
2100	PGSTPT pPTSrc;
2101	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2102	if (VBOX_SUCCESS(rc))
2103	{
2104	/*
2105	* Real page fault?
2106	*/
2107	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2108	const GSTPTE PteSrc = *pPteSrc;
2109	if ( !PteSrc.n.u1Present
2110	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2111	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2112	# endif
2113	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2114	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2115	)
2116	{
2117	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2118	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2119	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2120
2121	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2122	* See the 2nd case above as well.
2123	*/
2124	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2125	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2126
2127	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2128	return VINF_EM_RAW_GUEST_TRAP;
2129	}
2130	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2131
2132	/*
2133	* Set the accessed bits in the page directory and the page table.
2134	*/
2135	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2136	pPml4eSrc->n.u1Accessed = 1;
2137	pPdpeSrc->lm.u1Accessed = 1;
2138	# endif
2139	pPdeSrc->n.u1Accessed = 1;
2140	pPteSrc->n.u1Accessed = 1;
2141
2142	/*
2143	* Only write protection page faults are relevant here.
2144	*/
2145	if (fWriteFault)
2146	{
2147	/* Write access, so mark guest entry as dirty. */
2148	# ifdef VBOX_WITH_STATISTICS
2149	if (!pPteSrc->n.u1Dirty)
2150	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2151	else
2152	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2153	# endif
2154
2155	pPteSrc->n.u1Dirty = 1;
2156
2157	if (pPdeDst->n.u1Present)
2158	{
2159	#ifndef IN_RING0
2160	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2161	* Our individual shadow handlers will provide more information and force a fatal exit.
2162	*/
2163	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2164	{
2165	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
2166	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2167	return VINF_SUCCESS;
2168	}
2169	#endif
2170	/*
2171	* Map shadow page table.
2172	*/
2173	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2174	if (pShwPage)
2175	{
2176	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2177	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2178	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2179	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2180	{
2181	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
2182	# ifdef VBOX_STRICT
2183	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2184	if (pPage)
2185	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2186	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2187	# endif
2188	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2189
2190	Assert(pPteSrc->n.u1Write);
2191
2192	pPteDst->n.u1Write = 1;
2193	pPteDst->n.u1Dirty = 1;
2194	pPteDst->n.u1Accessed = 1;
2195	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2196	PGM_INVL_PG(GCPtrPage);
2197
2198	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2199	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2200	}
2201	}
2202	else
2203	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2204	}
2205	}
2206	/** @todo Optimize accessed bit emulation? */
2207	# ifdef VBOX_STRICT
2208	/*
2209	* Sanity check.
2210	*/
2211	else if ( !pPteSrc->n.u1Dirty
2212	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2213	&& pPdeDst->n.u1Present)
2214	{
2215	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2216	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2217	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2218	if ( pPteDst->n.u1Present
2219	&& pPteDst->n.u1Write)
2220	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2221	}
2222	# endif /* VBOX_STRICT */
2223	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2224	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2225	}
2226	AssertRC(rc);
2227	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2228	return rc;
2229
2230
2231	l_UpperLevelPageFault:
2232	/*
2233	* Pagefault detected while checking the PML4E, PDPE or PDE.
2234	* Single exit handler to get rid of duplicate code paths.
2235	*/
2236	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2237	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2238	Log(("CheckPageFault: real page fault at %VGv (%d)\n", GCPtrPage, uPageFaultLevel));
2239
2240	if (
2241	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2242	pPml4eSrc->n.u1Present &&
2243	# endif
2244	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2245	pPdpeSrc->n.u1Present &&
2246	# endif
2247	pPdeSrc->n.u1Present)
2248	{
2249	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2250	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2251	{
2252	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2253	}
2254	else
2255	{
2256	/*
2257	* Map the guest page table.
2258	*/
2259	PGSTPT pPTSrc;
2260	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2261	if (VBOX_SUCCESS(rc))
2262	{
2263	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2264	const GSTPTE PteSrc = *pPteSrc;
2265	if (pPteSrc->n.u1Present)
2266	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2267	}
2268	AssertRC(rc);
2269	}
2270	}
2271	return VINF_EM_RAW_GUEST_TRAP;
2272	}
2273	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2274
2275
2276	/**
2277	* Sync a shadow page table.
2278	*
2279	* The shadow page table is not present. This includes the case where
2280	* there is a conflict with a mapping.
2281	*
2282	* @returns VBox status code.
2283	* @param pVM VM handle.
2284	* @param iPD Page directory index.
2285	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2286	* Assume this is a temporary mapping.
2287	* @param GCPtrPage GC Pointer of the page that caused the fault
2288	*/
2289	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
2290	{
2291	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2292	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPtPD[iPDSrc]);
2293	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
2294
2295	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2296	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2297	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2298	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2299	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2300
2301	int rc = VINF_SUCCESS;
2302
2303	/*
2304	* Validate input a little bit.
2305	*/
2306	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%VGv\n", iPDSrc, GCPtrPage));
2307	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2308	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2309	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2310	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2311	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
2312	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte);
2313	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
2314	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2315	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2316	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2317	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2318	PX86PDPAE pPDDst;
2319	PX86PDPT pPdptDst;
2320	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2321	AssertRCSuccessReturn(rc, rc);
2322	Assert(pPDDst);
2323	# endif
2324
2325	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2326	SHWPDE PdeDst = *pPdeDst;
2327
2328	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2329	/* Fetch the pgm pool shadow descriptor. */
2330	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
2331	Assert(pShwPde);
2332	# endif
2333
2334	# ifndef PGM_WITHOUT_MAPPINGS
2335	/*
2336	* Check for conflicts.
2337	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2338	* HC: Simply resolve the conflict.
2339	*/
2340	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2341	{
2342	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2343	# ifndef IN_RING3
2344	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
2345	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2346	return VERR_ADDRESS_CONFLICT;
2347	# else
2348	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2349	Assert(pMapping);
2350	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2351	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2352	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2353	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2354	# else
2355	AssertFailed(); /* can't happen for amd64 */
2356	# endif
2357	if (VBOX_FAILURE(rc))
2358	{
2359	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2360	return rc;
2361	}
2362	PdeDst = *pPdeDst;
2363	# endif
2364	}
2365	# else /* PGM_WITHOUT_MAPPINGS */
2366	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2367	# endif /* PGM_WITHOUT_MAPPINGS */
2368	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2369
2370	/*
2371	* Sync page directory entry.
2372	*/
2373	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2374	if (PdeSrc.n.u1Present)
2375	{
2376	/*
2377	* Allocate & map the page table.
2378	*/
2379	PSHWPT pPTDst;
2380	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2381	const bool fPageTable = !PdeSrc.b.u1Size;
2382	# else
2383	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2384	# endif
2385	PPGMPOOLPAGE pShwPage;
2386	RTGCPHYS GCPhys;
2387	if (fPageTable)
2388	{
2389	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2390	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2391	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2392	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2393	# endif
2394	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2395	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2396	# else
2397	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2398	# endif
2399	}
2400	else
2401	{
2402	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2403	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2404	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2405	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2406	# endif
2407	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2408	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2409	# else
2410	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2411	# endif
2412	}
2413	if (rc == VINF_SUCCESS)
2414	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2415	else if (rc == VINF_PGM_CACHED_PAGE)
2416	{
2417	/*
2418	* The PT was cached, just hook it up.
2419	*/
2420	if (fPageTable)
2421	PdeDst.u = pShwPage->Core.Key
2422	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2423	else
2424	{
2425	PdeDst.u = pShwPage->Core.Key
2426	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2427	/* (see explanation and assumptions further down.) */
2428	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2429	{
2430	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2431	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2432	PdeDst.b.u1Write = 0;
2433	}
2434	}
2435	*pPdeDst = PdeDst;
2436	return VINF_SUCCESS;
2437	}
2438	else if (rc == VERR_PGM_POOL_FLUSHED)
2439	{
2440	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2441	return VINF_PGM_SYNC_CR3;
2442	}
2443	else
2444	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2445	PdeDst.u &= X86_PDE_AVL_MASK;
2446	PdeDst.u \|= pShwPage->Core.Key;
2447
2448	/*
2449	* Page directory has been accessed (this is a fault situation, remember).
2450	*/
2451	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2452	if (fPageTable)
2453	{
2454	/*
2455	* Page table - 4KB.
2456	*
2457	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2458	*/
2459	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2460	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2461	PGSTPT pPTSrc;
2462	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2463	if (VBOX_SUCCESS(rc))
2464	{
2465	/*
2466	* Start by syncing the page directory entry so CSAM's TLB trick works.
2467	*/
2468	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2469	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2470	*pPdeDst = PdeDst;
2471
2472	/*
2473	* Directory/page user or supervisor privilege: (same goes for read/write)
2474	*
2475	* Directory Page Combined
2476	* U/S U/S U/S
2477	* 0 0 0
2478	* 0 1 0
2479	* 1 0 0
2480	* 1 1 1
2481	*
2482	* Simple AND operation. Table listed for completeness.
2483	*
2484	*/
2485	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2486	# ifdef PGM_SYNC_N_PAGES
2487	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2488	unsigned iPTDst = iPTBase;
2489	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2490	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2491	iPTDst = 0;
2492	else
2493	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2494	# else /* !PGM_SYNC_N_PAGES */
2495	unsigned iPTDst = 0;
2496	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2497	# endif /* !PGM_SYNC_N_PAGES */
2498	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2499	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2500	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2501	# else
2502	const unsigned offPTSrc = 0;
2503	# endif
2504	for (; iPTDst < iPTDstEnd; iPTDst++)
2505	{
2506	const unsigned iPTSrc = iPTDst + offPTSrc;
2507	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2508
2509	if (PteSrc.n.u1Present) /* we've already cleared it above */
2510	{
2511	# ifndef IN_RING0
2512	/*
2513	* Assuming kernel code will be marked as supervisor - and not as user level
2514	* and executed using a conforming code selector - And marked as readonly.
2515	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2516	*/
2517	PPGMPAGE pPage;
2518	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2519	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2520	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2521	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2522	)
2523	# endif
2524	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2525	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2526	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2527	PteSrc.n.u1Present,
2528	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2529	PteSrc.n.u1User & PdeSrc.n.u1User,
2530	(uint64_t)PteSrc.u,
2531	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2532	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2533	}
2534	} /* for PTEs */
2535	}
2536	}
2537	else
2538	{
2539	/*
2540	* Big page - 2/4MB.
2541	*
2542	* We'll walk the ram range list in parallel and optimize lookups.
2543	* We will only sync on shadow page table at a time.
2544	*/
2545	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2546
2547	/**
2548	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2549	*/
2550
2551	/*
2552	* Start by syncing the page directory entry.
2553	*/
2554	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2555	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2556
2557	/*
2558	* If the page is not flagged as dirty and is writable, then make it read-only
2559	* at PD level, so we can set the dirty bit when the page is modified.
2560	*
2561	* ASSUMES that page access handlers are implemented on page table entry level.
2562	* Thus we will first catch the dirty access and set PDE.D and restart. If
2563	* there is an access handler, we'll trap again and let it work on the problem.
2564	*/
2565	/** @todo move the above stuff to a section in the PGM documentation. */
2566	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2567	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2568	{
2569	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2570	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2571	PdeDst.b.u1Write = 0;
2572	}
2573	*pPdeDst = PdeDst;
2574
2575	/*
2576	* Fill the shadow page table.
2577	*/
2578	/* Get address and flags from the source PDE. */
2579	SHWPTE PteDstBase;
2580	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2581
2582	/* Loop thru the entries in the shadow PT. */
2583	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2584	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2585	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2586	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2587	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2588	unsigned iPTDst = 0;
2589	while (iPTDst < RT_ELEMENTS(pPTDst->a))
2590	{
2591	/* Advance ram range list. */
2592	while (pRam && GCPhys > pRam->GCPhysLast)
2593	pRam = pRam->CTX_SUFF(pNext);
2594	if (pRam && GCPhys >= pRam->GCPhys)
2595	{
2596	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2597	do
2598	{
2599	/* Make shadow PTE. */
2600	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2601	SHWPTE PteDst;
2602
2603	/* Make sure the RAM has already been allocated. */
2604	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2605	{
2606	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2607	{
2608	# ifdef IN_RING3
2609	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2610	# else
2611	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2612	# endif
2613	if (rc != VINF_SUCCESS)
2614	return rc;
2615	}
2616	}
2617
2618	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2619	{
2620	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2621	{
2622	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2623	PteDst.n.u1Write = 0;
2624	}
2625	else
2626	PteDst.u = 0;
2627	}
2628	# ifndef IN_RING0
2629	/*
2630	* Assuming kernel code will be marked as supervisor and not as user level and executed
2631	* using a conforming code selector. Don't check for readonly, as that implies the whole
2632	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2633	*/
2634	else if ( !PdeSrc.n.u1User
2635	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2636	PteDst.u = 0;
2637	# endif
2638	else
2639	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2640	# ifdef PGMPOOL_WITH_USER_TRACKING
2641	if (PteDst.n.u1Present)
2642	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2643	# endif
2644	/* commit it */
2645	pPTDst->a[iPTDst] = PteDst;
2646	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2647	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2648	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2649
2650	/* advance */
2651	GCPhys += PAGE_SIZE;
2652	iHCPage++;
2653	iPTDst++;
2654	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2655	&& GCPhys <= pRam->GCPhysLast);
2656	}
2657	else if (pRam)
2658	{
2659	Log(("Invalid pages at %VGp\n", GCPhys));
2660	do
2661	{
2662	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2663	GCPhys += PAGE_SIZE;
2664	iPTDst++;
2665	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2666	&& GCPhys < pRam->GCPhys);
2667	}
2668	else
2669	{
2670	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2671	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2672	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2673	}
2674	} /* while more PTEs */
2675	} /* 4KB / 4MB */
2676	}
2677	else
2678	AssertRelease(!PdeDst.n.u1Present);
2679
2680	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2681	if (VBOX_FAILURE(rc))
2682	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2683	return rc;
2684
2685	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2686	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2687	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2688
2689	int rc = VINF_SUCCESS;
2690
2691	/*
2692	* Validate input a little bit.
2693	*/
2694	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2695	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2696	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2697	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2698	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
2699	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2700	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2701	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2702	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2703	PX86PDPAE pPDDst;
2704	PX86PDPT pPdptDst;
2705	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2706	AssertRCSuccessReturn(rc, rc);
2707	Assert(pPDDst);
2708
2709	/* Fetch the pgm pool shadow descriptor. */
2710	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
2711	Assert(pShwPde);
2712	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2713	const unsigned iPdpte = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2714	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2715	PEPTPD pPDDst;
2716	PEPTPDPT pPdptDst;
2717
2718	rc = PGMShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2719	if (rc != VINF_SUCCESS)
2720	{
2721	AssertRC(rc);
2722	return rc;
2723	}
2724	Assert(pPDDst);
2725
2726	/* Fetch the pgm pool shadow descriptor. */
2727	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & EPT_PDPTE_PG_MASK);
2728	Assert(pShwPde);
2729	# endif
2730	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2731	SHWPDE PdeDst = *pPdeDst;
2732
2733	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2734	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2735
2736	GSTPDE PdeSrc;
2737	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2738	PdeSrc.n.u1Present = 1;
2739	PdeSrc.n.u1Write = 1;
2740	PdeSrc.n.u1Accessed = 1;
2741	PdeSrc.n.u1User = 1;
2742
2743	/*
2744	* Allocate & map the page table.
2745	*/
2746	PSHWPT pPTDst;
2747	PPGMPOOLPAGE pShwPage;
2748	RTGCPHYS GCPhys;
2749
2750	/* Virtual address = physical address */
2751	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2752	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2753	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2754	# else
2755	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2756	# endif
2757
2758	if ( rc == VINF_SUCCESS
2759	\|\| rc == VINF_PGM_CACHED_PAGE)
2760	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2761	else
2762	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2763
2764	PdeDst.u &= X86_PDE_AVL_MASK;
2765	PdeDst.u \|= pShwPage->Core.Key;
2766	PdeDst.n.u1Present = 1;
2767	PdeDst.n.u1Write = 1;
2768	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2769	PdeDst.n.u1Execute = 1;
2770	# else
2771	PdeDst.n.u1User = 1;
2772	PdeDst.n.u1Accessed = 1;
2773	# endif
2774	*pPdeDst = PdeDst;
2775
2776	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2777	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2778	return rc;
2779
2780	#else
2781	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2782	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2783	return VERR_INTERNAL_ERROR;
2784	#endif
2785	}
2786
2787
2788
2789	/**
2790	* Prefetch a page/set of pages.
2791	*
2792	* Typically used to sync commonly used pages before entering raw mode
2793	* after a CR3 reload.
2794	*
2795	* @returns VBox status code.
2796	* @param pVM VM handle.
2797	* @param GCPtrPage Page to invalidate.
2798	*/
2799	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2800	{
2801	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2802	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2803	/*
2804	* Check that all Guest levels thru the PDE are present, getting the
2805	* PD and PDE in the processes.
2806	*/
2807	int rc = VINF_SUCCESS;
2808	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2809	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2810	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2811	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2812	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2813	unsigned iPDSrc;
2814	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2815	if (!pPDSrc)
2816	return VINF_SUCCESS; /* not present */
2817	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2818	unsigned iPDSrc;
2819	PX86PML4E pPml4eSrc;
2820	X86PDPE PdpeSrc;
2821	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2822	if (!pPDSrc)
2823	return VINF_SUCCESS; /* not present */
2824	# endif
2825	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2826	# else
2827	PGSTPD pPDSrc = NULL;
2828	const unsigned iPDSrc = 0;
2829	GSTPDE PdeSrc;
2830
2831	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2832	PdeSrc.n.u1Present = 1;
2833	PdeSrc.n.u1Write = 1;
2834	PdeSrc.n.u1Accessed = 1;
2835	PdeSrc.n.u1User = 1;
2836	# endif
2837
2838	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2839	{
2840	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2841	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2842	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2843	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2844	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2845	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2846	PX86PDPAE pPDDst;
2847	X86PDEPAE PdeDst;
2848
2849	# if PGM_GST_TYPE == PGM_TYPE_PROT
2850	/* AMD-V nested paging */
2851	X86PML4E Pml4eSrc;
2852	X86PDPE PdpeSrc;
2853	PX86PML4E pPml4eSrc = &Pml4eSrc;
2854
2855	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2856	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2857	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2858	# endif
2859
2860	int rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2861	if (rc != VINF_SUCCESS)
2862	{
2863	AssertRC(rc);
2864	return rc;
2865	}
2866	Assert(pPDDst);
2867	PdeDst = pPDDst->a[iPDDst];
2868	# endif
2869	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2870	{
2871	if (!PdeDst.n.u1Present)
2872	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2873	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2874	else
2875	{
2876	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2877	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2878	* makes no sense to prefetch more than one page.
2879	*/
2880	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2881	if (VBOX_SUCCESS(rc))
2882	rc = VINF_SUCCESS;
2883	}
2884	}
2885	}
2886	return rc;
2887
2888	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2889	return VINF_SUCCESS; /* ignore */
2890	#endif
2891	}
2892
2893
2894
2895
2896	/**
2897	* Syncs a page during a PGMVerifyAccess() call.
2898	*
2899	* @returns VBox status code (informational included).
2900	* @param GCPtrPage The address of the page to sync.
2901	* @param fPage The effective guest page flags.
2902	* @param uErr The trap error code.
2903	*/
2904	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2905	{
2906	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2907
2908	Assert(!HWACCMIsNestedPagingActive(pVM));
2909	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
2910	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2911
2912	# ifndef IN_RING0
2913	if (!(fPage & X86_PTE_US))
2914	{
2915	/*
2916	* Mark this page as safe.
2917	*/
2918	/** @todo not correct for pages that contain both code and data!! */
2919	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2920	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
2921	}
2922	# endif
2923
2924	/*
2925	* Get guest PD and index.
2926	*/
2927	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2928	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2929	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2930	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2931	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2932	unsigned iPDSrc;
2933	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2934
2935	if (pPDSrc)
2936	{
2937	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2938	return VINF_EM_RAW_GUEST_TRAP;
2939	}
2940	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2941	unsigned iPDSrc;
2942	PX86PML4E pPml4eSrc;
2943	X86PDPE PdpeSrc;
2944	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2945	if (!pPDSrc)
2946	{
2947	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2948	return VINF_EM_RAW_GUEST_TRAP;
2949	}
2950	# endif
2951	# else
2952	PGSTPD pPDSrc = NULL;
2953	const unsigned iPDSrc = 0;
2954	# endif
2955	int rc = VINF_SUCCESS;
2956
2957	/*
2958	* First check if the shadow pd is present.
2959	*/
2960	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2961	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2962	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2963	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2964	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2965	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2966	PX86PDPAE pPDDst;
2967	PX86PDEPAE pPdeDst;
2968
2969	# if PGM_GST_TYPE == PGM_TYPE_PROT
2970	/* AMD-V nested paging */
2971	X86PML4E Pml4eSrc;
2972	X86PDPE PdpeSrc;
2973	PX86PML4E pPml4eSrc = &Pml4eSrc;
2974
2975	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2976	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2977	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2978	# endif
2979
2980	rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2981	if (rc != VINF_SUCCESS)
2982	{
2983	AssertRC(rc);
2984	return rc;
2985	}
2986	Assert(pPDDst);
2987	pPdeDst = &pPDDst->a[iPDDst];
2988	# endif
2989	if (!pPdeDst->n.u1Present)
2990	{
2991	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2992	AssertRC(rc);
2993	if (rc != VINF_SUCCESS)
2994	return rc;
2995	}
2996
2997	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2998	/* Check for dirty bit fault */
2999	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3000	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3001	Log(("PGMVerifyAccess: success (dirty)\n"));
3002	else
3003	{
3004	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3005	#else
3006	{
3007	GSTPDE PdeSrc;
3008	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3009	PdeSrc.n.u1Present = 1;
3010	PdeSrc.n.u1Write = 1;
3011	PdeSrc.n.u1Accessed = 1;
3012	PdeSrc.n.u1User = 1;
3013
3014	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3015	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3016	if (uErr & X86_TRAP_PF_US)
3017	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3018	else /* supervisor */
3019	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3020
3021	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3022	if (VBOX_SUCCESS(rc))
3023	{
3024	/* Page was successfully synced */
3025	Log2(("PGMVerifyAccess: success (sync)\n"));
3026	rc = VINF_SUCCESS;
3027	}
3028	else
3029	{
3030	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
3031	return VINF_EM_RAW_GUEST_TRAP;
3032	}
3033	}
3034	return rc;
3035
3036	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3037
3038	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3039	return VERR_INTERNAL_ERROR;
3040	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3041	}
3042
3043
3044	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3045	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3046	/**
3047	* Figures out which kind of shadow page this guest PDE warrants.
3048	*
3049	* @returns Shadow page kind.
3050	* @param pPdeSrc The guest PDE in question.
3051	* @param cr4 The current guest cr4 value.
3052	*/
3053	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3054	{
3055	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3056	if (!pPdeSrc->n.u1Size)
3057	# else
3058	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3059	# endif
3060	return BTH_PGMPOOLKIND_PT_FOR_PT;
3061	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3062	//{
3063	// case 0:
3064	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3065	// case X86_PDE4M_RW:
3066	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3067	// case X86_PDE4M_US:
3068	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3069	// case X86_PDE4M_RW \| X86_PDE4M_US:
3070	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3071	# if 0
3072	// case X86_PDE4M_PAE_NX:
3073	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3074	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3075	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3076	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3077	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3078	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3079	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3080	# endif
3081	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3082	//}
3083	}
3084	# endif
3085	#endif
3086
3087	#undef MY_STAM_COUNTER_INC
3088	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3089
3090
3091	/**
3092	* Syncs the paging hierarchy starting at CR3.
3093	*
3094	* @returns VBox status code, no specials.
3095	* @param pVM The virtual machine.
3096	* @param cr0 Guest context CR0 register
3097	* @param cr3 Guest context CR3 register
3098	* @param cr4 Guest context CR4 register
3099	* @param fGlobal Including global page directories or not
3100	*/
3101	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3102	{
3103	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3104	fGlobal = true; /* Change this CR3 reload to be a global one. */
3105
3106	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3107	/*
3108	* Update page access handlers.
3109	* The virtual are always flushed, while the physical are only on demand.
3110	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3111	* have to look into that later because it will have a bad influence on the performance.
3112	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3113	* bird: Yes, but that won't work for aliases.
3114	*/
3115	/** @todo this MUST go away. See #1557. */
3116	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3117	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3118	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3119	#endif
3120
3121	#ifdef PGMPOOL_WITH_MONITORING
3122	int rc = pgmPoolSyncCR3(pVM);
3123	if (rc != VINF_SUCCESS)
3124	return rc;
3125	#endif
3126
3127	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3128	/** @todo check if this is really necessary */
3129	HWACCMFlushTLB(pVM);
3130	return VINF_SUCCESS;
3131
3132	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3133	/* No need to check all paging levels; we zero out the shadow parts when the guest modifies its tables. */
3134	return VINF_SUCCESS;
3135	#else
3136
3137	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
3138	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Global) : &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3NotGlobal));
3139
3140	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3141	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3142	bool fBigPagesSupported = true;
3143	# else
3144	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3145	# endif
3146
3147	/*
3148	* Get page directory addresses.
3149	*/
3150	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3151	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
3152	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64*/
3153	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3154	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
3155	# endif
3156	# endif
3157
3158	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3159	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
3160	Assert(pPDSrc);
3161	# ifndef IN_GC
3162	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3163	# endif
3164	# endif
3165
3166	/*
3167	* Iterate the page directory.
3168	*/
3169	PPGMMAPPING pMapping;
3170	unsigned iPdNoMapping;
3171	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
3172	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3173
3174	/* Only check mappings if they are supposed to be put into the shadow page table. */
3175	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
3176	{
3177	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3178	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
3179	}
3180	else
3181	{
3182	pMapping = 0;
3183	iPdNoMapping = ~0U;
3184	}
3185	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3186	for (uint64_t iPml4e = 0; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
3187	{
3188	PPGMPOOLPAGE pShwPdpt = NULL;
3189	PX86PML4E pPml4eSrc, pPml4eDst;
3190	RTGCPHYS GCPhysPdptSrc;
3191
3192	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
3193	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
3194
3195	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3196	if (!pPml4eDst->n.u1Present)
3197	continue;
3198	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3199
3200	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3201
3202	/* Anything significant changed? */
3203	if ( pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present
3204	\|\| GCPhysPdptSrc != pShwPdpt->GCPhys)
3205	{
3206	/* Free it. */
3207	LogFlow(("SyncCR3: Out-of-sync PML4E (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3208	(uint64_t)iPml4e << X86_PML4_SHIFT, pShwPdpt->GCPhys, GCPhysPdptSrc, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
3209	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
3210	pPml4eDst->u = 0;
3211	continue;
3212	}
3213	/* Force an attribute sync. */
3214	pPml4eDst->n.u1User = pPml4eSrc->n.u1User;
3215	pPml4eDst->n.u1Write = pPml4eSrc->n.u1Write;
3216	pPml4eDst->n.u1NoExecute = pPml4eSrc->n.u1NoExecute;
3217
3218	# else
3219	{
3220	# endif
3221	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3222	for (uint64_t iPdpte = 0; iPdpte < GST_PDPE_ENTRIES; iPdpte++)
3223	{
3224	unsigned iPDSrc;
3225	# if PGM_GST_TYPE == PGM_TYPE_PAE
3226	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3227	PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
3228	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpte << X86_PDPT_SHIFT, &iPDSrc);
3229	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
3230	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
3231
3232	if (pPDSrc == NULL)
3233	{
3234	/* PDPE not present */
3235	if (pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
3236	{
3237	LogFlow(("SyncCR3: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
3238	/* for each page directory entry */
3239	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3240	{
3241	if ( pPDEDst[iPD].n.u1Present
3242	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3243	{
3244	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
3245	pPDEDst[iPD].u = 0;
3246	}
3247	}
3248	}
3249	if (!(pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
3250	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 0;
3251	continue;
3252	}
3253	# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3254	PPGMPOOLPAGE pShwPde = NULL;
3255	RTGCPHYS GCPhysPdeSrc;
3256	PX86PDPE pPdpeDst;
3257	PX86PML4E pPml4eSrc;
3258	X86PDPE PdpeSrc;
3259	PX86PDPT pPdptDst;
3260	PX86PDPAE pPDDst;
3261	PX86PDEPAE pPDEDst;
3262	RTGCUINTPTR GCPtr = (iPml4e << X86_PML4_SHIFT) \|\| (iPdpte << X86_PDPT_SHIFT);
3263	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3264
3265	int rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
3266	if (rc != VINF_SUCCESS)
3267	{
3268	if (rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
3269	break; /* next PML4E */
3270
3271	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3272	continue; /* next PDPTE */
3273	}
3274	Assert(pPDDst);
3275	pPDEDst = &pPDDst->a[0];
3276	Assert(iPDSrc == 0);
3277
3278	pPdpeDst = &pPdptDst->a[iPdpte];
3279
3280	/* Fetch the pgm pool shadow descriptor if the shadow pdpte is present. */
3281	if (!pPdpeDst->n.u1Present)
3282	continue; /* next PDPTE */
3283
3284	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3285	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3286
3287	/* Anything significant changed? */
3288	if ( PdpeSrc.n.u1Present != pPdpeDst->n.u1Present
3289	\|\| GCPhysPdeSrc != pShwPde->GCPhys)
3290	{
3291	/* Free it. */
3292	LogFlow(("SyncCR3: Out-of-sync PDPE (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3293	((uint64_t)iPml4e << X86_PML4_SHIFT) + ((uint64_t)iPdpte << X86_PDPT_SHIFT), pShwPde->GCPhys, GCPhysPdeSrc, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
3294
3295	/* Mark it as not present if there's no hypervisor mapping present. (bit flipped at the top of Trap0eHandler) */
3296	Assert(!(pPdpeDst->u & PGM_PLXFLAGS_MAPPING));
3297	pgmPoolFreeByPage(pPool, pShwPde, pShwPde->idx, iPdpte);
3298	pPdpeDst->u = 0;
3299	continue; /* next guest PDPTE */
3300	}
3301	/* Force an attribute sync. */
3302	pPdpeDst->lm.u1User = PdpeSrc.lm.u1User;
3303	pPdpeDst->lm.u1Write = PdpeSrc.lm.u1Write;
3304	pPdpeDst->lm.u1NoExecute = PdpeSrc.lm.u1NoExecute;
3305	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
3306
3307	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3308	{
3309	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3310	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3311	{
3312	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3313	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
3314	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3315	AssertMsg(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst, ("%p vs %p\n", &pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512], pPDEDst));
3316	# endif
3317	GSTPDE PdeSrc = pPDSrc->a[iPD];
3318	if ( PdeSrc.n.u1Present
3319	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3320	{
3321	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3322	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3323	&& !defined(PGM_WITHOUT_MAPPINGS)
3324
3325	/*
3326	* Check for conflicts with GC mappings.
3327	*/
3328	# if PGM_GST_TYPE == PGM_TYPE_PAE
3329	if (iPD + iPdpte * X86_PG_PAE_ENTRIES == iPdNoMapping)
3330	# else
3331	if (iPD == iPdNoMapping)
3332	# endif
3333	{
3334	if (pVM->pgm.s.fMappingsFixed)
3335	{
3336	/* It's fixed, just skip the mapping. */
3337	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3338	iPD += cPTs - 1;
3339	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3340	pMapping = pMapping->CTX_SUFF(pNext);
3341	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3342	continue;
3343	}
3344	# ifdef IN_RING3
3345	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3346	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3347	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3348	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3349	# endif
3350	if (VBOX_FAILURE(rc))
3351	return rc;
3352
3353	/*
3354	* Update iPdNoMapping and pMapping.
3355	*/
3356	pMapping = pVM->pgm.s.pMappingsR3;
3357	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3358	pMapping = pMapping->pNextR3;
3359	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3360	# else
3361	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3362	return VINF_PGM_SYNC_CR3;
3363	# endif
3364	}
3365	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3366	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3367	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3368
3369	/*
3370	* Sync page directory entry.
3371	*
3372	* The current approach is to allocated the page table but to set
3373	* the entry to not-present and postpone the page table synching till
3374	* it's actually used.
3375	*/
3376	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3377	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3378	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3379	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3380	# else
3381	const unsigned iPdShw = iPD; NOREF(iPdShw);
3382	# endif
3383	{
3384	SHWPDE PdeDst = *pPDEDst;
3385	if (PdeDst.n.u1Present)
3386	{
3387	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3388	RTGCPHYS GCPhys;
3389	if ( !PdeSrc.b.u1Size
3390	\|\| !fBigPagesSupported)
3391	{
3392	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3393	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3394	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3395	GCPhys \|= i * (PAGE_SIZE / 2);
3396	# endif
3397	}
3398	else
3399	{
3400	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3401	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3402	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3403	GCPhys \|= i * X86_PAGE_2M_SIZE;
3404	# endif
3405	}
3406
3407	if ( pShwPage->GCPhys == GCPhys
3408	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3409	&& ( pShwPage->fCached
3410	\|\| ( !fGlobal
3411	&& ( false
3412	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3413	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3414	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3415	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3416	# else
3417	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3418	# endif
3419	\|\| ( !pShwPage->fSeenNonGlobal
3420	&& (cr4 & X86_CR4_PGE))
3421	# endif
3422	)
3423	)
3424	)
3425	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3426	\|\| ( fBigPagesSupported
3427	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3428	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3429	)
3430	)
3431	{
3432	# ifdef VBOX_WITH_STATISTICS
3433	if ( !fGlobal
3434	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3435	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3436	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3437	# else
3438	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3439	# endif
3440	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPD));
3441	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3442	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPT));
3443	else
3444	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstCacheHit));
3445	# endif /* VBOX_WITH_STATISTICS */
3446	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3447	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3448	//# ifdef PGMPOOL_WITH_CACHE
3449	// pgmPoolCacheUsed(pPool, pShwPage);
3450	//# endif
3451	}
3452	else
3453	{
3454	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3455	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPdShw);
3456	# else
3457	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3458	# endif
3459	pPDEDst->u = 0;
3460	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreed));
3461	}
3462	}
3463	else
3464	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstNotPresent));
3465	pPDEDst++;
3466	}
3467	}
3468	# if PGM_GST_TYPE == PGM_TYPE_PAE
3469	else if (iPD + iPdpte * X86_PG_PAE_ENTRIES != iPdNoMapping)
3470	# else
3471	else if (iPD != iPdNoMapping)
3472	# endif
3473	{
3474	/*
3475	* Check if there is any page directory to mark not present here.
3476	*/
3477	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3478	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3479	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3480	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3481	# else
3482	const unsigned iPdShw = iPD; NOREF(iPdShw);
3483	# endif
3484	{
3485	if (pPDEDst->n.u1Present)
3486	{
3487	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3488	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), pShwPde->idx, iPdShw);
3489	# else
3490	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
3491	# endif
3492	pPDEDst->u = 0;
3493	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreedSrcNP));
3494	}
3495	pPDEDst++;
3496	}
3497	}
3498	else
3499	{
3500	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3501	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3502	&& !defined(PGM_WITHOUT_MAPPINGS)
3503
3504	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3505
3506	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3507	if (pVM->pgm.s.fMappingsFixed)
3508	{
3509	/* It's fixed, just skip the mapping. */
3510	pMapping = pMapping->CTX_SUFF(pNext);
3511	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3512	}
3513	else
3514	{
3515	/*
3516	* Check for conflicts for subsequent pagetables
3517	* and advance to the next mapping.
3518	*/
3519	iPdNoMapping = ~0U;
3520	unsigned iPT = cPTs;
3521	while (iPT-- > 1)
3522	{
3523	if ( pPDSrc->a[iPD + iPT].n.u1Present
3524	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3525	{
3526	# ifdef IN_RING3
3527	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3528	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3529	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3530	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3531	# endif
3532	if (VBOX_FAILURE(rc))
3533	return rc;
3534
3535	/*
3536	* Update iPdNoMapping and pMapping.
3537	*/
3538	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3539	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3540	pMapping = pMapping->CTX_SUFF(pNext);
3541	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3542	break;
3543	# else
3544	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3545	return VINF_PGM_SYNC_CR3;
3546	# endif
3547	}
3548	}
3549	if (iPdNoMapping == ~0U && pMapping)
3550	{
3551	pMapping = pMapping->CTX_SUFF(pNext);
3552	if (pMapping)
3553	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3554	}
3555	}
3556
3557	/* advance. */
3558	iPD += cPTs - 1;
3559	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3560	# if PGM_GST_TYPE != PGM_SHW_TYPE
3561	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3562	# endif
3563	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3564	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3565	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3566	}
3567
3568	} /* for iPD */
3569	} /* for each PDPTE (PAE) */
3570	} /* for each page map level 4 entry (amd64) */
3571	return VINF_SUCCESS;
3572
3573	# else /* guest real and protected mode */
3574	return VINF_SUCCESS;
3575	# endif
3576	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
3577	}
3578
3579
3580
3581
3582	#ifdef VBOX_STRICT
3583	#ifdef IN_GC
3584	# undef AssertMsgFailed
3585	# define AssertMsgFailed Log
3586	#endif
3587	#ifdef IN_RING3
3588	# include <VBox/dbgf.h>
3589
3590	/**
3591	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3592	*
3593	* @returns VBox status code (VINF_SUCCESS).
3594	* @param pVM The VM handle.
3595	* @param cr3 The root of the hierarchy.
3596	* @param crr The cr4, only PAE and PSE is currently used.
3597	* @param fLongMode Set if long mode, false if not long mode.
3598	* @param cMaxDepth Number of levels to dump.
3599	* @param pHlp Pointer to the output functions.
3600	*/
3601	__BEGIN_DECLS
3602	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3603	__END_DECLS
3604
3605	#endif
3606
3607	/**
3608	* Checks that the shadow page table is in sync with the guest one.
3609	*
3610	* @returns The number of errors.
3611	* @param pVM The virtual machine.
3612	* @param cr3 Guest context CR3 register
3613	* @param cr4 Guest context CR4 register
3614	* @param GCPtr Where to start. Defaults to 0.
3615	* @param cb How much to check. Defaults to everything.
3616	*/
3617	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
3618	{
3619	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3620	return 0;
3621	#else
3622	unsigned cErrors = 0;
3623
3624	#if PGM_GST_TYPE == PGM_TYPE_PAE
3625	/** @todo currently broken; crashes below somewhere */
3626	AssertFailed();
3627	#endif
3628
3629	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3630	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3631	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3632
3633	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3634	bool fBigPagesSupported = true;
3635	# else
3636	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3637	# endif
3638	PPGM pPGM = &pVM->pgm.s;
3639	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3640	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3641	# ifndef IN_RING0
3642	RTHCPHYS HCPhys; /* general usage. */
3643	# endif
3644	int rc;
3645
3646	/*
3647	* Check that the Guest CR3 and all its mappings are correct.
3648	*/
3649	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3650	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3651	false);
3652	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3653	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3654	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGuestPDGC, NULL, &HCPhysShw);
3655	# else
3656	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePDPTGC, NULL, &HCPhysShw);
3657	# endif
3658	AssertRCReturn(rc, 1);
3659	HCPhys = NIL_RTHCPHYS;
3660	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3661	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
3662	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3663	RTGCPHYS GCPhys;
3664	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
3665	AssertRCReturn(rc, 1);
3666	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
3667	# endif
3668	#endif /* !IN_RING0 */
3669
3670	/*
3671	* Get and check the Shadow CR3.
3672	*/
3673	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3674	unsigned cPDEs = X86_PG_ENTRIES;
3675	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3676	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3677	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3678	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3679	# else
3680	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3681	# endif
3682	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3683	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3684	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3685	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3686	# endif
3687	if (cb != ~(RTGCUINTPTR)0)
3688	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3689
3690	/** @todo call the other two PGMAssert() functions. /
3691
3692	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3693	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3694	# endif
3695
3696	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3697	unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3698
3699	for (; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
3700	{
3701	PPGMPOOLPAGE pShwPdpt = NULL;
3702	PX86PML4E pPml4eSrc;
3703	PX86PML4E pPml4eDst;
3704	RTGCPHYS GCPhysPdptSrc;
3705
3706	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
3707	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
3708
3709	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3710	if (!pPml4eDst->n.u1Present)
3711	{
3712	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3713	continue;
3714	}
3715
3716	# if PGM_GST_TYPE == PGM_TYPE_PAE
3717	/* not correct to call pgmPoolGetPage */
3718	AssertFailed();
3719	# endif
3720	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3721	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3722
3723	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3724	{
3725	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3726	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3727	cErrors++;
3728	continue;
3729	}
3730
3731	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3732	{
3733	AssertMsgFailed(("Physical address doesn't match! iPml4e %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3734	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3735	cErrors++;
3736	continue;
3737	}
3738
3739	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3740	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3741	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3742	{
3743	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3744	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3745	cErrors++;
3746	continue;
3747	}
3748	# else
3749	{
3750	# endif
3751
3752	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3753	/*
3754	* Check the PDPTEs too.
3755	*/
3756	unsigned iPdpte = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3757
3758	for (;iPdpte <= SHW_PDPT_MASK; iPdpte++)
3759	{
3760	unsigned iPDSrc;
3761	PPGMPOOLPAGE pShwPde = NULL;
3762	PX86PDPE pPdpeDst;
3763	RTGCPHYS GCPhysPdeSrc;
3764	# if PGM_GST_TYPE == PGM_TYPE_PAE
3765	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3766	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc);
3767	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
3768	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
3769	# else
3770	PX86PML4E pPml4eSrc;
3771	X86PDPE PdpeSrc;
3772	PX86PDPT pPdptDst;
3773	PX86PDPAE pPDDst;
3774	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3775
3776	rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
3777	if (rc != VINF_SUCCESS)
3778	{
3779	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3780	GCPtr += 512 * _2M;
3781	continue; /* next PDPTE */
3782	}
3783	Assert(pPDDst);
3784	# endif
3785	Assert(iPDSrc == 0);
3786
3787	pPdpeDst = &pPdptDst->a[iPdpte];
3788
3789	if (!pPdpeDst->n.u1Present)
3790	{
3791	GCPtr += 512 * _2M;
3792	continue; /* next PDPTE */
3793	}
3794
3795	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3796	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3797
3798	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3799	{
3800	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3801	GCPtr += 512 * _2M;
3802	cErrors++;
3803	continue;
3804	}
3805
3806	if (GCPhysPdeSrc != pShwPde->GCPhys)
3807	{
3808	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3809	AssertMsgFailed(("Physical address doesn't match! iPml4e %d iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3810	# else
3811	AssertMsgFailed(("Physical address doesn't match! iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3812	# endif
3813	GCPtr += 512 * _2M;
3814	cErrors++;
3815	continue;
3816	}
3817
3818	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3819	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3820	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3821	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3822	{
3823	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3824	GCPtr += 512 * _2M;
3825	cErrors++;
3826	continue;
3827	}
3828	# endif
3829
3830	# else
3831	{
3832	# endif
3833	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3834	const GSTPD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
3835	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3836	PCX86PD pPDDst = pPGM->CTXMID(p,32BitPD);
3837	# else
3838	PCX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
3839	# endif
3840	# endif
3841	/*
3842	* Iterate the shadow page directory.
3843	*/
3844	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3845	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3846
3847	for (;
3848	iPDDst < cPDEs;
3849	iPDDst++, GCPtr += cIncrement)
3850	{
3851	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3852	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3853	{
3854	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3855	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3856	{
3857	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3858	cErrors++;
3859	continue;
3860	}
3861	}
3862	else if ( (PdeDst.u & X86_PDE_P)
3863	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3864	)
3865	{
3866	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3867	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3868	if (!pPoolPage)
3869	{
3870	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3871	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3872	cErrors++;
3873	continue;
3874	}
3875	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3876
3877	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3878	{
3879	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
3880	GCPtr, (uint64_t)PdeDst.u));
3881	cErrors++;
3882	}
3883
3884	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3885	{
3886	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
3887	GCPtr, (uint64_t)PdeDst.u));
3888	cErrors++;
3889	}
3890
3891	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3892	if (!PdeSrc.n.u1Present)
3893	{
3894	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3895	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3896	cErrors++;
3897	continue;
3898	}
3899
3900	if ( !PdeSrc.b.u1Size
3901	\|\| !fBigPagesSupported)
3902	{
3903	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3904	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3905	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3906	# endif
3907	}
3908	else
3909	{
3910	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3911	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3912	{
3913	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3914	GCPtr, (uint64_t)PdeSrc.u));
3915	cErrors++;
3916	continue;
3917	}
3918	# endif
3919	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3920	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3921	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3922	# endif
3923	}
3924
3925	if ( pPoolPage->enmKind
3926	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3927	{
3928	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3929	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3930	cErrors++;
3931	}
3932
3933	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3934	if (!pPhysPage)
3935	{
3936	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3937	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3938	cErrors++;
3939	continue;
3940	}
3941
3942	if (GCPhysGst != pPoolPage->GCPhys)
3943	{
3944	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3945	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3946	cErrors++;
3947	continue;
3948	}
3949
3950	if ( !PdeSrc.b.u1Size
3951	\|\| !fBigPagesSupported)
3952	{
3953	/*
3954	* Page Table.
3955	*/
3956	const GSTPT *pPTSrc;
3957	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3958	if (VBOX_FAILURE(rc))
3959	{
3960	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3961	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3962	cErrors++;
3963	continue;
3964	}
3965	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3966	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3967	{
3968	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3969	// (This problem will go away when/if we shadow multiple CR3s.)
3970	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3971	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3972	cErrors++;
3973	continue;
3974	}
3975	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3976	{
3977	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3978	GCPtr, (uint64_t)PdeDst.u));
3979	cErrors++;
3980	continue;
3981	}
3982
3983	/* iterate the page table. */
3984	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3985	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3986	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3987	# else
3988	const unsigned offPTSrc = 0;
3989	# endif
3990	for (unsigned iPT = 0, off = 0;
3991	iPT < RT_ELEMENTS(pPTDst->a);
3992	iPT++, off += PAGE_SIZE)
3993	{
3994	const SHWPTE PteDst = pPTDst->a[iPT];
3995
3996	/* skip not-present entries. */
3997	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3998	continue;
3999	Assert(PteDst.n.u1Present);
4000
4001	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4002	if (!PteSrc.n.u1Present)
4003	{
4004	# ifdef IN_RING3
4005	PGMAssertHandlerAndFlagsInSync(pVM);
4006	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
4007	# endif
4008	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
4009	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4010	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
4011	cErrors++;
4012	continue;
4013	}
4014
4015	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4016	# if 1 /** @todo sync accessed bit properly... */
4017	fIgnoreFlags \|= X86_PTE_A;
4018	# endif
4019
4020	/* match the physical addresses */
4021	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
4022	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
4023
4024	# ifdef IN_RING3
4025	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4026	if (VBOX_FAILURE(rc))
4027	{
4028	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4029	{
4030	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4031	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4032	cErrors++;
4033	continue;
4034	}
4035	}
4036	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4037	{
4038	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
4039	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4040	cErrors++;
4041	continue;
4042	}
4043	# endif
4044
4045	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4046	if (!pPhysPage)
4047	{
4048	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4049	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4050	{
4051	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4052	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4053	cErrors++;
4054	continue;
4055	}
4056	# endif
4057	if (PteDst.n.u1Write)
4058	{
4059	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
4060	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4061	cErrors++;
4062	}
4063	fIgnoreFlags \|= X86_PTE_RW;
4064	}
4065	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
4066	{
4067	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
4068	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4069	cErrors++;
4070	continue;
4071	}
4072
4073	/* flags */
4074	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4075	{
4076	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4077	{
4078	if (PteDst.n.u1Write)
4079	{
4080	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
4081	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4082	cErrors++;
4083	continue;
4084	}
4085	fIgnoreFlags \|= X86_PTE_RW;
4086	}
4087	else
4088	{
4089	if (PteDst.n.u1Present)
4090	{
4091	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
4092	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4093	cErrors++;
4094	continue;
4095	}
4096	fIgnoreFlags \|= X86_PTE_P;
4097	}
4098	}
4099	else
4100	{
4101	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4102	{
4103	if (PteDst.n.u1Write)
4104	{
4105	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4106	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4107	cErrors++;
4108	continue;
4109	}
4110	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4111	{
4112	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4113	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4114	cErrors++;
4115	continue;
4116	}
4117	if (PteDst.n.u1Dirty)
4118	{
4119	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4120	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4121	cErrors++;
4122	}
4123	# if 0 /** @todo sync access bit properly... */
4124	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4125	{
4126	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4127	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4128	cErrors++;
4129	}
4130	fIgnoreFlags \|= X86_PTE_RW;
4131	# else
4132	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4133	# endif
4134	}
4135	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4136	{
4137	/* access bit emulation (not implemented). */
4138	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4139	{
4140	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4141	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4142	cErrors++;
4143	continue;
4144	}
4145	if (!PteDst.n.u1Accessed)
4146	{
4147	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4148	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4149	cErrors++;
4150	}
4151	fIgnoreFlags \|= X86_PTE_P;
4152	}
4153	# ifdef DEBUG_sandervl
4154	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4155	# endif
4156	}
4157
4158	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4159	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4160	)
4161	{
4162	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4163	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4164	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4165	cErrors++;
4166	continue;
4167	}
4168	} /* foreach PTE */
4169	}
4170	else
4171	{
4172	/*
4173	* Big Page.
4174	*/
4175	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4176	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4177	{
4178	if (PdeDst.n.u1Write)
4179	{
4180	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4181	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4182	cErrors++;
4183	continue;
4184	}
4185	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4186	{
4187	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4188	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4189	cErrors++;
4190	continue;
4191	}
4192	# if 0 /** @todo sync access bit properly... */
4193	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4194	{
4195	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4196	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4197	cErrors++;
4198	}
4199	fIgnoreFlags \|= X86_PTE_RW;
4200	# else
4201	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4202	# endif
4203	}
4204	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4205	{
4206	/* access bit emulation (not implemented). */
4207	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4208	{
4209	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4210	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4211	cErrors++;
4212	continue;
4213	}
4214	if (!PdeDst.n.u1Accessed)
4215	{
4216	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4217	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4218	cErrors++;
4219	}
4220	fIgnoreFlags \|= X86_PTE_P;
4221	}
4222
4223	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4224	{
4225	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4226	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4227	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4228	cErrors++;
4229	}
4230
4231	/* iterate the page table. */
4232	for (unsigned iPT = 0, off = 0;
4233	iPT < RT_ELEMENTS(pPTDst->a);
4234	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4235	{
4236	const SHWPTE PteDst = pPTDst->a[iPT];
4237
4238	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4239	{
4240	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4241	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4242	cErrors++;
4243	}
4244
4245	/* skip not-present entries. */
4246	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4247	continue;
4248
4249	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4250
4251	/* match the physical addresses */
4252	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4253
4254	# ifdef IN_RING3
4255	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4256	if (VBOX_FAILURE(rc))
4257	{
4258	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4259	{
4260	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4261	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4262	cErrors++;
4263	}
4264	}
4265	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4266	{
4267	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4268	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4269	cErrors++;
4270	continue;
4271	}
4272	# endif
4273	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4274	if (!pPhysPage)
4275	{
4276	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4277	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4278	{
4279	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4280	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4281	cErrors++;
4282	continue;
4283	}
4284	# endif
4285	if (PteDst.n.u1Write)
4286	{
4287	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4288	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4289	cErrors++;
4290	}
4291	fIgnoreFlags \|= X86_PTE_RW;
4292	}
4293	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
4294	{
4295	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4296	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4297	cErrors++;
4298	continue;
4299	}
4300
4301	/* flags */
4302	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4303	{
4304	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4305	{
4306	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4307	{
4308	if (PteDst.n.u1Write)
4309	{
4310	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
4311	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4312	cErrors++;
4313	continue;
4314	}
4315	fIgnoreFlags \|= X86_PTE_RW;
4316	}
4317	}
4318	else
4319	{
4320	if (PteDst.n.u1Present)
4321	{
4322	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
4323	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4324	cErrors++;
4325	continue;
4326	}
4327	fIgnoreFlags \|= X86_PTE_P;
4328	}
4329	}
4330
4331	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4332	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4333	)
4334	{
4335	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4336	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4337	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4338	cErrors++;
4339	continue;
4340	}
4341	} /* for each PTE */
4342	}
4343	}
4344	/* not present */
4345
4346	} /* for each PDE */
4347
4348	} /* for each PDPTE */
4349
4350	} /* for each PML4E */
4351
4352	# ifdef DEBUG
4353	if (cErrors)
4354	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4355	# endif
4356
4357	#endif
4358	return cErrors;
4359
4360	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4361	}
4362	#endif /* VBOX_STRICT */
4363

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 13232

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