VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 7657

Last change on this file since 7657 was 7657, checked in by vboxsync, 17 years ago

Renamed 4M to BIG
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 147.0 KB
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1/* $Id: PGMAllBth.h 7657 2008-03-31 13:26:24Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4 *
5 * This file is a big challenge!
6 */
7
8/*
9 * Copyright (C) 2006-2007 innotek GmbH
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19
20/*******************************************************************************
21* Internal Functions *
22*******************************************************************************/
23__BEGIN_DECLS
24PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
25PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
26PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
27PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
28PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
29PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
30PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
31PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal);
32#ifdef VBOX_STRICT
33PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
34#endif
35#ifdef PGMPOOL_WITH_USER_TRACKING
36DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
37#endif
38__END_DECLS
39
40
41/**
42 * #PF Handler for raw-mode guest execution.
43 *
44 * @returns VBox status code (appropriate for trap handling and GC return).
45 * @param pVM VM Handle.
46 * @param uErr The trap error code.
47 * @param pRegFrame Trap register frame.
48 * @param pvFault The fault address.
49 */
50PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
51{
52#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT || PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
53
54# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
55# error "32-bit guest mode is only implemented for 32-bit and PAE shadow modes."
56# endif
57
58# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
59 /*
60 * Hide the instruction fetch trap indicator for now.
61 */
62 /** @todo NXE will change this and we must fix NXE in the switcher too! */
63 if (uErr & X86_TRAP_PF_ID)
64 {
65 uErr &= ~X86_TRAP_PF_ID;
66 TRPMSetErrorCode(pVM, uErr);
67 }
68# endif
69
70 /*
71 * Get PDs.
72 */
73 int rc;
74# if PGM_WITH_PAGING(PGM_GST_TYPE)
75# if PGM_GST_TYPE == PGM_TYPE_32BIT
76 const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
77 PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
78# else /* PAE */
79 unsigned iPDSrc;
80 PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
81# endif
82# else
83 PGSTPD pPDSrc = NULL;
84 const unsigned iPDSrc = 0;
85# endif
86
87 const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
88# if PGM_SHW_TYPE == PGM_TYPE_32BIT
89 PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
90# else /* PAE */
91 PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
92# endif
93
94# if PGM_WITH_PAGING(PGM_GST_TYPE)
95# ifdef PGM_SYNC_DIRTY_BIT
96 /*
97 * If we successfully correct the write protection fault due to dirty bit
98 * tracking, or this page fault is a genuine one, then return immediately.
99 */
100 STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
101 rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
102 STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
103 if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
104 || rc == VINF_EM_RAW_GUEST_TRAP)
105 {
106 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
107 = rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
108 LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
109 return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
110 }
111# endif
112
113 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
114# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
115
116 /*
117 * A common case is the not-present error caused by lazy page table syncing.
118 *
119 * It is IMPORTANT that we weed out any access to non-present shadow PDEs here
120 * so we can safely assume that the shadow PT is present when calling SyncPage later.
121 *
122 * On failure, we ASSUME that SyncPT is out of memory or detected some kind
123 * of mapping conflict and defer to SyncCR3 in R3.
124 * (Again, we do NOT support access handlers for non-present guest pages.)
125 *
126 */
127# if PGM_WITH_PAGING(PGM_GST_TYPE)
128 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
129# else
130 GSTPDE PdeSrc;
131 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
132 PdeSrc.n.u1Present = 1;
133 PdeSrc.n.u1Write = 1;
134 PdeSrc.n.u1Accessed = 1;
135 PdeSrc.n.u1User = 1;
136# endif
137 if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
138 && !pPDDst->a[iPDDst].n.u1Present
139 && PdeSrc.n.u1Present
140 )
141
142 {
143 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
144 STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
145 LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
146 rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
147 if (VBOX_SUCCESS(rc))
148 {
149 STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
150 return rc;
151 }
152 Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
153 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
154 STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
155 return VINF_PGM_SYNC_CR3;
156 }
157
158# if PGM_WITH_PAGING(PGM_GST_TYPE)
159 /*
160 * Check if this address is within any of our mappings.
161 *
162 * This is *very* fast and it's gonna save us a bit of effort below and prevent
163 * us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
164 * (BTW, it's impossible to have physical access handlers in a mapping.)
165 */
166 if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
167 {
168 STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
169 PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
170 for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
171 {
172 if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
173 break;
174 if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
175 {
176 /*
177 * The first thing we check is if we've got an undetected conflict.
178 */
179 if (!pVM->pgm.s.fMappingsFixed)
180 {
181 unsigned iPT = pMapping->cPTs;
182 while (iPT-- > 0)
183 if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
184 {
185 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
186 Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
187 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
188 STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
189 return VINF_PGM_SYNC_CR3;
190 }
191 }
192
193 /*
194 * Check if the fault address is in a virtual page access handler range.
195 */
196 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
197 if ( pCur
198 && (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
199 && uErr & X86_TRAP_PF_RW)
200 {
201# ifdef IN_GC
202 STAM_PROFILE_START(&pCur->Stat, h);
203 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
204 STAM_PROFILE_STOP(&pCur->Stat, h);
205# else
206 AssertFailed();
207 rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
208# endif
209 STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
210 STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
211 return rc;
212 }
213
214 /*
215 * Pretend we're not here and let the guest handle the trap.
216 */
217 TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
218 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
219 LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
220 STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
221 return VINF_EM_RAW_GUEST_TRAP;
222 }
223 }
224 STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
225 } /* pgmAreMappingsEnabled(&pVM->pgm.s) */
226# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
227
228 /*
229 * Check if this fault address is flagged for special treatment,
230 * which means we'll have to figure out the physical address and
231 * check flags associated with it.
232 *
233 * ASSUME that we can limit any special access handling to pages
234 * in page tables which the guest believes to be present.
235 */
236 if (PdeSrc.n.u1Present)
237 {
238 RTGCPHYS GCPhys = NIL_RTGCPHYS;
239
240# if PGM_WITH_PAGING(PGM_GST_TYPE)
241 uint32_t cr4 = CPUMGetGuestCR4(pVM);
242 if ( PdeSrc.b.u1Size
243 && (cr4 & X86_CR4_PSE))
244 GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
245 | ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
246 else
247 {
248 PX86PT pPTSrc;
249# ifdef IN_GC
250 rc = PGMGCDynMapGCPage(pVM, PdeSrc.u & GST_PDE_PG_MASK, (void **)&pPTSrc);
251# else
252 pPTSrc = (PX86PT)MMPhysGCPhys2HCVirt(pVM, PdeSrc.u & GST_PDE_PG_MASK, sizeof(*pPTSrc));
253 if (pPTSrc == 0)
254 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
255# endif
256 if (VBOX_SUCCESS(rc))
257 {
258 unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> PAGE_SHIFT) & GST_PT_MASK;
259 if (pPTSrc->a[iPTESrc].n.u1Present)
260 GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
261 }
262 }
263# else
264 /* No paging so the fault address is the physical address */
265 GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
266# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
267
268 /*
269 * If we have a GC address we'll check if it has any flags set.
270 */
271 if (GCPhys != NIL_RTGCPHYS)
272 {
273 STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
274
275 PPGMPAGE pPage;
276 rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
277 if (VBOX_SUCCESS(rc))
278 {
279 if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
280 {
281 if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
282 {
283 /*
284 * Physical page access handler.
285 */
286 const RTGCPHYS GCPhysFault = GCPhys | ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
287 PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
288 if (pCur)
289 {
290# ifdef PGM_SYNC_N_PAGES
291 /*
292 * If the region is write protected and we got a page not present fault, then sync
293 * the pages. If the fault was caused by a read, then restart the instruction.
294 * In case of write access continue to the GC write handler.
295 *
296 * ASSUMES that there is only one handler per page or that they have similar write properties.
297 */
298 if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
299 && !(uErr & X86_TRAP_PF_P))
300 {
301 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
302 if ( VBOX_FAILURE(rc)
303 || !(uErr & X86_TRAP_PF_RW)
304 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
305 {
306 AssertRC(rc);
307 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
308 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
309 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
310 return rc;
311 }
312 }
313# endif
314
315 AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
316 || (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
317 ("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
318
319#if defined(IN_GC) || defined(IN_RING0)
320 if (CTXALLSUFF(pCur->pfnHandler))
321 {
322 STAM_PROFILE_START(&pCur->Stat, h);
323 rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
324 STAM_PROFILE_STOP(&pCur->Stat, h);
325 }
326 else
327#endif
328 rc = VINF_EM_RAW_EMULATE_INSTR;
329 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
330 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
331 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
332 return rc;
333 }
334 }
335# if PGM_WITH_PAGING(PGM_GST_TYPE)
336 else
337 {
338# ifdef PGM_SYNC_N_PAGES
339 /*
340 * If the region is write protected and we got a page not present fault, then sync
341 * the pages. If the fault was caused by a read, then restart the instruction.
342 * In case of write access continue to the GC write handler.
343 */
344 if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
345 && !(uErr & X86_TRAP_PF_P))
346 {
347 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
348 if ( VBOX_FAILURE(rc)
349 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
350 || !(uErr & X86_TRAP_PF_RW))
351 {
352 AssertRC(rc);
353 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
354 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
355 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
356 return rc;
357 }
358 }
359# endif
360 /*
361 * Ok, it's an virtual page access handler.
362 *
363 * Since it's faster to search by address, we'll do that first
364 * and then retry by GCPhys if that fails.
365 */
366 /** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
367 /** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
368 * page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
369 */
370 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
371 if (pCur)
372 {
373 AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
374 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
375 || !(uErr & X86_TRAP_PF_P)
376 || (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
377 ("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
378
379 if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
380 && ( uErr & X86_TRAP_PF_RW
381 || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
382 {
383# ifdef IN_GC
384 STAM_PROFILE_START(&pCur->Stat, h);
385 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
386 STAM_PROFILE_STOP(&pCur->Stat, h);
387# else
388 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
389# endif
390 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
391 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
392 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
393 return rc;
394 }
395 /* Unhandled part of a monitored page */
396 }
397 else
398 {
399 /* Check by physical address. */
400 PPGMVIRTHANDLER pCur;
401 unsigned iPage;
402 rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
403 &pCur, &iPage);
404 Assert(VBOX_SUCCESS(rc) || !pCur);
405 if ( pCur
406 && ( uErr & X86_TRAP_PF_RW
407 || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
408 {
409 Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
410# ifdef IN_GC
411 RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
412 Assert(off < pCur->cb);
413 STAM_PROFILE_START(&pCur->Stat, h);
414 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
415 STAM_PROFILE_STOP(&pCur->Stat, h);
416# else
417 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
418# endif
419 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
420 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
421 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
422 return rc;
423 }
424 }
425 }
426# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
427
428 /*
429 * There is a handled area of the page, but this fault doesn't belong to it.
430 * We must emulate the instruction.
431 *
432 * To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
433 * we first check if this was a page-not-present fault for a page with only
434 * write access handlers. Restart the instruction if it wasn't a write access.
435 */
436 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
437
438 if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
439 && !(uErr & X86_TRAP_PF_P))
440 {
441 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
442 if ( VBOX_FAILURE(rc)
443 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
444 || !(uErr & X86_TRAP_PF_RW))
445 {
446 AssertRC(rc);
447 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
448 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
449 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
450 return rc;
451 }
452 }
453
454 /** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
455 * It's writing to an unhandled part of the LDT page several million times.
456 */
457 rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
458 LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
459 rc, pPage->HCPhys,
460 PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
461 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
462 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
463 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
464 return rc;
465 } /* if any kind of handler */
466
467# if PGM_WITH_PAGING(PGM_GST_TYPE)
468 if (uErr & X86_TRAP_PF_P)
469 {
470 /*
471 * The page isn't marked, but it might still be monitored by a virtual page access handler.
472 * (ASSUMES no temporary disabling of virtual handlers.)
473 */
474 /** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
475 * we should correct both the shadow page table and physical memory flags, and not only check for
476 * accesses within the handler region but for access to pages with virtual handlers. */
477 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
478 if (pCur)
479 {
480 AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
481 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
482 || !(uErr & X86_TRAP_PF_P)
483 || (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
484 ("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
485
486 if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
487 && ( uErr & X86_TRAP_PF_RW
488 || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
489 {
490# ifdef IN_GC
491 STAM_PROFILE_START(&pCur->Stat, h);
492 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
493 STAM_PROFILE_STOP(&pCur->Stat, h);
494# else
495 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
496# endif
497 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
498 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
499 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
500 return rc;
501 }
502 }
503 }
504# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
505 }
506 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
507
508# ifdef PGM_OUT_OF_SYNC_IN_GC
509 /*
510 * We are here only if page is present in Guest page tables and trap is not handled
511 * by our handlers.
512 * Check it for page out-of-sync situation.
513 */
514 STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
515
516 if (!(uErr & X86_TRAP_PF_P))
517 {
518 /*
519 * Page is not present in our page tables.
520 * Try to sync it!
521 * BTW, fPageShw is invalid in this branch!
522 */
523 if (uErr & X86_TRAP_PF_US)
524 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
525 else /* supervisor */
526 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
527
528# if defined(LOG_ENABLED) && !defined(IN_RING0)
529 RTGCPHYS GCPhys;
530 uint64_t fPageGst;
531 PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
532 Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
533 pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
534# endif /* LOG_ENABLED */
535
536# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
537 if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
538 {
539 uint64_t fPageGst;
540 rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
541 if ( VBOX_SUCCESS(rc)
542 && !(fPageGst & X86_PTE_US))
543 {
544 /* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
545 if ( pvFault == (RTGCPTR)pRegFrame->eip
546 || (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
547# ifdef CSAM_DETECT_NEW_CODE_PAGES
548 || ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
549 && CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
550# endif /* CSAM_DETECT_NEW_CODE_PAGES */
551 )
552 {
553 LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
554 rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
555 if (rc != VINF_SUCCESS)
556 {
557 /*
558 * CSAM needs to perform a job in ring 3.
559 *
560 * Sync the page before going to the host context; otherwise we'll end up in a loop if
561 * CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
562 */
563 LogFlow(("CSAM ring 3 job\n"));
564 int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
565 AssertRC(rc2);
566
567 STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
568 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
569 return rc;
570 }
571 }
572# ifdef CSAM_DETECT_NEW_CODE_PAGES
573 else
574 if ( uErr == X86_TRAP_PF_RW
575 && pRegFrame->ecx >= 0x100 /* early check for movswd count */
576 && pRegFrame->ecx < 0x10000
577 )
578 {
579 /* In case of a write to a non-present supervisor shadow page, we'll take special precautions
580 * to detect loading of new code pages.
581 */
582
583 /*
584 * Decode the instruction.
585 */
586 RTGCPTR PC;
587 rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
588 if (rc == VINF_SUCCESS)
589 {
590 DISCPUSTATE Cpu;
591 uint32_t cbOp;
592 rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
593
594 /* For now we'll restrict this to rep movsw/d instructions */
595 if ( rc == VINF_SUCCESS
596 && Cpu.pCurInstr->opcode == OP_MOVSWD
597 && (Cpu.prefix & PREFIX_REP))
598 {
599 CSAMMarkPossibleCodePage(pVM, pvFault);
600 }
601 }
602 }
603# endif /* CSAM_DETECT_NEW_CODE_PAGES */
604
605 /*
606 * Mark this page as safe.
607 */
608 /** @todo not correct for pages that contain both code and data!! */
609 Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
610 CSAMMarkPage(pVM, pvFault, true);
611 }
612 }
613# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
614 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
615 if (VBOX_SUCCESS(rc))
616 {
617 /* The page was successfully synced, return to the guest. */
618 STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
619 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
620 return VINF_SUCCESS;
621 }
622 }
623 else
624 {
625 /*
626 * A side effect of not flushing global PDEs are out of sync pages due
627 * to physical monitored regions, that are no longer valid.
628 * Assume for now it only applies to the read/write flag
629 */
630 if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
631 {
632 if (uErr & X86_TRAP_PF_US)
633 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
634 else /* supervisor */
635 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
636
637
638 /*
639 * Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
640 */
641 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
642 if (VBOX_SUCCESS(rc))
643 {
644 /*
645 * Page was successfully synced, return to guest.
646 */
647# ifdef VBOX_STRICT
648 RTGCPHYS GCPhys;
649 uint64_t fPageGst;
650 rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
651 Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
652 LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
653
654 uint64_t fPageShw;
655 rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
656 Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
657# endif /* VBOX_STRICT */
658 STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
659 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
660 return VINF_SUCCESS;
661 }
662 }
663
664# if PGM_WITH_PAGING(PGM_GST_TYPE)
665# ifdef VBOX_STRICT
666 /*
667 * Check for VMM page flags vs. Guest page flags consistency.
668 * Currently only for debug purposes.
669 */
670 if (VBOX_SUCCESS(rc))
671 {
672 /* Get guest page flags. */
673 uint64_t fPageGst;
674 rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
675 if (VBOX_SUCCESS(rc))
676 {
677 uint64_t fPageShw;
678 rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
679
680 /*
681 * Compare page flags.
682 * Note: we have AVL, A, D bits desynched.
683 */
684 AssertMsg((fPageShw & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK)),
685 ("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
686 }
687 else
688 AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
689 }
690 else
691 AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
692# endif /* VBOX_STRICT */
693# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
694 }
695 STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
696# endif /* PGM_OUT_OF_SYNC_IN_GC */
697 }
698 else
699 {
700 /*
701 * Page not present in Guest OS or invalid page table address.
702 * This is potential virtual page access handler food.
703 *
704 * For the present we'll say that our access handlers don't
705 * work for this case - we've already discarded the page table
706 * not present case which is identical to this.
707 *
708 * When we perchance find we need this, we will probably have AVL
709 * trees (offset based) to operate on and we can measure their speed
710 * agains mapping a page table and probably rearrange this handling
711 * a bit. (Like, searching virtual ranges before checking the
712 * physical address.)
713 */
714 }
715 }
716
717
718# if PGM_WITH_PAGING(PGM_GST_TYPE)
719 /*
720 * Conclusion, this is a guest trap.
721 */
722 LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
723 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
724 return VINF_EM_RAW_GUEST_TRAP;
725# else
726 /* present, but not a monitored page; perhaps the guest is probing physical memory */
727 return VINF_EM_RAW_EMULATE_INSTR;
728# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
729
730
731#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
732
733 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
734 return VERR_INTERNAL_ERROR;
735#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
736}
737
738
739/**
740 * Emulation of the invlpg instruction.
741 *
742 *
743 * @returns VBox status code.
744 *
745 * @param pVM VM handle.
746 * @param GCPtrPage Page to invalidate.
747 *
748 * @remark ASSUMES that the guest is updating before invalidating. This order
749 * isn't required by the CPU, so this is speculative and could cause
750 * trouble.
751 *
752 * @todo Flush page or page directory only if necessary!
753 * @todo Add a #define for simply invalidating the page.
754 */
755PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
756{
757#if PGM_GST_TYPE == PGM_TYPE_32BIT \
758 || PGM_GST_TYPE == PGM_TYPE_PAE
759
760 LogFlow(("InvalidatePage %x\n", GCPtrPage));
761# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE
762 /*
763 * Get the shadow PD entry and skip out if this PD isn't present.
764 * (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
765 */
766 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
767# if PGM_SHW_TYPE == PGM_TYPE_32BIT
768 PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
769# else
770 PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
771# endif
772 const SHWPDE PdeDst = *pPdeDst;
773 if (!PdeDst.n.u1Present)
774 {
775 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
776 return VINF_SUCCESS;
777 }
778
779 /*
780 * Get the guest PD entry and calc big page.
781 */
782# if PGM_GST_TYPE == PGM_TYPE_32BIT
783 PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
784 const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
785 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
786# else /* PAE */
787 unsigned iPDSrc;
788 PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
789 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
790# endif
791
792 const uint32_t cr4 = CPUMGetGuestCR4(pVM);
793 const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
794
795# ifdef IN_RING3
796 /*
797 * If a CR3 Sync is pending we may ignore the invalidate page operation
798 * depending on the kind of sync and if it's a global page or not.
799 * This doesn't make sense in GC/R0 so we'll skip it entirely there.
800 */
801# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
802 if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
803 || ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
804 && fIsBigPage
805 && PdeSrc.b.u1Global
806 && (cr4 & X86_CR4_PGE)
807 )
808 )
809# else
810 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
811# endif
812 {
813 STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
814 return VINF_SUCCESS;
815 }
816# endif /* IN_RING3 */
817
818
819 /*
820 * Deal with the Guest PDE.
821 */
822 int rc = VINF_SUCCESS;
823 if (PdeSrc.n.u1Present)
824 {
825 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
826 {
827 /*
828 * Conflict - Let SyncPT deal with it to avoid duplicate code.
829 */
830 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
831 Assert(PGMGetGuestMode(pVM) <= PGMMODE_32_BIT);
832 rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
833 }
834 else if ( PdeSrc.n.u1User != PdeDst.n.u1User
835 || (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
836 {
837 /*
838 * Mark not present so we can resync the PDE when it's used.
839 */
840 LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
841 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
842 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
843 pPdeDst->u = 0;
844 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
845 PGM_INVL_GUEST_TLBS();
846 }
847# ifdef PGM_SYNC_ACCESSED_BIT
848 else if (!PdeSrc.n.u1Accessed)
849 {
850 /*
851 * Mark not present so we can set the accessed bit.
852 */
853 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
854 pPdeDst->u = 0;
855 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
856 PGM_INVL_GUEST_TLBS();
857 }
858# endif
859 else if (!fIsBigPage)
860 {
861 /*
862 * 4KB - page.
863 */
864 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
865 RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
866# if PGM_SHW_TYPE != PGM_TYPE_32BIT
867 GCPhys |= (iPDDst & 1) * (PAGE_SIZE/2);
868# endif
869 if (pShwPage->GCPhys == GCPhys)
870 {
871#if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
872 const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
873 PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
874 if (pPT->a[iPTEDst].n.u1Present)
875 {
876# ifdef PGMPOOL_WITH_USER_TRACKING
877 /* This is very unlikely with caching/monitoring enabled. */
878 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
879# endif
880 pPT->a[iPTEDst].u = 0;
881 }
882#else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
883 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
884 if (VBOX_SUCCESS(rc))
885 rc = VINF_SUCCESS;
886#endif
887 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
888 PGM_INVL_PG(GCPtrPage);
889 }
890 else
891 {
892 /*
893 * The page table address changed.
894 */
895 LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
896 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
897 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
898 pPdeDst->u = 0;
899 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
900 PGM_INVL_GUEST_TLBS();
901 }
902 }
903 else
904 {
905 /*
906 * 4MB - page.
907 */
908 /* Before freeing the page, check if anything really changed. */
909 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
910 RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
911# if PGM_SHW_TYPE != PGM_TYPE_32BIT
912 GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
913# endif
914 if ( pShwPage->GCPhys == GCPhys
915 && pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
916 {
917 /* ASSUMES a the given bits are identical for 4M and normal PDEs */
918 /** @todo PAT */
919# ifdef PGM_SYNC_DIRTY_BIT
920 if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD))
921 == (PdeDst.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD))
922 && ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
923 || (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
924# else
925 if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD))
926 == (PdeDst.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD)))
927# endif
928 {
929 LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
930 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
931 return VINF_SUCCESS;
932 }
933 }
934
935 /*
936 * Ok, the page table is present and it's been changed in the guest.
937 * If we're in host context, we'll just mark it as not present taking the lazy approach.
938 * We could do this for some flushes in GC too, but we need an algorithm for
939 * deciding which 4MB pages containing code likely to be executed very soon.
940 */
941 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
942 pPdeDst->u = 0;
943 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
944 PGM_INVL_BIG_PG(GCPtrPage);
945 }
946 }
947 else
948 {
949 /*
950 * Page directory is not present, mark shadow PDE not present.
951 */
952 if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
953 {
954 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
955 pPdeDst->u = 0;
956 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
957 PGM_INVL_PG(GCPtrPage);
958 }
959 else
960 {
961 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
962 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
963 }
964 }
965
966 return rc;
967
968# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
969# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
970# endif
971 return VINF_SUCCESS;
972
973#elif PGM_GST_TYPE == PGM_TYPE_AMD64
974# if PGM_SHW_TYPE == PGM_TYPE_AMD64
975//# error not implemented
976 return VERR_INTERNAL_ERROR;
977
978# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
979# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
980# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
981
982#else /* guest real and protected mode */
983 /* There's no such thing when paging is disabled. */
984 return VINF_SUCCESS;
985#endif
986}
987
988
989#ifdef PGMPOOL_WITH_USER_TRACKING
990/**
991 * Update the tracking of shadowed pages.
992 *
993 * @param pVM The VM handle.
994 * @param pShwPage The shadow page.
995 * @param HCPhys The physical page we is being dereferenced.
996 */
997DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
998{
999# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1000 STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1001 LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1002
1003 /** @todo If this turns out to be a bottle neck (*very* likely) two things can be done:
1004 * 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1005 * 2. write protect all shadowed pages. I.e. implement caching.
1006 */
1007 /*
1008 * Find the guest address.
1009 */
1010 for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1011 pRam;
1012 pRam = CTXALLSUFF(pRam->pNext))
1013 {
1014 unsigned iPage = pRam->cb >> PAGE_SHIFT;
1015 while (iPage-- > 0)
1016 {
1017 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1018 {
1019 PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1020 pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1021 pShwPage->cPresent--;
1022 pPool->cPresent--;
1023 STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1024 return;
1025 }
1026 }
1027 }
1028
1029 for (;;)
1030 AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1031# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1032 pShwPage->cPresent--;
1033 pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1034# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1035}
1036
1037
1038/**
1039 * Update the tracking of shadowed pages.
1040 *
1041 * @param pVM The VM handle.
1042 * @param pShwPage The shadow page.
1043 * @param u16 The top 16-bit of the pPage->HCPhys.
1044 * @param pPage Pointer to the guest page. this will be modified.
1045 * @param iPTDst The index into the shadow table.
1046 */
1047DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1048{
1049# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1050 /*
1051 * We're making certain assumptions about the placement of cRef and idx.
1052 */
1053 Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1054 Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1055
1056 /*
1057 * Just deal with the simple first time here.
1058 */
1059 if (!u16)
1060 {
1061 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1062 u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) | pShwPage->idx;
1063 }
1064 else
1065 u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1066
1067 /* write back, trying to be clever... */
1068 Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1069 u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) | ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1070 *((uint16_t *)&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1071# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1072
1073 /* update statistics. */
1074 pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1075 pShwPage->cPresent++;
1076 if (pShwPage->iFirstPresent > iPTDst)
1077 pShwPage->iFirstPresent = iPTDst;
1078}
1079#endif /* PGMPOOL_WITH_USER_TRACKING */
1080
1081
1082/**
1083 * Creates a 4K shadow page for a guest page.
1084 *
1085 * For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1086 * physical address. The PdeSrc argument only the flags are used. No page structured
1087 * will be mapped in this function.
1088 *
1089 * @param pVM VM handle.
1090 * @param pPteDst Destination page table entry.
1091 * @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1092 * Can safely assume that only the flags are being used.
1093 * @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1094 * @param pShwPage Pointer to the shadow page.
1095 * @param iPTDst The index into the shadow table.
1096 *
1097 * @remark Not used for 2/4MB pages!
1098 */
1099DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1100{
1101 if (PteSrc.n.u1Present)
1102 {
1103 /*
1104 * Find the ram range.
1105 */
1106 PPGMPAGE pPage;
1107 int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1108 if (VBOX_SUCCESS(rc))
1109 {
1110 /** @todo investiage PWT, PCD and PAT. */
1111 /*
1112 * Make page table entry.
1113 */
1114 const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1115 SHWPTE PteDst;
1116 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1117 {
1118 /** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1119 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1120 PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
1121 | (HCPhys & X86_PTE_PAE_PG_MASK);
1122 else
1123 {
1124 LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1125 PteDst.u = 0;
1126 }
1127 /** @todo count these two kinds. */
1128 }
1129 else
1130 {
1131#ifdef PGM_SYNC_DIRTY_BIT
1132# ifdef PGM_SYNC_ACCESSED_BIT
1133 /*
1134 * If the page or page directory entry is not marked accessed,
1135 * we mark the page not present.
1136 */
1137 if (!PteSrc.n.u1Accessed || !PdeSrc.n.u1Accessed)
1138 {
1139 LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1140 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1141 PteDst.u = 0;
1142 }
1143 else
1144# endif
1145 /*
1146 * If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1147 * when the page is modified.
1148 */
1149 if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1150 {
1151 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1152 PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
1153 | (HCPhys & X86_PTE_PAE_PG_MASK)
1154 | PGM_PTFLAGS_TRACK_DIRTY;
1155 }
1156 else
1157 {
1158 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1159 PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
1160 | (HCPhys & X86_PTE_PAE_PG_MASK);
1161 }
1162#endif
1163 }
1164
1165#ifdef PGMPOOL_WITH_USER_TRACKING
1166 /*
1167 * Keep user track up to date.
1168 */
1169 if (PteDst.n.u1Present)
1170 {
1171 if (!pPteDst->n.u1Present)
1172 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1173 else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1174 {
1175 Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1176 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1177 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1178 }
1179 }
1180 else if (pPteDst->n.u1Present)
1181 {
1182 Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1183 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1184 }
1185#endif /* PGMPOOL_WITH_USER_TRACKING */
1186
1187 /*
1188 * Update statistics and commit the entry.
1189 */
1190 if (!PteSrc.n.u1Global)
1191 pShwPage->fSeenNonGlobal = true;
1192 *pPteDst = PteDst;
1193 }
1194 /* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1195 /** @todo count these. */
1196 }
1197 else
1198 {
1199 /*
1200 * Page not-present.
1201 */
1202 LogFlow(("SyncPageWorker: page not present in Pte\n"));
1203#ifdef PGMPOOL_WITH_USER_TRACKING
1204 /* Keep user track up to date. */
1205 if (pPteDst->n.u1Present)
1206 {
1207 Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1208 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1209 }
1210#endif /* PGMPOOL_WITH_USER_TRACKING */
1211 pPteDst->u = 0;
1212 /** @todo count these. */
1213 }
1214}
1215
1216
1217/**
1218 * Syncs a guest OS page.
1219 *
1220 * There are no conflicts at this point, neither is there any need for
1221 * page table allocations.
1222 *
1223 * @returns VBox status code.
1224 * @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1225 * @param pVM VM handle.
1226 * @param PdeSrc Page directory entry of the guest.
1227 * @param GCPtrPage Guest context page address.
1228 * @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1229 * @param uErr Fault error (X86_TRAP_PF_*).
1230 */
1231PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1232{
1233 LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1234
1235#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1236 || PGM_GST_TYPE == PGM_TYPE_PAE
1237
1238# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1239# error "Invalid shadow mode for 32-bit guest mode!"
1240# endif
1241
1242 /*
1243 * Assert preconditions.
1244 */
1245 STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & GST_PD_MASK]);
1246 Assert(PdeSrc.n.u1Present);
1247 Assert(cPages);
1248
1249 /*
1250 * Get the shadow PDE, find the shadow page table in the pool.
1251 */
1252 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1253# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1254 X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1255# else /* PAE */
1256 X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1257# endif
1258 Assert(PdeDst.n.u1Present);
1259 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1260
1261 /*
1262 * Check that the page is present and that the shadow PDE isn't out of sync.
1263 */
1264 const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1265 RTGCPHYS GCPhys;
1266 if (!fBigPage)
1267 {
1268 GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1269# if PGM_SHW_TYPE != PGM_TYPE_32BIT
1270 GCPhys |= (iPDDst & 1) * (PAGE_SIZE/2);
1271# endif
1272 }
1273 else
1274 {
1275 GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1276# if PGM_SHW_TYPE != PGM_TYPE_32BIT
1277 GCPhys |= GCPtrPage & X86_PAGE_2M_SIZE;
1278# endif
1279 }
1280 if ( pShwPage->GCPhys == GCPhys
1281 && PdeSrc.n.u1Present
1282 && (PdeSrc.n.u1User == PdeDst.n.u1User)
1283 && (PdeSrc.n.u1Write == PdeDst.n.u1Write || !PdeDst.n.u1Write)
1284# if PGM_GST_TYPE == PGM_TYPE_PAE
1285 && (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1286# endif
1287 )
1288 {
1289# ifdef PGM_SYNC_ACCESSED_BIT
1290 /*
1291 * Check that the PDE is marked accessed already.
1292 * Since we set the accessed bit *before* getting here on a #PF, this
1293 * check is only meant for dealing with non-#PF'ing paths.
1294 */
1295 if (PdeSrc.n.u1Accessed)
1296# endif
1297 {
1298 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1299 if (!fBigPage)
1300 {
1301 /*
1302 * 4KB Page - Map the guest page table.
1303 */
1304 PGSTPT pPTSrc;
1305 int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1306 if (VBOX_SUCCESS(rc))
1307 {
1308# ifdef PGM_SYNC_N_PAGES
1309 Assert(cPages == 1 || !(uErr & X86_TRAP_PF_P));
1310 if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1311 {
1312 /*
1313 * This code path is currently only taken when the caller is PGMTrap0eHandler
1314 * for non-present pages!
1315 *
1316 * We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1317 * deal with locality.
1318 */
1319 unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1320# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1321 const unsigned offPTSrc = 0;
1322# else
1323 const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1324# endif
1325 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1326 if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1327 iPTDst = 0;
1328 else
1329 iPTDst -= PGM_SYNC_NR_PAGES / 2;
1330 for (; iPTDst < iPTDstEnd; iPTDst++)
1331 {
1332 if (!pPTDst->a[iPTDst].n.u1Present)
1333 {
1334 GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1335 RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
1336 NOREF(GCPtrCurPage);
1337#ifndef IN_RING0
1338 /*
1339 * Assuming kernel code will be marked as supervisor - and not as user level
1340 * and executed using a conforming code selector - And marked as readonly.
1341 * Also assume that if we're monitoring a page, it's of no interest to CSAM.
1342 */
1343 PPGMPAGE pPage;
1344 if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW | X86_PTE_US))
1345 || iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1346 || !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1347 || ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1348 && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1349 )
1350#endif /* else: CSAM not active */
1351 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1352 Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1353 GCPtrCurPage, PteSrc.n.u1Present,
1354 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1355 PteSrc.n.u1User & PdeSrc.n.u1User,
1356 (uint64_t)PteSrc.u,
1357 (uint64_t)pPTDst->a[iPTDst].u,
1358 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1359 }
1360 }
1361 }
1362 else
1363# endif /* PGM_SYNC_N_PAGES */
1364 {
1365 const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1366 GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1367 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1368 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1369 Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1370 GCPtrPage, PteSrc.n.u1Present,
1371 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1372 PteSrc.n.u1User & PdeSrc.n.u1User,
1373 (uint64_t)PteSrc.u,
1374 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1375 }
1376 }
1377 else /* MMIO or invalid page: emulated in #PF handler. */
1378 {
1379 LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1380 Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1381 }
1382 }
1383 else
1384 {
1385 /*
1386 * 4/2MB page - lazy syncing shadow 4K pages.
1387 * (There are many causes of getting here, it's no longer only CSAM.)
1388 */
1389 /* Calculate the GC physical address of this 4KB shadow page. */
1390 RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) | ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1391 /* Find ram range. */
1392 PPGMPAGE pPage;
1393 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1394 if (VBOX_SUCCESS(rc))
1395 {
1396 /*
1397 * Make shadow PTE entry.
1398 */
1399 const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1400 SHWPTE PteDst;
1401 PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
1402 | (HCPhys & X86_PTE_PAE_PG_MASK);
1403 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1404 {
1405 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1406 PteDst.n.u1Write = 0;
1407 else
1408 PteDst.u = 0;
1409 }
1410 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1411# ifdef PGMPOOL_WITH_USER_TRACKING
1412 if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1413 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1414# endif
1415 pPTDst->a[iPTDst] = PteDst;
1416
1417
1418# ifdef PGM_SYNC_DIRTY_BIT
1419 /*
1420 * If the page is not flagged as dirty and is writable, then make it read-only
1421 * at PD level, so we can set the dirty bit when the page is modified.
1422 *
1423 * ASSUMES that page access handlers are implemented on page table entry level.
1424 * Thus we will first catch the dirty access and set PDE.D and restart. If
1425 * there is an access handler, we'll trap again and let it work on the problem.
1426 */
1427 /** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1428 * As for invlpg, it simply frees the whole shadow PT.
1429 * ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1430 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1431 {
1432 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1433 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
1434 PdeDst.n.u1Write = 0;
1435 }
1436 else
1437 {
1438 PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1439 PdeDst.n.u1Write = PdeSrc.n.u1Write;
1440 }
1441# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1442 pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1443# else /* PAE */
1444 pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1445# endif
1446# endif /* PGM_SYNC_DIRTY_BIT */
1447 Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1448 GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1449 PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1450 }
1451 else
1452 LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1453 }
1454 return VINF_SUCCESS;
1455 }
1456# ifdef PGM_SYNC_ACCESSED_BIT
1457 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1458#endif
1459 }
1460 else
1461 {
1462 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1463 Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1464 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1465 }
1466
1467 /*
1468 * Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1469 * Yea, I'm lazy.
1470 */
1471 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1472# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1473 pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1474# else /* PAE */
1475 pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1476# endif
1477 PGM_INVL_GUEST_TLBS();
1478 return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1479
1480#elif PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT
1481
1482# ifdef PGM_SYNC_N_PAGES
1483 /*
1484 * Get the shadow PDE, find the shadow page table in the pool.
1485 */
1486 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1487# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1488 X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1489# else /* PAE */
1490 X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1491# endif
1492 Assert(PdeDst.n.u1Present);
1493 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1494 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1495
1496# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1497 const unsigned offPTSrc = 0;
1498# else
1499 const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1500# endif
1501
1502 Assert(cPages == 1 || !(uErr & X86_TRAP_PF_P));
1503 if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1504 {
1505 /*
1506 * This code path is currently only taken when the caller is PGMTrap0eHandler
1507 * for non-present pages!
1508 *
1509 * We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1510 * deal with locality.
1511 */
1512 unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1513 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1514 if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1515 iPTDst = 0;
1516 else
1517 iPTDst -= PGM_SYNC_NR_PAGES / 2;
1518 for (; iPTDst < iPTDstEnd; iPTDst++)
1519 {
1520 if (!pPTDst->a[iPTDst].n.u1Present)
1521 {
1522 GSTPTE PteSrc;
1523
1524 RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
1525
1526 /* Fake the page table entry */
1527 PteSrc.u = GCPtrCurPage;
1528 PteSrc.n.u1Present = 1;
1529 PteSrc.n.u1Dirty = 1;
1530 PteSrc.n.u1Accessed = 1;
1531 PteSrc.n.u1Write = 1;
1532 PteSrc.n.u1User = 1;
1533
1534 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1535
1536 Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1537 GCPtrCurPage, PteSrc.n.u1Present,
1538 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1539 PteSrc.n.u1User & PdeSrc.n.u1User,
1540 (uint64_t)PteSrc.u,
1541 (uint64_t)pPTDst->a[iPTDst].u,
1542 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1543 }
1544 }
1545 }
1546 else
1547# endif /* PGM_SYNC_N_PAGES */
1548 {
1549 GSTPTE PteSrc;
1550 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1551 RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
1552
1553 /* Fake the page table entry */
1554 PteSrc.u = GCPtrCurPage;
1555 PteSrc.n.u1Present = 1;
1556 PteSrc.n.u1Dirty = 1;
1557 PteSrc.n.u1Accessed = 1;
1558 PteSrc.n.u1Write = 1;
1559 PteSrc.n.u1User = 1;
1560 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1561
1562 Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1563 GCPtrPage, PteSrc.n.u1Present,
1564 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1565 PteSrc.n.u1User & PdeSrc.n.u1User,
1566 (uint64_t)PteSrc.u,
1567 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1568 }
1569 return VINF_SUCCESS;
1570
1571#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1572 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1573 return VERR_INTERNAL_ERROR;
1574#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1575}
1576
1577
1578
1579#if PGM_WITH_PAGING(PGM_GST_TYPE)
1580
1581# ifdef PGM_SYNC_DIRTY_BIT
1582
1583/**
1584 * Investigate page fault and handle write protection page faults caused by
1585 * dirty bit tracking.
1586 *
1587 * @returns VBox status code.
1588 * @param pVM VM handle.
1589 * @param uErr Page fault error code.
1590 * @param pPdeDst Shadow page directory entry.
1591 * @param pPdeSrc Guest page directory entry.
1592 * @param GCPtrPage Guest context page address.
1593 */
1594PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1595{
1596 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1597 LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1598
1599 /*
1600 * Real page fault?
1601 */
1602 if ( (uErr & X86_TRAP_PF_RSVD)
1603 || !pPdeSrc->n.u1Present
1604# if PGM_WITH_NX(PGM_GST_TYPE)
1605 || ((uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1606# endif
1607 || ((uErr & X86_TRAP_PF_RW) && !pPdeSrc->n.u1Write)
1608 || ((uErr & X86_TRAP_PF_US) && !pPdeSrc->n.u1User) )
1609 {
1610# ifdef IN_GC
1611 STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1612# endif
1613 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1614 LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1615
1616 if (pPdeSrc->n.u1Present)
1617 {
1618 /* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1619 * See the 2nd case below as well.
1620 */
1621 if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1622 {
1623 TRPMSetErrorCode(pVM, uErr | X86_TRAP_PF_P); /* page-level protection violation */
1624 }
1625 else
1626 {
1627 /*
1628 * Map the guest page table.
1629 */
1630 PGSTPT pPTSrc;
1631 int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1632 if (VBOX_SUCCESS(rc))
1633 {
1634 PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & GST_PT_MASK];
1635 const GSTPTE PteSrc = *pPteSrc;
1636 if (pPteSrc->n.u1Present)
1637 TRPMSetErrorCode(pVM, uErr | X86_TRAP_PF_P); /* page-level protection violation */
1638 }
1639 AssertRC(rc);
1640 }
1641 }
1642 return VINF_EM_RAW_GUEST_TRAP;
1643 }
1644
1645 /*
1646 * First check the easy case where the page directory has been marked read-only to track
1647 * the dirty bit of an emulated BIG page
1648 */
1649 if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1650 {
1651 /* Mark guest page directory as accessed */
1652 pPdeSrc->b.u1Accessed = 1;
1653
1654 /*
1655 * Only write protection page faults are relevant here.
1656 */
1657 if (uErr & X86_TRAP_PF_RW)
1658 {
1659 /* Mark guest page directory as dirty (BIG page only). */
1660 pPdeSrc->b.u1Dirty = 1;
1661
1662 if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1663 {
1664 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1665
1666 Assert(pPdeSrc->b.u1Write);
1667
1668 pPdeDst->n.u1Write = 1;
1669 pPdeDst->n.u1Accessed = 1;
1670 pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1671 PGM_INVL_BIG_PG(GCPtrPage);
1672 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1673 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1674 }
1675 }
1676 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1677 return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1678 }
1679 /* else: 4KB page table */
1680
1681 /*
1682 * Map the guest page table.
1683 */
1684 PGSTPT pPTSrc;
1685 int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1686 if (VBOX_SUCCESS(rc))
1687 {
1688 /*
1689 * Real page fault?
1690 */
1691 PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & GST_PT_MASK];
1692 const GSTPTE PteSrc = *pPteSrc;
1693 if ( !PteSrc.n.u1Present
1694# if PGM_WITH_NX(PGM_GST_TYPE)
1695 || ((uErr & X86_TRAP_PF_ID) && !PteSrc.n.u1NoExecute)
1696# endif
1697 || ((uErr & X86_TRAP_PF_RW) && !PteSrc.n.u1Write)
1698 || ((uErr & X86_TRAP_PF_US) && !PteSrc.n.u1User)
1699 )
1700 {
1701# ifdef IN_GC
1702 STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1703# endif
1704 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1705 LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1706
1707 /* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1708 * See the 2nd case above as well.
1709 */
1710 if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1711 TRPMSetErrorCode(pVM, uErr | X86_TRAP_PF_P); /* page-level protection violation */
1712
1713 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1714 return VINF_EM_RAW_GUEST_TRAP;
1715 }
1716 LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1717
1718 /*
1719 * Set the accessed bits in the page directory and the page table.
1720 */
1721 pPdeSrc->n.u1Accessed = 1;
1722 pPteSrc->n.u1Accessed = 1;
1723
1724 /*
1725 * Only write protection page faults are relevant here.
1726 */
1727 if (uErr & X86_TRAP_PF_RW)
1728 {
1729 /* Write access, so mark guest entry as dirty. */
1730# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1731 if (!pPteSrc->n.u1Dirty)
1732 STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1733 else
1734 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1735# endif
1736 pPteSrc->n.u1Dirty = 1;
1737
1738 if (pPdeDst->n.u1Present)
1739 {
1740 /* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1741 * Our individual shadow handlers will provide more information and force a fatal exit.
1742 */
1743 if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1744 {
1745 LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1746 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1747 return VINF_SUCCESS;
1748 }
1749
1750 /*
1751 * Map shadow page table.
1752 */
1753 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1754 if (pShwPage)
1755 {
1756 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1757 PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1758 if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1759 && (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1760 {
1761 LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1762# ifdef VBOX_STRICT
1763 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
1764 if (pPage)
1765 AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
1766 ("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1767# endif
1768 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1769
1770 Assert(pPteSrc->n.u1Write);
1771
1772 pPteDst->n.u1Write = 1;
1773 pPteDst->n.u1Dirty = 1;
1774 pPteDst->n.u1Accessed = 1;
1775 pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1776 PGM_INVL_PG(GCPtrPage);
1777
1778 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1779 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1780 }
1781 }
1782 else
1783 AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1784 }
1785 }
1786/** @todo Optimize accessed bit emulation? */
1787# ifdef VBOX_STRICT
1788 /*
1789 * Sanity check.
1790 */
1791 else if ( !pPteSrc->n.u1Dirty
1792 && (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1793 && pPdeDst->n.u1Present)
1794 {
1795 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1796 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1797 PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1798 if ( pPteDst->n.u1Present
1799 && pPteDst->n.u1Write)
1800 LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1801 }
1802# endif /* VBOX_STRICT */
1803 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1804 return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1805 }
1806 AssertRC(rc);
1807 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1808 return rc;
1809}
1810
1811# endif
1812
1813#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1814
1815
1816/**
1817 * Sync a shadow page table.
1818 *
1819 * The shadow page table is not present. This includes the case where
1820 * there is a conflict with a mapping.
1821 *
1822 * @returns VBox status code.
1823 * @param pVM VM handle.
1824 * @param iPD Page directory index.
1825 * @param pPDSrc Source page directory (i.e. Guest OS page directory).
1826 * Assume this is a temporary mapping.
1827 * @param GCPtrPage GC Pointer of the page that caused the fault
1828 */
1829PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
1830{
1831 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1832 STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1833 LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1834
1835#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1836 || PGM_GST_TYPE == PGM_TYPE_PAE
1837
1838# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1839# error "Invalid shadow mode for 32-bit guest mode!"
1840# endif
1841
1842 /*
1843 * Validate input a little bit.
1844 */
1845 Assert(iPDSrc == (GCPtrPage >> GST_PD_SHIFT));
1846# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1847 PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1848# else
1849 PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1850# endif
1851 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1852 PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1853 SHWPDE PdeDst = *pPdeDst;
1854
1855# if PGM_GST_TYPE == PGM_TYPE_32BIT
1856 /*
1857 * Check for conflicts.
1858 * GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1859 * HC: Simply resolve the conflict.
1860 */
1861 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1862 {
1863 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1864# ifndef IN_RING3
1865 Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1866 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1867 return VERR_ADDRESS_CONFLICT;
1868# else
1869 PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1870 Assert(pMapping);
1871 int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPDSrc);
1872 if (VBOX_FAILURE(rc))
1873 {
1874 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1875 return rc;
1876 }
1877 PdeDst = *pPdeDst;
1878# endif
1879 }
1880# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1881 /* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
1882 Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
1883# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1884 Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1885
1886 /*
1887 * Sync page directory entry.
1888 */
1889 int rc = VINF_SUCCESS;
1890 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1891 if (PdeSrc.n.u1Present)
1892 {
1893 /*
1894 * Allocate & map the page table.
1895 */
1896 PSHWPT pPTDst;
1897 const bool fPageTable = !PdeSrc.b.u1Size || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1898 PPGMPOOLPAGE pShwPage;
1899 RTGCPHYS GCPhys;
1900 if (fPageTable)
1901 {
1902 GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1903# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1904 GCPhys |= (iPDDst & 1) * (PAGE_SIZE / 2);
1905# endif
1906 rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1907 }
1908 else
1909 {
1910 GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1911# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1912 GCPhys |= GCPtrPage & RT_BIT(X86_PAGE_2M_SHIFT);
1913# endif
1914 rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1915 }
1916 if (rc == VINF_SUCCESS)
1917 pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1918 else if (rc == VINF_PGM_CACHED_PAGE)
1919 {
1920 /*
1921 * The PT was cached, just hook it up.
1922 */
1923 if (fPageTable)
1924 PdeDst.u = pShwPage->Core.Key
1925 | (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
1926 else
1927 {
1928 PdeDst.u = pShwPage->Core.Key
1929 | (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
1930# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumtions further down.) */
1931 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1932 {
1933 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1934 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
1935 PdeDst.b.u1Write = 0;
1936 }
1937# endif
1938 }
1939 *pPdeDst = PdeDst;
1940 return VINF_SUCCESS;
1941 }
1942 else if (rc == VERR_PGM_POOL_FLUSHED)
1943 return VINF_PGM_SYNC_CR3;
1944 else
1945 AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
1946 PdeDst.u &= X86_PDE_AVL_MASK;
1947 PdeDst.u |= pShwPage->Core.Key;
1948
1949# ifdef PGM_SYNC_DIRTY_BIT
1950 /*
1951 * Page directory has been accessed (this is a fault situation, remember).
1952 */
1953 pPDSrc->a[iPDSrc].n.u1Accessed = 1;
1954# endif
1955 if (fPageTable)
1956 {
1957 /*
1958 * Page table - 4KB.
1959 *
1960 * Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
1961 */
1962 Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
1963 GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
1964 PGSTPT pPTSrc;
1965 rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1966 if (VBOX_SUCCESS(rc))
1967 {
1968 /*
1969 * Start by syncing the page directory entry so CSAM's TLB trick works.
1970 */
1971 PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK))
1972 | (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
1973 *pPdeDst = PdeDst;
1974
1975 /*
1976 * Directory/page user or supervisor privilege: (same goes for read/write)
1977 *
1978 * Directory Page Combined
1979 * U/S U/S U/S
1980 * 0 0 0
1981 * 0 1 0
1982 * 1 0 0
1983 * 1 1 1
1984 *
1985 * Simple AND operation. Table listed for completeness.
1986 *
1987 */
1988 STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
1989# ifdef PGM_SYNC_N_PAGES
1990 unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1991 unsigned iPTDst = iPTBase;
1992 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1993 if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
1994 iPTDst = 0;
1995 else
1996 iPTDst -= PGM_SYNC_NR_PAGES / 2;
1997# else /* !PGM_SYNC_N_PAGES */
1998 unsigned iPTDst = 0;
1999 const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2000# endif /* !PGM_SYNC_N_PAGES */
2001# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2002 const unsigned offPTSrc = 0;
2003# else
2004 const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2005# endif
2006 for (; iPTDst < iPTDstEnd; iPTDst++)
2007 {
2008 const unsigned iPTSrc = iPTDst + offPTSrc;
2009 const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2010
2011 if (PteSrc.n.u1Present) /* we've already cleared it above */
2012 {
2013#ifndef IN_RING0
2014 /*
2015 * Assuming kernel code will be marked as supervisor - and not as user level
2016 * and executed using a conforming code selector - And marked as readonly.
2017 * Also assume that if we're monitoring a page, it's of no interest to CSAM.
2018 */
2019 PPGMPAGE pPage;
2020 if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW | X86_PTE_US))
2021 || !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) | (iPTSrc << PAGE_SHIFT)))
2022 || ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2023 && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2024 )
2025#endif
2026 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2027 Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2028 (RTGCPTR)((iPDSrc << GST_PD_SHIFT) | (iPTSrc << PAGE_SHIFT)),
2029 PteSrc.n.u1Present,
2030 PteSrc.n.u1Write & PdeSrc.n.u1Write,
2031 PteSrc.n.u1User & PdeSrc.n.u1User,
2032 (uint64_t)PteSrc.u,
2033 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2034 (PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2035 }
2036 } /* for PTEs */
2037 }
2038 }
2039 else
2040 {
2041 /*
2042 * Big page - 2/4MB.
2043 *
2044 * We'll walk the ram range list in parallel and optimize lookups.
2045 * We will only sync on shadow page table at a time.
2046 */
2047 STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2048
2049 /**
2050 * @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2051 */
2052
2053 /*
2054 * Start by syncing the page directory entry.
2055 */
2056 PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK | (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2057 | (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
2058
2059# ifdef PGM_SYNC_DIRTY_BIT
2060 /*
2061 * If the page is not flagged as dirty and is writable, then make it read-only
2062 * at PD level, so we can set the dirty bit when the page is modified.
2063 *
2064 * ASSUMES that page access handlers are implemented on page table entry level.
2065 * Thus we will first catch the dirty access and set PDE.D and restart. If
2066 * there is an access handler, we'll trap again and let it work on the problem.
2067 */
2068 /** @todo move the above stuff to a section in the PGM documentation. */
2069 Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2070 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2071 {
2072 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2073 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
2074 PdeDst.b.u1Write = 0;
2075 }
2076# endif /* PGM_SYNC_DIRTY_BIT */
2077 *pPdeDst = PdeDst;
2078
2079 /*
2080 * Fill the shadow page table.
2081 */
2082 /* Get address and flags from the source PDE. */
2083 SHWPTE PteDstBase;
2084 PteDstBase.u = PdeSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT);
2085
2086 /* Loop thru the entries in the shadow PT. */
2087 const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2088 Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2089 GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2090 GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2091 PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2092 unsigned iPTDst = 0;
2093 while (iPTDst < ELEMENTS(pPTDst->a))
2094 {
2095 /* Advance ram range list. */
2096 while (pRam && GCPhys > pRam->GCPhysLast)
2097 pRam = CTXALLSUFF(pRam->pNext);
2098 if (pRam && GCPhys >= pRam->GCPhys)
2099 {
2100 unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2101 do
2102 {
2103 /* Make shadow PTE. */
2104 PPGMPAGE pPage = &pRam->aPages[iHCPage];
2105 SHWPTE PteDst;
2106
2107 /* Make sure the RAM has already been allocated. */
2108 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2109 {
2110 if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2111 {
2112# ifdef IN_RING3
2113 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2114# else
2115 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2116# endif
2117 if (rc != VINF_SUCCESS)
2118 return rc;
2119 }
2120 }
2121
2122 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2123 {
2124 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2125 {
2126 PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) | PteDstBase.u;
2127 PteDst.n.u1Write = 0;
2128 }
2129 else
2130 PteDst.u = 0;
2131 }
2132# ifndef IN_RING0
2133 /*
2134 * Assuming kernel code will be marked as supervisor and not as user level and executed
2135 * using a conforming code selector. Don't check for readonly, as that implies the whole
2136 * 4MB can be code or readonly data. Linux enables write access for its large pages.
2137 */
2138 else if ( !PdeSrc.n.u1User
2139 && CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT))))
2140 PteDst.u = 0;
2141# endif
2142 else
2143 PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) | PteDstBase.u;
2144# ifdef PGMPOOL_WITH_USER_TRACKING
2145 if (PteDst.n.u1Present)
2146 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2147# endif
2148 /* commit it */
2149 pPTDst->a[iPTDst] = PteDst;
2150 Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2151 (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2152 PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2153
2154 /* advance */
2155 GCPhys += PAGE_SIZE;
2156 iHCPage++;
2157 iPTDst++;
2158 } while ( iPTDst < ELEMENTS(pPTDst->a)
2159 && GCPhys <= pRam->GCPhysLast);
2160 }
2161 else if (pRam)
2162 {
2163 Log(("Invalid pages at %VGp\n", GCPhys));
2164 do
2165 {
2166 pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2167 GCPhys += PAGE_SIZE;
2168 iPTDst++;
2169 } while ( iPTDst < ELEMENTS(pPTDst->a)
2170 && GCPhys < pRam->GCPhys);
2171 }
2172 else
2173 {
2174 Log(("Invalid pages at %VGp (2)\n", GCPhys));
2175 for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2176 pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2177 }
2178 } /* while more PTEs */
2179 } /* 4KB / 4MB */
2180 }
2181 else
2182 AssertRelease(!PdeDst.n.u1Present);
2183
2184 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2185# ifdef IN_GC
2186 if (VBOX_FAILURE(rc))
2187 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2188# endif
2189 return rc;
2190
2191#elif PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT
2192
2193 int rc = VINF_SUCCESS;
2194
2195 /*
2196 * Validate input a little bit.
2197 */
2198# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2199 PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2200# else
2201 PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2202# endif
2203 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2204 PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2205 SHWPDE PdeDst = *pPdeDst;
2206
2207 Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2208 Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2209
2210 GSTPDE PdeSrc;
2211 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2212 PdeSrc.n.u1Present = 1;
2213 PdeSrc.n.u1Write = 1;
2214 PdeSrc.n.u1Accessed = 1;
2215 PdeSrc.n.u1User = 1;
2216
2217 /*
2218 * Allocate & map the page table.
2219 */
2220 PSHWPT pPTDst;
2221 PPGMPOOLPAGE pShwPage;
2222 RTGCPHYS GCPhys;
2223
2224 /* Virtual address = physical address */
2225 GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2226 rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2227
2228 if ( rc == VINF_SUCCESS
2229 || rc == VINF_PGM_CACHED_PAGE)
2230 pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2231 else
2232 AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2233
2234 PdeDst.u &= X86_PDE_AVL_MASK;
2235 PdeDst.u |= pShwPage->Core.Key;
2236 PdeDst.n.u1Present = 1;
2237 *pPdeDst = PdeDst;
2238
2239 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2240 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2241 return rc;
2242
2243#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2244
2245 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2246 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2247 return VERR_INTERNAL_ERROR;
2248#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2249}
2250
2251
2252
2253/**
2254 * Prefetch a page/set of pages.
2255 *
2256 * Typically used to sync commonly used pages before entering raw mode
2257 * after a CR3 reload.
2258 *
2259 * @returns VBox status code.
2260 * @param pVM VM handle.
2261 * @param GCPtrPage Page to invalidate.
2262 */
2263PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2264{
2265#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2266
2267# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2268# error "Invalid shadow mode for 32-bit guest mode!"
2269# endif
2270
2271 /*
2272 * Check that all Guest levels thru the PDE are present, getting the
2273 * PD and PDE in the processes.
2274 */
2275 int rc = VINF_SUCCESS;
2276# if PGM_WITH_PAGING(PGM_GST_TYPE)
2277# if PGM_GST_TYPE == PGM_TYPE_32BIT
2278 const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2279 PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2280# else /* PAE */
2281 unsigned iPDSrc
2282 PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2283# endif
2284# else
2285 PGSTPD pPDSrc = NULL;
2286 const unsigned iPDSrc = 0;
2287# endif
2288
2289# if PGM_WITH_PAGING(PGM_GST_TYPE)
2290 const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2291# else
2292 GSTPDE PdeSrc;
2293 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2294 PdeSrc.n.u1Present = 1;
2295 PdeSrc.n.u1Write = 1;
2296 PdeSrc.n.u1Accessed = 1;
2297 PdeSrc.n.u1User = 1;
2298# endif
2299
2300# ifdef PGM_SYNC_ACCESSED_BIT
2301 if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2302# else
2303 if (PdeSrc.n.u1Present)
2304# endif
2305 {
2306# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2307 const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2308# else
2309 const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2310# endif
2311 if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2312 {
2313 if (!PdeDst.n.u1Present)
2314 /** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2315 rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2316 else
2317 {
2318 /** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2319 * R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2320 * makes no sense to prefetch more than one page.
2321 */
2322 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2323 if (VBOX_SUCCESS(rc))
2324 rc = VINF_SUCCESS;
2325 }
2326 }
2327 }
2328 return rc;
2329
2330#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2331
2332 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2333 return VERR_INTERNAL_ERROR;
2334#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2335}
2336
2337
2338
2339
2340/**
2341 * Syncs a page during a PGMVerifyAccess() call.
2342 *
2343 * @returns VBox status code (informational included).
2344 * @param GCPtrPage The address of the page to sync.
2345 * @param fPage The effective guest page flags.
2346 * @param uErr The trap error code.
2347 */
2348PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2349{
2350 LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2351
2352#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT || PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2353
2354# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2355# error "Invalid shadow mode for 32-bit guest mode!"
2356# endif
2357
2358#ifndef IN_RING0
2359 if (!(fPage & X86_PTE_US))
2360 {
2361 /*
2362 * Mark this page as safe.
2363 */
2364 /** @todo not correct for pages that contain both code and data!! */
2365 Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2366 CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2367 }
2368#endif
2369 /*
2370 * Get guest PD and index.
2371 */
2372
2373# if PGM_WITH_PAGING(PGM_GST_TYPE)
2374# if PGM_GST_TYPE == PGM_TYPE_32BIT
2375 const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2376 PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2377# else /* PAE */
2378 unsigned iPDSrc;
2379 PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2380# endif
2381# else
2382 PGSTPD pPDSrc = NULL;
2383 const unsigned iPDSrc = 0;
2384# endif
2385 int rc = VINF_SUCCESS;
2386
2387 /*
2388 * First check if the shadow pd is present.
2389 */
2390# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2391 PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2392# else
2393 PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2394# endif
2395 if (!pPdeDst->n.u1Present)
2396 {
2397 rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2398 AssertRC(rc);
2399 if (rc != VINF_SUCCESS)
2400 return rc;
2401 }
2402
2403# if PGM_WITH_PAGING(PGM_GST_TYPE)
2404 /* Check for dirty bit fault */
2405 rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2406 if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2407 Log(("PGMVerifyAccess: success (dirty)\n"));
2408 else
2409 {
2410 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2411#else
2412 {
2413 GSTPDE PdeSrc;
2414 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2415 PdeSrc.n.u1Present = 1;
2416 PdeSrc.n.u1Write = 1;
2417 PdeSrc.n.u1Accessed = 1;
2418 PdeSrc.n.u1User = 1;
2419
2420#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2421 Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2422 if (uErr & X86_TRAP_PF_US)
2423 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2424 else /* supervisor */
2425 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2426
2427 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2428 if (VBOX_SUCCESS(rc))
2429 {
2430 /* Page was successfully synced */
2431 Log2(("PGMVerifyAccess: success (sync)\n"));
2432 rc = VINF_SUCCESS;
2433 }
2434 else
2435 {
2436 Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2437 return VINF_EM_RAW_GUEST_TRAP;
2438 }
2439 }
2440 return rc;
2441
2442#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2443
2444 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2445 return VERR_INTERNAL_ERROR;
2446#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2447}
2448
2449
2450#if PGM_GST_TYPE == PGM_TYPE_32BIT
2451# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE
2452/**
2453 * Figures out which kind of shadow page this guest PDE warrants.
2454 *
2455 * @returns Shadow page kind.
2456 * @param pPdeSrc The guest PDE in question.
2457 * @param cr4 The current guest cr4 value.
2458 */
2459DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2460{
2461 if (!pPdeSrc->n.u1Size || !(cr4 & X86_CR4_PSE))
2462 return BTH_PGMPOOLKIND_PT_FOR_PT;
2463 //switch (pPdeSrc->u & (X86_PDE4M_RW | X86_PDE4M_US /*| X86_PDE4M_PAE_NX*/))
2464 //{
2465 // case 0:
2466 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2467 // case X86_PDE4M_RW:
2468 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2469 // case X86_PDE4M_US:
2470 // return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2471 // case X86_PDE4M_RW | X86_PDE4M_US:
2472 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2473# if 0
2474 // case X86_PDE4M_PAE_NX:
2475 // return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2476 // case X86_PDE4M_RW | X86_PDE4M_PAE_NX:
2477 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2478 // case X86_PDE4M_US | X86_PDE4M_PAE_NX:
2479 // return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2480 // case X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PAE_NX:
2481 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2482# endif
2483 return BTH_PGMPOOLKIND_PT_FOR_BIG;
2484 //}
2485}
2486# endif
2487#endif
2488
2489#undef MY_STAM_COUNTER_INC
2490#define MY_STAM_COUNTER_INC(a) do { } while (0)
2491
2492
2493/**
2494 * Syncs the paging hierarchy starting at CR3.
2495 *
2496 * @returns VBox status code, no specials.
2497 * @param pVM The virtual machine.
2498 * @param cr0 Guest context CR0 register
2499 * @param cr3 Guest context CR3 register
2500 * @param cr4 Guest context CR4 register
2501 * @param fGlobal Including global page directories or not
2502 */
2503PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
2504{
2505#if PGM_GST_TYPE == PGM_TYPE_32BIT
2506# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE
2507 if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2508 fGlobal = true; /* Change this CR3 reload to be a global one. */
2509# endif
2510#endif
2511
2512 /*
2513 * Update page access handlers.
2514 * The virtual are always flushed, while the physical are only on demand.
2515 * WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2516 * have to look into that later because it will have a bad influence on the performance.
2517 * @note SvL: There's no need for that. Just invalidate the virtual range(s).
2518 * bird: Yes, but that won't work for aliases.
2519 */
2520 /** @todo this MUST go away. See #1557. */
2521 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2522 PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2523 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2524
2525#ifdef PGMPOOL_WITH_MONITORING
2526 /*
2527 * When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2528 * Occationally we will have to clear all the shadow page tables because we wanted
2529 * to monitor a page which was mapped by too many shadowed page tables. This operation
2530 * sometimes refered to as a 'lightweight flush'.
2531 */
2532 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2533 pgmPoolMonitorModifiedClearAll(pVM);
2534 else
2535 {
2536# ifdef IN_RING3
2537 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2538 pgmPoolClearAll(pVM);
2539# else
2540 LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2541 return VINF_PGM_SYNC_CR3;
2542# endif
2543 }
2544#endif
2545
2546 Assert(fGlobal || (cr4 & X86_CR4_PGE));
2547 MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2548
2549#if PGM_GST_TYPE == PGM_TYPE_32BIT
2550# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE
2551 /*
2552 * Get page directory addresses.
2553 */
2554# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2555 PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2556# else
2557 PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2558# endif
2559
2560# if PGM_GST_TYPE == PGM_TYPE_32BIT
2561 PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2562# else /* PAE */
2563 PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, 0);
2564# endif
2565
2566 Assert(pPDSrc);
2567#ifndef IN_GC
2568 Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2569#endif
2570
2571 /*
2572 * Iterate the page directory.
2573 */
2574 PPGMMAPPING pMapping;
2575 unsigned iPdNoMapping;
2576 const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2577 PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2578
2579 /* Only check mappings if they are supposed to be put into the shadow page table. */
2580 if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2581 {
2582 pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2583 iPdNoMapping = (pMapping) ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U; /** PAE todo */
2584 }
2585 else
2586 {
2587 pMapping = 0;
2588 iPdNoMapping = ~0U;
2589 }
2590
2591 for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2592 {
2593# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2594 Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2595# else
2596 Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2597# endif
2598 register GSTPDE PdeSrc = pPDSrc->a[iPD];
2599 if ( PdeSrc.n.u1Present
2600 && (PdeSrc.n.u1User || fRawR0Enabled))
2601 {
2602# if PGM_GST_TYPE == PGM_TYPE_32BIT
2603 /*
2604 * Check for conflicts with GC mappings.
2605 */
2606 if (iPD == iPdNoMapping)
2607 {
2608 if (pVM->pgm.s.fMappingsFixed)
2609 {
2610 /* It's fixed, just skip the mapping. */
2611 const unsigned cPTs = pMapping->cPTs;
2612 iPD += cPTs - 1;
2613 pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2614 pMapping = pMapping->CTXALLSUFF(pNext);
2615 iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2616 continue;
2617 }
2618
2619# ifdef IN_RING3
2620 int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2621 if (VBOX_FAILURE(rc))
2622 return rc;
2623
2624 /*
2625 * Update iPdNoMapping and pMapping.
2626 */
2627 pMapping = pVM->pgm.s.pMappingsR3;
2628 while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2629 pMapping = pMapping->pNextR3;
2630 iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2631# else
2632 LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2633 return VINF_PGM_SYNC_CR3;
2634# endif
2635 }
2636# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
2637 /* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2638 Assert(iPD != iPdNoMapping);
2639# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
2640 /*
2641 * Sync page directory entry.
2642 *
2643 * The current approach is to allocated the page table but to set
2644 * the entry to not-present and postpone the page table synching till
2645 * it's actually used.
2646 */
2647# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2648 const unsigned iPdShw = iPD; NOREF(iPdShw);
2649# else
2650 for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2651# endif
2652 {
2653 SHWPDE PdeDst = *pPDEDst;
2654 if (PdeDst.n.u1Present)
2655 {
2656 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2657 RTGCPHYS GCPhys;
2658 if ( !PdeSrc.b.u1Size
2659 || !(cr4 & X86_CR4_PSE))
2660 {
2661 GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2662# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2663 GCPhys |= i * (PAGE_SIZE / 2);
2664# endif
2665 }
2666 else
2667 {
2668 GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2669# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2670 GCPhys |= i * X86_PAGE_2M_SIZE;
2671# endif
2672 }
2673
2674 if ( pShwPage->GCPhys == GCPhys
2675 && pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2676 && ( pShwPage->fCached
2677 || ( !fGlobal
2678 && ( false
2679# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2680 || ( (PdeSrc.u & (X86_PDE4M_PS | X86_PDE4M_G)) == (X86_PDE4M_PS | X86_PDE4M_G)
2681 && (cr4 & (X86_CR4_PGE | X86_CR4_PSE)) == (X86_CR4_PGE | X86_CR4_PSE)) /* global 2/4MB page. */
2682 || ( !pShwPage->fSeenNonGlobal
2683 && (cr4 & X86_CR4_PGE))
2684# endif
2685 )
2686 )
2687 )
2688 && ( (PdeSrc.u & (X86_PDE_US | X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US | X86_PDE_RW))
2689 || ( (cr4 & X86_CR4_PSE)
2690 && ((PdeSrc.u & (X86_PDE_US | X86_PDE4M_PS | X86_PDE4M_D)) | PGM_PDFLAGS_TRACK_DIRTY)
2691 == ((PdeDst.u & (X86_PDE_US | X86_PDE_RW | PGM_PDFLAGS_TRACK_DIRTY)) | X86_PDE4M_PS))
2692 )
2693 )
2694 {
2695# ifdef VBOX_WITH_STATISTICS
2696 if ( !fGlobal
2697 && (PdeSrc.u & (X86_PDE4M_PS | X86_PDE4M_G)) == (X86_PDE4M_PS | X86_PDE4M_G)
2698 && (cr4 & (X86_CR4_PGE | X86_CR4_PSE)) == (X86_CR4_PGE | X86_CR4_PSE))
2699 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2700 else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2701 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2702 else
2703 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2704# endif /* VBOX_WITH_STATISTICS */
2705/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2706 * The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2707//# ifdef PGMPOOL_WITH_CACHE
2708// pgmPoolCacheUsed(pPool, pShwPage);
2709//# endif
2710 }
2711 else
2712 {
2713 pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2714 pPDEDst->u = 0;
2715 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2716 }
2717 }
2718 else
2719 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2720 pPDEDst++;
2721 }
2722 }
2723 else if (iPD != iPdNoMapping)
2724 {
2725 /*
2726 * Check if there is any page directory to mark not present here.
2727 */
2728# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2729 const unsigned iPdShw = iPD; NOREF(iPdShw);
2730# else
2731 for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2732# endif
2733 {
2734 if (pPDEDst->n.u1Present)
2735 {
2736 pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2737 pPDEDst->u = 0;
2738 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2739 }
2740 pPDEDst++;
2741 }
2742 }
2743 else
2744 {
2745# if PGM_GST_TYPE == PGM_TYPE_32BIT
2746 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2747 const unsigned cPTs = pMapping->cPTs;
2748 if (pVM->pgm.s.fMappingsFixed)
2749 {
2750 /* It's fixed, just skip the mapping. */
2751 pMapping = pMapping->CTXALLSUFF(pNext);
2752 iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2753 }
2754 else
2755 {
2756 /*
2757 * Check for conflicts for subsequent pagetables
2758 * and advance to the next mapping.
2759 */
2760 iPdNoMapping = ~0U;
2761 unsigned iPT = cPTs;
2762 while (iPT-- > 1)
2763 {
2764 if ( pPDSrc->a[iPD + iPT].n.u1Present
2765 && (pPDSrc->a[iPD + iPT].n.u1User || fRawR0Enabled))
2766 {
2767# ifdef IN_RING3
2768 int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2769 if (VBOX_FAILURE(rc))
2770 return rc;
2771
2772 /*
2773 * Update iPdNoMapping and pMapping.
2774 */
2775 pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2776 while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2777 pMapping = pMapping->CTXALLSUFF(pNext);
2778 iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2779 break;
2780# else
2781 LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2782 return VINF_PGM_SYNC_CR3;
2783# endif
2784 }
2785 }
2786 if (iPdNoMapping == ~0U && pMapping)
2787 {
2788 pMapping = pMapping->CTXALLSUFF(pNext);
2789 if (pMapping)
2790 iPdNoMapping = pMapping->GCPtr >> X86_PD_SHIFT;
2791 }
2792# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
2793 /* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2794 AssertFailed();
2795# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
2796 }
2797
2798 /* advance. */
2799 iPD += cPTs - 1;
2800 pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2801 }
2802
2803 } /* for iPD */
2804# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2805# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
2806# endif
2807
2808 return VINF_SUCCESS;
2809
2810#elif PGM_GST_TYPE == PGM_TYPE_PAE
2811# if PGM_SHW_TYPE == PGM_TYPE_PAE
2812//# error not implemented
2813 return VERR_INTERNAL_ERROR;
2814
2815# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2816# error "Guest PAE mode, but not the shadow mode ; 32bit - maybe, but amd64 no."
2817# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2818
2819#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2820# if PGM_SHW_TYPE == PGM_TYPE_AMD64
2821//# error not implemented
2822 return VERR_INTERNAL_ERROR;
2823
2824# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2825# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
2826# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2827
2828#else /* guest real and protected mode */
2829
2830 return VINF_SUCCESS;
2831#endif
2832}
2833
2834
2835
2836
2837#ifdef VBOX_STRICT
2838#ifdef IN_GC
2839# undef AssertMsgFailed
2840# define AssertMsgFailed Log
2841#endif
2842#ifdef IN_RING3
2843# include <VBox/dbgf.h>
2844
2845/**
2846 * Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2847 *
2848 * @returns VBox status code (VINF_SUCCESS).
2849 * @param pVM The VM handle.
2850 * @param cr3 The root of the hierarchy.
2851 * @param crr The cr4, only PAE and PSE is currently used.
2852 * @param fLongMode Set if long mode, false if not long mode.
2853 * @param cMaxDepth Number of levels to dump.
2854 * @param pHlp Pointer to the output functions.
2855 */
2856__BEGIN_DECLS
2857PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
2858__END_DECLS
2859
2860#endif
2861
2862/**
2863 * Checks that the shadow page table is in sync with the guest one.
2864 *
2865 * @returns The number of errors.
2866 * @param pVM The virtual machine.
2867 * @param cr3 Guest context CR3 register
2868 * @param cr4 Guest context CR4 register
2869 * @param GCPtr Where to start. Defaults to 0.
2870 * @param cb How much to check. Defaults to everything.
2871 */
2872PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
2873{
2874 unsigned cErrors = 0;
2875
2876#if PGM_GST_TYPE == PGM_TYPE_32BIT
2877
2878# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2879# error "Invalid shadow mode for 32-bit guest paging."
2880# endif
2881
2882 PPGM pPGM = &pVM->pgm.s;
2883 RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
2884 RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
2885 RTHCPHYS HCPhys; /* general usage. */
2886 int rc;
2887
2888 /*
2889 * Check that the Guest CR3 and all it's mappings are correct.
2890 */
2891 AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
2892 ("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
2893 false);
2894 rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
2895 AssertRCReturn(rc, 1);
2896 HCPhys = NIL_RTHCPHYS;
2897 rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
2898 AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
2899# ifdef IN_RING3
2900 RTGCPHYS GCPhys;
2901 rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
2902 AssertRCReturn(rc, 1);
2903 AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
2904# endif
2905 const X86PD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
2906
2907 /*
2908 * Get and check the Shadow CR3.
2909 */
2910# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2911 const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
2912 unsigned cPDEs = ELEMENTS(pPDDst->a);
2913# else
2914 const X86PDPAE *pPDDst = pPGM->CTXMID(ap,PaePDs[0]); /* use it as a 2048 entry PD */
2915 unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
2916# endif
2917 if (cb != ~(RTGCUINTPTR)0)
2918 cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
2919
2920/** @todo call the other two PGMAssert*() functions. */
2921
2922 /*
2923 * Iterate the shadow page directory.
2924 */
2925 GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
2926 unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
2927 cPDEs += iPDDst;
2928 for (;
2929 iPDDst < cPDEs;
2930 iPDDst++, GCPtr += _4G / cPDEs)
2931 {
2932 const SHWPDE PdeDst = pPDDst->a[iPDDst];
2933 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2934 {
2935 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2936 if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
2937 {
2938 AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
2939 cErrors++;
2940 continue;
2941 }
2942 }
2943 else if ( (PdeDst.u & X86_PDE_P)
2944 || ((PdeDst.u & (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY))
2945 )
2946 {
2947 HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
2948 PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
2949 if (!pPoolPage)
2950 {
2951 AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
2952 HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
2953 cErrors++;
2954 continue;
2955 }
2956 const SHWPT *pPTDst = (const SHWPT *)PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
2957
2958 if (PdeDst.u & (X86_PDE4M_PWT | X86_PDE4M_PCD))
2959 {
2960 AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
2961 GCPtr, (uint64_t)PdeDst.u));
2962 cErrors++;
2963 }
2964
2965 if (PdeDst.u & (X86_PDE4M_G | X86_PDE4M_D))
2966 {
2967 AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
2968 GCPtr, (uint64_t)PdeDst.u));
2969 cErrors++;
2970 }
2971
2972 const X86PDE PdeSrc = pPDSrc->a[iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)];
2973 if (!PdeSrc.n.u1Present)
2974 {
2975 AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
2976 GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
2977 cErrors++;
2978 continue;
2979 }
2980
2981 if ( !PdeSrc.b.u1Size
2982 || !(cr4 & X86_CR4_PSE))
2983 {
2984 GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
2985# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2986 GCPhysGst |= (iPDDst & 1) * (PAGE_SIZE / 2);
2987# endif
2988 }
2989 else
2990 {
2991 if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
2992 {
2993 AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
2994 GCPtr, (uint64_t)PdeSrc.u));
2995 cErrors++;
2996 continue;
2997 }
2998 GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2999# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3000 GCPhysGst |= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3001# endif
3002 }
3003
3004 if ( pPoolPage->enmKind
3005 != (!PdeSrc.b.u1Size || !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3006 {
3007 AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3008 pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3009 cErrors++;
3010 }
3011
3012 PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3013 if (!pPhysPage)
3014 {
3015 AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3016 GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3017 cErrors++;
3018 continue;
3019 }
3020
3021 if (GCPhysGst != pPoolPage->GCPhys)
3022 {
3023 AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3024 GCPhysGst, pPoolPage->GCPhys, GCPtr));
3025 cErrors++;
3026 continue;
3027 }
3028
3029 if ( !PdeSrc.b.u1Size
3030 || !(cr4 & X86_CR4_PSE))
3031 {
3032 /*
3033 * Page Table.
3034 */
3035 const GSTPT *pPTSrc;
3036 rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3037 if (VBOX_FAILURE(rc))
3038 {
3039 AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3040 GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3041 cErrors++;
3042 continue;
3043 }
3044 if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_US | X86_PDE_RW/* | X86_PDE_A*/))
3045 != (PdeDst.u & (X86_PDE_P | X86_PDE_US | X86_PDE_RW/* | X86_PDE_A*/)))
3046 {
3047 /// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3048 // (This problem will go away when/if we shadow multiple CR3s.)
3049 AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3050 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3051 cErrors++;
3052 continue;
3053 }
3054 if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3055 {
3056 AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3057 GCPtr, (uint64_t)PdeDst.u));
3058 cErrors++;
3059 continue;
3060 }
3061
3062 /* iterate the page table. */
3063# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3064 const unsigned offPTSrc = 0;
3065# else
3066 const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3067# endif
3068 for (unsigned iPT = 0, off = 0;
3069 iPT < ELEMENTS(pPTDst->a);
3070 iPT++, off += PAGE_SIZE)
3071 {
3072 const SHWPTE PteDst = pPTDst->a[iPT];
3073
3074 /* skip not-present entries. */
3075 if (!(PteDst.u & (X86_PTE_P | PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3076 continue;
3077 Assert(PteDst.n.u1Present);
3078
3079 const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3080 if (!PteSrc.n.u1Present)
3081 {
3082#ifdef IN_RING3
3083 PGMAssertHandlerAndFlagsInSync(pVM);
3084 PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3085#endif
3086 AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3087 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3088 (PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3089 cErrors++;
3090 continue;
3091 }
3092
3093 uint64_t fIgnoreFlags = GST_PTE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_G | X86_PTE_D | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT;
3094# if 1 /** @todo sync accessed bit properly... */
3095 fIgnoreFlags |= X86_PTE_A;
3096# endif
3097
3098 /* match the physical addresses */
3099 HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3100 GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3101
3102# ifdef IN_RING3
3103 rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3104 if (VBOX_FAILURE(rc))
3105 {
3106 if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3107 {
3108 AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3109 GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3110 cErrors++;
3111 continue;
3112 }
3113 }
3114 else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3115 {
3116 AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3117 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3118 cErrors++;
3119 continue;
3120 }
3121# endif
3122
3123 pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3124 if (!pPhysPage)
3125 {
3126# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3127 if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3128 {
3129 AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3130 GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3131 cErrors++;
3132 continue;
3133 }
3134# endif
3135 if (PteDst.n.u1Write)
3136 {
3137 AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3138 GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3139 cErrors++;
3140 }
3141 fIgnoreFlags |= X86_PTE_RW;
3142 }
3143 else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3144 {
3145 AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3146 GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3147 cErrors++;
3148 continue;
3149 }
3150
3151 /* flags */
3152 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3153 {
3154 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3155 {
3156 if (PteDst.n.u1Write)
3157 {
3158 AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3159 GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3160 cErrors++;
3161 continue;
3162 }
3163 fIgnoreFlags |= X86_PTE_RW;
3164 }
3165 else
3166 {
3167 if (PteDst.n.u1Present)
3168 {
3169 AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3170 GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3171 cErrors++;
3172 continue;
3173 }
3174 fIgnoreFlags |= X86_PTE_P;
3175 }
3176 }
3177 else
3178 {
3179 if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3180 {
3181 if (PteDst.n.u1Write)
3182 {
3183 AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3184 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3185 cErrors++;
3186 continue;
3187 }
3188 if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3189 {
3190 AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3191 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3192 cErrors++;
3193 continue;
3194 }
3195 if (PteDst.n.u1Dirty)
3196 {
3197 AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3198 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3199 cErrors++;
3200 }
3201# if 0 /** @todo sync access bit properly... */
3202 if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3203 {
3204 AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3205 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3206 cErrors++;
3207 }
3208 fIgnoreFlags |= X86_PTE_RW;
3209# else
3210 fIgnoreFlags |= X86_PTE_RW | X86_PTE_A;
3211# endif
3212 }
3213 else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3214 {
3215 /* access bit emulation (not implemented). */
3216 if (PteSrc.n.u1Accessed || PteDst.n.u1Present)
3217 {
3218 AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3219 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3220 cErrors++;
3221 continue;
3222 }
3223 if (!PteDst.n.u1Accessed)
3224 {
3225 AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3226 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3227 cErrors++;
3228 }
3229 fIgnoreFlags |= X86_PTE_P;
3230 }
3231# ifdef DEBUG_sandervl
3232 fIgnoreFlags |= X86_PTE_D | X86_PTE_A;
3233# endif
3234 }
3235
3236 if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3237 && (PteSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3238 )
3239 {
3240 AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3241 GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3242 fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3243 cErrors++;
3244 continue;
3245 }
3246 } /* foreach PTE */
3247 }
3248 else
3249 {
3250 /*
3251 * Big Page.
3252 */
3253 uint64_t fIgnoreFlags = X86_PDE_AVL_MASK | X86_PDE_PAE_PG_MASK | X86_PDE4M_G | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_PWT | X86_PDE4M_PCD;
3254 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3255 {
3256 if (PdeDst.n.u1Write)
3257 {
3258 AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3259 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3260 cErrors++;
3261 continue;
3262 }
3263 if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3264 {
3265 AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3266 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3267 cErrors++;
3268 continue;
3269 }
3270# if 0 /** @todo sync access bit properly... */
3271 if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3272 {
3273 AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3274 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3275 cErrors++;
3276 }
3277 fIgnoreFlags |= X86_PTE_RW;
3278# else
3279 fIgnoreFlags |= X86_PTE_RW | X86_PTE_A;
3280# endif
3281 }
3282 else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3283 {
3284 /* access bit emulation (not implemented). */
3285 if (PdeSrc.b.u1Accessed || PdeDst.n.u1Present)
3286 {
3287 AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3288 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3289 cErrors++;
3290 continue;
3291 }
3292 if (!PdeDst.n.u1Accessed)
3293 {
3294 AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3295 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3296 cErrors++;
3297 }
3298 fIgnoreFlags |= X86_PTE_P;
3299 }
3300
3301 if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3302 {
3303 AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3304 GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3305 fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3306 cErrors++;
3307 }
3308
3309 /* iterate the page table. */
3310 for (unsigned iPT = 0, off = 0;
3311 iPT < ELEMENTS(pPTDst->a);
3312 iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3313 {
3314 const SHWPTE PteDst = pPTDst->a[iPT];
3315
3316 if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3317 {
3318 AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3319 GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3320 cErrors++;
3321 }
3322
3323 /* skip not-present entries. */
3324 if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3325 continue;
3326
3327 fIgnoreFlags = X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT;
3328
3329 /* match the physical addresses */
3330 HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3331
3332# ifdef IN_RING3
3333 rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3334 if (VBOX_FAILURE(rc))
3335 {
3336 if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3337 {
3338 AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3339 GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3340 cErrors++;
3341 }
3342 }
3343 else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3344 {
3345 AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3346 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3347 cErrors++;
3348 continue;
3349 }
3350# endif
3351
3352 pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3353 if (!pPhysPage)
3354 {
3355# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3356 if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3357 {
3358 AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3359 GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3360 cErrors++;
3361 continue;
3362 }
3363# endif
3364 if (PteDst.n.u1Write)
3365 {
3366 AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3367 GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3368 cErrors++;
3369 }
3370 fIgnoreFlags |= X86_PTE_RW;
3371 }
3372 else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
3373 {
3374 AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3375 GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3376 cErrors++;
3377 continue;
3378 }
3379
3380 /* flags */
3381 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3382 {
3383 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3384 {
3385 if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
3386 {
3387 if (PteDst.n.u1Write)
3388 {
3389 AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3390 GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3391 cErrors++;
3392 continue;
3393 }
3394 fIgnoreFlags |= X86_PTE_RW;
3395 }
3396 }
3397 else
3398 {
3399 if (PteDst.n.u1Present)
3400 {
3401 AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3402 GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3403 cErrors++;
3404 continue;
3405 }
3406 fIgnoreFlags |= X86_PTE_P;
3407 }
3408 }
3409
3410 if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3411 && (PdeSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3412 )
3413 {
3414 AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3415 GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3416 fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3417 cErrors++;
3418 continue;
3419 }
3420 } /* foreach PTE */
3421 }
3422 }
3423 /* not present */
3424
3425 } /* forearch PDE */
3426
3427# ifdef DEBUG
3428 if (cErrors)
3429 LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3430# endif
3431
3432#elif PGM_GST_TYPE == PGM_TYPE_PAE
3433//# error not implemented
3434
3435
3436#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3437//# error not implemented
3438
3439/*#else: guest real and protected mode */
3440#endif
3441 return cErrors;
3442}
3443#endif /* VBOX_STRICT */
3444
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