PGMAllBth.h@ 7666

Last change on this file since 7666 was 7666, checked in by vboxsync, 17 years ago
Put back the original PAE defines. AMD differs from Intel wrt valid pae & long mode physical address bits.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 147.7 KB

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1	/* $Id: PGMAllBth.h 7666 2008-03-31 15:02:43Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 innotek GmbH
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20	/*******************************************************************************
21	* Internal Functions *
22	*******************************************************************************/
23	__BEGIN_DECLS
24	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
25	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
26	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
27	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
28	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
29	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
30	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
31	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal);
32	#ifdef VBOX_STRICT
33	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
34	#endif
35	#ifdef PGMPOOL_WITH_USER_TRACKING
36	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
37	#endif
38	__END_DECLS
39
40
41	/**
42	* #PF Handler for raw-mode guest execution.
43	*
44	* @returns VBox status code (appropriate for trap handling and GC return).
45	* @param pVM VM Handle.
46	* @param uErr The trap error code.
47	* @param pRegFrame Trap register frame.
48	* @param pvFault The fault address.
49	*/
50	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
51	{
52	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
53
54	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
55	# error "32-bit guest mode is only implemented for 32-bit and PAE shadow modes."
56	# endif
57
58	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
59	/*
60	* Hide the instruction fetch trap indicator for now.
61	*/
62	/** @todo NXE will change this and we must fix NXE in the switcher too! */
63	if (uErr & X86_TRAP_PF_ID)
64	{
65	uErr &= ~X86_TRAP_PF_ID;
66	TRPMSetErrorCode(pVM, uErr);
67	}
68	# endif
69
70	/*
71	* Get PDs.
72	*/
73	int rc;
74	# if PGM_WITH_PAGING(PGM_GST_TYPE)
75	# if PGM_GST_TYPE == PGM_TYPE_32BIT
76	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
77	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
78	# else /* PAE */
79	unsigned iPDSrc;
80	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
81	# endif
82	# else
83	PGSTPD pPDSrc = NULL;
84	const unsigned iPDSrc = 0;
85	# endif
86
87	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
88	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
89	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
90	# else /* PAE */
91	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
92	# endif
93
94	# if PGM_WITH_PAGING(PGM_GST_TYPE)
95	# ifdef PGM_SYNC_DIRTY_BIT
96	/*
97	* If we successfully correct the write protection fault due to dirty bit
98	* tracking, or this page fault is a genuine one, then return immediately.
99	*/
100	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
101	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
102	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
103	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
104	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
105	{
106	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
107	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
108	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
109	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
110	}
111	# endif
112
113	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
114	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
115
116	/*
117	* A common case is the not-present error caused by lazy page table syncing.
118	*
119	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
120	* so we can safely assume that the shadow PT is present when calling SyncPage later.
121	*
122	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
123	* of mapping conflict and defer to SyncCR3 in R3.
124	* (Again, we do NOT support access handlers for non-present guest pages.)
125	*
126	*/
127	# if PGM_WITH_PAGING(PGM_GST_TYPE)
128	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
129	# else
130	GSTPDE PdeSrc;
131	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
132	PdeSrc.n.u1Present = 1;
133	PdeSrc.n.u1Write = 1;
134	PdeSrc.n.u1Accessed = 1;
135	PdeSrc.n.u1User = 1;
136	# endif
137	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
138	&& !pPDDst->a[iPDDst].n.u1Present
139	&& PdeSrc.n.u1Present
140	)
141
142	{
143	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
144	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
145	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
146	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
147	if (VBOX_SUCCESS(rc))
148	{
149	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
150	return rc;
151	}
152	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
153	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
154	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
155	return VINF_PGM_SYNC_CR3;
156	}
157
158	# if PGM_WITH_PAGING(PGM_GST_TYPE)
159	/*
160	* Check if this address is within any of our mappings.
161	*
162	* This is very fast and it's gonna save us a bit of effort below and prevent
163	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
164	* (BTW, it's impossible to have physical access handlers in a mapping.)
165	*/
166	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
167	{
168	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
169	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
170	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
171	{
172	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
173	break;
174	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
175	{
176	/*
177	* The first thing we check is if we've got an undetected conflict.
178	*/
179	if (!pVM->pgm.s.fMappingsFixed)
180	{
181	unsigned iPT = pMapping->cPTs;
182	while (iPT-- > 0)
183	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
184	{
185	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
186	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
187	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
188	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
189	return VINF_PGM_SYNC_CR3;
190	}
191	}
192
193	/*
194	* Check if the fault address is in a virtual page access handler range.
195	*/
196	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
197	if ( pCur
198	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
199	&& uErr & X86_TRAP_PF_RW)
200	{
201	# ifdef IN_GC
202	STAM_PROFILE_START(&pCur->Stat, h);
203	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
204	STAM_PROFILE_STOP(&pCur->Stat, h);
205	# else
206	AssertFailed();
207	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
208	# endif
209	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
210	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
211	return rc;
212	}
213
214	/*
215	* Pretend we're not here and let the guest handle the trap.
216	*/
217	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
218	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
219	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
220	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
221	return VINF_EM_RAW_GUEST_TRAP;
222	}
223	}
224	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
225	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
226	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
227
228	/*
229	* Check if this fault address is flagged for special treatment,
230	* which means we'll have to figure out the physical address and
231	* check flags associated with it.
232	*
233	* ASSUME that we can limit any special access handling to pages
234	* in page tables which the guest believes to be present.
235	*/
236	if (PdeSrc.n.u1Present)
237	{
238	RTGCPHYS GCPhys = NIL_RTGCPHYS;
239
240	# if PGM_WITH_PAGING(PGM_GST_TYPE)
241	uint32_t cr4 = CPUMGetGuestCR4(pVM);
242	if ( PdeSrc.b.u1Size
243	&& (cr4 & X86_CR4_PSE))
244	GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
245	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
246	else
247	{
248	PX86PT pPTSrc;
249	# ifdef IN_GC
250	rc = PGMGCDynMapGCPage(pVM, PdeSrc.u & GST_PDE_PG_MASK, (void **)&pPTSrc);
251	# else
252	pPTSrc = (PX86PT)MMPhysGCPhys2HCVirt(pVM, PdeSrc.u & GST_PDE_PG_MASK, sizeof(*pPTSrc));
253	if (pPTSrc == 0)
254	rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
255	# endif
256	if (VBOX_SUCCESS(rc))
257	{
258	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> PAGE_SHIFT) & GST_PT_MASK;
259	if (pPTSrc->a[iPTESrc].n.u1Present)
260	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
261	}
262	}
263	# else
264	/* No paging so the fault address is the physical address */
265	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
266	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
267
268	/*
269	* If we have a GC address we'll check if it has any flags set.
270	*/
271	if (GCPhys != NIL_RTGCPHYS)
272	{
273	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
274
275	PPGMPAGE pPage;
276	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
277	if (VBOX_SUCCESS(rc))
278	{
279	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
280	{
281	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
282	{
283	/*
284	* Physical page access handler.
285	*/
286	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
287	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
288	if (pCur)
289	{
290	# ifdef PGM_SYNC_N_PAGES
291	/*
292	* If the region is write protected and we got a page not present fault, then sync
293	* the pages. If the fault was caused by a read, then restart the instruction.
294	* In case of write access continue to the GC write handler.
295	*
296	* ASSUMES that there is only one handler per page or that they have similar write properties.
297	*/
298	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
299	&& !(uErr & X86_TRAP_PF_P))
300	{
301	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
302	if ( VBOX_FAILURE(rc)
303	\|\| !(uErr & X86_TRAP_PF_RW)
304	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
305	{
306	AssertRC(rc);
307	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
308	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
309	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
310	return rc;
311	}
312	}
313	# endif
314
315	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
316	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
317	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
318
319	#if defined(IN_GC) \|\| defined(IN_RING0)
320	if (CTXALLSUFF(pCur->pfnHandler))
321	{
322	STAM_PROFILE_START(&pCur->Stat, h);
323	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
324	STAM_PROFILE_STOP(&pCur->Stat, h);
325	}
326	else
327	#endif
328	rc = VINF_EM_RAW_EMULATE_INSTR;
329	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
330	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
331	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
332	return rc;
333	}
334	}
335	# if PGM_WITH_PAGING(PGM_GST_TYPE)
336	else
337	{
338	# ifdef PGM_SYNC_N_PAGES
339	/*
340	* If the region is write protected and we got a page not present fault, then sync
341	* the pages. If the fault was caused by a read, then restart the instruction.
342	* In case of write access continue to the GC write handler.
343	*/
344	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
345	&& !(uErr & X86_TRAP_PF_P))
346	{
347	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
348	if ( VBOX_FAILURE(rc)
349	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
350	\|\| !(uErr & X86_TRAP_PF_RW))
351	{
352	AssertRC(rc);
353	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
354	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
355	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
356	return rc;
357	}
358	}
359	# endif
360	/*
361	* Ok, it's an virtual page access handler.
362	*
363	* Since it's faster to search by address, we'll do that first
364	* and then retry by GCPhys if that fails.
365	*/
366	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
367	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
368	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
369	*/
370	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
371	if (pCur)
372	{
373	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
374	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
375	\|\| !(uErr & X86_TRAP_PF_P)
376	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
377	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
378
379	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
380	&& ( uErr & X86_TRAP_PF_RW
381	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
382	{
383	# ifdef IN_GC
384	STAM_PROFILE_START(&pCur->Stat, h);
385	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
386	STAM_PROFILE_STOP(&pCur->Stat, h);
387	# else
388	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
389	# endif
390	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
391	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
392	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
393	return rc;
394	}
395	/* Unhandled part of a monitored page */
396	}
397	else
398	{
399	/* Check by physical address. */
400	PPGMVIRTHANDLER pCur;
401	unsigned iPage;
402	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
403	&pCur, &iPage);
404	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
405	if ( pCur
406	&& ( uErr & X86_TRAP_PF_RW
407	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
408	{
409	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
410	# ifdef IN_GC
411	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
412	Assert(off < pCur->cb);
413	STAM_PROFILE_START(&pCur->Stat, h);
414	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
415	STAM_PROFILE_STOP(&pCur->Stat, h);
416	# else
417	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
418	# endif
419	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
420	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
421	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
422	return rc;
423	}
424	}
425	}
426	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
427
428	/*
429	* There is a handled area of the page, but this fault doesn't belong to it.
430	* We must emulate the instruction.
431	*
432	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
433	* we first check if this was a page-not-present fault for a page with only
434	* write access handlers. Restart the instruction if it wasn't a write access.
435	*/
436	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
437
438	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
439	&& !(uErr & X86_TRAP_PF_P))
440	{
441	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
442	if ( VBOX_FAILURE(rc)
443	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
444	\|\| !(uErr & X86_TRAP_PF_RW))
445	{
446	AssertRC(rc);
447	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
448	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
449	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
450	return rc;
451	}
452	}
453
454	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
455	* It's writing to an unhandled part of the LDT page several million times.
456	*/
457	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
458	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
459	rc, pPage->HCPhys,
460	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
461	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
462	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
463	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
464	return rc;
465	} /* if any kind of handler */
466
467	# if PGM_WITH_PAGING(PGM_GST_TYPE)
468	if (uErr & X86_TRAP_PF_P)
469	{
470	/*
471	* The page isn't marked, but it might still be monitored by a virtual page access handler.
472	* (ASSUMES no temporary disabling of virtual handlers.)
473	*/
474	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
475	* we should correct both the shadow page table and physical memory flags, and not only check for
476	* accesses within the handler region but for access to pages with virtual handlers. */
477	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
478	if (pCur)
479	{
480	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
481	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
482	\|\| !(uErr & X86_TRAP_PF_P)
483	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
484	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
485
486	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
487	&& ( uErr & X86_TRAP_PF_RW
488	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
489	{
490	# ifdef IN_GC
491	STAM_PROFILE_START(&pCur->Stat, h);
492	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
493	STAM_PROFILE_STOP(&pCur->Stat, h);
494	# else
495	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
496	# endif
497	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
498	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
499	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
500	return rc;
501	}
502	}
503	}
504	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
505	}
506	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
507
508	# ifdef PGM_OUT_OF_SYNC_IN_GC
509	/*
510	* We are here only if page is present in Guest page tables and trap is not handled
511	* by our handlers.
512	* Check it for page out-of-sync situation.
513	*/
514	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
515
516	if (!(uErr & X86_TRAP_PF_P))
517	{
518	/*
519	* Page is not present in our page tables.
520	* Try to sync it!
521	* BTW, fPageShw is invalid in this branch!
522	*/
523	if (uErr & X86_TRAP_PF_US)
524	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
525	else /* supervisor */
526	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
527
528	# if defined(LOG_ENABLED) && !defined(IN_RING0)
529	RTGCPHYS GCPhys;
530	uint64_t fPageGst;
531	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
532	Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
533	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
534	# endif /* LOG_ENABLED */
535
536	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
537	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
538	{
539	uint64_t fPageGst;
540	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
541	if ( VBOX_SUCCESS(rc)
542	&& !(fPageGst & X86_PTE_US))
543	{
544	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
545	if ( pvFault == (RTGCPTR)pRegFrame->eip
546	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
547	# ifdef CSAM_DETECT_NEW_CODE_PAGES
548	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
549	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
550	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
551	)
552	{
553	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
554	rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
555	if (rc != VINF_SUCCESS)
556	{
557	/*
558	* CSAM needs to perform a job in ring 3.
559	*
560	* Sync the page before going to the host context; otherwise we'll end up in a loop if
561	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
562	*/
563	LogFlow(("CSAM ring 3 job\n"));
564	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
565	AssertRC(rc2);
566
567	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
568	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
569	return rc;
570	}
571	}
572	# ifdef CSAM_DETECT_NEW_CODE_PAGES
573	else
574	if ( uErr == X86_TRAP_PF_RW
575	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
576	&& pRegFrame->ecx < 0x10000
577	)
578	{
579	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
580	* to detect loading of new code pages.
581	*/
582
583	/*
584	* Decode the instruction.
585	*/
586	RTGCPTR PC;
587	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
588	if (rc == VINF_SUCCESS)
589	{
590	DISCPUSTATE Cpu;
591	uint32_t cbOp;
592	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
593
594	/* For now we'll restrict this to rep movsw/d instructions */
595	if ( rc == VINF_SUCCESS
596	&& Cpu.pCurInstr->opcode == OP_MOVSWD
597	&& (Cpu.prefix & PREFIX_REP))
598	{
599	CSAMMarkPossibleCodePage(pVM, pvFault);
600	}
601	}
602	}
603	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
604
605	/*
606	* Mark this page as safe.
607	*/
608	/** @todo not correct for pages that contain both code and data!! */
609	Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
610	CSAMMarkPage(pVM, pvFault, true);
611	}
612	}
613	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
614	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
615	if (VBOX_SUCCESS(rc))
616	{
617	/* The page was successfully synced, return to the guest. */
618	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
619	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
620	return VINF_SUCCESS;
621	}
622	}
623	else
624	{
625	/*
626	* A side effect of not flushing global PDEs are out of sync pages due
627	* to physical monitored regions, that are no longer valid.
628	* Assume for now it only applies to the read/write flag
629	*/
630	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
631	{
632	if (uErr & X86_TRAP_PF_US)
633	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
634	else /* supervisor */
635	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
636
637
638	/*
639	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
640	*/
641	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
642	if (VBOX_SUCCESS(rc))
643	{
644	/*
645	* Page was successfully synced, return to guest.
646	*/
647	# ifdef VBOX_STRICT
648	RTGCPHYS GCPhys;
649	uint64_t fPageGst;
650	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
651	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
652	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
653
654	uint64_t fPageShw;
655	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
656	Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
657	# endif /* VBOX_STRICT */
658	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
659	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
660	return VINF_SUCCESS;
661	}
662	}
663
664	# if PGM_WITH_PAGING(PGM_GST_TYPE)
665	# ifdef VBOX_STRICT
666	/*
667	* Check for VMM page flags vs. Guest page flags consistency.
668	* Currently only for debug purposes.
669	*/
670	if (VBOX_SUCCESS(rc))
671	{
672	/* Get guest page flags. */
673	uint64_t fPageGst;
674	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
675	if (VBOX_SUCCESS(rc))
676	{
677	uint64_t fPageShw;
678	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
679
680	/*
681	* Compare page flags.
682	* Note: we have AVL, A, D bits desynched.
683	*/
684	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
685	("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
686	}
687	else
688	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
689	}
690	else
691	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
692	# endif /* VBOX_STRICT */
693	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
694	}
695	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
696	# endif /* PGM_OUT_OF_SYNC_IN_GC */
697	}
698	else
699	{
700	/*
701	* Page not present in Guest OS or invalid page table address.
702	* This is potential virtual page access handler food.
703	*
704	* For the present we'll say that our access handlers don't
705	* work for this case - we've already discarded the page table
706	* not present case which is identical to this.
707	*
708	* When we perchance find we need this, we will probably have AVL
709	* trees (offset based) to operate on and we can measure their speed
710	* agains mapping a page table and probably rearrange this handling
711	* a bit. (Like, searching virtual ranges before checking the
712	* physical address.)
713	*/
714	}
715	}
716
717
718	# if PGM_WITH_PAGING(PGM_GST_TYPE)
719	/*
720	* Conclusion, this is a guest trap.
721	*/
722	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
723	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
724	return VINF_EM_RAW_GUEST_TRAP;
725	# else
726	/* present, but not a monitored page; perhaps the guest is probing physical memory */
727	return VINF_EM_RAW_EMULATE_INSTR;
728	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
729
730
731	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
732
733	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
734	return VERR_INTERNAL_ERROR;
735	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
736	}
737
738
739	/**
740	* Emulation of the invlpg instruction.
741	*
742	*
743	* @returns VBox status code.
744	*
745	* @param pVM VM handle.
746	* @param GCPtrPage Page to invalidate.
747	*
748	* @remark ASSUMES that the guest is updating before invalidating. This order
749	* isn't required by the CPU, so this is speculative and could cause
750	* trouble.
751	*
752	* @todo Flush page or page directory only if necessary!
753	* @todo Add a #define for simply invalidating the page.
754	*/
755	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
756	{
757	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
758	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
759
760	LogFlow(("InvalidatePage %x\n", GCPtrPage));
761	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
762	/*
763	* Get the shadow PD entry and skip out if this PD isn't present.
764	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
765	*/
766	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
767	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
768	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
769	# else
770	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
771	# endif
772	const SHWPDE PdeDst = *pPdeDst;
773	if (!PdeDst.n.u1Present)
774	{
775	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
776	return VINF_SUCCESS;
777	}
778
779	/*
780	* Get the guest PD entry and calc big page.
781	*/
782	# if PGM_GST_TYPE == PGM_TYPE_32BIT
783	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
784	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
785	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
786	# else /* PAE */
787	unsigned iPDSrc;
788	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
789	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
790	# endif
791
792	const uint32_t cr4 = CPUMGetGuestCR4(pVM);
793	const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
794
795	# ifdef IN_RING3
796	/*
797	* If a CR3 Sync is pending we may ignore the invalidate page operation
798	* depending on the kind of sync and if it's a global page or not.
799	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
800	*/
801	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
802	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
803	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
804	&& fIsBigPage
805	&& PdeSrc.b.u1Global
806	&& (cr4 & X86_CR4_PGE)
807	)
808	)
809	# else
810	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
811	# endif
812	{
813	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
814	return VINF_SUCCESS;
815	}
816	# endif /* IN_RING3 */
817
818
819	/*
820	* Deal with the Guest PDE.
821	*/
822	int rc = VINF_SUCCESS;
823	if (PdeSrc.n.u1Present)
824	{
825	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
826	{
827	/*
828	* Conflict - Let SyncPT deal with it to avoid duplicate code.
829	*/
830	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
831	Assert(PGMGetGuestMode(pVM) <= PGMMODE_32_BIT);
832	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
833	}
834	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
835	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
836	{
837	/*
838	* Mark not present so we can resync the PDE when it's used.
839	*/
840	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
841	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
842	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
843	pPdeDst->u = 0;
844	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
845	PGM_INVL_GUEST_TLBS();
846	}
847	# ifdef PGM_SYNC_ACCESSED_BIT
848	else if (!PdeSrc.n.u1Accessed)
849	{
850	/*
851	* Mark not present so we can set the accessed bit.
852	*/
853	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
854	pPdeDst->u = 0;
855	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
856	PGM_INVL_GUEST_TLBS();
857	}
858	# endif
859	else if (!fIsBigPage)
860	{
861	/*
862	* 4KB - page.
863	*/
864	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
865	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
866	# if PGM_SHW_TYPE != PGM_TYPE_32BIT \
867	&& PGM_GST_TYPE == PGM_TYPE_32BIT
868	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
869	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
870	# endif
871	if (pShwPage->GCPhys == GCPhys)
872	{
873	#if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
874	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
875	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
876	if (pPT->a[iPTEDst].n.u1Present)
877	{
878	# ifdef PGMPOOL_WITH_USER_TRACKING
879	/* This is very unlikely with caching/monitoring enabled. */
880	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
881	# endif
882	pPT->a[iPTEDst].u = 0;
883	}
884	#else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
885	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
886	if (VBOX_SUCCESS(rc))
887	rc = VINF_SUCCESS;
888	#endif
889	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
890	PGM_INVL_PG(GCPtrPage);
891	}
892	else
893	{
894	/*
895	* The page table address changed.
896	*/
897	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
898	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
899	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
900	pPdeDst->u = 0;
901	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
902	PGM_INVL_GUEST_TLBS();
903	}
904	}
905	else
906	{
907	/*
908	* 4MB - page.
909	*/
910	/* Before freeing the page, check if anything really changed. */
911	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
912	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
913	# if PGM_SHW_TYPE != PGM_TYPE_32BIT \
914	&& PGM_GST_TYPE == PGM_TYPE_32BIT
915	/* Select the right PDE as we're emulating a 4MB page with two 2 MB shadow PDEs */
916	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
917	# endif
918	if ( pShwPage->GCPhys == GCPhys
919	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
920	{
921	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
922	/** @todo PAT */
923	# ifdef PGM_SYNC_DIRTY_BIT
924	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
925	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
926	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
927	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
928	# else
929	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
930	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD)))
931	# endif
932	{
933	LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
934	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
935	return VINF_SUCCESS;
936	}
937	}
938
939	/*
940	* Ok, the page table is present and it's been changed in the guest.
941	* If we're in host context, we'll just mark it as not present taking the lazy approach.
942	* We could do this for some flushes in GC too, but we need an algorithm for
943	* deciding which 4MB pages containing code likely to be executed very soon.
944	*/
945	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
946	pPdeDst->u = 0;
947	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
948	PGM_INVL_BIG_PG(GCPtrPage);
949	}
950	}
951	else
952	{
953	/*
954	* Page directory is not present, mark shadow PDE not present.
955	*/
956	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
957	{
958	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
959	pPdeDst->u = 0;
960	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
961	PGM_INVL_PG(GCPtrPage);
962	}
963	else
964	{
965	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
966	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
967	}
968	}
969
970	return rc;
971
972	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
973	# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
974	# endif
975	return VINF_SUCCESS;
976
977	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
978	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
979	//# error not implemented
980	return VERR_INTERNAL_ERROR;
981
982	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
983	# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
984	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
985
986	#else /* guest real and protected mode */
987	/* There's no such thing when paging is disabled. */
988	return VINF_SUCCESS;
989	#endif
990	}
991
992
993	#ifdef PGMPOOL_WITH_USER_TRACKING
994	/**
995	* Update the tracking of shadowed pages.
996	*
997	* @param pVM The VM handle.
998	* @param pShwPage The shadow page.
999	* @param HCPhys The physical page we is being dereferenced.
1000	*/
1001	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1002	{
1003	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1004	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1005	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1006
1007	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1008	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1009	* 2. write protect all shadowed pages. I.e. implement caching.
1010	*/
1011	/*
1012	* Find the guest address.
1013	*/
1014	for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1015	pRam;
1016	pRam = CTXALLSUFF(pRam->pNext))
1017	{
1018	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1019	while (iPage-- > 0)
1020	{
1021	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1022	{
1023	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1024	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1025	pShwPage->cPresent--;
1026	pPool->cPresent--;
1027	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1028	return;
1029	}
1030	}
1031	}
1032
1033	for (;;)
1034	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1035	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1036	pShwPage->cPresent--;
1037	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1038	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1039	}
1040
1041
1042	/**
1043	* Update the tracking of shadowed pages.
1044	*
1045	* @param pVM The VM handle.
1046	* @param pShwPage The shadow page.
1047	* @param u16 The top 16-bit of the pPage->HCPhys.
1048	* @param pPage Pointer to the guest page. this will be modified.
1049	* @param iPTDst The index into the shadow table.
1050	*/
1051	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1052	{
1053	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1054	/*
1055	* We're making certain assumptions about the placement of cRef and idx.
1056	*/
1057	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1058	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1059
1060	/*
1061	* Just deal with the simple first time here.
1062	*/
1063	if (!u16)
1064	{
1065	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1066	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1067	}
1068	else
1069	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1070
1071	/* write back, trying to be clever... */
1072	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1073	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1074	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1075	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1076
1077	/* update statistics. */
1078	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1079	pShwPage->cPresent++;
1080	if (pShwPage->iFirstPresent > iPTDst)
1081	pShwPage->iFirstPresent = iPTDst;
1082	}
1083	#endif /* PGMPOOL_WITH_USER_TRACKING */
1084
1085
1086	/**
1087	* Creates a 4K shadow page for a guest page.
1088	*
1089	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1090	* physical address. The PdeSrc argument only the flags are used. No page structured
1091	* will be mapped in this function.
1092	*
1093	* @param pVM VM handle.
1094	* @param pPteDst Destination page table entry.
1095	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1096	* Can safely assume that only the flags are being used.
1097	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1098	* @param pShwPage Pointer to the shadow page.
1099	* @param iPTDst The index into the shadow table.
1100	*
1101	* @remark Not used for 2/4MB pages!
1102	*/
1103	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1104	{
1105	if (PteSrc.n.u1Present)
1106	{
1107	/*
1108	* Find the ram range.
1109	*/
1110	PPGMPAGE pPage;
1111	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1112	if (VBOX_SUCCESS(rc))
1113	{
1114	/** @todo investiage PWT, PCD and PAT. */
1115	/*
1116	* Make page table entry.
1117	*/
1118	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1119	SHWPTE PteDst;
1120	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1121	{
1122	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1123	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1124	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1125	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1126	else
1127	{
1128	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1129	PteDst.u = 0;
1130	}
1131	/** @todo count these two kinds. */
1132	}
1133	else
1134	{
1135	#ifdef PGM_SYNC_DIRTY_BIT
1136	# ifdef PGM_SYNC_ACCESSED_BIT
1137	/*
1138	* If the page or page directory entry is not marked accessed,
1139	* we mark the page not present.
1140	*/
1141	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1142	{
1143	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1144	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1145	PteDst.u = 0;
1146	}
1147	else
1148	# endif
1149	/*
1150	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1151	* when the page is modified.
1152	*/
1153	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1154	{
1155	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1156	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1157	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1158	\| PGM_PTFLAGS_TRACK_DIRTY;
1159	}
1160	else
1161	{
1162	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1163	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1164	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1165	}
1166	#endif
1167	}
1168
1169	#ifdef PGMPOOL_WITH_USER_TRACKING
1170	/*
1171	* Keep user track up to date.
1172	*/
1173	if (PteDst.n.u1Present)
1174	{
1175	if (!pPteDst->n.u1Present)
1176	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1177	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1178	{
1179	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1180	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1181	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1182	}
1183	}
1184	else if (pPteDst->n.u1Present)
1185	{
1186	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1187	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1188	}
1189	#endif /* PGMPOOL_WITH_USER_TRACKING */
1190
1191	/*
1192	* Update statistics and commit the entry.
1193	*/
1194	if (!PteSrc.n.u1Global)
1195	pShwPage->fSeenNonGlobal = true;
1196	*pPteDst = PteDst;
1197	}
1198	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1199	/** @todo count these. */
1200	}
1201	else
1202	{
1203	/*
1204	* Page not-present.
1205	*/
1206	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1207	#ifdef PGMPOOL_WITH_USER_TRACKING
1208	/* Keep user track up to date. */
1209	if (pPteDst->n.u1Present)
1210	{
1211	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1212	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1213	}
1214	#endif /* PGMPOOL_WITH_USER_TRACKING */
1215	pPteDst->u = 0;
1216	/** @todo count these. */
1217	}
1218	}
1219
1220
1221	/**
1222	* Syncs a guest OS page.
1223	*
1224	* There are no conflicts at this point, neither is there any need for
1225	* page table allocations.
1226	*
1227	* @returns VBox status code.
1228	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1229	* @param pVM VM handle.
1230	* @param PdeSrc Page directory entry of the guest.
1231	* @param GCPtrPage Guest context page address.
1232	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1233	* @param uErr Fault error (X86_TRAP_PF_*).
1234	*/
1235	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1236	{
1237	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1238
1239	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1240	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1241
1242	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1243	# error "Invalid shadow mode for 32-bit guest mode!"
1244	# endif
1245
1246	/*
1247	* Assert preconditions.
1248	*/
1249	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & GST_PD_MASK]);
1250	Assert(PdeSrc.n.u1Present);
1251	Assert(cPages);
1252
1253	/*
1254	* Get the shadow PDE, find the shadow page table in the pool.
1255	*/
1256	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1257	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1258	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1259	# else /* PAE */
1260	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1261	# endif
1262	Assert(PdeDst.n.u1Present);
1263	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1264
1265	/*
1266	* Check that the page is present and that the shadow PDE isn't out of sync.
1267	*/
1268	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1269	RTGCPHYS GCPhys;
1270	if (!fBigPage)
1271	{
1272	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1273	# if PGM_SHW_TYPE != PGM_TYPE_32BIT \
1274	&& PGM_GST_TYPE == PGM_TYPE_32BIT
1275	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1276	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1277	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1278	# endif
1279	}
1280	else
1281	{
1282	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1283	# if PGM_SHW_TYPE != PGM_TYPE_32BIT \
1284	&& PGM_GST_TYPE == PGM_TYPE_32BIT
1285	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs */
1286	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1287	# endif
1288	}
1289	if ( pShwPage->GCPhys == GCPhys
1290	&& PdeSrc.n.u1Present
1291	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1292	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1293	# if PGM_GST_TYPE == PGM_TYPE_PAE
1294	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1295	# endif
1296	)
1297	{
1298	# ifdef PGM_SYNC_ACCESSED_BIT
1299	/*
1300	* Check that the PDE is marked accessed already.
1301	* Since we set the accessed bit before getting here on a #PF, this
1302	* check is only meant for dealing with non-#PF'ing paths.
1303	*/
1304	if (PdeSrc.n.u1Accessed)
1305	# endif
1306	{
1307	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1308	if (!fBigPage)
1309	{
1310	/*
1311	* 4KB Page - Map the guest page table.
1312	*/
1313	PGSTPT pPTSrc;
1314	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1315	if (VBOX_SUCCESS(rc))
1316	{
1317	# ifdef PGM_SYNC_N_PAGES
1318	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1319	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1320	{
1321	/*
1322	* This code path is currently only taken when the caller is PGMTrap0eHandler
1323	* for non-present pages!
1324	*
1325	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1326	* deal with locality.
1327	*/
1328	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1329	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1330	const unsigned offPTSrc = 0;
1331	# else
1332	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1333	# endif
1334	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1335	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1336	iPTDst = 0;
1337	else
1338	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1339	for (; iPTDst < iPTDstEnd; iPTDst++)
1340	{
1341	if (!pPTDst->a[iPTDst].n.u1Present)
1342	{
1343	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1344	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1345	NOREF(GCPtrCurPage);
1346	#ifndef IN_RING0
1347	/*
1348	* Assuming kernel code will be marked as supervisor - and not as user level
1349	* and executed using a conforming code selector - And marked as readonly.
1350	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1351	*/
1352	PPGMPAGE pPage;
1353	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1354	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1355	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1356	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1357	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1358	)
1359	#endif /* else: CSAM not active */
1360	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1361	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1362	GCPtrCurPage, PteSrc.n.u1Present,
1363	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1364	PteSrc.n.u1User & PdeSrc.n.u1User,
1365	(uint64_t)PteSrc.u,
1366	(uint64_t)pPTDst->a[iPTDst].u,
1367	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1368	}
1369	}
1370	}
1371	else
1372	# endif /* PGM_SYNC_N_PAGES */
1373	{
1374	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1375	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1376	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1377	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1378	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1379	GCPtrPage, PteSrc.n.u1Present,
1380	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1381	PteSrc.n.u1User & PdeSrc.n.u1User,
1382	(uint64_t)PteSrc.u,
1383	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1384	}
1385	}
1386	else /* MMIO or invalid page: emulated in #PF handler. */
1387	{
1388	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1389	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1390	}
1391	}
1392	else
1393	{
1394	/*
1395	* 4/2MB page - lazy syncing shadow 4K pages.
1396	* (There are many causes of getting here, it's no longer only CSAM.)
1397	*/
1398	/* Calculate the GC physical address of this 4KB shadow page. */
1399	RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1400	/* Find ram range. */
1401	PPGMPAGE pPage;
1402	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1403	if (VBOX_SUCCESS(rc))
1404	{
1405	/*
1406	* Make shadow PTE entry.
1407	*/
1408	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1409	SHWPTE PteDst;
1410	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1411	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1412	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1413	{
1414	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1415	PteDst.n.u1Write = 0;
1416	else
1417	PteDst.u = 0;
1418	}
1419	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1420	# ifdef PGMPOOL_WITH_USER_TRACKING
1421	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1422	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1423	# endif
1424	pPTDst->a[iPTDst] = PteDst;
1425
1426
1427	# ifdef PGM_SYNC_DIRTY_BIT
1428	/*
1429	* If the page is not flagged as dirty and is writable, then make it read-only
1430	* at PD level, so we can set the dirty bit when the page is modified.
1431	*
1432	* ASSUMES that page access handlers are implemented on page table entry level.
1433	* Thus we will first catch the dirty access and set PDE.D and restart. If
1434	* there is an access handler, we'll trap again and let it work on the problem.
1435	*/
1436	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1437	* As for invlpg, it simply frees the whole shadow PT.
1438	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1439	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1440	{
1441	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1442	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1443	PdeDst.n.u1Write = 0;
1444	}
1445	else
1446	{
1447	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1448	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1449	}
1450	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1451	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1452	# else /* PAE */
1453	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1454	# endif
1455	# endif /* PGM_SYNC_DIRTY_BIT */
1456	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1457	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1458	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1459	}
1460	else
1461	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1462	}
1463	return VINF_SUCCESS;
1464	}
1465	# ifdef PGM_SYNC_ACCESSED_BIT
1466	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1467	#endif
1468	}
1469	else
1470	{
1471	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1472	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1473	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1474	}
1475
1476	/*
1477	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1478	* Yea, I'm lazy.
1479	*/
1480	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1481	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1482	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1483	# else /* PAE */
1484	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1485	# endif
1486	PGM_INVL_GUEST_TLBS();
1487	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1488
1489	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
1490
1491	# ifdef PGM_SYNC_N_PAGES
1492	/*
1493	* Get the shadow PDE, find the shadow page table in the pool.
1494	*/
1495	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1496	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1497	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1498	# else /* PAE */
1499	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1500	# endif
1501	Assert(PdeDst.n.u1Present);
1502	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1503	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1504
1505	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1506	const unsigned offPTSrc = 0;
1507	# else
1508	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1509	# endif
1510
1511	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1512	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1513	{
1514	/*
1515	* This code path is currently only taken when the caller is PGMTrap0eHandler
1516	* for non-present pages!
1517	*
1518	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1519	* deal with locality.
1520	*/
1521	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1522	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1523	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1524	iPTDst = 0;
1525	else
1526	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1527	for (; iPTDst < iPTDstEnd; iPTDst++)
1528	{
1529	if (!pPTDst->a[iPTDst].n.u1Present)
1530	{
1531	GSTPTE PteSrc;
1532
1533	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1534
1535	/* Fake the page table entry */
1536	PteSrc.u = GCPtrCurPage;
1537	PteSrc.n.u1Present = 1;
1538	PteSrc.n.u1Dirty = 1;
1539	PteSrc.n.u1Accessed = 1;
1540	PteSrc.n.u1Write = 1;
1541	PteSrc.n.u1User = 1;
1542
1543	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1544
1545	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1546	GCPtrCurPage, PteSrc.n.u1Present,
1547	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1548	PteSrc.n.u1User & PdeSrc.n.u1User,
1549	(uint64_t)PteSrc.u,
1550	(uint64_t)pPTDst->a[iPTDst].u,
1551	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1552	}
1553	}
1554	}
1555	else
1556	# endif /* PGM_SYNC_N_PAGES */
1557	{
1558	GSTPTE PteSrc;
1559	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1560	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1561
1562	/* Fake the page table entry */
1563	PteSrc.u = GCPtrCurPage;
1564	PteSrc.n.u1Present = 1;
1565	PteSrc.n.u1Dirty = 1;
1566	PteSrc.n.u1Accessed = 1;
1567	PteSrc.n.u1Write = 1;
1568	PteSrc.n.u1User = 1;
1569	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1570
1571	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1572	GCPtrPage, PteSrc.n.u1Present,
1573	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1574	PteSrc.n.u1User & PdeSrc.n.u1User,
1575	(uint64_t)PteSrc.u,
1576	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1577	}
1578	return VINF_SUCCESS;
1579
1580	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1581	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1582	return VERR_INTERNAL_ERROR;
1583	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1584	}
1585
1586
1587
1588	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1589
1590	# ifdef PGM_SYNC_DIRTY_BIT
1591
1592	/**
1593	* Investigate page fault and handle write protection page faults caused by
1594	* dirty bit tracking.
1595	*
1596	* @returns VBox status code.
1597	* @param pVM VM handle.
1598	* @param uErr Page fault error code.
1599	* @param pPdeDst Shadow page directory entry.
1600	* @param pPdeSrc Guest page directory entry.
1601	* @param GCPtrPage Guest context page address.
1602	*/
1603	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1604	{
1605	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1606	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1607
1608	/*
1609	* Real page fault?
1610	*/
1611	if ( (uErr & X86_TRAP_PF_RSVD)
1612	\|\| !pPdeSrc->n.u1Present
1613	# if PGM_WITH_NX(PGM_GST_TYPE)
1614	\|\| ((uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1615	# endif
1616	\|\| ((uErr & X86_TRAP_PF_RW) && !pPdeSrc->n.u1Write)
1617	\|\| ((uErr & X86_TRAP_PF_US) && !pPdeSrc->n.u1User) )
1618	{
1619	# ifdef IN_GC
1620	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1621	# endif
1622	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1623	LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1624
1625	if (pPdeSrc->n.u1Present)
1626	{
1627	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1628	* See the 2nd case below as well.
1629	*/
1630	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1631	{
1632	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1633	}
1634	else
1635	{
1636	/*
1637	* Map the guest page table.
1638	*/
1639	PGSTPT pPTSrc;
1640	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1641	if (VBOX_SUCCESS(rc))
1642	{
1643	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & GST_PT_MASK];
1644	const GSTPTE PteSrc = *pPteSrc;
1645	if (pPteSrc->n.u1Present)
1646	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1647	}
1648	AssertRC(rc);
1649	}
1650	}
1651	return VINF_EM_RAW_GUEST_TRAP;
1652	}
1653
1654	/*
1655	* First check the easy case where the page directory has been marked read-only to track
1656	* the dirty bit of an emulated BIG page
1657	*/
1658	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1659	{
1660	/* Mark guest page directory as accessed */
1661	pPdeSrc->b.u1Accessed = 1;
1662
1663	/*
1664	* Only write protection page faults are relevant here.
1665	*/
1666	if (uErr & X86_TRAP_PF_RW)
1667	{
1668	/* Mark guest page directory as dirty (BIG page only). */
1669	pPdeSrc->b.u1Dirty = 1;
1670
1671	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1672	{
1673	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1674
1675	Assert(pPdeSrc->b.u1Write);
1676
1677	pPdeDst->n.u1Write = 1;
1678	pPdeDst->n.u1Accessed = 1;
1679	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1680	PGM_INVL_BIG_PG(GCPtrPage);
1681	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1682	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1683	}
1684	}
1685	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1686	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1687	}
1688	/* else: 4KB page table */
1689
1690	/*
1691	* Map the guest page table.
1692	*/
1693	PGSTPT pPTSrc;
1694	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1695	if (VBOX_SUCCESS(rc))
1696	{
1697	/*
1698	* Real page fault?
1699	*/
1700	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & GST_PT_MASK];
1701	const GSTPTE PteSrc = *pPteSrc;
1702	if ( !PteSrc.n.u1Present
1703	# if PGM_WITH_NX(PGM_GST_TYPE)
1704	\|\| ((uErr & X86_TRAP_PF_ID) && !PteSrc.n.u1NoExecute)
1705	# endif
1706	\|\| ((uErr & X86_TRAP_PF_RW) && !PteSrc.n.u1Write)
1707	\|\| ((uErr & X86_TRAP_PF_US) && !PteSrc.n.u1User)
1708	)
1709	{
1710	# ifdef IN_GC
1711	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1712	# endif
1713	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1714	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1715
1716	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1717	* See the 2nd case above as well.
1718	*/
1719	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1720	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1721
1722	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1723	return VINF_EM_RAW_GUEST_TRAP;
1724	}
1725	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1726
1727	/*
1728	* Set the accessed bits in the page directory and the page table.
1729	*/
1730	pPdeSrc->n.u1Accessed = 1;
1731	pPteSrc->n.u1Accessed = 1;
1732
1733	/*
1734	* Only write protection page faults are relevant here.
1735	*/
1736	if (uErr & X86_TRAP_PF_RW)
1737	{
1738	/* Write access, so mark guest entry as dirty. */
1739	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1740	if (!pPteSrc->n.u1Dirty)
1741	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1742	else
1743	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1744	# endif
1745	pPteSrc->n.u1Dirty = 1;
1746
1747	if (pPdeDst->n.u1Present)
1748	{
1749	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1750	* Our individual shadow handlers will provide more information and force a fatal exit.
1751	*/
1752	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1753	{
1754	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1755	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1756	return VINF_SUCCESS;
1757	}
1758
1759	/*
1760	* Map shadow page table.
1761	*/
1762	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1763	if (pShwPage)
1764	{
1765	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1766	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1767	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1768	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1769	{
1770	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1771	# ifdef VBOX_STRICT
1772	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
1773	if (pPage)
1774	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
1775	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1776	# endif
1777	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1778
1779	Assert(pPteSrc->n.u1Write);
1780
1781	pPteDst->n.u1Write = 1;
1782	pPteDst->n.u1Dirty = 1;
1783	pPteDst->n.u1Accessed = 1;
1784	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1785	PGM_INVL_PG(GCPtrPage);
1786
1787	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1788	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1789	}
1790	}
1791	else
1792	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1793	}
1794	}
1795	/** @todo Optimize accessed bit emulation? */
1796	# ifdef VBOX_STRICT
1797	/*
1798	* Sanity check.
1799	*/
1800	else if ( !pPteSrc->n.u1Dirty
1801	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1802	&& pPdeDst->n.u1Present)
1803	{
1804	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1805	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1806	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1807	if ( pPteDst->n.u1Present
1808	&& pPteDst->n.u1Write)
1809	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1810	}
1811	# endif /* VBOX_STRICT */
1812	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1813	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1814	}
1815	AssertRC(rc);
1816	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1817	return rc;
1818	}
1819
1820	# endif
1821
1822	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1823
1824
1825	/**
1826	* Sync a shadow page table.
1827	*
1828	* The shadow page table is not present. This includes the case where
1829	* there is a conflict with a mapping.
1830	*
1831	* @returns VBox status code.
1832	* @param pVM VM handle.
1833	* @param iPD Page directory index.
1834	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
1835	* Assume this is a temporary mapping.
1836	* @param GCPtrPage GC Pointer of the page that caused the fault
1837	*/
1838	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
1839	{
1840	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1841	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1842	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1843
1844	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1845	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1846
1847	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1848	# error "Invalid shadow mode for 32-bit guest mode!"
1849	# endif
1850
1851	/*
1852	* Validate input a little bit.
1853	*/
1854	Assert(iPDSrc == (GCPtrPage >> GST_PD_SHIFT));
1855	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1856	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1857	# else
1858	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1859	# endif
1860	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1861	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1862	SHWPDE PdeDst = *pPdeDst;
1863
1864	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1865	/*
1866	* Check for conflicts.
1867	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1868	* HC: Simply resolve the conflict.
1869	*/
1870	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1871	{
1872	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1873	# ifndef IN_RING3
1874	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1875	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1876	return VERR_ADDRESS_CONFLICT;
1877	# else
1878	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1879	Assert(pMapping);
1880	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPDSrc);
1881	if (VBOX_FAILURE(rc))
1882	{
1883	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1884	return rc;
1885	}
1886	PdeDst = *pPdeDst;
1887	# endif
1888	}
1889	# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1890	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
1891	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
1892	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1893	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1894
1895	/*
1896	* Sync page directory entry.
1897	*/
1898	int rc = VINF_SUCCESS;
1899	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1900	if (PdeSrc.n.u1Present)
1901	{
1902	/*
1903	* Allocate & map the page table.
1904	*/
1905	PSHWPT pPTDst;
1906	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1907	PPGMPOOLPAGE pShwPage;
1908	RTGCPHYS GCPhys;
1909	if (fPageTable)
1910	{
1911	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1912	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1913	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1914	# endif
1915	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1916	}
1917	else
1918	{
1919	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1920	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1921	GCPhys \|= GCPtrPage & RT_BIT(X86_PAGE_2M_SHIFT);
1922	# endif
1923	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1924	}
1925	if (rc == VINF_SUCCESS)
1926	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1927	else if (rc == VINF_PGM_CACHED_PAGE)
1928	{
1929	/*
1930	* The PT was cached, just hook it up.
1931	*/
1932	if (fPageTable)
1933	PdeDst.u = pShwPage->Core.Key
1934	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1935	else
1936	{
1937	PdeDst.u = pShwPage->Core.Key
1938	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1939	# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumtions further down.) */
1940	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1941	{
1942	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1943	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1944	PdeDst.b.u1Write = 0;
1945	}
1946	# endif
1947	}
1948	*pPdeDst = PdeDst;
1949	return VINF_SUCCESS;
1950	}
1951	else if (rc == VERR_PGM_POOL_FLUSHED)
1952	return VINF_PGM_SYNC_CR3;
1953	else
1954	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
1955	PdeDst.u &= X86_PDE_AVL_MASK;
1956	PdeDst.u \|= pShwPage->Core.Key;
1957
1958	# ifdef PGM_SYNC_DIRTY_BIT
1959	/*
1960	* Page directory has been accessed (this is a fault situation, remember).
1961	*/
1962	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
1963	# endif
1964	if (fPageTable)
1965	{
1966	/*
1967	* Page table - 4KB.
1968	*
1969	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
1970	*/
1971	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
1972	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
1973	PGSTPT pPTSrc;
1974	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1975	if (VBOX_SUCCESS(rc))
1976	{
1977	/*
1978	* Start by syncing the page directory entry so CSAM's TLB trick works.
1979	*/
1980	PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK))
1981	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1982	*pPdeDst = PdeDst;
1983
1984	/*
1985	* Directory/page user or supervisor privilege: (same goes for read/write)
1986	*
1987	* Directory Page Combined
1988	* U/S U/S U/S
1989	* 0 0 0
1990	* 0 1 0
1991	* 1 0 0
1992	* 1 1 1
1993	*
1994	* Simple AND operation. Table listed for completeness.
1995	*
1996	*/
1997	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
1998	# ifdef PGM_SYNC_N_PAGES
1999	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2000	unsigned iPTDst = iPTBase;
2001	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2002	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2003	iPTDst = 0;
2004	else
2005	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2006	# else /* !PGM_SYNC_N_PAGES */
2007	unsigned iPTDst = 0;
2008	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2009	# endif /* !PGM_SYNC_N_PAGES */
2010	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2011	const unsigned offPTSrc = 0;
2012	# else
2013	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2014	# endif
2015	for (; iPTDst < iPTDstEnd; iPTDst++)
2016	{
2017	const unsigned iPTSrc = iPTDst + offPTSrc;
2018	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2019
2020	if (PteSrc.n.u1Present) /* we've already cleared it above */
2021	{
2022	#ifndef IN_RING0
2023	/*
2024	* Assuming kernel code will be marked as supervisor - and not as user level
2025	* and executed using a conforming code selector - And marked as readonly.
2026	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2027	*/
2028	PPGMPAGE pPage;
2029	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2030	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2031	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2032	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2033	)
2034	#endif
2035	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2036	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2037	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2038	PteSrc.n.u1Present,
2039	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2040	PteSrc.n.u1User & PdeSrc.n.u1User,
2041	(uint64_t)PteSrc.u,
2042	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2043	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2044	}
2045	} /* for PTEs */
2046	}
2047	}
2048	else
2049	{
2050	/*
2051	* Big page - 2/4MB.
2052	*
2053	* We'll walk the ram range list in parallel and optimize lookups.
2054	* We will only sync on shadow page table at a time.
2055	*/
2056	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2057
2058	/**
2059	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2060	*/
2061
2062	/*
2063	* Start by syncing the page directory entry.
2064	*/
2065	PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2066	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2067
2068	# ifdef PGM_SYNC_DIRTY_BIT
2069	/*
2070	* If the page is not flagged as dirty and is writable, then make it read-only
2071	* at PD level, so we can set the dirty bit when the page is modified.
2072	*
2073	* ASSUMES that page access handlers are implemented on page table entry level.
2074	* Thus we will first catch the dirty access and set PDE.D and restart. If
2075	* there is an access handler, we'll trap again and let it work on the problem.
2076	*/
2077	/** @todo move the above stuff to a section in the PGM documentation. */
2078	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2079	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2080	{
2081	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2082	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2083	PdeDst.b.u1Write = 0;
2084	}
2085	# endif /* PGM_SYNC_DIRTY_BIT */
2086	*pPdeDst = PdeDst;
2087
2088	/*
2089	* Fill the shadow page table.
2090	*/
2091	/* Get address and flags from the source PDE. */
2092	SHWPTE PteDstBase;
2093	PteDstBase.u = PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2094
2095	/* Loop thru the entries in the shadow PT. */
2096	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2097	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2098	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2099	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2100	PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2101	unsigned iPTDst = 0;
2102	while (iPTDst < ELEMENTS(pPTDst->a))
2103	{
2104	/* Advance ram range list. */
2105	while (pRam && GCPhys > pRam->GCPhysLast)
2106	pRam = CTXALLSUFF(pRam->pNext);
2107	if (pRam && GCPhys >= pRam->GCPhys)
2108	{
2109	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2110	do
2111	{
2112	/* Make shadow PTE. */
2113	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2114	SHWPTE PteDst;
2115
2116	/* Make sure the RAM has already been allocated. */
2117	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2118	{
2119	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2120	{
2121	# ifdef IN_RING3
2122	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2123	# else
2124	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2125	# endif
2126	if (rc != VINF_SUCCESS)
2127	return rc;
2128	}
2129	}
2130
2131	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2132	{
2133	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2134	{
2135	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2136	PteDst.n.u1Write = 0;
2137	}
2138	else
2139	PteDst.u = 0;
2140	}
2141	# ifndef IN_RING0
2142	/*
2143	* Assuming kernel code will be marked as supervisor and not as user level and executed
2144	* using a conforming code selector. Don't check for readonly, as that implies the whole
2145	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2146	*/
2147	else if ( !PdeSrc.n.u1User
2148	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2149	PteDst.u = 0;
2150	# endif
2151	else
2152	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2153	# ifdef PGMPOOL_WITH_USER_TRACKING
2154	if (PteDst.n.u1Present)
2155	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2156	# endif
2157	/* commit it */
2158	pPTDst->a[iPTDst] = PteDst;
2159	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2160	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2161	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2162
2163	/* advance */
2164	GCPhys += PAGE_SIZE;
2165	iHCPage++;
2166	iPTDst++;
2167	} while ( iPTDst < ELEMENTS(pPTDst->a)
2168	&& GCPhys <= pRam->GCPhysLast);
2169	}
2170	else if (pRam)
2171	{
2172	Log(("Invalid pages at %VGp\n", GCPhys));
2173	do
2174	{
2175	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2176	GCPhys += PAGE_SIZE;
2177	iPTDst++;
2178	} while ( iPTDst < ELEMENTS(pPTDst->a)
2179	&& GCPhys < pRam->GCPhys);
2180	}
2181	else
2182	{
2183	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2184	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2185	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2186	}
2187	} /* while more PTEs */
2188	} /* 4KB / 4MB */
2189	}
2190	else
2191	AssertRelease(!PdeDst.n.u1Present);
2192
2193	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2194	# ifdef IN_GC
2195	if (VBOX_FAILURE(rc))
2196	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2197	# endif
2198	return rc;
2199
2200	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
2201
2202	int rc = VINF_SUCCESS;
2203
2204	/*
2205	* Validate input a little bit.
2206	*/
2207	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2208	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2209	# else
2210	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2211	# endif
2212	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2213	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2214	SHWPDE PdeDst = *pPdeDst;
2215
2216	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2217	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2218
2219	GSTPDE PdeSrc;
2220	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2221	PdeSrc.n.u1Present = 1;
2222	PdeSrc.n.u1Write = 1;
2223	PdeSrc.n.u1Accessed = 1;
2224	PdeSrc.n.u1User = 1;
2225
2226	/*
2227	* Allocate & map the page table.
2228	*/
2229	PSHWPT pPTDst;
2230	PPGMPOOLPAGE pShwPage;
2231	RTGCPHYS GCPhys;
2232
2233	/* Virtual address = physical address */
2234	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2235	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2236
2237	if ( rc == VINF_SUCCESS
2238	\|\| rc == VINF_PGM_CACHED_PAGE)
2239	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2240	else
2241	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2242
2243	PdeDst.u &= X86_PDE_AVL_MASK;
2244	PdeDst.u \|= pShwPage->Core.Key;
2245	PdeDst.n.u1Present = 1;
2246	*pPdeDst = PdeDst;
2247
2248	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2249	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2250	return rc;
2251
2252	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2253
2254	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2255	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2256	return VERR_INTERNAL_ERROR;
2257	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2258	}
2259
2260
2261
2262	/**
2263	* Prefetch a page/set of pages.
2264	*
2265	* Typically used to sync commonly used pages before entering raw mode
2266	* after a CR3 reload.
2267	*
2268	* @returns VBox status code.
2269	* @param pVM VM handle.
2270	* @param GCPtrPage Page to invalidate.
2271	*/
2272	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2273	{
2274	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2275
2276	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2277	# error "Invalid shadow mode for 32-bit guest mode!"
2278	# endif
2279
2280	/*
2281	* Check that all Guest levels thru the PDE are present, getting the
2282	* PD and PDE in the processes.
2283	*/
2284	int rc = VINF_SUCCESS;
2285	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2286	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2287	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2288	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2289	# else /* PAE */
2290	unsigned iPDSrc
2291	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2292	# endif
2293	# else
2294	PGSTPD pPDSrc = NULL;
2295	const unsigned iPDSrc = 0;
2296	# endif
2297
2298	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2299	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2300	# else
2301	GSTPDE PdeSrc;
2302	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2303	PdeSrc.n.u1Present = 1;
2304	PdeSrc.n.u1Write = 1;
2305	PdeSrc.n.u1Accessed = 1;
2306	PdeSrc.n.u1User = 1;
2307	# endif
2308
2309	# ifdef PGM_SYNC_ACCESSED_BIT
2310	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2311	# else
2312	if (PdeSrc.n.u1Present)
2313	# endif
2314	{
2315	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2316	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2317	# else
2318	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2319	# endif
2320	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2321	{
2322	if (!PdeDst.n.u1Present)
2323	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2324	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2325	else
2326	{
2327	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2328	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2329	* makes no sense to prefetch more than one page.
2330	*/
2331	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2332	if (VBOX_SUCCESS(rc))
2333	rc = VINF_SUCCESS;
2334	}
2335	}
2336	}
2337	return rc;
2338
2339	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2340
2341	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2342	return VERR_INTERNAL_ERROR;
2343	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2344	}
2345
2346
2347
2348
2349	/**
2350	* Syncs a page during a PGMVerifyAccess() call.
2351	*
2352	* @returns VBox status code (informational included).
2353	* @param GCPtrPage The address of the page to sync.
2354	* @param fPage The effective guest page flags.
2355	* @param uErr The trap error code.
2356	*/
2357	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2358	{
2359	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2360
2361	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2362
2363	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2364	# error "Invalid shadow mode for 32-bit guest mode!"
2365	# endif
2366
2367	#ifndef IN_RING0
2368	if (!(fPage & X86_PTE_US))
2369	{
2370	/*
2371	* Mark this page as safe.
2372	*/
2373	/** @todo not correct for pages that contain both code and data!! */
2374	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2375	CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2376	}
2377	#endif
2378	/*
2379	* Get guest PD and index.
2380	*/
2381
2382	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2383	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2384	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2385	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2386	# else /* PAE */
2387	unsigned iPDSrc;
2388	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2389	# endif
2390	# else
2391	PGSTPD pPDSrc = NULL;
2392	const unsigned iPDSrc = 0;
2393	# endif
2394	int rc = VINF_SUCCESS;
2395
2396	/*
2397	* First check if the shadow pd is present.
2398	*/
2399	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2400	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2401	# else
2402	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2403	# endif
2404	if (!pPdeDst->n.u1Present)
2405	{
2406	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2407	AssertRC(rc);
2408	if (rc != VINF_SUCCESS)
2409	return rc;
2410	}
2411
2412	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2413	/* Check for dirty bit fault */
2414	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2415	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2416	Log(("PGMVerifyAccess: success (dirty)\n"));
2417	else
2418	{
2419	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2420	#else
2421	{
2422	GSTPDE PdeSrc;
2423	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2424	PdeSrc.n.u1Present = 1;
2425	PdeSrc.n.u1Write = 1;
2426	PdeSrc.n.u1Accessed = 1;
2427	PdeSrc.n.u1User = 1;
2428
2429	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2430	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2431	if (uErr & X86_TRAP_PF_US)
2432	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2433	else /* supervisor */
2434	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2435
2436	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2437	if (VBOX_SUCCESS(rc))
2438	{
2439	/* Page was successfully synced */
2440	Log2(("PGMVerifyAccess: success (sync)\n"));
2441	rc = VINF_SUCCESS;
2442	}
2443	else
2444	{
2445	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2446	return VINF_EM_RAW_GUEST_TRAP;
2447	}
2448	}
2449	return rc;
2450
2451	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2452
2453	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2454	return VERR_INTERNAL_ERROR;
2455	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2456	}
2457
2458
2459	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2460	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2461	/**
2462	* Figures out which kind of shadow page this guest PDE warrants.
2463	*
2464	* @returns Shadow page kind.
2465	* @param pPdeSrc The guest PDE in question.
2466	* @param cr4 The current guest cr4 value.
2467	*/
2468	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2469	{
2470	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2471	return BTH_PGMPOOLKIND_PT_FOR_PT;
2472	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2473	//{
2474	// case 0:
2475	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2476	// case X86_PDE4M_RW:
2477	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2478	// case X86_PDE4M_US:
2479	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2480	// case X86_PDE4M_RW \| X86_PDE4M_US:
2481	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2482	# if 0
2483	// case X86_PDE4M_PAE_NX:
2484	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2485	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2486	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2487	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2488	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2489	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2490	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2491	# endif
2492	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2493	//}
2494	}
2495	# endif
2496	#endif
2497
2498	#undef MY_STAM_COUNTER_INC
2499	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2500
2501
2502	/**
2503	* Syncs the paging hierarchy starting at CR3.
2504	*
2505	* @returns VBox status code, no specials.
2506	* @param pVM The virtual machine.
2507	* @param cr0 Guest context CR0 register
2508	* @param cr3 Guest context CR3 register
2509	* @param cr4 Guest context CR4 register
2510	* @param fGlobal Including global page directories or not
2511	*/
2512	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
2513	{
2514	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2515	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2516	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2517	fGlobal = true; /* Change this CR3 reload to be a global one. */
2518	# endif
2519	#endif
2520
2521	/*
2522	* Update page access handlers.
2523	* The virtual are always flushed, while the physical are only on demand.
2524	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2525	* have to look into that later because it will have a bad influence on the performance.
2526	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2527	* bird: Yes, but that won't work for aliases.
2528	*/
2529	/** @todo this MUST go away. See #1557. */
2530	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2531	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2532	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2533
2534	#ifdef PGMPOOL_WITH_MONITORING
2535	/*
2536	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2537	* Occationally we will have to clear all the shadow page tables because we wanted
2538	* to monitor a page which was mapped by too many shadowed page tables. This operation
2539	* sometimes refered to as a 'lightweight flush'.
2540	*/
2541	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2542	pgmPoolMonitorModifiedClearAll(pVM);
2543	else
2544	{
2545	# ifdef IN_RING3
2546	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2547	pgmPoolClearAll(pVM);
2548	# else
2549	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2550	return VINF_PGM_SYNC_CR3;
2551	# endif
2552	}
2553	#endif
2554
2555	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
2556	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2557
2558	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2559	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2560	/*
2561	* Get page directory addresses.
2562	*/
2563	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2564	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2565	# else
2566	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2567	# endif
2568
2569	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2570	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2571	# else /* PAE */
2572	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, 0);
2573	# endif
2574
2575	Assert(pPDSrc);
2576	#ifndef IN_GC
2577	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2578	#endif
2579
2580	/*
2581	* Iterate the page directory.
2582	*/
2583	PPGMMAPPING pMapping;
2584	unsigned iPdNoMapping;
2585	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2586	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2587
2588	/* Only check mappings if they are supposed to be put into the shadow page table. */
2589	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2590	{
2591	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2592	iPdNoMapping = (pMapping) ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U; /** PAE todo */
2593	}
2594	else
2595	{
2596	pMapping = 0;
2597	iPdNoMapping = ~0U;
2598	}
2599
2600	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2601	{
2602	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2603	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2604	# else
2605	Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2606	# endif
2607	register GSTPDE PdeSrc = pPDSrc->a[iPD];
2608	if ( PdeSrc.n.u1Present
2609	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
2610	{
2611	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2612	/*
2613	* Check for conflicts with GC mappings.
2614	*/
2615	if (iPD == iPdNoMapping)
2616	{
2617	if (pVM->pgm.s.fMappingsFixed)
2618	{
2619	/* It's fixed, just skip the mapping. */
2620	const unsigned cPTs = pMapping->cPTs;
2621	iPD += cPTs - 1;
2622	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2623	pMapping = pMapping->CTXALLSUFF(pNext);
2624	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2625	continue;
2626	}
2627
2628	# ifdef IN_RING3
2629	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2630	if (VBOX_FAILURE(rc))
2631	return rc;
2632
2633	/*
2634	* Update iPdNoMapping and pMapping.
2635	*/
2636	pMapping = pVM->pgm.s.pMappingsR3;
2637	while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2638	pMapping = pMapping->pNextR3;
2639	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2640	# else
2641	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2642	return VINF_PGM_SYNC_CR3;
2643	# endif
2644	}
2645	# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
2646	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2647	Assert(iPD != iPdNoMapping);
2648	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
2649	/*
2650	* Sync page directory entry.
2651	*
2652	* The current approach is to allocated the page table but to set
2653	* the entry to not-present and postpone the page table synching till
2654	* it's actually used.
2655	*/
2656	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2657	const unsigned iPdShw = iPD; NOREF(iPdShw);
2658	# else
2659	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2660	# endif
2661	{
2662	SHWPDE PdeDst = *pPDEDst;
2663	if (PdeDst.n.u1Present)
2664	{
2665	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2666	RTGCPHYS GCPhys;
2667	if ( !PdeSrc.b.u1Size
2668	\|\| !(cr4 & X86_CR4_PSE))
2669	{
2670	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2671	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2672	GCPhys \|= i * (PAGE_SIZE / 2);
2673	# endif
2674	}
2675	else
2676	{
2677	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2678	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2679	GCPhys \|= i * X86_PAGE_2M_SIZE;
2680	# endif
2681	}
2682
2683	if ( pShwPage->GCPhys == GCPhys
2684	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2685	&& ( pShwPage->fCached
2686	\|\| ( !fGlobal
2687	&& ( false
2688	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2689	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2690	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
2691	\|\| ( !pShwPage->fSeenNonGlobal
2692	&& (cr4 & X86_CR4_PGE))
2693	# endif
2694	)
2695	)
2696	)
2697	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
2698	\|\| ( (cr4 & X86_CR4_PSE)
2699	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
2700	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
2701	)
2702	)
2703	{
2704	# ifdef VBOX_WITH_STATISTICS
2705	if ( !fGlobal
2706	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2707	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
2708	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2709	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2710	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2711	else
2712	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2713	# endif /* VBOX_WITH_STATISTICS */
2714	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2715	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2716	//# ifdef PGMPOOL_WITH_CACHE
2717	// pgmPoolCacheUsed(pPool, pShwPage);
2718	//# endif
2719	}
2720	else
2721	{
2722	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2723	pPDEDst->u = 0;
2724	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2725	}
2726	}
2727	else
2728	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2729	pPDEDst++;
2730	}
2731	}
2732	else if (iPD != iPdNoMapping)
2733	{
2734	/*
2735	* Check if there is any page directory to mark not present here.
2736	*/
2737	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2738	const unsigned iPdShw = iPD; NOREF(iPdShw);
2739	# else
2740	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2741	# endif
2742	{
2743	if (pPDEDst->n.u1Present)
2744	{
2745	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2746	pPDEDst->u = 0;
2747	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2748	}
2749	pPDEDst++;
2750	}
2751	}
2752	else
2753	{
2754	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2755	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2756	const unsigned cPTs = pMapping->cPTs;
2757	if (pVM->pgm.s.fMappingsFixed)
2758	{
2759	/* It's fixed, just skip the mapping. */
2760	pMapping = pMapping->CTXALLSUFF(pNext);
2761	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2762	}
2763	else
2764	{
2765	/*
2766	* Check for conflicts for subsequent pagetables
2767	* and advance to the next mapping.
2768	*/
2769	iPdNoMapping = ~0U;
2770	unsigned iPT = cPTs;
2771	while (iPT-- > 1)
2772	{
2773	if ( pPDSrc->a[iPD + iPT].n.u1Present
2774	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
2775	{
2776	# ifdef IN_RING3
2777	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2778	if (VBOX_FAILURE(rc))
2779	return rc;
2780
2781	/*
2782	* Update iPdNoMapping and pMapping.
2783	*/
2784	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2785	while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2786	pMapping = pMapping->CTXALLSUFF(pNext);
2787	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2788	break;
2789	# else
2790	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2791	return VINF_PGM_SYNC_CR3;
2792	# endif
2793	}
2794	}
2795	if (iPdNoMapping == ~0U && pMapping)
2796	{
2797	pMapping = pMapping->CTXALLSUFF(pNext);
2798	if (pMapping)
2799	iPdNoMapping = pMapping->GCPtr >> X86_PD_SHIFT;
2800	}
2801	# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
2802	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2803	AssertFailed();
2804	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
2805	}
2806
2807	/* advance. */
2808	iPD += cPTs - 1;
2809	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2810	}
2811
2812	} /* for iPD */
2813	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2814	# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
2815	# endif
2816
2817	return VINF_SUCCESS;
2818
2819	#elif PGM_GST_TYPE == PGM_TYPE_PAE
2820	# if PGM_SHW_TYPE == PGM_TYPE_PAE
2821	//# error not implemented
2822	return VERR_INTERNAL_ERROR;
2823
2824	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2825	# error "Guest PAE mode, but not the shadow mode ; 32bit - maybe, but amd64 no."
2826	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2827
2828	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2829	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
2830	//# error not implemented
2831	return VERR_INTERNAL_ERROR;
2832
2833	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2834	# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
2835	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2836
2837	#else /* guest real and protected mode */
2838
2839	return VINF_SUCCESS;
2840	#endif
2841	}
2842
2843
2844
2845
2846	#ifdef VBOX_STRICT
2847	#ifdef IN_GC
2848	# undef AssertMsgFailed
2849	# define AssertMsgFailed Log
2850	#endif
2851	#ifdef IN_RING3
2852	# include <VBox/dbgf.h>
2853
2854	/**
2855	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2856	*
2857	* @returns VBox status code (VINF_SUCCESS).
2858	* @param pVM The VM handle.
2859	* @param cr3 The root of the hierarchy.
2860	* @param crr The cr4, only PAE and PSE is currently used.
2861	* @param fLongMode Set if long mode, false if not long mode.
2862	* @param cMaxDepth Number of levels to dump.
2863	* @param pHlp Pointer to the output functions.
2864	*/
2865	__BEGIN_DECLS
2866	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
2867	__END_DECLS
2868
2869	#endif
2870
2871	/**
2872	* Checks that the shadow page table is in sync with the guest one.
2873	*
2874	* @returns The number of errors.
2875	* @param pVM The virtual machine.
2876	* @param cr3 Guest context CR3 register
2877	* @param cr4 Guest context CR4 register
2878	* @param GCPtr Where to start. Defaults to 0.
2879	* @param cb How much to check. Defaults to everything.
2880	*/
2881	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
2882	{
2883	unsigned cErrors = 0;
2884
2885	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2886
2887	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2888	# error "Invalid shadow mode for 32-bit guest paging."
2889	# endif
2890
2891	PPGM pPGM = &pVM->pgm.s;
2892	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
2893	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
2894	RTHCPHYS HCPhys; /* general usage. */
2895	int rc;
2896
2897	/*
2898	* Check that the Guest CR3 and all it's mappings are correct.
2899	*/
2900	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
2901	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
2902	false);
2903	rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
2904	AssertRCReturn(rc, 1);
2905	HCPhys = NIL_RTHCPHYS;
2906	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
2907	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
2908	# ifdef IN_RING3
2909	RTGCPHYS GCPhys;
2910	rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
2911	AssertRCReturn(rc, 1);
2912	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
2913	# endif
2914	const X86PD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
2915
2916	/*
2917	* Get and check the Shadow CR3.
2918	*/
2919	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2920	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
2921	unsigned cPDEs = ELEMENTS(pPDDst->a);
2922	# else
2923	const X86PDPAE pPDDst = pPGM->CTXMID(ap,PaePDs[0]); / use it as a 2048 entry PD */
2924	unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
2925	# endif
2926	if (cb != ~(RTGCUINTPTR)0)
2927	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
2928
2929	/** @todo call the other two PGMAssert() functions. /
2930
2931	/*
2932	* Iterate the shadow page directory.
2933	*/
2934	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
2935	unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
2936	cPDEs += iPDDst;
2937	for (;
2938	iPDDst < cPDEs;
2939	iPDDst++, GCPtr += _4G / cPDEs)
2940	{
2941	const SHWPDE PdeDst = pPDDst->a[iPDDst];
2942	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2943	{
2944	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2945	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
2946	{
2947	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
2948	cErrors++;
2949	continue;
2950	}
2951	}
2952	else if ( (PdeDst.u & X86_PDE_P)
2953	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
2954	)
2955	{
2956	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
2957	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
2958	if (!pPoolPage)
2959	{
2960	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
2961	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
2962	cErrors++;
2963	continue;
2964	}
2965	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
2966
2967	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
2968	{
2969	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
2970	GCPtr, (uint64_t)PdeDst.u));
2971	cErrors++;
2972	}
2973
2974	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
2975	{
2976	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
2977	GCPtr, (uint64_t)PdeDst.u));
2978	cErrors++;
2979	}
2980
2981	const X86PDE PdeSrc = pPDSrc->a[iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)];
2982	if (!PdeSrc.n.u1Present)
2983	{
2984	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
2985	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
2986	cErrors++;
2987	continue;
2988	}
2989
2990	if ( !PdeSrc.b.u1Size
2991	\|\| !(cr4 & X86_CR4_PSE))
2992	{
2993	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
2994	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2995	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2996	# endif
2997	}
2998	else
2999	{
3000	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3001	{
3002	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3003	GCPtr, (uint64_t)PdeSrc.u));
3004	cErrors++;
3005	continue;
3006	}
3007	GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3008	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3009	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3010	# endif
3011	}
3012
3013	if ( pPoolPage->enmKind
3014	!= (!PdeSrc.b.u1Size \|\| !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3015	{
3016	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3017	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3018	cErrors++;
3019	}
3020
3021	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3022	if (!pPhysPage)
3023	{
3024	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3025	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3026	cErrors++;
3027	continue;
3028	}
3029
3030	if (GCPhysGst != pPoolPage->GCPhys)
3031	{
3032	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3033	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3034	cErrors++;
3035	continue;
3036	}
3037
3038	if ( !PdeSrc.b.u1Size
3039	\|\| !(cr4 & X86_CR4_PSE))
3040	{
3041	/*
3042	* Page Table.
3043	*/
3044	const GSTPT *pPTSrc;
3045	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3046	if (VBOX_FAILURE(rc))
3047	{
3048	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3049	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3050	cErrors++;
3051	continue;
3052	}
3053	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3054	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3055	{
3056	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3057	// (This problem will go away when/if we shadow multiple CR3s.)
3058	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3059	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3060	cErrors++;
3061	continue;
3062	}
3063	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3064	{
3065	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3066	GCPtr, (uint64_t)PdeDst.u));
3067	cErrors++;
3068	continue;
3069	}
3070
3071	/* iterate the page table. */
3072	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3073	const unsigned offPTSrc = 0;
3074	# else
3075	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3076	# endif
3077	for (unsigned iPT = 0, off = 0;
3078	iPT < ELEMENTS(pPTDst->a);
3079	iPT++, off += PAGE_SIZE)
3080	{
3081	const SHWPTE PteDst = pPTDst->a[iPT];
3082
3083	/* skip not-present entries. */
3084	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3085	continue;
3086	Assert(PteDst.n.u1Present);
3087
3088	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3089	if (!PteSrc.n.u1Present)
3090	{
3091	#ifdef IN_RING3
3092	PGMAssertHandlerAndFlagsInSync(pVM);
3093	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3094	#endif
3095	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3096	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3097	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3098	cErrors++;
3099	continue;
3100	}
3101
3102	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3103	# if 1 /** @todo sync accessed bit properly... */
3104	fIgnoreFlags \|= X86_PTE_A;
3105	# endif
3106
3107	/* match the physical addresses */
3108	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3109	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3110
3111	# ifdef IN_RING3
3112	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3113	if (VBOX_FAILURE(rc))
3114	{
3115	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3116	{
3117	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3118	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3119	cErrors++;
3120	continue;
3121	}
3122	}
3123	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3124	{
3125	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3126	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3127	cErrors++;
3128	continue;
3129	}
3130	# endif
3131
3132	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3133	if (!pPhysPage)
3134	{
3135	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3136	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3137	{
3138	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3139	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3140	cErrors++;
3141	continue;
3142	}
3143	# endif
3144	if (PteDst.n.u1Write)
3145	{
3146	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3147	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3148	cErrors++;
3149	}
3150	fIgnoreFlags \|= X86_PTE_RW;
3151	}
3152	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3153	{
3154	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3155	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3156	cErrors++;
3157	continue;
3158	}
3159
3160	/* flags */
3161	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3162	{
3163	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3164	{
3165	if (PteDst.n.u1Write)
3166	{
3167	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3168	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3169	cErrors++;
3170	continue;
3171	}
3172	fIgnoreFlags \|= X86_PTE_RW;
3173	}
3174	else
3175	{
3176	if (PteDst.n.u1Present)
3177	{
3178	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3179	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3180	cErrors++;
3181	continue;
3182	}
3183	fIgnoreFlags \|= X86_PTE_P;
3184	}
3185	}
3186	else
3187	{
3188	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3189	{
3190	if (PteDst.n.u1Write)
3191	{
3192	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3193	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3194	cErrors++;
3195	continue;
3196	}
3197	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3198	{
3199	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3200	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3201	cErrors++;
3202	continue;
3203	}
3204	if (PteDst.n.u1Dirty)
3205	{
3206	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3207	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3208	cErrors++;
3209	}
3210	# if 0 /** @todo sync access bit properly... */
3211	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3212	{
3213	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3214	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3215	cErrors++;
3216	}
3217	fIgnoreFlags \|= X86_PTE_RW;
3218	# else
3219	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3220	# endif
3221	}
3222	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3223	{
3224	/* access bit emulation (not implemented). */
3225	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3226	{
3227	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3228	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3229	cErrors++;
3230	continue;
3231	}
3232	if (!PteDst.n.u1Accessed)
3233	{
3234	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3235	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3236	cErrors++;
3237	}
3238	fIgnoreFlags \|= X86_PTE_P;
3239	}
3240	# ifdef DEBUG_sandervl
3241	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3242	# endif
3243	}
3244
3245	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3246	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3247	)
3248	{
3249	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3250	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3251	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3252	cErrors++;
3253	continue;
3254	}
3255	} /* foreach PTE */
3256	}
3257	else
3258	{
3259	/*
3260	* Big Page.
3261	*/
3262	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| X86_PDE_PAE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3263	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3264	{
3265	if (PdeDst.n.u1Write)
3266	{
3267	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3268	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3269	cErrors++;
3270	continue;
3271	}
3272	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3273	{
3274	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3275	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3276	cErrors++;
3277	continue;
3278	}
3279	# if 0 /** @todo sync access bit properly... */
3280	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3281	{
3282	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3283	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3284	cErrors++;
3285	}
3286	fIgnoreFlags \|= X86_PTE_RW;
3287	# else
3288	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3289	# endif
3290	}
3291	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3292	{
3293	/* access bit emulation (not implemented). */
3294	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3295	{
3296	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3297	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3298	cErrors++;
3299	continue;
3300	}
3301	if (!PdeDst.n.u1Accessed)
3302	{
3303	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3304	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3305	cErrors++;
3306	}
3307	fIgnoreFlags \|= X86_PTE_P;
3308	}
3309
3310	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3311	{
3312	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3313	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3314	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3315	cErrors++;
3316	}
3317
3318	/* iterate the page table. */
3319	for (unsigned iPT = 0, off = 0;
3320	iPT < ELEMENTS(pPTDst->a);
3321	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3322	{
3323	const SHWPTE PteDst = pPTDst->a[iPT];
3324
3325	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3326	{
3327	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3328	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3329	cErrors++;
3330	}
3331
3332	/* skip not-present entries. */
3333	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3334	continue;
3335
3336	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3337
3338	/* match the physical addresses */
3339	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3340
3341	# ifdef IN_RING3
3342	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3343	if (VBOX_FAILURE(rc))
3344	{
3345	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3346	{
3347	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3348	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3349	cErrors++;
3350	}
3351	}
3352	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3353	{
3354	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3355	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3356	cErrors++;
3357	continue;
3358	}
3359	# endif
3360
3361	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3362	if (!pPhysPage)
3363	{
3364	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3365	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3366	{
3367	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3368	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3369	cErrors++;
3370	continue;
3371	}
3372	# endif
3373	if (PteDst.n.u1Write)
3374	{
3375	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3376	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3377	cErrors++;
3378	}
3379	fIgnoreFlags \|= X86_PTE_RW;
3380	}
3381	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
3382	{
3383	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3384	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3385	cErrors++;
3386	continue;
3387	}
3388
3389	/* flags */
3390	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3391	{
3392	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3393	{
3394	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
3395	{
3396	if (PteDst.n.u1Write)
3397	{
3398	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3399	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3400	cErrors++;
3401	continue;
3402	}
3403	fIgnoreFlags \|= X86_PTE_RW;
3404	}
3405	}
3406	else
3407	{
3408	if (PteDst.n.u1Present)
3409	{
3410	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3411	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3412	cErrors++;
3413	continue;
3414	}
3415	fIgnoreFlags \|= X86_PTE_P;
3416	}
3417	}
3418
3419	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3420	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3421	)
3422	{
3423	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3424	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3425	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3426	cErrors++;
3427	continue;
3428	}
3429	} /* foreach PTE */
3430	}
3431	}
3432	/* not present */
3433
3434	} /* forearch PDE */
3435
3436	# ifdef DEBUG
3437	if (cErrors)
3438	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3439	# endif
3440
3441	#elif PGM_GST_TYPE == PGM_TYPE_PAE
3442	//# error not implemented
3443
3444
3445	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3446	//# error not implemented
3447
3448	/#else: guest real and protected mode /
3449	#endif
3450	return cErrors;
3451	}
3452	#endif /* VBOX_STRICT */
3453

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 7666

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