Changeset 7666 in vbox

Timestamp:

Mar 31, 2008 3:02:43 PM (17 years ago)

Author:

vboxsync

Message:

Put back the original PAE defines. AMD differs from Intel wrt valid pae & long mode physical address bits.

Location:

trunk

Files:

• include/VBox/x86.h (modified) (2 diffs)
• src/VBox/VMM/VMMAll/PGMAllBth.h (modified) (3 diffs)
• src/VBox/VMM/VMMAll/PGMAllGst.h (modified) (2 diffs)

trunk/include/VBox/x86.h

@@ -899 +899 @@
 #define X86_PTE_PG_MASK                     ( 0xfffff000 )
 
-/** Bits 12-51 - - PAE - Physical Page number of the next level. */
+/** Bits 12-36 - - PAE - Physical Page number of the next level. */
 #if 1 /* we're using this internally and have to mask of the top 16-bit. */
 #define X86_PTE_PAE_PG_MASK                 ( 0x0000fffffffff000ULL )
@@ -1210 +1210 @@
 #define X86_PDE4M_PG_HIGH_SHIFT             19
 
-/** Bits 21-36 - - PAE - Physical Page number. */
-#define X86_PDE2M_PAE_PG_MASK               ( 0x0000000fffe00000ULL )
-/** Bits 63 - NX - PAE - No execution flag. */
-#define X86_PDE2M_PAE_NX                    RT_BIT_64(63)
-
-/** Bits 21-39 - - AMD64 - Physical Page number. (bits 40-51 are reserved) */
-#define X86_PDE2M_AMD64_PG_MASK             ( 0x000000ffffe00000ULL )
-/** Bits 63 - NX - AMD64 - No execution flag. */
-#define X86_PDE2M_AMD64_NX                  X86_PDE2M_PAE_NX
+/** Bits 21-51 - - PAE & AMD64 - Physical Page number. (bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more) */
+#define X86_PDE2M_PAE_PG_MASK               ( 0x000fffffffe00000ULL )
+/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
+#define X86_PDE2M_PAE_NX                    X86_PDE2M_PAE_NX
 
 /**

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -864 +864 @@
             PPGMPOOLPAGE    pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
             RTGCPHYS        GCPhys   = PdeSrc.u & GST_PDE_PG_MASK;
-#  if PGM_SHW_TYPE != PGM_TYPE_32BIT
+#  if    PGM_SHW_TYPE != PGM_TYPE_32BIT \
+      && PGM_GST_TYPE == PGM_TYPE_32BIT    
+            /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
             GCPhys |= (iPDDst & 1) * (PAGE_SIZE/2);
 #  endif
@@ -1269 +1271 @@
     {
         GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
-# if PGM_SHW_TYPE != PGM_TYPE_32BIT
+#  if    PGM_SHW_TYPE != PGM_TYPE_32BIT \
+      && PGM_GST_TYPE == PGM_TYPE_32BIT    
+            /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
+        /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
         GCPhys |= (iPDDst & 1) * (PAGE_SIZE/2);
 # endif
@@ -1278 +1283 @@
 #  if    PGM_SHW_TYPE != PGM_TYPE_32BIT \
       && PGM_GST_TYPE == PGM_TYPE_32BIT
-        /* Select the right PDE as we're emulating a 4MB page with two 2 MB shadow PDEs */
+        /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs */
         GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
 # endif

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -62 +62 @@
 # define GST_PT_MASK                X86_PT_MASK
 # define GST_CR3_PAGE_MASK          X86_CR3_PAGE_MASK
-#elif PGM_GST_TYPE == PGM_TYPE_PAE
+#elif   PGM_GST_TYPE == PGM_TYPE_PAE \
+     || PGM_GST_TYPE == PGM_TYPE_AMD64
 # define GSTPT                      X86PTPAE
 # define PGSTPT                     PX86PTPAE
@@ -78 +79 @@
 # define GST_PD_MASK                X86_PD_PAE_MASK
 # define GST_TOTAL_PD_ENTRIES       (X86_PG_PAE_ENTRIES*4)
-# define GST_PTE_PG_MASK            X86_PTE_PAE_PG_MASK
-# define GST_PT_SHIFT               X86_PT_PAE_SHIFT
-# define GST_PT_MASK                X86_PT_PAE_MASK
-# define GST_CR3_PAGE_MASK          X86_CR3_PAE_PAGE_MASK
-#elif PGM_GST_TYPE == PGM_TYPE_AMD64
-/* @todo */
-# define GSTPT                      X86PTPAE
-# define PGSTPT                     PX86PTPAE
-# define GSTPTE                     X86PTEPAE
-# define PGSTPTE                    PX86PTEPAE
-# define GSTPD                      X86PDPAE
-# define PGSTPD                     PX86PDPAE
-# define GSTPDE                     X86PDEPAE
-# define PGSTPDE                    PX86PDEPAE
-# define GST_BIG_PAGE_SIZE          X86_PAGE_2M_SIZE
-# define GST_BIG_PAGE_OFFSET_MASK   X86_PAGE_2M_OFFSET_MASK
-# define GST_PDE_PG_MASK            X86_PDE_PAE_PG_MASK
-# define GST_PDE_BIG_PG_MASK        X86_PDE2M_AMD64_PG_MASK
-# define GST_PD_SHIFT               X86_PD_PAE_SHIFT
-# define GST_PD_MASK                X86_PD_PAE_MASK
-# define GST_TOTAL_PD_ENTRIES       (X86_PG_PAE_ENTRIES*512)
 # define GST_PTE_PG_MASK            X86_PTE_PAE_PG_MASK
 # define GST_PT_SHIFT               X86_PT_PAE_SHIFT