PGMAllBth.h@ 9682

Last change on this file since 9682 was 9682, checked in by vboxsync, 17 years ago
Long mode paging updates
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1	/* $Id: PGMAllBth.h 9682 2008-06-13 13:27:40Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
46	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED
47	# error "Invalid combination; PAE guest implies PAE shadow"
48	#endif
49
50	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
51	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED)
52	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
53	#endif
54
55	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
56	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED)
57	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED) \
61	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
62	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
63	#endif
64
65	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
66	# define PGM_WITHOUT_MAPPINGS
67	#endif
68
69	/**
70	* #PF Handler for raw-mode guest execution.
71	*
72	* @returns VBox status code (appropriate for trap handling and GC return).
73	* @param pVM VM Handle.
74	* @param uErr The trap error code.
75	* @param pRegFrame Trap register frame.
76	* @param pvFault The fault address.
77	*/
78	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
79	{
80	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
81	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
82
83	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
84	/*
85	* Hide the instruction fetch trap indicator for now.
86	*/
87	/** @todo NXE will change this and we must fix NXE in the switcher too! */
88	if (uErr & X86_TRAP_PF_ID)
89	{
90	uErr &= ~X86_TRAP_PF_ID;
91	TRPMSetErrorCode(pVM, uErr);
92	}
93	# endif
94
95	/*
96	* Get PDs.
97	*/
98	int rc;
99	# if PGM_WITH_PAGING(PGM_GST_TYPE)
100	# if PGM_GST_TYPE == PGM_TYPE_32BIT
101	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
102	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
103
104	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
105
106	# if PGM_GST_TYPE == PGM_TYPE_PAE
107	unsigned iPDSrc;
108	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
109
110	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
111	unsigned iPDSrc;
112	PX86PML4E pPml4eSrc;
113	X86PDPE PdpeSrc;
114	PGSTPD pPDSrc;
115
116	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
117	Assert(pPml4eSrc);
118	# endif
119	/* Quick check for a valid guest trap. */
120	if (!pPDSrc)
121	{
122	LogFlow(("Trap0eHandler: guest PDPTR not present CR3=%VGp\n", (CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK)));
123	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eGuestTrap; });
124	TRPMSetErrorCode(pVM, uErr);
125	return VINF_EM_RAW_GUEST_TRAP;
126	}
127	# endif
128	# else
129	PGSTPD pPDSrc = NULL;
130	const unsigned iPDSrc = 0;
131	# endif
132
133	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
134	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
135	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
136	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
137	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
138	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
139
140	# if PGM_GST_TYPE == PGM_TYPE_PAE
141	/* Did we mark the PDPT as not present in SyncCR3? */
142	unsigned iPDPTE = ((RTGCUINTPTR)pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
143	if (!pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present)
144	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present = 1;
145
146	# endif
147
148	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
149	const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
150	PX86PDPAE pPDDst;
151	# if PGM_GST_TYPE == PGM_TYPE_PROT
152	/* AMD-V nested paging */
153	X86PML4E Pml4eSrc;
154	X86PDPE PdpeSrc;
155	PX86PML4E pPml4eSrc = &Pml4eSrc;
156
157	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
158	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
159	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
160	# endif
161
162	rc = PGMShwSyncLongModePDPtr(pVM, (RTGCUINTPTR)pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
163	if (rc != VINF_SUCCESS)
164	{
165	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
166	return rc;
167	}
168	Assert(pPDDst);
169	# endif
170
171	# if PGM_WITH_PAGING(PGM_GST_TYPE)
172	/*
173	* If we successfully correct the write protection fault due to dirty bit
174	* tracking, or this page fault is a genuine one, then return immediately.
175	*/
176	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
177	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
178	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
179	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
180	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
181	{
182	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
183	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
184	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
185	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
186	}
187
188	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
189	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
190
191	/*
192	* A common case is the not-present error caused by lazy page table syncing.
193	*
194	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
195	* so we can safely assume that the shadow PT is present when calling SyncPage later.
196	*
197	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
198	* of mapping conflict and defer to SyncCR3 in R3.
199	* (Again, we do NOT support access handlers for non-present guest pages.)
200	*
201	*/
202	# if PGM_WITH_PAGING(PGM_GST_TYPE)
203	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
204	# else
205	GSTPDE PdeSrc;
206	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
207	PdeSrc.n.u1Present = 1;
208	PdeSrc.n.u1Write = 1;
209	PdeSrc.n.u1Accessed = 1;
210	PdeSrc.n.u1User = 1;
211	# endif
212	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
213	&& !pPDDst->a[iPDDst].n.u1Present
214	&& PdeSrc.n.u1Present
215	)
216
217	{
218	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
219	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
220	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
221	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
222	if (VBOX_SUCCESS(rc))
223	{
224	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
225	return rc;
226	}
227	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
228	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
229	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
230	return VINF_PGM_SYNC_CR3;
231	}
232
233	# if PGM_WITH_PAGING(PGM_GST_TYPE)
234	/*
235	* Check if this address is within any of our mappings.
236	*
237	* This is very fast and it's gonna save us a bit of effort below and prevent
238	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
239	* (BTW, it's impossible to have physical access handlers in a mapping.)
240	*/
241	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
242	{
243	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
244	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
245	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
246	{
247	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
248	break;
249	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
250	{
251	/*
252	* The first thing we check is if we've got an undetected conflict.
253	*/
254	if (!pVM->pgm.s.fMappingsFixed)
255	{
256	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
257	while (iPT-- > 0)
258	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
259	{
260	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
261	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
262	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
263	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
264	return VINF_PGM_SYNC_CR3;
265	}
266	}
267
268	/*
269	* Check if the fault address is in a virtual page access handler range.
270	*/
271	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
272	if ( pCur
273	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
274	&& uErr & X86_TRAP_PF_RW)
275	{
276	# ifdef IN_GC
277	STAM_PROFILE_START(&pCur->Stat, h);
278	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
279	STAM_PROFILE_STOP(&pCur->Stat, h);
280	# else
281	AssertFailed();
282	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
283	# endif
284	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
285	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
286	return rc;
287	}
288
289	/*
290	* Pretend we're not here and let the guest handle the trap.
291	*/
292	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
293	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
294	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
295	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
296	return VINF_EM_RAW_GUEST_TRAP;
297	}
298	}
299	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
300	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
301	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
302
303	/*
304	* Check if this fault address is flagged for special treatment,
305	* which means we'll have to figure out the physical address and
306	* check flags associated with it.
307	*
308	* ASSUME that we can limit any special access handling to pages
309	* in page tables which the guest believes to be present.
310	*/
311	if (PdeSrc.n.u1Present)
312	{
313	RTGCPHYS GCPhys = NIL_RTGCPHYS;
314
315	# if PGM_WITH_PAGING(PGM_GST_TYPE)
316	# if PGM_GST_TYPE == PGM_TYPE_AMD64
317	bool fBigPagesSupported = true;
318	# else
319	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
320	# endif
321	if ( PdeSrc.b.u1Size
322	&& fBigPagesSupported)
323	GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
324	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
325	else
326	{
327	PGSTPT pPTSrc;
328	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
329	if (VBOX_SUCCESS(rc))
330	{
331	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
332	if (pPTSrc->a[iPTESrc].n.u1Present)
333	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
334	}
335	}
336	# else
337	/* No paging so the fault address is the physical address */
338	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
339	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
340
341	/*
342	* If we have a GC address we'll check if it has any flags set.
343	*/
344	if (GCPhys != NIL_RTGCPHYS)
345	{
346	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
347
348	PPGMPAGE pPage;
349	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
350	if (VBOX_SUCCESS(rc))
351	{
352	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
353	{
354	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
355	{
356	/*
357	* Physical page access handler.
358	*/
359	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
360	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
361	if (pCur)
362	{
363	# ifdef PGM_SYNC_N_PAGES
364	/*
365	* If the region is write protected and we got a page not present fault, then sync
366	* the pages. If the fault was caused by a read, then restart the instruction.
367	* In case of write access continue to the GC write handler.
368	*
369	* ASSUMES that there is only one handler per page or that they have similar write properties.
370	*/
371	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
372	&& !(uErr & X86_TRAP_PF_P))
373	{
374	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
375	if ( VBOX_FAILURE(rc)
376	\|\| !(uErr & X86_TRAP_PF_RW)
377	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
378	{
379	AssertRC(rc);
380	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
381	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
382	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
383	return rc;
384	}
385	}
386	# endif
387
388	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
389	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
390	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
391
392	#if defined(IN_GC) \|\| defined(IN_RING0)
393	if (CTXALLSUFF(pCur->pfnHandler))
394	{
395	STAM_PROFILE_START(&pCur->Stat, h);
396	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
397	STAM_PROFILE_STOP(&pCur->Stat, h);
398	}
399	else
400	#endif
401	rc = VINF_EM_RAW_EMULATE_INSTR;
402	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
403	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
404	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
405	return rc;
406	}
407	}
408	# if PGM_WITH_PAGING(PGM_GST_TYPE)
409	else
410	{
411	# ifdef PGM_SYNC_N_PAGES
412	/*
413	* If the region is write protected and we got a page not present fault, then sync
414	* the pages. If the fault was caused by a read, then restart the instruction.
415	* In case of write access continue to the GC write handler.
416	*/
417	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
418	&& !(uErr & X86_TRAP_PF_P))
419	{
420	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
421	if ( VBOX_FAILURE(rc)
422	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
423	\|\| !(uErr & X86_TRAP_PF_RW))
424	{
425	AssertRC(rc);
426	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
427	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
428	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
429	return rc;
430	}
431	}
432	# endif
433	/*
434	* Ok, it's an virtual page access handler.
435	*
436	* Since it's faster to search by address, we'll do that first
437	* and then retry by GCPhys if that fails.
438	*/
439	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
440	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
441	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
442	*/
443	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
444	if (pCur)
445	{
446	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
447	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
448	\|\| !(uErr & X86_TRAP_PF_P)
449	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
450	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
451
452	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
453	&& ( uErr & X86_TRAP_PF_RW
454	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
455	{
456	# ifdef IN_GC
457	STAM_PROFILE_START(&pCur->Stat, h);
458	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
459	STAM_PROFILE_STOP(&pCur->Stat, h);
460	# else
461	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
462	# endif
463	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
464	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
465	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
466	return rc;
467	}
468	/* Unhandled part of a monitored page */
469	}
470	else
471	{
472	/* Check by physical address. */
473	PPGMVIRTHANDLER pCur;
474	unsigned iPage;
475	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
476	&pCur, &iPage);
477	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
478	if ( pCur
479	&& ( uErr & X86_TRAP_PF_RW
480	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
481	{
482	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
483	# ifdef IN_GC
484	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
485	Assert(off < pCur->cb);
486	STAM_PROFILE_START(&pCur->Stat, h);
487	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
488	STAM_PROFILE_STOP(&pCur->Stat, h);
489	# else
490	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
491	# endif
492	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
493	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
494	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
495	return rc;
496	}
497	}
498	}
499	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
500
501	/*
502	* There is a handled area of the page, but this fault doesn't belong to it.
503	* We must emulate the instruction.
504	*
505	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
506	* we first check if this was a page-not-present fault for a page with only
507	* write access handlers. Restart the instruction if it wasn't a write access.
508	*/
509	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
510
511	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
512	&& !(uErr & X86_TRAP_PF_P))
513	{
514	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
515	if ( VBOX_FAILURE(rc)
516	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
517	\|\| !(uErr & X86_TRAP_PF_RW))
518	{
519	AssertRC(rc);
520	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
521	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
522	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
523	return rc;
524	}
525	}
526
527	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
528	* It's writing to an unhandled part of the LDT page several million times.
529	*/
530	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
531	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
532	rc, pPage->HCPhys,
533	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
534	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
535	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
536	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
537	return rc;
538	} /* if any kind of handler */
539
540	# if PGM_WITH_PAGING(PGM_GST_TYPE)
541	if (uErr & X86_TRAP_PF_P)
542	{
543	/*
544	* The page isn't marked, but it might still be monitored by a virtual page access handler.
545	* (ASSUMES no temporary disabling of virtual handlers.)
546	*/
547	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
548	* we should correct both the shadow page table and physical memory flags, and not only check for
549	* accesses within the handler region but for access to pages with virtual handlers. */
550	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
551	if (pCur)
552	{
553	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
554	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
555	\|\| !(uErr & X86_TRAP_PF_P)
556	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
557	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
558
559	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
560	&& ( uErr & X86_TRAP_PF_RW
561	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
562	{
563	# ifdef IN_GC
564	STAM_PROFILE_START(&pCur->Stat, h);
565	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
566	STAM_PROFILE_STOP(&pCur->Stat, h);
567	# else
568	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
569	# endif
570	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
571	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
572	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
573	return rc;
574	}
575	}
576	}
577	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
578	}
579	else
580	{
581	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
582	* back to the recompiler to emulate the instruction.
583	*/
584	LogFlow(("pgmPhysGetPageEx %VGp failed with %Vrc\n", GCPhys, rc));
585	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersInvalid);
586	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
587	return VINF_EM_RAW_EMULATE_INSTR;
588	}
589
590	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
591
592	# ifdef PGM_OUT_OF_SYNC_IN_GC
593	/*
594	* We are here only if page is present in Guest page tables and trap is not handled
595	* by our handlers.
596	* Check it for page out-of-sync situation.
597	*/
598	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
599
600	if (!(uErr & X86_TRAP_PF_P))
601	{
602	/*
603	* Page is not present in our page tables.
604	* Try to sync it!
605	* BTW, fPageShw is invalid in this branch!
606	*/
607	if (uErr & X86_TRAP_PF_US)
608	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
609	else /* supervisor */
610	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
611
612	# if defined(LOG_ENABLED) && !defined(IN_RING0)
613	RTGCPHYS GCPhys;
614	uint64_t fPageGst;
615	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
616	Log(("Page out of sync: %VGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
617	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
618	# endif /* LOG_ENABLED */
619
620	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
621	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
622	{
623	uint64_t fPageGst;
624	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
625	if ( VBOX_SUCCESS(rc)
626	&& !(fPageGst & X86_PTE_US))
627	{
628	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
629	if ( pvFault == (RTGCPTR)pRegFrame->eip
630	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
631	# ifdef CSAM_DETECT_NEW_CODE_PAGES
632	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
633	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
634	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
635	)
636	{
637	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
638	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
639	if (rc != VINF_SUCCESS)
640	{
641	/*
642	* CSAM needs to perform a job in ring 3.
643	*
644	* Sync the page before going to the host context; otherwise we'll end up in a loop if
645	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
646	*/
647	LogFlow(("CSAM ring 3 job\n"));
648	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
649	AssertRC(rc2);
650
651	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
652	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
653	return rc;
654	}
655	}
656	# ifdef CSAM_DETECT_NEW_CODE_PAGES
657	else
658	if ( uErr == X86_TRAP_PF_RW
659	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
660	&& pRegFrame->ecx < 0x10000
661	)
662	{
663	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
664	* to detect loading of new code pages.
665	*/
666
667	/*
668	* Decode the instruction.
669	*/
670	RTGCPTR PC;
671	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
672	if (rc == VINF_SUCCESS)
673	{
674	DISCPUSTATE Cpu;
675	uint32_t cbOp;
676	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
677
678	/* For now we'll restrict this to rep movsw/d instructions */
679	if ( rc == VINF_SUCCESS
680	&& Cpu.pCurInstr->opcode == OP_MOVSWD
681	&& (Cpu.prefix & PREFIX_REP))
682	{
683	CSAMMarkPossibleCodePage(pVM, pvFault);
684	}
685	}
686	}
687	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
688
689	/*
690	* Mark this page as safe.
691	*/
692	/** @todo not correct for pages that contain both code and data!! */
693	Log2(("CSAMMarkPage %VGv; scanned=%d\n", pvFault, true));
694	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
695	}
696	}
697	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
698	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
699	if (VBOX_SUCCESS(rc))
700	{
701	/* The page was successfully synced, return to the guest. */
702	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
703	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
704	return VINF_SUCCESS;
705	}
706	}
707	else
708	{
709	/*
710	* A side effect of not flushing global PDEs are out of sync pages due
711	* to physical monitored regions, that are no longer valid.
712	* Assume for now it only applies to the read/write flag
713	*/
714	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
715	{
716	if (uErr & X86_TRAP_PF_US)
717	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
718	else /* supervisor */
719	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
720
721
722	/*
723	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
724	*/
725	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
726	if (VBOX_SUCCESS(rc))
727	{
728	/*
729	* Page was successfully synced, return to guest.
730	*/
731	# ifdef VBOX_STRICT
732	RTGCPHYS GCPhys;
733	uint64_t fPageGst;
734	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
735	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
736	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
737
738	uint64_t fPageShw;
739	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
740	AssertMsg(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Vrc fPageShw=%VX64\n", rc, fPageShw));
741	# endif /* VBOX_STRICT */
742	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
743	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
744	return VINF_SUCCESS;
745	}
746
747	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
748	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
749	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP\|X86_CR0_PG)) == X86_CR0_PG)
750	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
751	{
752	uint64_t fPageGst;
753	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
754	if ( VBOX_SUCCESS(rc)
755	&& !(fPageGst & X86_PTE_RW))
756	{
757	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
758	if (VBOX_SUCCESS(rc))
759	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulGC);
760	else
761	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulR3);
762	return rc;
763	}
764	else
765	AssertMsgFailed(("Unexpected r/w page %x flag=%x\n", pvFault, (uint32_t)fPageGst));
766	}
767
768	}
769
770	# if PGM_WITH_PAGING(PGM_GST_TYPE)
771	# ifdef VBOX_STRICT
772	/*
773	* Check for VMM page flags vs. Guest page flags consistency.
774	* Currently only for debug purposes.
775	*/
776	if (VBOX_SUCCESS(rc))
777	{
778	/* Get guest page flags. */
779	uint64_t fPageGst;
780	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
781	if (VBOX_SUCCESS(rc))
782	{
783	uint64_t fPageShw;
784	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
785
786	/*
787	* Compare page flags.
788	* Note: we have AVL, A, D bits desynched.
789	*/
790	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
791	("Page flags mismatch! pvFault=%VGv GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
792	}
793	else
794	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
795	}
796	else
797	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
798	# endif /* VBOX_STRICT */
799	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
800	}
801	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
802	# endif /* PGM_OUT_OF_SYNC_IN_GC */
803	}
804	else
805	{
806	/*
807	* Page not present in Guest OS or invalid page table address.
808	* This is potential virtual page access handler food.
809	*
810	* For the present we'll say that our access handlers don't
811	* work for this case - we've already discarded the page table
812	* not present case which is identical to this.
813	*
814	* When we perchance find we need this, we will probably have AVL
815	* trees (offset based) to operate on and we can measure their speed
816	* agains mapping a page table and probably rearrange this handling
817	* a bit. (Like, searching virtual ranges before checking the
818	* physical address.)
819	*/
820	}
821	}
822
823
824	# if PGM_WITH_PAGING(PGM_GST_TYPE)
825	/*
826	* Conclusion, this is a guest trap.
827	*/
828	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
829	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
830	return VINF_EM_RAW_GUEST_TRAP;
831	# else
832	/* present, but not a monitored page; perhaps the guest is probing physical memory */
833	return VINF_EM_RAW_EMULATE_INSTR;
834	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
835
836
837	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
838
839	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
840	return VERR_INTERNAL_ERROR;
841	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
842	}
843
844
845	/**
846	* Emulation of the invlpg instruction.
847	*
848	*
849	* @returns VBox status code.
850	*
851	* @param pVM VM handle.
852	* @param GCPtrPage Page to invalidate.
853	*
854	* @remark ASSUMES that the guest is updating before invalidating. This order
855	* isn't required by the CPU, so this is speculative and could cause
856	* trouble.
857	*
858	* @todo Flush page or page directory only if necessary!
859	* @todo Add a #define for simply invalidating the page.
860	*/
861	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
862	{
863	#if PGM_WITH_PAGING(PGM_GST_TYPE) \
864	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
865	int rc;
866
867	LogFlow(("InvalidatePage %x\n", GCPtrPage));
868	/*
869	* Get the shadow PD entry and skip out if this PD isn't present.
870	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
871	*/
872	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
873	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
874	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
875	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
876	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
877	# else /* AMD64 */
878	/* PML4 */
879	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
880	PX86PML4E pPml4eDst = &CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
881	if (!pPml4eDst->n.u1Present)
882	{
883	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
884	return VINF_SUCCESS;
885	}
886
887	/* PDPT */
888	PX86PDPT pPDPT;
889	rc = PGM_HCPHYS_2_PTR(pVM, pPml4eDst->u & X86_PML4E_PG_MASK, &pPDPT);
890	if (VBOX_FAILURE(rc))
891	return rc;
892	const unsigned iPDPT = ((RTGCUINTPTR64)GCPtrPage >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
893	PX86PDPE pPdpeDst = &pPDPT->a[iPDPT];
894	if (!pPdpeDst->n.u1Present)
895	{
896	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
897	return VINF_SUCCESS;
898	}
899
900	/* PD */
901	PX86PDPAE pPd;
902	rc = PGM_HCPHYS_2_PTR(pVM, pPdpeDst->u & X86_PDPE_PG_MASK, &pPd);
903	if (VBOX_FAILURE(rc))
904	return rc;
905	const unsigned iPd = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
906	PX86PDEPAE pPdeDst = &pPd->a[iPd];
907	# endif
908
909	const SHWPDE PdeDst = *pPdeDst;
910	if (!PdeDst.n.u1Present)
911	{
912	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
913	return VINF_SUCCESS;
914	}
915
916	/*
917	* Get the guest PD entry and calc big page.
918	*/
919	# if PGM_GST_TYPE == PGM_TYPE_32BIT
920	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
921	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
922	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
923	# else
924	unsigned iPDSrc;
925	# if PGM_GST_TYPE == PGM_TYPE_PAE
926	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
927	# else /* AMD64 */
928	PX86PML4E pPml4eSrc;
929	X86PDPE PdpeSrc;
930	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
931	# endif
932	GSTPDE PdeSrc;
933
934	if (pPDSrc)
935	PdeSrc = pPDSrc->a[iPDSrc];
936	else
937	PdeSrc.u = 0;
938	# endif
939
940	const uint32_t cr4 = CPUMGetGuestCR4(pVM);
941	# if PGM_GST_TYPE == PGM_TYPE_AMD64
942	const bool fIsBigPage = PdeSrc.b.u1Size;
943	# else
944	const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
945	# endif
946
947	# ifdef IN_RING3
948	/*
949	* If a CR3 Sync is pending we may ignore the invalidate page operation
950	* depending on the kind of sync and if it's a global page or not.
951	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
952	*/
953	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
954	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
955	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
956	&& fIsBigPage
957	&& PdeSrc.b.u1Global
958	&& (cr4 & X86_CR4_PGE)
959	)
960	)
961	# else
962	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
963	# endif
964	{
965	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
966	return VINF_SUCCESS;
967	}
968	# endif /* IN_RING3 */
969
970
971	# if PGM_GST_TYPE == PGM_TYPE_AMD64
972	Assert(pPml4eDst->n.u1Present && pPml4eDst->u & SHW_PDPT_MASK);
973	if (pPml4eSrc->n.u1Present)
974	{
975	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
976	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
977	{
978	/*
979	* Mark not present so we can resync the PML4E when it's used.
980	*/
981	LogFlow(("InvalidatePage: Out-of-sync PML4E at %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
982	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
983	pgmPoolFree(pVM, pPml4eDst->u & X86_PML4E_PG_MASK, PGMPOOL_IDX_PML4, iPml4);
984	pPml4eDst->u = 0;
985	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
986	PGM_INVL_GUEST_TLBS();
987	}
988	else if (!pPml4eSrc->n.u1Accessed)
989	{
990	/*
991	* Mark not present so we can set the accessed bit.
992	*/
993	pgmPoolFree(pVM, pPml4eDst->u & X86_PML4E_PG_MASK, PGMPOOL_IDX_PML4, iPml4);
994	pPml4eDst->u = 0;
995	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
996	PGM_INVL_GUEST_TLBS();
997	}
998	}
999	else
1000	{
1001	pgmPoolFree(pVM, pPml4eDst->u & X86_PML4E_PG_MASK, PGMPOOL_IDX_PML4, iPml4);
1002	pPml4eDst->u = 0;
1003	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1004	PGM_INVL_PG(GCPtrPage);
1005	return VINF_SUCCESS;
1006	}
1007
1008	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1009	if (PdpeSrc.n.u1Present)
1010	{
1011	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1012	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1013	{
1014	/*
1015	* Mark not present so we can resync the PML4E when it's used.
1016	*/
1017	LogFlow(("InvalidatePage: Out-of-sync PDPE at %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1018	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1019	pgmPoolFree(pVM, pPdpeDst->u & SHW_PDPT_MASK, PGMPOOL_IDX_PML4, iPml4);
1020	pPdpeDst->u = 0;
1021	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1022	PGM_INVL_GUEST_TLBS();
1023	}
1024	else if (!PdpeSrc.lm.u1Accessed)
1025	{
1026	/*
1027	* Mark not present so we can set the accessed bit.
1028	*/
1029	pgmPoolFree(pVM, pPdpeDst->u & SHW_PDPT_MASK, PGMPOOL_IDX_PML4, iPml4);
1030	pPdpeDst->u = 0;
1031	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
1032	PGM_INVL_GUEST_TLBS();
1033	}
1034	}
1035	else
1036	{
1037	pgmPoolFree(pVM, pPdpeDst->u & SHW_PDPT_MASK, PGMPOOL_IDX_PDPT, iPDDst);
1038	pPdpeDst->u = 0;
1039	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1040	PGM_INVL_PG(GCPtrPage);
1041	return VINF_SUCCESS;
1042	}
1043	# endif
1044
1045	/*
1046	* Deal with the Guest PDE.
1047	*/
1048	rc = VINF_SUCCESS;
1049	if (PdeSrc.n.u1Present)
1050	{
1051	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1052	{
1053	/*
1054	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1055	*/
1056	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1057	Assert(PGMGetGuestMode(pVM) <= PGMMODE_32_BIT);
1058	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1059	}
1060	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1061	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1062	{
1063	/*
1064	* Mark not present so we can resync the PDE when it's used.
1065	*/
1066	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1067	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1068	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1069	pPdeDst->u = 0;
1070	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1071	PGM_INVL_GUEST_TLBS();
1072	}
1073	else if (!PdeSrc.n.u1Accessed)
1074	{
1075	/*
1076	* Mark not present so we can set the accessed bit.
1077	*/
1078	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1079	pPdeDst->u = 0;
1080	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
1081	PGM_INVL_GUEST_TLBS();
1082	}
1083	else if (!fIsBigPage)
1084	{
1085	/*
1086	* 4KB - page.
1087	*/
1088	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1089	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1090	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1091	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1092	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1093	# endif
1094	if (pShwPage->GCPhys == GCPhys)
1095	{
1096	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1097	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1098	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1099	if (pPT->a[iPTEDst].n.u1Present)
1100	{
1101	# ifdef PGMPOOL_WITH_USER_TRACKING
1102	/* This is very unlikely with caching/monitoring enabled. */
1103	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1104	# endif
1105	pPT->a[iPTEDst].u = 0;
1106	}
1107	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1108	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1109	if (VBOX_SUCCESS(rc))
1110	rc = VINF_SUCCESS;
1111	# endif
1112	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
1113	PGM_INVL_PG(GCPtrPage);
1114	}
1115	else
1116	{
1117	/*
1118	* The page table address changed.
1119	*/
1120	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
1121	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1122	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1123	pPdeDst->u = 0;
1124	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1125	PGM_INVL_GUEST_TLBS();
1126	}
1127	}
1128	else
1129	{
1130	/*
1131	* 2/4MB - page.
1132	*/
1133	/* Before freeing the page, check if anything really changed. */
1134	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1135	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1136	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1137	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1138	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1139	# endif
1140	if ( pShwPage->GCPhys == GCPhys
1141	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1142	{
1143	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1144	/** @todo PAT */
1145	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1146	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1147	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1148	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1149	{
1150	LogFlow(("Skipping flush for big page containing %VGv (PD=%X .u=%VX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1151	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
1152	return VINF_SUCCESS;
1153	}
1154	}
1155
1156	/*
1157	* Ok, the page table is present and it's been changed in the guest.
1158	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1159	* We could do this for some flushes in GC too, but we need an algorithm for
1160	* deciding which 4MB pages containing code likely to be executed very soon.
1161	*/
1162	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1163	pPdeDst->u = 0;
1164	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
1165	PGM_INVL_BIG_PG(GCPtrPage);
1166	}
1167	}
1168	else
1169	{
1170	/*
1171	* Page directory is not present, mark shadow PDE not present.
1172	*/
1173	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1174	{
1175	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1176	pPdeDst->u = 0;
1177	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1178	PGM_INVL_PG(GCPtrPage);
1179	}
1180	else
1181	{
1182	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1183	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
1184	}
1185	}
1186
1187	return rc;
1188
1189	#else /* guest real and protected mode */
1190	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1191	return VINF_SUCCESS;
1192	#endif
1193	}
1194
1195
1196	#ifdef PGMPOOL_WITH_USER_TRACKING
1197	/**
1198	* Update the tracking of shadowed pages.
1199	*
1200	* @param pVM The VM handle.
1201	* @param pShwPage The shadow page.
1202	* @param HCPhys The physical page we is being dereferenced.
1203	*/
1204	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1205	{
1206	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1207	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1208	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1209
1210	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1211	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1212	* 2. write protect all shadowed pages. I.e. implement caching.
1213	*/
1214	/*
1215	* Find the guest address.
1216	*/
1217	for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1218	pRam;
1219	pRam = CTXALLSUFF(pRam->pNext))
1220	{
1221	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1222	while (iPage-- > 0)
1223	{
1224	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1225	{
1226	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1227	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1228	pShwPage->cPresent--;
1229	pPool->cPresent--;
1230	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1231	return;
1232	}
1233	}
1234	}
1235
1236	for (;;)
1237	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1238	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1239	pShwPage->cPresent--;
1240	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1241	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1242	}
1243
1244
1245	/**
1246	* Update the tracking of shadowed pages.
1247	*
1248	* @param pVM The VM handle.
1249	* @param pShwPage The shadow page.
1250	* @param u16 The top 16-bit of the pPage->HCPhys.
1251	* @param pPage Pointer to the guest page. this will be modified.
1252	* @param iPTDst The index into the shadow table.
1253	*/
1254	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1255	{
1256	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1257	/*
1258	* We're making certain assumptions about the placement of cRef and idx.
1259	*/
1260	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1261	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1262
1263	/*
1264	* Just deal with the simple first time here.
1265	*/
1266	if (!u16)
1267	{
1268	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1269	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1270	}
1271	else
1272	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1273
1274	/* write back, trying to be clever... */
1275	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1276	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1277	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1278	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1279
1280	/* update statistics. */
1281	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1282	pShwPage->cPresent++;
1283	if (pShwPage->iFirstPresent > iPTDst)
1284	pShwPage->iFirstPresent = iPTDst;
1285	}
1286	#endif /* PGMPOOL_WITH_USER_TRACKING */
1287
1288
1289	/**
1290	* Creates a 4K shadow page for a guest page.
1291	*
1292	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1293	* physical address. The PdeSrc argument only the flags are used. No page structured
1294	* will be mapped in this function.
1295	*
1296	* @param pVM VM handle.
1297	* @param pPteDst Destination page table entry.
1298	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1299	* Can safely assume that only the flags are being used.
1300	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1301	* @param pShwPage Pointer to the shadow page.
1302	* @param iPTDst The index into the shadow table.
1303	*
1304	* @remark Not used for 2/4MB pages!
1305	*/
1306	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1307	{
1308	if (PteSrc.n.u1Present)
1309	{
1310	/*
1311	* Find the ram range.
1312	*/
1313	PPGMPAGE pPage;
1314	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1315	if (VBOX_SUCCESS(rc))
1316	{
1317	/** @todo investiage PWT, PCD and PAT. */
1318	/*
1319	* Make page table entry.
1320	*/
1321	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1322	SHWPTE PteDst;
1323	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1324	{
1325	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1326	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1327	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1328	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1329	else
1330	{
1331	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1332	PteDst.u = 0;
1333	}
1334	/** @todo count these two kinds. */
1335	}
1336	else
1337	{
1338	/*
1339	* If the page or page directory entry is not marked accessed,
1340	* we mark the page not present.
1341	*/
1342	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1343	{
1344	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1345	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1346	PteDst.u = 0;
1347	}
1348	else
1349	/*
1350	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1351	* when the page is modified.
1352	*/
1353	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1354	{
1355	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1356	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1357	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1358	\| PGM_PTFLAGS_TRACK_DIRTY;
1359	}
1360	else
1361	{
1362	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1363	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1364	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1365	}
1366	}
1367
1368	#ifdef PGMPOOL_WITH_USER_TRACKING
1369	/*
1370	* Keep user track up to date.
1371	*/
1372	if (PteDst.n.u1Present)
1373	{
1374	if (!pPteDst->n.u1Present)
1375	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1376	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1377	{
1378	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1379	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1380	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1381	}
1382	}
1383	else if (pPteDst->n.u1Present)
1384	{
1385	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1386	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1387	}
1388	#endif /* PGMPOOL_WITH_USER_TRACKING */
1389
1390	/*
1391	* Update statistics and commit the entry.
1392	*/
1393	if (!PteSrc.n.u1Global)
1394	pShwPage->fSeenNonGlobal = true;
1395	*pPteDst = PteDst;
1396	}
1397	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1398	/** @todo count these. */
1399	}
1400	else
1401	{
1402	/*
1403	* Page not-present.
1404	*/
1405	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1406	#ifdef PGMPOOL_WITH_USER_TRACKING
1407	/* Keep user track up to date. */
1408	if (pPteDst->n.u1Present)
1409	{
1410	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1411	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1412	}
1413	#endif /* PGMPOOL_WITH_USER_TRACKING */
1414	pPteDst->u = 0;
1415	/** @todo count these. */
1416	}
1417	}
1418
1419
1420	/**
1421	* Syncs a guest OS page.
1422	*
1423	* There are no conflicts at this point, neither is there any need for
1424	* page table allocations.
1425	*
1426	* @returns VBox status code.
1427	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1428	* @param pVM VM handle.
1429	* @param PdeSrc Page directory entry of the guest.
1430	* @param GCPtrPage Guest context page address.
1431	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1432	* @param uErr Fault error (X86_TRAP_PF_*).
1433	*/
1434	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1435	{
1436	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1437
1438	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1439	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1440	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1441	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
1442
1443	# if PGM_WITH_NX(PGM_GST_TYPE)
1444	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1445	# endif
1446
1447	/*
1448	* Assert preconditions.
1449	*/
1450	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1451	Assert(PdeSrc.n.u1Present);
1452	Assert(cPages);
1453
1454	/*
1455	* Get the shadow PDE, find the shadow page table in the pool.
1456	*/
1457	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1458	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1459	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1460	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1461	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1462	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1463	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1464	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1465	PX86PDPAE pPDDst;
1466	X86PDEPAE PdeDst;
1467	PX86PDPT pPdpt;
1468
1469	int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdpt, &pPDDst);
1470	AssertRCReturn(rc, rc);
1471	Assert(pPDDst && pPdpt);
1472	PdeDst = pPDDst->a[iPDDst];
1473	# endif
1474	Assert(PdeDst.n.u1Present);
1475	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1476
1477	/*
1478	* Check that the page is present and that the shadow PDE isn't out of sync.
1479	*/
1480	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1481	const bool fBigPage = PdeSrc.b.u1Size;
1482	# else
1483	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1484	# endif
1485	RTGCPHYS GCPhys;
1486	if (!fBigPage)
1487	{
1488	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1489	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1490	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1491	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1492	# endif
1493	}
1494	else
1495	{
1496	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1497	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1498	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1499	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1500	# endif
1501	}
1502	if ( pShwPage->GCPhys == GCPhys
1503	&& PdeSrc.n.u1Present
1504	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1505	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1506	# if PGM_WITH_NX(PGM_GST_TYPE)
1507	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1508	# endif
1509	)
1510	{
1511	/*
1512	* Check that the PDE is marked accessed already.
1513	* Since we set the accessed bit before getting here on a #PF, this
1514	* check is only meant for dealing with non-#PF'ing paths.
1515	*/
1516	if (PdeSrc.n.u1Accessed)
1517	{
1518	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1519	if (!fBigPage)
1520	{
1521	/*
1522	* 4KB Page - Map the guest page table.
1523	*/
1524	PGSTPT pPTSrc;
1525	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1526	if (VBOX_SUCCESS(rc))
1527	{
1528	# ifdef PGM_SYNC_N_PAGES
1529	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1530	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1531	{
1532	/*
1533	* This code path is currently only taken when the caller is PGMTrap0eHandler
1534	* for non-present pages!
1535	*
1536	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1537	* deal with locality.
1538	*/
1539	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1540	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1541	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1542	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1543	# else
1544	const unsigned offPTSrc = 0;
1545	# endif
1546	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1547	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1548	iPTDst = 0;
1549	else
1550	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1551	for (; iPTDst < iPTDstEnd; iPTDst++)
1552	{
1553	if (!pPTDst->a[iPTDst].n.u1Present)
1554	{
1555	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1556	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1557	NOREF(GCPtrCurPage);
1558	#ifndef IN_RING0
1559	/*
1560	* Assuming kernel code will be marked as supervisor - and not as user level
1561	* and executed using a conforming code selector - And marked as readonly.
1562	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1563	*/
1564	PPGMPAGE pPage;
1565	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1566	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1567	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1568	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1569	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1570	)
1571	#endif /* else: CSAM not active */
1572	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1573	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1574	GCPtrCurPage, PteSrc.n.u1Present,
1575	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1576	PteSrc.n.u1User & PdeSrc.n.u1User,
1577	(uint64_t)PteSrc.u,
1578	(uint64_t)pPTDst->a[iPTDst].u,
1579	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1580	}
1581	}
1582	}
1583	else
1584	# endif /* PGM_SYNC_N_PAGES */
1585	{
1586	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1587	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1588	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1589	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1590	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1591	GCPtrPage, PteSrc.n.u1Present,
1592	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1593	PteSrc.n.u1User & PdeSrc.n.u1User,
1594	(uint64_t)PteSrc.u,
1595	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1596	}
1597	}
1598	else /* MMIO or invalid page: emulated in #PF handler. */
1599	{
1600	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1601	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1602	}
1603	}
1604	else
1605	{
1606	/*
1607	* 4/2MB page - lazy syncing shadow 4K pages.
1608	* (There are many causes of getting here, it's no longer only CSAM.)
1609	*/
1610	/* Calculate the GC physical address of this 4KB shadow page. */
1611	RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1612	/* Find ram range. */
1613	PPGMPAGE pPage;
1614	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1615	if (VBOX_SUCCESS(rc))
1616	{
1617	/*
1618	* Make shadow PTE entry.
1619	*/
1620	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1621	SHWPTE PteDst;
1622	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1623	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1624	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1625	{
1626	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1627	PteDst.n.u1Write = 0;
1628	else
1629	PteDst.u = 0;
1630	}
1631	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1632	# ifdef PGMPOOL_WITH_USER_TRACKING
1633	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1634	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1635	# endif
1636	pPTDst->a[iPTDst] = PteDst;
1637
1638
1639	/*
1640	* If the page is not flagged as dirty and is writable, then make it read-only
1641	* at PD level, so we can set the dirty bit when the page is modified.
1642	*
1643	* ASSUMES that page access handlers are implemented on page table entry level.
1644	* Thus we will first catch the dirty access and set PDE.D and restart. If
1645	* there is an access handler, we'll trap again and let it work on the problem.
1646	*/
1647	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1648	* As for invlpg, it simply frees the whole shadow PT.
1649	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1650	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1651	{
1652	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1653	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1654	PdeDst.n.u1Write = 0;
1655	}
1656	else
1657	{
1658	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1659	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1660	}
1661	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1662	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1663	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1664	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1665	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1666	pPDDst->a[iPDDst] = PdeDst;
1667	# endif
1668	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1669	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1670	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1671	}
1672	else
1673	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1674	}
1675	return VINF_SUCCESS;
1676	}
1677	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1678	}
1679	else
1680	{
1681	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1682	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1683	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1684	}
1685
1686	/*
1687	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1688	* Yea, I'm lazy.
1689	*/
1690	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1691	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1692	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1693	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1694	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1695	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1696	pPDDst->a[iPDDst].u = 0;
1697	# endif
1698	PGM_INVL_GUEST_TLBS();
1699	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1700
1701	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1702	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
1703
1704	# ifdef PGM_SYNC_N_PAGES
1705	/*
1706	* Get the shadow PDE, find the shadow page table in the pool.
1707	*/
1708	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1709	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1710	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1711	# else /* PAE */
1712	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1713	# endif
1714	Assert(PdeDst.n.u1Present);
1715	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1716	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1717
1718	# if PGM_SHW_TYPE == PGM_TYPE_PAE
1719	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1720	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1721	# else
1722	const unsigned offPTSrc = 0;
1723	# endif
1724
1725	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1726	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1727	{
1728	/*
1729	* This code path is currently only taken when the caller is PGMTrap0eHandler
1730	* for non-present pages!
1731	*
1732	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1733	* deal with locality.
1734	*/
1735	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1736	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1737	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1738	iPTDst = 0;
1739	else
1740	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1741	for (; iPTDst < iPTDstEnd; iPTDst++)
1742	{
1743	if (!pPTDst->a[iPTDst].n.u1Present)
1744	{
1745	GSTPTE PteSrc;
1746
1747	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1748
1749	/* Fake the page table entry */
1750	PteSrc.u = GCPtrCurPage;
1751	PteSrc.n.u1Present = 1;
1752	PteSrc.n.u1Dirty = 1;
1753	PteSrc.n.u1Accessed = 1;
1754	PteSrc.n.u1Write = 1;
1755	PteSrc.n.u1User = 1;
1756
1757	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1758
1759	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1760	GCPtrCurPage, PteSrc.n.u1Present,
1761	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1762	PteSrc.n.u1User & PdeSrc.n.u1User,
1763	(uint64_t)PteSrc.u,
1764	(uint64_t)pPTDst->a[iPTDst].u,
1765	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1766	}
1767	}
1768	}
1769	else
1770	# endif /* PGM_SYNC_N_PAGES */
1771	{
1772	GSTPTE PteSrc;
1773	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1774	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1775
1776	/* Fake the page table entry */
1777	PteSrc.u = GCPtrCurPage;
1778	PteSrc.n.u1Present = 1;
1779	PteSrc.n.u1Dirty = 1;
1780	PteSrc.n.u1Accessed = 1;
1781	PteSrc.n.u1Write = 1;
1782	PteSrc.n.u1User = 1;
1783	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1784
1785	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
1786	GCPtrPage, PteSrc.n.u1Present,
1787	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1788	PteSrc.n.u1User & PdeSrc.n.u1User,
1789	(uint64_t)PteSrc.u,
1790	(uint64_t)pPTDst->a[iPTDst].u,
1791	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1792	}
1793	return VINF_SUCCESS;
1794
1795	#else
1796	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1797	return VERR_INTERNAL_ERROR;
1798	#endif
1799	}
1800
1801
1802
1803	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1804
1805	/**
1806	* Investigate page fault and handle write protection page faults caused by
1807	* dirty bit tracking.
1808	*
1809	* @returns VBox status code.
1810	* @param pVM VM handle.
1811	* @param uErr Page fault error code.
1812	* @param pPdeDst Shadow page directory entry.
1813	* @param pPdeSrc Guest page directory entry.
1814	* @param GCPtrPage Guest context page address.
1815	*/
1816	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1817	{
1818	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1819	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1820	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1821	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1822	bool fBigPagesSupported = true;
1823	# else
1824	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1825	# endif
1826	# if PGM_WITH_NX(PGM_GST_TYPE)
1827	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1828	# endif
1829	unsigned uPageFaultLevel;
1830	int rc;
1831
1832	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1833	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1834
1835	# if PGM_GST_TYPE == PGM_TYPE_PAE \
1836	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
1837
1838	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1839	PX86PML4E pPml4eSrc;
1840	PX86PDPE pPdpeSrc;
1841
1842	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
1843	Assert(pPml4eSrc);
1844
1845	/*
1846	* Real page fault? (PML4E level)
1847	*/
1848	if ( (uErr & X86_TRAP_PF_RSVD)
1849	\|\| !pPml4eSrc->n.u1Present
1850	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
1851	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1852	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
1853	)
1854	{
1855	uPageFaultLevel = 0;
1856	goto UpperLevelPageFault;
1857	}
1858	Assert(pPdpeSrc);
1859
1860	# else /* PAE */
1861	PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
1862	# endif
1863
1864	/*
1865	* Real page fault? (PDPE level)
1866	*/
1867	if ( (uErr & X86_TRAP_PF_RSVD)
1868	\|\| !pPdpeSrc->n.u1Present
1869	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
1870	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
1871	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
1872	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
1873	# endif
1874	)
1875	{
1876	uPageFaultLevel = 1;
1877	goto UpperLevelPageFault;
1878	}
1879	# endif
1880
1881	/*
1882	* Real page fault? (PDE level)
1883	*/
1884	if ( (uErr & X86_TRAP_PF_RSVD)
1885	\|\| !pPdeSrc->n.u1Present
1886	# if PGM_WITH_NX(PGM_GST_TYPE)
1887	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1888	# endif
1889	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1890	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
1891	{
1892	uPageFaultLevel = 2;
1893	goto UpperLevelPageFault;
1894	}
1895
1896	/*
1897	* First check the easy case where the page directory has been marked read-only to track
1898	* the dirty bit of an emulated BIG page
1899	*/
1900	if (pPdeSrc->b.u1Size && fBigPagesSupported)
1901	{
1902	/* Mark guest page directory as accessed */
1903	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1904	pPml4eSrc->n.u1Accessed = 1;
1905	pPdpeSrc->lm.u1Accessed = 1;
1906	# endif
1907	pPdeSrc->b.u1Accessed = 1;
1908
1909	/*
1910	* Only write protection page faults are relevant here.
1911	*/
1912	if (fWriteFault)
1913	{
1914	/* Mark guest page directory as dirty (BIG page only). */
1915	pPdeSrc->b.u1Dirty = 1;
1916
1917	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1918	{
1919	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1920
1921	Assert(pPdeSrc->b.u1Write);
1922
1923	pPdeDst->n.u1Write = 1;
1924	pPdeDst->n.u1Accessed = 1;
1925	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1926	PGM_INVL_BIG_PG(GCPtrPage);
1927	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1928	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1929	}
1930	}
1931	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1932	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1933	}
1934	/* else: 4KB page table */
1935
1936	/*
1937	* Map the guest page table.
1938	*/
1939	PGSTPT pPTSrc;
1940	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1941	if (VBOX_SUCCESS(rc))
1942	{
1943	/*
1944	* Real page fault?
1945	*/
1946	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1947	const GSTPTE PteSrc = *pPteSrc;
1948	if ( !PteSrc.n.u1Present
1949	# if PGM_WITH_NX(PGM_GST_TYPE)
1950	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
1951	# endif
1952	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1953	\|\| (fUserLevelFault && !PteSrc.n.u1User)
1954	)
1955	{
1956	# ifdef IN_GC
1957	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1958	# endif
1959	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1960	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1961
1962	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1963	* See the 2nd case above as well.
1964	*/
1965	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1966	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1967
1968	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1969	return VINF_EM_RAW_GUEST_TRAP;
1970	}
1971	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1972
1973	/*
1974	* Set the accessed bits in the page directory and the page table.
1975	*/
1976	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1977	pPml4eSrc->n.u1Accessed = 1;
1978	pPdpeSrc->lm.u1Accessed = 1;
1979	# endif
1980	pPdeSrc->n.u1Accessed = 1;
1981	pPteSrc->n.u1Accessed = 1;
1982
1983	/*
1984	* Only write protection page faults are relevant here.
1985	*/
1986	if (fWriteFault)
1987	{
1988	/* Write access, so mark guest entry as dirty. */
1989	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1990	if (!pPteSrc->n.u1Dirty)
1991	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1992	else
1993	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1994	# endif
1995
1996	pPteSrc->n.u1Dirty = 1;
1997
1998	if (pPdeDst->n.u1Present)
1999	{
2000	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2001	* Our individual shadow handlers will provide more information and force a fatal exit.
2002	*/
2003	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2004	{
2005	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
2006	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2007	return VINF_SUCCESS;
2008	}
2009
2010	/*
2011	* Map shadow page table.
2012	*/
2013	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2014	if (pShwPage)
2015	{
2016	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2017	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2018	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2019	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2020	{
2021	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
2022	# ifdef VBOX_STRICT
2023	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2024	if (pPage)
2025	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2026	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2027	# endif
2028	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
2029
2030	Assert(pPteSrc->n.u1Write);
2031
2032	pPteDst->n.u1Write = 1;
2033	pPteDst->n.u1Dirty = 1;
2034	pPteDst->n.u1Accessed = 1;
2035	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2036	PGM_INVL_PG(GCPtrPage);
2037
2038	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2039	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2040	}
2041	}
2042	else
2043	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2044	}
2045	}
2046	/** @todo Optimize accessed bit emulation? */
2047	# ifdef VBOX_STRICT
2048	/*
2049	* Sanity check.
2050	*/
2051	else if ( !pPteSrc->n.u1Dirty
2052	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2053	&& pPdeDst->n.u1Present)
2054	{
2055	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2056	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2057	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2058	if ( pPteDst->n.u1Present
2059	&& pPteDst->n.u1Write)
2060	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2061	}
2062	# endif /* VBOX_STRICT */
2063	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2064	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2065	}
2066	AssertRC(rc);
2067	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2068	return rc;
2069
2070
2071	UpperLevelPageFault:
2072	/* Pagefault detected while checking the PML4E, PDPE or PDE.
2073	* Single exit handler to get rid of duplicate code paths.
2074	*/
2075	# ifdef IN_GC
2076	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
2077	# endif
2078	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
2079	LogFlow(("CheckPageFault: real page fault at %VGv (%d)\n", GCPtrPage, uPageFaultLevel));
2080
2081	if (
2082	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2083	pPml4eSrc->n.u1Present &&
2084	# endif
2085	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2086	pPdpeSrc->n.u1Present &&
2087	# endif
2088	pPdeSrc->n.u1Present)
2089	{
2090	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2091	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2092	{
2093	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2094	}
2095	else
2096	{
2097	/*
2098	* Map the guest page table.
2099	*/
2100	PGSTPT pPTSrc;
2101	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2102	if (VBOX_SUCCESS(rc))
2103	{
2104	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2105	const GSTPTE PteSrc = *pPteSrc;
2106	if (pPteSrc->n.u1Present)
2107	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2108	}
2109	AssertRC(rc);
2110	}
2111	}
2112	return VINF_EM_RAW_GUEST_TRAP;
2113	}
2114
2115	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2116
2117
2118	/**
2119	* Sync a shadow page table.
2120	*
2121	* The shadow page table is not present. This includes the case where
2122	* there is a conflict with a mapping.
2123	*
2124	* @returns VBox status code.
2125	* @param pVM VM handle.
2126	* @param iPD Page directory index.
2127	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2128	* Assume this is a temporary mapping.
2129	* @param GCPtrPage GC Pointer of the page that caused the fault
2130	*/
2131	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
2132	{
2133	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2134	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
2135	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
2136
2137	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2138	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2139	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2140	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2141
2142	int rc = VINF_SUCCESS;
2143
2144	/*
2145	* Validate input a little bit.
2146	*/
2147	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%VGv\n", iPDSrc, GCPtrPage));
2148	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2149	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2150	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2151	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2152	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2153	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2154	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2155	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2156	PX86PDPAE pPDDst;
2157	PX86PDPT pPdpt;
2158	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdpt, &pPDDst);
2159	if (rc != VINF_SUCCESS)
2160	{
2161	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
2162	return rc;
2163	}
2164	Assert(pPDDst);
2165	# endif
2166	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2167	SHWPDE PdeDst = *pPdeDst;
2168
2169	# ifndef PGM_WITHOUT_MAPPINGS
2170	/*
2171	* Check for conflicts.
2172	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2173	* HC: Simply resolve the conflict.
2174	*/
2175	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2176	{
2177	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2178	# ifndef IN_RING3
2179	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
2180	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2181	return VERR_ADDRESS_CONFLICT;
2182	# else
2183	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2184	Assert(pMapping);
2185	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2186	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2187	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2188	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2189	# else
2190	AssertFailed(); /* can't happen for amd64 */
2191	# endif
2192	if (VBOX_FAILURE(rc))
2193	{
2194	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2195	return rc;
2196	}
2197	PdeDst = *pPdeDst;
2198	# endif
2199	}
2200	# else /* PGM_WITHOUT_MAPPINGS */
2201	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2202	# endif /* PGM_WITHOUT_MAPPINGS */
2203	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2204
2205	/*
2206	* Sync page directory entry.
2207	*/
2208	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2209	if (PdeSrc.n.u1Present)
2210	{
2211	/*
2212	* Allocate & map the page table.
2213	*/
2214	PSHWPT pPTDst;
2215	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2216	const bool fPageTable = !PdeSrc.b.u1Size;
2217	# else
2218	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2219	# endif
2220	PPGMPOOLPAGE pShwPage;
2221	RTGCPHYS GCPhys;
2222	if (fPageTable)
2223	{
2224	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2225	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2226	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2227	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2228	# endif
2229	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2230	}
2231	else
2232	{
2233	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2234	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2235	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2236	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2237	# endif
2238	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2239	}
2240	if (rc == VINF_SUCCESS)
2241	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2242	else if (rc == VINF_PGM_CACHED_PAGE)
2243	{
2244	/*
2245	* The PT was cached, just hook it up.
2246	*/
2247	if (fPageTable)
2248	PdeDst.u = pShwPage->Core.Key
2249	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2250	else
2251	{
2252	PdeDst.u = pShwPage->Core.Key
2253	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2254	/* (see explanation and assumptions further down.) */
2255	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2256	{
2257	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2258	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2259	PdeDst.b.u1Write = 0;
2260	}
2261	}
2262	*pPdeDst = PdeDst;
2263	return VINF_SUCCESS;
2264	}
2265	else if (rc == VERR_PGM_POOL_FLUSHED)
2266	return VINF_PGM_SYNC_CR3;
2267	else
2268	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2269	PdeDst.u &= X86_PDE_AVL_MASK;
2270	PdeDst.u \|= pShwPage->Core.Key;
2271
2272	/*
2273	* Page directory has been accessed (this is a fault situation, remember).
2274	*/
2275	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2276	if (fPageTable)
2277	{
2278	/*
2279	* Page table - 4KB.
2280	*
2281	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2282	*/
2283	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2284	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2285	PGSTPT pPTSrc;
2286	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2287	if (VBOX_SUCCESS(rc))
2288	{
2289	/*
2290	* Start by syncing the page directory entry so CSAM's TLB trick works.
2291	*/
2292	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2293	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2294	*pPdeDst = PdeDst;
2295
2296	/*
2297	* Directory/page user or supervisor privilege: (same goes for read/write)
2298	*
2299	* Directory Page Combined
2300	* U/S U/S U/S
2301	* 0 0 0
2302	* 0 1 0
2303	* 1 0 0
2304	* 1 1 1
2305	*
2306	* Simple AND operation. Table listed for completeness.
2307	*
2308	*/
2309	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2310	# ifdef PGM_SYNC_N_PAGES
2311	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2312	unsigned iPTDst = iPTBase;
2313	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2314	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2315	iPTDst = 0;
2316	else
2317	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2318	# else /* !PGM_SYNC_N_PAGES */
2319	unsigned iPTDst = 0;
2320	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2321	# endif /* !PGM_SYNC_N_PAGES */
2322	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2323	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2324	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2325	# else
2326	const unsigned offPTSrc = 0;
2327	# endif
2328	for (; iPTDst < iPTDstEnd; iPTDst++)
2329	{
2330	const unsigned iPTSrc = iPTDst + offPTSrc;
2331	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2332
2333	if (PteSrc.n.u1Present) /* we've already cleared it above */
2334	{
2335	# ifndef IN_RING0
2336	/*
2337	* Assuming kernel code will be marked as supervisor - and not as user level
2338	* and executed using a conforming code selector - And marked as readonly.
2339	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2340	*/
2341	PPGMPAGE pPage;
2342	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2343	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2344	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2345	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2346	)
2347	# endif
2348	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2349	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2350	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2351	PteSrc.n.u1Present,
2352	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2353	PteSrc.n.u1User & PdeSrc.n.u1User,
2354	(uint64_t)PteSrc.u,
2355	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2356	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2357	}
2358	} /* for PTEs */
2359	}
2360	}
2361	else
2362	{
2363	/*
2364	* Big page - 2/4MB.
2365	*
2366	* We'll walk the ram range list in parallel and optimize lookups.
2367	* We will only sync on shadow page table at a time.
2368	*/
2369	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2370
2371	/**
2372	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2373	*/
2374
2375	/*
2376	* Start by syncing the page directory entry.
2377	*/
2378	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2379	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2380
2381	/*
2382	* If the page is not flagged as dirty and is writable, then make it read-only
2383	* at PD level, so we can set the dirty bit when the page is modified.
2384	*
2385	* ASSUMES that page access handlers are implemented on page table entry level.
2386	* Thus we will first catch the dirty access and set PDE.D and restart. If
2387	* there is an access handler, we'll trap again and let it work on the problem.
2388	*/
2389	/** @todo move the above stuff to a section in the PGM documentation. */
2390	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2391	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2392	{
2393	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2394	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2395	PdeDst.b.u1Write = 0;
2396	}
2397	*pPdeDst = PdeDst;
2398
2399	/*
2400	* Fill the shadow page table.
2401	*/
2402	/* Get address and flags from the source PDE. */
2403	SHWPTE PteDstBase;
2404	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2405
2406	/* Loop thru the entries in the shadow PT. */
2407	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2408	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2409	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2410	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2411	PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2412	unsigned iPTDst = 0;
2413	while (iPTDst < ELEMENTS(pPTDst->a))
2414	{
2415	/* Advance ram range list. */
2416	while (pRam && GCPhys > pRam->GCPhysLast)
2417	pRam = CTXALLSUFF(pRam->pNext);
2418	if (pRam && GCPhys >= pRam->GCPhys)
2419	{
2420	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2421	do
2422	{
2423	/* Make shadow PTE. */
2424	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2425	SHWPTE PteDst;
2426
2427	/* Make sure the RAM has already been allocated. */
2428	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2429	{
2430	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2431	{
2432	# ifdef IN_RING3
2433	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2434	# else
2435	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2436	# endif
2437	if (rc != VINF_SUCCESS)
2438	return rc;
2439	}
2440	}
2441
2442	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2443	{
2444	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2445	{
2446	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2447	PteDst.n.u1Write = 0;
2448	}
2449	else
2450	PteDst.u = 0;
2451	}
2452	# ifndef IN_RING0
2453	/*
2454	* Assuming kernel code will be marked as supervisor and not as user level and executed
2455	* using a conforming code selector. Don't check for readonly, as that implies the whole
2456	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2457	*/
2458	else if ( !PdeSrc.n.u1User
2459	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2460	PteDst.u = 0;
2461	# endif
2462	else
2463	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2464	# ifdef PGMPOOL_WITH_USER_TRACKING
2465	if (PteDst.n.u1Present)
2466	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2467	# endif
2468	/* commit it */
2469	pPTDst->a[iPTDst] = PteDst;
2470	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2471	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2472	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2473
2474	/* advance */
2475	GCPhys += PAGE_SIZE;
2476	iHCPage++;
2477	iPTDst++;
2478	} while ( iPTDst < ELEMENTS(pPTDst->a)
2479	&& GCPhys <= pRam->GCPhysLast);
2480	}
2481	else if (pRam)
2482	{
2483	Log(("Invalid pages at %VGp\n", GCPhys));
2484	do
2485	{
2486	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2487	GCPhys += PAGE_SIZE;
2488	iPTDst++;
2489	} while ( iPTDst < ELEMENTS(pPTDst->a)
2490	&& GCPhys < pRam->GCPhys);
2491	}
2492	else
2493	{
2494	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2495	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2496	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2497	}
2498	} /* while more PTEs */
2499	} /* 4KB / 4MB */
2500	}
2501	else
2502	AssertRelease(!PdeDst.n.u1Present);
2503
2504	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2505	# ifdef IN_GC
2506	if (VBOX_FAILURE(rc))
2507	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2508	# endif
2509	return rc;
2510
2511	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2512	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2513
2514	int rc = VINF_SUCCESS;
2515
2516	/*
2517	* Validate input a little bit.
2518	*/
2519	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2520	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2521	# else
2522	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2523	# endif
2524	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2525	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2526	SHWPDE PdeDst = *pPdeDst;
2527
2528	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2529	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2530
2531	GSTPDE PdeSrc;
2532	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2533	PdeSrc.n.u1Present = 1;
2534	PdeSrc.n.u1Write = 1;
2535	PdeSrc.n.u1Accessed = 1;
2536	PdeSrc.n.u1User = 1;
2537
2538	/*
2539	* Allocate & map the page table.
2540	*/
2541	PSHWPT pPTDst;
2542	PPGMPOOLPAGE pShwPage;
2543	RTGCPHYS GCPhys;
2544
2545	/* Virtual address = physical address */
2546	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2547	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2548
2549	if ( rc == VINF_SUCCESS
2550	\|\| rc == VINF_PGM_CACHED_PAGE)
2551	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2552	else
2553	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2554
2555	PdeDst.u &= X86_PDE_AVL_MASK;
2556	PdeDst.u \|= pShwPage->Core.Key;
2557	PdeDst.n.u1Present = 1;
2558	PdeDst.n.u1Write = 1;
2559	PdeDst.n.u1User = 1;
2560	*pPdeDst = PdeDst;
2561
2562	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2563	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2564	return rc;
2565
2566	#else
2567	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2568	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2569	return VERR_INTERNAL_ERROR;
2570	#endif
2571	}
2572
2573
2574
2575	/**
2576	* Prefetch a page/set of pages.
2577	*
2578	* Typically used to sync commonly used pages before entering raw mode
2579	* after a CR3 reload.
2580	*
2581	* @returns VBox status code.
2582	* @param pVM VM handle.
2583	* @param GCPtrPage Page to invalidate.
2584	*/
2585	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2586	{
2587	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2588	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2589	/*
2590	* Check that all Guest levels thru the PDE are present, getting the
2591	* PD and PDE in the processes.
2592	*/
2593	int rc = VINF_SUCCESS;
2594	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2595	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2596	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2597	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2598	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2599	unsigned iPDSrc;
2600	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2601	if (!pPDSrc)
2602	return VINF_SUCCESS; /* not present */
2603	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2604	unsigned iPDSrc;
2605	PX86PML4E pPml4eSrc;
2606	X86PDPE PdpeSrc;
2607	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2608	if (!pPDSrc)
2609	return VINF_SUCCESS; /* not present */
2610	# endif
2611	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2612	# else
2613	PGSTPD pPDSrc = NULL;
2614	const unsigned iPDSrc = 0;
2615	GSTPDE PdeSrc;
2616
2617	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2618	PdeSrc.n.u1Present = 1;
2619	PdeSrc.n.u1Write = 1;
2620	PdeSrc.n.u1Accessed = 1;
2621	PdeSrc.n.u1User = 1;
2622	# endif
2623
2624	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2625	{
2626	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2627	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2628	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2629	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2630	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2631	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2632	PX86PDPAE pPDDst;
2633	X86PDEPAE PdeDst;
2634
2635	# if PGM_GST_TYPE == PGM_TYPE_PROT
2636	/* AMD-V nested paging */
2637	X86PML4E Pml4eSrc;
2638	X86PDPE PdpeSrc;
2639	PX86PML4E pPml4eSrc = &Pml4eSrc;
2640
2641	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2642	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2643	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2644	# endif
2645
2646	int rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2647	if (rc != VINF_SUCCESS)
2648	{
2649	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
2650	return rc;
2651	}
2652	Assert(pPDDst);
2653	PdeDst = pPDDst->a[iPDDst];
2654	# endif
2655	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2656	{
2657	if (!PdeDst.n.u1Present)
2658	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2659	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2660	else
2661	{
2662	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2663	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2664	* makes no sense to prefetch more than one page.
2665	*/
2666	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2667	if (VBOX_SUCCESS(rc))
2668	rc = VINF_SUCCESS;
2669	}
2670	}
2671	}
2672	return rc;
2673	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED
2674	return VINF_SUCCESS; /* ignore */
2675	#endif
2676	}
2677
2678
2679
2680
2681	/**
2682	* Syncs a page during a PGMVerifyAccess() call.
2683	*
2684	* @returns VBox status code (informational included).
2685	* @param GCPtrPage The address of the page to sync.
2686	* @param fPage The effective guest page flags.
2687	* @param uErr The trap error code.
2688	*/
2689	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2690	{
2691	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2692
2693	Assert(!HWACCMIsNestedPagingActive(pVM));
2694	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
2695	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2696
2697	# ifndef IN_RING0
2698	if (!(fPage & X86_PTE_US))
2699	{
2700	/*
2701	* Mark this page as safe.
2702	*/
2703	/** @todo not correct for pages that contain both code and data!! */
2704	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2705	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
2706	}
2707	# endif
2708	/*
2709	* Get guest PD and index.
2710	*/
2711
2712	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2713	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2714	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2715	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2716	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2717	unsigned iPDSrc;
2718	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2719
2720	if (pPDSrc)
2721	{
2722	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2723	return VINF_EM_RAW_GUEST_TRAP;
2724	}
2725	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2726	unsigned iPDSrc;
2727	PX86PML4E pPml4eSrc;
2728	X86PDPE PdpeSrc;
2729	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2730	if (!pPDSrc)
2731	{
2732	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2733	return VINF_EM_RAW_GUEST_TRAP;
2734	}
2735	# endif
2736	# else
2737	PGSTPD pPDSrc = NULL;
2738	const unsigned iPDSrc = 0;
2739	# endif
2740	int rc = VINF_SUCCESS;
2741
2742	/*
2743	* First check if the shadow pd is present.
2744	*/
2745	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2746	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2747	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2748	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2749	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2750	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2751	PX86PDPAE pPDDst;
2752	PX86PDEPAE pPdeDst;
2753
2754	# if PGM_GST_TYPE == PGM_TYPE_PROT
2755	/* AMD-V nested paging */
2756	X86PML4E Pml4eSrc;
2757	X86PDPE PdpeSrc;
2758	PX86PML4E pPml4eSrc = &Pml4eSrc;
2759
2760	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2761	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2762	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2763	# endif
2764
2765	rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2766	if (rc != VINF_SUCCESS)
2767	{
2768	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
2769	return rc;
2770	}
2771	Assert(pPDDst);
2772	pPdeDst = &pPDDst->a[iPDDst];
2773	# endif
2774	if (!pPdeDst->n.u1Present)
2775	{
2776	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2777	AssertRC(rc);
2778	if (rc != VINF_SUCCESS)
2779	return rc;
2780	}
2781
2782	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2783	/* Check for dirty bit fault */
2784	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2785	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2786	Log(("PGMVerifyAccess: success (dirty)\n"));
2787	else
2788	{
2789	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2790	#else
2791	{
2792	GSTPDE PdeSrc;
2793	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2794	PdeSrc.n.u1Present = 1;
2795	PdeSrc.n.u1Write = 1;
2796	PdeSrc.n.u1Accessed = 1;
2797	PdeSrc.n.u1User = 1;
2798
2799	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2800	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2801	if (uErr & X86_TRAP_PF_US)
2802	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2803	else /* supervisor */
2804	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2805
2806	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2807	if (VBOX_SUCCESS(rc))
2808	{
2809	/* Page was successfully synced */
2810	Log2(("PGMVerifyAccess: success (sync)\n"));
2811	rc = VINF_SUCCESS;
2812	}
2813	else
2814	{
2815	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2816	return VINF_EM_RAW_GUEST_TRAP;
2817	}
2818	}
2819	return rc;
2820
2821	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2822
2823	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2824	return VERR_INTERNAL_ERROR;
2825	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2826	}
2827
2828
2829	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2830	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
2831	/**
2832	* Figures out which kind of shadow page this guest PDE warrants.
2833	*
2834	* @returns Shadow page kind.
2835	* @param pPdeSrc The guest PDE in question.
2836	* @param cr4 The current guest cr4 value.
2837	*/
2838	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2839	{
2840	# if PMG_GST_TYPE == PGM_TYPE_AMD64
2841	if (!pPdeSrc->n.u1Size)
2842	# else
2843	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2844	# endif
2845	return BTH_PGMPOOLKIND_PT_FOR_PT;
2846	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2847	//{
2848	// case 0:
2849	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2850	// case X86_PDE4M_RW:
2851	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2852	// case X86_PDE4M_US:
2853	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2854	// case X86_PDE4M_RW \| X86_PDE4M_US:
2855	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2856	# if 0
2857	// case X86_PDE4M_PAE_NX:
2858	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2859	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2860	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2861	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2862	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2863	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2864	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2865	# endif
2866	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2867	//}
2868	}
2869	# endif
2870	#endif
2871
2872	#undef MY_STAM_COUNTER_INC
2873	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2874
2875
2876	/**
2877	* Syncs the paging hierarchy starting at CR3.
2878	*
2879	* @returns VBox status code, no specials.
2880	* @param pVM The virtual machine.
2881	* @param cr0 Guest context CR0 register
2882	* @param cr3 Guest context CR3 register
2883	* @param cr4 Guest context CR4 register
2884	* @param fGlobal Including global page directories or not
2885	*/
2886	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2887	{
2888	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
2889	/** @todo check if this is really necessary */
2890	HWACCMFlushTLB(pVM);
2891	return VINF_SUCCESS;
2892
2893	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
2894	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2895	fGlobal = true; /* Change this CR3 reload to be a global one. */
2896
2897	/*
2898	* Update page access handlers.
2899	* The virtual are always flushed, while the physical are only on demand.
2900	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2901	* have to look into that later because it will have a bad influence on the performance.
2902	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2903	* bird: Yes, but that won't work for aliases.
2904	*/
2905	/** @todo this MUST go away. See #1557. */
2906	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2907	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2908	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2909
2910	# ifdef PGMPOOL_WITH_MONITORING
2911	/*
2912	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2913	* Occationally we will have to clear all the shadow page tables because we wanted
2914	* to monitor a page which was mapped by too many shadowed page tables. This operation
2915	* sometimes refered to as a 'lightweight flush'.
2916	*/
2917	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2918	pgmPoolMonitorModifiedClearAll(pVM);
2919	else
2920	{
2921	# ifdef IN_RING3
2922	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2923	pgmPoolClearAll(pVM);
2924	# else
2925	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2926	return VINF_PGM_SYNC_CR3;
2927	# endif
2928	}
2929	# endif
2930
2931	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
2932	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2933
2934	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2935	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2936	bool fBigPagesSupported = true;
2937	# else
2938	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2939	# endif
2940
2941	/*
2942	* Get page directory addresses.
2943	*/
2944	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2945	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2946	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64*/
2947	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2948	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2949	# endif
2950	# endif
2951
2952	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2953	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2954	Assert(pPDSrc);
2955	# ifndef IN_GC
2956	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2957	# endif
2958	# endif
2959
2960	/*
2961	* Iterate the page directory.
2962	*/
2963	PPGMMAPPING pMapping;
2964	unsigned iPdNoMapping;
2965	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2966	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2967
2968	/* Only check mappings if they are supposed to be put into the shadow page table. */
2969	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2970	{
2971	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2972	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
2973	}
2974	else
2975	{
2976	pMapping = 0;
2977	iPdNoMapping = ~0U;
2978	}
2979	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2980	for (uint64_t iPML4E = 0; iPML4E < X86_PG_PAE_ENTRIES; iPML4E++)
2981	{
2982	/* Guest PML4E not present (anymore). */
2983	if (!pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPML4E].n.u1Present)
2984	{
2985	/** @todo this is not efficient; figure out if we can reuse the existing cached version */
2986	/* Shadow PML4E present? */
2987	if (pVM->pgm.s.CTXMID(p,PaePML4)->a[iPML4E].n.u1Present)
2988	{
2989	/* Shadow PML4 present, so free all pdpt & pd entries. */
2990	for (uint64_t iPDPTE = 0; iPDPTE < X86_PG_AMD64_PDPE_ENTRIES; iPDPTE++)
2991	{
2992	PX86PDPT pPdptDst;
2993	PX86PDPAE pPDDst;
2994	RTGCUINTPTR GCPtr = (iPML4E << X86_PML4_SHIFT) \|\| (iPDPTE << X86_PDPT_SHIFT);
2995
2996	int rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
2997	if (rc != VINF_SUCCESS)
2998	{
2999	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3000	continue; /* next PDPTE */
3001	}
3002
3003	if (pPdptDst->a[iPDPTE].n.u1Present)
3004	{
3005	for (unsigned iPD = 0; iPD < ELEMENTS(pPDDst->a); iPD++)
3006	{
3007	if ( pPDDst->a[iPD].n.u1Present
3008	&& !(pPDDst->a[iPD].u & PGM_PDFLAGS_MAPPING))
3009	{
3010	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDDst->a[iPD].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_PAE_PD, (iPML4E * X86_PG_PAE_ENTRIES + iPDPTE) * X86_PG_PAE_ENTRIES + iPD);
3011	pPDDst->a[iPD].u = 0;
3012	}
3013	}
3014
3015	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPdptDst->a[iPDPTE].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_PDPT, iPDPTE);
3016	pPdptDst->a[iPDPTE].u = 0;
3017	}
3018	}
3019	}
3020	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pVM->pgm.s.CTXMID(p,PaePML4)->a[iPML4E].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_PML4, iPML4E);
3021	pVM->pgm.s.CTXMID(p,PaePML4)->a[iPML4E].u = 0;
3022	continue;
3023	}
3024
3025	# else
3026	{
3027	# endif
3028	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3029	for (uint64_t iPDPTE = 0; iPDPTE < GST_PDPE_ENTRIES; iPDPTE++)
3030	{
3031	unsigned iPDSrc;
3032	# if PGM_GST_TYPE == PGM_TYPE_PAE
3033	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3034	PX86PDEPAE pPDEDst = &pPDPAE->a[iPDPTE * X86_PG_PAE_ENTRIES];
3035	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPDPTE << X86_PDPT_SHIFT, &iPDSrc);
3036	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
3037	# else
3038	PX86PML4E pPml4eSrc;
3039	X86PDPE PdpeSrc;
3040	PX86PDPT pPdptDst;
3041	PX86PDPAE pPDDst;
3042	PX86PDEPAE pPDEDst;
3043	RTGCUINTPTR GCPtr = (iPML4E << X86_PML4_SHIFT) \|\| (iPDPTE << X86_PDPT_SHIFT);
3044	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3045
3046	int rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
3047	if (rc != VINF_SUCCESS)
3048	{
3049	if (rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
3050	break; /* next PML4E */
3051
3052	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3053	continue; /* next PDPTE */
3054	}
3055	Assert(pPDDst);
3056	pPDEDst = &pPDDst->a[0];
3057	# endif
3058	Assert(iPDSrc == 0);
3059
3060	if (pPDSrc == NULL)
3061	{
3062	/** @todo this is not efficient; figure out if we can reuse the existing cached version */
3063	/* PDPE not present */
3064	if (pPdptDst->a[iPDPTE].n.u1Present)
3065	{
3066	/* for each page directory entry */
3067	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
3068	{
3069	if ( pPDEDst[iPD].n.u1Present
3070	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3071	{
3072	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3073	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_PAE_PD, (iPML4E * X86_PG_PAE_ENTRIES + iPDPTE) * X86_PG_PAE_ENTRIES + iPD);
3074	# else
3075	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_PAE_PD, iPDPTE * X86_PG_PAE_ENTRIES + iPD);
3076	# endif
3077	pPDEDst[iPD].u = 0;
3078	}
3079	}
3080	}
3081	/* Mark it as not present if there's no hypervisor mapping present. (bit flipped at the top of Trap0eHandler) */
3082	if (!(pPdptDst->a[iPDPTE].u & PGM_PLXFLAGS_MAPPING))
3083	{
3084	if (!(pPdptDst->a[iPDPTE].u & PGM_PLXFLAGS_PERMANENT))
3085	{
3086	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPdptDst->a[iPDPTE].u & SHW_PDE_PG_MASK), PGMPOOL_IDX_PDPT, iPDPTE);
3087	pPdptDst->a[iPDPTE].u = 0;
3088	}
3089	else
3090	pPdptDst->a[iPDPTE].n.u1Present = 0;
3091	}
3092	continue; /* next PDPTE */
3093	}
3094	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3095	{
3096	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3097	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
3098	{
3099	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3100	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
3101	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3102	AssertMsg(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst, ("%p vs %p\n", &pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512], pPDEDst));
3103	# endif
3104	register GSTPDE PdeSrc = pPDSrc->a[iPD];
3105	if ( PdeSrc.n.u1Present
3106	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3107	{
3108	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3109	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3110	&& !defined(PGM_WITHOUT_MAPPINGS)
3111
3112	/*
3113	* Check for conflicts with GC mappings.
3114	*/
3115	# if PGM_GST_TYPE == PGM_TYPE_PAE
3116	if (iPD + iPDPTE * X86_PG_PAE_ENTRIES == iPdNoMapping)
3117	# else
3118	if (iPD == iPdNoMapping)
3119	# endif
3120	{
3121	if (pVM->pgm.s.fMappingsFixed)
3122	{
3123	/* It's fixed, just skip the mapping. */
3124	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3125	iPD += cPTs - 1;
3126	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3127	pMapping = pMapping->CTXALLSUFF(pNext);
3128	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3129	continue;
3130	}
3131	# ifdef IN_RING3
3132	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3133	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3134	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3135	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPDPTE << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3136	# endif
3137	if (VBOX_FAILURE(rc))
3138	return rc;
3139
3140	/*
3141	* Update iPdNoMapping and pMapping.
3142	*/
3143	pMapping = pVM->pgm.s.pMappingsR3;
3144	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3145	pMapping = pMapping->pNextR3;
3146	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3147	# else
3148	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3149	return VINF_PGM_SYNC_CR3;
3150	# endif
3151	}
3152	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3153	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3154	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3155	/*
3156	* Sync page directory entry.
3157	*
3158	* The current approach is to allocated the page table but to set
3159	* the entry to not-present and postpone the page table synching till
3160	* it's actually used.
3161	*/
3162	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3163	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3164	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3165	const unsigned iPdShw = iPD + iPDPTE * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3166	# else
3167	const unsigned iPdShw = iPD; NOREF(iPdShw);
3168	# endif
3169	{
3170	SHWPDE PdeDst = *pPDEDst;
3171	if (PdeDst.n.u1Present)
3172	{
3173	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3174	RTGCPHYS GCPhys;
3175	if ( !PdeSrc.b.u1Size
3176	\|\| !fBigPagesSupported)
3177	{
3178	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3179	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3180	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3181	GCPhys \|= i * (PAGE_SIZE / 2);
3182	# endif
3183	}
3184	else
3185	{
3186	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3187	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3188	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3189	GCPhys \|= i * X86_PAGE_2M_SIZE;
3190	# endif
3191	}
3192
3193	if ( pShwPage->GCPhys == GCPhys
3194	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3195	&& ( pShwPage->fCached
3196	\|\| ( !fGlobal
3197	&& ( false
3198	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3199	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3200	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3201	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3202	# else
3203	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3204	# endif
3205	\|\| ( !pShwPage->fSeenNonGlobal
3206	&& (cr4 & X86_CR4_PGE))
3207	# endif
3208	)
3209	)
3210	)
3211	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3212	\|\| ( fBigPagesSupported
3213	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3214	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3215	)
3216	)
3217	{
3218	# ifdef VBOX_WITH_STATISTICS
3219	if ( !fGlobal
3220	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3221	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3222	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3223	# else
3224	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3225	# endif
3226	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
3227	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3228	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
3229	else
3230	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
3231	# endif /* VBOX_WITH_STATISTICS */
3232	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3233	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3234	//# ifdef PGMPOOL_WITH_CACHE
3235	// pgmPoolCacheUsed(pPool, pShwPage);
3236	//# endif
3237	}
3238	else
3239	{
3240	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3241	pPDEDst->u = 0;
3242	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
3243	}
3244	}
3245	else
3246	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
3247	pPDEDst++;
3248	}
3249	}
3250	# if PGM_GST_TYPE == PGM_TYPE_PAE
3251	else if (iPD + iPDPTE * X86_PG_PAE_ENTRIES != iPdNoMapping)
3252	# else
3253	else if (iPD != iPdNoMapping)
3254	# endif
3255	{
3256	/*
3257	* Check if there is any page directory to mark not present here.
3258	*/
3259	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3260	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3261	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3262	const unsigned iPdShw = iPD + iPDPTE * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3263	# else
3264	const unsigned iPdShw = iPD; NOREF(iPdShw);
3265	# endif
3266	{
3267	if (pPDEDst->n.u1Present)
3268	{
3269	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
3270	pPDEDst->u = 0;
3271	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
3272	}
3273	pPDEDst++;
3274	}
3275	}
3276	else
3277	{
3278	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3279	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3280	&& !defined(PGM_WITHOUT_MAPPINGS)
3281
3282	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3283
3284	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3285	if (pVM->pgm.s.fMappingsFixed)
3286	{
3287	/* It's fixed, just skip the mapping. */
3288	pMapping = pMapping->CTXALLSUFF(pNext);
3289	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3290	}
3291	else
3292	{
3293	/*
3294	* Check for conflicts for subsequent pagetables
3295	* and advance to the next mapping.
3296	*/
3297	iPdNoMapping = ~0U;
3298	unsigned iPT = cPTs;
3299	while (iPT-- > 1)
3300	{
3301	if ( pPDSrc->a[iPD + iPT].n.u1Present
3302	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3303	{
3304	# ifdef IN_RING3
3305	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3306	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3307	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3308	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPDPTE << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3309	# endif
3310	if (VBOX_FAILURE(rc))
3311	return rc;
3312
3313	/*
3314	* Update iPdNoMapping and pMapping.
3315	*/
3316	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
3317	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3318	pMapping = pMapping->CTXALLSUFF(pNext);
3319	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3320	break;
3321	# else
3322	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3323	return VINF_PGM_SYNC_CR3;
3324	# endif
3325	}
3326	}
3327	if (iPdNoMapping == ~0U && pMapping)
3328	{
3329	pMapping = pMapping->CTXALLSUFF(pNext);
3330	if (pMapping)
3331	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3332	}
3333	}
3334
3335	/* advance. */
3336	iPD += cPTs - 1;
3337	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3338	# if PGM_GST_TYPE != PGM_SHW_TYPE
3339	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3340	# endif
3341	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3342	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3343	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3344	}
3345
3346	} /* for iPD */
3347	} /* for each PDPTE (PAE) */
3348	} /* for each page map level 4 entry (amd64) */
3349	return VINF_SUCCESS;
3350
3351	# else /* guest real and protected mode */
3352	return VINF_SUCCESS;
3353	# endif
3354	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
3355	}
3356
3357
3358
3359
3360	#ifdef VBOX_STRICT
3361	#ifdef IN_GC
3362	# undef AssertMsgFailed
3363	# define AssertMsgFailed Log
3364	#endif
3365	#ifdef IN_RING3
3366	# include <VBox/dbgf.h>
3367
3368	/**
3369	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3370	*
3371	* @returns VBox status code (VINF_SUCCESS).
3372	* @param pVM The VM handle.
3373	* @param cr3 The root of the hierarchy.
3374	* @param crr The cr4, only PAE and PSE is currently used.
3375	* @param fLongMode Set if long mode, false if not long mode.
3376	* @param cMaxDepth Number of levels to dump.
3377	* @param pHlp Pointer to the output functions.
3378	*/
3379	__BEGIN_DECLS
3380	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3381	__END_DECLS
3382
3383	#endif
3384
3385	/**
3386	* Checks that the shadow page table is in sync with the guest one.
3387	*
3388	* @returns The number of errors.
3389	* @param pVM The virtual machine.
3390	* @param cr3 Guest context CR3 register
3391	* @param cr4 Guest context CR4 register
3392	* @param GCPtr Where to start. Defaults to 0.
3393	* @param cb How much to check. Defaults to everything.
3394	*/
3395	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
3396	{
3397	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
3398	return 0;
3399	#else
3400	unsigned cErrors = 0;
3401
3402	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3403	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
3404
3405	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3406	bool fBigPagesSupported = true;
3407	# else
3408	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3409	# endif
3410	PPGM pPGM = &pVM->pgm.s;
3411	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3412	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3413	# ifndef IN_RING0
3414	RTHCPHYS HCPhys; /* general usage. */
3415	# endif
3416	int rc;
3417
3418	/*
3419	* Check that the Guest CR3 and all its mappings are correct.
3420	*/
3421	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3422	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3423	false);
3424	# ifndef IN_RING0
3425	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3426	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGuestPDGC, NULL, &HCPhysShw);
3427	# else
3428	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePDPTGC, NULL, &HCPhysShw);
3429	# endif
3430	AssertRCReturn(rc, 1);
3431	HCPhys = NIL_RTHCPHYS;
3432	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3433	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
3434	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3435	RTGCPHYS GCPhys;
3436	rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
3437	AssertRCReturn(rc, 1);
3438	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
3439	# endif
3440	#endif /* !IN_RING0 */
3441
3442	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3443	const GSTPD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
3444	# endif
3445
3446	/*
3447	* Get and check the Shadow CR3.
3448	*/
3449	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3450	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
3451	unsigned cPDEs = ELEMENTS(pPDDst->a);
3452	# else
3453	const X86PDPAE pPDDst = pPGM->CTXMID(ap,PaePDs[0]); / use it as a 2048 entry PD */
3454	unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
3455	# endif
3456	if (cb != ~(RTGCUINTPTR)0)
3457	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3458
3459	/** @todo call the other two PGMAssert() functions. /
3460
3461	# if PGM_GST_TYPE == PGM_TYPE_PAE
3462	/*
3463	* Check the 4 PDPTs too.
3464	*/
3465	for (unsigned i = 0; i < 4; i++)
3466	{
3467	RTHCPTR HCPtr;
3468	RTHCPHYS HCPhys;
3469	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
3470	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
3471	if (VBOX_SUCCESS(rc2))
3472	{
3473	AssertMsg( pVM->pgm.s.apGstPaePDsHC[i] == (R3R0PTRTYPE(PX86PDPAE))HCPtr
3474	&& pVM->pgm.s.aGCPhysGstPaePDs[i] == GCPhys,
3475	("idx %d apGstPaePDsHC %VHv vs %VHv aGCPhysGstPaePDs %VGp vs %VGp\n",
3476	i, pVM->pgm.s.apGstPaePDsHC[i], HCPtr, pVM->pgm.s.aGCPhysGstPaePDs[i], GCPhys));
3477	}
3478	}
3479	# endif
3480
3481	/*
3482	* Iterate the shadow page directory.
3483	*/
3484	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3485	unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
3486	cPDEs += iPDDst;
3487	for (;
3488	iPDDst < cPDEs;
3489	iPDDst++, GCPtr += _4G / cPDEs)
3490	{
3491	# if PGM_GST_TYPE == PGM_TYPE_PAE
3492	uint32_t iPDSrc;
3493	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pPGM, (RTGCUINTPTR)GCPtr, &iPDSrc);
3494	if (!pPDSrc)
3495	{
3496	AssertMsg(!pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK].n.u1Present, ("Guest PDTPR not present, shadow PDPTR %VX64\n", pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK].u));
3497	continue;
3498	}
3499	#endif
3500
3501	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3502	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3503	{
3504	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3505	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3506	{
3507	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3508	cErrors++;
3509	continue;
3510	}
3511	}
3512	else if ( (PdeDst.u & X86_PDE_P)
3513	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3514	)
3515	{
3516	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3517	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3518	if (!pPoolPage)
3519	{
3520	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3521	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3522	cErrors++;
3523	continue;
3524	}
3525	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3526
3527	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3528	{
3529	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
3530	GCPtr, (uint64_t)PdeDst.u));
3531	cErrors++;
3532	}
3533
3534	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3535	{
3536	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
3537	GCPtr, (uint64_t)PdeDst.u));
3538	cErrors++;
3539	}
3540
3541	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3542	if (!PdeSrc.n.u1Present)
3543	{
3544	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3545	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3546	cErrors++;
3547	continue;
3548	}
3549
3550	if ( !PdeSrc.b.u1Size
3551	\|\| !fBigPagesSupported)
3552	{
3553	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3554	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3555	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3556	# endif
3557	}
3558	else
3559	{
3560	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3561	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3562	{
3563	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3564	GCPtr, (uint64_t)PdeSrc.u));
3565	cErrors++;
3566	continue;
3567	}
3568	# endif
3569	GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3570	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3571	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3572	# endif
3573	}
3574
3575	if ( pPoolPage->enmKind
3576	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3577	{
3578	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3579	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3580	cErrors++;
3581	}
3582
3583	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3584	if (!pPhysPage)
3585	{
3586	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3587	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3588	cErrors++;
3589	continue;
3590	}
3591
3592	if (GCPhysGst != pPoolPage->GCPhys)
3593	{
3594	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3595	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3596	cErrors++;
3597	continue;
3598	}
3599
3600	if ( !PdeSrc.b.u1Size
3601	\|\| !fBigPagesSupported)
3602	{
3603	/*
3604	* Page Table.
3605	*/
3606	const GSTPT *pPTSrc;
3607	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3608	if (VBOX_FAILURE(rc))
3609	{
3610	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3611	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3612	cErrors++;
3613	continue;
3614	}
3615	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3616	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3617	{
3618	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3619	// (This problem will go away when/if we shadow multiple CR3s.)
3620	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3621	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3622	cErrors++;
3623	continue;
3624	}
3625	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3626	{
3627	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3628	GCPtr, (uint64_t)PdeDst.u));
3629	cErrors++;
3630	continue;
3631	}
3632
3633	/* iterate the page table. */
3634	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3635	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3636	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3637	# else
3638	const unsigned offPTSrc = 0;
3639	# endif
3640	for (unsigned iPT = 0, off = 0;
3641	iPT < ELEMENTS(pPTDst->a);
3642	iPT++, off += PAGE_SIZE)
3643	{
3644	const SHWPTE PteDst = pPTDst->a[iPT];
3645
3646	/* skip not-present entries. */
3647	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3648	continue;
3649	Assert(PteDst.n.u1Present);
3650
3651	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3652	if (!PteSrc.n.u1Present)
3653	{
3654	#ifdef IN_RING3
3655	PGMAssertHandlerAndFlagsInSync(pVM);
3656	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3657	#endif
3658	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3659	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3660	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3661	cErrors++;
3662	continue;
3663	}
3664
3665	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3666	# if 1 /** @todo sync accessed bit properly... */
3667	fIgnoreFlags \|= X86_PTE_A;
3668	# endif
3669
3670	/* match the physical addresses */
3671	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3672	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3673
3674	# ifdef IN_RING3
3675	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3676	if (VBOX_FAILURE(rc))
3677	{
3678	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3679	{
3680	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3681	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3682	cErrors++;
3683	continue;
3684	}
3685	}
3686	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3687	{
3688	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3689	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3690	cErrors++;
3691	continue;
3692	}
3693	# endif
3694
3695	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3696	if (!pPhysPage)
3697	{
3698	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3699	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3700	{
3701	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3702	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3703	cErrors++;
3704	continue;
3705	}
3706	# endif
3707	if (PteDst.n.u1Write)
3708	{
3709	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3710	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3711	cErrors++;
3712	}
3713	fIgnoreFlags \|= X86_PTE_RW;
3714	}
3715	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3716	{
3717	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3718	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3719	cErrors++;
3720	continue;
3721	}
3722
3723	/* flags */
3724	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3725	{
3726	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3727	{
3728	if (PteDst.n.u1Write)
3729	{
3730	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3731	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3732	cErrors++;
3733	continue;
3734	}
3735	fIgnoreFlags \|= X86_PTE_RW;
3736	}
3737	else
3738	{
3739	if (PteDst.n.u1Present)
3740	{
3741	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3742	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3743	cErrors++;
3744	continue;
3745	}
3746	fIgnoreFlags \|= X86_PTE_P;
3747	}
3748	}
3749	else
3750	{
3751	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3752	{
3753	if (PteDst.n.u1Write)
3754	{
3755	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3756	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3757	cErrors++;
3758	continue;
3759	}
3760	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3761	{
3762	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3763	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3764	cErrors++;
3765	continue;
3766	}
3767	if (PteDst.n.u1Dirty)
3768	{
3769	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3770	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3771	cErrors++;
3772	}
3773	# if 0 /** @todo sync access bit properly... */
3774	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3775	{
3776	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3777	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3778	cErrors++;
3779	}
3780	fIgnoreFlags \|= X86_PTE_RW;
3781	# else
3782	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3783	# endif
3784	}
3785	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3786	{
3787	/* access bit emulation (not implemented). */
3788	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3789	{
3790	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3791	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3792	cErrors++;
3793	continue;
3794	}
3795	if (!PteDst.n.u1Accessed)
3796	{
3797	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3798	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3799	cErrors++;
3800	}
3801	fIgnoreFlags \|= X86_PTE_P;
3802	}
3803	# ifdef DEBUG_sandervl
3804	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3805	# endif
3806	}
3807
3808	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3809	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3810	)
3811	{
3812	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3813	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3814	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3815	cErrors++;
3816	continue;
3817	}
3818	} /* foreach PTE */
3819	}
3820	else
3821	{
3822	/*
3823	* Big Page.
3824	*/
3825	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3826	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3827	{
3828	if (PdeDst.n.u1Write)
3829	{
3830	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3831	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3832	cErrors++;
3833	continue;
3834	}
3835	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3836	{
3837	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3838	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3839	cErrors++;
3840	continue;
3841	}
3842	# if 0 /** @todo sync access bit properly... */
3843	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3844	{
3845	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3846	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3847	cErrors++;
3848	}
3849	fIgnoreFlags \|= X86_PTE_RW;
3850	# else
3851	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3852	# endif
3853	}
3854	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3855	{
3856	/* access bit emulation (not implemented). */
3857	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3858	{
3859	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3860	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3861	cErrors++;
3862	continue;
3863	}
3864	if (!PdeDst.n.u1Accessed)
3865	{
3866	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3867	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3868	cErrors++;
3869	}
3870	fIgnoreFlags \|= X86_PTE_P;
3871	}
3872
3873	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3874	{
3875	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3876	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3877	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3878	cErrors++;
3879	}
3880
3881	/* iterate the page table. */
3882	for (unsigned iPT = 0, off = 0;
3883	iPT < ELEMENTS(pPTDst->a);
3884	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3885	{
3886	const SHWPTE PteDst = pPTDst->a[iPT];
3887
3888	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3889	{
3890	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3891	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3892	cErrors++;
3893	}
3894
3895	/* skip not-present entries. */
3896	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3897	continue;
3898
3899	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3900
3901	/* match the physical addresses */
3902	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3903
3904	# ifdef IN_RING3
3905	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3906	if (VBOX_FAILURE(rc))
3907	{
3908	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3909	{
3910	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3911	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3912	cErrors++;
3913	}
3914	}
3915	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3916	{
3917	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3918	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3919	cErrors++;
3920	continue;
3921	}
3922	# endif
3923
3924	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3925	if (!pPhysPage)
3926	{
3927	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3928	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3929	{
3930	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3931	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3932	cErrors++;
3933	continue;
3934	}
3935	# endif
3936	if (PteDst.n.u1Write)
3937	{
3938	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3939	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3940	cErrors++;
3941	}
3942	fIgnoreFlags \|= X86_PTE_RW;
3943	}
3944	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
3945	{
3946	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3947	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3948	cErrors++;
3949	continue;
3950	}
3951
3952	/* flags */
3953	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3954	{
3955	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3956	{
3957	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
3958	{
3959	if (PteDst.n.u1Write)
3960	{
3961	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3962	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3963	cErrors++;
3964	continue;
3965	}
3966	fIgnoreFlags \|= X86_PTE_RW;
3967	}
3968	}
3969	else
3970	{
3971	if (PteDst.n.u1Present)
3972	{
3973	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3974	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3975	cErrors++;
3976	continue;
3977	}
3978	fIgnoreFlags \|= X86_PTE_P;
3979	}
3980	}
3981
3982	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3983	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3984	)
3985	{
3986	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3987	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3988	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3989	cErrors++;
3990	continue;
3991	}
3992	} /* foreach PTE */
3993	}
3994	}
3995	/* not present */
3996
3997	} /* forearch PDE */
3998
3999	# ifdef DEBUG
4000	if (cErrors)
4001	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4002	# endif
4003
4004	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4005	//# error not implemented
4006
4007
4008	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4009	//# error not implemented
4010
4011	/#else: guest real and protected mode /
4012	#endif
4013	return cErrors;
4014
4015	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
4016	}
4017	#endif /* VBOX_STRICT */
4018

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 9682

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