Changeset 9682 in vbox

Timestamp:

Jun 13, 2008 1:27:40 PM (17 years ago)

Author:

vboxsync

Message:

Long mode paging updates

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• PGMAll.cpp (modified) (3 diffs)
• PGMAllBth.h (modified) (9 diffs)

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -723 +723 @@
 #ifndef IN_GC
 /**
- * Gets the SHADOW page directory pointer for the specified address. Allocates
- * backing pages in case the PDPT or page dirctory is missing.
+ * Syncs the SHADOW page directory pointer for the specified address. Allocates
+ * backing pages in case the PDPT or PML4 entry is missing.
  *
  * @returns VBox status.
  * @param   pVM         VM handle.
  * @param   GCPtr       The address.
+ * @param   pGstPml4e   Guest PML4 entry
+ * @param   pGstPdpe    Guest PDPT entry
  * @param   ppPD        Receives address of page directory
  */
-PGMDECL(int) PGMShwGetAllocLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PDPAE *ppPD)
+PGMDECL(int) PGMShwSyncLongModePDPtr(PVM pVM, RTGCUINTPTR64 GCPtr, PX86PML4E pGstPml4e, PX86PDPE pGstPdpe, PX86PDPAE *ppPD)
 {
     PPGM           pPGM   = &pVM->pgm.s;
@@ -756 +758 @@
 
         /* The PDPT was cached or created; hook it up now. */
-        pPml4e->u |= pShwPage->Core.Key;
+        pPml4e->u |=   pShwPage->Core.Key 
+                    | (pGstPml4e->u & ~(X86_PML4E_PG_MASK | X86_PML4E_AVL_MASK | X86_PML4E_PCD | X86_PML4E_PWT));
     }
     else
     {
+        AssertMsg((pGstPml4e->u & (X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_NX)) == (pPml4e->u & (X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_NX)), ("pGstMpl4e.u=%RX64 pPml4e->u=%RX64\n", pGstPml4e->u, pPml4e->u));
+
         pShwPage = pgmPoolGetPage(pPool, pPml4e->u & X86_PML4E_PG_MASK);
         AssertReturn(pShwPage, VERR_INTERNAL_ERROR);
@@ -784 +789 @@
 
         /* The PD was cached or created; hook it up now. */
-        pPdpe->u |= pShwPage->Core.Key;
+        pPdpe->u |=    pShwPage->Core.Key
+                    | (pGstPdpe->u & ~(X86_PDPE_PG_MASK | X86_PDPE_AVL_MASK | X86_PDPE_PCD | X86_PDPE_PWT));
     }
     else
     {
+        AssertMsg((pGstPdpe->u & (X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_NX)) == (pPdpe->u & (X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_NX)), ("pGstPdpe.u=%RX64 pPdpe->u=%RX64\n", pGstPdpe->u, pPdpe->u));
+
         pShwPage = pgmPoolGetPage(pPool, pPdpe->u & X86_PDPE_PG_MASK);
         AssertReturn(pShwPage, VERR_INTERNAL_ERROR);

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -110 +110 @@
 #   elif PGM_GST_TYPE == PGM_TYPE_AMD64
     unsigned     iPDSrc;
-    PX86PML4E    pPml4e;
-    X86PDPE      Pdpe;
+    PX86PML4E    pPml4eSrc;
+    X86PDPE      PdpeSrc;
     PGSTPD       pPDSrc;
 
-    pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4e, &Pdpe, &iPDSrc);
-    Assert(pPml4e);
+    pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
+    Assert(pPml4eSrc);
 #   endif
     /* Quick check for a valid guest trap. */
@@ -149 +149 @@
     const unsigned  iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
     PX86PDPAE       pPDDst;
-
-    rc = PGMShwGetAllocLongModePDPtr(pVM, (RTGCUINTPTR)pvFault, &pPDDst);
+#  if PGM_GST_TYPE == PGM_TYPE_PROT
+    /* AMD-V nested paging */
+    X86PML4E     Pml4eSrc;
+    X86PDPE      PdpeSrc;
+    PX86PML4E    pPml4eSrc = &Pml4eSrc;
+
+    /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
+    Pml4eSrc.u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_NX | X86_PML4E_A;
+    PdpeSrc.u  = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_NX | X86_PDPE_A;
+#  endif
+
+    rc = PGMShwSyncLongModePDPtr(pVM, (RTGCUINTPTR)pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
     if (rc != VINF_SUCCESS)
     {
@@ -1455 +1465 @@
     PX86PDPAE       pPDDst;
     X86PDEPAE       PdeDst;
-
-    int rc = PGMShwGetAllocLongModePDPtr(pVM, GCPtrPage, &pPDDst);
-    if (rc != VINF_SUCCESS)
-    {
-        AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
-        return rc;
-    }
-    Assert(pPDDst);
+    PX86PDPT        pPdpt;
+
+    int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdpt, &pPDDst);
+    AssertRCReturn(rc, rc);
+    Assert(pPDDst && pPdpt);
     PdeDst = pPDDst->a[iPDDst];
 # endif
@@ -2148 +2155 @@
     const unsigned  iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
     PX86PDPAE       pPDDst;
-    rc = PGMShwGetAllocLongModePDPtr(pVM, GCPtrPage, &pPDDst);
+    PX86PDPT        pPdpt;
+    rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdpt, &pPDDst);
     if (rc != VINF_SUCCESS)
     {
@@ -2595 +2603 @@
 #  elif PGM_GST_TYPE == PGM_TYPE_AMD64
     unsigned        iPDSrc;
-    PX86PML4E       pPml4e;
-    X86PDPE         Pdpe;
-    PGSTPD          pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4e, &Pdpe, &iPDSrc);
+    PX86PML4E       pPml4eSrc;
+    X86PDPE         PdpeSrc;
+    PGSTPD          pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
     if (!pPDSrc)
         return VINF_SUCCESS; /* not present */
@@ -2625 +2633 @@
         X86PDEPAE       PdeDst;
 
-        int rc = PGMShwGetAllocLongModePDPtr(pVM, GCPtrPage, &pPDDst);
+#  if PGM_GST_TYPE == PGM_TYPE_PROT
+        /* AMD-V nested paging */
+        X86PML4E     Pml4eSrc;
+        X86PDPE      PdpeSrc;
+        PX86PML4E    pPml4eSrc = &Pml4eSrc;
+
+        /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
+        Pml4eSrc.u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_NX | X86_PML4E_A;
+        PdpeSrc.u  = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_NX | X86_PDPE_A;
+#  endif
+
+        int rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
         if (rc != VINF_SUCCESS)
         {
@@ -2706 +2725 @@
 #  elif PGM_GST_TYPE == PGM_TYPE_AMD64
     unsigned        iPDSrc;
-    PX86PML4E       pPml4e;
-    X86PDPE         Pdpe;
-    PGSTPD          pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4e, &Pdpe, &iPDSrc);
+    PX86PML4E       pPml4eSrc;
+    X86PDPE         PdpeSrc;
+    PGSTPD          pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
     if (!pPDSrc)
     {
@@ -2733 +2752 @@
     PX86PDEPAE      pPdeDst;
 
-    rc = PGMShwGetAllocLongModePDPtr(pVM, GCPtrPage, &pPDDst);
+#  if PGM_GST_TYPE == PGM_TYPE_PROT
+    /* AMD-V nested paging */
+    X86PML4E     Pml4eSrc;
+    X86PDPE      PdpeSrc;
+    PX86PML4E    pPml4eSrc = &Pml4eSrc;
+
+    /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
+    Pml4eSrc.u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_NX | X86_PML4E_A;
+    PdpeSrc.u  = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_NX | X86_PDPE_A;
+#  endif
+
+    rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
     if (rc != VINF_SUCCESS)
     {
@@ -2950 +2980 @@
     for (uint64_t iPML4E = 0; iPML4E < X86_PG_PAE_ENTRIES; iPML4E++)
     {
-        /* Shadow PML4E present? */
-        if (pVM->pgm.s.CTXMID(p,PaePML4)->a[iPML4E].n.u1Present)
+        /* Guest PML4E not present (anymore). */
+        if (!pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPML4E].n.u1Present)
         {
             /** @todo this is not efficient; figure out if we can reuse the existing cached version */
-            /* Guest PML4E not present (anymore). */
-            if (!pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPML4E].n.u1Present)
+            /* Shadow PML4E present? */
+            if (pVM->pgm.s.CTXMID(p,PaePML4)->a[iPML4E].n.u1Present)
             {
                 /* Shadow PML4 present, so free all pdpt & pd entries. */