PGMAllGst.h@ 13266

Last change on this file since 13266 was 13232, checked in by vboxsync, 16 years ago
#1865: changed some validation into pure assertions or assert-return. added some todos, update a comment or five and adjusted lots of whitespace.
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File size: 45.1 KB

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1	/* $Id: PGMAllGst.h 13232 2008-10-13 20:03:48Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Defined Constants And Macros *
25	*******************************************************************************/
26	#undef GSTPT
27	#undef PGSTPT
28	#undef GSTPTE
29	#undef PGSTPTE
30	#undef GSTPD
31	#undef PGSTPD
32	#undef GSTPDE
33	#undef PGSTPDE
34	#undef GST_BIG_PAGE_SIZE
35	#undef GST_BIG_PAGE_OFFSET_MASK
36	#undef GST_PDE_PG_MASK
37	#undef GST_PDE_BIG_PG_MASK
38	#undef GST_PD_SHIFT
39	#undef GST_PD_MASK
40	#undef GST_PTE_PG_MASK
41	#undef GST_PT_SHIFT
42	#undef GST_PT_MASK
43	#undef GST_TOTAL_PD_ENTRIES
44	#undef GST_CR3_PAGE_MASK
45	#undef GST_PDPE_ENTRIES
46	#undef GST_PDPT_SHIFT
47	#undef GST_PDPT_MASK
48	#undef GST_PDPE_PG_MASK
49	#undef GST_GET_PDE_BIG_PG_GCPHYS
50
51	#if PGM_GST_TYPE == PGM_TYPE_REAL \
52	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
53	# define GSTPT SHWPT
54	# define PGSTPT PSHWPT
55	# define GSTPTE SHWPTE
56	# define PGSTPTE PSHWPTE
57	# define GSTPD SHWPD
58	# define PGSTPD PSHWPD
59	# define GSTPDE SHWPDE
60	# define PGSTPDE PSHWPDE
61	# define GST_PTE_PG_MASK SHW_PTE_PG_MASK
62
63	#elif PGM_GST_TYPE == PGM_TYPE_32BIT
64	# define GSTPT X86PT
65	# define PGSTPT PX86PT
66	# define GSTPTE X86PTE
67	# define PGSTPTE PX86PTE
68	# define GSTPD X86PD
69	# define PGSTPD PX86PD
70	# define GSTPDE X86PDE
71	# define PGSTPDE PX86PDE
72	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
73	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
74	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
75	# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
76	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeGst)
77	# define GST_PD_SHIFT X86_PD_SHIFT
78	# define GST_PD_MASK X86_PD_MASK
79	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
80	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
81	# define GST_PT_SHIFT X86_PT_SHIFT
82	# define GST_PT_MASK X86_PT_MASK
83	# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
84
85	#elif PGM_GST_TYPE == PGM_TYPE_PAE \
86	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
87	# define GSTPT X86PTPAE
88	# define PGSTPT PX86PTPAE
89	# define GSTPTE X86PTEPAE
90	# define PGSTPTE PX86PTEPAE
91	# define GSTPD X86PDPAE
92	# define PGSTPD PX86PDPAE
93	# define GSTPDE X86PDEPAE
94	# define PGSTPDE PX86PDEPAE
95	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
96	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
97	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
98	# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
99	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) (PdeGst.u & GST_PDE_BIG_PG_MASK)
100	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
101	# define GST_PD_MASK X86_PD_PAE_MASK
102	# if PGM_GST_TYPE == PGM_TYPE_PAE
103	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
104	# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
105	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
106	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
107	# define GST_PDPT_MASK X86_PDPT_MASK_PAE
108	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
109	# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
110	# else
111	# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
112	# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
113	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
114	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
115	# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
116	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
117	# define GST_CR3_PAGE_MASK X86_CR3_AMD64_PAGE_MASK
118	# endif
119	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
120	# define GST_PT_MASK X86_PT_PAE_MASK
121	#endif
122
123
124	/*******************************************************************************
125	* Internal Functions *
126	*******************************************************************************/
127	__BEGIN_DECLS
128	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
129	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
130	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
131	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
132	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
133	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
134	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
135	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
136	#ifndef IN_RING3
137	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
138	# if PGM_GST_TYPE == PGM_TYPE_PAE \
139	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
140	PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
141	# endif
142	#endif
143	__END_DECLS
144
145
146
147	/**
148	* Gets effective Guest OS page information.
149	*
150	* When GCPtr is in a big page, the function will return as if it was a normal
151	* 4KB page. If the need for distinguishing between big and normal page becomes
152	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
153	* purpose.
154	*
155	* @returns VBox status.
156	* @param pVM VM Handle.
157	* @param GCPtr Guest Context virtual address of the page. Page aligned!
158	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
159	* @param pGCPhys Where to store the GC physical address of the page.
160	* This is page aligned. The fact that the
161	*/
162	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
163	{
164	#if PGM_GST_TYPE == PGM_TYPE_REAL \
165	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
166	/*
167	* Fake it.
168	*/
169	if (pfFlags)
170	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
171	if (pGCPhys)
172	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
173	return VINF_SUCCESS;
174
175	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
176
177	/*
178	* Get the PDE.
179	*/
180	# if PGM_GST_TYPE == PGM_TYPE_32BIT
181	const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
182	#elif PGM_GST_TYPE == PGM_TYPE_PAE
183	X86PDEPAE Pde;
184	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
185
186	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
187	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
188	*/
189	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
190	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
191	PX86PML4E pPml4e;
192	X86PDPE Pdpe;
193	X86PDEPAE Pde;
194	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
195
196	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
197	Assert(pPml4e);
198	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
199	return VERR_PAGE_TABLE_NOT_PRESENT;
200
201	/* Merge accessed, write, user and no-execute bits into the PDE. */
202	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
203	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
204	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
205	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
206	# endif
207
208	/*
209	* Lookup the page.
210	*/
211	if (!Pde.n.u1Present)
212	return VERR_PAGE_TABLE_NOT_PRESENT;
213
214	if ( !Pde.b.u1Size
215	# if PGM_GST_TYPE != PGM_TYPE_AMD64
216	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
217	# endif
218	)
219	{
220	PGSTPT pPT;
221	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
222	if (VBOX_FAILURE(rc))
223	return rc;
224
225	/*
226	* Get PT entry and check presence.
227	*/
228	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
229	if (!Pte.n.u1Present)
230	return VERR_PAGE_NOT_PRESENT;
231
232	/*
233	* Store the result.
234	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
235	* where the PDPE is simplified.
236	*/
237	if (pfFlags)
238	{
239	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
240	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
241	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
242	/* The NX bit is determined by a bitwise OR between the PT and PD */
243	if (fNoExecuteBitValid)
244	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
245	# endif
246	}
247	if (pGCPhys)
248	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
249	}
250	else
251	{
252	/*
253	* Map big to 4k PTE and store the result
254	*/
255	if (pfFlags)
256	{
257	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
258	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
259	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
260	/* The NX bit is determined by a bitwise OR between the PT and PD */
261	if (fNoExecuteBitValid)
262	*pfFlags \|= (Pde.u & X86_PTE_PAE_NX);
263	# endif
264	}
265	if (pGCPhys)
266	*pGCPhys = GST_GET_PDE_BIG_PG_GCPHYS(Pde) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK));
267	}
268	return VINF_SUCCESS;
269	#else
270	# error "shouldn't be here!"
271	/* something else... */
272	return VERR_NOT_SUPPORTED;
273	#endif
274	}
275
276
277	/**
278	* Modify page flags for a range of pages in the guest's tables
279	*
280	* The existing flags are ANDed with the fMask and ORed with the fFlags.
281	*
282	* @returns VBox status code.
283	* @param pVM VM handle.
284	* @param GCPtr Virtual address of the first page in the range. Page aligned!
285	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
286	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
287	* @param fMask The AND mask - page flags X86_PTE_*.
288	*/
289	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
290	{
291	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
292	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
293	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
294
295	for (;;)
296	{
297	/*
298	* Get the PD entry.
299	*/
300	# if PGM_GST_TYPE == PGM_TYPE_32BIT
301	PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
302	# elif PGM_GST_TYPE == PGM_TYPE_PAE
303	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
304	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
305	*/
306	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
307	Assert(pPde);
308	if (!pPde)
309	return VERR_PAGE_TABLE_NOT_PRESENT;
310	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
311	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
312	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
313	Assert(pPde);
314	if (!pPde)
315	return VERR_PAGE_TABLE_NOT_PRESENT;
316	# endif
317	GSTPDE Pde = *pPde;
318	Assert(Pde.n.u1Present);
319	if (!Pde.n.u1Present)
320	return VERR_PAGE_TABLE_NOT_PRESENT;
321
322	if ( !Pde.b.u1Size
323	# if PGM_GST_TYPE != PGM_TYPE_AMD64
324	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
325	# endif
326	)
327	{
328	/*
329	* 4KB Page table
330	*
331	* Walk page tables and pages till we're done.
332	*/
333	PGSTPT pPT;
334	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
335	if (VBOX_FAILURE(rc))
336	return rc;
337
338	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
339	while (iPTE < RT_ELEMENTS(pPT->a))
340	{
341	GSTPTE Pte = pPT->a[iPTE];
342	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
343	\| (fFlags & ~GST_PTE_PG_MASK);
344	pPT->a[iPTE] = Pte;
345
346	/* next page */
347	cb -= PAGE_SIZE;
348	if (!cb)
349	return VINF_SUCCESS;
350	GCPtr += PAGE_SIZE;
351	iPTE++;
352	}
353	}
354	else
355	{
356	/*
357	* 4MB Page table
358	*/
359	# if PGM_GST_TYPE == PGM_TYPE_32BIT
360	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
361	# else
362	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
363	# endif
364	\| (fFlags & ~GST_PTE_PG_MASK)
365	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
366	*pPde = Pde;
367
368	/* advance */
369	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
370	if (cbDone >= cb)
371	return VINF_SUCCESS;
372	cb -= cbDone;
373	GCPtr += cbDone;
374	}
375	}
376
377	#else
378	/* real / protected mode: ignore. */
379	return VINF_SUCCESS;
380	#endif
381	}
382
383
384	/**
385	* Retrieve guest PDE information
386	*
387	* @returns VBox status code.
388	* @param pVM The virtual machine.
389	* @param GCPtr Guest context pointer
390	* @param pPDE Pointer to guest PDE structure
391	*/
392	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
393	{
394	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
395	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
396	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
397
398	# if PGM_GST_TYPE == PGM_TYPE_32BIT
399	X86PDE Pde;
400	Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
401	# elif PGM_GST_TYPE == PGM_TYPE_PAE
402	X86PDEPAE Pde;
403	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
404	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
405	X86PDEPAE Pde;
406	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
407	# endif
408
409	pPDE->u = (X86PGPAEUINT)Pde.u;
410	return VINF_SUCCESS;
411	#else
412	AssertFailed();
413	return VERR_NOT_IMPLEMENTED;
414	#endif
415	}
416
417
418
419	/**
420	* Maps the CR3 into HMA in GC and locate it in HC.
421	*
422	* Note that a MapCR3 call is usually not followed by an UnmapCR3 call; whenever
423	* CR3 is updated we simply call MapCR3 again.
424	*
425	* @returns VBox status, no specials.
426	* @param pVM VM handle.
427	* @param GCPhysCR3 The physical address in the CR3 register.
428	*/
429	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
430	{
431	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
432	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
433	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
434
435	LogFlow(("MapCR3: %VGp\n", GCPhysCR3));
436
437	/*
438	* Map the page CR3 points at.
439	*/
440	RTHCPHYS HCPhysGuestCR3;
441	RTHCPTR HCPtrGuestCR3;
442	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
443	if (VBOX_SUCCESS(rc))
444	{
445	rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
446	if (VBOX_SUCCESS(rc))
447	{
448	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
449	# if PGM_GST_TYPE == PGM_TYPE_32BIT
450	pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
451	pVM->pgm.s.pGuestPDGC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
452
453	# elif PGM_GST_TYPE == PGM_TYPE_PAE
454	unsigned offset = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
455	pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3;
456	pVM->pgm.s.pGstPaePDPTGC = (RCPTRTYPE(PX86PDPT)) ((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + offset);
457	Log(("Cached mapping %VGv\n", pVM->pgm.s.pGstPaePDPTGC));
458
459	/*
460	* Map the 4 PDs too.
461	*/
462	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
463	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
464	{
465	if (pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].n.u1Present)
466	{
467	RTHCPTR HCPtr;
468	RTHCPHYS HCPhys;
469	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
470	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
471	if (VBOX_SUCCESS(rc2))
472	{
473	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
474	AssertRCReturn(rc, rc);
475	pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
476	pVM->pgm.s.apGstPaePDsGC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
477	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
478	PGM_INVL_PG(GCPtr);
479	continue;
480	}
481	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
482	}
483
484	pVM->pgm.s.apGstPaePDsHC[i] = 0;
485	pVM->pgm.s.apGstPaePDsGC[i] = 0;
486	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
487	PGM_INVL_PG(GCPtr);
488	}
489	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
490	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
491
492	pVM->pgm.s.pGstPaePML4HC = (R3R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
493
494	if (!HWACCMIsNestedPagingActive(pVM))
495	{
496	if (pVM->pgm.s.pHCShwAmd64CR3)
497	{
498	/* It might have been freed already by a pool flush (see e.g. PGMR3MappingsUnfix). */
499	if (pVM->pgm.s.pHCShwAmd64CR3->enmKind != PGMPOOLKIND_FREE)
500	pgmPoolFreeByPage(pPool, pVM->pgm.s.pHCShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pHCShwAmd64CR3->GCPhys >> PAGE_SHIFT);
501	pVM->pgm.s.pHCShwAmd64CR3 = 0;
502	pVM->pgm.s.pHCPaePML4 = 0;
503	pVM->pgm.s.HCPhysPaePML4 = 0;
504	}
505
506	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
507	l_try_again:
508	rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.pHCShwAmd64CR3);
509	if (rc == VERR_PGM_POOL_FLUSHED)
510	{
511	Log(("MapCR3: Flush pool and try again\n"));
512	Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
513	rc = pgmPoolSyncCR3(pVM);
514	AssertRC(rc);
515	goto l_try_again;
516	}
517	pVM->pgm.s.pHCPaePML4 = (PX86PML4)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.pHCShwAmd64CR3);
518	pVM->pgm.s.HCPhysPaePML4 = pVM->pgm.s.pHCShwAmd64CR3->Core.Key;
519	}
520	# endif
521	}
522	else
523	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
524	}
525	else
526	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
527
528	#else /* prot/real stub */
529	int rc = VINF_SUCCESS;
530	#endif
531	return rc;
532	}
533
534
535	/**
536	* Unmaps the CR3.
537	*
538	* @returns VBox status, no specials.
539	* @param pVM VM handle.
540	*/
541	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
542	{
543	LogFlow(("UnmapCR3\n"));
544
545	int rc = VINF_SUCCESS;
546
547	#if PGM_GST_TYPE == PGM_TYPE_32BIT
548	pVM->pgm.s.pGuestPDHC = 0;
549	pVM->pgm.s.pGuestPDGC = 0;
550
551	#elif PGM_GST_TYPE == PGM_TYPE_PAE
552	pVM->pgm.s.pGstPaePDPTHC = 0;
553	pVM->pgm.s.pGstPaePDPTGC = 0;
554	for (unsigned i=0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
555	{
556	pVM->pgm.s.apGstPaePDsHC[i] = 0;
557	pVM->pgm.s.apGstPaePDsGC[i] = 0;
558	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
559	}
560
561	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
562	pVM->pgm.s.pGstPaePML4HC = 0;
563	if (!HWACCMIsNestedPagingActive(pVM))
564	{
565	pVM->pgm.s.pHCPaePML4 = 0;
566	if (pVM->pgm.s.pHCShwAmd64CR3)
567	{
568	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
569	pgmPoolFreeByPage(pPool, pVM->pgm.s.pHCShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pHCShwAmd64CR3->GCPhys >> PAGE_SHIFT);
570	pVM->pgm.s.pHCShwAmd64CR3 = NULL;
571	}
572	}
573
574	#else /* prot/real mode stub */
575	/* nothing to do */
576	#endif
577	return rc;
578	}
579
580
581	#undef LOG_GROUP
582	#define LOG_GROUP LOG_GROUP_PGM_POOL
583
584	/**
585	* Registers physical page monitors for the necessary paging
586	* structures to detect conflicts with our guest mappings.
587	*
588	* This is always called after mapping CR3.
589	* This is never called with fixed mappings.
590	*
591	* @returns VBox status, no specials.
592	* @param pVM VM handle.
593	* @param GCPhysCR3 The physical address in the CR3 register.
594	*/
595	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
596	{
597	Assert(!pVM->pgm.s.fMappingsFixed);
598	int rc = VINF_SUCCESS;
599
600	/*
601	* Register/Modify write phys handler for guest's CR3 if it changed.
602	*/
603	#if PGM_GST_TYPE == PGM_TYPE_32BIT
604
605	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
606	{
607	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
608	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
609	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
610	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
611	else
612	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
613	pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
614	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
615	pVM->pgm.s.pfnRCGstWriteHandlerCR3, 0,
616	pVM->pgm.s.pszR3GstWriteHandlerCR3);
617	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
618	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool),
619	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
620	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
621	? PGMPOOL_IDX_PAE_PD
622	: PGMPOOL_IDX_PD,
623	GCPhysCR3);
624	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
625	if (VBOX_FAILURE(rc))
626	{
627	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
628	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
629	return rc;
630	}
631	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
632	}
633
634	#elif PGM_GST_TYPE == PGM_TYPE_PAE
635	/* Monitor the PDPT page */
636	/*
637	* Register/Modify write phys handler for guest's CR3 if it changed.
638	*/
639	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
640	AssertFailed();
641	# endif
642	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
643	{
644	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
645	if (VBOX_FAILURE(rc))
646	{
647	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
648	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
649	return rc;
650	}
651	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
652	}
653
654	/*
655	* Do the 4 PDs.
656	*/
657	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
658	{
659	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present)
660	{
661	RTGCPHYS GCPhys = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
662	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
663	{
664	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
665
666	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
667	}
668
669	if (VBOX_FAILURE(rc))
670	{
671	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
672	rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
673	return rc;
674	}
675	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
676	}
677	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
678	{
679	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
680	AssertRC(rc);
681	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
682	}
683	}
684
685	#else
686	/* prot/real/amd64 mode stub */
687
688	#endif
689	return rc;
690	}
691
692	/**
693	* Deregisters any physical page monitors installed by MonitorCR3.
694	*
695	* @returns VBox status code, no specials.
696	* @param pVM The VM handle.
697	*/
698	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
699	{
700	int rc = VINF_SUCCESS;
701
702	/*
703	* Deregister the access handlers.
704	*
705	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
706	* before we enter GC again.
707	*/
708	#if PGM_GST_TYPE == PGM_TYPE_32BIT
709	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
710	{
711	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
712	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
713	AssertRCReturn(rc, rc);
714	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
715	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool),
716	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
717	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
718	? PGMPOOL_IDX_PAE_PD
719	: PGMPOOL_IDX_PD);
720	AssertRCReturn(rc, rc);
721	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
722	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
723	}
724
725	#elif PGM_GST_TYPE == PGM_TYPE_PAE
726	/* The PDPT page */
727	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
728	AssertFailed();
729	# endif
730
731	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
732	{
733	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PDPT);
734	AssertRC(rc);
735	}
736
737	/* The 4 PDs. */
738	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
739	{
740	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
741	{
742	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
743	int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
744	AssertRC(rc2);
745	if (VBOX_FAILURE(rc2))
746	rc = rc2;
747	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
748	}
749	}
750	#else
751	/* prot/real/amd64 mode stub */
752	#endif
753	return rc;
754
755	}
756
757	#undef LOG_GROUP
758	#define LOG_GROUP LOG_GROUP_PGM
759
760
761	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
762	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
763	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
764	/**
765	* Updates one virtual handler range.
766	*
767	* @returns 0
768	* @param pNode Pointer to a PGMVIRTHANDLER.
769	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
770	*/
771	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
772	{
773	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
774	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
775	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
776
777	#if PGM_GST_TYPE == PGM_TYPE_32BIT
778	PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
779	#endif
780
781	RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->Core.Key;
782	#if PGM_GST_MODE != PGM_MODE_AMD64
783	/* skip all stuff above 4GB if not AMD64 mode. */
784	if (GCPtr >= _4GB)
785	return 0;
786	#endif
787
788	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
789	unsigned iPage = 0;
790	while (iPage < pCur->cPages)
791	{
792	#if PGM_GST_TYPE == PGM_TYPE_32BIT
793	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
794	#elif PGM_GST_TYPE == PGM_TYPE_PAE
795	X86PDEPAE Pde;
796	Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
797	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
798	X86PDEPAE Pde;
799	Pde.u = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
800	#endif
801	if (Pde.n.u1Present)
802	{
803	if ( !Pde.b.u1Size
804	# if PGM_GST_TYPE != PGM_TYPE_AMD64
805	\|\| !(pState->cr4 & X86_CR4_PSE)
806	# endif
807	)
808	{
809	/*
810	* Normal page table.
811	*/
812	PGSTPT pPT;
813	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
814	if (VBOX_SUCCESS(rc))
815	{
816	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
817	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
818	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
819	{
820	GSTPTE Pte = pPT->a[iPTE];
821	RTGCPHYS GCPhysNew;
822	if (Pte.n.u1Present)
823	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
824	else
825	GCPhysNew = NIL_RTGCPHYS;
826	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
827	{
828	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
829	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
830	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
831	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
832	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
833	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
834	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
835	#endif
836	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
837	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
838	}
839	}
840	}
841	else
842	{
843	/* not-present. */
844	offPage = 0;
845	AssertRC(rc);
846	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
847	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
848	iPTE++, iPage++, GCPtr += PAGE_SIZE)
849	{
850	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
851	{
852	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
853	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
854	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
855	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
856	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
857	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
858	#endif
859	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
860	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
861	}
862	}
863	}
864	}
865	else
866	{
867	/*
868	* 2/4MB page.
869	*/
870	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
871	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
872	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
873	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
874	{
875	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
876	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
877	{
878	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
879	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
880	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
881	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
882	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
883	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
884	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
885	#endif
886	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
887	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
888	}
889	}
890	} /* pde type */
891	}
892	else
893	{
894	/* not-present. */
895	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
896	cPages && iPage < pCur->cPages;
897	iPage++, GCPtr += PAGE_SIZE)
898	{
899	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
900	{
901	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
902	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
903	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
904	}
905	}
906	offPage = 0;
907	}
908	} /* for pages in virtual mapping. */
909
910	return 0;
911	}
912	#endif /* 32BIT, PAE and AMD64 */
913
914
915	/**
916	* Updates the virtual page access handlers.
917	*
918	* @returns true if bits were flushed.
919	* @returns false if bits weren't flushed.
920	* @param pVM VM handle.
921	* @param pPDSrc The page directory.
922	* @param cr4 The cr4 register value.
923	*/
924	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
925	{
926	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
927	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
928	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
929
930	/** @todo
931	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
932	*/
933
934	/*
935	* Resolve any virtual address based access handlers to GC physical addresses.
936	* This should be fairly quick.
937	*/
938	PGMHVUSTATE State;
939
940	pgmLock(pVM);
941	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
942	State.pVM = pVM;
943	State.fTodo = pVM->pgm.s.fSyncFlags;
944	State.cr4 = cr4;
945	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
946	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
947
948
949	/*
950	* Set / reset bits?
951	*/
952	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
953	{
954	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
955	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
956	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
957	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
958	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
959	}
960	pgmUnlock(pVM);
961
962	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
963
964	#else /* real / protected */
965	return false;
966	#endif
967	}
968
969
970	#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
971
972	/**
973	* Write access handler for the Guest CR3 page in 32-bit mode.
974	*
975	* This will try interpret the instruction, if failure fail back to the recompiler.
976	* Check if the changed PDEs are marked present and conflicts with our
977	* mappings. If conflict, we'll switch to the host context and resolve it there
978	*
979	* @returns VBox status code (appropritate for trap handling and GC return).
980	* @param pVM VM Handle.
981	* @param uErrorCode CPU Error code.
982	* @param pRegFrame Trap register frame.
983	* @param pvFault The fault address (cr2).
984	* @param GCPhysFault The GC physical address corresponding to pvFault.
985	* @param pvUser User argument.
986	*/
987	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
988	{
989	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
990
991	/*
992	* Try interpret the instruction.
993	*/
994	uint32_t cb;
995	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
996	if (VBOX_SUCCESS(rc) && cb)
997	{
998	/*
999	* Check if the modified PDEs are present and mappings.
1000	*/
1001	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1002	const unsigned iPD1 = offPD / sizeof(X86PDE);
1003	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
1004
1005	Assert(cb > 0 && cb <= 8);
1006	Assert(iPD1 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a)); /// @todo R3/R0 separation.
1007	Assert(iPD2 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a));
1008
1009	#ifdef DEBUG
1010	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD1, iPD1 << X86_PD_SHIFT));
1011	if (iPD1 != iPD2)
1012	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD2, iPD2 << X86_PD_SHIFT));
1013	#endif
1014
1015	if (!pVM->pgm.s.fMappingsFixed)
1016	{
1017	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
1018	if ( ( pPDSrc->a[iPD1].n.u1Present
1019	&& pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
1020	\|\| ( iPD1 != iPD2
1021	&& pPDSrc->a[iPD2].n.u1Present
1022	&& pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
1023	)
1024	{
1025	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteConflict);
1026	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1027	if (rc == VINF_SUCCESS)
1028	rc = VINF_PGM_SYNC_CR3;
1029	Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
1030	return rc;
1031	}
1032	}
1033
1034	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1035	}
1036	else
1037	{
1038	Assert(VBOX_FAILURE(rc));
1039	if (rc == VERR_EM_INTERPRETER)
1040	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1041	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1042	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1043	}
1044	return rc;
1045	}
1046
1047	#endif /* PGM_TYPE_32BIT && !IN_RING3 */
1048	#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
1049
1050	/**
1051	* Write access handler for the Guest CR3 page in PAE mode.
1052	*
1053	* This will try interpret the instruction, if failure fail back to the recompiler.
1054	* Check if the changed PDEs are marked present and conflicts with our
1055	* mappings. If conflict, we'll switch to the host context and resolve it there
1056	*
1057	* @returns VBox status code (appropritate for trap handling and GC return).
1058	* @param pVM VM Handle.
1059	* @param uErrorCode CPU Error code.
1060	* @param pRegFrame Trap register frame.
1061	* @param pvFault The fault address (cr2).
1062	* @param GCPhysFault The GC physical address corresponding to pvFault.
1063	* @param pvUser User argument.
1064	*/
1065	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1066	{
1067	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1068
1069	/*
1070	* Try interpret the instruction.
1071	*/
1072	uint32_t cb;
1073	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1074	if (VBOX_SUCCESS(rc) && cb)
1075	{
1076	/*
1077	* Check if any of the PDs have changed.
1078	* We'll simply check all of them instead of figuring out which one/two to check.
1079	*/
1080	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1081	{
1082	if ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present
1083	&& ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK)
1084	!= pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1085	{
1086	/*
1087	* The PDPE has changed.
1088	* We will schedule a monitoring update for the next TLB Flush,
1089	* InvalidatePage or SyncCR3.
1090	*
1091	* This isn't perfect, because a lazy page sync might be dealing with an half
1092	* updated PDPE. However, we assume that the guest OS is disabling interrupts
1093	* and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1094	* executing.
1095	*/
1096	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1097	Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%VGp\n",
1098	i, CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1099	}
1100	}
1101
1102	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1103	}
1104	else
1105	{
1106	Assert(VBOX_FAILURE(rc));
1107	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1108	if (rc == VERR_EM_INTERPRETER)
1109	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1110	}
1111	Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1112	return rc;
1113	}
1114
1115
1116	/**
1117	* Write access handler for the Guest PDs in PAE mode.
1118	*
1119	* This will try interpret the instruction, if failure fail back to the recompiler.
1120	* Check if the changed PDEs are marked present and conflicts with our
1121	* mappings. If conflict, we'll switch to the host context and resolve it there
1122	*
1123	* @returns VBox status code (appropritate for trap handling and GC return).
1124	* @param pVM VM Handle.
1125	* @param uErrorCode CPU Error code.
1126	* @param pRegFrame Trap register frame.
1127	* @param pvFault The fault address (cr2).
1128	* @param GCPhysFault The GC physical address corresponding to pvFault.
1129	* @param pvUser User argument.
1130	*/
1131	PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1132	{
1133	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1134
1135	/*
1136	* Try interpret the instruction.
1137	*/
1138	uint32_t cb;
1139	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1140	if (VBOX_SUCCESS(rc) && cb)
1141	{
1142	/*
1143	* Figure out which of the 4 PDs this is.
1144	*/
1145	RTGCUINTPTR i;
1146	for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1147	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1148	{
1149	PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1150	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1151	const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1152	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1153
1154	Assert(cb > 0 && cb <= 8);
1155	Assert(iPD1 < X86_PG_PAE_ENTRIES);
1156	Assert(iPD2 < X86_PG_PAE_ENTRIES);
1157
1158	#ifdef DEBUG
1159	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%VGv)\n",
1160	i, iPD1, (i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT)));
1161	if (iPD1 != iPD2)
1162	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%VGv)\n",
1163	i, iPD2, (i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT)));
1164	#endif
1165
1166	if (!pVM->pgm.s.fMappingsFixed)
1167	{
1168	if ( ( pPDSrc->a[iPD1].n.u1Present
1169	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT))) )
1170	\|\| ( iPD1 != iPD2
1171	&& pPDSrc->a[iPD2].n.u1Present
1172	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT))) )
1173	)
1174	{
1175	Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1176	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteConflict);
1177	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1178	return VINF_PGM_SYNC_CR3;
1179	}
1180	}
1181	break; /* ASSUMES no duplicate entries... */
1182	}
1183	Assert(i < 4);
1184
1185	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1186	}
1187	else
1188	{
1189	Assert(VBOX_FAILURE(rc));
1190	if (rc == VERR_EM_INTERPRETER)
1191	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1192	else
1193	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1194	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1195	}
1196	return rc;
1197	}
1198
1199	#endif /* PGM_TYPE_PAE && !IN_RING3 */
1200

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 13266

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