VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 14853

Last change on this file since 14853 was 13960, checked in by vboxsync, 16 years ago

Moved guest and host CPU contexts into per-VCPU array.
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File size: 11.9 KB
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1/* $Id: CPUMR0.cpp 13960 2008-11-07 13:04:45Z vboxsync $ */
2/** @file
3 * CPUM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_CPUM
27#include <VBox/cpum.h>
28#include "CPUMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/err.h>
32#include <VBox/log.h>
33#include <iprt/assert.h>
34#include <iprt/asm.h>
35
36
37
38/**
39 * Does Ring-0 CPUM initialization.
40 *
41 * This is mainly to check that the Host CPU mode is compatible
42 * with VBox.
43 *
44 * @returns VBox status code.
45 * @param pVM The VM to operate on.
46 */
47VMMR0DECL(int) CPUMR0Init(PVM pVM)
48{
49 LogFlow(("CPUMR0Init: %p\n", pVM));
50
51 /*
52 * Check CR0 & CR4 flags.
53 */
54 uint32_t u32CR0 = ASMGetCR0();
55 if ((u32CR0 & (X86_CR0_PE | X86_CR0_PG)) != (X86_CR0_PE | X86_CR0_PG)) /* a bit paranoid perhaps.. */
56 {
57 Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
58 return VERR_UNSUPPORTED_CPU_MODE;
59 }
60
61 /*
62 * Check for sysenter if it's used.
63 */
64 if (ASMHasCpuId())
65 {
66 uint32_t u32CpuVersion;
67 uint32_t u32Dummy;
68 uint32_t u32Features;
69 ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &u32Features);
70 uint32_t u32Family = u32CpuVersion >> 8;
71 uint32_t u32Model = (u32CpuVersion >> 4) & 0xF;
72 uint32_t u32Stepping = u32CpuVersion & 0xF;
73
74 /*
75 * Intel docs claim you should test both the flag and family, model & stepping.
76 * Some Pentium Pro cpus have the SEP cpuid flag set, but don't support it.
77 */
78 if ( (u32Features & X86_CPUID_FEATURE_EDX_SEP)
79 && !(u32Family == 6 && u32Model < 3 && u32Stepping < 3))
80 {
81 /*
82 * Read the MSR and see if it's in use or not.
83 */
84 uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
85 if (u32)
86 {
87 for (unsigned i=0;i<pVM->cCPUs;i++)
88 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_SYSENTER;
89
90 Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
91 }
92 }
93
94 /** @todo check for AMD and syscall!!!!!! */
95 }
96
97
98 /*
99 * Check if debug registers are armed.
100 * This ASSUMES that DR7.GD is not set, or that it's handled transparently!
101 */
102 uint32_t u32DR7 = ASMGetDR7();
103 if (u32DR7 & X86_DR7_ENABLED_MASK)
104 {
105 for (unsigned i=0;i<pVM->cCPUs;i++)
106 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST;
107 Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
108 }
109
110 return VINF_SUCCESS;
111}
112
113
114/**
115 * Lazily sync in the FPU/XMM state
116 *
117 * @returns VBox status code.
118 * @param pVM VM handle.
119 * @param pVCpu VMCPU handle.
120 * @param pCtx CPU context
121 */
122VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
123{
124 Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
125 Assert(ASMGetCR4() & X86_CR4_OSFSXR);
126
127 /* If the FPU state has already been loaded, then it's a guest trap. */
128 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU)
129 {
130 Assert( ((pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
131 || ((pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)));
132 return VINF_EM_RAW_GUEST_TRAP;
133 }
134
135 /*
136 * There are two basic actions:
137 * 1. Save host fpu and restore guest fpu.
138 * 2. Generate guest trap.
139 *
140 * When entering the hypervisor we'll always enable MP (for proper wait
141 * trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
142 * is taken from the guest OS in order to get proper SSE handling.
143 *
144 *
145 * Actions taken depending on the guest CR0 flags:
146 *
147 * 3 2 1
148 * TS | EM | MP | FPUInstr | WAIT :: VMM Action
149 * ------------------------------------------------------------------------
150 * 0 | 0 | 0 | Exec | Exec :: Clear TS & MP, Save HC, Load GC.
151 * 0 | 0 | 1 | Exec | Exec :: Clear TS, Save HC, Load GC.
152 * 0 | 1 | 0 | #NM | Exec :: Clear TS & MP, Save HC, Load GC.
153 * 0 | 1 | 1 | #NM | Exec :: Clear TS, Save HC, Load GC.
154 * 1 | 0 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
155 * 1 | 0 | 1 | #NM | #NM :: Go to guest taking trap there.
156 * 1 | 1 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
157 * 1 | 1 | 1 | #NM | #NM :: Go to guest taking trap there.
158 */
159
160 switch (pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
161 {
162 case X86_CR0_MP | X86_CR0_TS:
163 case X86_CR0_MP | X86_CR0_EM | X86_CR0_TS:
164 return VINF_EM_RAW_GUEST_TRAP;
165 default:
166 break;
167 }
168
169#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
170 uint64_t oldMsrEFERHost;
171 uint32_t oldCR0 = ASMGetCR0();
172
173 /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
174 if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
175 {
176 /** @todo Do we really need to read this every time?? The host could change this on the fly though.
177 * bird: what about starting by skipping the ASMWrMsr below if we didn't
178 * change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
179 oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
180 if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
181 {
182 ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
183 pVCpu->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
184 }
185 }
186
187 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
188 int rc = CPUMHandleLazyFPU(pVM, pVCpu);
189 AssertRC(rc);
190 Assert(CPUMIsGuestFPUStateActive(pVCpu));
191
192 /* Restore EFER MSR */
193 if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
194 ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
195
196 /* CPUMHandleLazyFPU could have changed CR0; restore it. */
197 ASMSetCR0(oldCR0);
198
199#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
200
201 /*
202 * Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
203 * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
204 */
205 pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
206 if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
207 pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
208
209 CPUMLoadFPUAsm(pCtx);
210
211 /*
212 * The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
213 *
214 * MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
215 */
216 if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
217 {
218 /** @todo Do we really need to read this every time?? The host could change this on the fly though. */
219 uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
220
221 if (msrEFERHost & MSR_K6_EFER_FFXSR)
222 {
223 /* fxrstor doesn't restore the XMM state! */
224 CPUMLoadXMMAsm(pCtx);
225 pVCpu->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
226 }
227 }
228#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
229
230 pVCpu->cpum.s.fUseFlags |= CPUM_USED_FPU;
231 return VINF_SUCCESS;
232}
233
234
235/**
236 * Save guest FPU/XMM state
237 *
238 * @returns VBox status code.
239 * @param pVM VM handle.
240 * @param pVCpu VMCPU handle.
241 * @param pCtx CPU context
242 */
243VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
244{
245 Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
246 Assert(ASMGetCR4() & X86_CR4_OSFSXR);
247 AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
248
249#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
250 uint64_t oldMsrEFERHost;
251
252 /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
253 if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
254 {
255 oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
256 ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
257 }
258 CPUMRestoreHostFPUState(pVM, pVCpu);
259
260 /* Restore EFER MSR */
261 if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
262 ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost | MSR_K6_EFER_FFXSR);
263
264#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
265 CPUMSaveFPUAsm(pCtx);
266 if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
267 {
268 /* fxsave doesn't save the XMM state! */
269 CPUMSaveXMMAsm(pCtx);
270 }
271
272 /*
273 * Restore the original FPU control word and MXCSR.
274 * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
275 */
276 CPUMSetFCW(pVCpu->cpum.s.Host.fpu.FCW);
277 if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
278 CPUMSetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
279#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
280
281 pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU | CPUM_MANUAL_XMM_RESTORE);
282 return VINF_SUCCESS;
283}
284
285
286/**
287 * Save guest debug state
288 *
289 * @returns VBox status code.
290 * @param pVM VM handle.
291 * @param pVCpu VMCPU handle.
292 * @param pCtx CPU context
293 * @param fDR6 Include DR6 or not
294 */
295VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
296{
297 Assert(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);
298
299 /* Save the guest's debug state. The caller is responsible for DR7. */
300 pCtx->dr[0] = ASMGetDR0();
301 pCtx->dr[1] = ASMGetDR1();
302 pCtx->dr[2] = ASMGetDR2();
303 pCtx->dr[3] = ASMGetDR3();
304 if (fDR6)
305 pCtx->dr[6] = ASMGetDR6();
306
307 /*
308 * Restore the host's debug state. DR0-3, DR6 and only then DR7!
309 * DR7 contains 0x400 right now.
310 */
311 ASMSetDR0(pVCpu->cpum.s.Host.dr0);
312 ASMSetDR1(pVCpu->cpum.s.Host.dr1);
313 ASMSetDR2(pVCpu->cpum.s.Host.dr2);
314 ASMSetDR3(pVCpu->cpum.s.Host.dr3);
315 ASMSetDR6(pVCpu->cpum.s.Host.dr6);
316 ASMSetDR7(pVCpu->cpum.s.Host.dr7);
317
318 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
319 return VINF_SUCCESS;
320}
321
322
323/**
324 * Lazily sync in the debug state
325 *
326 * @returns VBox status code.
327 * @param pVM VM handle.
328 * @param pVCpu VMCPU handle.
329 * @param pCtx CPU context
330 * @param fDR6 Include DR6 or not
331 */
332VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
333{
334 /* Save the host state. */
335 pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
336 pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
337 pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
338 pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
339 pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
340 /** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
341 pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
342 /* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
343 ASMSetDR7(X86_DR7_INIT_VAL);
344
345 /* Activate the guest state DR0-3; DR7 is left to the caller. */
346 ASMSetDR0(pCtx->dr[0]);
347 ASMSetDR1(pCtx->dr[1]);
348 ASMSetDR2(pCtx->dr[2]);
349 ASMSetDR3(pCtx->dr[3]);
350 if (fDR6)
351 ASMSetDR6(pCtx->dr[6]);
352
353 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
354 return VINF_SUCCESS;
355}
356
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