HMR0.cpp@ 49966

Last change on this file since 49966 was 49934, checked in by vboxsync, 11 years ago
VMM/HMR0: Don't unnecessarily reset uCurrentAsid.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 71.9 KB

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1	/* $Id: HMR0.cpp 49934 2013-12-16 14:51:20Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback,(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
93	bool fEnabledByHost, void *pvArg));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxAsid;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	/** @todo This isn't used for anything relevant. Remove later? */
117	uint64_t u64HostCr4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121
122	/** VMX MSR values */
123	VMXMSRS Msrs;
124
125	/* Last instruction error */
126	uint32_t ulLastInstrError;
127	} vmx;
128
129	/** AMD-V information. */
130	struct
131	{
132	/* HWCR MSR (for diagnostics) */
133	uint64_t u64MsrHwcr;
134
135	/** SVM revision. */
136	uint32_t u32Rev;
137
138	/** SVM feature bits from cpuid 0x8000000a */
139	uint32_t u32Features;
140
141	/** Set by us to indicate SVM is supported by the CPU. */
142	bool fSupported;
143	} svm;
144	/** Saved error from detection */
145	int32_t lLastError;
146
147	struct
148	{
149	uint32_t u32AMDFeatureECX;
150	uint32_t u32AMDFeatureEDX;
151	} cpuid;
152
153	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
154	* enabled and disabled each time it's used to execute guest code. */
155	bool fGlobalInit;
156	/** Indicates whether the host is suspending or not. We'll refuse a few
157	* actions when the host is being suspended to speed up the suspending and
158	* avoid trouble. */
159	volatile bool fSuspended;
160
161	/** Whether we've already initialized all CPUs.
162	* @remarks We could check the EnableAllCpusOnce state, but this is
163	* simpler and hopefully easier to understand. */
164	bool fEnabled;
165	/** Serialize initialization in HMR0EnableAllCpus. */
166	RTONCE EnableAllCpusOnce;
167	} g_HvmR0;
168
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	/**
212	* Get the CPU ID on which the failure status code was reported.
213	*
214	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
215	* @param pFirstRc The first return code structure.
216	*/
217	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
218	{
219	return pFirstRc->idCpu;
220	}
221	#endif /* VBOX_STRICT */
222
223
224	/** @name Dummy callback handlers.
225	* @{ */
226
227	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
228	{
229	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
230	return VINF_SUCCESS;
231	}
232
233	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
234	{
235	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
236	}
237
238	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
239	bool fEnabledBySystem, void *pvArg)
240	{
241	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
242	return VINF_SUCCESS;
243	}
244
245	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
246	{
247	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
248	return VINF_SUCCESS;
249	}
250
251	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
252	{
253	NOREF(pVM);
254	return VINF_SUCCESS;
255	}
256
257	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
258	{
259	NOREF(pVM);
260	return VINF_SUCCESS;
261	}
262
263	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
264	{
265	NOREF(pVM);
266	return VINF_SUCCESS;
267	}
268
269	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
270	{
271	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
272	return VINF_SUCCESS;
273	}
274
275	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
276	{
277	NOREF(pVM); NOREF(pVCpu);
278	return VINF_SUCCESS;
279	}
280
281	/** @} */
282
283
284	/**
285	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
286	* Down at the Rate Specified" erratum.
287	*
288	* Errata names and related steppings:
289	* - BA86 - D0.
290	* - AAX65 - C2.
291	* - AAU65 - C2, K0.
292	* - AAO95 - B1.
293	* - AAT59 - C2.
294	* - AAK139 - D0.
295	* - AAM126 - C0, C1, D0.
296	* - AAN92 - B1.
297	* - AAJ124 - C0, D0.
298	*
299	* - AAP86 - B1.
300	*
301	* Steppings: B1, C0, C1, C2, D0, K0.
302	*
303	* @returns true if subject to it, false if not.
304	*/
305	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
306	{
307	uint32_t u = ASMCpuId_EAX(1);
308	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
309	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
310	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
311	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
312	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
313	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
314	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
315	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
316	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
317	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
318	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
319	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
320	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
321	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
322	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
323	)
324	return true;
325	return false;
326	}
327
328
329	/**
330	* Intel specific initialization code.
331	*
332	* @returns VBox status code (will only fail if out of memory).
333	*/
334	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
335	{
336	/*
337	* Check that all the required VT-x features are present.
338	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
339	*/
340	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
341	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
342	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
343	)
344	{
345	/** @todo move this into a separate function. */
346	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
347
348	/*
349	* First try use native kernel API for controlling VT-x.
350	* (This is only supported by some Mac OS X kernels atm.)
351	*/
352	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
353	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
354	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
355	{
356	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
357	if (RT_SUCCESS(rc))
358	{
359	g_HvmR0.vmx.fSupported = true;
360	rc = SUPR0EnableVTx(false /* fEnable */);
361	AssertLogRelRC(rc);
362	}
363	}
364	else
365	{
366	/* We need to check if VT-x has been properly initialized on all
367	CPUs. Some BIOSes do a lousy job. */
368	HMR0FIRSTRC FirstRc;
369	hmR0FirstRcInit(&FirstRc);
370	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
371	if (RT_SUCCESS(g_HvmR0.lLastError))
372	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
373	}
374	if (RT_SUCCESS(g_HvmR0.lLastError))
375	{
376	/* Reread in case it was changed by hmR0InitIntelCpu(). */
377	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
378
379	/*
380	* Read all relevant registers and MSRs.
381	*/
382	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
383	g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
384	g_HvmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
385	g_HvmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
386	g_HvmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
387	g_HvmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
388	g_HvmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
389	g_HvmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
390	g_HvmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
391	g_HvmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
392	g_HvmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
393	g_HvmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
394	g_HvmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
395	/* VPID 16 bits ASID. */
396	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
397
398	if (g_HvmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
399	{
400	g_HvmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
401	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
402	g_HvmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
403
404	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
405	g_HvmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
406	}
407
408	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
409	{
410	/*
411	* Enter root mode
412	*/
413	RTR0MEMOBJ hScatchMemObj;
414	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
415	if (RT_FAILURE(rc))
416	{
417	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
418	return rc;
419	}
420
421	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
422	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
423	ASMMemZeroPage(pvScatchPage);
424
425	/* Set revision dword at the beginning of the structure. */
426	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.Msrs.u64BasicInfo);
427
428	/* Make sure we don't get rescheduled to another cpu during this probe. */
429	RTCCUINTREG fFlags = ASMIntDisableFlags();
430
431	/*
432	* Check CR4.VMXE
433	*/
434	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
435	if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
436	{
437	/* In theory this bit could be cleared behind our back. Which would cause
438	#UD faults when we try to execute the VMX instructions... */
439	ASMSetCR4(g_HvmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
440	}
441
442	/*
443	* The only way of checking if we're in VMX root mode or not is to try and enter it.
444	* There is no instruction or control bit that tells us if we're in VMX root mode.
445	* Therefore, try and enter VMX root mode here.
446	*/
447	rc = VMXEnable(HCPhysScratchPage);
448	if (RT_SUCCESS(rc))
449	{
450	g_HvmR0.vmx.fSupported = true;
451	VMXDisable();
452	}
453	else
454	{
455	/*
456	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
457	* it will crash the host when we enter raw mode, because:
458	*
459	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
460	* this bit), and
461	* (b) turning off paging causes a #GP (unavoidable when switching
462	* from long to 32 bits mode or 32 bits to PAE).
463	*
464	* They should fix their code, but until they do we simply refuse to run.
465	*/
466	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
467	Assert(g_HvmR0.vmx.fSupported == false);
468	}
469
470	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
471	if it wasn't so before (some software could incorrectly
472	think it's in VMX mode). */
473	ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
474	ASMSetFlags(fFlags);
475
476	RTR0MemObjFree(hScatchMemObj, false);
477	}
478
479	if (g_HvmR0.vmx.fSupported)
480	{
481	rc = VMXR0GlobalInit();
482	if (RT_FAILURE(rc))
483	g_HvmR0.lLastError = rc;
484
485	/*
486	* Install the VT-x methods.
487	*/
488	g_HvmR0.pfnEnterSession = VMXR0Enter;
489	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
490	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
491	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
492	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
493	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
494	g_HvmR0.pfnInitVM = VMXR0InitVM;
495	g_HvmR0.pfnTermVM = VMXR0TermVM;
496	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
497
498	/*
499	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
500	* Timer Does Not Count Down at the Rate Specified" erratum.
501	*/
502	if (g_HvmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
503	{
504	g_HvmR0.vmx.fUsePreemptTimer = true;
505	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.Msrs.u64Misc);
506	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
507	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
508	}
509	}
510	}
511	#ifdef LOG_ENABLED
512	else
513	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
514	#endif
515	}
516	else
517	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
518	return VINF_SUCCESS;
519	}
520
521
522	/**
523	* AMD-specific initialization code.
524	*
525	* @returns VBox status code.
526	*/
527	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
528	{
529	/*
530	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
531	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
532	*/
533	int rc;
534	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
535	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
536	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
537	&& ASMIsValidExtRange(uMaxExtLeaf)
538	&& uMaxExtLeaf >= 0x8000000a
539	)
540	{
541	/* Call the global AMD-V initialization routine. */
542	rc = SVMR0GlobalInit();
543	if (RT_FAILURE(rc))
544	{
545	g_HvmR0.lLastError = rc;
546	return rc;
547	}
548
549	/*
550	* Install the AMD-V methods.
551	*/
552	g_HvmR0.pfnEnterSession = SVMR0Enter;
553	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
554	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
555	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
556	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
557	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
558	g_HvmR0.pfnInitVM = SVMR0InitVM;
559	g_HvmR0.pfnTermVM = SVMR0TermVM;
560	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
561
562	/* Query AMD features. */
563	uint32_t u32Dummy;
564	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
565
566	/*
567	* We need to check if AMD-V has been properly initialized on all CPUs.
568	* Some BIOSes might do a poor job.
569	*/
570	HMR0FIRSTRC FirstRc;
571	hmR0FirstRcInit(&FirstRc);
572	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
573	AssertRC(rc);
574	if (RT_SUCCESS(rc))
575	rc = hmR0FirstRcGetStatus(&FirstRc);
576	#ifndef DEBUG_bird
577	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
578	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
579	#endif
580	if (RT_SUCCESS(rc))
581	{
582	/* Read the HWCR MSR for diagnostics. */
583	g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
584	g_HvmR0.svm.fSupported = true;
585	}
586	else
587	{
588	g_HvmR0.lLastError = rc;
589	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
590	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
591	}
592	}
593	else
594	{
595	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
596	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
597	}
598	return rc;
599	}
600
601
602	/**
603	* Does global Ring-0 HM initialization (at module init).
604	*
605	* @returns VBox status code.
606	*/
607	VMMR0_INT_DECL(int) HMR0Init(void)
608	{
609	/*
610	* Initialize the globals.
611	*/
612	g_HvmR0.fEnabled = false;
613	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
614	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
615	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
616	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
617
618	/* Fill in all callbacks with placeholders. */
619	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
620	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
621	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
622	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
623	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
624	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
625	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
626	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
627	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
628
629	/* Default is global VT-x/AMD-V init. */
630	g_HvmR0.fGlobalInit = true;
631
632	/*
633	* Make sure aCpuInfo is big enough for all the CPUs on this system.
634	*/
635	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
636	{
637	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
638	return VERR_TOO_MANY_CPUS;
639	}
640
641	/*
642	* Check for VT-x and AMD-V capabilities.
643	*/
644	int rc;
645	if (ASMHasCpuId())
646	{
647	/* Standard features. */
648	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
649	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
650	if (ASMIsValidStdRange(uMaxLeaf))
651	{
652	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
653	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
654
655	/* Query AMD features. */
656	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
657	if (ASMIsValidExtRange(uMaxExtLeaf))
658	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
659	&g_HvmR0.cpuid.u32AMDFeatureECX,
660	&g_HvmR0.cpuid.u32AMDFeatureEDX);
661	else
662	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
663
664	/* Go to CPU specific initialization code. */
665	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
666	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
667	{
668	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
669	if (RT_FAILURE(rc))
670	return rc;
671	}
672	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
673	{
674	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
675	if (RT_FAILURE(rc))
676	return rc;
677	}
678	else
679	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
680	}
681	else
682	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
683	}
684	else
685	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
686
687	/*
688	* Register notification callbacks that we can use to disable/enable CPUs
689	* when brought offline/online or suspending/resuming.
690	*/
691	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
692	{
693	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
694	AssertRC(rc);
695
696	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
697	AssertRC(rc);
698	}
699
700	/* We return success here because module init shall not fail if HM
701	fails to initialize. */
702	return VINF_SUCCESS;
703	}
704
705
706	/**
707	* Does global Ring-0 HM termination (at module termination).
708	*
709	* @returns VBox status code.
710	*/
711	VMMR0_INT_DECL(int) HMR0Term(void)
712	{
713	int rc;
714	if ( g_HvmR0.vmx.fSupported
715	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
716	{
717	/*
718	* Simple if the host OS manages VT-x.
719	*/
720	Assert(g_HvmR0.fGlobalInit);
721	rc = SUPR0EnableVTx(false /* fEnable */);
722
723	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
724	{
725	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
726	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
727	}
728	}
729	else
730	{
731	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
732	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
733	{
734	/* Doesn't really matter if this fails. */
735	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
736	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
737	}
738	else
739	rc = VINF_SUCCESS;
740
741	/*
742	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
743	*/
744	if (g_HvmR0.fGlobalInit)
745	{
746	HMR0FIRSTRC FirstRc;
747	hmR0FirstRcInit(&FirstRc);
748	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
749	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
750	if (RT_SUCCESS(rc))
751	{
752	rc = hmR0FirstRcGetStatus(&FirstRc);
753	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
754	}
755	}
756
757	/*
758	* Free the per-cpu pages used for VT-x and AMD-V.
759	*/
760	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
761	{
762	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
763	{
764	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
765	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
766	}
767	}
768	}
769
770	/** @todo This needs cleaning up. There's no matching
771	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
772	* should move into their respective modules. */
773	/* Finally, call global VT-x/AMD-V termination. */
774	if (g_HvmR0.vmx.fSupported)
775	VMXR0GlobalTerm();
776	else if (g_HvmR0.svm.fSupported)
777	SVMR0GlobalTerm();
778
779	return rc;
780	}
781
782
783	/**
784	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
785	* on a CPU.
786	*
787	* @param idCpu The identifier for the CPU the function is called on.
788	* @param pvUser1 Pointer to the first RC structure.
789	* @param pvUser2 Ignored.
790	*/
791	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
792	{
793	/** @todo Unify code with SUPR0QueryVTCaps(). */
794	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
795	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
796	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
797	NOREF(idCpu); NOREF(pvUser2);
798
799	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
800	bool const fInSmxMode = RT_BOOL(ASMGetCR4() & X86_CR4_SMXE);
801	bool fMsrLocked = RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_LOCK);
802	bool fSmxVmxAllowed = RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
803	bool fVmxAllowed = RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_VMXON);
804
805	/* Check if the LOCK bit is set but excludes the required VMXON bit. */
806	int rc = VERR_HM_IPE_1;
807	if (fMsrLocked)
808	{
809	if (fInSmxMode && !fSmxVmxAllowed)
810	rc = VERR_VMX_MSR_SMX_VMXON_DISABLED;
811	else if (!fVmxAllowed)
812	rc = VERR_VMX_MSR_VMXON_DISABLED;
813	else
814	rc = VINF_SUCCESS;
815	}
816	else
817	{
818	/*
819	* MSR is not yet locked; we can change it ourselves here.
820	* Once the lock bit is set, this MSR can no longer be modified.
821	*/
822	fFC \|= MSR_IA32_FEATURE_CONTROL_LOCK;
823	if (fInSmxMode)
824	fFC \|= MSR_IA32_FEATURE_CONTROL_SMX_VMXON;
825	else
826	fFC \|= MSR_IA32_FEATURE_CONTROL_VMXON;
827
828	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, fFC);
829
830	/* Verify. */
831	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
832	fMsrLocked = RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_LOCK);
833	fSmxVmxAllowed = fMsrLocked && RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
834	fVmxAllowed = fMsrLocked && RT_BOOL(fFC & MSR_IA32_FEATURE_CONTROL_VMXON);
835	bool const fAllowed = fInSmxMode ? fSmxVmxAllowed : fVmxAllowed;
836	if (fAllowed)
837	rc = VINF_SUCCESS;
838	else
839	rc = VERR_VMX_MSR_LOCKING_FAILED;
840	}
841
842	hmR0FirstRcSetStatus(pFirstRc, rc);
843	}
844
845
846	/**
847	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
848	* on a CPU.
849	*
850	* @param idCpu The identifier for the CPU the function is called on.
851	* @param pvUser1 Pointer to the first RC structure.
852	* @param pvUser2 Ignored.
853	*/
854	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
855	{
856	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
857	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
858	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
859	NOREF(idCpu); NOREF(pvUser2);
860
861	/* Check if SVM is disabled. */
862	int rc;
863	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
864	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
865	{
866	/* Turn on SVM in the EFER MSR. */
867	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
868	if (fEfer & MSR_K6_EFER_SVME)
869	rc = VERR_SVM_IN_USE;
870	else
871	{
872	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
873
874	/* Paranoia. */
875	fEfer = ASMRdMsr(MSR_K6_EFER);
876	if (fEfer & MSR_K6_EFER_SVME)
877	{
878	/* Restore previous value. */
879	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
880	rc = VINF_SUCCESS;
881	}
882	else
883	rc = VERR_SVM_ILLEGAL_EFER_MSR;
884	}
885	}
886	else
887	rc = VERR_SVM_DISABLED;
888
889	hmR0FirstRcSetStatus(pFirstRc, rc);
890	}
891
892
893	/**
894	* Enable VT-x or AMD-V on the current CPU
895	*
896	* @returns VBox status code.
897	* @param pVM Pointer to the VM (can be NULL).
898	* @param idCpu The identifier for the CPU the function is called on.
899	*
900	* @remarks Maybe called with interrupts disabled!
901	*/
902	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
903	{
904	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
905
906	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
907	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
908	Assert(!pCpu->fConfigured);
909
910	pCpu->idCpu = idCpu;
911	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
912
913	int rc;
914	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
915	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HvmR0.vmx.Msrs);
916	else
917	{
918	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
919	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
920	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
921
922	if (g_HvmR0.vmx.fSupported)
923	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
924	else
925	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
926	}
927	AssertRC(rc);
928	if (RT_SUCCESS(rc))
929	pCpu->fConfigured = true;
930
931	return rc;
932	}
933
934
935	/**
936	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
937	*
938	* @param idCpu The identifier for the CPU the function is called on.
939	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
940	* @param pvUser2 The 2nd user argument.
941	*/
942	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
943	{
944	PVM pVM = (PVM)pvUser1; /* can be NULL! */
945	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
946	AssertReturnVoid(g_HvmR0.fGlobalInit);
947	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
948	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
949	}
950
951
952	/**
953	* RTOnce callback employed by HMR0EnableAllCpus.
954	*
955	* @returns VBox status code.
956	* @param pvUser Pointer to the VM.
957	* @param pvUserIgnore NULL, ignored.
958	*/
959	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
960	{
961	PVM pVM = (PVM)pvUser;
962
963	/*
964	* Indicate that we've initialized.
965	*
966	* Note! There is a potential race between this function and the suspend
967	* notification. Kind of unlikely though, so ignored for now.
968	*/
969	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
970	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
971
972	/*
973	* The global init variable is set by the first VM.
974	*/
975	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
976
977	#ifdef VBOX_STRICT
978	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
979	{
980	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
981	Assert(!g_HvmR0.aCpuInfo[i].fConfigured);
982	Assert(!g_HvmR0.aCpuInfo[i].cTlbFlushes);
983	Assert(!g_HvmR0.aCpuInfo[i].uCurrentAsid);
984	}
985	#endif
986
987	int rc;
988	if ( g_HvmR0.vmx.fSupported
989	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
990	{
991	/*
992	* Global VT-x initialization API (only darwin for now).
993	*/
994	rc = SUPR0EnableVTx(true /* fEnable */);
995	if (RT_SUCCESS(rc))
996	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
997	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
998	else
999	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
1000	}
1001	else
1002	{
1003	/*
1004	* We're doing the job ourselves.
1005	*/
1006	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
1007	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1008	{
1009	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1010
1011	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1012	{
1013	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1014	AssertLogRelRCReturn(rc, rc);
1015
1016	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1017	ASMMemZeroPage(pvR0);
1018	}
1019	}
1020
1021	rc = VINF_SUCCESS;
1022	}
1023
1024	if ( RT_SUCCESS(rc)
1025	&& g_HvmR0.fGlobalInit)
1026	{
1027	/* First time, so initialize each cpu/core. */
1028	HMR0FIRSTRC FirstRc;
1029	hmR0FirstRcInit(&FirstRc);
1030	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1031	if (RT_SUCCESS(rc))
1032	rc = hmR0FirstRcGetStatus(&FirstRc);
1033	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1034	}
1035
1036	return rc;
1037	}
1038
1039
1040	/**
1041	* Sets up HM on all cpus.
1042	*
1043	* @returns VBox status code.
1044	* @param pVM Pointer to the VM.
1045	*/
1046	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1047	{
1048	/* Make sure we don't touch HM after we've disabled HM in
1049	preparation of a suspend. */
1050	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1051	return VERR_HM_SUSPEND_PENDING;
1052
1053	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1054	}
1055
1056
1057	/**
1058	* Disable VT-x or AMD-V on the current CPU.
1059	*
1060	* @returns VBox status code.
1061	* @param idCpu The identifier for the CPU the function is called on.
1062	*
1063	* @remarks Must be called with preemption disabled.
1064	*/
1065	static int hmR0DisableCpu(RTCPUID idCpu)
1066	{
1067	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1068
1069	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1070	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1071	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1072	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1073	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1074
1075	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1076	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1077
1078	int rc;
1079	if (pCpu->fConfigured)
1080	{
1081	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1082	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1083
1084	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1085	AssertRCReturn(rc, rc);
1086
1087	pCpu->fConfigured = false;
1088	}
1089	else
1090	rc = VINF_SUCCESS; /* nothing to do */
1091
1092	return rc;
1093	}
1094
1095
1096	/**
1097	* Worker function passed to RTMpOnAll() that is to be called on the target
1098	* CPUs.
1099	*
1100	* @param idCpu The identifier for the CPU the function is called on.
1101	* @param pvUser1 The 1st user argument.
1102	* @param pvUser2 Opaque pointer to the FirstRc.
1103	*/
1104	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1105	{
1106	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1107	AssertReturnVoid(g_HvmR0.fGlobalInit);
1108	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1109	}
1110
1111
1112	/**
1113	* Callback function invoked when a cpu goes online or offline.
1114	*
1115	* @param enmEvent The Mp event.
1116	* @param idCpu The identifier for the CPU the function is called on.
1117	* @param pvData Opaque data (PVM pointer).
1118	*/
1119	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1120	{
1121	NOREF(pvData);
1122
1123	/*
1124	* We only care about uninitializing a CPU that is going offline. When a
1125	* CPU comes online, the initialization is done lazily in HMR0Enter().
1126	*/
1127	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1128	switch (enmEvent)
1129	{
1130	case RTMPEVENT_OFFLINE:
1131	{
1132	int rc = hmR0DisableCpu(idCpu);
1133	AssertRC(rc);
1134	break;
1135	}
1136
1137	default:
1138	break;
1139	}
1140	}
1141
1142
1143	/**
1144	* Called whenever a system power state change occurs.
1145	*
1146	* @param enmEvent The Power event.
1147	* @param pvUser User argument.
1148	*/
1149	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1150	{
1151	NOREF(pvUser);
1152	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1153
1154	#ifdef LOG_ENABLED
1155	if (enmEvent == RTPOWEREVENT_SUSPEND)
1156	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1157	else
1158	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1159	#endif
1160
1161	if (enmEvent == RTPOWEREVENT_SUSPEND)
1162	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1163
1164	if (g_HvmR0.fEnabled)
1165	{
1166	int rc;
1167	HMR0FIRSTRC FirstRc;
1168	hmR0FirstRcInit(&FirstRc);
1169
1170	if (enmEvent == RTPOWEREVENT_SUSPEND)
1171	{
1172	if (g_HvmR0.fGlobalInit)
1173	{
1174	/* Turn off VT-x or AMD-V on all CPUs. */
1175	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1176	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1177	}
1178	/* else nothing to do here for the local init case */
1179	}
1180	else
1181	{
1182	/* Reinit the CPUs from scratch as the suspend state might have
1183	messed with the MSRs. (lousy BIOSes as usual) */
1184	if (g_HvmR0.vmx.fSupported)
1185	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1186	else
1187	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1188	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1189	if (RT_SUCCESS(rc))
1190	rc = hmR0FirstRcGetStatus(&FirstRc);
1191	#ifdef LOG_ENABLED
1192	if (RT_FAILURE(rc))
1193	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1194	#endif
1195	if (g_HvmR0.fGlobalInit)
1196	{
1197	/* Turn VT-x or AMD-V back on on all CPUs. */
1198	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1199	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1200	}
1201	/* else nothing to do here for the local init case */
1202	}
1203	}
1204
1205	if (enmEvent == RTPOWEREVENT_RESUME)
1206	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1207	}
1208
1209
1210	/**
1211	* Does Ring-0 per VM HM initialization.
1212	*
1213	* This will copy HM global into the VM structure and call the CPU specific
1214	* init routine which will allocate resources for each virtual CPU and such.
1215	*
1216	* @returns VBox status code.
1217	* @param pVM Pointer to the VM.
1218	*/
1219	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1220	{
1221	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1222
1223	#ifdef LOG_ENABLED
1224	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1225	#endif
1226
1227	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1228	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1229	return VERR_HM_SUSPEND_PENDING;
1230
1231	/*
1232	* Copy globals to the VM structure.
1233	*/
1234	/** @todo r=ramshankar: Why do we do this for MSRs? We never change them in the
1235	* per-VM structures anyway... */
1236	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1237	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1238
1239	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1240	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1241	pVM->hm.s.vmx.u64HostCr4 = g_HvmR0.vmx.u64HostCr4;
1242	pVM->hm.s.vmx.u64HostEfer = g_HvmR0.vmx.u64HostEfer;
1243	pVM->hm.s.vmx.Msrs = g_HvmR0.vmx.Msrs;
1244	pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr;
1245	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1246	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1247	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1248	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1249	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1250
1251	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1252
1253
1254	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1255	{
1256	pVM->hm.s.cMaxResumeLoops = 1024;
1257	if (RTThreadPreemptIsPendingTrusty())
1258	pVM->hm.s.cMaxResumeLoops = 8192;
1259	}
1260
1261	/*
1262	* Initialize some per CPU fields.
1263	*/
1264	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1265	{
1266	PVMCPU pVCpu = &pVM->aCpus[i];
1267
1268	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1269
1270	/* Invalidate the last cpu we were running on. */
1271	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1272
1273	/* We'll aways increment this the first time (host uses ASID 0) */
1274	pVCpu->hm.s.uCurrentAsid = 0;
1275	}
1276
1277	/*
1278	* Call the hardware specific initialization method.
1279	*/
1280	return g_HvmR0.pfnInitVM(pVM);
1281	}
1282
1283
1284	/**
1285	* Does Ring-0 per VM HM termination.
1286	*
1287	* @returns VBox status code.
1288	* @param pVM Pointer to the VM.
1289	*/
1290	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1291	{
1292	Log(("HMR0TermVM: %p\n", pVM));
1293	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1294
1295	/*
1296	* Call the hardware specific method.
1297	*
1298	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1299	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1300	*/
1301	return g_HvmR0.pfnTermVM(pVM);
1302	}
1303
1304
1305	/**
1306	* Sets up a VT-x or AMD-V session.
1307	*
1308	* This is mostly about setting up the hardware VM state.
1309	*
1310	* @returns VBox status code.
1311	* @param pVM Pointer to the VM.
1312	*/
1313	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1314	{
1315	Log(("HMR0SetupVM: %p\n", pVM));
1316	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1317
1318	/* Make sure we don't touch HM after we've disabled HM in
1319	preparation of a suspend. */
1320	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1321
1322	/* On first entry we'll sync everything. */
1323	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1324	HMCPU_CF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1325
1326	/*
1327	* Call the hardware specific setup VM method. This requires the CPU to be
1328	* enabled for AMD-V/VT-x and preemption to be prevented.
1329	*/
1330	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1331	RTThreadPreemptDisable(&PreemptState);
1332	RTCPUID idCpu = RTMpCpuId();
1333
1334	/* Enable VT-x or AMD-V if local init is required. */
1335	int rc;
1336	if (!g_HvmR0.fGlobalInit)
1337	{
1338	rc = hmR0EnableCpu(pVM, idCpu);
1339	AssertRCReturnStmt(rc, RTThreadPreemptRestore(&PreemptState), rc);
1340	}
1341
1342	/* Setup VT-x or AMD-V. */
1343	rc = g_HvmR0.pfnSetupVM(pVM);
1344
1345	/* Disable VT-x or AMD-V if local init was done before. */
1346	if (!g_HvmR0.fGlobalInit)
1347	{
1348	int rc2 = hmR0DisableCpu(idCpu);
1349	AssertRC(rc2);
1350	}
1351
1352	RTThreadPreemptRestore(&PreemptState);
1353	return rc;
1354	}
1355
1356
1357	/**
1358	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1359	* required for entering HM context.
1360	*
1361	* @returns VBox status code.
1362	* @param pvCpu Pointer to the VMCPU.
1363	*
1364	* @remarks No-long-jump zone!!!
1365	*/
1366	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1367	{
1368	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1369
1370	int rc = VINF_SUCCESS;
1371	RTCPUID idCpu = RTMpCpuId();
1372	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1373	AssertPtr(pCpu);
1374
1375	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1376	if (!pCpu->fConfigured)
1377	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1378
1379	/* Reload host-context (back from ring-3/migrated CPUs), reload host context & shared bits. */
1380	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE);
1381	pVCpu->hm.s.idEnteredCpu = idCpu;
1382	return rc;
1383	}
1384
1385
1386	/**
1387	* Enters the VT-x or AMD-V session.
1388	*
1389	* @returns VBox status code.
1390	* @param pVM Pointer to the VM.
1391	* @param pVCpu Pointer to the VMCPU.
1392	*
1393	* @remarks This is called with preemption disabled.
1394	*/
1395	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1396	{
1397	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1398	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1399	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1400
1401	/* Load the bare minimum state required for entering HM. */
1402	int rc = HMR0EnterCpu(pVCpu);
1403	AssertRCReturn(rc, rc);
1404
1405	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1406	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1407	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1408	#endif
1409
1410	RTCPUID idCpu = RTMpCpuId();
1411	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1412	Assert(pCpu);
1413	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1414
1415	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1416	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1417
1418	/* Load the host as we may be resuming code after a longjmp and quite
1419	possibly now be scheduled on a different CPU. */
1420	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1421	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1422
1423	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1424	if (fStartedSet)
1425	PGMRZDynMapReleaseAutoSet(pVCpu);
1426	#endif
1427
1428	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1429	and ring-3 calls. */
1430	if (RT_FAILURE(rc))
1431	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1432	return rc;
1433	}
1434
1435
1436	/**
1437	* Deinitializes the bare minimum state used for HM context and if necessary
1438	* disable HM on the CPU.
1439	*
1440	* @returns VBox status code.
1441	* @param pVCpu Pointer to the VMCPU.
1442	*
1443	* @remarks No-long-jump zone!!!
1444	*/
1445	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1446	{
1447	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1448	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU_1);
1449
1450	RTCPUID idCpu = RTMpCpuId();
1451	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1452
1453	if ( !g_HvmR0.fGlobalInit
1454	&& pCpu->fConfigured)
1455	{
1456	int rc = hmR0DisableCpu(idCpu);
1457	AssertRCReturn(rc, rc);
1458	Assert(!pCpu->fConfigured);
1459	}
1460
1461	/* Reset these to force a TLB flush for the next entry. */
1462	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1463	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1464	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1465
1466	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1467	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1468
1469	return VINF_SUCCESS;
1470	}
1471
1472
1473	/**
1474	* Thread-context hook for HM.
1475	*
1476	* @param enmEvent The thread-context event.
1477	* @param pvUser Opaque pointer to the VMCPU.
1478	*/
1479	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1480	{
1481	PVMCPU pVCpu = (PVMCPU)pvUser;
1482	Assert(pVCpu);
1483	Assert(g_HvmR0.pfnThreadCtxCallback);
1484
1485	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1486	}
1487
1488
1489	/**
1490	* Runs guest code in a hardware accelerated VM.
1491	*
1492	* @returns VBox status code.
1493	* @param pVM Pointer to the VM.
1494	* @param pVCpu Pointer to the VMCPU.
1495	*
1496	* @remarks Can be called with preemption enabled if thread-context hooks are
1497	* used!!!
1498	*/
1499	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1500	{
1501	#ifdef VBOX_STRICT
1502	/* With thread-context hooks we would be running this code with preemption enabled. */
1503	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1504	{
1505	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1506	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1507	Assert(pCpu->fConfigured);
1508	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1509	}
1510	#endif
1511
1512	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1513	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1514	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1515	PGMRZDynMapStartAutoSet(pVCpu);
1516	#endif
1517
1518	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1519
1520	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1521	PGMRZDynMapReleaseAutoSet(pVCpu);
1522	#endif
1523	return rc;
1524	}
1525
1526	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1527
1528	/**
1529	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1530	*
1531	* @returns VBox status code.
1532	* @param pVM Pointer to the VM.
1533	* @param pVCpu Pointer to the VMCPU.
1534	* @param pCtx Pointer to the guest CPU context.
1535	*/
1536	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1537	{
1538	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1539	if (pVM->hm.s.vmx.fSupported)
1540	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1541	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1542	}
1543
1544
1545	/**
1546	* Save guest debug state (64 bits guest mode & 32 bits host only)
1547	*
1548	* @returns VBox status code.
1549	* @param pVM Pointer to the VM.
1550	* @param pVCpu Pointer to the VMCPU.
1551	* @param pCtx Pointer to the guest CPU context.
1552	*/
1553	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1554	{
1555	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1556	if (pVM->hm.s.vmx.fSupported)
1557	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1558	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1559	}
1560
1561
1562	/**
1563	* Test the 32->64 bits switcher.
1564	*
1565	* @returns VBox status code.
1566	* @param pVM Pointer to the VM.
1567	*/
1568	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1569	{
1570	PVMCPU pVCpu = &pVM->aCpus[0];
1571	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1572	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1573	int rc;
1574
1575	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1576	if (pVM->hm.s.vmx.fSupported)
1577	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1578	else
1579	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1580	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1581
1582	return rc;
1583	}
1584
1585	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1586
1587	/**
1588	* Returns suspend status of the host.
1589	*
1590	* @returns Suspend pending or not.
1591	*/
1592	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1593	{
1594	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1595	}
1596
1597
1598	/**
1599	* Returns the cpu structure for the current cpu.
1600	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1601	*
1602	* @returns The cpu structure pointer.
1603	*/
1604	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1605	{
1606	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1607	RTCPUID idCpu = RTMpCpuId();
1608	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1609	return &g_HvmR0.aCpuInfo[idCpu];
1610	}
1611
1612
1613	/**
1614	* Returns the cpu structure for the current cpu.
1615	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1616	*
1617	* @returns The cpu structure pointer.
1618	* @param idCpu id of the VCPU.
1619	*/
1620	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1621	{
1622	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1623	return &g_HvmR0.aCpuInfo[idCpu];
1624	}
1625
1626
1627	/**
1628	* Save a pending IO read.
1629	*
1630	* @param pVCpu Pointer to the VMCPU.
1631	* @param GCPtrRip Address of IO instruction.
1632	* @param GCPtrRipNext Address of the next instruction.
1633	* @param uPort Port address.
1634	* @param uAndVal AND mask for saving the result in eax.
1635	* @param cbSize Read size.
1636	*/
1637	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1638	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1639	{
1640	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1641	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1642	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1643	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1644	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1645	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1646	return;
1647	}
1648
1649
1650	/**
1651	* Save a pending IO write.
1652	*
1653	* @param pVCpu Pointer to the VMCPU.
1654	* @param GCPtrRIP Address of IO instruction.
1655	* @param uPort Port address.
1656	* @param uAndVal AND mask for fetching the result from eax.
1657	* @param cbSize Read size.
1658	*/
1659	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1660	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1661	{
1662	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1663	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1664	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1665	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1666	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1667	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1668	return;
1669	}
1670
1671
1672	/**
1673	* Raw-mode switcher hook - disable VT-x if it's active and the current
1674	* switcher turns off paging.
1675	*
1676	* @returns VBox status code.
1677	* @param pVM Pointer to the VM.
1678	* @param enmSwitcher The switcher we're about to use.
1679	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1680	*/
1681	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1682	{
1683	NOREF(pVM);
1684
1685	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1686
1687	*pfVTxDisabled = false;
1688
1689	/* No such issues with AMD-V */
1690	if (!g_HvmR0.vmx.fSupported)
1691	return VINF_SUCCESS;
1692
1693	/* Check if the swithcing we're up to is safe. */
1694	switch (enmSwitcher)
1695	{
1696	case VMMSWITCHER_32_TO_32:
1697	case VMMSWITCHER_PAE_TO_PAE:
1698	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1699
1700	case VMMSWITCHER_32_TO_PAE:
1701	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1702	case VMMSWITCHER_AMD64_TO_32:
1703	case VMMSWITCHER_AMD64_TO_PAE:
1704	break; /* unsafe switchers */
1705
1706	default:
1707	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1708	}
1709
1710	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1711	regardless of whether we're currently using VT-x or not. */
1712	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1713	{
1714	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1715	return VINF_SUCCESS;
1716	}
1717
1718	/** @todo Check if this code is presumtive wrt other VT-x users on the
1719	* system... */
1720
1721	/* Nothing to do if we haven't enabled VT-x. */
1722	if (!g_HvmR0.fEnabled)
1723	return VINF_SUCCESS;
1724
1725	/* Local init implies the CPU is currently not in VMX root mode. */
1726	if (!g_HvmR0.fGlobalInit)
1727	return VINF_SUCCESS;
1728
1729	/* Ok, disable VT-x. */
1730	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1731	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1732
1733	*pfVTxDisabled = true;
1734	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1735	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1736	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1737	}
1738
1739
1740	/**
1741	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1742	* switcher turned off paging.
1743	*
1744	* @param pVM Pointer to the VM.
1745	* @param fVTxDisabled Whether VT-x was disabled or not.
1746	*/
1747	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1748	{
1749	Assert(!(ASMGetFlags() & X86_EFL_IF));
1750
1751	if (!fVTxDisabled)
1752	return; /* nothing to do */
1753
1754	Assert(g_HvmR0.vmx.fSupported);
1755	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1756	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1757	else
1758	{
1759	Assert(g_HvmR0.fEnabled);
1760	Assert(g_HvmR0.fGlobalInit);
1761
1762	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1763	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1764
1765	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1766	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1767	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
1768	}
1769	}
1770
1771	#ifdef VBOX_STRICT
1772
1773	/**
1774	* Dumps a descriptor.
1775	*
1776	* @param pDesc Descriptor to dump.
1777	* @param Sel Selector number.
1778	* @param pszMsg Message to prepend the log entry with.
1779	*/
1780	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1781	{
1782	/*
1783	* Make variable description string.
1784	*/
1785	static struct
1786	{
1787	unsigned cch;
1788	const char *psz;
1789	} const s_aTypes[32] =
1790	{
1791	# define STRENTRY(str) { sizeof(str) - 1, str }
1792
1793	/* system */
1794	# if HC_ARCH_BITS == 64
1795	STRENTRY("Reserved0 "), /* 0x00 */
1796	STRENTRY("Reserved1 "), /* 0x01 */
1797	STRENTRY("LDT "), /* 0x02 */
1798	STRENTRY("Reserved3 "), /* 0x03 */
1799	STRENTRY("Reserved4 "), /* 0x04 */
1800	STRENTRY("Reserved5 "), /* 0x05 */
1801	STRENTRY("Reserved6 "), /* 0x06 */
1802	STRENTRY("Reserved7 "), /* 0x07 */
1803	STRENTRY("Reserved8 "), /* 0x08 */
1804	STRENTRY("TSS64Avail "), /* 0x09 */
1805	STRENTRY("ReservedA "), /* 0x0a */
1806	STRENTRY("TSS64Busy "), /* 0x0b */
1807	STRENTRY("Call64 "), /* 0x0c */
1808	STRENTRY("ReservedD "), /* 0x0d */
1809	STRENTRY("Int64 "), /* 0x0e */
1810	STRENTRY("Trap64 "), /* 0x0f */
1811	# else
1812	STRENTRY("Reserved0 "), /* 0x00 */
1813	STRENTRY("TSS16Avail "), /* 0x01 */
1814	STRENTRY("LDT "), /* 0x02 */
1815	STRENTRY("TSS16Busy "), /* 0x03 */
1816	STRENTRY("Call16 "), /* 0x04 */
1817	STRENTRY("Task "), /* 0x05 */
1818	STRENTRY("Int16 "), /* 0x06 */
1819	STRENTRY("Trap16 "), /* 0x07 */
1820	STRENTRY("Reserved8 "), /* 0x08 */
1821	STRENTRY("TSS32Avail "), /* 0x09 */
1822	STRENTRY("ReservedA "), /* 0x0a */
1823	STRENTRY("TSS32Busy "), /* 0x0b */
1824	STRENTRY("Call32 "), /* 0x0c */
1825	STRENTRY("ReservedD "), /* 0x0d */
1826	STRENTRY("Int32 "), /* 0x0e */
1827	STRENTRY("Trap32 "), /* 0x0f */
1828	# endif
1829	/* non system */
1830	STRENTRY("DataRO "), /* 0x10 */
1831	STRENTRY("DataRO Accessed "), /* 0x11 */
1832	STRENTRY("DataRW "), /* 0x12 */
1833	STRENTRY("DataRW Accessed "), /* 0x13 */
1834	STRENTRY("DataDownRO "), /* 0x14 */
1835	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1836	STRENTRY("DataDownRW "), /* 0x16 */
1837	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1838	STRENTRY("CodeEO "), /* 0x18 */
1839	STRENTRY("CodeEO Accessed "), /* 0x19 */
1840	STRENTRY("CodeER "), /* 0x1a */
1841	STRENTRY("CodeER Accessed "), /* 0x1b */
1842	STRENTRY("CodeConfEO "), /* 0x1c */
1843	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1844	STRENTRY("CodeConfER "), /* 0x1e */
1845	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1846	# undef SYSENTRY
1847	};
1848	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1849	char szMsg[128];
1850	char *psz = &szMsg[0];
1851	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1852	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1853	psz += s_aTypes[i].cch;
1854
1855	if (pDesc->Gen.u1Present)
1856	ADD_STR(psz, "Present ");
1857	else
1858	ADD_STR(psz, "Not-Present ");
1859	# if HC_ARCH_BITS == 64
1860	if (pDesc->Gen.u1Long)
1861	ADD_STR(psz, "64-bit ");
1862	else
1863	ADD_STR(psz, "Comp ");
1864	# else
1865	if (pDesc->Gen.u1Granularity)
1866	ADD_STR(psz, "Page ");
1867	if (pDesc->Gen.u1DefBig)
1868	ADD_STR(psz, "32-bit ");
1869	else
1870	ADD_STR(psz, "16-bit ");
1871	# endif
1872	# undef ADD_STR
1873	*psz = '\0';
1874
1875	/*
1876	* Limit and Base and format the output.
1877	*/
1878	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1879
1880	# if HC_ARCH_BITS == 64
1881	uint64_t u32Base = X86DESC64_BASE(pDesc);
1882
1883	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1884	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1885	# else
1886	uint32_t u32Base = X86DESC_BASE(pDesc);
1887
1888	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1889	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1890	# endif
1891	}
1892
1893
1894	/**
1895	* Formats a full register dump.
1896	*
1897	* @param pVM Pointer to the VM.
1898	* @param pVCpu Pointer to the VMCPU.
1899	* @param pCtx Pointer to the CPU context.
1900	*/
1901	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1902	{
1903	NOREF(pVM);
1904
1905	/*
1906	* Format the flags.
1907	*/
1908	static struct
1909	{
1910	const char pszSet; const char pszClear; uint32_t fFlag;
1911	} const s_aFlags[] =
1912	{
1913	{ "vip",NULL, X86_EFL_VIP },
1914	{ "vif",NULL, X86_EFL_VIF },
1915	{ "ac", NULL, X86_EFL_AC },
1916	{ "vm", NULL, X86_EFL_VM },
1917	{ "rf", NULL, X86_EFL_RF },
1918	{ "nt", NULL, X86_EFL_NT },
1919	{ "ov", "nv", X86_EFL_OF },
1920	{ "dn", "up", X86_EFL_DF },
1921	{ "ei", "di", X86_EFL_IF },
1922	{ "tf", NULL, X86_EFL_TF },
1923	{ "nt", "pl", X86_EFL_SF },
1924	{ "nz", "zr", X86_EFL_ZF },
1925	{ "ac", "na", X86_EFL_AF },
1926	{ "po", "pe", X86_EFL_PF },
1927	{ "cy", "nc", X86_EFL_CF },
1928	};
1929	char szEFlags[80];
1930	char *psz = szEFlags;
1931	uint32_t efl = pCtx->eflags.u32;
1932	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1933	{
1934	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1935	if (pszAdd)
1936	{
1937	strcpy(psz, pszAdd);
1938	psz += strlen(pszAdd);
1939	*psz++ = ' ';
1940	}
1941	}
1942	psz[-1] = '\0';
1943
1944
1945	/*
1946	* Format the registers.
1947	*/
1948	if (CPUMIsGuestIn64BitCode(pVCpu))
1949	{
1950	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1951	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1952	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1953	"r14=%016RX64 r15=%016RX64\n"
1954	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1955	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1956	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1957	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1958	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1959	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1960	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1961	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1962	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1963	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1964	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1965	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1966	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1967	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1968	,
1969	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1970	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1971	pCtx->r14, pCtx->r15,
1972	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1973	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1974	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1975	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1976	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1977	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1978	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1979	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1980	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1981	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1982	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1983	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1984	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1985	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1986	}
1987	else
1988	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1989	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1990	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1991	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1992	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1993	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1994	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1995	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1996	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1997	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1998	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1999	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2000	,
2001	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2002	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2003	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2004	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2005	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2006	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2007	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2008	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2009	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2010	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2011	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2012	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2013
2014	Log(("FPU:\n"
2015	"FCW=%04x FSW=%04x FTW=%02x\n"
2016	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2017	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2018	,
2019	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2020	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2021	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2022	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2023
2024
2025	Log(("MSR:\n"
2026	"EFER =%016RX64\n"
2027	"PAT =%016RX64\n"
2028	"STAR =%016RX64\n"
2029	"CSTAR =%016RX64\n"
2030	"LSTAR =%016RX64\n"
2031	"SFMASK =%016RX64\n"
2032	"KERNELGSBASE =%016RX64\n",
2033	pCtx->msrEFER,
2034	pCtx->msrPAT,
2035	pCtx->msrSTAR,
2036	pCtx->msrCSTAR,
2037	pCtx->msrLSTAR,
2038	pCtx->msrSFMASK,
2039	pCtx->msrKERNELGSBASE));
2040
2041	}
2042
2043	#endif /* VBOX_STRICT */
2044

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 49966

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