HMSVMR0.cpp@ 55435

Last change on this file since 55435 was 55316, checked in by vboxsync, 10 years ago
CPUM,IEM,HM: Enabled XSAVE and AVX for AMD-V too.
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1	/* $Id: HMSVMR0.cpp 55316 2015-04-16 17:34:30Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <iprt/asm-amd64-x86.h>
23	#include <iprt/thread.h>
24
25	#include <VBox/vmm/pdmapi.h>
26	#include <VBox/vmm/dbgf.h>
27	#include <VBox/vmm/iem.h>
28	#include <VBox/vmm/iom.h>
29	#include <VBox/vmm/tm.h>
30	#include <VBox/vmm/gim.h>
31	#include "HMInternal.h"
32	#include <VBox/vmm/vm.h>
33	#include "HMSVMR0.h"
34	#include "dtrace/VBoxVMM.h"
35
36	#ifdef DEBUG_ramshankar
37	# define HMSVM_SYNC_FULL_GUEST_STATE
38	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
39	# define HMSVM_ALWAYS_TRAP_PF
40	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
41	#endif
42
43
44	/*******************************************************************************
45	* Defined Constants And Macros *
46	*******************************************************************************/
47	#ifdef VBOX_WITH_STATISTICS
48	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
49	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
50	if ((u64ExitCode) == SVM_EXIT_NPF) \
51	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
52	else \
53	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
54	} while (0)
55	#else
56	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
57	#endif
58
59	/** If we decide to use a function table approach this can be useful to
60	* switch to a "static DECLCALLBACK(int)". */
61	#define HMSVM_EXIT_DECL static int
62
63	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
64	*
65	* The CPU format of the segment attribute is described in X86DESCATTRBITS
66	* which is 16-bits (i.e. includes 4 bits of the segment limit).
67	*
68	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
69	* only the attribute bits and nothing else). Upper 4-bits are unused.
70	*
71	* @{ */
72	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0xf000) >> 4) )
73	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0x0f00) << 4) )
74	/** @} */
75
76	/** @name Macros for loading, storing segment registers to/from the VMCB.
77	* @{ */
78	#define HMSVM_LOAD_SEG_REG(REG, reg) \
79	do \
80	{ \
81	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
82	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
83	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
84	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
85	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
86	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
87	} while (0)
88
89	#define HMSVM_SAVE_SEG_REG(REG, reg) \
90	do \
91	{ \
92	pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
93	pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
94	pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
95	pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
96	pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
97	pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
98	} while (0)
99	/** @} */
100
101	/** Macro for checking and returning from the using function for
102	* \#VMEXIT intercepts that maybe caused during delivering of another
103	* event in the guest. */
104	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
105	do \
106	{ \
107	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
108	if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT)) \
109	return VINF_SUCCESS; \
110	else if (RT_UNLIKELY(rc == VINF_EM_RESET)) \
111	return rc; \
112	} while (0)
113
114	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
115	* instruction that exited. */
116	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
117	do { \
118	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
119	(a_rc) = VINF_EM_DBG_STEPPED; \
120	} while (0)
121
122	/** Assert that preemption is disabled or covered by thread-context hooks. */
123	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
124	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
125
126	/** Assert that we haven't migrated CPUs when thread-context hooks are not
127	* used. */
128	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
129	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
130	("Illegal migration! Entered on CPU %u Current %u\n", \
131	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
132
133	/** Exception bitmap mask for all contributory exceptions.
134	*
135	* Page fault is deliberately excluded here as it's conditional as to whether
136	* it's contributory or benign. Page faults are handled separately.
137	*/
138	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
139	\| RT_BIT(X86_XCPT_DE))
140
141	/** @name VMCB Clean Bits.
142	*
143	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
144	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
145	* memory.
146	*
147	* @{ */
148	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
149	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
150	/** I/O permission bitmap, MSR permission bitmap. */
151	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
152	/** ASID. */
153	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
154	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
155	V_INTR_VECTOR. */
156	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
157	/** Nested Paging: Nested CR3 (nCR3), PAT. */
158	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
159	/** Control registers (CR0, CR3, CR4, EFER). */
160	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
161	/** Debug registers (DR6, DR7). */
162	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
163	/** GDT, IDT limit and base. */
164	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
165	/** Segment register: CS, SS, DS, ES limit and base. */
166	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
167	/** CR2.*/
168	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
169	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
170	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
171	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
172	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
173	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
174	/** Mask of all valid VMCB Clean bits. */
175	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
176	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
177	\| HMSVM_VMCB_CLEAN_ASID \
178	\| HMSVM_VMCB_CLEAN_TPR \
179	\| HMSVM_VMCB_CLEAN_NP \
180	\| HMSVM_VMCB_CLEAN_CRX_EFER \
181	\| HMSVM_VMCB_CLEAN_DRX \
182	\| HMSVM_VMCB_CLEAN_DT \
183	\| HMSVM_VMCB_CLEAN_SEG \
184	\| HMSVM_VMCB_CLEAN_CR2 \
185	\| HMSVM_VMCB_CLEAN_LBR \
186	\| HMSVM_VMCB_CLEAN_AVIC)
187	/** @} */
188
189	/** @name SVM transient.
190	*
191	* A state structure for holding miscellaneous information across AMD-V
192	* VMRUN/#VMEXIT operation, restored after the transition.
193	*
194	* @{ */
195	typedef struct SVMTRANSIENT
196	{
197	/** The host's rflags/eflags. */
198	RTCCUINTREG uEflags;
199	#if HC_ARCH_BITS == 32
200	uint32_t u32Alignment0;
201	#endif
202
203	/** The #VMEXIT exit code (the EXITCODE field in the VMCB). */
204	uint64_t u64ExitCode;
205	/** The guest's TPR value used for TPR shadowing. */
206	uint8_t u8GuestTpr;
207	/** Alignment. */
208	uint8_t abAlignment0[7];
209
210	/** Whether the guest FPU state was active at the time of #VMEXIT. */
211	bool fWasGuestFPUStateActive;
212	/** Whether the guest debug state was active at the time of #VMEXIT. */
213	bool fWasGuestDebugStateActive;
214	/** Whether the hyper debug state was active at the time of #VMEXIT. */
215	bool fWasHyperDebugStateActive;
216	/** Whether the TSC offset mode needs to be updated. */
217	bool fUpdateTscOffsetting;
218	/** Whether the TSC_AUX MSR needs restoring on #VMEXIT. */
219	bool fRestoreTscAuxMsr;
220	/** Whether the #VMEXIT was caused by a page-fault during delivery of a
221	* contributary exception or a page-fault. */
222	bool fVectoringDoublePF;
223	/** Whether the #VMEXIT was caused by a page-fault during delivery of an
224	* external interrupt or NMI. */
225	bool fVectoringPF;
226	} SVMTRANSIENT, *PSVMTRANSIENT;
227	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
228	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
229	/** @} */
230
231	/**
232	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
233	*/
234	typedef enum SVMMSREXITREAD
235	{
236	/** Reading this MSR causes a #VMEXIT. */
237	SVMMSREXIT_INTERCEPT_READ = 0xb,
238	/** Reading this MSR does not cause a #VMEXIT. */
239	SVMMSREXIT_PASSTHRU_READ
240	} SVMMSREXITREAD;
241
242	/**
243	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
244	*/
245	typedef enum SVMMSREXITWRITE
246	{
247	/** Writing to this MSR causes a #VMEXIT. */
248	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
249	/** Writing to this MSR does not cause a #VMEXIT. */
250	SVMMSREXIT_PASSTHRU_WRITE
251	} SVMMSREXITWRITE;
252
253	/**
254	* SVM #VMEXIT handler.
255	*
256	* @returns VBox status code.
257	* @param pVCpu Pointer to the VMCPU.
258	* @param pMixedCtx Pointer to the guest-CPU context.
259	* @param pSvmTransient Pointer to the SVM-transient structure.
260	*/
261	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
262
263	/*******************************************************************************
264	* Internal Functions *
265	*******************************************************************************/
266	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
267	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
268	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
269
270	/** @name #VMEXIT handlers.
271	* @{
272	*/
273	static FNSVMEXITHANDLER hmR0SvmExitIntr;
274	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
275	static FNSVMEXITHANDLER hmR0SvmExitInvd;
276	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
277	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
278	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
279	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
280	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
281	static FNSVMEXITHANDLER hmR0SvmExitHlt;
282	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
283	static FNSVMEXITHANDLER hmR0SvmExitMwait;
284	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
285	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
286	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
287	static FNSVMEXITHANDLER hmR0SvmExitSetPendingXcptUD;
288	static FNSVMEXITHANDLER hmR0SvmExitMsr;
289	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
290	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
291	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
292	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
293	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
294	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
295	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
296	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
297	static FNSVMEXITHANDLER hmR0SvmExitIret;
298	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
299	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
300	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
301	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
302	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
303	/** @} */
304
305	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
306
307	/*******************************************************************************
308	* Global Variables *
309	*******************************************************************************/
310	/** Ring-0 memory object for the IO bitmap. */
311	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
312	/** Physical address of the IO bitmap. */
313	RTHCPHYS g_HCPhysIOBitmap = 0;
314	/** Virtual address of the IO bitmap. */
315	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
316
317
318	/**
319	* Sets up and activates AMD-V on the current CPU.
320	*
321	* @returns VBox status code.
322	* @param pCpu Pointer to the CPU info struct.
323	* @param pVM Pointer to the VM (can be NULL after a resume!).
324	* @param pvCpuPage Pointer to the global CPU page.
325	* @param HCPhysCpuPage Physical address of the global CPU page.
326	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
327	* @param pvArg Unused on AMD-V.
328	*/
329	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
330	void *pvArg)
331	{
332	Assert(!fEnabledByHost);
333	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
334	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
335	Assert(pvCpuPage);
336	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
337
338	NOREF(pvArg);
339	NOREF(fEnabledByHost);
340
341	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
342	RTCCUINTREG uEflags = ASMIntDisableFlags();
343
344	/*
345	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
346	*/
347	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
348	if (u64HostEfer & MSR_K6_EFER_SVME)
349	{
350	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
351	if ( pVM
352	&& pVM->hm.s.svm.fIgnoreInUseError)
353	{
354	pCpu->fIgnoreAMDVInUseError = true;
355	}
356
357	if (!pCpu->fIgnoreAMDVInUseError)
358	{
359	ASMSetFlags(uEflags);
360	return VERR_SVM_IN_USE;
361	}
362	}
363
364	/* Turn on AMD-V in the EFER MSR. */
365	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
366
367	/* Write the physical page address where the CPU will store the host state while executing the VM. */
368	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
369
370	/* Restore interrupts. */
371	ASMSetFlags(uEflags);
372
373	/*
374	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
375	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
376	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
377	* to flush the TLB with before using a new ASID.
378	*/
379	pCpu->fFlushAsidBeforeUse = true;
380
381	/*
382	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
383	*/
384	++pCpu->cTlbFlushes;
385
386	return VINF_SUCCESS;
387	}
388
389
390	/**
391	* Deactivates AMD-V on the current CPU.
392	*
393	* @returns VBox status code.
394	* @param pCpu Pointer to the CPU info struct.
395	* @param pvCpuPage Pointer to the global CPU page.
396	* @param HCPhysCpuPage Physical address of the global CPU page.
397	*/
398	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
399	{
400	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
401	AssertReturn( HCPhysCpuPage
402	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
403	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
404	NOREF(pCpu);
405
406	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
407	RTCCUINTREG uEflags = ASMIntDisableFlags();
408
409	/* Turn off AMD-V in the EFER MSR. */
410	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
411	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
412
413	/* Invalidate host state physical address. */
414	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
415
416	/* Restore interrupts. */
417	ASMSetFlags(uEflags);
418
419	return VINF_SUCCESS;
420	}
421
422
423	/**
424	* Does global AMD-V initialization (called during module initialization).
425	*
426	* @returns VBox status code.
427	*/
428	VMMR0DECL(int) SVMR0GlobalInit(void)
429	{
430	/*
431	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
432	* once globally here instead of per-VM.
433	*/
434	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
435	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
436	if (RT_FAILURE(rc))
437	return rc;
438
439	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
440	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
441
442	/* Set all bits to intercept all IO accesses. */
443	ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
444	return VINF_SUCCESS;
445	}
446
447
448	/**
449	* Does global AMD-V termination (called during module termination).
450	*/
451	VMMR0DECL(void) SVMR0GlobalTerm(void)
452	{
453	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
454	{
455	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
456	g_pvIOBitmap = NULL;
457	g_HCPhysIOBitmap = 0;
458	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
459	}
460	}
461
462
463	/**
464	* Frees any allocated per-VCPU structures for a VM.
465	*
466	* @param pVM Pointer to the VM.
467	*/
468	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
469	{
470	for (uint32_t i = 0; i < pVM->cCpus; i++)
471	{
472	PVMCPU pVCpu = &pVM->aCpus[i];
473	AssertPtr(pVCpu);
474
475	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
476	{
477	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
478	pVCpu->hm.s.svm.pvVmcbHost = 0;
479	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
480	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
481	}
482
483	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
484	{
485	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
486	pVCpu->hm.s.svm.pvVmcb = 0;
487	pVCpu->hm.s.svm.HCPhysVmcb = 0;
488	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
489	}
490
491	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
492	{
493	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
494	pVCpu->hm.s.svm.pvMsrBitmap = 0;
495	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
496	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
497	}
498	}
499	}
500
501
502	/**
503	* Does per-VM AMD-V initialization.
504	*
505	* @returns VBox status code.
506	* @param pVM Pointer to the VM.
507	*/
508	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
509	{
510	int rc = VERR_INTERNAL_ERROR_5;
511
512	/*
513	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
514	*/
515	uint32_t u32Family;
516	uint32_t u32Model;
517	uint32_t u32Stepping;
518	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
519	{
520	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
521	pVM->hm.s.svm.fAlwaysFlushTLB = true;
522	}
523
524	/*
525	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
526	*/
527	for (VMCPUID i = 0; i < pVM->cCpus; i++)
528	{
529	PVMCPU pVCpu = &pVM->aCpus[i];
530	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
531	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
532	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
533	}
534
535	for (VMCPUID i = 0; i < pVM->cCpus; i++)
536	{
537	PVMCPU pVCpu = &pVM->aCpus[i];
538
539	/*
540	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
541	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
542	*/
543	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
544	if (RT_FAILURE(rc))
545	goto failure_cleanup;
546
547	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
548	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
549	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
550	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
551
552	/*
553	* Allocate one page for the guest-state VMCB.
554	*/
555	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
556	if (RT_FAILURE(rc))
557	goto failure_cleanup;
558
559	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
560	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
561	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
562	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
563
564	/*
565	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
566	* SVM to not require one.
567	*/
568	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
569	if (RT_FAILURE(rc))
570	goto failure_cleanup;
571
572	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
573	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
574	/* Set all bits to intercept all MSR accesses (changed later on). */
575	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, UINT32_C(0xffffffff));
576	}
577
578	return VINF_SUCCESS;
579
580	failure_cleanup:
581	hmR0SvmFreeStructs(pVM);
582	return rc;
583	}
584
585
586	/**
587	* Does per-VM AMD-V termination.
588	*
589	* @returns VBox status code.
590	* @param pVM Pointer to the VM.
591	*/
592	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
593	{
594	hmR0SvmFreeStructs(pVM);
595	return VINF_SUCCESS;
596	}
597
598
599	/**
600	* Sets the permission bits for the specified MSR in the MSRPM.
601	*
602	* @param pVCpu Pointer to the VMCPU.
603	* @param uMsr The MSR for which the access permissions are being set.
604	* @param enmRead MSR read permissions.
605	* @param enmWrite MSR write permissions.
606	*/
607	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
608	{
609	unsigned ulBit;
610	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
611
612	/*
613	* Layout:
614	* Byte offset MSR range
615	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
616	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
617	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
618	* 0x1800 - 0x1fff Reserved
619	*/
620	if (uMsr <= 0x00001FFF)
621	{
622	/* Pentium-compatible MSRs. */
623	ulBit = uMsr * 2;
624	}
625	else if ( uMsr >= 0xC0000000
626	&& uMsr <= 0xC0001FFF)
627	{
628	/* AMD Sixth Generation x86 Processor MSRs. */
629	ulBit = (uMsr - 0xC0000000) * 2;
630	pbMsrBitmap += 0x800;
631	}
632	else if ( uMsr >= 0xC0010000
633	&& uMsr <= 0xC0011FFF)
634	{
635	/* AMD Seventh and Eighth Generation Processor MSRs. */
636	ulBit = (uMsr - 0xC0001000) * 2;
637	pbMsrBitmap += 0x1000;
638	}
639	else
640	{
641	AssertFailed();
642	return;
643	}
644
645	Assert(ulBit < 0x3fff /* 16 * 1024 - 1 */);
646	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
647	ASMBitSet(pbMsrBitmap, ulBit);
648	else
649	ASMBitClear(pbMsrBitmap, ulBit);
650
651	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
652	ASMBitSet(pbMsrBitmap, ulBit + 1);
653	else
654	ASMBitClear(pbMsrBitmap, ulBit + 1);
655
656	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
657	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
658	}
659
660
661	/**
662	* Sets up AMD-V for the specified VM.
663	* This function is only called once per-VM during initalization.
664	*
665	* @returns VBox status code.
666	* @param pVM Pointer to the VM.
667	*/
668	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
669	{
670	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
671	AssertReturn(pVM, VERR_INVALID_PARAMETER);
672	Assert(pVM->hm.s.svm.fSupported);
673
674	for (VMCPUID i = 0; i < pVM->cCpus; i++)
675	{
676	PVMCPU pVCpu = &pVM->aCpus[i];
677	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
678
679	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
680
681	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
682	Assert(!pVCpu->hm.s.idxExitHistoryFree);
683	HMCPU_EXIT_HISTORY_RESET(pVCpu);
684
685	/* Trap exceptions unconditionally (debug purposes). */
686	#ifdef HMSVM_ALWAYS_TRAP_PF
687	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
688	#endif
689	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
690	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
691	pVmcb->ctrl.u32InterceptException \|= 0
692	\| RT_BIT(X86_XCPT_BP)
693	\| RT_BIT(X86_XCPT_DB)
694	\| RT_BIT(X86_XCPT_DE)
695	\| RT_BIT(X86_XCPT_NM)
696	\| RT_BIT(X86_XCPT_UD)
697	\| RT_BIT(X86_XCPT_NP)
698	\| RT_BIT(X86_XCPT_SS)
699	\| RT_BIT(X86_XCPT_GP)
700	\| RT_BIT(X86_XCPT_PF)
701	\| RT_BIT(X86_XCPT_MF)
702	;
703	#endif
704
705	/* Set up unconditional intercepts and conditions. */
706	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a #VMEXIT. */
707	\| SVM_CTRL1_INTERCEPT_NMI /* Non-maskable interrupts causes a #VMEXIT. */
708	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a #VMEXIT. */
709	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a #VMEXIT. */
710	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a #VMEXIT. */
711	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a #VMEXIT. */
712	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a #VMEXIT. */
713	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO #VMEXITs. */
714	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a #VMEXIT.*/
715	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a #VMEXIT. */
716	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a #VMEXIT. */
717	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
718
719	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a #VMEXIT. */
720	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a #VMEXIT. */
721	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a #VMEXIT. */
722	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a #VMEXIT. */
723	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a #VMEXIT. */
724	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a #VMEXIT. */
725	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a #VMEXIT. */
726	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a #VMEXIT. */
727	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a #VMEXIT. */
728	\| SVM_CTRL2_INTERCEPT_MWAIT /* MWAIT causes a #VMEXIT. */
729	\| SVM_CTRL2_INTERCEPT_XSETBV; /* XSETBV causes a #VMEXIT. */
730
731	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
732	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
733
734	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
735	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
736
737	/* Intercept all DRx reads and writes by default. Changed later on. */
738	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
739	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
740
741	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
742	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
743
744	/* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
745	deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
746	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
747
748	/* Set IO and MSR bitmap permission bitmap physical addresses. */
749	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
750	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
751
752	/* No LBR virtualization. */
753	pVmcb->ctrl.u64LBRVirt = 0;
754
755	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
756	pVmcb->ctrl.u64VmcbCleanBits = 0;
757
758	/* The host ASID MBZ, for the guest start with 1. */
759	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
760
761	/*
762	* Setup the PAT MSR (applicable for Nested Paging only).
763	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
764	* so choose type 6 for all PAT slots.
765	*/
766	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
767
768	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
769	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
770
771	/* Without Nested Paging, we need additionally intercepts. */
772	if (!pVM->hm.s.fNestedPaging)
773	{
774	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
775	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
776	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
777
778	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
779	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
780	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
781
782	/* Page faults must be intercepted to implement shadow paging. */
783	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
784	}
785
786	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
787	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_TASK_SWITCH;
788	#endif
789
790	/* Apply the exceptions intercepts needed by the GIM provider. */
791	if (pVCpu->hm.s.fGIMTrapXcptUD)
792	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_UD);
793
794	/*
795	* The following MSRs are saved/restored automatically during the world-switch.
796	* Don't intercept guest read/write accesses to these MSRs.
797	*/
798	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
799	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
800	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
801	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
802	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
803	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
804	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
805	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
806	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
807	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
808	}
809
810	return VINF_SUCCESS;
811	}
812
813
814	/**
815	* Invalidates a guest page by guest virtual address.
816	*
817	* @returns VBox status code.
818	* @param pVM Pointer to the VM.
819	* @param pVCpu Pointer to the VMCPU.
820	* @param GCVirt Guest virtual address of the page to invalidate.
821	*/
822	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
823	{
824	AssertReturn(pVM, VERR_INVALID_PARAMETER);
825	Assert(pVM->hm.s.svm.fSupported);
826
827	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
828
829	/* Skip it if a TLB flush is already pending. */
830	if (!fFlushPending)
831	{
832	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
833
834	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
835	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
836
837	#if HC_ARCH_BITS == 32
838	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
839	if (CPUMIsGuestInLongMode(pVCpu))
840	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
841	else
842	#endif
843	{
844	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
845	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
846	}
847	}
848	return VINF_SUCCESS;
849	}
850
851
852	/**
853	* Flushes the appropriate tagged-TLB entries.
854	*
855	* @param pVM Pointer to the VM.
856	* @param pVCpu Pointer to the VMCPU.
857	*/
858	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
859	{
860	PVM pVM = pVCpu->CTX_SUFF(pVM);
861	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
862	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
863
864	/*
865	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
866	* This can happen both for start & resume due to long jumps back to ring-3.
867	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
868	* so we cannot reuse the ASIDs without flushing.
869	*/
870	bool fNewAsid = false;
871	Assert(pCpu->idCpu != NIL_RTCPUID);
872	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
873	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
874	{
875	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
876	pVCpu->hm.s.fForceTLBFlush = true;
877	fNewAsid = true;
878	}
879
880	/* Set TLB flush state as checked until we return from the world switch. */
881	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
882
883	/* Check for explicit TLB shootdowns. */
884	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
885	{
886	pVCpu->hm.s.fForceTLBFlush = true;
887	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
888	}
889
890	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
891
892	if (pVM->hm.s.svm.fAlwaysFlushTLB)
893	{
894	/*
895	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
896	*/
897	pCpu->uCurrentAsid = 1;
898	pVCpu->hm.s.uCurrentAsid = 1;
899	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
900	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
901
902	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
903	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
904	}
905	else if (pVCpu->hm.s.fForceTLBFlush)
906	{
907	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
908	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
909
910	if (fNewAsid)
911	{
912	++pCpu->uCurrentAsid;
913	bool fHitASIDLimit = false;
914	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
915	{
916	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
917	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
918	fHitASIDLimit = true;
919
920	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
921	{
922	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
923	pCpu->fFlushAsidBeforeUse = true;
924	}
925	else
926	{
927	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
928	pCpu->fFlushAsidBeforeUse = false;
929	}
930	}
931
932	if ( !fHitASIDLimit
933	&& pCpu->fFlushAsidBeforeUse)
934	{
935	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
936	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
937	else
938	{
939	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
940	pCpu->fFlushAsidBeforeUse = false;
941	}
942	}
943
944	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
945	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
946	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
947	}
948	else
949	{
950	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
951	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
952	else
953	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
954	}
955
956	pVCpu->hm.s.fForceTLBFlush = false;
957	}
958	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
959	* not be executed. See hmQueueInvlPage() where it is commented
960	* out. Support individual entry flushing someday. */
961	#if 0
962	else
963	{
964	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
965	{
966	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
967	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
968	for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
969	SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
970
971	pVCpu->hm.s.TlbShootdown.cPages = 0;
972	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
973	}
974	}
975	#endif
976
977
978	/* Update VMCB with the ASID. */
979	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
980	{
981	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
982	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
983	}
984
985	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
986	("vcpu idLastCpu=%x pcpu idCpu=%x\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
987	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
988	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
989	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
990	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
991	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
992	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
993
994	#ifdef VBOX_WITH_STATISTICS
995	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
996	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
997	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
998	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
999	{
1000	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1001	}
1002	else
1003	{
1004	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1005	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1006	}
1007	#endif
1008	}
1009
1010
1011	/** @name 64-bit guest on 32-bit host OS helper functions.
1012	*
1013	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1014	* mode (code segment, paging). These wrappers/helpers perform the necessary
1015	* bits for the 32->64 switcher.
1016	*
1017	* @{ */
1018	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1019	/**
1020	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1021	*
1022	* @returns VBox status code.
1023	* @param HCPhysVmcbHost Physical address of host VMCB.
1024	* @param HCPhysVmcb Physical address of the VMCB.
1025	* @param pCtx Pointer to the guest-CPU context.
1026	* @param pVM Pointer to the VM.
1027	* @param pVCpu Pointer to the VMCPU.
1028	*/
1029	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1030	{
1031	uint32_t aParam[8];
1032	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1033	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
1034	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1035	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
1036	aParam[4] = VM_RC_ADDR(pVM, pVM);
1037	aParam[5] = 0;
1038	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1039	aParam[7] = 0;
1040
1041	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1042	}
1043
1044
1045	/**
1046	* Executes the specified VMRUN handler in 64-bit mode.
1047	*
1048	* @returns VBox status code.
1049	* @param pVM Pointer to the VM.
1050	* @param pVCpu Pointer to the VMCPU.
1051	* @param pCtx Pointer to the guest-CPU context.
1052	* @param enmOp The operation to perform.
1053	* @param cParams Number of parameters.
1054	* @param paParam Array of 32-bit parameters.
1055	*/
1056	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1057	uint32_t cParams, uint32_t *paParam)
1058	{
1059	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1060	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1061
1062	/* Disable interrupts. */
1063	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1064
1065	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1066	RTCPUID idHostCpu = RTMpCpuId();
1067	CPUMR0SetLApic(pVCpu, idHostCpu);
1068	#endif
1069
1070	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1071	CPUMSetHyperEIP(pVCpu, enmOp);
1072	for (int i = (int)cParams - 1; i >= 0; i--)
1073	CPUMPushHyper(pVCpu, paParam[i]);
1074
1075	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1076	/* Call the switcher. */
1077	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1078	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1079
1080	/* Restore interrupts. */
1081	ASMSetFlags(uOldEFlags);
1082	return rc;
1083	}
1084
1085	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1086	/** @} */
1087
1088
1089	/**
1090	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1091	* the corresponding VMCB Clean bit.
1092	*
1093	* @param pVmcb Pointer to the VM control block.
1094	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1095	*/
1096	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1097	{
1098	if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
1099	{
1100	pVmcb->ctrl.u32InterceptException \|= RT_BIT(u32Xcpt);
1101	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1102	}
1103	}
1104
1105
1106	/**
1107	* Removes an exception from the intercept-exception bitmap in the VMCB and
1108	* updates the corresponding VMCB Clean bit.
1109	*
1110	* @param pVmcb Pointer to the VM control block.
1111	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1112	*/
1113	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1114	{
1115	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1116	if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1117	{
1118	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1119	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1120	}
1121	#endif
1122	}
1123
1124
1125	/**
1126	* Loads the guest CR0 control register into the guest-state area in the VMCB.
1127	* Although the guest CR0 is a separate field in the VMCB we have to consider
1128	* the FPU state itself which is shared between the host and the guest.
1129	*
1130	* @returns VBox status code.
1131	* @param pVM Pointer to the VMCPU.
1132	* @param pVmcb Pointer to the VM control block.
1133	* @param pCtx Pointer to the guest-CPU context.
1134	*
1135	* @remarks No-long-jump zone!!!
1136	*/
1137	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1138	{
1139	/*
1140	* Guest CR0.
1141	*/
1142	PVM pVM = pVCpu->CTX_SUFF(pVM);
1143	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1144	{
1145	uint64_t u64GuestCR0 = pCtx->cr0;
1146
1147	/* Always enable caching. */
1148	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1149
1150	/*
1151	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1152	*/
1153	if (!pVM->hm.s.fNestedPaging)
1154	{
1155	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1156	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1157	}
1158
1159	/*
1160	* Guest FPU bits.
1161	*/
1162	bool fInterceptNM = false;
1163	bool fInterceptMF = false;
1164	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1165	if (CPUMIsGuestFPUStateActive(pVCpu))
1166	{
1167	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1168	if (!(pCtx->cr0 & X86_CR0_NE))
1169	{
1170	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1171	fInterceptMF = true;
1172	}
1173	}
1174	else
1175	{
1176	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1177	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1178	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1179	}
1180
1181	/*
1182	* Update the exception intercept bitmap.
1183	*/
1184	if (fInterceptNM)
1185	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1186	else
1187	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1188
1189	if (fInterceptMF)
1190	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1191	else
1192	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1193
1194	pVmcb->guest.u64CR0 = u64GuestCR0;
1195	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1196	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
1197	}
1198	}
1199
1200
1201	/**
1202	* Loads the guest control registers (CR2, CR3, CR4) into the VMCB.
1203	*
1204	* @returns VBox status code.
1205	* @param pVCpu Pointer to the VMCPU.
1206	* @param pVmcb Pointer to the VM control block.
1207	* @param pCtx Pointer to the guest-CPU context.
1208	*
1209	* @remarks No-long-jump zone!!!
1210	*/
1211	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1212	{
1213	PVM pVM = pVCpu->CTX_SUFF(pVM);
1214
1215	/*
1216	* Guest CR2.
1217	*/
1218	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1219	{
1220	pVmcb->guest.u64CR2 = pCtx->cr2;
1221	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1222	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1223	}
1224
1225	/*
1226	* Guest CR3.
1227	*/
1228	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1229	{
1230	if (pVM->hm.s.fNestedPaging)
1231	{
1232	PGMMODE enmShwPagingMode;
1233	#if HC_ARCH_BITS == 32
1234	if (CPUMIsGuestInLongModeEx(pCtx))
1235	enmShwPagingMode = PGMMODE_AMD64_NX;
1236	else
1237	#endif
1238	enmShwPagingMode = PGMGetHostMode(pVM);
1239
1240	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1241	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1242	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1243	pVmcb->guest.u64CR3 = pCtx->cr3;
1244	}
1245	else
1246	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1247
1248	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1249	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1250	}
1251
1252	/*
1253	* Guest CR4.
1254	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1255	*/
1256	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1257	{
1258	uint64_t u64GuestCR4 = pCtx->cr4;
1259	if (!pVM->hm.s.fNestedPaging)
1260	{
1261	switch (pVCpu->hm.s.enmShadowMode)
1262	{
1263	case PGMMODE_REAL:
1264	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1265	AssertFailed();
1266	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1267
1268	case PGMMODE_32_BIT: /* 32-bit paging. */
1269	u64GuestCR4 &= ~X86_CR4_PAE;
1270	break;
1271
1272	case PGMMODE_PAE: /* PAE paging. */
1273	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1274	/** Must use PAE paging as we could use physical memory > 4 GB */
1275	u64GuestCR4 \|= X86_CR4_PAE;
1276	break;
1277
1278	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1279	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1280	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1281	break;
1282	#else
1283	AssertFailed();
1284	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1285	#endif
1286
1287	default: /* shut up gcc */
1288	AssertFailed();
1289	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1290	}
1291	}
1292
1293	pVmcb->guest.u64CR4 = u64GuestCR4;
1294	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1295
1296	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1297	pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1298
1299	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1300	}
1301
1302	return VINF_SUCCESS;
1303	}
1304
1305
1306	/**
1307	* Loads the guest segment registers into the VMCB.
1308	*
1309	* @returns VBox status code.
1310	* @param pVCpu Pointer to the VMCPU.
1311	* @param pVmcb Pointer to the VM control block.
1312	* @param pCtx Pointer to the guest-CPU context.
1313	*
1314	* @remarks No-long-jump zone!!!
1315	*/
1316	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1317	{
1318	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1319	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1320	{
1321	HMSVM_LOAD_SEG_REG(CS, cs);
1322	HMSVM_LOAD_SEG_REG(SS, ss);
1323	HMSVM_LOAD_SEG_REG(DS, ds);
1324	HMSVM_LOAD_SEG_REG(ES, es);
1325	HMSVM_LOAD_SEG_REG(FS, fs);
1326	HMSVM_LOAD_SEG_REG(GS, gs);
1327
1328	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1329	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1330	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1331	}
1332
1333	/* Guest TR. */
1334	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1335	{
1336	HMSVM_LOAD_SEG_REG(TR, tr);
1337	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1338	}
1339
1340	/* Guest LDTR. */
1341	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1342	{
1343	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1344	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1345	}
1346
1347	/* Guest GDTR. */
1348	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1349	{
1350	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1351	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1352	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1353	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1354	}
1355
1356	/* Guest IDTR. */
1357	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1358	{
1359	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1360	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1361	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1362	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1363	}
1364	}
1365
1366
1367	/**
1368	* Loads the guest MSRs into the VMCB.
1369	*
1370	* @param pVCpu Pointer to the VMCPU.
1371	* @param pVmcb Pointer to the VM control block.
1372	* @param pCtx Pointer to the guest-CPU context.
1373	*
1374	* @remarks No-long-jump zone!!!
1375	*/
1376	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1377	{
1378	/* Guest Sysenter MSRs. */
1379	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1380	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1381	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1382
1383	/*
1384	* Guest EFER MSR.
1385	* AMD-V requires guest EFER.SVME to be set. Weird.
1386	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1387	*/
1388	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1389	{
1390	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1391	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1392	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1393	}
1394
1395	/* 64-bit MSRs. */
1396	if (CPUMIsGuestInLongModeEx(pCtx))
1397	{
1398	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1399	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1400	}
1401	else
1402	{
1403	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1404	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1405	{
1406	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1407	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1408	}
1409	}
1410
1411
1412	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1413	* be writable in 32-bit mode. Clarify with AMD spec. */
1414	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1415	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1416	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1417	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1418	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1419	}
1420
1421
1422	/**
1423	* Loads the guest state into the VMCB and programs the necessary intercepts
1424	* accordingly.
1425	*
1426	* @param pVCpu Pointer to the VMCPU.
1427	* @param pVmcb Pointer to the VM control block.
1428	* @param pCtx Pointer to the guest-CPU context.
1429	*
1430	* @remarks No-long-jump zone!!!
1431	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1432	*/
1433	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1434	{
1435	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1436	return;
1437	Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
1438	Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
1439
1440	bool fInterceptDB = false;
1441	bool fInterceptMovDRx = false;
1442
1443	/*
1444	* Anyone single stepping on the host side? If so, we'll have to use the
1445	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1446	* the VMM level like the VT-x implementations does.
1447	*/
1448	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1449	if (fStepping)
1450	{
1451	pVCpu->hm.s.fClearTrapFlag = true;
1452	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1453	fInterceptDB = true;
1454	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1455	}
1456
1457	if ( fStepping
1458	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1459	{
1460	/*
1461	* Use the combined guest and host DRx values found in the hypervisor
1462	* register set because the debugger has breakpoints active or someone
1463	* is single stepping on the host side.
1464	*
1465	* Note! DBGF expects a clean DR6 state before executing guest code.
1466	*/
1467	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1468	if ( CPUMIsGuestInLongModeEx(pCtx)
1469	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1470	{
1471	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1472	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1473	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1474	}
1475	else
1476	#endif
1477	if (!CPUMIsHyperDebugStateActive(pVCpu))
1478	{
1479	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1480	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1481	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1482	}
1483
1484	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1485	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1486	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1487	{
1488	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1489	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1490	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1491	pVCpu->hm.s.fUsingHyperDR7 = true;
1492	}
1493
1494	/** @todo If we cared, we could optimize to allow the guest to read registers
1495	* with the same values. */
1496	fInterceptDB = true;
1497	fInterceptMovDRx = true;
1498	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1499	}
1500	else
1501	{
1502	/*
1503	* Update DR6, DR7 with the guest values if necessary.
1504	*/
1505	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1506	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1507	{
1508	pVmcb->guest.u64DR7 = pCtx->dr[7];
1509	pVmcb->guest.u64DR6 = pCtx->dr[6];
1510	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1511	pVCpu->hm.s.fUsingHyperDR7 = false;
1512	}
1513
1514	/*
1515	* If the guest has enabled debug registers, we need to load them prior to
1516	* executing guest code so they'll trigger at the right time.
1517	*/
1518	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1519	{
1520	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1521	if ( CPUMIsGuestInLongModeEx(pCtx)
1522	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1523	{
1524	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1525	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1526	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1527	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1528	}
1529	else
1530	#endif
1531	if (!CPUMIsGuestDebugStateActive(pVCpu))
1532	{
1533	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1534	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1535	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1536	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1537	}
1538	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1539	}
1540	/*
1541	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1542	* intercept #DB as DR6 is updated in the VMCB.
1543	*/
1544	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1545	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1546	&& !CPUMIsGuestDebugStateActive(pVCpu))
1547	#else
1548	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1549	#endif
1550	{
1551	fInterceptMovDRx = true;
1552	}
1553	}
1554
1555	/*
1556	* Set up the intercepts.
1557	*/
1558	if (fInterceptDB)
1559	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_DB);
1560	else
1561	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_DB);
1562
1563	if (fInterceptMovDRx)
1564	{
1565	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1566	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1567	{
1568	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1569	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1570	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1571	}
1572	}
1573	else
1574	{
1575	if ( pVmcb->ctrl.u16InterceptRdDRx
1576	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1577	{
1578	pVmcb->ctrl.u16InterceptRdDRx = 0;
1579	pVmcb->ctrl.u16InterceptWrDRx = 0;
1580	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1581	}
1582	}
1583
1584	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
1585	}
1586
1587
1588	/**
1589	* Loads the guest APIC state (currently just the TPR).
1590	*
1591	* @returns VBox status code.
1592	* @param pVCpu Pointer to the VMCPU.
1593	* @param pVmcb Pointer to the VM control block.
1594	* @param pCtx Pointer to the guest-CPU context.
1595	*/
1596	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1597	{
1598	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1599	return VINF_SUCCESS;
1600
1601	bool fPendingIntr;
1602	uint8_t u8Tpr;
1603	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1604	AssertRCReturn(rc, rc);
1605
1606	/* Assume that we need to trap all TPR accesses and thus need not check on
1607	every #VMEXIT if we should update the TPR. */
1608	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1609	pVCpu->hm.s.svm.fSyncVTpr = false;
1610
1611	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1612	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1613	{
1614	pCtx->msrLSTAR = u8Tpr;
1615
1616	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1617	if (fPendingIntr)
1618	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1619	else
1620	{
1621	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1622	pVCpu->hm.s.svm.fSyncVTpr = true;
1623	}
1624	}
1625	else
1626	{
1627	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1628	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1629
1630	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1631	if (fPendingIntr)
1632	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1633	else
1634	{
1635	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1636	pVCpu->hm.s.svm.fSyncVTpr = true;
1637	}
1638
1639	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1640	}
1641
1642	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1643	return rc;
1644	}
1645
1646
1647	/**
1648	* Loads the exception interrupts required for guest execution in the VMCB.
1649	*
1650	* @returns VBox status code.
1651	* @param pVCpu Pointer to the VMCPU.
1652	* @param pVmcb Pointer to the VM control block.
1653	* @param pCtx Pointer to the guest-CPU context.
1654	*/
1655	static int hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1656	{
1657	int rc = VINF_SUCCESS;
1658	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1659	{
1660	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
1661	if (pVCpu->hm.s.fGIMTrapXcptUD)
1662	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
1663	else
1664	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_UD);
1665	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
1666	}
1667	return rc;
1668	}
1669
1670
1671	/**
1672	* Sets up the appropriate function to run guest code.
1673	*
1674	* @returns VBox status code.
1675	* @param pVCpu Pointer to the VMCPU.
1676	* @param pCtx Pointer to the guest-CPU context.
1677	*
1678	* @remarks No-long-jump zone!!!
1679	*/
1680	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1681	{
1682	if (CPUMIsGuestInLongModeEx(pCtx))
1683	{
1684	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1685	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1686	#endif
1687	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1688	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1689	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1690	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1691	#else
1692	/* 64-bit host or hybrid host. */
1693	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1694	#endif
1695	}
1696	else
1697	{
1698	/* Guest is not in long mode, use the 32-bit handler. */
1699	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1700	}
1701	return VINF_SUCCESS;
1702	}
1703
1704
1705	/**
1706	* Enters the AMD-V session.
1707	*
1708	* @returns VBox status code.
1709	* @param pVM Pointer to the VM.
1710	* @param pVCpu Pointer to the VMCPU.
1711	* @param pCpu Pointer to the CPU info struct.
1712	*/
1713	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1714	{
1715	AssertPtr(pVM);
1716	AssertPtr(pVCpu);
1717	Assert(pVM->hm.s.svm.fSupported);
1718	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1719	NOREF(pVM); NOREF(pCpu);
1720
1721	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1722	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1723
1724	pVCpu->hm.s.fLeaveDone = false;
1725	return VINF_SUCCESS;
1726	}
1727
1728
1729	/**
1730	* Thread-context callback for AMD-V.
1731	*
1732	* @param enmEvent The thread-context event.
1733	* @param pVCpu Pointer to the VMCPU.
1734	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1735	* @thread EMT(pVCpu)
1736	*/
1737	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1738	{
1739	NOREF(fGlobalInit);
1740
1741	switch (enmEvent)
1742	{
1743	case RTTHREADCTXEVENT_PREEMPTING:
1744	{
1745	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1746	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1747	VMCPU_ASSERT_EMT(pVCpu);
1748
1749	PVM pVM = pVCpu->CTX_SUFF(pVM);
1750	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1751
1752	/* No longjmps (log-flush, locks) in this fragile context. */
1753	VMMRZCallRing3Disable(pVCpu);
1754
1755	if (!pVCpu->hm.s.fLeaveDone)
1756	{
1757	hmR0SvmLeave(pVM, pVCpu, pCtx);
1758	pVCpu->hm.s.fLeaveDone = true;
1759	}
1760
1761	/* Leave HM context, takes care of local init (term). */
1762	int rc = HMR0LeaveCpu(pVCpu);
1763	AssertRC(rc); NOREF(rc);
1764
1765	/* Restore longjmp state. */
1766	VMMRZCallRing3Enable(pVCpu);
1767	STAM_COUNTER_INC(&pVCpu->hm.s.StatPreemptPreempting);
1768	break;
1769	}
1770
1771	case RTTHREADCTXEVENT_RESUMED:
1772	{
1773	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1774	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1775	VMCPU_ASSERT_EMT(pVCpu);
1776
1777	/* No longjmps (log-flush, locks) in this fragile context. */
1778	VMMRZCallRing3Disable(pVCpu);
1779
1780	/*
1781	* Initialize the bare minimum state required for HM. This takes care of
1782	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1783	*/
1784	int rc = HMR0EnterCpu(pVCpu);
1785	AssertRC(rc); NOREF(rc);
1786	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1787
1788	pVCpu->hm.s.fLeaveDone = false;
1789
1790	/* Restore longjmp state. */
1791	VMMRZCallRing3Enable(pVCpu);
1792	break;
1793	}
1794
1795	default:
1796	break;
1797	}
1798	}
1799
1800
1801	/**
1802	* Saves the host state.
1803	*
1804	* @returns VBox status code.
1805	* @param pVM Pointer to the VM.
1806	* @param pVCpu Pointer to the VMCPU.
1807	*
1808	* @remarks No-long-jump zone!!!
1809	*/
1810	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1811	{
1812	NOREF(pVM);
1813	NOREF(pVCpu);
1814	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1815	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
1816	return VINF_SUCCESS;
1817	}
1818
1819
1820	/**
1821	* Loads the guest state into the VMCB.
1822	*
1823	* The CPU state will be loaded from these fields on every successful VM-entry.
1824	* Also sets up the appropriate VMRUN function to execute guest code based on
1825	* the guest CPU mode.
1826	*
1827	* @returns VBox status code.
1828	* @param pVM Pointer to the VM.
1829	* @param pVCpu Pointer to the VMCPU.
1830	* @param pCtx Pointer to the guest-CPU context.
1831	*
1832	* @remarks No-long-jump zone!!!
1833	*/
1834	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1835	{
1836	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1837	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1838
1839	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1840
1841	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1842	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1843
1844	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1845	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1846
1847	pVmcb->guest.u64RIP = pCtx->rip;
1848	pVmcb->guest.u64RSP = pCtx->rsp;
1849	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1850	pVmcb->guest.u64RAX = pCtx->rax;
1851
1852	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1853	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1854
1855	rc = hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
1856	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestXcptIntercepts! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1857
1858	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1859	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1860
1861	/* Clear any unused and reserved bits. */
1862	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1863	\| HM_CHANGED_GUEST_RSP
1864	\| HM_CHANGED_GUEST_RFLAGS
1865	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1866	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1867	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1868	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
1869	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1870	\| HM_CHANGED_SVM_RESERVED2
1871	\| HM_CHANGED_SVM_RESERVED3
1872	\| HM_CHANGED_SVM_RESERVED4);
1873
1874	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
1875	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
1876	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
1877	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1878
1879	Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss, pCtx->rsp));
1880	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1881	return rc;
1882	}
1883
1884
1885	/**
1886	* Loads the state shared between the host and guest into the
1887	* VMCB.
1888	*
1889	* @param pVCpu Pointer to the VMCPU.
1890	* @param pVmcb Pointer to the VM control block.
1891	* @param pCtx Pointer to the guest-CPU context.
1892	*
1893	* @remarks No-long-jump zone!!!
1894	*/
1895	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1896	{
1897	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1898	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1899
1900	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1901	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
1902
1903	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1904	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
1905
1906	/* Unused on AMD-V. */
1907	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
1908
1909	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
1910	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1911	}
1912
1913
1914	/**
1915	* Saves the entire guest state from the VMCB into the
1916	* guest-CPU context. Currently there is no residual state left in the CPU that
1917	* is not updated in the VMCB.
1918	*
1919	* @returns VBox status code.
1920	* @param pVCpu Pointer to the VMCPU.
1921	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1922	* out-of-sync. Make sure to update the required fields
1923	* before using them.
1924	*/
1925	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1926	{
1927	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1928
1929	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1930
1931	pMixedCtx->rip = pVmcb->guest.u64RIP;
1932	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1933	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1934	pMixedCtx->rax = pVmcb->guest.u64RAX;
1935
1936	/*
1937	* Guest interrupt shadow.
1938	*/
1939	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1940	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1941	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1942	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1943
1944	/*
1945	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1946	*/
1947	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1948
1949	/*
1950	* Guest MSRs.
1951	*/
1952	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1953	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1954	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1955	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1956	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1957	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1958	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1959	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1960
1961	/*
1962	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1963	*/
1964	HMSVM_SAVE_SEG_REG(CS, cs);
1965	HMSVM_SAVE_SEG_REG(SS, ss);
1966	HMSVM_SAVE_SEG_REG(DS, ds);
1967	HMSVM_SAVE_SEG_REG(ES, es);
1968	HMSVM_SAVE_SEG_REG(FS, fs);
1969	HMSVM_SAVE_SEG_REG(GS, gs);
1970
1971	/*
1972	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1973	* register (yet).
1974	*/
1975	/** @todo SELM might need to be fixed as it too should not care about the
1976	* granularity bit. See @bugref{6785}. */
1977	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1978	&& pMixedCtx->cs.Attr.n.u1Present
1979	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1980	{
1981	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1982	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1983	}
1984
1985	#ifdef VBOX_STRICT
1986	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1987	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1988	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1989	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1990	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1991	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
1992	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1993
1994	HMSVM_ASSERT_SEG_GRANULARITY(cs);
1995	HMSVM_ASSERT_SEG_GRANULARITY(ss);
1996	HMSVM_ASSERT_SEG_GRANULARITY(ds);
1997	HMSVM_ASSERT_SEG_GRANULARITY(es);
1998	HMSVM_ASSERT_SEG_GRANULARITY(fs);
1999	HMSVM_ASSERT_SEG_GRANULARITY(gs);
2000
2001	# undef HMSVM_ASSERT_SEL_GRANULARITY
2002	#endif
2003
2004	/*
2005	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
2006	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
2007	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
2008	* See AMD spec. 15.5.1 "Basic operation".
2009	*/
2010	Assert(!(pVmcb->guest.u8CPL & ~0x3));
2011	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
2012
2013	/*
2014	* Guest TR.
2015	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
2016	* between Intel and AMD. See @bugref{6208} comment #39.
2017	*/
2018	HMSVM_SAVE_SEG_REG(TR, tr);
2019	if (CPUMIsGuestInLongModeEx(pMixedCtx))
2020	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2021
2022	/*
2023	* Guest Descriptor-Table registers.
2024	*/
2025	HMSVM_SAVE_SEG_REG(LDTR, ldtr);
2026	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2027	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2028
2029	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2030	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2031
2032	/*
2033	* Guest Debug registers.
2034	*/
2035	if (!pVCpu->hm.s.fUsingHyperDR7)
2036	{
2037	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2038	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2039	}
2040	else
2041	{
2042	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2043	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2044	}
2045
2046	/*
2047	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2048	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2049	*/
2050	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
2051	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2052	{
2053	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2054	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2055	}
2056	}
2057
2058
2059	/**
2060	* Does the necessary state syncing before returning to ring-3 for any reason
2061	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2062	*
2063	* @param pVM Pointer to the VM.
2064	* @param pVCpu Pointer to the VMCPU.
2065	* @param pMixedCtx Pointer to the guest-CPU context.
2066	*
2067	* @remarks No-long-jmp zone!!!
2068	*/
2069	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2070	{
2071	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2072	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2073	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2074
2075	/*
2076	* !!! IMPORTANT !!!
2077	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2078	*/
2079
2080	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2081	if (CPUMIsGuestFPUStateActive(pVCpu))
2082	{
2083	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
2084	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
2085	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
2086	}
2087
2088	/*
2089	* Restore host debug registers if necessary and resync on next R0 reentry.
2090	*/
2091	#ifdef VBOX_STRICT
2092	if (CPUMIsHyperDebugStateActive(pVCpu))
2093	{
2094	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2095	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2096	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2097	}
2098	#endif
2099	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2100	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
2101
2102	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2103	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2104
2105	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2106	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2107	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2108	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2109	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2110
2111	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2112	}
2113
2114
2115	/**
2116	* Leaves the AMD-V session.
2117	*
2118	* @returns VBox status code.
2119	* @param pVM Pointer to the VM.
2120	* @param pVCpu Pointer to the VMCPU.
2121	* @param pCtx Pointer to the guest-CPU context.
2122	*/
2123	static int hmR0SvmLeaveSession(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2124	{
2125	HM_DISABLE_PREEMPT();
2126	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2127	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2128
2129	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2130	and done this from the SVMR0ThreadCtxCallback(). */
2131	if (!pVCpu->hm.s.fLeaveDone)
2132	{
2133	hmR0SvmLeave(pVM, pVCpu, pCtx);
2134	pVCpu->hm.s.fLeaveDone = true;
2135	}
2136
2137	/*
2138	* !!! IMPORTANT !!!
2139	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2140	*/
2141
2142	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2143	VMMR0ThreadCtxHooksDeregister(pVCpu);
2144
2145	/* Leave HM context. This takes care of local init (term). */
2146	int rc = HMR0LeaveCpu(pVCpu);
2147
2148	HM_RESTORE_PREEMPT();
2149	return rc;
2150	}
2151
2152
2153	/**
2154	* Does the necessary state syncing before doing a longjmp to ring-3.
2155	*
2156	* @returns VBox status code.
2157	* @param pVM Pointer to the VM.
2158	* @param pVCpu Pointer to the VMCPU.
2159	* @param pCtx Pointer to the guest-CPU context.
2160	*
2161	* @remarks No-long-jmp zone!!!
2162	*/
2163	static int hmR0SvmLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2164	{
2165	return hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
2166	}
2167
2168
2169	/**
2170	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2171	* any remaining host state) before we longjump to ring-3 and possibly get
2172	* preempted.
2173	*
2174	* @param pVCpu Pointer to the VMCPU.
2175	* @param enmOperation The operation causing the ring-3 longjump.
2176	* @param pvUser The user argument (pointer to the possibly
2177	* out-of-date guest-CPU context).
2178	*/
2179	DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2180	{
2181	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2182	{
2183	/*
2184	* !!! IMPORTANT !!!
2185	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2186	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2187	*/
2188	VMMRZCallRing3RemoveNotification(pVCpu);
2189	VMMRZCallRing3Disable(pVCpu);
2190	HM_DISABLE_PREEMPT();
2191
2192	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2193	if (CPUMIsGuestFPUStateActive(pVCpu))
2194	CPUMR0SaveGuestFPU(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser);
2195
2196	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2197	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2198
2199	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2200	VMMR0ThreadCtxHooksDeregister(pVCpu);
2201
2202	/* Leave HM context. This takes care of local init (term). */
2203	HMR0LeaveCpu(pVCpu);
2204
2205	HM_RESTORE_PREEMPT();
2206	return VINF_SUCCESS;
2207	}
2208
2209	Assert(pVCpu);
2210	Assert(pvUser);
2211	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2212	HMSVM_ASSERT_PREEMPT_SAFE();
2213
2214	VMMRZCallRing3Disable(pVCpu);
2215	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2216
2217	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2218	int rc = hmR0SvmLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser);
2219	AssertRCReturn(rc, rc);
2220
2221	VMMRZCallRing3Enable(pVCpu);
2222	return VINF_SUCCESS;
2223	}
2224
2225
2226	/**
2227	* Take necessary actions before going back to ring-3.
2228	*
2229	* An action requires us to go back to ring-3. This function does the necessary
2230	* steps before we can safely return to ring-3. This is not the same as longjmps
2231	* to ring-3, this is voluntary.
2232	*
2233	* @param pVM Pointer to the VM.
2234	* @param pVCpu Pointer to the VMCPU.
2235	* @param pCtx Pointer to the guest-CPU context.
2236	* @param rcExit The reason for exiting to ring-3. Can be
2237	* VINF_VMM_UNKNOWN_RING3_CALL.
2238	*/
2239	static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2240	{
2241	Assert(pVM);
2242	Assert(pVCpu);
2243	Assert(pCtx);
2244	HMSVM_ASSERT_PREEMPT_SAFE();
2245
2246	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2247	VMMRZCallRing3Disable(pVCpu);
2248	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2249
2250	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2251	if (pVCpu->hm.s.Event.fPending)
2252	{
2253	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2254	Assert(!pVCpu->hm.s.Event.fPending);
2255	}
2256
2257	/* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2258	and if we're injecting an event we should have a TRPM trap pending. */
2259	Assert(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu));
2260	Assert(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu));
2261
2262	/* Sync. the necessary state for going back to ring-3. */
2263	hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
2264	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2265
2266	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2267	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2268	\| CPUM_CHANGED_LDTR
2269	\| CPUM_CHANGED_GDTR
2270	\| CPUM_CHANGED_IDTR
2271	\| CPUM_CHANGED_TR
2272	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2273	if ( pVM->hm.s.fNestedPaging
2274	&& CPUMIsGuestPagingEnabledEx(pCtx))
2275	{
2276	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2277	}
2278
2279	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2280	if (rcExit != VINF_EM_RAW_INTERRUPT)
2281	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2282
2283	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2284
2285	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2286	VMMRZCallRing3RemoveNotification(pVCpu);
2287	VMMRZCallRing3Enable(pVCpu);
2288	}
2289
2290
2291	/**
2292	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2293	* intercepts.
2294	*
2295	* @param pVM The shared VM handle.
2296	* @param pVCpu Pointer to the VMCPU.
2297	*
2298	* @remarks No-long-jump zone!!!
2299	*/
2300	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu)
2301	{
2302	bool fParavirtTsc;
2303	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2304	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2305	if (fCanUseRealTsc)
2306	{
2307	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
2308	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
2309	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2310	}
2311	else
2312	{
2313	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2314	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2315	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2316	}
2317	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2318
2319	/** @todo later optimize this to be done elsewhere and not before every
2320	* VM-entry. */
2321	if (fParavirtTsc)
2322	{
2323	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
2324	AssertRC(rc);
2325	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2326	}
2327	}
2328
2329
2330	/**
2331	* Sets an event as a pending event to be injected into the guest.
2332	*
2333	* @param pVCpu Pointer to the VMCPU.
2334	* @param pEvent Pointer to the SVM event.
2335	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2336	* page-fault.
2337	*
2338	* @remarks Statistics counter assumes this is a guest event being reflected to
2339	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2340	*/
2341	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2342	{
2343	Assert(!pVCpu->hm.s.Event.fPending);
2344	Assert(pEvent->n.u1Valid);
2345
2346	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
2347	pVCpu->hm.s.Event.fPending = true;
2348	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2349
2350	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2351	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2352
2353	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
2354	}
2355
2356
2357	/**
2358	* Injects an event into the guest upon VMRUN by updating the relevant field
2359	* in the VMCB.
2360	*
2361	* @param pVCpu Pointer to the VMCPU.
2362	* @param pVmcb Pointer to the guest VM control block.
2363	* @param pCtx Pointer to the guest-CPU context.
2364	* @param pEvent Pointer to the event.
2365	*
2366	* @remarks No-long-jump zone!!!
2367	* @remarks Requires CR0!
2368	*/
2369	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2370	{
2371	NOREF(pVCpu); NOREF(pCtx);
2372
2373	pVmcb->ctrl.EventInject.u = pEvent->u;
2374	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2375
2376	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2377	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2378	}
2379
2380
2381
2382	/**
2383	* Converts any TRPM trap into a pending HM event. This is typically used when
2384	* entering from ring-3 (not longjmp returns).
2385	*
2386	* @param pVCpu Pointer to the VMCPU.
2387	*/
2388	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2389	{
2390	Assert(TRPMHasTrap(pVCpu));
2391	Assert(!pVCpu->hm.s.Event.fPending);
2392
2393	uint8_t uVector;
2394	TRPMEVENT enmTrpmEvent;
2395	RTGCUINT uErrCode;
2396	RTGCUINTPTR GCPtrFaultAddress;
2397	uint8_t cbInstr;
2398
2399	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2400	AssertRC(rc);
2401
2402	SVMEVENT Event;
2403	Event.u = 0;
2404	Event.n.u1Valid = 1;
2405	Event.n.u8Vector = uVector;
2406
2407	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2408	if (enmTrpmEvent == TRPM_TRAP)
2409	{
2410	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2411	switch (uVector)
2412	{
2413	case X86_XCPT_NMI:
2414	{
2415	Event.n.u3Type = SVM_EVENT_NMI;
2416	break;
2417	}
2418
2419	case X86_XCPT_PF:
2420	case X86_XCPT_DF:
2421	case X86_XCPT_TS:
2422	case X86_XCPT_NP:
2423	case X86_XCPT_SS:
2424	case X86_XCPT_GP:
2425	case X86_XCPT_AC:
2426	{
2427	Event.n.u1ErrorCodeValid = 1;
2428	Event.n.u32ErrorCode = uErrCode;
2429	break;
2430	}
2431	}
2432	}
2433	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2434	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2435	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2436	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2437	else
2438	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2439
2440	rc = TRPMResetTrap(pVCpu);
2441	AssertRC(rc);
2442
2443	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2444	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2445
2446	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2447	STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect);
2448	}
2449
2450
2451	/**
2452	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2453	* AMD-V to execute any instruction.
2454	*
2455	* @param pvCpu Pointer to the VMCPU.
2456	*/
2457	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2458	{
2459	Assert(pVCpu->hm.s.Event.fPending);
2460	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2461
2462	SVMEVENT Event;
2463	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2464
2465	uint8_t uVector = Event.n.u8Vector;
2466	uint8_t uVectorType = Event.n.u3Type;
2467
2468	TRPMEVENT enmTrapType;
2469	switch (uVectorType)
2470	{
2471	case SVM_EVENT_EXTERNAL_IRQ:
2472	enmTrapType = TRPM_HARDWARE_INT;
2473	break;
2474	case SVM_EVENT_SOFTWARE_INT:
2475	enmTrapType = TRPM_SOFTWARE_INT;
2476	break;
2477	case SVM_EVENT_EXCEPTION:
2478	case SVM_EVENT_NMI:
2479	enmTrapType = TRPM_TRAP;
2480	break;
2481	default:
2482	AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2483	enmTrapType = TRPM_32BIT_HACK;
2484	break;
2485	}
2486
2487	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2488
2489	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2490	AssertRC(rc);
2491
2492	if (Event.n.u1ErrorCodeValid)
2493	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2494
2495	if ( uVectorType == SVM_EVENT_EXCEPTION
2496	&& uVector == X86_XCPT_PF)
2497	{
2498	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2499	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2500	}
2501	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2502	{
2503	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2504	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2505	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2506	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2507	}
2508	pVCpu->hm.s.Event.fPending = false;
2509	}
2510
2511
2512	/**
2513	* Gets the guest's interrupt-shadow.
2514	*
2515	* @returns The guest's interrupt-shadow.
2516	* @param pVCpu Pointer to the VMCPU.
2517	* @param pCtx Pointer to the guest-CPU context.
2518	*
2519	* @remarks No-long-jump zone!!!
2520	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2521	*/
2522	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2523	{
2524	/*
2525	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2526	* inhibit interrupts or clear any existing interrupt-inhibition.
2527	*/
2528	uint32_t uIntrState = 0;
2529	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2530	{
2531	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2532	{
2533	/*
2534	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2535	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2536	*/
2537	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2538	}
2539	else
2540	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2541	}
2542	return uIntrState;
2543	}
2544
2545
2546	/**
2547	* Sets the virtual interrupt intercept control in the VMCB which
2548	* instructs AMD-V to cause a #VMEXIT as soon as the guest is in a state to
2549	* receive interrupts.
2550	*
2551	* @param pVmcb Pointer to the VM control block.
2552	*/
2553	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2554	{
2555	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2556	{
2557	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2558	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2559	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
2560	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2561
2562	Log4(("Setting VINTR intercept\n"));
2563	}
2564	}
2565
2566
2567	/**
2568	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
2569	* #VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
2570	* virtual NMIs.
2571	*
2572	* @param pVmcb Pointer to the VM control block.
2573	*/
2574	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
2575	{
2576	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_IRET))
2577	{
2578	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_IRET;
2579	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2580
2581	Log4(("Setting IRET intercept\n"));
2582	}
2583	}
2584
2585
2586	/**
2587	* Clears the IRET intercept control in the VMCB.
2588	*
2589	* @param pVmcb Pointer to the VM control block.
2590	*/
2591	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
2592	{
2593	if (pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_IRET)
2594	{
2595	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_IRET;
2596	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2597
2598	Log4(("Clearing IRET intercept\n"));
2599	}
2600	}
2601
2602
2603	/**
2604	* Evaluates the event to be delivered to the guest and sets it as the pending
2605	* event.
2606	*
2607	* @param pVCpu Pointer to the VMCPU.
2608	* @param pCtx Pointer to the guest-CPU context.
2609	*/
2610	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2611	{
2612	Assert(!pVCpu->hm.s.Event.fPending);
2613	Log4Func(("\n"));
2614
2615	bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2616	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2617	bool const fBlockNmi = RT_BOOL(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS));
2618	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2619
2620	SVMEVENT Event;
2621	Event.u = 0;
2622	/** @todo SMI. SMIs take priority over NMIs. */
2623	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2624	{
2625	if (fBlockNmi)
2626	hmR0SvmSetIretIntercept(pVmcb);
2627	else if (fIntShadow)
2628	hmR0SvmSetVirtIntrIntercept(pVmcb);
2629	else
2630	{
2631	Log4(("Pending NMI\n"));
2632
2633	Event.n.u1Valid = 1;
2634	Event.n.u8Vector = X86_XCPT_NMI;
2635	Event.n.u3Type = SVM_EVENT_NMI;
2636
2637	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2638	hmR0SvmSetIretIntercept(pVmcb);
2639	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2640	}
2641	}
2642	else if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
2643	{
2644	/*
2645	* Check if the guest can receive external interrupts (PIC/APIC). Once we do PDMGetInterrupt() we -must- deliver
2646	* the interrupt ASAP. We must not execute any guest code until we inject the interrupt which is why it is
2647	* evaluated here and not set as pending, solely based on the force-flags.
2648	*/
2649	if ( !fBlockInt
2650	&& !fIntShadow)
2651	{
2652	uint8_t u8Interrupt;
2653	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2654	if (RT_SUCCESS(rc))
2655	{
2656	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2657
2658	Event.n.u1Valid = 1;
2659	Event.n.u8Vector = u8Interrupt;
2660	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2661
2662	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2663	}
2664	else
2665	{
2666	/** @todo Does this actually happen? If not turn it into an assertion. */
2667	Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
2668	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2669	}
2670	}
2671	else
2672	hmR0SvmSetVirtIntrIntercept(pVmcb);
2673	}
2674	}
2675
2676
2677	/**
2678	* Injects any pending events into the guest if the guest is in a state to
2679	* receive them.
2680	*
2681	* @param pVCpu Pointer to the VMCPU.
2682	* @param pCtx Pointer to the guest-CPU context.
2683	*/
2684	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2685	{
2686	Assert(!TRPMHasTrap(pVCpu));
2687	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2688
2689	bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2690	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2691	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2692
2693	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2694	{
2695	SVMEVENT Event;
2696	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2697	Assert(Event.n.u1Valid);
2698	#ifdef VBOX_STRICT
2699	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2700	{
2701	Assert(!fBlockInt);
2702	Assert(!fIntShadow);
2703	}
2704	else if (Event.n.u3Type == SVM_EVENT_NMI)
2705	Assert(!fIntShadow);
2706	#endif
2707
2708	Log4(("Injecting pending HM event.\n"));
2709	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2710	pVCpu->hm.s.Event.fPending = false;
2711
2712	#ifdef VBOX_WITH_STATISTICS
2713	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2714	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2715	else
2716	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2717	#endif
2718	}
2719
2720	/* Update the guest interrupt shadow in the VMCB. */
2721	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2722	NOREF(fBlockInt);
2723	}
2724
2725
2726	/**
2727	* Reports world-switch error and dumps some useful debug info.
2728	*
2729	* @param pVM Pointer to the VM.
2730	* @param pVCpu Pointer to the VMCPU.
2731	* @param rcVMRun The return code from VMRUN (or
2732	* VERR_SVM_INVALID_GUEST_STATE for invalid
2733	* guest-state).
2734	* @param pCtx Pointer to the guest-CPU context.
2735	*/
2736	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2737	{
2738	NOREF(pCtx);
2739	HMSVM_ASSERT_PREEMPT_SAFE();
2740	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2741
2742	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2743	{
2744	HMDumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
2745	#ifdef VBOX_STRICT
2746	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2747	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2748	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2749	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2750	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2751	Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2752	Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2753	Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2754	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2755	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2756	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2757
2758	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2759	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2760	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2761
2762	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2763	Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2764	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2765	Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2766	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2767	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2768	Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2769	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2770	Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2771	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2772
2773	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2774	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2775	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2776	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2777	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2778	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2779	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2780	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2781	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2782	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2783	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2784	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2785	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2786	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2787	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2788	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2789	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2790
2791	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2792	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2793
2794	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2795	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2796	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2797	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2798	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2799	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2800	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2801	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2802	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2803	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2804	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2805	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2806	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2807	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2808	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2809	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2810	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2811	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2812	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2813	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2814
2815	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2816	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2817
2818	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2819	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2820	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2821	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2822
2823	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2824	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2825
2826	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2827	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2828	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2829	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2830
2831	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2832	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2833	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2834	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2835	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2836	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2837	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2838
2839	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2840	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2841	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2842	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2843
2844	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2845	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2846	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2847
2848	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2849	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2850	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2851	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2852	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2853	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2854	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2855	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2856	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2857	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2858	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2859	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2860	#else
2861	NOREF(pVmcb);
2862	#endif /* VBOX_STRICT */
2863	}
2864	else
2865	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2866	}
2867
2868
2869	/**
2870	* Check per-VM and per-VCPU force flag actions that require us to go back to
2871	* ring-3 for one reason or another.
2872	*
2873	* @returns VBox status code (information status code included).
2874	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2875	* ring-3.
2876	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2877	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2878	* interrupts)
2879	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2880	* all EMTs to be in ring-3.
2881	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2882	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2883	* to the EM loop.
2884	*
2885	* @param pVM Pointer to the VM.
2886	* @param pVCpu Pointer to the VMCPU.
2887	* @param pCtx Pointer to the guest-CPU context.
2888	*/
2889	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2890	{
2891	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2892
2893	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2894	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2895	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2896
2897	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
2898	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2899	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
2900	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2901	{
2902	/* Pending PGM C3 sync. */
2903	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2904	{
2905	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2906	if (rc != VINF_SUCCESS)
2907	{
2908	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2909	return rc;
2910	}
2911	}
2912
2913	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2914	/* -XXX- what was that about single stepping? */
2915	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2916	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2917	{
2918	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2919	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2920	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2921	return rc;
2922	}
2923
2924	/* Pending VM request packets, such as hardware interrupts. */
2925	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2926	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2927	{
2928	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2929	return VINF_EM_PENDING_REQUEST;
2930	}
2931
2932	/* Pending PGM pool flushes. */
2933	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2934	{
2935	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2936	return VINF_PGM_POOL_FLUSH_PENDING;
2937	}
2938
2939	/* Pending DMA requests. */
2940	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2941	{
2942	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2943	return VINF_EM_RAW_TO_R3;
2944	}
2945	}
2946
2947	return VINF_SUCCESS;
2948	}
2949
2950
2951	/**
2952	* Does the preparations before executing guest code in AMD-V.
2953	*
2954	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2955	* recompiler. We must be cautious what we do here regarding committing
2956	* guest-state information into the the VMCB assuming we assuredly execute the
2957	* guest in AMD-V. If we fall back to the recompiler after updating the VMCB and
2958	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2959	* that the recompiler can (and should) use them when it resumes guest
2960	* execution. Otherwise such operations must be done when we can no longer
2961	* exit to ring-3.
2962	*
2963	* @returns VBox status code (informational status codes included).
2964	* @retval VINF_SUCCESS if we can proceed with running the guest.
2965	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2966	*
2967	* @param pVM Pointer to the VM.
2968	* @param pVCpu Pointer to the VMCPU.
2969	* @param pCtx Pointer to the guest-CPU context.
2970	* @param pSvmTransient Pointer to the SVM transient structure.
2971	*/
2972	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2973	{
2974	HMSVM_ASSERT_PREEMPT_SAFE();
2975
2976	/* Check force flag actions that might require us to go back to ring-3. */
2977	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2978	if (rc != VINF_SUCCESS)
2979	return rc;
2980
2981	if (TRPMHasTrap(pVCpu))
2982	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2983	else if (!pVCpu->hm.s.Event.fPending)
2984	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
2985
2986	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
2987	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2988	#endif
2989
2990	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
2991	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
2992	AssertRCReturn(rc, rc);
2993	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
2994
2995	/*
2996	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
2997	* so we can update it on the way back if the guest changed the TPR.
2998	*/
2999	if (pVCpu->hm.s.svm.fSyncVTpr)
3000	{
3001	if (pVM->hm.s.fTPRPatchingActive)
3002	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
3003	else
3004	{
3005	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3006	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
3007	}
3008	}
3009
3010	/*
3011	* No longjmps to ring-3 from this point on!!!
3012	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3013	* This also disables flushing of the R0-logger instance (if any).
3014	*/
3015	VMMRZCallRing3Disable(pVCpu);
3016
3017	/*
3018	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3019	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3020	*
3021	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3022	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3023	*
3024	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3025	* executing guest code.
3026	*/
3027	pSvmTransient->uEflags = ASMIntDisableFlags();
3028	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3029	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3030	{
3031	ASMSetFlags(pSvmTransient->uEflags);
3032	VMMRZCallRing3Enable(pVCpu);
3033	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3034	return VINF_EM_RAW_TO_R3;
3035	}
3036	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3037	{
3038	ASMSetFlags(pSvmTransient->uEflags);
3039	VMMRZCallRing3Enable(pVCpu);
3040	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3041	return VINF_EM_RAW_INTERRUPT;
3042	}
3043
3044	/*
3045	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3046	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3047	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3048	*
3049	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3050	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3051	*/
3052	if (pVCpu->hm.s.Event.fPending)
3053	{
3054	SVMEVENT Event;
3055	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3056	if ( Event.n.u1Valid
3057	&& Event.n.u3Type == SVM_EVENT_NMI
3058	&& Event.n.u8Vector == X86_XCPT_NMI
3059	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3060	{
3061	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3062	}
3063	}
3064
3065	return VINF_SUCCESS;
3066	}
3067
3068
3069	/**
3070	* Prepares to run guest code in AMD-V and we've committed to doing so. This
3071	* means there is no backing out to ring-3 or anywhere else at this
3072	* point.
3073	*
3074	* @param pVM Pointer to the VM.
3075	* @param pVCpu Pointer to the VMCPU.
3076	* @param pCtx Pointer to the guest-CPU context.
3077	* @param pSvmTransient Pointer to the SVM transient structure.
3078	*
3079	* @remarks Called with preemption disabled.
3080	* @remarks No-long-jump zone!!!
3081	*/
3082	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3083	{
3084	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3085	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3086	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3087
3088	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3089	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3090
3091	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
3092
3093	if ( pVCpu->hm.s.fPreloadGuestFpu
3094	&& !CPUMIsGuestFPUStateActive(pVCpu))
3095	{
3096	CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
3097	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3098	}
3099
3100	/* Load the state shared between host and guest (FPU, debug). */
3101	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3102	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3103	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
3104	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3105	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
3106
3107	/* Setup TSC offsetting. */
3108	RTCPUID idCurrentCpu = HMR0GetCurrentCpu()->idCpu;
3109	if ( pSvmTransient->fUpdateTscOffsetting
3110	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
3111	{
3112	hmR0SvmUpdateTscOffsetting(pVM, pVCpu);
3113	pSvmTransient->fUpdateTscOffsetting = false;
3114	}
3115
3116	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
3117	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
3118	pVmcb->ctrl.u64VmcbCleanBits = 0;
3119
3120	/* Store status of the shared guest-host state at the time of VMRUN. */
3121	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3122	if (CPUMIsGuestInLongModeEx(pCtx))
3123	{
3124	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
3125	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
3126	}
3127	else
3128	#endif
3129	{
3130	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
3131	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
3132	}
3133	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
3134
3135	/* Flush the appropriate tagged-TLB entries. */
3136	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
3137	hmR0SvmFlushTaggedTlb(pVCpu);
3138	Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
3139
3140	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
3141
3142	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
3143	to start executing. */
3144
3145	/*
3146	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
3147	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
3148	*
3149	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
3150	*/
3151	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
3152	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
3153	{
3154	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
3155	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
3156	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
3157	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
3158	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
3159	pSvmTransient->fRestoreTscAuxMsr = true;
3160	}
3161	else
3162	{
3163	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
3164	pSvmTransient->fRestoreTscAuxMsr = false;
3165	}
3166
3167	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
3168	if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
3169	pVmcb->ctrl.u64VmcbCleanBits = 0;
3170	}
3171
3172
3173	/**
3174	* Wrapper for running the guest code in AMD-V.
3175	*
3176	* @returns VBox strict status code.
3177	* @param pVM Pointer to the VM.
3178	* @param pVCpu Pointer to the VMCPU.
3179	* @param pCtx Pointer to the guest-CPU context.
3180	*
3181	* @remarks No-long-jump zone!!!
3182	*/
3183	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3184	{
3185	/*
3186	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
3187	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
3188	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
3189	*/
3190	#ifdef VBOX_WITH_KERNEL_USING_XMM
3191	return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
3192	pVCpu->hm.s.svm.pfnVMRun);
3193	#else
3194	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
3195	#endif
3196	}
3197
3198
3199	/**
3200	* Performs some essential restoration of state after running guest code in
3201	* AMD-V.
3202	*
3203	* @param pVM Pointer to the VM.
3204	* @param pVCpu Pointer to the VMCPU.
3205	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
3206	* out-of-sync. Make sure to update the required fields
3207	* before using them.
3208	* @param pSvmTransient Pointer to the SVM transient structure.
3209	* @param rcVMRun Return code of VMRUN.
3210	*
3211	* @remarks Called with interrupts disabled.
3212	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
3213	* unconditionally when it is safe to do so.
3214	*/
3215	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
3216	{
3217	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3218
3219	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
3220	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
3221
3222	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3223	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
3224
3225	if (pSvmTransient->fRestoreTscAuxMsr)
3226	{
3227	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
3228	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
3229	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
3230	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
3231	}
3232
3233	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
3234	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
3235
3236	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
3237	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
3238	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3239
3240	Assert(!(ASMGetFlags() & X86_EFL_IF));
3241	ASMSetFlags(pSvmTransient->uEflags); /* Enable interrupts. */
3242	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
3243
3244	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
3245	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
3246	{
3247	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
3248	return;
3249	}
3250
3251	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
3252	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
3253	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
3254	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
3255
3256	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
3257
3258	if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
3259	{
3260	if (pVCpu->hm.s.svm.fSyncVTpr)
3261	{
3262	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
3263	if ( pVM->hm.s.fTPRPatchingActive
3264	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
3265	{
3266	int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
3267	AssertRC(rc);
3268	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3269	}
3270	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
3271	{
3272	int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
3273	AssertRC(rc);
3274	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3275	}
3276	}
3277	}
3278	}
3279
3280
3281	/**
3282	* Runs the guest code using AMD-V.
3283	*
3284	* @returns VBox status code.
3285	* @param pVM Pointer to the VM.
3286	* @param pVCpu Pointer to the VMCPU.
3287	*/
3288	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3289	{
3290	SVMTRANSIENT SvmTransient;
3291	SvmTransient.fUpdateTscOffsetting = true;
3292	uint32_t cLoops = 0;
3293	int rc = VERR_INTERNAL_ERROR_5;
3294
3295	for (;; cLoops++)
3296	{
3297	Assert(!HMR0SuspendPending());
3298	HMSVM_ASSERT_CPU_SAFE();
3299
3300	/* Preparatory work for running guest code, this may force us to return
3301	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3302	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3303	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3304	if (rc != VINF_SUCCESS)
3305	break;
3306
3307	/*
3308	* No longjmps to ring-3 from this point on!!!
3309	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3310	* This also disables flushing of the R0-logger instance (if any).
3311	*/
3312	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3313	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3314
3315	/* Restore any residual host-state and save any bits shared between host
3316	and guest into the guest-CPU state. Re-enables interrupts! */
3317	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3318
3319	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3320	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3321	{
3322	if (rc == VINF_SUCCESS)
3323	rc = VERR_SVM_INVALID_GUEST_STATE;
3324	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3325	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3326	break;
3327	}
3328
3329	/* Handle the #VMEXIT. */
3330	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3331	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3332	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb);
3333	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3334	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3335	if (rc != VINF_SUCCESS)
3336	break;
3337	if (cLoops > pVM->hm.s.cMaxResumeLoops)
3338	{
3339	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
3340	rc = VINF_EM_RAW_INTERRUPT;
3341	break;
3342	}
3343	}
3344
3345	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3346	return rc;
3347	}
3348
3349
3350	/**
3351	* Runs the guest code using AMD-V in single step mode.
3352	*
3353	* @returns VBox status code.
3354	* @param pVM Pointer to the VM.
3355	* @param pVCpu Pointer to the VMCPU.
3356	* @param pCtx Pointer to the guest-CPU context.
3357	*/
3358	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3359	{
3360	SVMTRANSIENT SvmTransient;
3361	SvmTransient.fUpdateTscOffsetting = true;
3362	uint32_t cLoops = 0;
3363	int rc = VERR_INTERNAL_ERROR_5;
3364	uint16_t uCsStart = pCtx->cs.Sel;
3365	uint64_t uRipStart = pCtx->rip;
3366
3367	for (;; cLoops++)
3368	{
3369	Assert(!HMR0SuspendPending());
3370	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
3371	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
3372	(unsigned)RTMpCpuId(), cLoops));
3373
3374	/* Preparatory work for running guest code, this may force us to return
3375	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3376	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3377	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3378	if (rc != VINF_SUCCESS)
3379	break;
3380
3381	/*
3382	* No longjmps to ring-3 from this point on!!!
3383	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3384	* This also disables flushing of the R0-logger instance (if any).
3385	*/
3386	VMMRZCallRing3Disable(pVCpu);
3387	VMMRZCallRing3RemoveNotification(pVCpu);
3388	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3389
3390	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3391
3392	/*
3393	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
3394	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
3395	*/
3396	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3397	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3398	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3399	{
3400	if (rc == VINF_SUCCESS)
3401	rc = VERR_SVM_INVALID_GUEST_STATE;
3402	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3403	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3404	return rc;
3405	}
3406
3407	/* Handle the #VMEXIT. */
3408	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3409	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3410	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb);
3411	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3412	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3413	if (rc != VINF_SUCCESS)
3414	break;
3415	if (cLoops > pVM->hm.s.cMaxResumeLoops)
3416	{
3417	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
3418	rc = VINF_EM_RAW_INTERRUPT;
3419	break;
3420	}
3421
3422	/*
3423	* Did the RIP change, if so, consider it a single step.
3424	* Otherwise, make sure one of the TFs gets set.
3425	*/
3426	if ( pCtx->rip != uRipStart
3427	\|\| pCtx->cs.Sel != uCsStart)
3428	{
3429	rc = VINF_EM_DBG_STEPPED;
3430	break;
3431	}
3432	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
3433	}
3434
3435	/*
3436	* Clear the X86_EFL_TF if necessary.
3437	*/
3438	if (pVCpu->hm.s.fClearTrapFlag)
3439	{
3440	pVCpu->hm.s.fClearTrapFlag = false;
3441	pCtx->eflags.Bits.u1TF = 0;
3442	}
3443
3444	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3445	return rc;
3446	}
3447
3448
3449	/**
3450	* Runs the guest code using AMD-V.
3451	*
3452	* @returns VBox status code.
3453	* @param pVM Pointer to the VM.
3454	* @param pVCpu Pointer to the VMCPU.
3455	* @param pCtx Pointer to the guest-CPU context.
3456	*/
3457	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3458	{
3459	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3460	HMSVM_ASSERT_PREEMPT_SAFE();
3461	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
3462
3463	int rc;
3464	if (!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu))
3465	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx);
3466	else
3467	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx);
3468
3469	if (rc == VERR_EM_INTERPRETER)
3470	rc = VINF_EM_RAW_EMULATE_INSTR;
3471	else if (rc == VINF_EM_RESET)
3472	rc = VINF_EM_TRIPLE_FAULT;
3473
3474	/* Prepare to return to ring-3. This will remove longjmp notifications. */
3475	hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
3476	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
3477	return rc;
3478	}
3479
3480
3481	/**
3482	* Handles a #VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
3483	*
3484	* @returns VBox status code (informational status codes included).
3485	* @param pVCpu Pointer to the VMCPU.
3486	* @param pCtx Pointer to the guest-CPU context.
3487	* @param pSvmTransient Pointer to the SVM transient structure.
3488	*/
3489	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3490	{
3491	Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
3492	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
3493
3494	/*
3495	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
3496	* normal workloads (for some definition of "normal").
3497	*/
3498	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
3499	switch (pSvmTransient->u64ExitCode)
3500	{
3501	case SVM_EXIT_NPF:
3502	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
3503
3504	case SVM_EXIT_IOIO:
3505	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
3506
3507	case SVM_EXIT_RDTSC:
3508	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
3509
3510	case SVM_EXIT_RDTSCP:
3511	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
3512
3513	case SVM_EXIT_CPUID:
3514	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
3515
3516	case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
3517	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
3518
3519	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
3520	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
3521
3522	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3523	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
3524
3525	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
3526	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
3527
3528	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
3529	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
3530
3531	case SVM_EXIT_MONITOR:
3532	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
3533
3534	case SVM_EXIT_MWAIT:
3535	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
3536
3537	case SVM_EXIT_HLT:
3538	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
3539
3540	case SVM_EXIT_READ_CR0:
3541	case SVM_EXIT_READ_CR3:
3542	case SVM_EXIT_READ_CR4:
3543	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
3544
3545	case SVM_EXIT_WRITE_CR0:
3546	case SVM_EXIT_WRITE_CR3:
3547	case SVM_EXIT_WRITE_CR4:
3548	case SVM_EXIT_WRITE_CR8:
3549	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
3550
3551	case SVM_EXIT_VMMCALL:
3552	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
3553
3554	case SVM_EXIT_VINTR:
3555	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
3556
3557	case SVM_EXIT_INTR:
3558	case SVM_EXIT_FERR_FREEZE:
3559	case SVM_EXIT_NMI:
3560	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
3561
3562	case SVM_EXIT_MSR:
3563	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
3564
3565	case SVM_EXIT_INVLPG:
3566	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
3567
3568	case SVM_EXIT_WBINVD:
3569	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
3570
3571	case SVM_EXIT_INVD:
3572	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
3573
3574	case SVM_EXIT_RDPMC:
3575	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
3576
3577	default:
3578	{
3579	switch (pSvmTransient->u64ExitCode)
3580	{
3581	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
3582	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
3583	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
3584	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
3585	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3586
3587	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
3588	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
3589	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
3590	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
3591	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
3592
3593	case SVM_EXIT_XSETBV:
3594	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
3595
3596	case SVM_EXIT_TASK_SWITCH:
3597	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
3598
3599	case SVM_EXIT_IRET:
3600	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
3601
3602	case SVM_EXIT_SHUTDOWN:
3603	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
3604
3605	case SVM_EXIT_SMI:
3606	case SVM_EXIT_INIT:
3607	{
3608	/*
3609	* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
3610	* we want to know about it so log the exit code and bail.
3611	*/
3612	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
3613	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
3614	return VERR_SVM_UNEXPECTED_EXIT;
3615	}
3616
3617	case SVM_EXIT_INVLPGA:
3618	case SVM_EXIT_RSM:
3619	case SVM_EXIT_VMRUN:
3620	case SVM_EXIT_VMLOAD:
3621	case SVM_EXIT_VMSAVE:
3622	case SVM_EXIT_STGI:
3623	case SVM_EXIT_CLGI:
3624	case SVM_EXIT_SKINIT:
3625	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
3626
3627	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
3628	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
3629	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
3630	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
3631	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
3632	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
3633	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
3634	/* case SVM_EXIT_EXCEPTION_6: / / X86_XCPT_UD - Handled above. */
3635	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
3636	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3637	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3638	case SVM_EXIT_EXCEPTION_A: /* X86_XCPT_TS */
3639	case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
3640	case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
3641	case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
3642	/* SVM_EXIT_EXCEPTION_E: / / X86_XCPT_PF - Handled above. */
3643	/* SVM_EXIT_EXCEPTION_10: / / X86_XCPT_MF - Handled above. */
3644	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_AC */
3645	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC */
3646	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_XF */
3647	case SVM_EXIT_EXCEPTION_F: /* Reserved */
3648	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:
3649	case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
3650	case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:
3651	case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
3652	{
3653	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3654	SVMEVENT Event;
3655	Event.u = 0;
3656	Event.n.u1Valid = 1;
3657	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3658	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3659
3660	switch (Event.n.u8Vector)
3661	{
3662	case X86_XCPT_DE:
3663	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3664	break;
3665
3666	case X86_XCPT_BP:
3667	/** Saves the wrong EIP on the stack (pointing to the int3) instead of the
3668	* next instruction. */
3669	/** @todo Investigate this later. */
3670	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
3671	break;
3672
3673	case X86_XCPT_NP:
3674	Event.n.u1ErrorCodeValid = 1;
3675	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3676	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3677	break;
3678
3679	case X86_XCPT_SS:
3680	Event.n.u1ErrorCodeValid = 1;
3681	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3682	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3683	break;
3684
3685	case X86_XCPT_GP:
3686	Event.n.u1ErrorCodeValid = 1;
3687	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3688	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3689	break;
3690
3691	default:
3692	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3693	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3694	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3695	}
3696
3697	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3698	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3699	return VINF_SUCCESS;
3700	}
3701	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3702
3703	default:
3704	{
3705	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3706	pVCpu->hm.s.u32HMError = u32ExitCode;
3707	return VERR_SVM_UNKNOWN_EXIT;
3708	}
3709	}
3710	}
3711	}
3712	return VERR_INTERNAL_ERROR_5; /* Should never happen. */
3713	}
3714
3715
3716	#ifdef DEBUG
3717	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3718	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3719	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3720
3721	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3722	do \
3723	{ \
3724	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3725	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3726	} while (0)
3727
3728	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3729	do { \
3730	AssertPtr(pVCpu); \
3731	AssertPtr(pCtx); \
3732	AssertPtr(pSvmTransient); \
3733	Assert(ASMIntAreEnabled()); \
3734	HMSVM_ASSERT_PREEMPT_SAFE(); \
3735	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3736	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3737	HMSVM_ASSERT_PREEMPT_SAFE(); \
3738	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3739	HMSVM_ASSERT_PREEMPT_CPUID(); \
3740	} while (0)
3741	#else /* Release builds */
3742	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
3743	#endif
3744
3745
3746	/**
3747	* Worker for hmR0SvmInterpretInvlpg().
3748	*
3749	* @return VBox status code.
3750	* @param pVCpu Pointer to the VMCPU.
3751	* @param pCpu Pointer to the disassembler state.
3752	* @param pCtx The guest CPU context.
3753	*/
3754	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
3755	{
3756	DISQPVPARAMVAL Param1;
3757	RTGCPTR GCPtrPage;
3758
3759	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3760	if (RT_FAILURE(rc))
3761	return VERR_EM_INTERPRETER;
3762
3763	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3764	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3765	{
3766	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3767	return VERR_EM_INTERPRETER;
3768
3769	GCPtrPage = Param1.val.val64;
3770	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
3771	rc = VBOXSTRICTRC_VAL(rc2);
3772	}
3773	else
3774	{
3775	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3776	rc = VERR_EM_INTERPRETER;
3777	}
3778
3779	return rc;
3780	}
3781
3782
3783	/**
3784	* Interprets INVLPG.
3785	*
3786	* @returns VBox status code.
3787	* @retval VINF_* Scheduling instructions.
3788	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3789	* @retval VERR_* Fatal errors.
3790	*
3791	* @param pVM Pointer to the VM.
3792	* @param pCtx The guest CPU context.
3793	*
3794	* @remarks Updates the RIP if the instruction was executed successfully.
3795	*/
3796	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3797	{
3798	/* Only allow 32 & 64 bit code. */
3799	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3800	{
3801	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3802	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3803	if ( RT_SUCCESS(rc)
3804	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3805	{
3806	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
3807	if (RT_SUCCESS(rc))
3808	pCtx->rip += pDis->cbInstr;
3809	return rc;
3810	}
3811	else
3812	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3813	}
3814	return VERR_EM_INTERPRETER;
3815	}
3816
3817
3818	/**
3819	* Sets an invalid-opcode (#UD) exception as pending-for-injection into the VM.
3820	*
3821	* @param pVCpu Pointer to the VMCPU.
3822	*/
3823	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3824	{
3825	SVMEVENT Event;
3826	Event.u = 0;
3827	Event.n.u1Valid = 1;
3828	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3829	Event.n.u8Vector = X86_XCPT_UD;
3830	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3831	}
3832
3833
3834	/**
3835	* Sets a debug (#DB) exception as pending-for-injection into the VM.
3836	*
3837	* @param pVCpu Pointer to the VMCPU.
3838	*/
3839	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3840	{
3841	SVMEVENT Event;
3842	Event.u = 0;
3843	Event.n.u1Valid = 1;
3844	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3845	Event.n.u8Vector = X86_XCPT_DB;
3846	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3847	}
3848
3849
3850	/**
3851	* Sets a page fault (#PF) exception as pending-for-injection into the VM.
3852	*
3853	* @param pVCpu Pointer to the VMCPU.
3854	* @param pCtx Pointer to the guest-CPU context.
3855	* @param u32ErrCode The error-code for the page-fault.
3856	* @param uFaultAddress The page fault address (CR2).
3857	*
3858	* @remarks This updates the guest CR2 with @a uFaultAddress!
3859	*/
3860	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3861	{
3862	SVMEVENT Event;
3863	Event.u = 0;
3864	Event.n.u1Valid = 1;
3865	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3866	Event.n.u8Vector = X86_XCPT_PF;
3867	Event.n.u1ErrorCodeValid = 1;
3868	Event.n.u32ErrorCode = u32ErrCode;
3869
3870	/* Update CR2 of the guest. */
3871	if (pCtx->cr2 != uFaultAddress)
3872	{
3873	pCtx->cr2 = uFaultAddress;
3874	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
3875	}
3876
3877	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3878	}
3879
3880
3881	/**
3882	* Sets a device-not-available (#NM) exception as pending-for-injection into the
3883	* VM.
3884	*
3885	* @param pVCpu Pointer to the VMCPU.
3886	*/
3887	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3888	{
3889	SVMEVENT Event;
3890	Event.u = 0;
3891	Event.n.u1Valid = 1;
3892	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3893	Event.n.u8Vector = X86_XCPT_NM;
3894	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3895	}
3896
3897
3898	/**
3899	* Sets a math-fault (#MF) exception as pending-for-injection into the VM.
3900	*
3901	* @param pVCpu Pointer to the VMCPU.
3902	*/
3903	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3904	{
3905	SVMEVENT Event;
3906	Event.u = 0;
3907	Event.n.u1Valid = 1;
3908	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3909	Event.n.u8Vector = X86_XCPT_MF;
3910	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3911	}
3912
3913
3914	/**
3915	* Sets a double fault (#DF) exception as pending-for-injection into the VM.
3916	*
3917	* @param pVCpu Pointer to the VMCPU.
3918	*/
3919	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3920	{
3921	SVMEVENT Event;
3922	Event.u = 0;
3923	Event.n.u1Valid = 1;
3924	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3925	Event.n.u8Vector = X86_XCPT_DF;
3926	Event.n.u1ErrorCodeValid = 1;
3927	Event.n.u32ErrorCode = 0;
3928	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3929	}
3930
3931
3932	/**
3933	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3934	* guests. This simply looks up the patch record at EIP and does the required.
3935	*
3936	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3937	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
3938	* TPR). See hmR3ReplaceTprInstr() for the details.
3939	*
3940	* @returns VBox status code.
3941	* @retval VINF_SUCCESS if the access was handled successfully.
3942	* @retval VERR_NOT_FOUND if no patch record for this RIP could be found.
3943	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
3944	*
3945	* @param pVM Pointer to the VM.
3946	* @param pVCpu Pointer to the VMCPU.
3947	* @param pCtx Pointer to the guest-CPU context.
3948	*/
3949	static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3950	{
3951	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3952
3953	/*
3954	* We do this in a loop as we increment the RIP after a successful emulation
3955	* and the new RIP may be a patched instruction which needs emulation as well.
3956	*/
3957	bool fPatchFound = false;
3958	for (;;)
3959	{
3960	bool fPending;
3961	uint8_t u8Tpr;
3962
3963	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
3964	if (!pPatch)
3965	break;
3966
3967	fPatchFound = true;
3968	switch (pPatch->enmType)
3969	{
3970	case HMTPRINSTR_READ:
3971	{
3972	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
3973	AssertRC(rc);
3974
3975	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
3976	AssertRC(rc);
3977	pCtx->rip += pPatch->cbOp;
3978	break;
3979	}
3980
3981	case HMTPRINSTR_WRITE_REG:
3982	case HMTPRINSTR_WRITE_IMM:
3983	{
3984	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
3985	{
3986	uint32_t u32Val;
3987	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
3988	AssertRC(rc);
3989	u8Tpr = u32Val;
3990	}
3991	else
3992	u8Tpr = (uint8_t)pPatch->uSrcOperand;
3993
3994	int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
3995	AssertRC(rc2);
3996	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3997
3998	pCtx->rip += pPatch->cbOp;
3999	break;
4000	}
4001
4002	default:
4003	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
4004	pVCpu->hm.s.u32HMError = pPatch->enmType;
4005	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
4006	}
4007	}
4008
4009	if (fPatchFound)
4010	return VINF_SUCCESS;
4011	return VERR_NOT_FOUND;
4012	}
4013
4014
4015	/**
4016	* Determines if an exception is a contributory exception.
4017	*
4018	* Contributory exceptions are ones which can cause double-faults unless the
4019	* original exception was a benign exception. Page-fault is intentionally not
4020	* included here as it's a conditional contributory exception.
4021	*
4022	* @returns true if the exception is contributory, false otherwise.
4023	* @param uVector The exception vector.
4024	*/
4025	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
4026	{
4027	switch (uVector)
4028	{
4029	case X86_XCPT_GP:
4030	case X86_XCPT_SS:
4031	case X86_XCPT_NP:
4032	case X86_XCPT_TS:
4033	case X86_XCPT_DE:
4034	return true;
4035	default:
4036	break;
4037	}
4038	return false;
4039	}
4040
4041
4042	/**
4043	* Handle a condition that occurred while delivering an event through the guest
4044	* IDT.
4045	*
4046	* @returns VBox status code (informational error codes included).
4047	* @retval VINF_SUCCESS if we should continue handling the #VMEXIT.
4048	* @retval VINF_HM_DOUBLE_FAULT if a #DF condition was detected and we ought to
4049	* continue execution of the guest which will delivery the #DF.
4050	* @retval VINF_EM_RESET if we detected a triple-fault condition.
4051	*
4052	* @param pVCpu Pointer to the VMCPU.
4053	* @param pCtx Pointer to the guest-CPU context.
4054	* @param pSvmTransient Pointer to the SVM transient structure.
4055	*
4056	* @remarks No-long-jump zone!!!
4057	*/
4058	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4059	{
4060	int rc = VINF_SUCCESS;
4061	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4062
4063	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
4064	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
4065	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
4066	{
4067	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
4068
4069	typedef enum
4070	{
4071	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
4072	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
4073	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
4074	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
4075	} SVMREFLECTXCPT;
4076
4077	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
4078	bool fReflectingNmi = false;
4079	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
4080	{
4081	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
4082	{
4083	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4084
4085	#ifdef VBOX_STRICT
4086	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
4087	&& uExitVector == X86_XCPT_PF)
4088	{
4089	Log4(("IDT: Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
4090	}
4091	#endif
4092	if ( uExitVector == X86_XCPT_PF
4093	&& uIdtVector == X86_XCPT_PF)
4094	{
4095	pSvmTransient->fVectoringDoublePF = true;
4096	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
4097	}
4098	else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
4099	&& hmR0SvmIsContributoryXcpt(uExitVector)
4100	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
4101	\|\| uIdtVector == X86_XCPT_PF))
4102	{
4103	enmReflect = SVMREFLECTXCPT_DF;
4104	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
4105	uIdtVector, uExitVector));
4106	}
4107	else if (uIdtVector == X86_XCPT_DF)
4108	{
4109	enmReflect = SVMREFLECTXCPT_TF;
4110	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
4111	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
4112	}
4113	else
4114	enmReflect = SVMREFLECTXCPT_XCPT;
4115	}
4116	else
4117	{
4118	/*
4119	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
4120	* exception to the guest after handling the #VMEXIT.
4121	*/
4122	enmReflect = SVMREFLECTXCPT_XCPT;
4123	}
4124	}
4125	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
4126	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
4127	{
4128	enmReflect = SVMREFLECTXCPT_XCPT;
4129	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
4130
4131	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
4132	{
4133	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4134	if (uExitVector == X86_XCPT_PF)
4135	{
4136	pSvmTransient->fVectoringPF = true;
4137	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
4138	}
4139	}
4140	}
4141	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
4142
4143	switch (enmReflect)
4144	{
4145	case SVMREFLECTXCPT_XCPT:
4146	{
4147	/* If we are re-injecting the NMI, clear NMI blocking. */
4148	if (fReflectingNmi)
4149	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
4150
4151	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
4152	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
4153
4154	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
4155	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
4156	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
4157	break;
4158	}
4159
4160	case SVMREFLECTXCPT_DF:
4161	{
4162	hmR0SvmSetPendingXcptDF(pVCpu);
4163	rc = VINF_HM_DOUBLE_FAULT;
4164	break;
4165	}
4166
4167	case SVMREFLECTXCPT_TF:
4168	{
4169	rc = VINF_EM_RESET;
4170	break;
4171	}
4172
4173	default:
4174	Assert(rc == VINF_SUCCESS);
4175	break;
4176	}
4177	}
4178	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET);
4179	NOREF(pCtx);
4180	return rc;
4181	}
4182
4183
4184	/**
4185	* Advances the guest RIP in the if the NRIP_SAVE feature is supported by the
4186	* CPU, otherwise advances the RIP by @a cb bytes.
4187	*
4188	* @param pVCpu Pointer to the VMCPU.
4189	* @param pCtx Pointer to the guest-CPU context.
4190	* @param cb RIP increment value in bytes.
4191	*
4192	* @remarks Use this function only from #VMEXIT's where the NRIP value is valid
4193	* when NRIP_SAVE is supported by the CPU!
4194	*/
4195	DECLINLINE(void) hmR0SvmUpdateRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
4196	{
4197	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4198	{
4199	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4200	Assert(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb);
4201	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4202	}
4203	else
4204	pCtx->rip += cb;
4205	}
4206
4207
4208	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4209	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
4210	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4211
4212	/** @name #VMEXIT handlers.
4213	* @{
4214	*/
4215
4216	/**
4217	* #VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
4218	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
4219	*/
4220	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4221	{
4222	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4223
4224	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
4225	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
4226	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
4227	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
4228
4229	/*
4230	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
4231	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
4232	* interrupt it is until the host actually take the interrupt.
4233	*
4234	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
4235	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
4236	*/
4237	return VINF_EM_RAW_INTERRUPT;
4238	}
4239
4240
4241	/**
4242	* #VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional #VMEXIT.
4243	*/
4244	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4245	{
4246	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4247
4248	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4249	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
4250	int rc = VINF_SUCCESS;
4251	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4252	return rc;
4253	}
4254
4255
4256	/**
4257	* #VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional #VMEXIT.
4258	*/
4259	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4260	{
4261	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4262
4263	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4264	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
4265	int rc = VINF_SUCCESS;
4266	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4267	return rc;
4268	}
4269
4270
4271	/**
4272	* #VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional #VMEXIT.
4273	*/
4274	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4275	{
4276	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4277	PVM pVM = pVCpu->CTX_SUFF(pVM);
4278	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4279	if (RT_LIKELY(rc == VINF_SUCCESS))
4280	{
4281	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4282	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4283	}
4284	else
4285	{
4286	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
4287	rc = VERR_EM_INTERPRETER;
4288	}
4289	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
4290	return rc;
4291	}
4292
4293
4294	/**
4295	* #VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional #VMEXIT.
4296	*/
4297	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4298	{
4299	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4300	PVM pVM = pVCpu->CTX_SUFF(pVM);
4301	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4302	if (RT_LIKELY(rc == VINF_SUCCESS))
4303	{
4304	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4305	pSvmTransient->fUpdateTscOffsetting = true;
4306
4307	/* Single step check. */
4308	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4309	}
4310	else
4311	{
4312	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
4313	rc = VERR_EM_INTERPRETER;
4314	}
4315	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
4316	return rc;
4317	}
4318
4319
4320	/**
4321	* #VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional #VMEXIT.
4322	*/
4323	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4324	{
4325	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4326	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4327	if (RT_LIKELY(rc == VINF_SUCCESS))
4328	{
4329	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
4330	pSvmTransient->fUpdateTscOffsetting = true;
4331	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4332	}
4333	else
4334	{
4335	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
4336	rc = VERR_EM_INTERPRETER;
4337	}
4338	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
4339	return rc;
4340	}
4341
4342
4343	/**
4344	* #VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional #VMEXIT.
4345	*/
4346	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4347	{
4348	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4349	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4350	if (RT_LIKELY(rc == VINF_SUCCESS))
4351	{
4352	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4353	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4354	}
4355	else
4356	{
4357	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
4358	rc = VERR_EM_INTERPRETER;
4359	}
4360	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
4361	return rc;
4362	}
4363
4364
4365	/**
4366	* #VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional #VMEXIT.
4367	*/
4368	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4369	{
4370	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4371	PVM pVM = pVCpu->CTX_SUFF(pVM);
4372	Assert(!pVM->hm.s.fNestedPaging);
4373
4374	/** @todo Decode Assist. */
4375	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
4376	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
4377	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
4378	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4379	return rc;
4380	}
4381
4382
4383	/**
4384	* #VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional #VMEXIT.
4385	*/
4386	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4387	{
4388	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4389
4390	hmR0SvmUpdateRip(pVCpu, pCtx, 1);
4391	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
4392	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4393	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
4394	if (rc != VINF_SUCCESS)
4395	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
4396	return rc;
4397	}
4398
4399
4400	/**
4401	* #VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional #VMEXIT.
4402	*/
4403	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4404	{
4405	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4406	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4407	if (RT_LIKELY(rc == VINF_SUCCESS))
4408	{
4409	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
4410	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4411	}
4412	else
4413	{
4414	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
4415	rc = VERR_EM_INTERPRETER;
4416	}
4417	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
4418	return rc;
4419	}
4420
4421
4422	/**
4423	* #VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional #VMEXIT.
4424	*/
4425	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4426	{
4427	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4428	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4429	int rc = VBOXSTRICTRC_VAL(rc2);
4430	if ( rc == VINF_EM_HALT
4431	\|\| rc == VINF_SUCCESS)
4432	{
4433	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
4434
4435	if ( rc == VINF_EM_HALT
4436	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
4437	{
4438	rc = VINF_SUCCESS;
4439	}
4440	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4441	}
4442	else
4443	{
4444	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
4445	rc = VERR_EM_INTERPRETER;
4446	}
4447	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
4448	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
4449	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
4450	return rc;
4451	}
4452
4453
4454	/**
4455	* #VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN).
4456	* Conditional #VMEXIT.
4457	*/
4458	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4459	{
4460	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4461	return VINF_EM_RESET;
4462	}
4463
4464
4465	/**
4466	* #VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional #VMEXIT.
4467	*/
4468	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4469	{
4470	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4471
4472	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4473
4474	/** @todo Decode Assist. */
4475	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4476	int rc = VBOXSTRICTRC_VAL(rc2);
4477	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
4478	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
4479	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
4480	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
4481	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4482	return rc;
4483	}
4484
4485
4486	/**
4487	* #VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional #VMEXIT.
4488	*/
4489	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4490	{
4491	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4492	/** @todo Decode Assist. */
4493	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4494	int rc = VBOXSTRICTRC_VAL(rc2);
4495	if (rc == VINF_SUCCESS)
4496	{
4497	/* RIP has been updated by EMInterpretInstruction(). */
4498	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
4499	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
4500	{
4501	case 0: /* CR0. */
4502	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4503	break;
4504
4505	case 3: /* CR3. */
4506	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4507	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
4508	break;
4509
4510	case 4: /* CR4. */
4511	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
4512	break;
4513
4514	case 8: /* CR8 (TPR). */
4515	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4516	break;
4517
4518	default:
4519	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x CRx=%#RX64\n",
4520	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
4521	break;
4522	}
4523	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4524	}
4525	else
4526	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
4527	return rc;
4528	}
4529
4530
4531	/**
4532	* #VMEXIT handler for instructions that result in a #UD exception delivered to
4533	* the guest.
4534	*/
4535	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4536	{
4537	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4538	hmR0SvmSetPendingXcptUD(pVCpu);
4539	return VINF_SUCCESS;
4540	}
4541
4542
4543	/**
4544	* #VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional #VMEXIT.
4545	*/
4546	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4547	{
4548	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4549	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4550	PVM pVM = pVCpu->CTX_SUFF(pVM);
4551
4552	int rc;
4553	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4554	{
4555	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
4556
4557	/* Handle TPR patching; intercepted LSTAR write. */
4558	if ( pVM->hm.s.fTPRPatchingActive
4559	&& pCtx->ecx == MSR_K8_LSTAR)
4560	{
4561	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
4562	{
4563	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
4564	int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
4565	AssertRC(rc2);
4566	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4567	}
4568	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4569	rc = VINF_SUCCESS;
4570	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4571	return rc;
4572	}
4573
4574	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4575	{
4576	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4577	if (RT_LIKELY(rc == VINF_SUCCESS))
4578	{
4579	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4580	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4581	}
4582	else
4583	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
4584	}
4585	else
4586	{
4587	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
4588	if (RT_LIKELY(rc == VINF_SUCCESS))
4589	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
4590	else
4591	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4592	}
4593
4594	if (rc == VINF_SUCCESS)
4595	{
4596	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
4597	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
4598	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
4599	{
4600	/*
4601	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
4602	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
4603	* EMInterpretWrmsr() changes it.
4604	*/
4605	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4606	}
4607	else if (pCtx->ecx == MSR_K6_EFER)
4608	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
4609	else if (pCtx->ecx == MSR_IA32_TSC)
4610	pSvmTransient->fUpdateTscOffsetting = true;
4611	}
4612	}
4613	else
4614	{
4615	/* MSR Read access. */
4616	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
4617	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
4618
4619	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4620	{
4621	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4622	if (RT_LIKELY(rc == VINF_SUCCESS))
4623	{
4624	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4625	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4626	}
4627	else
4628	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
4629	}
4630	else
4631	{
4632	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
4633	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4634	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4635	/* RIP updated by EMInterpretInstruction(). */
4636	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4637	}
4638	}
4639
4640	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
4641	return rc;
4642	}
4643
4644
4645	/**
4646	* #VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional #VMEXIT.
4647	*/
4648	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4649	{
4650	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4651	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
4652
4653	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
4654	if (pSvmTransient->fWasGuestDebugStateActive)
4655	{
4656	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
4657	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
4658	return VERR_SVM_UNEXPECTED_EXIT;
4659	}
4660
4661	/*
4662	* Lazy DR0-3 loading.
4663	*/
4664	if (!pSvmTransient->fWasHyperDebugStateActive)
4665	{
4666	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
4667	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
4668
4669	/* Don't intercept DRx read and writes. */
4670	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4671	pVmcb->ctrl.u16InterceptRdDRx = 0;
4672	pVmcb->ctrl.u16InterceptWrDRx = 0;
4673	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
4674
4675	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4676	VMMRZCallRing3Disable(pVCpu);
4677	HM_DISABLE_PREEMPT();
4678
4679	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
4680	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
4681	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
4682
4683	HM_RESTORE_PREEMPT();
4684	VMMRZCallRing3Enable(pVCpu);
4685
4686	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
4687	return VINF_SUCCESS;
4688	}
4689
4690	/*
4691	* Interpret the read/writing of DRx.
4692	*/
4693	/** @todo Decode assist. */
4694	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4695	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
4696	if (RT_LIKELY(rc == VINF_SUCCESS))
4697	{
4698	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
4699	/** @todo CPUM should set this flag! */
4700	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
4701	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4702	}
4703	else
4704	Assert(rc == VERR_EM_INTERPRETER);
4705	return VBOXSTRICTRC_TODO(rc);
4706	}
4707
4708
4709	/**
4710	* #VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional #VMEXIT.
4711	*/
4712	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4713	{
4714	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4715	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
4716	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4717	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
4718	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
4719	return rc;
4720	}
4721
4722
4723	/**
4724	* #VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional #VMEXIT.
4725	*/
4726	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4727	{
4728	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4729
4730	/** @todo decode assists... */
4731	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
4732	if (rcStrict == VINF_IEM_RAISED_XCPT)
4733	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4734
4735	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
4736
4737	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4738	return VBOXSTRICTRC_TODO(rcStrict);
4739	}
4740
4741
4742	/**
4743	* #VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional #VMEXIT.
4744	*/
4745	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4746	{
4747	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4748
4749	/* I/O operation lookup arrays. */
4750	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
4751	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
4752	the result (in AL/AX/EAX). */
4753	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4754
4755	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4756	PVM pVM = pVCpu->CTX_SUFF(pVM);
4757
4758	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
4759	SVMIOIOEXIT IoExitInfo;
4760	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
4761	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
4762	uint32_t cbValue = s_aIOSize[uIOWidth];
4763	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
4764
4765	if (RT_UNLIKELY(!cbValue))
4766	{
4767	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
4768	return VERR_EM_INTERPRETER;
4769	}
4770
4771	VBOXSTRICTRC rcStrict;
4772	if (IoExitInfo.n.u1STR)
4773	{
4774	/* INS/OUTS - I/O String instruction. */
4775	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
4776
4777	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
4778	* in EXITINFO1? Investigate once this thing is up and running. */
4779
4780	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
4781	if (rcStrict == VINF_SUCCESS)
4782	{
4783	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4784	{
4785	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4786	(DISCPUMODE)pDis->uAddrMode, cbValue);
4787	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4788	}
4789	else
4790	{
4791	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4792	(DISCPUMODE)pDis->uAddrMode, cbValue);
4793	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4794	}
4795	}
4796	else
4797	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
4798	}
4799	else
4800	{
4801	/* IN/OUT - I/O instruction. */
4802	Assert(!IoExitInfo.n.u1REP);
4803
4804	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4805	{
4806	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
4807	if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4808	HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4809
4810	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
4811	}
4812	else
4813	{
4814	uint32_t u32Val = 0;
4815
4816	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
4817	if (IOM_SUCCESS(rcStrict))
4818	{
4819	/* Save result of I/O IN instr. in AL/AX/EAX. */
4820	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
4821	}
4822	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4823	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4824
4825	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
4826	}
4827	}
4828
4829	if (IOM_SUCCESS(rcStrict))
4830	{
4831	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
4832	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
4833
4834	/*
4835	* If any I/O breakpoints are armed, we need to check if one triggered
4836	* and take appropriate action.
4837	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
4838	*/
4839	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
4840	* execution engines about whether hyper BPs and such are pending. */
4841	uint32_t const uDr7 = pCtx->dr[7];
4842	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
4843	&& X86_DR7_ANY_RW_IO(uDr7)
4844	&& (pCtx->cr4 & X86_CR4_DE))
4845	\|\| DBGFBpIsHwIoArmed(pVM)))
4846	{
4847	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4848	VMMRZCallRing3Disable(pVCpu);
4849	HM_DISABLE_PREEMPT();
4850
4851	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
4852	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
4853
4854	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
4855	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
4856	{
4857	/* Raise #DB. */
4858	pVmcb->guest.u64DR6 = pCtx->dr[6];
4859	pVmcb->guest.u64DR7 = pCtx->dr[7];
4860	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4861	hmR0SvmSetPendingXcptDB(pVCpu);
4862	}
4863	/* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
4864	else if ( rcStrict2 != VINF_SUCCESS
4865	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
4866	rcStrict = rcStrict2;
4867
4868	HM_RESTORE_PREEMPT();
4869	VMMRZCallRing3Enable(pVCpu);
4870	}
4871
4872	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4873	}
4874
4875	#ifdef VBOX_STRICT
4876	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4877	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
4878	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4879	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
4880	else
4881	{
4882	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
4883	* statuses, that the VMM device and some others may return. See
4884	* IOM_SUCCESS() for guidance. */
4885	AssertMsg( RT_FAILURE(rcStrict)
4886	\|\| rcStrict == VINF_SUCCESS
4887	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
4888	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
4889	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
4890	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
4891	}
4892	#endif
4893	return VBOXSTRICTRC_TODO(rcStrict);
4894	}
4895
4896
4897	/**
4898	* #VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional
4899	* #VMEXIT.
4900	*/
4901	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4902	{
4903	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4904	PVM pVM = pVCpu->CTX_SUFF(pVM);
4905	Assert(pVM->hm.s.fNestedPaging);
4906
4907	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4908
4909	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
4910	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4911	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4912	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
4913
4914	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
4915
4916	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4917	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
4918	if ( pVM->hm.s.fTprPatchingAllowed
4919	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80 /* TPR offset. */
4920	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
4921	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
4922	&& !CPUMIsGuestInLongModeEx(pCtx)
4923	&& !CPUMGetGuestCPL(pVCpu)
4924	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4925	{
4926	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
4927	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4928
4929	if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
4930	{
4931	/* Only attempt to patch the instruction once. */
4932	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4933	if (!pPatch)
4934	return VINF_EM_HM_PATCH_TPR_INSTR;
4935	}
4936	}
4937	#endif
4938
4939	/*
4940	* Determine the nested paging mode.
4941	*/
4942	PGMMODE enmNestedPagingMode;
4943	#if HC_ARCH_BITS == 32
4944	if (CPUMIsGuestInLongModeEx(pCtx))
4945	enmNestedPagingMode = PGMMODE_AMD64_NX;
4946	else
4947	#endif
4948	enmNestedPagingMode = PGMGetHostMode(pVM);
4949
4950	/*
4951	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
4952	*/
4953	int rc;
4954	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
4955	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
4956	{
4957	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
4958	u32ErrCode);
4959	rc = VBOXSTRICTRC_VAL(rc2);
4960
4961	/*
4962	* If we succeed, resume guest execution.
4963	* If we fail in interpreting the instruction because we couldn't get the guest physical address
4964	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
4965	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
4966	* weird case. See @bugref{6043}.
4967	*/
4968	if ( rc == VINF_SUCCESS
4969	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4970	\|\| rc == VERR_PAGE_NOT_PRESENT)
4971	{
4972	/* Successfully handled MMIO operation. */
4973	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4974	rc = VINF_SUCCESS;
4975	}
4976	return rc;
4977	}
4978
4979	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
4980	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
4981	TRPMResetTrap(pVCpu);
4982
4983	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
4984
4985	/*
4986	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
4987	*/
4988	if ( rc == VINF_SUCCESS
4989	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4990	\|\| rc == VERR_PAGE_NOT_PRESENT)
4991	{
4992	/* We've successfully synced our shadow page tables. */
4993	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4994	rc = VINF_SUCCESS;
4995	}
4996
4997	return rc;
4998	}
4999
5000
5001	/**
5002	* #VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional #VMEXIT.
5003	*/
5004	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5005	{
5006	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5007
5008	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5009	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one/NMI before reentry. */
5010	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
5011
5012	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive interrupts/NMIs, it is now ready. */
5013	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
5014	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
5015
5016	/* Deliver the pending interrupt/NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
5017	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
5018	return VINF_SUCCESS;
5019	}
5020
5021
5022	/**
5023	* #VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional #VMEXIT.
5024	*/
5025	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5026	{
5027	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5028
5029	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
5030	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5031	#endif
5032
5033	/* Check if this task-switch occurred while delivery an event through the guest IDT. */
5034	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5035	if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
5036	&& pVCpu->hm.s.Event.fPending) /** @todo fPending cannot be 'true', see hmR0SvmInjectPendingEvent(). See @bugref{7362}.*/
5037	{
5038	/*
5039	* AMD-V does not provide us with the original exception but we have it in u64IntInfo since we
5040	* injected the event during VM-entry.
5041	*/
5042	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
5043	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
5044	return VINF_EM_RAW_INJECT_TRPM_EVENT;
5045	}
5046
5047	/** @todo Emulate task switch someday, currently just going back to ring-3 for
5048	* emulation. */
5049	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
5050	return VERR_EM_INTERPRETER;
5051	}
5052
5053
5054	/**
5055	* #VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional #VMEXIT.
5056	*/
5057	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5058	{
5059	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5060	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
5061
5062	/* First check if this is a patched VMMCALL for mov TPR */
5063	int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
5064	if (rc == VINF_SUCCESS)
5065	{
5066	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5067	return VINF_SUCCESS;
5068	}
5069	else if (rc == VERR_NOT_FOUND)
5070	{
5071	if (pVCpu->hm.s.fHypercallsEnabled)
5072	{
5073	rc = GIMHypercall(pVCpu, pCtx);
5074	if (RT_SUCCESS(rc))
5075	{
5076	/* If the hypercall changes anything other than guest general-purpose registers,
5077	we would need to reload the guest changed bits here before VM-reentry. */
5078	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
5079	return VINF_SUCCESS;
5080	}
5081	}
5082	}
5083
5084	hmR0SvmSetPendingXcptUD(pVCpu);
5085	return VINF_SUCCESS;
5086	}
5087
5088
5089	/**
5090	* #VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional #VMEXIT.
5091	*/
5092	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5093	{
5094	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5095
5096	/* Clear NMI blocking. */
5097	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5098
5099	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
5100	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5101	hmR0SvmClearIretIntercept(pVmcb);
5102
5103	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
5104	return VINF_SUCCESS;
5105	}
5106
5107
5108	/**
5109	* #VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_E). Conditional
5110	* #VMEXIT.
5111	*/
5112	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5113	{
5114	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5115
5116	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5117
5118	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
5119	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5120	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
5121	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
5122	PVM pVM = pVCpu->CTX_SUFF(pVM);
5123
5124	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
5125	if (pVM->hm.s.fNestedPaging)
5126	{
5127	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5128	if (!pSvmTransient->fVectoringDoublePF)
5129	{
5130	/* A genuine guest #PF, reflect it to the guest. */
5131	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5132	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
5133	uFaultAddress, u32ErrCode));
5134	}
5135	else
5136	{
5137	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5138	hmR0SvmSetPendingXcptDF(pVCpu);
5139	Log4(("Pending #DF due to vectoring #PF. NP\n"));
5140	}
5141	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5142	return VINF_SUCCESS;
5143	}
5144	#endif
5145
5146	Assert(!pVM->hm.s.fNestedPaging);
5147
5148	#ifdef VBOX_HM_WITH_GUEST_PATCHING
5149	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
5150	if ( pVM->hm.s.fTprPatchingAllowed
5151	&& (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
5152	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
5153	&& !CPUMIsGuestInLongModeEx(pCtx)
5154	&& !CPUMGetGuestCPL(pVCpu)
5155	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
5156	{
5157	RTGCPHYS GCPhysApicBase;
5158	GCPhysApicBase = pCtx->msrApicBase;
5159	GCPhysApicBase &= PAGE_BASE_GC_MASK;
5160
5161	/* Check if the page at the fault-address is the APIC base. */
5162	RTGCPHYS GCPhysPage;
5163	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
5164	if ( rc2 == VINF_SUCCESS
5165	&& GCPhysPage == GCPhysApicBase)
5166	{
5167	/* Only attempt to patch the instruction once. */
5168	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
5169	if (!pPatch)
5170	return VINF_EM_HM_PATCH_TPR_INSTR;
5171	}
5172	}
5173	#endif
5174
5175	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
5176	pCtx->rip, u32ErrCode, pCtx->cr3));
5177
5178	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
5179	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
5180	if (pSvmTransient->fVectoringPF)
5181	{
5182	Assert(pVCpu->hm.s.Event.fPending);
5183	return VINF_EM_RAW_INJECT_TRPM_EVENT;
5184	}
5185
5186	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
5187	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
5188
5189	Log4(("#PF rc=%Rrc\n", rc));
5190
5191	if (rc == VINF_SUCCESS)
5192	{
5193	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
5194	TRPMResetTrap(pVCpu);
5195	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
5196	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
5197	return rc;
5198	}
5199	else if (rc == VINF_EM_RAW_GUEST_TRAP)
5200	{
5201	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5202
5203	if (!pSvmTransient->fVectoringDoublePF)
5204	{
5205	/* It's a guest page fault and needs to be reflected to the guest. */
5206	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
5207	TRPMResetTrap(pVCpu);
5208	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5209	}
5210	else
5211	{
5212	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5213	TRPMResetTrap(pVCpu);
5214	hmR0SvmSetPendingXcptDF(pVCpu);
5215	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
5216	}
5217
5218	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5219	return VINF_SUCCESS;
5220	}
5221
5222	TRPMResetTrap(pVCpu);
5223	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
5224	return rc;
5225	}
5226
5227
5228	/**
5229	* #VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
5230	* Conditional #VMEXIT.
5231	*/
5232	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5233	{
5234	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5235
5236	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5237
5238	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
5239	VMMRZCallRing3Disable(pVCpu);
5240	HM_DISABLE_PREEMPT();
5241
5242	int rc;
5243	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
5244	if (pSvmTransient->fWasGuestFPUStateActive)
5245	{
5246	rc = VINF_EM_RAW_GUEST_TRAP;
5247	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
5248	}
5249	else
5250	{
5251	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5252	Assert(!pSvmTransient->fWasGuestFPUStateActive);
5253	#endif
5254	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
5255	Assert(rc == VINF_EM_RAW_GUEST_TRAP \|\| (rc == VINF_SUCCESS && CPUMIsGuestFPUStateActive(pVCpu)));
5256	}
5257
5258	HM_RESTORE_PREEMPT();
5259	VMMRZCallRing3Enable(pVCpu);
5260
5261	if (rc == VINF_SUCCESS)
5262	{
5263	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
5264	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
5265	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
5266	pVCpu->hm.s.fPreloadGuestFpu = true;
5267	}
5268	else
5269	{
5270	/* Forward #NM to the guest. */
5271	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
5272	hmR0SvmSetPendingXcptNM(pVCpu);
5273	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
5274	}
5275	return VINF_SUCCESS;
5276	}
5277
5278
5279	/**
5280	* #VMEXIT handler for undefined opcode (SVM_EXIT_EXCEPTION_6).
5281	* Conditional #VMEXIT.
5282	*/
5283	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5284	{
5285	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5286
5287	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5288
5289	if (pVCpu->hm.s.fGIMTrapXcptUD)
5290	GIMXcptUD(pVCpu, pCtx, NULL /* pDis */);
5291	else
5292	hmR0SvmSetPendingXcptUD(pVCpu);
5293
5294	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
5295	return VINF_SUCCESS;
5296	}
5297
5298
5299	/**
5300	* #VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_10).
5301	* Conditional #VMEXIT.
5302	*/
5303	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5304	{
5305	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5306
5307	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5308
5309	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
5310
5311	if (!(pCtx->cr0 & X86_CR0_NE))
5312	{
5313	PVM pVM = pVCpu->CTX_SUFF(pVM);
5314	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5315	unsigned cbOp;
5316	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
5317	if (RT_SUCCESS(rc))
5318	{
5319	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
5320	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
5321	if (RT_SUCCESS(rc))
5322	pCtx->rip += cbOp;
5323	}
5324	else
5325	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5326	return rc;
5327	}
5328
5329	hmR0SvmSetPendingXcptMF(pVCpu);
5330	return VINF_SUCCESS;
5331	}
5332
5333
5334	/**
5335	* #VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
5336	* #VMEXIT.
5337	*/
5338	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5339	{
5340	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5341
5342	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5343
5344	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
5345
5346	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
5347	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
5348	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5349	PVM pVM = pVCpu->CTX_SUFF(pVM);
5350	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
5351	if (rc == VINF_EM_RAW_GUEST_TRAP)
5352	{
5353	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
5354	if (CPUMIsHyperDebugStateActive(pVCpu))
5355	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
5356
5357	/* Reflect the exception back to the guest. */
5358	hmR0SvmSetPendingXcptDB(pVCpu);
5359	rc = VINF_SUCCESS;
5360	}
5361
5362	/*
5363	* Update DR6.
5364	*/
5365	if (CPUMIsHyperDebugStateActive(pVCpu))
5366	{
5367	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
5368	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
5369	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
5370	}
5371	else
5372	{
5373	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
5374	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
5375	}
5376
5377	return rc;
5378	}
5379
5380	/** @} */
5381

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 55435

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