HMSVMR0.cpp@ 91286

Last change on this file since 91286 was 91271, checked in by vboxsync, 4 years ago
VMM: bugref:10092 Moved the PAE PDPTEs out of PGM into CPUMCTX.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 320.4 KB

Line
1	/* $Id: HMSVMR0.cpp 91271 2021-09-16 07:42:37Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/em.h>
33	#include <VBox/vmm/gim.h>
34	#include <VBox/vmm/apic.h>
35	#include "HMInternal.h"
36	#include <VBox/vmm/vmcc.h>
37	#include <VBox/err.h>
38	#include "HMSVMR0.h"
39	#include "dtrace/VBoxVMM.h"
40
41	#ifdef DEBUG_ramshankar
42	# define HMSVM_SYNC_FULL_GUEST_STATE
43	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
44	# define HMSVM_ALWAYS_TRAP_PF
45	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
46	#endif
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	#ifdef VBOX_WITH_STATISTICS
53	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
55	if ((u64ExitCode) == SVM_EXIT_NPF) \
56	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
57	else \
58	STAM_COUNTER_INC(&pVCpu->hm.s.aStatExitReason[(u64ExitCode) & MASK_EXITREASON_STAT]); \
59	} while (0)
60
61	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
62	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
63	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
64	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitAll); \
65	if ((u64ExitCode) == SVM_EXIT_NPF) \
66	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitReasonNpf); \
67	else \
68	STAM_COUNTER_INC(&pVCpu->hm.s.aStatNestedExitReason[(u64ExitCode) & MASK_EXITREASON_STAT]); \
69	} while (0)
70	# endif
71	#else
72	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
73	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
74	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
75	# endif
76	#endif /* !VBOX_WITH_STATISTICS */
77
78	/** If we decide to use a function table approach this can be useful to
79	* switch to a "static DECLCALLBACK(int)". */
80	#define HMSVM_EXIT_DECL static VBOXSTRICTRC
81
82	/**
83	* Subset of the guest-CPU state that is kept by SVM R0 code while executing the
84	* guest using hardware-assisted SVM.
85	*
86	* This excludes state like TSC AUX, GPRs (other than RSP, RAX) which are always
87	* are swapped and restored across the world-switch and also registers like
88	* EFER, PAT MSR etc. which cannot be modified by the guest without causing a
89	* \#VMEXIT.
90	*/
91	#define HMSVM_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
92	\| CPUMCTX_EXTRN_RFLAGS \
93	\| CPUMCTX_EXTRN_RAX \
94	\| CPUMCTX_EXTRN_RSP \
95	\| CPUMCTX_EXTRN_SREG_MASK \
96	\| CPUMCTX_EXTRN_CR0 \
97	\| CPUMCTX_EXTRN_CR2 \
98	\| CPUMCTX_EXTRN_CR3 \
99	\| CPUMCTX_EXTRN_TABLE_MASK \
100	\| CPUMCTX_EXTRN_DR6 \
101	\| CPUMCTX_EXTRN_DR7 \
102	\| CPUMCTX_EXTRN_KERNEL_GS_BASE \
103	\| CPUMCTX_EXTRN_SYSCALL_MSRS \
104	\| CPUMCTX_EXTRN_SYSENTER_MSRS \
105	\| CPUMCTX_EXTRN_HWVIRT \
106	\| CPUMCTX_EXTRN_HM_SVM_MASK)
107
108	/**
109	* Subset of the guest-CPU state that is shared between the guest and host.
110	*/
111	#define HMSVM_CPUMCTX_SHARED_STATE CPUMCTX_EXTRN_DR_MASK
112
113	/** Macro for importing guest state from the VMCB back into CPUMCTX. */
114	#define HMSVM_CPUMCTX_IMPORT_STATE(a_pVCpu, a_fWhat) \
115	do { \
116	if ((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fWhat)) \
117	hmR0SvmImportGuestState((a_pVCpu), (a_fWhat)); \
118	} while (0)
119
120	/** Assert that the required state bits are fetched. */
121	#define HMSVM_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
122	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
123	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
124
125	/** Assert that preemption is disabled or covered by thread-context hooks. */
126	#define HMSVM_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
127	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
128
129	/** Assert that we haven't migrated CPUs when thread-context hooks are not
130	* used. */
131	#define HMSVM_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
132	\|\| (a_pVCpu)->hmr0.s.idEnteredCpu == RTMpCpuId(), \
133	("Illegal migration! Entered on CPU %u Current %u\n", \
134	(a_pVCpu)->hmr0.s.idEnteredCpu, RTMpCpuId()));
135
136	/** Assert that we're not executing a nested-guest. */
137	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
138	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
139	#else
140	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
141	#endif
142
143	/** Assert that we're executing a nested-guest. */
144	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
145	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
146	#else
147	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
148	#endif
149
150	/** Macro for checking and returning from the using function for
151	* \#VMEXIT intercepts that maybe caused during delivering of another
152	* event in the guest. */
153	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
154	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
155	do \
156	{ \
157	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
158	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
159	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
160	else if ( rc == VINF_EM_RESET \
161	&& CPUMIsGuestSvmCtrlInterceptSet((a_pVCpu), &(a_pVCpu)->cpum.GstCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
162	{ \
163	HMSVM_CPUMCTX_IMPORT_STATE((a_pVCpu), HMSVM_CPUMCTX_EXTRN_ALL); \
164	return IEMExecSvmVmexit((a_pVCpu), SVM_EXIT_SHUTDOWN, 0, 0); \
165	} \
166	else \
167	return rc; \
168	} while (0)
169	#else
170	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
171	do \
172	{ \
173	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
174	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
175	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
176	else \
177	return rc; \
178	} while (0)
179	#endif
180
181	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
182	* instruction that exited. */
183	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
184	do { \
185	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
186	(a_rc) = VINF_EM_DBG_STEPPED; \
187	} while (0)
188
189	/** Validate segment descriptor granularity bit. */
190	#ifdef VBOX_STRICT
191	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) \
192	AssertMsg( !(a_pCtx)->reg.Attr.n.u1Present \
193	\|\| ( (a_pCtx)->reg.Attr.n.u1Granularity \
194	? ((a_pCtx)->reg.u32Limit & 0xfff) == 0xfff \
195	: (a_pCtx)->reg.u32Limit <= UINT32_C(0xfffff)), \
196	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", (a_pCtx)->reg.u32Limit, \
197	(a_pCtx)->reg.Attr.u, (a_pCtx)->reg.u64Base))
198	#else
199	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) do { } while (0)
200	#endif
201
202	/**
203	* Exception bitmap mask for all contributory exceptions.
204	*
205	* Page fault is deliberately excluded here as it's conditional as to whether
206	* it's contributory or benign. Page faults are handled separately.
207	*/
208	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
209	\| RT_BIT(X86_XCPT_DE))
210
211	/**
212	* Mandatory/unconditional guest control intercepts.
213	*
214	* SMIs can and do happen in normal operation. We need not intercept them
215	* while executing the guest (or nested-guest).
216	*/
217	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
218	\| SVM_CTRL_INTERCEPT_NMI \
219	\| SVM_CTRL_INTERCEPT_INIT \
220	\| SVM_CTRL_INTERCEPT_RDPMC \
221	\| SVM_CTRL_INTERCEPT_CPUID \
222	\| SVM_CTRL_INTERCEPT_RSM \
223	\| SVM_CTRL_INTERCEPT_HLT \
224	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
225	\| SVM_CTRL_INTERCEPT_MSR_PROT \
226	\| SVM_CTRL_INTERCEPT_INVLPGA \
227	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
228	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
229	\| SVM_CTRL_INTERCEPT_VMRUN \
230	\| SVM_CTRL_INTERCEPT_SKINIT \
231	\| SVM_CTRL_INTERCEPT_WBINVD \
232	\| SVM_CTRL_INTERCEPT_MONITOR \
233	\| SVM_CTRL_INTERCEPT_MWAIT \
234	\| SVM_CTRL_INTERCEPT_CR0_SEL_WRITE \
235	\| SVM_CTRL_INTERCEPT_XSETBV)
236
237	/** @name VMCB Clean Bits.
238	*
239	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
240	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
241	* memory.
242	*
243	* @{ */
244	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
245	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
246	/** I/O permission bitmap, MSR permission bitmap. */
247	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
248	/** ASID. */
249	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
250	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
251	V_INTR_VECTOR. */
252	#define HMSVM_VMCB_CLEAN_INT_CTRL RT_BIT(3)
253	/** Nested Paging: Nested CR3 (nCR3), PAT. */
254	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
255	/** Control registers (CR0, CR3, CR4, EFER). */
256	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
257	/** Debug registers (DR6, DR7). */
258	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
259	/** GDT, IDT limit and base. */
260	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
261	/** Segment register: CS, SS, DS, ES limit and base. */
262	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
263	/** CR2.*/
264	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
265	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
266	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
267	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
268	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
269	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
270	/** Mask of all valid VMCB Clean bits. */
271	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
272	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
273	\| HMSVM_VMCB_CLEAN_ASID \
274	\| HMSVM_VMCB_CLEAN_INT_CTRL \
275	\| HMSVM_VMCB_CLEAN_NP \
276	\| HMSVM_VMCB_CLEAN_CRX_EFER \
277	\| HMSVM_VMCB_CLEAN_DRX \
278	\| HMSVM_VMCB_CLEAN_DT \
279	\| HMSVM_VMCB_CLEAN_SEG \
280	\| HMSVM_VMCB_CLEAN_CR2 \
281	\| HMSVM_VMCB_CLEAN_LBR \
282	\| HMSVM_VMCB_CLEAN_AVIC)
283	/** @} */
284
285	/** @name SVM transient.
286	*
287	* A state structure for holding miscellaneous information across AMD-V
288	* VMRUN/\#VMEXIT operation, restored after the transition.
289	*
290	* @{ */
291	typedef struct SVMTRANSIENT
292	{
293	/** The host's rflags/eflags. */
294	RTCCUINTREG fEFlags;
295	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
296	uint64_t u64ExitCode;
297
298	/** The guest's TPR value used for TPR shadowing. */
299	uint8_t u8GuestTpr;
300	/** Alignment. */
301	uint8_t abAlignment0[7];
302
303	/** Pointer to the currently executing VMCB. */
304	PSVMVMCB pVmcb;
305
306	/** Whether we are currently executing a nested-guest. */
307	bool fIsNestedGuest;
308	/** Whether the guest debug state was active at the time of \#VMEXIT. */
309	bool fWasGuestDebugStateActive;
310	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
311	bool fWasHyperDebugStateActive;
312	/** Whether the TSC offset mode needs to be updated. */
313	bool fUpdateTscOffsetting;
314	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
315	bool fRestoreTscAuxMsr;
316	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
317	* contributary exception or a page-fault. */
318	bool fVectoringDoublePF;
319	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
320	* external interrupt or NMI. */
321	bool fVectoringPF;
322	/** Padding. */
323	bool afPadding0;
324	} SVMTRANSIENT;
325	/** Pointer to SVM transient state. */
326	typedef SVMTRANSIENT *PSVMTRANSIENT;
327	/** Pointer to a const SVM transient state. */
328	typedef const SVMTRANSIENT *PCSVMTRANSIENT;
329
330	AssertCompileSizeAlignment(SVMTRANSIENT, sizeof(uint64_t));
331	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
332	AssertCompileMemberAlignment(SVMTRANSIENT, pVmcb, sizeof(uint64_t));
333	/** @} */
334
335	/**
336	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
337	*/
338	typedef enum SVMMSREXITREAD
339	{
340	/** Reading this MSR causes a \#VMEXIT. */
341	SVMMSREXIT_INTERCEPT_READ = 0xb,
342	/** Reading this MSR does not cause a \#VMEXIT. */
343	SVMMSREXIT_PASSTHRU_READ
344	} SVMMSREXITREAD;
345
346	/**
347	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
348	*/
349	typedef enum SVMMSREXITWRITE
350	{
351	/** Writing to this MSR causes a \#VMEXIT. */
352	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
353	/** Writing to this MSR does not cause a \#VMEXIT. */
354	SVMMSREXIT_PASSTHRU_WRITE
355	} SVMMSREXITWRITE;
356
357	/**
358	* SVM \#VMEXIT handler.
359	*
360	* @returns Strict VBox status code.
361	* @param pVCpu The cross context virtual CPU structure.
362	* @param pSvmTransient Pointer to the SVM-transient structure.
363	*/
364	typedef VBOXSTRICTRC FNSVMEXITHANDLER(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
365
366
367	/*********************************************************************************************************************************
368	* Internal Functions *
369	*********************************************************************************************************************************/
370	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu);
371	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState);
372
373
374	/** @name \#VMEXIT handlers.
375	* @{
376	*/
377	static FNSVMEXITHANDLER hmR0SvmExitIntr;
378	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
379	static FNSVMEXITHANDLER hmR0SvmExitInvd;
380	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
381	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
382	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
383	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
384	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
385	static FNSVMEXITHANDLER hmR0SvmExitHlt;
386	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
387	static FNSVMEXITHANDLER hmR0SvmExitMwait;
388	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
389	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
390	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
391	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
392	static FNSVMEXITHANDLER hmR0SvmExitMsr;
393	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
394	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
395	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
396	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
397	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
398	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
399	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
400	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
401	static FNSVMEXITHANDLER hmR0SvmExitPause;
402	static FNSVMEXITHANDLER hmR0SvmExitFerrFreeze;
403	static FNSVMEXITHANDLER hmR0SvmExitIret;
404	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
405	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
406	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
407	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
408	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
409	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
410	static FNSVMEXITHANDLER hmR0SvmExitXcptGP;
411	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
412	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
413	#endif
414	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
415	static FNSVMEXITHANDLER hmR0SvmExitClgi;
416	static FNSVMEXITHANDLER hmR0SvmExitStgi;
417	static FNSVMEXITHANDLER hmR0SvmExitVmload;
418	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
419	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
420	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
421	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
422	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
423	#endif
424	/** @} */
425
426	static VBOXSTRICTRC hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
427	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
428	static VBOXSTRICTRC hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
429	#endif
430
431
432	/*********************************************************************************************************************************
433	* Global Variables *
434	*********************************************************************************************************************************/
435	/** Ring-0 memory object for the IO bitmap. */
436	static RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
437	/** Physical address of the IO bitmap. */
438	static RTHCPHYS g_HCPhysIOBitmap;
439	/** Pointer to the IO bitmap. */
440	static R0PTRTYPE(void *) g_pvIOBitmap;
441
442	#ifdef VBOX_STRICT
443	# define HMSVM_LOG_RBP_RSP RT_BIT_32(0)
444	# define HMSVM_LOG_CR_REGS RT_BIT_32(1)
445	# define HMSVM_LOG_CS RT_BIT_32(2)
446	# define HMSVM_LOG_SS RT_BIT_32(3)
447	# define HMSVM_LOG_FS RT_BIT_32(4)
448	# define HMSVM_LOG_GS RT_BIT_32(5)
449	# define HMSVM_LOG_LBR RT_BIT_32(6)
450	# define HMSVM_LOG_ALL ( HMSVM_LOG_RBP_RSP \
451	\| HMSVM_LOG_CR_REGS \
452	\| HMSVM_LOG_CS \
453	\| HMSVM_LOG_SS \
454	\| HMSVM_LOG_FS \
455	\| HMSVM_LOG_GS \
456	\| HMSVM_LOG_LBR)
457
458	/**
459	* Dumps virtual CPU state and additional info. to the logger for diagnostics.
460	*
461	* @param pVCpu The cross context virtual CPU structure.
462	* @param pVmcb Pointer to the VM control block.
463	* @param pszPrefix Log prefix.
464	* @param fFlags Log flags, see HMSVM_LOG_XXX.
465	* @param uVerbose The verbosity level, currently unused.
466	*/
467	static void hmR0SvmLogState(PVMCPUCC pVCpu, PCSVMVMCB pVmcb, const char *pszPrefix, uint32_t fFlags, uint8_t uVerbose)
468	{
469	RT_NOREF2(pVCpu, uVerbose);
470	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
471
472	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
473	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip, pCtx->rflags.u));
474
475	if (fFlags & HMSVM_LOG_RBP_RSP)
476	{
477	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_RBP);
478	Log4(("%s: rsp=%#RX64 rbp=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp));
479	}
480
481	if (fFlags & HMSVM_LOG_CR_REGS)
482	{
483	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4);
484	Log4(("%s: cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cr0, pCtx->cr3, pCtx->cr4));
485	}
486
487	if (fFlags & HMSVM_LOG_CS)
488	{
489	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
490	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
491	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
492	}
493	if (fFlags & HMSVM_LOG_SS)
494	{
495	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
496	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
497	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
498	}
499	if (fFlags & HMSVM_LOG_FS)
500	{
501	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
502	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
503	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
504	}
505	if (fFlags & HMSVM_LOG_GS)
506	{
507	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
508	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
509	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
510	}
511
512	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
513	if (fFlags & HMSVM_LOG_LBR)
514	{
515	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
516	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
517	}
518	NOREF(pszPrefix); NOREF(pVmcbGuest); NOREF(pCtx);
519	}
520	#endif /* VBOX_STRICT */
521
522
523	/**
524	* Sets up and activates AMD-V on the current CPU.
525	*
526	* @returns VBox status code.
527	* @param pHostCpu The HM physical-CPU structure.
528	* @param pVM The cross context VM structure. Can be
529	* NULL after a resume!
530	* @param pvCpuPage Pointer to the global CPU page.
531	* @param HCPhysCpuPage Physical address of the global CPU page.
532	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
533	* @param pHwvirtMsrs Pointer to the hardware-virtualization MSRs (currently
534	* unused).
535	*/
536	VMMR0DECL(int) SVMR0EnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
537	PCSUPHWVIRTMSRS pHwvirtMsrs)
538	{
539	Assert(!fEnabledByHost);
540	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
541	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
542	Assert(pvCpuPage); NOREF(pvCpuPage);
543	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
544
545	RT_NOREF2(fEnabledByHost, pHwvirtMsrs);
546
547	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
548	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
549
550	/*
551	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
552	*/
553	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
554	if (u64HostEfer & MSR_K6_EFER_SVME)
555	{
556	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
557	if ( pVM
558	&& pVM->hm.s.svm.fIgnoreInUseError)
559	pHostCpu->fIgnoreAMDVInUseError = true;
560
561	if (!pHostCpu->fIgnoreAMDVInUseError)
562	{
563	ASMSetFlags(fEFlags);
564	return VERR_SVM_IN_USE;
565	}
566	}
567
568	/* Turn on AMD-V in the EFER MSR. */
569	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
570
571	/* Write the physical page address where the CPU will store the host state while executing the VM. */
572	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
573
574	/* Restore interrupts. */
575	ASMSetFlags(fEFlags);
576
577	/*
578	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all
579	* non-zero ASIDs when enabling SVM. AMD doesn't have an SVM instruction to flush all
580	* ASIDs (flushing is done upon VMRUN). Therefore, flag that we need to flush the TLB
581	* entirely with before executing any guest code.
582	*/
583	pHostCpu->fFlushAsidBeforeUse = true;
584
585	/*
586	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
587	*/
588	++pHostCpu->cTlbFlushes;
589
590	return VINF_SUCCESS;
591	}
592
593
594	/**
595	* Deactivates AMD-V on the current CPU.
596	*
597	* @returns VBox status code.
598	* @param pHostCpu The HM physical-CPU structure.
599	* @param pvCpuPage Pointer to the global CPU page.
600	* @param HCPhysCpuPage Physical address of the global CPU page.
601	*/
602	VMMR0DECL(int) SVMR0DisableCpu(PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
603	{
604	RT_NOREF1(pHostCpu);
605	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
606	AssertReturn( HCPhysCpuPage
607	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
608	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
609
610	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
611	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
612
613	/* Turn off AMD-V in the EFER MSR. */
614	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
615	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
616
617	/* Invalidate host state physical address. */
618	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
619
620	/* Restore interrupts. */
621	ASMSetFlags(fEFlags);
622
623	return VINF_SUCCESS;
624	}
625
626
627	/**
628	* Does global AMD-V initialization (called during module initialization).
629	*
630	* @returns VBox status code.
631	*/
632	VMMR0DECL(int) SVMR0GlobalInit(void)
633	{
634	/*
635	* Allocate 12 KB (3 pages) for the IO bitmap. Since this is non-optional and we always
636	* intercept all IO accesses, it's done once globally here instead of per-VM.
637	*/
638	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
639	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
640	if (RT_FAILURE(rc))
641	return rc;
642
643	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
644	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
645
646	/* Set all bits to intercept all IO accesses. */
647	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
648
649	return VINF_SUCCESS;
650	}
651
652
653	/**
654	* Does global AMD-V termination (called during module termination).
655	*/
656	VMMR0DECL(void) SVMR0GlobalTerm(void)
657	{
658	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
659	{
660	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
661	g_pvIOBitmap = NULL;
662	g_HCPhysIOBitmap = 0;
663	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
664	}
665	}
666
667
668	/**
669	* Frees any allocated per-VCPU structures for a VM.
670	*
671	* @param pVM The cross context VM structure.
672	*/
673	DECLINLINE(void) hmR0SvmFreeStructs(PVMCC pVM)
674	{
675	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
676	{
677	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
678	AssertPtr(pVCpu);
679
680	if (pVCpu->hmr0.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
681	{
682	RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjVmcbHost, false);
683	pVCpu->hmr0.s.svm.HCPhysVmcbHost = 0;
684	pVCpu->hmr0.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
685	}
686
687	if (pVCpu->hmr0.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
688	{
689	RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjVmcb, false);
690	pVCpu->hmr0.s.svm.pVmcb = NULL;
691	pVCpu->hmr0.s.svm.HCPhysVmcb = 0;
692	pVCpu->hmr0.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
693	}
694
695	if (pVCpu->hmr0.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
696	{
697	RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjMsrBitmap, false);
698	pVCpu->hmr0.s.svm.pvMsrBitmap = NULL;
699	pVCpu->hmr0.s.svm.HCPhysMsrBitmap = 0;
700	pVCpu->hmr0.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
701	}
702	}
703	}
704
705
706	/**
707	* Sets pfnVMRun to the best suited variant.
708	*
709	* This must be called whenever anything changes relative to the SVMR0VMRun
710	* variant selection:
711	* - pVCpu->hm.s.fLoadSaveGuestXcr0
712	* - CPUMCTX_WSF_IBPB_ENTRY in pVCpu->cpum.GstCtx.fWorldSwitcher
713	* - CPUMCTX_WSF_IBPB_EXIT in pVCpu->cpum.GstCtx.fWorldSwitcher
714	* - Perhaps: CPUMIsGuestFPUStateActive() (windows only)
715	* - Perhaps: CPUMCTX.fXStateMask (windows only)
716	*
717	* We currently ASSUME that neither CPUMCTX_WSF_IBPB_ENTRY nor
718	* CPUMCTX_WSF_IBPB_EXIT cannot be changed at runtime.
719	*/
720	static void hmR0SvmUpdateVmRunFunction(PVMCPUCC pVCpu)
721	{
722	static const struct CLANGWORKAROUND { PFNHMSVMVMRUN pfn; } s_aHmR0SvmVmRunFunctions[] =
723	{
724	{ hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit },
725	{ hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit },
726	{ hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit },
727	{ hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit },
728	{ hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit },
729	{ hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit },
730	{ hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit },
731	{ hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit },
732	};
733	uintptr_t const idx = (pVCpu->hmr0.s.fLoadSaveGuestXcr0 ? 1 : 0)
734	\| (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_IBPB_ENTRY ? 2 : 0)
735	\| (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_IBPB_EXIT ? 4 : 0);
736	PFNHMSVMVMRUN const pfnVMRun = s_aHmR0SvmVmRunFunctions[idx].pfn;
737	if (pVCpu->hmr0.s.svm.pfnVMRun != pfnVMRun)
738	pVCpu->hmr0.s.svm.pfnVMRun = pfnVMRun;
739	}
740
741
742	/**
743	* Selector FNHMSVMVMRUN implementation.
744	*/
745	static DECLCALLBACK(int) hmR0SvmVMRunSelector(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB)
746	{
747	hmR0SvmUpdateVmRunFunction(pVCpu);
748	return pVCpu->hmr0.s.svm.pfnVMRun(pVM, pVCpu, HCPhysVMCB);
749	}
750
751
752	/**
753	* Does per-VM AMD-V initialization.
754	*
755	* @returns VBox status code.
756	* @param pVM The cross context VM structure.
757	*/
758	VMMR0DECL(int) SVMR0InitVM(PVMCC pVM)
759	{
760	int rc = VERR_INTERNAL_ERROR_5;
761
762	/*
763	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
764	*/
765	uint32_t u32Family;
766	uint32_t u32Model;
767	uint32_t u32Stepping;
768	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
769	{
770	Log4Func(("AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
771	pVM->hmr0.s.svm.fAlwaysFlushTLB = true;
772	}
773
774	/*
775	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
776	*/
777	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
778	{
779	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
780	pVCpu->hmr0.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
781	pVCpu->hmr0.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
782	pVCpu->hmr0.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
783	}
784
785	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
786	{
787	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
788
789	/*
790	* Initialize the hardware-assisted SVM guest-execution handler.
791	* We now use a single handler for both 32-bit and 64-bit guests, see @bugref{6208#c73}.
792	*/
793	pVCpu->hmr0.s.svm.pfnVMRun = hmR0SvmVMRunSelector;
794
795	/*
796	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
797	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
798	*/
799	/** @todo Does this need to be below 4G? */
800	rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
801	if (RT_FAILURE(rc))
802	goto failure_cleanup;
803
804	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjVmcbHost);
805	pVCpu->hmr0.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjVmcbHost, 0 /* iPage */);
806	Assert(pVCpu->hmr0.s.svm.HCPhysVmcbHost < _4G);
807	ASMMemZeroPage(pvVmcbHost);
808
809	/*
810	* Allocate one page for the guest-state VMCB.
811	*/
812	/** @todo Does this need to be below 4G? */
813	rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
814	if (RT_FAILURE(rc))
815	goto failure_cleanup;
816
817	pVCpu->hmr0.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjVmcb);
818	pVCpu->hmr0.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjVmcb, 0 /* iPage */);
819	Assert(pVCpu->hmr0.s.svm.HCPhysVmcb < _4G);
820	ASMMemZeroPage(pVCpu->hmr0.s.svm.pVmcb);
821
822	/*
823	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
824	* SVM to not require one.
825	*/
826	/** @todo Does this need to be below 4G? */
827	rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
828	false /* fExecutable */);
829	if (RT_FAILURE(rc))
830	goto failure_cleanup;
831
832	pVCpu->hmr0.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjMsrBitmap);
833	pVCpu->hmr0.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
834	/* Set all bits to intercept all MSR accesses (changed later on). */
835	ASMMemFill32(pVCpu->hmr0.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
836	}
837
838	return VINF_SUCCESS;
839
840	failure_cleanup:
841	hmR0SvmFreeStructs(pVM);
842	return rc;
843	}
844
845
846	/**
847	* Does per-VM AMD-V termination.
848	*
849	* @returns VBox status code.
850	* @param pVM The cross context VM structure.
851	*/
852	VMMR0DECL(int) SVMR0TermVM(PVMCC pVM)
853	{
854	hmR0SvmFreeStructs(pVM);
855	return VINF_SUCCESS;
856	}
857
858
859	/**
860	* Returns whether the VMCB Clean Bits feature is supported.
861	*
862	* @returns @c true if supported, @c false otherwise.
863	* @param pVCpu The cross context virtual CPU structure.
864	* @param fIsNestedGuest Whether we are currently executing the nested-guest.
865	*/
866	DECL_FORCE_INLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPUCC pVCpu, bool fIsNestedGuest)
867	{
868	PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
869	bool const fHostVmcbCleanBits = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
870	if (!fIsNestedGuest)
871	return fHostVmcbCleanBits;
872	return fHostVmcbCleanBits && pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
873	}
874
875
876	/**
877	* Returns whether the decode assists feature is supported.
878	*
879	* @returns @c true if supported, @c false otherwise.
880	* @param pVCpu The cross context virtual CPU structure.
881	*/
882	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPUCC pVCpu)
883	{
884	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
885	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
886	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
887	return (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
888	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
889	#endif
890	return RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
891	}
892
893
894	/**
895	* Returns whether the NRIP_SAVE feature is supported.
896	*
897	* @returns @c true if supported, @c false otherwise.
898	* @param pVCpu The cross context virtual CPU structure.
899	*/
900	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPUCC pVCpu)
901	{
902	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
903	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
904	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
905	return (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
906	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
907	#endif
908	return RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
909	}
910
911
912	/**
913	* Sets the permission bits for the specified MSR in the MSRPM bitmap.
914	*
915	* @param pVCpu The cross context virtual CPU structure.
916	* @param pbMsrBitmap Pointer to the MSR bitmap.
917	* @param idMsr The MSR for which the permissions are being set.
918	* @param enmRead MSR read permissions.
919	* @param enmWrite MSR write permissions.
920	*
921	* @remarks This function does -not- clear the VMCB clean bits for MSRPM. The
922	* caller needs to take care of this.
923	*/
924	static void hmR0SvmSetMsrPermission(PVMCPUCC pVCpu, uint8_t *pbMsrBitmap, uint32_t idMsr, SVMMSREXITREAD enmRead,
925	SVMMSREXITWRITE enmWrite)
926	{
927	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx);
928	uint16_t offMsrpm;
929	uint8_t uMsrpmBit;
930	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
931	AssertRC(rc);
932
933	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
934	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
935
936	pbMsrBitmap += offMsrpm;
937	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
938	*pbMsrBitmap \|= RT_BIT(uMsrpmBit);
939	else
940	{
941	if (!fInNestedGuestMode)
942	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
943	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
944	else
945	{
946	/* Only clear the bit if the nested-guest is also not intercepting the MSR read.*/
947	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
948	pbNstGstMsrBitmap += offMsrpm;
949	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit)))
950	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
951	else
952	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit));
953	}
954	#endif
955	}
956
957	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
958	*pbMsrBitmap \|= RT_BIT(uMsrpmBit + 1);
959	else
960	{
961	if (!fInNestedGuestMode)
962	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
963	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
964	else
965	{
966	/* Only clear the bit if the nested-guest is also not intercepting the MSR write.*/
967	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
968	pbNstGstMsrBitmap += offMsrpm;
969	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit + 1)))
970	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
971	else
972	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
973	}
974	#endif
975	}
976	}
977
978
979	/**
980	* Sets up AMD-V for the specified VM.
981	* This function is only called once per-VM during initalization.
982	*
983	* @returns VBox status code.
984	* @param pVM The cross context VM structure.
985	*/
986	VMMR0DECL(int) SVMR0SetupVM(PVMCC pVM)
987	{
988	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
989	AssertReturn(pVM, VERR_INVALID_PARAMETER);
990
991	/*
992	* Validate and copy over some parameters.
993	*/
994	AssertReturn(pVM->hm.s.svm.fSupported, VERR_INCOMPATIBLE_CONFIG);
995	bool const fNestedPaging = pVM->hm.s.fNestedPagingCfg;
996	AssertReturn(!fNestedPaging \|\| (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING), VERR_INCOMPATIBLE_CONFIG);
997	pVM->hmr0.s.fNestedPaging = fNestedPaging;
998	pVM->hmr0.s.fAllow64BitGuests = pVM->hm.s.fAllow64BitGuestsCfg;
999
1000	/*
1001	* Determin some configuration parameters.
1002	*/
1003	bool const fPauseFilter = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1004	bool const fPauseFilterThreshold = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1005	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter;
1006
1007	bool const fLbrVirt = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1008	bool const fUseLbrVirt = fLbrVirt && pVM->hm.s.svm.fLbrVirt; /** @todo IEM implementation etc. */
1009
1010	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1011	bool const fVirtVmsaveVmload = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1012	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && fNestedPaging;
1013
1014	bool const fVGif = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1015	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
1016	#endif
1017
1018	PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
1019	PSVMVMCB pVmcb0 = pVCpu0->hmr0.s.svm.pVmcb;
1020	AssertMsgReturn(RT_VALID_PTR(pVmcb0), ("Invalid pVmcb (%p) for vcpu[0]\n", pVmcb0), VERR_SVM_INVALID_PVMCB);
1021	PSVMVMCBCTRL pVmcbCtrl0 = &pVmcb0->ctrl;
1022
1023	/* Always trap #AC for reasons of security. */
1024	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
1025
1026	/* Always trap #DB for reasons of security. */
1027	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
1028
1029	/* Trap exceptions unconditionally (debug purposes). */
1030	#ifdef HMSVM_ALWAYS_TRAP_PF
1031	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_PF);
1032	#endif
1033	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1034	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
1035	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_BP)
1036	\| RT_BIT_32(X86_XCPT_DE)
1037	\| RT_BIT_32(X86_XCPT_NM)
1038	\| RT_BIT_32(X86_XCPT_UD)
1039	\| RT_BIT_32(X86_XCPT_NP)
1040	\| RT_BIT_32(X86_XCPT_SS)
1041	\| RT_BIT_32(X86_XCPT_GP)
1042	\| RT_BIT_32(X86_XCPT_PF)
1043	\| RT_BIT_32(X86_XCPT_MF)
1044	;
1045	#endif
1046
1047	/* Apply the exceptions intercepts needed by the GIM provider. */
1048	if (pVCpu0->hm.s.fGIMTrapXcptUD \|\| pVCpu0->hm.s.svm.fEmulateLongModeSysEnterExit)
1049	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
1050
1051	/* The mesa 3d driver hack needs #GP. */
1052	if (pVCpu0->hm.s.fTrapXcptGpForLovelyMesaDrv)
1053	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_GP);
1054
1055	/* Set up unconditional intercepts and conditions. */
1056	pVmcbCtrl0->u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
1057	\| SVM_CTRL_INTERCEPT_VMMCALL
1058	\| SVM_CTRL_INTERCEPT_VMSAVE
1059	\| SVM_CTRL_INTERCEPT_VMLOAD
1060	\| SVM_CTRL_INTERCEPT_CLGI
1061	\| SVM_CTRL_INTERCEPT_STGI;
1062
1063	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
1064	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
1065	#endif
1066
1067	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1068	if (pVCpu0->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvm)
1069	{
1070	/* Virtualized VMSAVE/VMLOAD. */
1071	if (fUseVirtVmsaveVmload)
1072	{
1073	pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload = 1;
1074	pVmcbCtrl0->u64InterceptCtrl &= ~( SVM_CTRL_INTERCEPT_VMSAVE
1075	\| SVM_CTRL_INTERCEPT_VMLOAD);
1076	}
1077	else
1078	Assert(!pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload);
1079
1080	/* Virtual GIF. */
1081	if (fUseVGif)
1082	{
1083	pVmcbCtrl0->IntCtrl.n.u1VGifEnable = 1;
1084	pVmcbCtrl0->u64InterceptCtrl &= ~( SVM_CTRL_INTERCEPT_CLGI
1085	\| SVM_CTRL_INTERCEPT_STGI);
1086	}
1087	else
1088	Assert(!pVmcbCtrl0->IntCtrl.n.u1VGifEnable);
1089	}
1090	else
1091	#endif
1092	{
1093	Assert(!pVCpu0->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvm);
1094	Assert(!pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload);
1095	Assert(!pVmcbCtrl0->IntCtrl.n.u1VGifEnable);
1096	}
1097
1098	/* CR4 writes must always be intercepted for tracking PGM mode changes. */
1099	pVmcbCtrl0->u16InterceptWrCRx = RT_BIT(4);
1100
1101	/* Intercept all DRx reads and writes by default. Changed later on. */
1102	pVmcbCtrl0->u16InterceptRdDRx = 0xffff;
1103	pVmcbCtrl0->u16InterceptWrDRx = 0xffff;
1104
1105	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
1106	pVmcbCtrl0->IntCtrl.n.u1VIntrMasking = 1;
1107
1108	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
1109	and we currently deliver both PIC and APIC interrupts alike, see hmR0SvmEvaluatePendingEvent() */
1110	pVmcbCtrl0->IntCtrl.n.u1IgnoreTPR = 1;
1111
1112	/* Set the IO permission bitmap physical addresses. */
1113	pVmcbCtrl0->u64IOPMPhysAddr = g_HCPhysIOBitmap;
1114
1115	/* LBR virtualization. */
1116	pVmcbCtrl0->LbrVirt.n.u1LbrVirt = fUseLbrVirt;
1117
1118	/* The host ASID MBZ, for the guest start with 1. */
1119	pVmcbCtrl0->TLBCtrl.n.u32ASID = 1;
1120
1121	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1122	pVmcbCtrl0->NestedPagingCtrl.n.u1NestedPaging = fNestedPaging;
1123
1124	/* Without Nested Paging, we need additionally intercepts. */
1125	if (!fNestedPaging)
1126	{
1127	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1128	pVmcbCtrl0->u16InterceptRdCRx \|= RT_BIT(3);
1129	pVmcbCtrl0->u16InterceptWrCRx \|= RT_BIT(3);
1130
1131	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1132	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1133	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1134
1135	/* Page faults must be intercepted to implement shadow paging. */
1136	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1137	}
1138
1139	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1140	if (fUsePauseFilter)
1141	{
1142	Assert(pVM->hm.s.svm.cPauseFilter > 0);
1143	pVmcbCtrl0->u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1144	if (fPauseFilterThreshold)
1145	pVmcbCtrl0->u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1146	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_PAUSE;
1147	}
1148
1149	/*
1150	* Setup the MSR permission bitmap.
1151	* The following MSRs are saved/restored automatically during the world-switch.
1152	* Don't intercept guest read/write accesses to these MSRs.
1153	*/
1154	uint8_t pbMsrBitmap0 = (uint8_t )pVCpu0->hmr0.s.svm.pvMsrBitmap;
1155	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1156	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1157	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1158	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1159	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1160	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1161	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1162	if (!pVCpu0->hm.s.svm.fEmulateLongModeSysEnterExit)
1163	{
1164	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1165	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1166	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1167	}
1168	else
1169	{
1170	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_CS, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
1171	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
1172	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
1173	}
1174	pVmcbCtrl0->u64MSRPMPhysAddr = pVCpu0->hmr0.s.svm.HCPhysMsrBitmap;
1175
1176	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1177	Assert(pVmcbCtrl0->u32VmcbCleanBits == 0);
1178
1179	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
1180	{
1181	PVMCPUCC pVCpuCur = VMCC_GET_CPU(pVM, idCpu);
1182	PSVMVMCB pVmcbCur = pVCpuCur->hmr0.s.svm.pVmcb;
1183	AssertMsgReturn(RT_VALID_PTR(pVmcbCur), ("Invalid pVmcb (%p) for vcpu[%u]\n", pVmcbCur, idCpu), VERR_SVM_INVALID_PVMCB);
1184	PSVMVMCBCTRL pVmcbCtrlCur = &pVmcbCur->ctrl;
1185
1186	/* Copy the VMCB control area. */
1187	memcpy(pVmcbCtrlCur, pVmcbCtrl0, sizeof(*pVmcbCtrlCur));
1188
1189	/* Copy the MSR bitmap and setup the VCPU-specific host physical address. */
1190	uint8_t pbMsrBitmapCur = (uint8_t )pVCpuCur->hmr0.s.svm.pvMsrBitmap;
1191	memcpy(pbMsrBitmapCur, pbMsrBitmap0, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1192	pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hmr0.s.svm.HCPhysMsrBitmap;
1193
1194	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1195	Assert(pVmcbCtrlCur->u32VmcbCleanBits == 0);
1196
1197	/* Verify our assumption that GIM providers trap #UD uniformly across VCPUs initially. */
1198	Assert(pVCpuCur->hm.s.fGIMTrapXcptUD == pVCpu0->hm.s.fGIMTrapXcptUD);
1199	}
1200
1201	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1202	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool fUseVGif=%RTbool fUseVirtVmsaveVmload=%RTbool\n", fUsePauseFilter,
1203	fUseLbrVirt, fUseVGif, fUseVirtVmsaveVmload));
1204	#else
1205	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool\n", fUsePauseFilter, fUseLbrVirt));
1206	#endif
1207	return VINF_SUCCESS;
1208	}
1209
1210
1211	/**
1212	* Gets a pointer to the currently active guest (or nested-guest) VMCB.
1213	*
1214	* @returns Pointer to the current context VMCB.
1215	* @param pVCpu The cross context virtual CPU structure.
1216	*/
1217	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPUCC pVCpu)
1218	{
1219	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1220	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1221	return pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
1222	#endif
1223	return pVCpu->hmr0.s.svm.pVmcb;
1224	}
1225
1226
1227	/**
1228	* Gets a pointer to the nested-guest VMCB cache.
1229	*
1230	* @returns Pointer to the nested-guest VMCB cache.
1231	* @param pVCpu The cross context virtual CPU structure.
1232	*/
1233	DECLINLINE(PSVMNESTEDVMCBCACHE) hmR0SvmGetNestedVmcbCache(PVMCPUCC pVCpu)
1234	{
1235	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1236	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
1237	return &pVCpu->hm.s.svm.NstGstVmcbCache;
1238	#else
1239	RT_NOREF(pVCpu);
1240	return NULL;
1241	#endif
1242	}
1243
1244
1245	/**
1246	* Invalidates a guest page by guest virtual address.
1247	*
1248	* @returns VBox status code.
1249	* @param pVCpu The cross context virtual CPU structure.
1250	* @param GCVirt Guest virtual address of the page to invalidate.
1251	*/
1252	VMMR0DECL(int) SVMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
1253	{
1254	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
1255
1256	bool const fFlushPending = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH) \|\| pVCpu->CTX_SUFF(pVM)->hmr0.s.svm.fAlwaysFlushTLB;
1257
1258	/* Skip it if a TLB flush is already pending. */
1259	if (!fFlushPending)
1260	{
1261	Log4Func(("%#RGv\n", GCVirt));
1262
1263	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
1264	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1265
1266	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1267	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1268	}
1269	return VINF_SUCCESS;
1270	}
1271
1272
1273	/**
1274	* Flushes the appropriate tagged-TLB entries.
1275	*
1276	* @param pHostCpu The HM physical-CPU structure.
1277	* @param pVCpu The cross context virtual CPU structure.
1278	* @param pVmcb Pointer to the VM control block.
1279	*/
1280	static void hmR0SvmFlushTaggedTlb(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1281	{
1282	/*
1283	* Force a TLB flush for the first world switch if the current CPU differs from the one
1284	* we ran on last. This can happen both for start & resume due to long jumps back to
1285	* ring-3.
1286	*
1287	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no
1288	* correlation between it and the physical CPU.
1289	*
1290	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while
1291	* flushing the TLB, so we cannot reuse the ASIDs without flushing.
1292	*/
1293	bool fNewAsid = false;
1294	Assert(pHostCpu->idCpu != NIL_RTCPUID);
1295	if ( pVCpu->hmr0.s.idLastCpu != pHostCpu->idCpu
1296	\|\| pVCpu->hmr0.s.cTlbFlushes != pHostCpu->cTlbFlushes
1297	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1298	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx)
1299	#endif
1300	)
1301	{
1302	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1303	pVCpu->hmr0.s.fForceTLBFlush = true;
1304	fNewAsid = true;
1305	}
1306
1307	/* Set TLB flush state as checked until we return from the world switch. */
1308	ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1309
1310	/* Check for explicit TLB flushes. */
1311	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1312	{
1313	pVCpu->hmr0.s.fForceTLBFlush = true;
1314	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1315	}
1316
1317	/*
1318	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1319	* This Host CPU requirement takes precedence.
1320	*/
1321	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1322	if (pVM->hmr0.s.svm.fAlwaysFlushTLB)
1323	{
1324	pHostCpu->uCurrentAsid = 1;
1325	pVCpu->hmr0.s.uCurrentAsid = 1;
1326	pVCpu->hmr0.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1327	pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
1328	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1329
1330	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1331	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1332	}
1333	else
1334	{
1335	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1336	if (pVCpu->hmr0.s.fForceTLBFlush)
1337	{
1338	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1339	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1340
1341	if (fNewAsid)
1342	{
1343	++pHostCpu->uCurrentAsid;
1344
1345	bool fHitASIDLimit = false;
1346	if (pHostCpu->uCurrentAsid >= g_uHmMaxAsid)
1347	{
1348	pHostCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1349	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1350	fHitASIDLimit = true;
1351	}
1352
1353	if ( fHitASIDLimit
1354	\|\| pHostCpu->fFlushAsidBeforeUse)
1355	{
1356	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1357	pHostCpu->fFlushAsidBeforeUse = false;
1358	}
1359
1360	pVCpu->hmr0.s.uCurrentAsid = pHostCpu->uCurrentAsid;
1361	pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
1362	pVCpu->hmr0.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1363	}
1364	else
1365	{
1366	if (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1367	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1368	else
1369	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1370	}
1371
1372	pVCpu->hmr0.s.fForceTLBFlush = false;
1373	}
1374	}
1375
1376	/* Update VMCB with the ASID. */
1377	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hmr0.s.uCurrentAsid)
1378	{
1379	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hmr0.s.uCurrentAsid;
1380	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1381	}
1382
1383	AssertMsg(pVCpu->hmr0.s.idLastCpu == pHostCpu->idCpu,
1384	("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hmr0.s.idLastCpu, pHostCpu->idCpu));
1385	AssertMsg(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes,
1386	("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hmr0.s.cTlbFlushes, pHostCpu->cTlbFlushes));
1387	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < g_uHmMaxAsid,
1388	("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
1389	AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < g_uHmMaxAsid,
1390	("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid));
1391
1392	#ifdef VBOX_WITH_STATISTICS
1393	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1394	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1395	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1396	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1397	{
1398	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1399	}
1400	else
1401	{
1402	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1403	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1404	}
1405	#endif
1406	}
1407
1408
1409	/**
1410	* Sets an exception intercept in the specified VMCB.
1411	*
1412	* @param pVmcb Pointer to the VM control block.
1413	* @param uXcpt The exception (X86_XCPT_*).
1414	*/
1415	DECLINLINE(void) hmR0SvmSetXcptIntercept(PSVMVMCB pVmcb, uint8_t uXcpt)
1416	{
1417	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt)))
1418	{
1419	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(uXcpt);
1420	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1421	}
1422	}
1423
1424
1425	/**
1426	* Clears an exception intercept in the specified VMCB.
1427	*
1428	* @param pVCpu The cross context virtual CPU structure.
1429	* @param pVmcb Pointer to the VM control block.
1430	* @param uXcpt The exception (X86_XCPT_*).
1431	*
1432	* @remarks This takes into account if we're executing a nested-guest and only
1433	* removes the exception intercept if both the guest -and- nested-guest
1434	* are not intercepting it.
1435	*/
1436	DECLINLINE(void) hmR0SvmClearXcptIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint8_t uXcpt)
1437	{
1438	Assert(uXcpt != X86_XCPT_DB);
1439	Assert(uXcpt != X86_XCPT_AC);
1440	Assert(uXcpt != X86_XCPT_GP);
1441	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1442	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt))
1443	{
1444	bool fRemove = true;
1445	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1446	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1447	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1448	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1449	{
1450	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1451	fRemove = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(uXcpt));
1452	}
1453	# else
1454	RT_NOREF(pVCpu);
1455	# endif
1456	if (fRemove)
1457	{
1458	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(uXcpt);
1459	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1460	}
1461	}
1462	#else
1463	RT_NOREF3(pVCpu, pVmcb, uXcpt);
1464	#endif
1465	}
1466
1467
1468	/**
1469	* Sets a control intercept in the specified VMCB.
1470	*
1471	* @param pVmcb Pointer to the VM control block.
1472	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1473	*/
1474	DECLINLINE(void) hmR0SvmSetCtrlIntercept(PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1475	{
1476	if (!(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept))
1477	{
1478	pVmcb->ctrl.u64InterceptCtrl \|= fCtrlIntercept;
1479	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1480	}
1481	}
1482
1483
1484	/**
1485	* Clears a control intercept in the specified VMCB.
1486	*
1487	* @returns @c true if the intercept is still set, @c false otherwise.
1488	* @param pVCpu The cross context virtual CPU structure.
1489	* @param pVmcb Pointer to the VM control block.
1490	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1491	*
1492	* @remarks This takes into account if we're executing a nested-guest and only
1493	* removes the control intercept if both the guest -and- nested-guest
1494	* are not intercepting it.
1495	*/
1496	static bool hmR0SvmClearCtrlIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1497	{
1498	if (pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept)
1499	{
1500	bool fRemove = true;
1501	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1502	/* Only remove the control intercept if the nested-guest is also not intercepting it! */
1503	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1504	{
1505	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1506	fRemove = !(pVmcbNstGstCache->u64InterceptCtrl & fCtrlIntercept);
1507	}
1508	#else
1509	RT_NOREF(pVCpu);
1510	#endif
1511	if (fRemove)
1512	{
1513	pVmcb->ctrl.u64InterceptCtrl &= ~fCtrlIntercept;
1514	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1515	}
1516	}
1517
1518	return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept);
1519	}
1520
1521
1522	/**
1523	* Exports the guest (or nested-guest) CR0 into the VMCB.
1524	*
1525	* @param pVCpu The cross context virtual CPU structure.
1526	* @param pVmcb Pointer to the VM control block.
1527	*
1528	* @remarks This assumes we always pre-load the guest FPU.
1529	* @remarks No-long-jump zone!!!
1530	*/
1531	static void hmR0SvmExportGuestCR0(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1532	{
1533	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1534
1535	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1536	uint64_t const uGuestCr0 = pCtx->cr0;
1537	uint64_t uShadowCr0 = uGuestCr0;
1538
1539	/* Always enable caching. */
1540	uShadowCr0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1541
1542	/* When Nested Paging is not available use shadow page tables and intercept #PFs (latter done in SVMR0SetupVM()). */
1543	if (!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging)
1544	{
1545	uShadowCr0 \|= X86_CR0_PG /* Use shadow page tables. */
1546	\| X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1547	}
1548
1549	/*
1550	* Use the #MF style of legacy-FPU error reporting for now. Although AMD-V has MSRs that
1551	* lets us isolate the host from it, IEM/REM still needs work to emulate it properly,
1552	* see @bugref{7243#c103}.
1553	*/
1554	if (!(uGuestCr0 & X86_CR0_NE))
1555	{
1556	uShadowCr0 \|= X86_CR0_NE;
1557	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_MF);
1558	}
1559	else
1560	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_MF);
1561
1562	/*
1563	* If the shadow and guest CR0 are identical we can avoid intercepting CR0 reads.
1564	*
1565	* CR0 writes still needs interception as PGM requires tracking paging mode changes,
1566	* see @bugref{6944}.
1567	*
1568	* We also don't ever want to honor weird things like cache disable from the guest.
1569	* However, we can avoid intercepting changes to the TS & MP bits by clearing the CR0
1570	* write intercept below and keeping SVM_CTRL_INTERCEPT_CR0_SEL_WRITE instead.
1571	*/
1572	if (uShadowCr0 == uGuestCr0)
1573	{
1574	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1575	{
1576	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(0);
1577	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(0);
1578	Assert(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_CR0_SEL_WRITE);
1579	}
1580	else
1581	{
1582	/* If the nested-hypervisor intercepts CR0 reads/writes, we need to continue intercepting them. */
1583	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1584	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(0))
1585	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(0));
1586	pVmcb->ctrl.u16InterceptWrCRx = (pVmcb->ctrl.u16InterceptWrCRx & ~RT_BIT(0))
1587	\| (pVmcbNstGstCache->u16InterceptWrCRx & RT_BIT(0));
1588	}
1589	}
1590	else
1591	{
1592	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(0);
1593	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(0);
1594	}
1595	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1596
1597	Assert(!RT_HI_U32(uShadowCr0));
1598	if (pVmcb->guest.u64CR0 != uShadowCr0)
1599	{
1600	pVmcb->guest.u64CR0 = uShadowCr0;
1601	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1602	}
1603	}
1604
1605
1606	/**
1607	* Exports the guest (or nested-guest) CR3 into the VMCB.
1608	*
1609	* @param pVCpu The cross context virtual CPU structure.
1610	* @param pVmcb Pointer to the VM control block.
1611	*
1612	* @remarks No-long-jump zone!!!
1613	*/
1614	static void hmR0SvmExportGuestCR3(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1615	{
1616	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1617
1618	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1619	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1620	if (pVM->hmr0.s.fNestedPaging)
1621	{
1622	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetHyperCR3(pVCpu);
1623	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1624	pVmcb->guest.u64CR3 = pCtx->cr3;
1625	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1626	}
1627	else
1628	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1629
1630	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1631	}
1632
1633
1634	/**
1635	* Exports the guest (or nested-guest) CR4 into the VMCB.
1636	*
1637	* @param pVCpu The cross context virtual CPU structure.
1638	* @param pVmcb Pointer to the VM control block.
1639	*
1640	* @remarks No-long-jump zone!!!
1641	*/
1642	static int hmR0SvmExportGuestCR4(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1643	{
1644	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1645
1646	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1647	uint64_t uShadowCr4 = pCtx->cr4;
1648	if (!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging)
1649	{
1650	switch (pVCpu->hm.s.enmShadowMode)
1651	{
1652	case PGMMODE_REAL:
1653	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1654	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1655
1656	case PGMMODE_32_BIT: /* 32-bit paging. */
1657	uShadowCr4 &= ~X86_CR4_PAE;
1658	break;
1659
1660	case PGMMODE_PAE: /* PAE paging. */
1661	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1662	/** Must use PAE paging as we could use physical memory > 4 GB */
1663	uShadowCr4 \|= X86_CR4_PAE;
1664	break;
1665
1666	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1667	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1668	#ifdef VBOX_WITH_64_BITS_GUESTS
1669	break;
1670	#else
1671	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1672	#endif
1673
1674	default: /* shut up gcc */
1675	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1676	}
1677	}
1678
1679	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1680	bool const fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1681	if (fLoadSaveGuestXcr0 != pVCpu->hmr0.s.fLoadSaveGuestXcr0)
1682	{
1683	pVCpu->hmr0.s.fLoadSaveGuestXcr0 = fLoadSaveGuestXcr0;
1684	hmR0SvmUpdateVmRunFunction(pVCpu);
1685	}
1686
1687	/* Avoid intercepting CR4 reads if the guest and shadow CR4 values are identical. */
1688	if (uShadowCr4 == pCtx->cr4)
1689	{
1690	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1691	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(4);
1692	else
1693	{
1694	/* If the nested-hypervisor intercepts CR4 reads, we need to continue intercepting them. */
1695	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1696	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(4))
1697	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(4));
1698	}
1699	}
1700	else
1701	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(4);
1702
1703	/* CR4 writes are always intercepted (both guest, nested-guest) for tracking PGM mode changes. */
1704	Assert(pVmcb->ctrl.u16InterceptWrCRx & RT_BIT(4));
1705
1706	/* Update VMCB with the shadow CR4 the appropriate VMCB clean bits. */
1707	Assert(!RT_HI_U32(uShadowCr4));
1708	pVmcb->guest.u64CR4 = uShadowCr4;
1709	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_CRX_EFER \| HMSVM_VMCB_CLEAN_INTERCEPTS);
1710
1711	return VINF_SUCCESS;
1712	}
1713
1714
1715	/**
1716	* Exports the guest (or nested-guest) control registers into the VMCB.
1717	*
1718	* @returns VBox status code.
1719	* @param pVCpu The cross context virtual CPU structure.
1720	* @param pVmcb Pointer to the VM control block.
1721	*
1722	* @remarks No-long-jump zone!!!
1723	*/
1724	static int hmR0SvmExportGuestControlRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1725	{
1726	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1727
1728	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR_MASK)
1729	{
1730	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR0)
1731	hmR0SvmExportGuestCR0(pVCpu, pVmcb);
1732
1733	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR2)
1734	{
1735	pVmcb->guest.u64CR2 = pVCpu->cpum.GstCtx.cr2;
1736	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1737	}
1738
1739	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR3)
1740	hmR0SvmExportGuestCR3(pVCpu, pVmcb);
1741
1742	/* CR4 re-loading is ASSUMED to be done everytime we get in from ring-3! (XCR0) */
1743	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR4)
1744	{
1745	int rc = hmR0SvmExportGuestCR4(pVCpu, pVmcb);
1746	if (RT_FAILURE(rc))
1747	return rc;
1748	}
1749
1750	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_CR_MASK;
1751	}
1752	return VINF_SUCCESS;
1753	}
1754
1755
1756	/**
1757	* Exports the guest (or nested-guest) segment registers into the VMCB.
1758	*
1759	* @returns VBox status code.
1760	* @param pVCpu The cross context virtual CPU structure.
1761	* @param pVmcb Pointer to the VM control block.
1762	*
1763	* @remarks No-long-jump zone!!!
1764	*/
1765	static void hmR0SvmExportGuestSegmentRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1766	{
1767	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1768	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1769
1770	/* Guest segment registers. */
1771	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SREG_MASK)
1772	{
1773	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CS)
1774	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1775
1776	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SS)
1777	{
1778	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1779	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1780	}
1781
1782	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DS)
1783	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1784
1785	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_ES)
1786	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1787
1788	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_FS)
1789	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1790
1791	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GS)
1792	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1793
1794	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1795	}
1796
1797	/* Guest TR. */
1798	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_TR)
1799	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1800
1801	/* Guest LDTR. */
1802	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_LDTR)
1803	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1804
1805	/* Guest GDTR. */
1806	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GDTR)
1807	{
1808	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1809	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1810	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1811	}
1812
1813	/* Guest IDTR. */
1814	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_IDTR)
1815	{
1816	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1817	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1818	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1819	}
1820
1821	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SREG_MASK
1822	\| HM_CHANGED_GUEST_TABLE_MASK);
1823	}
1824
1825
1826	/**
1827	* Exports the guest (or nested-guest) MSRs into the VMCB.
1828	*
1829	* @param pVCpu The cross context virtual CPU structure.
1830	* @param pVmcb Pointer to the VM control block.
1831	*
1832	* @remarks No-long-jump zone!!!
1833	*/
1834	static void hmR0SvmExportGuestMsrs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1835	{
1836	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1837	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1838
1839	/* Guest Sysenter MSRs. */
1840	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
1841	{
1842	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
1843	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1844
1845	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
1846	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1847
1848	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
1849	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1850	}
1851
1852	/*
1853	* Guest EFER MSR.
1854	* AMD-V requires guest EFER.SVME to be set. Weird.
1855	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1856	*/
1857	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_EFER_MSR)
1858	{
1859	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1860	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1861	}
1862
1863	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit, otherwise SVM expects amd64 shadow paging. */
1864	if ( !CPUMIsGuestInLongModeEx(pCtx)
1865	&& (pCtx->msrEFER & MSR_K6_EFER_LME))
1866	{
1867	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1868	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1869	}
1870
1871	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSCALL_MSRS)
1872	{
1873	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1874	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1875	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1876	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1877	}
1878
1879	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_KERNEL_GS_BASE)
1880	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1881
1882	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SYSENTER_MSR_MASK
1883	\| HM_CHANGED_GUEST_EFER_MSR
1884	\| HM_CHANGED_GUEST_SYSCALL_MSRS
1885	\| HM_CHANGED_GUEST_KERNEL_GS_BASE);
1886
1887	/*
1888	* Setup the PAT MSR (applicable for Nested Paging only).
1889	*
1890	* The default value should be MSR_IA32_CR_PAT_INIT_VAL, but we treat all guest memory
1891	* as WB, so choose type 6 for all PAT slots, see @bugref{9634}.
1892	*
1893	* While guests can modify and see the modified values through the shadow values,
1894	* we shall not honor any guest modifications of this MSR to ensure caching is always
1895	* enabled similar to how we clear CR0.CD and NW bits.
1896	*
1897	* For nested-guests this needs to always be set as well, see @bugref{7243#c109}.
1898	*/
1899	pVmcb->guest.u64PAT = UINT64_C(0x0006060606060606);
1900
1901	/* Enable the last branch record bit if LBR virtualization is enabled. */
1902	if (pVmcb->ctrl.LbrVirt.n.u1LbrVirt)
1903	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
1904	}
1905
1906
1907	/**
1908	* Exports the guest (or nested-guest) debug state into the VMCB and programs
1909	* the necessary intercepts accordingly.
1910	*
1911	* @param pVCpu The cross context virtual CPU structure.
1912	* @param pVmcb Pointer to the VM control block.
1913	*
1914	* @remarks No-long-jump zone!!!
1915	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1916	*/
1917	static void hmR0SvmExportSharedDebugState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1918	{
1919	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1920
1921	/** @todo Figure out stepping with nested-guest. */
1922	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1923	{
1924	/*
1925	* We don't want to always intercept DRx read/writes for nested-guests as it causes
1926	* problems when the nested hypervisor isn't intercepting them, see @bugref{10080}.
1927	* Instead, they are strictly only requested when the nested hypervisor intercepts
1928	* them -- handled while merging VMCB controls.
1929	*
1930	* If neither the outer nor the nested-hypervisor is intercepting DRx read/writes,
1931	* then the nested-guest debug state should be actively loaded on the host so that
1932	* nested-guest reads/writes its own debug registers without causing VM-exits.
1933	*/
1934	if ( ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1935	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1936	&& !CPUMIsGuestDebugStateActive(pVCpu))
1937	{
1938	CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
1939	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1940	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1941	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1942	}
1943
1944	pVmcb->guest.u64DR6 = pCtx->dr[6];
1945	pVmcb->guest.u64DR7 = pCtx->dr[7];
1946	return;
1947	}
1948
1949	/*
1950	* Anyone single stepping on the host side? If so, we'll have to use the
1951	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1952	* the VMM level like the VT-x implementations does.
1953	*/
1954	bool fInterceptMovDRx = false;
1955	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1956	if (fStepping)
1957	{
1958	pVCpu->hmr0.s.fClearTrapFlag = true;
1959	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1960	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1961	}
1962
1963	if ( fStepping
1964	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1965	{
1966	/*
1967	* Use the combined guest and host DRx values found in the hypervisor
1968	* register set because the debugger has breakpoints active or someone
1969	* is single stepping on the host side.
1970	*
1971	* Note! DBGF expects a clean DR6 state before executing guest code.
1972	*/
1973	if (!CPUMIsHyperDebugStateActive(pVCpu))
1974	{
1975	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1976	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1977	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1978	}
1979
1980	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1981	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1982	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1983	{
1984	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1985	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1986	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1987	}
1988
1989	/** @todo If we cared, we could optimize to allow the guest to read registers
1990	* with the same values. */
1991	fInterceptMovDRx = true;
1992	pVCpu->hmr0.s.fUsingHyperDR7 = true;
1993	Log5(("hmR0SvmExportSharedDebugState: Loaded hyper DRx\n"));
1994	}
1995	else
1996	{
1997	/*
1998	* Update DR6, DR7 with the guest values if necessary.
1999	*/
2000	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
2001	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
2002	{
2003	pVmcb->guest.u64DR7 = pCtx->dr[7];
2004	pVmcb->guest.u64DR6 = pCtx->dr[6];
2005	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
2006	}
2007	pVCpu->hmr0.s.fUsingHyperDR7 = false;
2008
2009	/*
2010	* If the guest has enabled debug registers, we need to load them prior to
2011	* executing guest code so they'll trigger at the right time.
2012	*/
2013	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
2014	{
2015	if (!CPUMIsGuestDebugStateActive(pVCpu))
2016	{
2017	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
2018	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
2019	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2020	Assert(CPUMIsGuestDebugStateActive(pVCpu));
2021	}
2022	Log5(("hmR0SvmExportSharedDebugState: Loaded guest DRx\n"));
2023	}
2024	/*
2025	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
2026	* intercept #DB as DR6 is updated in the VMCB.
2027	*
2028	* Note! If we cared and dared, we could skip intercepting \#DB here.
2029	* However, \#DB shouldn't be performance critical, so we'll play safe
2030	* and keep the code similar to the VT-x code and always intercept it.
2031	*/
2032	else if (!CPUMIsGuestDebugStateActive(pVCpu))
2033	fInterceptMovDRx = true;
2034	}
2035
2036	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
2037	if (fInterceptMovDRx)
2038	{
2039	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
2040	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
2041	{
2042	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
2043	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
2044	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2045	}
2046	}
2047	else
2048	{
2049	if ( pVmcb->ctrl.u16InterceptRdDRx
2050	\|\| pVmcb->ctrl.u16InterceptWrDRx)
2051	{
2052	pVmcb->ctrl.u16InterceptRdDRx = 0;
2053	pVmcb->ctrl.u16InterceptWrDRx = 0;
2054	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2055	}
2056	}
2057	Log4Func(("DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2058	}
2059
2060	/**
2061	* Exports the hardware virtualization state into the nested-guest
2062	* VMCB.
2063	*
2064	* @param pVCpu The cross context virtual CPU structure.
2065	* @param pVmcb Pointer to the VM control block.
2066	*
2067	* @remarks No-long-jump zone!!!
2068	*/
2069	static void hmR0SvmExportGuestHwvirtState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2070	{
2071	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2072
2073	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_HWVIRT)
2074	{
2075	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
2076	{
2077	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2078	PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
2079
2080	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx); /* Nested VGIF is not supported yet. */
2081	Assert(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF); /* Physical hardware supports VGIF. */
2082	Assert(HMIsSvmVGifActive(pVM)); /* Outer VM has enabled VGIF. */
2083	NOREF(pVM);
2084
2085	pVmcb->ctrl.IntCtrl.n.u1VGif = CPUMGetGuestGif(pCtx);
2086	}
2087
2088	/*
2089	* Ensure the nested-guest pause-filter counters don't exceed the outer guest values esp.
2090	* since SVM doesn't have a preemption timer.
2091	*
2092	* We do this here rather than in hmR0SvmSetupVmcbNested() as we may have been executing the
2093	* nested-guest in IEM incl. PAUSE instructions which would update the pause-filter counters
2094	* and may continue execution in SVM R0 without a nested-guest #VMEXIT in between.
2095	*/
2096	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2097	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2098	uint16_t const uGuestPauseFilterCount = pVM->hm.s.svm.cPauseFilter;
2099	uint16_t const uGuestPauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
2100	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, SVM_CTRL_INTERCEPT_PAUSE))
2101	{
2102	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2103	pVmcbCtrl->u16PauseFilterCount = RT_MIN(pCtx->hwvirt.svm.cPauseFilter, uGuestPauseFilterCount);
2104	pVmcbCtrl->u16PauseFilterThreshold = RT_MIN(pCtx->hwvirt.svm.cPauseFilterThreshold, uGuestPauseFilterThreshold);
2105	}
2106	else
2107	{
2108	/** @todo r=ramshankar: We can turn these assignments into assertions. */
2109	pVmcbCtrl->u16PauseFilterCount = uGuestPauseFilterCount;
2110	pVmcbCtrl->u16PauseFilterThreshold = uGuestPauseFilterThreshold;
2111	}
2112	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2113
2114	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_HWVIRT;
2115	}
2116	}
2117
2118
2119	/**
2120	* Exports the guest APIC TPR state into the VMCB.
2121	*
2122	* @returns VBox status code.
2123	* @param pVCpu The cross context virtual CPU structure.
2124	* @param pVmcb Pointer to the VM control block.
2125	*/
2126	static int hmR0SvmExportGuestApicTpr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2127	{
2128	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2129
2130	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
2131	{
2132	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2133	if ( PDMHasApic(pVM)
2134	&& APICIsEnabled(pVCpu))
2135	{
2136	bool fPendingIntr;
2137	uint8_t u8Tpr;
2138	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
2139	AssertRCReturn(rc, rc);
2140
2141	/* Assume that we need to trap all TPR accesses and thus need not check on
2142	every #VMEXIT if we should update the TPR. */
2143	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
2144	pVCpu->hmr0.s.svm.fSyncVTpr = false;
2145
2146	if (!pVM->hm.s.fTprPatchingActive)
2147	{
2148	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
2149	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
2150
2151	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we
2152	can deliver the interrupt to the guest. */
2153	if (fPendingIntr)
2154	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
2155	else
2156	{
2157	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
2158	pVCpu->hmr0.s.svm.fSyncVTpr = true;
2159	}
2160
2161	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_INT_CTRL);
2162	}
2163	else
2164	{
2165	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
2166	pVmcb->guest.u64LSTAR = u8Tpr;
2167	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hmr0.s.svm.pvMsrBitmap;
2168
2169	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
2170	if (fPendingIntr)
2171	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
2172	else
2173	{
2174	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
2175	pVCpu->hmr0.s.svm.fSyncVTpr = true;
2176	}
2177	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
2178	}
2179	}
2180	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
2181	}
2182	return VINF_SUCCESS;
2183	}
2184
2185
2186	/**
2187	* Sets up the exception interrupts required for guest execution in the VMCB.
2188	*
2189	* @param pVCpu The cross context virtual CPU structure.
2190	* @param pVmcb Pointer to the VM control block.
2191	*
2192	* @remarks No-long-jump zone!!!
2193	*/
2194	static void hmR0SvmExportGuestXcptIntercepts(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2195	{
2196	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2197
2198	/* If we modify intercepts from here, please check & adjust hmR0SvmMergeVmcbCtrlsNested() if required. */
2199	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_SVM_XCPT_INTERCEPTS)
2200	{
2201	/* Trap #UD for GIM provider (e.g. for hypercalls). */
2202	if (pVCpu->hm.s.fGIMTrapXcptUD \|\| pVCpu->hm.s.svm.fEmulateLongModeSysEnterExit)
2203	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_UD);
2204	else
2205	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_UD);
2206
2207	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
2208	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2209	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_BP);
2210	else
2211	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_BP);
2212
2213	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmExportGuestCR0(). */
2214	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_SVM_XCPT_INTERCEPTS);
2215	}
2216	}
2217
2218
2219	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2220	/**
2221	* Merges guest and nested-guest intercepts for executing the nested-guest using
2222	* hardware-assisted SVM.
2223	*
2224	* This merges the guest and nested-guest intercepts in a way that if the outer
2225	* guest intercept is set we need to intercept it in the nested-guest as
2226	* well.
2227	*
2228	* @param pVCpu The cross context virtual CPU structure.
2229	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2230	*/
2231	static void hmR0SvmMergeVmcbCtrlsNested(PVMCPUCC pVCpu)
2232	{
2233	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2234	PCSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
2235	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2236	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2237
2238	/* Merge the guest's CR intercepts into the nested-guest VMCB. */
2239	pVmcbNstGstCtrl->u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
2240	pVmcbNstGstCtrl->u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
2241
2242	/* Always intercept CR4 writes for tracking PGM mode changes. */
2243	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(4);
2244
2245	/* Without nested paging, intercept CR3 reads and writes as we load shadow page tables. */
2246	if (!pVM->hmr0.s.fNestedPaging)
2247	{
2248	pVmcbNstGstCtrl->u16InterceptRdCRx \|= RT_BIT(3);
2249	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(3);
2250	}
2251
2252	/* Merge the guest's DR intercepts into the nested-guest VMCB. */
2253	pVmcbNstGstCtrl->u16InterceptRdDRx \|= pVmcb->ctrl.u16InterceptRdDRx;
2254	pVmcbNstGstCtrl->u16InterceptWrDRx \|= pVmcb->ctrl.u16InterceptWrDRx;
2255
2256	/*
2257	* Merge the guest's exception intercepts into the nested-guest VMCB.
2258	*
2259	* - #UD: Exclude these as the outer guest's GIM hypercalls are not applicable
2260	* while executing the nested-guest.
2261	*
2262	* - #BP: Exclude breakpoints set by the VM debugger for the outer guest. This can
2263	* be tweaked later depending on how we wish to implement breakpoints.
2264	*
2265	* - #GP: Exclude these as it's the inner VMMs problem to get vmsvga 3d drivers
2266	* loaded into their guests, not ours.
2267	*
2268	* Warning!! This ASSUMES we only intercept \#UD for hypercall purposes and \#BP
2269	* for VM debugger breakpoints, see hmR0SvmExportGuestXcptIntercepts().
2270	*/
2271	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2272	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt
2273	& ~( RT_BIT(X86_XCPT_UD)
2274	\| RT_BIT(X86_XCPT_BP)
2275	\| (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv ? RT_BIT(X86_XCPT_GP) : 0));
2276	#else
2277	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2278	#endif
2279
2280	/*
2281	* Adjust intercepts while executing the nested-guest that differ from the
2282	* outer guest intercepts.
2283	*
2284	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2285	* that belong to the nested-guest to the outer guest.
2286	*
2287	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2288	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2289	*/
2290	pVmcbNstGstCtrl->u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ~( SVM_CTRL_INTERCEPT_VINTR
2291	\| SVM_CTRL_INTERCEPT_VMMCALL))
2292	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2293
2294	Assert( (pVmcbNstGstCtrl->u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2295	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2296
2297	/* Finally, update the VMCB clean bits. */
2298	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2299	}
2300	#endif
2301
2302
2303	/**
2304	* Enters the AMD-V session.
2305	*
2306	* @returns VBox status code.
2307	* @param pVCpu The cross context virtual CPU structure.
2308	*/
2309	VMMR0DECL(int) SVMR0Enter(PVMCPUCC pVCpu)
2310	{
2311	AssertPtr(pVCpu);
2312	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
2313	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2314
2315	LogFlowFunc(("pVCpu=%p\n", pVCpu));
2316	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2317	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2318
2319	pVCpu->hmr0.s.fLeaveDone = false;
2320	return VINF_SUCCESS;
2321	}
2322
2323
2324	/**
2325	* Thread-context callback for AMD-V.
2326	*
2327	* This is used together with RTThreadCtxHookCreate() on platforms which
2328	* supports it, and directly from VMMR0EmtPrepareForBlocking() and
2329	* VMMR0EmtResumeAfterBlocking() on platforms which don't.
2330	*
2331	* @param enmEvent The thread-context event.
2332	* @param pVCpu The cross context virtual CPU structure.
2333	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2334	* @thread EMT(pVCpu)
2335	*/
2336	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
2337	{
2338	NOREF(fGlobalInit);
2339
2340	switch (enmEvent)
2341	{
2342	case RTTHREADCTXEVENT_OUT:
2343	{
2344	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2345	VMCPU_ASSERT_EMT(pVCpu);
2346
2347	/* No longjmps (log-flush, locks) in this fragile context. */
2348	VMMRZCallRing3Disable(pVCpu);
2349
2350	if (!pVCpu->hmr0.s.fLeaveDone)
2351	{
2352	hmR0SvmLeave(pVCpu, false /* fImportState */);
2353	pVCpu->hmr0.s.fLeaveDone = true;
2354	}
2355
2356	/* Leave HM context, takes care of local init (term). */
2357	int rc = HMR0LeaveCpu(pVCpu);
2358	AssertRC(rc); NOREF(rc);
2359
2360	/* Restore longjmp state. */
2361	VMMRZCallRing3Enable(pVCpu);
2362	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2363	break;
2364	}
2365
2366	case RTTHREADCTXEVENT_IN:
2367	{
2368	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2369	VMCPU_ASSERT_EMT(pVCpu);
2370
2371	/* No longjmps (log-flush, locks) in this fragile context. */
2372	VMMRZCallRing3Disable(pVCpu);
2373
2374	/*
2375	* Initialize the bare minimum state required for HM. This takes care of
2376	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2377	*/
2378	int rc = hmR0EnterCpu(pVCpu);
2379	AssertRC(rc); NOREF(rc);
2380	Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2381	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2382
2383	pVCpu->hmr0.s.fLeaveDone = false;
2384
2385	/* Restore longjmp state. */
2386	VMMRZCallRing3Enable(pVCpu);
2387	break;
2388	}
2389
2390	default:
2391	break;
2392	}
2393	}
2394
2395
2396	/**
2397	* Saves the host state.
2398	*
2399	* @returns VBox status code.
2400	* @param pVCpu The cross context virtual CPU structure.
2401	*
2402	* @remarks No-long-jump zone!!!
2403	*/
2404	VMMR0DECL(int) SVMR0ExportHostState(PVMCPUCC pVCpu)
2405	{
2406	NOREF(pVCpu);
2407
2408	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2409	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_HOST_CONTEXT);
2410	return VINF_SUCCESS;
2411	}
2412
2413
2414	/**
2415	* Exports the guest or nested-guest state from the virtual-CPU context into the
2416	* VMCB.
2417	*
2418	* Also sets up the appropriate VMRUN function to execute guest or nested-guest
2419	* code based on the virtual-CPU mode.
2420	*
2421	* @returns VBox status code.
2422	* @param pVCpu The cross context virtual CPU structure.
2423	* @param pSvmTransient Pointer to the SVM-transient structure.
2424	*
2425	* @remarks No-long-jump zone!!!
2426	*/
2427	static int hmR0SvmExportGuestState(PVMCPUCC pVCpu, PCSVMTRANSIENT pSvmTransient)
2428	{
2429	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2430
2431	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2432	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2433	Assert(pVmcb);
2434
2435	pVmcb->guest.u64RIP = pCtx->rip;
2436	pVmcb->guest.u64RSP = pCtx->rsp;
2437	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2438	pVmcb->guest.u64RAX = pCtx->rax;
2439
2440	bool const fIsNestedGuest = pSvmTransient->fIsNestedGuest;
2441	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2442
2443	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcb);
2444	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2445	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcb);
2446	hmR0SvmExportGuestMsrs(pVCpu, pVmcb);
2447	hmR0SvmExportGuestHwvirtState(pVCpu, pVmcb);
2448
2449	ASMSetFlags(fEFlags);
2450
2451	if (!fIsNestedGuest)
2452	{
2453	/* hmR0SvmExportGuestApicTpr() must be called -after- hmR0SvmExportGuestMsrs() as we
2454	otherwise we would overwrite the LSTAR MSR that we use for TPR patching. */
2455	hmR0SvmExportGuestApicTpr(pVCpu, pVmcb);
2456	hmR0SvmExportGuestXcptIntercepts(pVCpu, pVmcb);
2457	}
2458
2459	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2460	uint64_t fUnusedMask = HM_CHANGED_GUEST_RIP
2461	\| HM_CHANGED_GUEST_RFLAGS
2462	\| HM_CHANGED_GUEST_GPRS_MASK
2463	\| HM_CHANGED_GUEST_X87
2464	\| HM_CHANGED_GUEST_SSE_AVX
2465	\| HM_CHANGED_GUEST_OTHER_XSAVE
2466	\| HM_CHANGED_GUEST_XCRx
2467	\| HM_CHANGED_GUEST_TSC_AUX
2468	\| HM_CHANGED_GUEST_OTHER_MSRS;
2469	if (fIsNestedGuest)
2470	fUnusedMask \|= HM_CHANGED_SVM_XCPT_INTERCEPTS
2471	\| HM_CHANGED_GUEST_APIC_TPR;
2472
2473	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( fUnusedMask
2474	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_MASK)));
2475
2476	#ifdef VBOX_STRICT
2477	/*
2478	* All of the guest-CPU state and SVM keeper bits should be exported here by now,
2479	* except for the host-context and/or shared host-guest context bits.
2480	*/
2481	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2482	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2483	("fCtxChanged=%#RX64\n", fCtxChanged));
2484
2485	/*
2486	* If we need to log state that isn't always imported, we'll need to import them here.
2487	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2488	*/
2489	hmR0SvmLogState(pVCpu, pVmcb, "hmR0SvmExportGuestState", 0 /* fFlags /, 0 / uVerbose */);
2490	#endif
2491
2492	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2493	return VINF_SUCCESS;
2494	}
2495
2496
2497	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2498	/**
2499	* Merges the guest and nested-guest MSR permission bitmap.
2500	*
2501	* If the guest is intercepting an MSR we need to intercept it regardless of
2502	* whether the nested-guest is intercepting it or not.
2503	*
2504	* @param pHostCpu The HM physical-CPU structure.
2505	* @param pVCpu The cross context virtual CPU structure.
2506	*
2507	* @remarks No-long-jmp zone!!!
2508	*/
2509	DECLINLINE(void) hmR0SvmMergeMsrpmNested(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu)
2510	{
2511	uint64_t const pu64GstMsrpm = (uint64_t const )pVCpu->hmr0.s.svm.pvMsrBitmap;
2512	uint64_t const pu64NstGstMsrpm = (uint64_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
2513	uint64_t pu64DstMsrpm = (uint64_t )pHostCpu->n.svm.pvNstGstMsrpm;
2514
2515	/* MSRPM bytes from offset 0x1800 are reserved, so we stop merging there. */
2516	uint32_t const offRsvdQwords = 0x1800 >> 3;
2517	for (uint32_t i = 0; i < offRsvdQwords; i++)
2518	pu64DstMsrpm[i] = pu64NstGstMsrpm[i] \| pu64GstMsrpm[i];
2519	}
2520
2521
2522	/**
2523	* Caches the nested-guest VMCB fields before we modify them for execution using
2524	* hardware-assisted SVM.
2525	*
2526	* @returns true if the VMCB was previously already cached, false otherwise.
2527	* @param pVCpu The cross context virtual CPU structure.
2528	*
2529	* @sa HMNotifySvmNstGstVmexit.
2530	*/
2531	static bool hmR0SvmCacheVmcbNested(PVMCPUCC pVCpu)
2532	{
2533	/*
2534	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2535	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2536	*
2537	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2538	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2539	*/
2540	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2541	bool const fWasCached = pVmcbNstGstCache->fCacheValid;
2542	if (!fWasCached)
2543	{
2544	PCSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2545	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2546	pVmcbNstGstCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2547	pVmcbNstGstCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2548	pVmcbNstGstCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2549	pVmcbNstGstCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2550	pVmcbNstGstCache->u16PauseFilterThreshold = pVmcbNstGstCtrl->u16PauseFilterThreshold;
2551	pVmcbNstGstCache->u16PauseFilterCount = pVmcbNstGstCtrl->u16PauseFilterCount;
2552	pVmcbNstGstCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2553	pVmcbNstGstCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2554	pVmcbNstGstCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2555	pVmcbNstGstCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2556	pVmcbNstGstCache->fNestedPaging = pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging;
2557	pVmcbNstGstCache->fLbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2558	pVmcbNstGstCache->fCacheValid = true;
2559	Log4Func(("Cached VMCB fields\n"));
2560	}
2561
2562	return fWasCached;
2563	}
2564
2565
2566	/**
2567	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2568	*
2569	* This is done the first time we enter nested-guest execution using SVM R0
2570	* until the nested-guest \#VMEXIT (not to be confused with physical CPU
2571	* \#VMEXITs which may or may not cause a corresponding nested-guest \#VMEXIT).
2572	*
2573	* @param pVCpu The cross context virtual CPU structure.
2574	*/
2575	static void hmR0SvmSetupVmcbNested(PVMCPUCC pVCpu)
2576	{
2577	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2578	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2579
2580	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2581
2582	/*
2583	* First cache the nested-guest VMCB fields we may potentially modify.
2584	*/
2585	bool const fVmcbCached = hmR0SvmCacheVmcbNested(pVCpu);
2586	if (!fVmcbCached)
2587	{
2588	/*
2589	* The IOPM of the nested-guest can be ignored because the the guest always
2590	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2591	* than the nested-guest IOPM and swap the field back on the #VMEXIT.
2592	*/
2593	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2594
2595	/*
2596	* Use the same nested-paging as the outer guest. We can't dynamically switch off
2597	* nested-paging suddenly while executing a VM (see assertion at the end of
2598	* Trap0eHandler() in PGMAllBth.h).
2599	*/
2600	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging;
2601
2602	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
2603	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = 1;
2604
2605	/*
2606	* Turn off TPR syncing on #VMEXIT for nested-guests as CR8 intercepts are subject
2607	* to the nested-guest intercepts and we always run with V_INTR_MASKING.
2608	*/
2609	pVCpu->hmr0.s.svm.fSyncVTpr = false;
2610
2611	#ifdef DEBUG_ramshankar
2612	/* For debugging purposes - copy the LBR info. from outer guest VMCB. */
2613	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2614	#endif
2615
2616	/*
2617	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2618	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2619	*/
2620	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2621	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2622	\| SVM_CTRL_INTERCEPT_VMLOAD;
2623
2624	/*
2625	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2626	* CLGI/STGI instructions executed by the nested-guest.
2627	*/
2628	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2629	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2630	\| SVM_CTRL_INTERCEPT_STGI;
2631
2632	/* Merge the guest and nested-guest intercepts. */
2633	hmR0SvmMergeVmcbCtrlsNested(pVCpu);
2634
2635	/* Update the VMCB clean bits. */
2636	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2637	}
2638	else
2639	{
2640	Assert(!pVCpu->hmr0.s.svm.fSyncVTpr);
2641	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2642	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
2643	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPagingCfg == pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
2644	}
2645	}
2646	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
2647
2648
2649	/**
2650	* Exports the state shared between the host and guest (or nested-guest) into
2651	* the VMCB.
2652	*
2653	* @param pVCpu The cross context virtual CPU structure.
2654	* @param pVmcb Pointer to the VM control block.
2655	*
2656	* @remarks No-long-jump zone!!!
2657	*/
2658	static void hmR0SvmExportSharedState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2659	{
2660	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2661	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2662
2663	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
2664	hmR0SvmExportSharedDebugState(pVCpu, pVmcb);
2665
2666	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
2667	AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE),
2668	("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
2669	}
2670
2671
2672	/**
2673	* Worker for SVMR0ImportStateOnDemand.
2674	*
2675	* @param pVCpu The cross context virtual CPU structure.
2676	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2677	*/
2678	static void hmR0SvmImportGuestState(PVMCPUCC pVCpu, uint64_t fWhat)
2679	{
2680	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
2681
2682	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2683	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2684	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
2685	PCSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2686
2687	/*
2688	* We disable interrupts to make the updating of the state and in particular
2689	* the fExtrn modification atomic wrt to preemption hooks.
2690	*/
2691	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2692
2693	fWhat &= pCtx->fExtrn;
2694	if (fWhat)
2695	{
2696	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2697	if (fWhat & CPUMCTX_EXTRN_HWVIRT)
2698	{
2699	if (pVmcbCtrl->IntCtrl.n.u1VGifEnable)
2700	{
2701	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx)); /* We don't yet support passing VGIF feature to the guest. */
2702	Assert(HMIsSvmVGifActive(pVCpu->CTX_SUFF(pVM))); /* VM has configured it. */
2703	CPUMSetGuestGif(pCtx, pVmcbCtrl->IntCtrl.n.u1VGif);
2704	}
2705	}
2706
2707	if (fWhat & CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
2708	{
2709	if ( !pVmcbCtrl->IntCtrl.n.u1VIrqPending
2710	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
2711	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
2712	}
2713	#endif
2714
2715	if (fWhat & CPUMCTX_EXTRN_HM_SVM_INT_SHADOW)
2716	{
2717	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
2718	EMSetInhibitInterruptsPC(pVCpu, pVmcbGuest->u64RIP);
2719	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2720	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2721	}
2722
2723	if (fWhat & CPUMCTX_EXTRN_RIP)
2724	pCtx->rip = pVmcbGuest->u64RIP;
2725
2726	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
2727	pCtx->eflags.u32 = pVmcbGuest->u64RFlags;
2728
2729	if (fWhat & CPUMCTX_EXTRN_RSP)
2730	pCtx->rsp = pVmcbGuest->u64RSP;
2731
2732	if (fWhat & CPUMCTX_EXTRN_RAX)
2733	pCtx->rax = pVmcbGuest->u64RAX;
2734
2735	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
2736	{
2737	if (fWhat & CPUMCTX_EXTRN_CS)
2738	{
2739	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, CS, cs);
2740	/* Correct the CS granularity bit. Haven't seen it being wrong in any other register (yet). */
2741	/** @todo SELM might need to be fixed as it too should not care about the
2742	* granularity bit. See @bugref{6785}. */
2743	if ( !pCtx->cs.Attr.n.u1Granularity
2744	&& pCtx->cs.Attr.n.u1Present
2745	&& pCtx->cs.u32Limit > UINT32_C(0xfffff))
2746	{
2747	Assert((pCtx->cs.u32Limit & 0xfff) == 0xfff);
2748	pCtx->cs.Attr.n.u1Granularity = 1;
2749	}
2750	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, cs);
2751	}
2752	if (fWhat & CPUMCTX_EXTRN_SS)
2753	{
2754	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, SS, ss);
2755	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ss);
2756	/*
2757	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the
2758	* VMCB and uses that and thus it's possible that when the CPL changes during
2759	* guest execution that the SS DPL isn't updated by AMD-V. Observed on some
2760	* AMD Fusion CPUs with 64-bit guests.
2761	*
2762	* See AMD spec. 15.5.1 "Basic operation".
2763	*/
2764	Assert(!(pVmcbGuest->u8CPL & ~0x3));
2765	uint8_t const uCpl = pVmcbGuest->u8CPL;
2766	if (pCtx->ss.Attr.n.u2Dpl != uCpl)
2767	pCtx->ss.Attr.n.u2Dpl = uCpl & 0x3;
2768	}
2769	if (fWhat & CPUMCTX_EXTRN_DS)
2770	{
2771	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, DS, ds);
2772	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ds);
2773	}
2774	if (fWhat & CPUMCTX_EXTRN_ES)
2775	{
2776	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, ES, es);
2777	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, es);
2778	}
2779	if (fWhat & CPUMCTX_EXTRN_FS)
2780	{
2781	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, FS, fs);
2782	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, fs);
2783	}
2784	if (fWhat & CPUMCTX_EXTRN_GS)
2785	{
2786	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, GS, gs);
2787	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, gs);
2788	}
2789	}
2790
2791	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
2792	{
2793	if (fWhat & CPUMCTX_EXTRN_TR)
2794	{
2795	/*
2796	* Fixup TR attributes so it's compatible with Intel. Important when saved-states
2797	* are used between Intel and AMD, see @bugref{6208#c39}.
2798	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2799	*/
2800	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, TR, tr);
2801	if (pCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2802	{
2803	if ( pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2804	\|\| CPUMIsGuestInLongModeEx(pCtx))
2805	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2806	else if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2807	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2808	}
2809	}
2810
2811	if (fWhat & CPUMCTX_EXTRN_LDTR)
2812	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, LDTR, ldtr);
2813
2814	if (fWhat & CPUMCTX_EXTRN_GDTR)
2815	{
2816	pCtx->gdtr.cbGdt = pVmcbGuest->GDTR.u32Limit;
2817	pCtx->gdtr.pGdt = pVmcbGuest->GDTR.u64Base;
2818	}
2819
2820	if (fWhat & CPUMCTX_EXTRN_IDTR)
2821	{
2822	pCtx->idtr.cbIdt = pVmcbGuest->IDTR.u32Limit;
2823	pCtx->idtr.pIdt = pVmcbGuest->IDTR.u64Base;
2824	}
2825	}
2826
2827	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
2828	{
2829	pCtx->msrSTAR = pVmcbGuest->u64STAR;
2830	pCtx->msrLSTAR = pVmcbGuest->u64LSTAR;
2831	pCtx->msrCSTAR = pVmcbGuest->u64CSTAR;
2832	pCtx->msrSFMASK = pVmcbGuest->u64SFMASK;
2833	}
2834
2835	if ( (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
2836	&& !pVCpu->hm.s.svm.fEmulateLongModeSysEnterExit /* Intercepted. AMD-V would clear the high 32 bits of EIP & ESP. */)
2837	{
2838	pCtx->SysEnter.cs = pVmcbGuest->u64SysEnterCS;
2839	pCtx->SysEnter.eip = pVmcbGuest->u64SysEnterEIP;
2840	pCtx->SysEnter.esp = pVmcbGuest->u64SysEnterESP;
2841	}
2842
2843	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
2844	pCtx->msrKERNELGSBASE = pVmcbGuest->u64KernelGSBase;
2845
2846	if (fWhat & CPUMCTX_EXTRN_DR_MASK)
2847	{
2848	if (fWhat & CPUMCTX_EXTRN_DR6)
2849	{
2850	if (!pVCpu->hmr0.s.fUsingHyperDR7)
2851	pCtx->dr[6] = pVmcbGuest->u64DR6;
2852	else
2853	CPUMSetHyperDR6(pVCpu, pVmcbGuest->u64DR6);
2854	}
2855
2856	if (fWhat & CPUMCTX_EXTRN_DR7)
2857	{
2858	if (!pVCpu->hmr0.s.fUsingHyperDR7)
2859	pCtx->dr[7] = pVmcbGuest->u64DR7;
2860	else
2861	Assert(pVmcbGuest->u64DR7 == CPUMGetHyperDR7(pVCpu));
2862	}
2863	}
2864
2865	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
2866	{
2867	if (fWhat & CPUMCTX_EXTRN_CR0)
2868	{
2869	/* We intercept changes to all CR0 bits except maybe TS & MP bits. */
2870	uint64_t const uCr0 = (pCtx->cr0 & ~(X86_CR0_TS \| X86_CR0_MP))
2871	\| (pVmcbGuest->u64CR0 & (X86_CR0_TS \| X86_CR0_MP));
2872	VMMRZCallRing3Disable(pVCpu); /* Calls into PGM which has Log statements. */
2873	CPUMSetGuestCR0(pVCpu, uCr0);
2874	VMMRZCallRing3Enable(pVCpu);
2875	}
2876
2877	if (fWhat & CPUMCTX_EXTRN_CR2)
2878	pCtx->cr2 = pVmcbGuest->u64CR2;
2879
2880	if (fWhat & CPUMCTX_EXTRN_CR3)
2881	{
2882	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
2883	&& pCtx->cr3 != pVmcbGuest->u64CR3)
2884	{
2885	CPUMSetGuestCR3(pVCpu, pVmcbGuest->u64CR3);
2886	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2887	}
2888	}
2889
2890	/* Changes to CR4 are always intercepted. */
2891	}
2892
2893	/* Update fExtrn. */
2894	pCtx->fExtrn &= ~fWhat;
2895
2896	/* If everything has been imported, clear the HM keeper bit. */
2897	if (!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL))
2898	{
2899	pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
2900	Assert(!pCtx->fExtrn);
2901	}
2902	}
2903	else
2904	Assert(!pCtx->fExtrn \|\| (pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
2905
2906	ASMSetFlags(fEFlags);
2907
2908	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatImportGuestState, x);
2909
2910	/*
2911	* Honor any pending CR3 updates.
2912	*
2913	* Consider this scenario: #VMEXIT -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp
2914	* -> SVMR0CallRing3Callback() -> VMMRZCallRing3Disable() -> hmR0SvmImportGuestState()
2915	* -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp -> continue with #VMEXIT
2916	* handling -> hmR0SvmImportGuestState() and here we are.
2917	*
2918	* The reason for such complicated handling is because VM-exits that call into PGM expect
2919	* CR3 to be up-to-date and thus any CR3-saves -before- the VM-exit (longjmp) would've
2920	* postponed the CR3 update via the force-flag and cleared CR3 from fExtrn. Any SVM R0
2921	* VM-exit handler that requests CR3 to be saved will end up here and we call PGMUpdateCR3().
2922	*
2923	* The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again,
2924	* and does not process force-flag like regular exits to ring-3 either, we cover for it here.
2925	*/
2926	if ( VMMRZCallRing3IsEnabled(pVCpu)
2927	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
2928	{
2929	AssertMsg(pCtx->cr3 == pVmcbGuest->u64CR3, ("cr3=%#RX64 vmcb_cr3=%#RX64\n", pCtx->cr3, pVmcbGuest->u64CR3));
2930	PGMUpdateCR3(pVCpu, pCtx->cr3);
2931	}
2932	}
2933
2934
2935	/**
2936	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
2937	* context.
2938	*
2939	* Currently there is no residual state left in the CPU that is not updated in the
2940	* VMCB.
2941	*
2942	* @returns VBox status code.
2943	* @param pVCpu The cross context virtual CPU structure.
2944	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2945	*/
2946	VMMR0DECL(int) SVMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
2947	{
2948	hmR0SvmImportGuestState(pVCpu, fWhat);
2949	return VINF_SUCCESS;
2950	}
2951
2952
2953	/**
2954	* Does the necessary state syncing before returning to ring-3 for any reason
2955	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2956	*
2957	* @param pVCpu The cross context virtual CPU structure.
2958	* @param fImportState Whether to import the guest state from the VMCB back
2959	* to the guest-CPU context.
2960	*
2961	* @remarks No-long-jmp zone!!!
2962	*/
2963	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState)
2964	{
2965	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2966	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2967
2968	/*
2969	* !!! IMPORTANT !!!
2970	* If you modify code here, make sure to check whether SVMR0CallRing3Callback() needs to be updated too.
2971	*/
2972
2973	/* Save the guest state if necessary. */
2974	if (fImportState)
2975	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
2976
2977	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2978	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2979	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
2980
2981	/*
2982	* Restore host debug registers if necessary and resync on next R0 reentry.
2983	*/
2984	#ifdef VBOX_STRICT
2985	if (CPUMIsHyperDebugStateActive(pVCpu))
2986	{
2987	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb; /** @todo nested-guest. */
2988	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2989	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2990	}
2991	#endif
2992	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2993	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2994	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2995
2996	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2997	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
2998	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
2999	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
3000	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
3001	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitVmentry);
3002	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3003
3004	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
3005	}
3006
3007
3008	/**
3009	* Leaves the AMD-V session.
3010	*
3011	* Only used while returning to ring-3 either due to longjump or exits to
3012	* ring-3.
3013	*
3014	* @returns VBox status code.
3015	* @param pVCpu The cross context virtual CPU structure.
3016	*/
3017	static int hmR0SvmLeaveSession(PVMCPUCC pVCpu)
3018	{
3019	HM_DISABLE_PREEMPT(pVCpu);
3020	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3021	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3022
3023	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
3024	and done this from the SVMR0ThreadCtxCallback(). */
3025	if (!pVCpu->hmr0.s.fLeaveDone)
3026	{
3027	hmR0SvmLeave(pVCpu, true /* fImportState */);
3028	pVCpu->hmr0.s.fLeaveDone = true;
3029	}
3030
3031	/*
3032	* !!! IMPORTANT !!!
3033	* If you modify code here, make sure to check whether SVMR0CallRing3Callback() needs to be updated too.
3034	*/
3035
3036	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3037	/* Deregister hook now that we've left HM context before re-enabling preemption. */
3038	VMMR0ThreadCtxHookDisable(pVCpu);
3039
3040	/* Leave HM context. This takes care of local init (term). */
3041	int rc = HMR0LeaveCpu(pVCpu);
3042
3043	HM_RESTORE_PREEMPT();
3044	return rc;
3045	}
3046
3047
3048	/**
3049	* Does the necessary state syncing before doing a longjmp to ring-3.
3050	*
3051	* @returns VBox status code.
3052	* @param pVCpu The cross context virtual CPU structure.
3053	*
3054	* @remarks No-long-jmp zone!!!
3055	*/
3056	static int hmR0SvmLongJmpToRing3(PVMCPUCC pVCpu)
3057	{
3058	return hmR0SvmLeaveSession(pVCpu);
3059	}
3060
3061
3062	/**
3063	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
3064	* any remaining host state) before we longjump to ring-3 and possibly get
3065	* preempted.
3066	*
3067	* @param pVCpu The cross context virtual CPU structure.
3068	* @param enmOperation The operation causing the ring-3 longjump.
3069	*/
3070	VMMR0DECL(int) SVMR0CallRing3Callback(PVMCPUCC pVCpu, VMMCALLRING3 enmOperation)
3071	{
3072	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
3073	{
3074	/*
3075	* !!! IMPORTANT !!!
3076	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
3077	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
3078	*/
3079	VMMRZCallRing3RemoveNotification(pVCpu);
3080	VMMRZCallRing3Disable(pVCpu);
3081	HM_DISABLE_PREEMPT(pVCpu);
3082
3083	/* Import the entire guest state. */
3084	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3085
3086	/* Restore host FPU state if necessary and resync on next R0 reentry. */
3087	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
3088
3089	/* Restore host debug registers if necessary and resync on next R0 reentry. */
3090	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3091
3092	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
3093	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3094	VMMR0ThreadCtxHookDisable(pVCpu);
3095
3096	/* Leave HM context. This takes care of local init (term). */
3097	HMR0LeaveCpu(pVCpu);
3098
3099	HM_RESTORE_PREEMPT();
3100	return VINF_SUCCESS;
3101	}
3102
3103	Assert(pVCpu);
3104	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3105	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3106
3107	VMMRZCallRing3Disable(pVCpu);
3108
3109	Log4Func(("Calling hmR0SvmLongJmpToRing3\n"));
3110	int rc = hmR0SvmLongJmpToRing3(pVCpu);
3111	AssertRCReturn(rc, rc);
3112
3113	VMMRZCallRing3Enable(pVCpu);
3114	return VINF_SUCCESS;
3115	}
3116
3117
3118	/**
3119	* Take necessary actions before going back to ring-3.
3120	*
3121	* An action requires us to go back to ring-3. This function does the necessary
3122	* steps before we can safely return to ring-3. This is not the same as longjmps
3123	* to ring-3, this is voluntary.
3124	*
3125	* @returns Strict VBox status code.
3126	* @param pVCpu The cross context virtual CPU structure.
3127	* @param rcExit The reason for exiting to ring-3. Can be
3128	* VINF_VMM_UNKNOWN_RING3_CALL.
3129	*/
3130	static VBOXSTRICTRC hmR0SvmExitToRing3(PVMCPUCC pVCpu, VBOXSTRICTRC rcExit)
3131	{
3132	Assert(pVCpu);
3133	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3134
3135	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
3136	VMMRZCallRing3Disable(pVCpu);
3137	Log4Func(("rcExit=%d LocalFF=%#RX64 GlobalFF=%#RX32\n", VBOXSTRICTRC_VAL(rcExit), (uint64_t)pVCpu->fLocalForcedActions,
3138	pVCpu->CTX_SUFF(pVM)->fGlobalForcedActions));
3139
3140	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
3141	if (pVCpu->hm.s.Event.fPending)
3142	{
3143	hmR0SvmPendingEventToTrpmTrap(pVCpu);
3144	Assert(!pVCpu->hm.s.Event.fPending);
3145	}
3146
3147	/* Sync. the necessary state for going back to ring-3. */
3148	hmR0SvmLeaveSession(pVCpu);
3149	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3150
3151	/* Thread-context hooks are unregistered at this point!!! */
3152	/* Ring-3 callback notifications are unregistered at this point!!! */
3153
3154	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
3155	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
3156	\| CPUM_CHANGED_LDTR
3157	\| CPUM_CHANGED_GDTR
3158	\| CPUM_CHANGED_IDTR
3159	\| CPUM_CHANGED_TR
3160	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
3161	if ( pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging
3162	&& CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
3163	{
3164	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3165	}
3166
3167	/* Update the exit-to-ring 3 reason. */
3168	pVCpu->hm.s.rcLastExitToR3 = VBOXSTRICTRC_VAL(rcExit);
3169
3170	/* On our way back from ring-3, reload the guest-CPU state if it may change while in ring-3. */
3171	if ( rcExit != VINF_EM_RAW_INTERRUPT
3172	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3173	{
3174	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
3175	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
3176	}
3177
3178	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
3179	VMMRZCallRing3Enable(pVCpu);
3180
3181	/*
3182	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
3183	* and if we're injecting an event we should have a TRPM trap pending.
3184	*/
3185	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
3186	pVCpu->hm.s.u32HMError = VBOXSTRICTRC_VAL(rcExit),
3187	VERR_SVM_IPE_5);
3188	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
3189	pVCpu->hm.s.u32HMError = VBOXSTRICTRC_VAL(rcExit),
3190	VERR_SVM_IPE_4);
3191
3192	return rcExit;
3193	}
3194
3195
3196	/**
3197	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
3198	* intercepts.
3199	*
3200	* @param pVCpu The cross context virtual CPU structure.
3201	* @param pVmcb Pointer to the VM control block.
3202	*
3203	* @remarks No-long-jump zone!!!
3204	*/
3205	static void hmR0SvmUpdateTscOffsetting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3206	{
3207	/*
3208	* Avoid intercepting RDTSC/RDTSCP if we determined the host TSC (++) is stable
3209	* and in case of a nested-guest, if the nested-VMCB specifies it is not intercepting
3210	* RDTSC/RDTSCP as well.
3211	*/
3212	bool fParavirtTsc;
3213	uint64_t uTscOffset;
3214	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVCpu->CTX_SUFF(pVM), pVCpu, &uTscOffset, &fParavirtTsc);
3215
3216	bool fIntercept;
3217	if (fCanUseRealTsc)
3218	fIntercept = hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3219	else
3220	{
3221	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3222	fIntercept = true;
3223	}
3224
3225	if (!fIntercept)
3226	{
3227	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3228	/* Apply the nested-guest VMCB's TSC offset over the guest TSC offset. */
3229	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3230	uTscOffset = CPUMApplyNestedGuestTscOffset(pVCpu, uTscOffset);
3231	#endif
3232
3233	/* Update the TSC offset in the VMCB and the relevant clean bits. */
3234	pVmcb->ctrl.u64TSCOffset = uTscOffset;
3235	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3236	}
3237
3238	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3239	information before every VM-entry, hence we have nothing to do here at the moment. */
3240	if (fParavirtTsc)
3241	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3242	}
3243
3244
3245	/**
3246	* Sets an event as a pending event to be injected into the guest.
3247	*
3248	* @param pVCpu The cross context virtual CPU structure.
3249	* @param pEvent Pointer to the SVM event.
3250	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3251	* page-fault.
3252	*
3253	* @remarks Statistics counter assumes this is a guest event being reflected to
3254	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3255	*/
3256	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPUCC pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3257	{
3258	Assert(!pVCpu->hm.s.Event.fPending);
3259	Assert(pEvent->n.u1Valid);
3260
3261	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3262	pVCpu->hm.s.Event.fPending = true;
3263	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3264
3265	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3266	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3267	}
3268
3269
3270	/**
3271	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3272	*
3273	* @param pVCpu The cross context virtual CPU structure.
3274	*/
3275	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPUCC pVCpu)
3276	{
3277	SVMEVENT Event;
3278	Event.u = 0;
3279	Event.n.u1Valid = 1;
3280	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3281	Event.n.u8Vector = X86_XCPT_UD;
3282	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3283	}
3284
3285
3286	/**
3287	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3288	*
3289	* @param pVCpu The cross context virtual CPU structure.
3290	*/
3291	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPUCC pVCpu)
3292	{
3293	SVMEVENT Event;
3294	Event.u = 0;
3295	Event.n.u1Valid = 1;
3296	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3297	Event.n.u8Vector = X86_XCPT_DB;
3298	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3299	}
3300
3301
3302	/**
3303	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3304	*
3305	* @param pVCpu The cross context virtual CPU structure.
3306	* @param u32ErrCode The error-code for the page-fault.
3307	* @param uFaultAddress The page fault address (CR2).
3308	*
3309	* @remarks This updates the guest CR2 with @a uFaultAddress!
3310	*/
3311	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPUCC pVCpu, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3312	{
3313	SVMEVENT Event;
3314	Event.u = 0;
3315	Event.n.u1Valid = 1;
3316	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3317	Event.n.u8Vector = X86_XCPT_PF;
3318	Event.n.u1ErrorCodeValid = 1;
3319	Event.n.u32ErrorCode = u32ErrCode;
3320
3321	/* Update CR2 of the guest. */
3322	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR2);
3323	if (pVCpu->cpum.GstCtx.cr2 != uFaultAddress)
3324	{
3325	pVCpu->cpum.GstCtx.cr2 = uFaultAddress;
3326	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3327	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
3328	}
3329
3330	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3331	}
3332
3333
3334	/**
3335	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3336	*
3337	* @param pVCpu The cross context virtual CPU structure.
3338	*/
3339	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPUCC pVCpu)
3340	{
3341	SVMEVENT Event;
3342	Event.u = 0;
3343	Event.n.u1Valid = 1;
3344	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3345	Event.n.u8Vector = X86_XCPT_MF;
3346	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3347	}
3348
3349
3350	/**
3351	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3352	*
3353	* @param pVCpu The cross context virtual CPU structure.
3354	*/
3355	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPUCC pVCpu)
3356	{
3357	SVMEVENT Event;
3358	Event.u = 0;
3359	Event.n.u1Valid = 1;
3360	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3361	Event.n.u8Vector = X86_XCPT_DF;
3362	Event.n.u1ErrorCodeValid = 1;
3363	Event.n.u32ErrorCode = 0;
3364	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3365	}
3366
3367
3368	/**
3369	* Injects an event into the guest upon VMRUN by updating the relevant field
3370	* in the VMCB.
3371	*
3372	* @param pVCpu The cross context virtual CPU structure.
3373	* @param pVmcb Pointer to the guest VM control block.
3374	* @param pEvent Pointer to the event.
3375	*
3376	* @remarks No-long-jump zone!!!
3377	* @remarks Requires CR0!
3378	*/
3379	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMEVENT pEvent)
3380	{
3381	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3382	pVmcb->ctrl.EventInject.u = pEvent->u;
3383	if ( pVmcb->ctrl.EventInject.n.u3Type == SVM_EVENT_EXCEPTION
3384	\|\| pVmcb->ctrl.EventInject.n.u3Type == SVM_EVENT_NMI)
3385	{
3386	Assert(pEvent->n.u8Vector <= X86_XCPT_LAST);
3387	STAM_COUNTER_INC(&pVCpu->hm.s.aStatInjectedXcpts[pEvent->n.u8Vector]);
3388	}
3389	else
3390	STAM_COUNTER_INC(&pVCpu->hm.s.aStatInjectedIrqs[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3391	RT_NOREF(pVCpu);
3392
3393	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3394	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3395	}
3396
3397
3398
3399	/**
3400	* Converts any TRPM trap into a pending HM event. This is typically used when
3401	* entering from ring-3 (not longjmp returns).
3402	*
3403	* @param pVCpu The cross context virtual CPU structure.
3404	*/
3405	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPUCC pVCpu)
3406	{
3407	Assert(TRPMHasTrap(pVCpu));
3408	Assert(!pVCpu->hm.s.Event.fPending);
3409
3410	uint8_t uVector;
3411	TRPMEVENT enmTrpmEvent;
3412	uint32_t uErrCode;
3413	RTGCUINTPTR GCPtrFaultAddress;
3414	uint8_t cbInstr;
3415
3416	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr, NULL /* pfIcebp */);
3417	AssertRC(rc);
3418
3419	SVMEVENT Event;
3420	Event.u = 0;
3421	Event.n.u1Valid = 1;
3422	Event.n.u8Vector = uVector;
3423
3424	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3425	if (enmTrpmEvent == TRPM_TRAP)
3426	{
3427	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3428	switch (uVector)
3429	{
3430	case X86_XCPT_NMI:
3431	{
3432	Event.n.u3Type = SVM_EVENT_NMI;
3433	break;
3434	}
3435
3436	case X86_XCPT_BP:
3437	case X86_XCPT_OF:
3438	AssertMsgFailed(("Invalid TRPM vector %d for event type %d\n", uVector, enmTrpmEvent));
3439	RT_FALL_THRU();
3440
3441	case X86_XCPT_PF:
3442	case X86_XCPT_DF:
3443	case X86_XCPT_TS:
3444	case X86_XCPT_NP:
3445	case X86_XCPT_SS:
3446	case X86_XCPT_GP:
3447	case X86_XCPT_AC:
3448	{
3449	Event.n.u1ErrorCodeValid = 1;
3450	Event.n.u32ErrorCode = uErrCode;
3451	break;
3452	}
3453	}
3454	}
3455	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3456	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3457	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3458	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3459	else
3460	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3461
3462	rc = TRPMResetTrap(pVCpu);
3463	AssertRC(rc);
3464
3465	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3466	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3467
3468	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3469	}
3470
3471
3472	/**
3473	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3474	* AMD-V to execute any instruction.
3475	*
3476	* @param pVCpu The cross context virtual CPU structure.
3477	*/
3478	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu)
3479	{
3480	Assert(pVCpu->hm.s.Event.fPending);
3481	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3482
3483	SVMEVENT Event;
3484	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3485
3486	uint8_t uVector = Event.n.u8Vector;
3487	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event, uVector);
3488
3489	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, Event.n.u3Type));
3490
3491	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3492	AssertRC(rc);
3493
3494	if (Event.n.u1ErrorCodeValid)
3495	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3496
3497	if ( enmTrapType == TRPM_TRAP
3498	&& uVector == X86_XCPT_PF)
3499	{
3500	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3501	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3502	}
3503	else if (enmTrapType == TRPM_SOFTWARE_INT)
3504	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3505	pVCpu->hm.s.Event.fPending = false;
3506	}
3507
3508
3509	/**
3510	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3511	* now.
3512	*
3513	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3514	* @param pVCpu The cross context virtual CPU structure.
3515	*
3516	* @remarks No-long-jump zone!!!
3517	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3518	*/
3519	static bool hmR0SvmIsIntrShadowActive(PVMCPUCC pVCpu)
3520	{
3521	/*
3522	* Instructions like STI and MOV SS inhibit interrupts till the next instruction
3523	* completes. Check if we should inhibit interrupts or clear any existing
3524	* interrupt inhibition.
3525	*/
3526	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3527	{
3528	if (pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
3529	{
3530	/*
3531	* We can clear the inhibit force flag as even if we go back to the recompiler
3532	* without executing guest code in AMD-V, the flag's condition to be cleared is
3533	* met and thus the cleared state is correct.
3534	*/
3535	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3536	return false;
3537	}
3538	return true;
3539	}
3540	return false;
3541	}
3542
3543
3544	/**
3545	* Sets the virtual interrupt intercept control in the VMCB.
3546	*
3547	* @param pVCpu The cross context virtual CPU structure.
3548	* @param pVmcb Pointer to the VM control block.
3549	*/
3550	static void hmR0SvmSetIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3551	{
3552	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx); NOREF(pVCpu);
3553
3554	/*
3555	* When AVIC isn't supported, set up an interrupt window to cause a #VMEXIT when the guest
3556	* is ready to accept interrupts. At #VMEXIT, we then get the interrupt from the APIC
3557	* (updating ISR at the right time) and inject the interrupt.
3558	*
3559	* With AVIC is supported, we could make use of the asynchronously delivery without
3560	* #VMEXIT and we would be passing the AVIC page to SVM.
3561	*
3562	* In AMD-V, an interrupt window is achieved using a combination of V_IRQ (an interrupt
3563	* is pending), V_IGN_TPR (ignore TPR priorities) and the VINTR intercept all being set.
3564	*/
3565	Assert(pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR);
3566	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3567	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3568	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3569	Log4(("Set VINTR intercept\n"));
3570	}
3571
3572
3573	/**
3574	* Clears the virtual interrupt intercept control in the VMCB as
3575	* we are figured the guest is unable process any interrupts
3576	* at this point of time.
3577	*
3578	* @param pVCpu The cross context virtual CPU structure.
3579	* @param pVmcb Pointer to the VM control block.
3580	*/
3581	static void hmR0SvmClearIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3582	{
3583	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx); NOREF(pVCpu);
3584
3585	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
3586	if ( pVmcbCtrl->IntCtrl.n.u1VIrqPending
3587	\|\| (pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3588	{
3589	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
3590	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3591	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3592	Log4(("Cleared VINTR intercept\n"));
3593	}
3594	}
3595
3596
3597	/**
3598	* Evaluates the event to be delivered to the guest and sets it as the pending
3599	* event.
3600	*
3601	* @returns Strict VBox status code.
3602	* @param pVCpu The cross context virtual CPU structure.
3603	* @param pSvmTransient Pointer to the SVM transient structure.
3604	*/
3605	static VBOXSTRICTRC hmR0SvmEvaluatePendingEvent(PVMCPUCC pVCpu, PCSVMTRANSIENT pSvmTransient)
3606	{
3607	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3608	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3609	\| CPUMCTX_EXTRN_RFLAGS
3610	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
3611	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ);
3612
3613	Assert(!pVCpu->hm.s.Event.fPending);
3614	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3615	Assert(pVmcb);
3616
3617	bool const fGif = CPUMGetGuestGif(pCtx);
3618	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3619	bool const fBlockNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3620
3621	Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fIntShadow=%RTbool fIntPending=%RTbool fNmiPending=%RTbool\n",
3622	fGif, fBlockNmi, fIntShadow, VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3623	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3624
3625	/** @todo SMI. SMIs take priority over NMIs. */
3626
3627	/*
3628	* Check if the guest or nested-guest can receive NMIs.
3629	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3630	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3631	*/
3632	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3633	&& !fBlockNmi)
3634	{
3635	if ( fGif
3636	&& !fIntShadow)
3637	{
3638	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3639	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
3640	{
3641	Log4(("Intercepting NMI -> #VMEXIT\n"));
3642	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3643	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_NMI, 0, 0);
3644	}
3645	#endif
3646	Log4(("Setting NMI pending for injection\n"));
3647	SVMEVENT Event;
3648	Event.u = 0;
3649	Event.n.u1Valid = 1;
3650	Event.n.u8Vector = X86_XCPT_NMI;
3651	Event.n.u3Type = SVM_EVENT_NMI;
3652	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3653	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3654	}
3655	else if (!fGif)
3656	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3657	else if (!pSvmTransient->fIsNestedGuest)
3658	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3659	/* else: for nested-guests, interrupt-window exiting will be picked up when merging VMCB controls. */
3660	}
3661	/*
3662	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt()
3663	* returns a valid interrupt we -must- deliver the interrupt. We can no longer re-request
3664	* it from the APIC device.
3665	*
3666	* For nested-guests, physical interrupts always take priority over virtual interrupts.
3667	* We don't need to inject nested-guest virtual interrupts here, we can let the hardware
3668	* do that work when we execute nested-guest code esp. since all the required information
3669	* is in the VMCB, unlike physical interrupts where we need to fetch the interrupt from
3670	* the virtual interrupt controller.
3671	*
3672	* See AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3673	*/
3674	else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3675	&& !pVCpu->hm.s.fSingleInstruction)
3676	{
3677	bool const fBlockInt = !pSvmTransient->fIsNestedGuest ? !(pCtx->eflags.u32 & X86_EFL_IF)
3678	: CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx);
3679	if ( fGif
3680	&& !fBlockInt
3681	&& !fIntShadow)
3682	{
3683	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3684	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
3685	{
3686	Log4(("Intercepting INTR -> #VMEXIT\n"));
3687	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3688	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3689	}
3690	#endif
3691	uint8_t u8Interrupt;
3692	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3693	if (RT_SUCCESS(rc))
3694	{
3695	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3696	SVMEVENT Event;
3697	Event.u = 0;
3698	Event.n.u1Valid = 1;
3699	Event.n.u8Vector = u8Interrupt;
3700	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3701	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3702	}
3703	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3704	{
3705	/*
3706	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3707	* updated eventually when the TPR is written by the guest.
3708	*/
3709	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3710	}
3711	else
3712	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3713	}
3714	else if (!fGif)
3715	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3716	else if (!pSvmTransient->fIsNestedGuest)
3717	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3718	/* else: for nested-guests, interrupt-window exiting will be picked up when merging VMCB controls. */
3719	}
3720
3721	return VINF_SUCCESS;
3722	}
3723
3724
3725	/**
3726	* Injects any pending events into the guest (or nested-guest).
3727	*
3728	* @param pVCpu The cross context virtual CPU structure.
3729	* @param pVmcb Pointer to the VM control block.
3730	*
3731	* @remarks Must only be called when we are guaranteed to enter
3732	* hardware-assisted SVM execution and not return to ring-3
3733	* prematurely.
3734	*/
3735	static void hmR0SvmInjectPendingEvent(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3736	{
3737	Assert(!TRPMHasTrap(pVCpu));
3738	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3739
3740	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3741	#ifdef VBOX_STRICT
3742	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3743	bool const fGif = CPUMGetGuestGif(pCtx);
3744	bool fAllowInt = fGif;
3745	if (fGif)
3746	{
3747	/*
3748	* For nested-guests we have no way to determine if we're injecting a physical or
3749	* virtual interrupt at this point. Hence the partial verification below.
3750	*/
3751	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3752	fAllowInt = CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx) \|\| CPUMIsGuestSvmVirtIntrEnabled(pVCpu, pCtx);
3753	else
3754	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3755	}
3756	#endif
3757
3758	if (pVCpu->hm.s.Event.fPending)
3759	{
3760	SVMEVENT Event;
3761	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3762	Assert(Event.n.u1Valid);
3763
3764	/*
3765	* Validate event injection pre-conditions.
3766	*/
3767	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3768	{
3769	Assert(fAllowInt);
3770	Assert(!fIntShadow);
3771	}
3772	else if (Event.n.u3Type == SVM_EVENT_NMI)
3773	{
3774	Assert(fGif);
3775	Assert(!fIntShadow);
3776	}
3777
3778	/*
3779	* Before injecting an NMI we must set VMCPU_FF_BLOCK_NMIS to prevent nested NMIs. We
3780	* do this only when we are surely going to inject the NMI as otherwise if we return
3781	* to ring-3 prematurely we could leave NMIs blocked indefinitely upon re-entry into
3782	* SVM R0.
3783	*
3784	* With VT-x, this is handled by the Guest interruptibility information VMCS field
3785	* which will set the VMCS field after actually delivering the NMI which we read on
3786	* VM-exit to determine the state.
3787	*/
3788	if ( Event.n.u3Type == SVM_EVENT_NMI
3789	&& Event.n.u8Vector == X86_XCPT_NMI
3790	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3791	{
3792	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3793	}
3794
3795	/*
3796	* Inject it (update VMCB for injection by the hardware).
3797	*/
3798	Log4(("Injecting pending HM event\n"));
3799	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, &Event);
3800	pVCpu->hm.s.Event.fPending = false;
3801
3802	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3803	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3804	else
3805	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3806	}
3807	else
3808	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
3809
3810	/*
3811	* We could have injected an NMI through IEM and continue guest execution using
3812	* hardware-assisted SVM. In which case, we would not have any events pending (above)
3813	* but we still need to intercept IRET in order to eventually clear NMI inhibition.
3814	*/
3815	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3816	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_IRET);
3817
3818	/*
3819	* Update the guest interrupt shadow in the guest (or nested-guest) VMCB.
3820	*
3821	* For nested-guests: We need to update it too for the scenario where IEM executes
3822	* the nested-guest but execution later continues here with an interrupt shadow active.
3823	*/
3824	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
3825	}
3826
3827
3828	/**
3829	* Reports world-switch error and dumps some useful debug info.
3830	*
3831	* @param pVCpu The cross context virtual CPU structure.
3832	* @param rcVMRun The return code from VMRUN (or
3833	* VERR_SVM_INVALID_GUEST_STATE for invalid
3834	* guest-state).
3835	*/
3836	static void hmR0SvmReportWorldSwitchError(PVMCPUCC pVCpu, int rcVMRun)
3837	{
3838	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3839	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
3840	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3841
3842	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3843	{
3844	#ifdef VBOX_STRICT
3845	hmR0DumpRegs(pVCpu, HM_DUMP_REG_FLAGS_ALL);
3846	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3847	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
3848	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3849	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3850	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3851	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3852	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3853	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3854	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3855	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3856	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3857
3858	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3859	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3860	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3861
3862	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3863	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3864	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
3865	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
3866	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3867	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3868	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3869	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3870	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
3871	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved));
3872	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3873	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3874
3875	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
3876	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
3877	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3878	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3879	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3880	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3881	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3882	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3883	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3884	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3885	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3886	Log4(("ctrl.NestedPagingCtrl.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging));
3887	Log4(("ctrl.NestedPagingCtrl.u1Sev %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1Sev));
3888	Log4(("ctrl.NestedPagingCtrl.u1SevEs %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1SevEs));
3889	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3890	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3891	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3892	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3893	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3894	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3895
3896	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3897
3898	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
3899	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
3900
3901	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3902	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3903	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3904	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3905	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3906	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3907	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3908	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3909	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3910	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3911	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3912	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3913	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3914	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3915	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3916	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3917	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3918	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3919	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3920	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3921
3922	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3923	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3924
3925	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3926	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3927	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3928	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3929
3930	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3931	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3932
3933	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3934	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3935	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3936	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3937
3938	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3939	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3940	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3941	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3942	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3943	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3944	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3945
3946	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3947	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3948	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3949	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3950
3951	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3952	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3953	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3954
3955	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3956	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3957	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3958	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3959	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3960	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3961	Log4(("guest.u64PAT %#RX64\n", pVmcb->guest.u64PAT));
3962	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3963	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3964	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3965	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3966	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3967
3968	NOREF(pVmcb);
3969	#endif /* VBOX_STRICT */
3970	}
3971	else
3972	Log4Func(("rcVMRun=%d\n", rcVMRun));
3973	}
3974
3975
3976	/**
3977	* Check per-VM and per-VCPU force flag actions that require us to go back to
3978	* ring-3 for one reason or another.
3979	*
3980	* @returns Strict VBox status code (information status code included).
3981	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3982	* ring-3.
3983	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3984	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3985	* interrupts)
3986	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3987	* all EMTs to be in ring-3.
3988	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3989	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3990	* to the EM loop.
3991	*
3992	* @param pVCpu The cross context virtual CPU structure.
3993	*/
3994	static VBOXSTRICTRC hmR0SvmCheckForceFlags(PVMCPUCC pVCpu)
3995	{
3996	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3997
3998	/* Could happen as a result of longjump. */
3999	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
4000	PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
4001
4002	/* Update pending interrupts into the APIC's IRR. */
4003	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
4004	APICUpdatePendingInterrupts(pVCpu);
4005
4006	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4007	if ( VM_FF_IS_ANY_SET(pVM, !pVCpu->hm.s.fSingleInstruction
4008	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
4009	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, !pVCpu->hm.s.fSingleInstruction
4010	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
4011	{
4012	/* Pending PGM C3 sync. */
4013	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
4014	{
4015	int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4,
4016	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4017	if (rc != VINF_SUCCESS)
4018	{
4019	Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
4020	return rc;
4021	}
4022	}
4023
4024	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
4025	/* -XXX- what was that about single stepping? */
4026	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HM_TO_R3_MASK)
4027	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4028	{
4029	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4030	int rc = RT_LIKELY(!VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_RAW_TO_R3 : VINF_EM_NO_MEMORY;
4031	Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
4032	return rc;
4033	}
4034
4035	/* Pending VM request packets, such as hardware interrupts. */
4036	if ( VM_FF_IS_SET(pVM, VM_FF_REQUEST)
4037	\|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
4038	{
4039	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchVmReq);
4040	Log4Func(("Pending VM request forcing us back to ring-3\n"));
4041	return VINF_EM_PENDING_REQUEST;
4042	}
4043
4044	/* Pending PGM pool flushes. */
4045	if (VM_FF_IS_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
4046	{
4047	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPgmPoolFlush);
4048	Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
4049	return VINF_PGM_POOL_FLUSH_PENDING;
4050	}
4051
4052	/* Pending DMA requests. */
4053	if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA))
4054	{
4055	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchDma);
4056	Log4Func(("Pending DMA request forcing us back to ring-3\n"));
4057	return VINF_EM_RAW_TO_R3;
4058	}
4059	}
4060
4061	return VINF_SUCCESS;
4062	}
4063
4064
4065	/**
4066	* Does the preparations before executing guest code in AMD-V.
4067	*
4068	* This may cause longjmps to ring-3 and may even result in rescheduling to the
4069	* recompiler. We must be cautious what we do here regarding committing
4070	* guest-state information into the VMCB assuming we assuredly execute the guest
4071	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
4072	* clearing the common-state (TRPM/forceflags), we must undo those changes so
4073	* that the recompiler can (and should) use them when it resumes guest
4074	* execution. Otherwise such operations must be done when we can no longer
4075	* exit to ring-3.
4076	*
4077	* @returns Strict VBox status code (informational status codes included).
4078	* @retval VINF_SUCCESS if we can proceed with running the guest.
4079	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4080	*
4081	* @param pVCpu The cross context virtual CPU structure.
4082	* @param pSvmTransient Pointer to the SVM transient structure.
4083	*/
4084	static VBOXSTRICTRC hmR0SvmPreRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4085	{
4086	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4087
4088	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
4089	if (pSvmTransient->fIsNestedGuest)
4090	{
4091	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
4092	return VINF_EM_RESCHEDULE_REM;
4093	}
4094	#endif
4095
4096	/* Check force flag actions that might require us to go back to ring-3. */
4097	VBOXSTRICTRC rc = hmR0SvmCheckForceFlags(pVCpu);
4098	if (rc != VINF_SUCCESS)
4099	return rc;
4100
4101	if (TRPMHasTrap(pVCpu))
4102	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4103	else if (!pVCpu->hm.s.Event.fPending)
4104	{
4105	rc = hmR0SvmEvaluatePendingEvent(pVCpu, pSvmTransient);
4106	if ( rc != VINF_SUCCESS
4107	\|\| pSvmTransient->fIsNestedGuest != CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4108	{
4109	/* If a nested-guest VM-exit occurred, bail. */
4110	if (pSvmTransient->fIsNestedGuest)
4111	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
4112	return rc;
4113	}
4114	}
4115
4116	/*
4117	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4118	* Just do it in software, see @bugref{8411}.
4119	* NB: If we could continue a task switch exit we wouldn't need to do this.
4120	*/
4121	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4122	if (RT_UNLIKELY( !g_fHmSvmFeatures
4123	&& pVCpu->hm.s.Event.fPending
4124	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
4125	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4126
4127	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4128	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4129	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4130	#endif
4131
4132	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4133	/*
4134	* Set up the nested-guest VMCB for execution using hardware-assisted SVM.
4135	*/
4136	if (pSvmTransient->fIsNestedGuest)
4137	hmR0SvmSetupVmcbNested(pVCpu);
4138	#endif
4139
4140	/*
4141	* Export the guest state bits that are not shared with the host in any way as we can
4142	* longjmp or get preempted in the midst of exporting some of the state.
4143	*/
4144	rc = hmR0SvmExportGuestState(pVCpu, pSvmTransient);
4145	AssertRCReturn(rc, rc);
4146	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4147
4148	/* Ensure we've cached (and hopefully modified) the nested-guest VMCB for execution using hardware-assisted SVM. */
4149	Assert(!pSvmTransient->fIsNestedGuest \|\| pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
4150
4151	/*
4152	* If we're not intercepting TPR changes in the guest, save the guest TPR before the
4153	* world-switch so we can update it on the way back if the guest changed the TPR.
4154	*/
4155	if (pVCpu->hmr0.s.svm.fSyncVTpr)
4156	{
4157	Assert(!pSvmTransient->fIsNestedGuest);
4158	PCSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
4159	if (pVM->hm.s.fTprPatchingActive)
4160	pSvmTransient->u8GuestTpr = pVmcb->guest.u64LSTAR;
4161	else
4162	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4163	}
4164
4165	/*
4166	* No longjmps to ring-3 from this point on!!!
4167	*
4168	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4169	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4170	*/
4171	VMMRZCallRing3Disable(pVCpu);
4172
4173	/*
4174	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4175	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4176	* preemption disabled for a while. Since this is purly to aid the
4177	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4178	* disable interrupt on NT.
4179	*
4180	* We need to check for force-flags that could've possible been altered since we last
4181	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4182	* see @bugref{6398}).
4183	*
4184	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4185	* to ring-3 before executing guest code.
4186	*/
4187	pSvmTransient->fEFlags = ASMIntDisableFlags();
4188	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4189	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4190	{
4191	ASMSetFlags(pSvmTransient->fEFlags);
4192	VMMRZCallRing3Enable(pVCpu);
4193	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4194	return VINF_EM_RAW_TO_R3;
4195	}
4196	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4197	{
4198	ASMSetFlags(pSvmTransient->fEFlags);
4199	VMMRZCallRing3Enable(pVCpu);
4200	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4201	return VINF_EM_RAW_INTERRUPT;
4202	}
4203
4204	return VINF_SUCCESS;
4205	}
4206
4207
4208	/**
4209	* Prepares to run guest (or nested-guest) code in AMD-V and we've committed to
4210	* doing so.
4211	*
4212	* This means there is no backing out to ring-3 or anywhere else at this point.
4213	*
4214	* @param pVCpu The cross context virtual CPU structure.
4215	* @param pSvmTransient Pointer to the SVM transient structure.
4216	*
4217	* @remarks Called with preemption disabled.
4218	* @remarks No-long-jump zone!!!
4219	*/
4220	static void hmR0SvmPreRunGuestCommitted(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4221	{
4222	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4223	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4224
4225	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4226	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4227
4228	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4229	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4230
4231	hmR0SvmInjectPendingEvent(pVCpu, pVmcb);
4232
4233	if (!CPUMIsGuestFPUStateActive(pVCpu))
4234	{
4235	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4236	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4237	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4238	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
4239	}
4240
4241	/* Load the state shared between host and guest (FPU, debug). */
4242	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)
4243	hmR0SvmExportSharedState(pVCpu, pVmcb);
4244
4245	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
4246	AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
4247
4248	PHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
4249	RTCPUID const idHostCpu = pHostCpu->idCpu;
4250	bool const fMigratedHostCpu = idHostCpu != pVCpu->hmr0.s.idLastCpu;
4251
4252	/* Setup TSC offsetting. */
4253	if ( pSvmTransient->fUpdateTscOffsetting
4254	\|\| fMigratedHostCpu)
4255	{
4256	hmR0SvmUpdateTscOffsetting(pVCpu, pVmcb);
4257	pSvmTransient->fUpdateTscOffsetting = false;
4258	}
4259
4260	/* Record statistics of how often we use TSC offsetting as opposed to intercepting RDTSC/P. */
4261	if (!(pVmcb->ctrl.u64InterceptCtrl & (SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP)))
4262	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
4263	else
4264	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
4265
4266	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4267	if (fMigratedHostCpu)
4268	pVmcb->ctrl.u32VmcbCleanBits = 0;
4269
4270	/* Store status of the shared guest-host state at the time of VMRUN. */
4271	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4272	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4273
4274	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4275	uint8_t *pbMsrBitmap;
4276	if (!pSvmTransient->fIsNestedGuest)
4277	pbMsrBitmap = (uint8_t *)pVCpu->hmr0.s.svm.pvMsrBitmap;
4278	else
4279	{
4280	/** @todo We could perhaps optimize this by monitoring if the guest modifies its
4281	* MSRPM and only perform this if it changed also use EVEX.POR when it
4282	* does. */
4283	hmR0SvmMergeMsrpmNested(pHostCpu, pVCpu);
4284
4285	/* Update the nested-guest VMCB with the newly merged MSRPM (clean bits updated below). */
4286	pVmcb->ctrl.u64MSRPMPhysAddr = pHostCpu->n.svm.HCPhysNstGstMsrpm;
4287	pbMsrBitmap = (uint8_t *)pHostCpu->n.svm.pvNstGstMsrpm;
4288	}
4289	#else
4290	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4291	#endif
4292
4293	ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4294	/* Flush the appropriate tagged-TLB entries. */
4295	hmR0SvmFlushTaggedTlb(pHostCpu, pVCpu, pVmcb);
4296	Assert(pVCpu->hmr0.s.idLastCpu == idHostCpu);
4297
4298	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4299
4300	TMNotifyStartOfExecution(pVM, pVCpu); /* Finally, notify TM to resume its clocks as we're about
4301	to start executing. */
4302
4303	/*
4304	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that RDTSCPs
4305	* (that don't cause exits) reads the guest MSR, see @bugref{3324}.
4306	*
4307	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4308	*/
4309	if ( pVM->cpum.ro.HostFeatures.fRdTscP
4310	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4311	{
4312	uint64_t const uGuestTscAux = CPUMGetGuestTscAux(pVCpu);
4313	pVCpu->hmr0.s.svm.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4314	if (uGuestTscAux != pVCpu->hmr0.s.svm.u64HostTscAux)
4315	ASMWrMsr(MSR_K8_TSC_AUX, uGuestTscAux);
4316	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4317	pSvmTransient->fRestoreTscAuxMsr = true;
4318	}
4319	else
4320	{
4321	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4322	pSvmTransient->fRestoreTscAuxMsr = false;
4323	}
4324	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
4325
4326	/*
4327	* If VMCB Clean bits isn't supported by the CPU or exposed to the guest in the nested
4328	* virtualization case, mark all state-bits as dirty indicating to the CPU to re-load
4329	* from the VMCB.
4330	*/
4331	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pSvmTransient->fIsNestedGuest);
4332	if (!fSupportsVmcbCleanBits)
4333	pVmcb->ctrl.u32VmcbCleanBits = 0;
4334	}
4335
4336
4337	/**
4338	* Wrapper for running the guest (or nested-guest) code in AMD-V.
4339	*
4340	* @returns VBox strict status code.
4341	* @param pVCpu The cross context virtual CPU structure.
4342	* @param HCPhysVmcb The host physical address of the VMCB.
4343	*
4344	* @remarks No-long-jump zone!!!
4345	*/
4346	DECLINLINE(int) hmR0SvmRunGuest(PVMCPUCC pVCpu, RTHCPHYS HCPhysVmcb)
4347	{
4348	/* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
4349	pVCpu->cpum.GstCtx.fExtrn \|= HMSVM_CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_HM;
4350	return pVCpu->hmr0.s.svm.pfnVMRun(pVCpu->CTX_SUFF(pVM), pVCpu, HCPhysVmcb);
4351	}
4352
4353
4354	/**
4355	* Performs some essential restoration of state after running guest (or
4356	* nested-guest) code in AMD-V.
4357	*
4358	* @param pVCpu The cross context virtual CPU structure.
4359	* @param pSvmTransient Pointer to the SVM transient structure.
4360	* @param rcVMRun Return code of VMRUN.
4361	*
4362	* @remarks Called with interrupts disabled.
4363	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4364	* unconditionally when it is safe to do so.
4365	*/
4366	static void hmR0SvmPostRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient, VBOXSTRICTRC rcVMRun)
4367	{
4368	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4369
4370	ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4371	ASMAtomicIncU32(&pVCpu->hmr0.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4372
4373	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4374	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
4375
4376	/* TSC read must be done early for maximum accuracy. */
4377	if (!(pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4378	{
4379	if (!pSvmTransient->fIsNestedGuest)
4380	TMCpuTickSetLastSeen(pVCpu, pVCpu->hmr0.s.uTscExit + pVmcbCtrl->u64TSCOffset);
4381	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4382	else
4383	{
4384	/* The nested-guest VMCB TSC offset shall eventually be restored on #VMEXIT via HMNotifySvmNstGstVmexit(). */
4385	uint64_t const uGstTsc = CPUMRemoveNestedGuestTscOffset(pVCpu, pVCpu->hmr0.s.uTscExit + pVmcbCtrl->u64TSCOffset);
4386	TMCpuTickSetLastSeen(pVCpu, uGstTsc);
4387	}
4388	#endif
4389	}
4390
4391	if (pSvmTransient->fRestoreTscAuxMsr)
4392	{
4393	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4394	CPUMSetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4395	if (u64GuestTscAuxMsr != pVCpu->hmr0.s.svm.u64HostTscAux)
4396	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hmr0.s.svm.u64HostTscAux);
4397	}
4398
4399	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
4400	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4401	TMNotifyEndOfExecution(pVM, pVCpu, pVCpu->hmr0.s.uTscExit); /* Notify TM that the guest is no longer running. */
4402	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4403
4404	Assert(!(ASMGetFlags() & X86_EFL_IF));
4405	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4406	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4407
4408	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4409	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4410	{
4411	Log4Func(("VMRUN failure: rcVMRun=%Rrc\n", VBOXSTRICTRC_VAL(rcVMRun)));
4412	return;
4413	}
4414
4415	pSvmTransient->u64ExitCode = pVmcbCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4416	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4417	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4418	pVmcbCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4419
4420	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4421	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4422	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4423	#else
4424	/*
4425	* Always import the following:
4426	*
4427	* - RIP for exit optimizations and evaluating event injection on re-entry.
4428	* - RFLAGS for evaluating event injection on VM re-entry and for exporting shared debug
4429	* state on preemption.
4430	* - Interrupt shadow, GIF for evaluating event injection on VM re-entry.
4431	* - CS for exit optimizations.
4432	* - RAX, RSP for simplifying assumptions on GPRs. All other GPRs are swapped by the
4433	* assembly switcher code.
4434	* - Shared state (only DR7 currently) for exporting shared debug state on preemption.
4435	*/
4436	hmR0SvmImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP
4437	\| CPUMCTX_EXTRN_RFLAGS
4438	\| CPUMCTX_EXTRN_RAX
4439	\| CPUMCTX_EXTRN_RSP
4440	\| CPUMCTX_EXTRN_CS
4441	\| CPUMCTX_EXTRN_HWVIRT
4442	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
4443	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ
4444	\| HMSVM_CPUMCTX_SHARED_STATE);
4445	#endif
4446
4447	if ( pSvmTransient->u64ExitCode != SVM_EXIT_INVALID
4448	&& pVCpu->hmr0.s.svm.fSyncVTpr)
4449	{
4450	Assert(!pSvmTransient->fIsNestedGuest);
4451	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4452	if ( pVM->hm.s.fTprPatchingActive
4453	&& (pVmcb->guest.u64LSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4454	{
4455	int rc = APICSetTpr(pVCpu, pVmcb->guest.u64LSTAR & 0xff);
4456	AssertRC(rc);
4457	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4458	}
4459	/* Sync TPR when we aren't intercepting CR8 writes. */
4460	else if (pSvmTransient->u8GuestTpr != pVmcbCtrl->IntCtrl.n.u8VTPR)
4461	{
4462	int rc = APICSetTpr(pVCpu, pVmcbCtrl->IntCtrl.n.u8VTPR << 4);
4463	AssertRC(rc);
4464	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4465	}
4466	}
4467
4468	#ifdef DEBUG_ramshankar
4469	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4470	{
4471	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4472	hmR0SvmLogState(pVCpu, pVmcb, pVCpu->cpum.GstCtx, "hmR0SvmPostRunGuestNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR,
4473	0 /* uVerbose */);
4474	}
4475	#endif
4476
4477	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
4478	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_SVM, pSvmTransient->u64ExitCode & EMEXIT_F_TYPE_MASK),
4479	pVCpu->cpum.GstCtx.cs.u64Base + pVCpu->cpum.GstCtx.rip, pVCpu->hmr0.s.uTscExit);
4480	}
4481
4482
4483	/**
4484	* Runs the guest code using AMD-V.
4485	*
4486	* @returns Strict VBox status code.
4487	* @param pVCpu The cross context virtual CPU structure.
4488	* @param pcLoops Pointer to the number of executed loops.
4489	*/
4490	static VBOXSTRICTRC hmR0SvmRunGuestCodeNormal(PVMCPUCC pVCpu, uint32_t *pcLoops)
4491	{
4492	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops;
4493	Assert(pcLoops);
4494	Assert(*pcLoops <= cMaxResumeLoops);
4495
4496	SVMTRANSIENT SvmTransient;
4497	RT_ZERO(SvmTransient);
4498	SvmTransient.fUpdateTscOffsetting = true;
4499	SvmTransient.pVmcb = pVCpu->hmr0.s.svm.pVmcb;
4500
4501	VBOXSTRICTRC rc = VERR_INTERNAL_ERROR_5;
4502	for (;;)
4503	{
4504	Assert(!HMR0SuspendPending());
4505	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4506
4507	/* Preparatory work for running nested-guest code, this may force us to return to
4508	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4509	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4510	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4511	if (rc != VINF_SUCCESS)
4512	break;
4513
4514	/*
4515	* No longjmps to ring-3 from this point on!!!
4516	*
4517	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4518	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4519	*/
4520	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4521	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hmr0.s.svm.HCPhysVmcb);
4522
4523	/* Restore any residual host-state and save any bits shared between host and guest
4524	into the guest-CPU state. Re-enables interrupts! */
4525	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4526
4527	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4528	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4529	{
4530	if (rc == VINF_SUCCESS)
4531	rc = VERR_SVM_INVALID_GUEST_STATE;
4532	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4533	hmR0SvmReportWorldSwitchError(pVCpu, VBOXSTRICTRC_VAL(rc));
4534	break;
4535	}
4536
4537	/* Handle the #VMEXIT. */
4538	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4539	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4540	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, SvmTransient.u64ExitCode, pVCpu->hmr0.s.svm.pVmcb);
4541	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4542	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4543	if (rc != VINF_SUCCESS)
4544	break;
4545	if (++(*pcLoops) >= cMaxResumeLoops)
4546	{
4547	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4548	rc = VINF_EM_RAW_INTERRUPT;
4549	break;
4550	}
4551	}
4552
4553	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4554	return rc;
4555	}
4556
4557
4558	/**
4559	* Runs the guest code using AMD-V in single step mode.
4560	*
4561	* @returns Strict VBox status code.
4562	* @param pVCpu The cross context virtual CPU structure.
4563	* @param pcLoops Pointer to the number of executed loops.
4564	*/
4565	static VBOXSTRICTRC hmR0SvmRunGuestCodeStep(PVMCPUCC pVCpu, uint32_t *pcLoops)
4566	{
4567	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops;
4568	Assert(pcLoops);
4569	Assert(*pcLoops <= cMaxResumeLoops);
4570
4571	SVMTRANSIENT SvmTransient;
4572	RT_ZERO(SvmTransient);
4573	SvmTransient.fUpdateTscOffsetting = true;
4574	SvmTransient.pVmcb = pVCpu->hmr0.s.svm.pVmcb;
4575
4576	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4577	uint16_t const uCsStart = pCtx->cs.Sel;
4578	uint64_t const uRipStart = pCtx->rip;
4579
4580	VBOXSTRICTRC rc = VERR_INTERNAL_ERROR_5;
4581	for (;;)
4582	{
4583	Assert(!HMR0SuspendPending());
4584	AssertMsg(pVCpu->hmr0.s.idEnteredCpu == RTMpCpuId(),
4585	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hmr0.s.idEnteredCpu,
4586	(unsigned)RTMpCpuId(), *pcLoops));
4587
4588	/* Preparatory work for running nested-guest code, this may force us to return to
4589	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4590	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4591	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4592	if (rc != VINF_SUCCESS)
4593	break;
4594
4595	/*
4596	* No longjmps to ring-3 from this point on!!!
4597	*
4598	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4599	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4600	*/
4601	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4602
4603	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hmr0.s.svm.HCPhysVmcb);
4604
4605	/* Restore any residual host-state and save any bits shared between host and guest
4606	into the guest-CPU state. Re-enables interrupts! */
4607	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4608
4609	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4610	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4611	{
4612	if (rc == VINF_SUCCESS)
4613	rc = VERR_SVM_INVALID_GUEST_STATE;
4614	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4615	hmR0SvmReportWorldSwitchError(pVCpu, VBOXSTRICTRC_VAL(rc));
4616	return rc;
4617	}
4618
4619	/* Handle the #VMEXIT. */
4620	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4621	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4622	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hmr0.s.svm.pVmcb);
4623	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4624	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4625	if (rc != VINF_SUCCESS)
4626	break;
4627	if (++(*pcLoops) >= cMaxResumeLoops)
4628	{
4629	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4630	rc = VINF_EM_RAW_INTERRUPT;
4631	break;
4632	}
4633
4634	/*
4635	* Did the RIP change, if so, consider it a single step.
4636	* Otherwise, make sure one of the TFs gets set.
4637	*/
4638	if ( pCtx->rip != uRipStart
4639	\|\| pCtx->cs.Sel != uCsStart)
4640	{
4641	rc = VINF_EM_DBG_STEPPED;
4642	break;
4643	}
4644	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_GUEST_DR_MASK;
4645	}
4646
4647	/*
4648	* Clear the X86_EFL_TF if necessary.
4649	*/
4650	if (pVCpu->hmr0.s.fClearTrapFlag)
4651	{
4652	pVCpu->hmr0.s.fClearTrapFlag = false;
4653	pCtx->eflags.Bits.u1TF = 0;
4654	}
4655
4656	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4657	return rc;
4658	}
4659
4660	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4661	/**
4662	* Runs the nested-guest code using AMD-V.
4663	*
4664	* @returns Strict VBox status code.
4665	* @param pVCpu The cross context virtual CPU structure.
4666	* @param pcLoops Pointer to the number of executed loops. If we're switching
4667	* from the guest-code execution loop to this nested-guest
4668	* execution loop pass the remainder value, else pass 0.
4669	*/
4670	static VBOXSTRICTRC hmR0SvmRunGuestCodeNested(PVMCPUCC pVCpu, uint32_t *pcLoops)
4671	{
4672	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4673	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4674	Assert(pcLoops);
4675	Assert(*pcLoops <= pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops);
4676
4677	SVMTRANSIENT SvmTransient;
4678	RT_ZERO(SvmTransient);
4679	SvmTransient.fUpdateTscOffsetting = true;
4680	SvmTransient.pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4681	SvmTransient.fIsNestedGuest = true;
4682
4683	VBOXSTRICTRC rc = VERR_INTERNAL_ERROR_4;
4684	for (;;)
4685	{
4686	Assert(!HMR0SuspendPending());
4687	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4688
4689	/* Preparatory work for running nested-guest code, this may force us to return to
4690	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4691	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4692	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4693	if ( rc != VINF_SUCCESS
4694	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4695	break;
4696
4697	/*
4698	* No longjmps to ring-3 from this point on!!!
4699	*
4700	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4701	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4702	*/
4703	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4704
4705	rc = hmR0SvmRunGuest(pVCpu, pCtx->hwvirt.svm.HCPhysVmcb);
4706
4707	/* Restore any residual host-state and save any bits shared between host and guest
4708	into the guest-CPU state. Re-enables interrupts! */
4709	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4710
4711	if (RT_LIKELY( rc == VINF_SUCCESS
4712	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
4713	{ /* extremely likely */ }
4714	else
4715	{
4716	/* VMRUN failed, shouldn't really happen, Guru. */
4717	if (rc != VINF_SUCCESS)
4718	break;
4719
4720	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
4721	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4722	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
4723	rc = IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0);
4724	break;
4725	}
4726
4727	/* Handle the #VMEXIT. */
4728	HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4729	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4730	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
4731	rc = hmR0SvmHandleExitNested(pVCpu, &SvmTransient);
4732	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4733	if (rc == VINF_SUCCESS)
4734	{
4735	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4736	{
4737	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
4738	rc = VINF_SVM_VMEXIT;
4739	}
4740	else
4741	{
4742	if (++(*pcLoops) <= pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops)
4743	continue;
4744	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4745	rc = VINF_EM_RAW_INTERRUPT;
4746	}
4747	}
4748	else
4749	Assert(rc != VINF_SVM_VMEXIT);
4750	break;
4751	/** @todo NSTSVM: handle single-stepping. */
4752	}
4753
4754	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4755	return rc;
4756	}
4757	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
4758
4759
4760	/**
4761	* Runs the guest code using AMD-V.
4762	*
4763	* @returns Strict VBox status code.
4764	* @param pVCpu The cross context virtual CPU structure.
4765	*/
4766	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVMCPUCC pVCpu)
4767	{
4768	AssertPtr(pVCpu);
4769	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4770	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4771	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
4772	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4773
4774	uint32_t cLoops = 0;
4775	VBOXSTRICTRC rc;
4776	for (;;)
4777	{
4778	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4779	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
4780	#else
4781	NOREF(pCtx);
4782	bool const fInNestedGuestMode = false;
4783	#endif
4784	if (!fInNestedGuestMode)
4785	{
4786	if (!pVCpu->hm.s.fSingleInstruction)
4787	rc = hmR0SvmRunGuestCodeNormal(pVCpu, &cLoops);
4788	else
4789	rc = hmR0SvmRunGuestCodeStep(pVCpu, &cLoops);
4790	}
4791	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4792	else
4793	rc = hmR0SvmRunGuestCodeNested(pVCpu, &cLoops);
4794
4795	if (rc == VINF_SVM_VMRUN)
4796	{
4797	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4798	continue;
4799	}
4800	if (rc == VINF_SVM_VMEXIT)
4801	{
4802	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4803	continue;
4804	}
4805	#endif
4806	break;
4807	}
4808
4809	/* Fixup error codes. */
4810	if (rc == VERR_EM_INTERPRETER)
4811	rc = VINF_EM_RAW_EMULATE_INSTR;
4812	else if (rc == VINF_EM_RESET)
4813	rc = VINF_EM_TRIPLE_FAULT;
4814
4815	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4816	rc = hmR0SvmExitToRing3(pVCpu, rc);
4817	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
4818	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4819	return rc;
4820	}
4821
4822
4823	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4824	/**
4825	* Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
4826	*
4827	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4828	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4829	*/
4830	static bool hmR0SvmIsIoInterceptSet(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4831	{
4832	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4833	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4834	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4835	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4836	const uint8_t iEffSeg = pIoExitInfo->n.u3Seg;
4837	const bool fRep = pIoExitInfo->n.u1Rep;
4838	const bool fStrIo = pIoExitInfo->n.u1Str;
4839
4840	return CPUMIsSvmIoInterceptSet(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4841	NULL /* pIoExitInfo */);
4842	}
4843
4844
4845	/**
4846	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4847	* SVM_EXIT_INVALID).
4848	*
4849	* @returns VBox status code (informational status codes included).
4850	* @param pVCpu The cross context virtual CPU structure.
4851	* @param pSvmTransient Pointer to the SVM transient structure.
4852	*/
4853	static VBOXSTRICTRC hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4854	{
4855	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
4856	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4857	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4858
4859	/*
4860	* We import the complete state here because we use separate VMCBs for the guest and the
4861	* nested-guest, and the guest's VMCB is used after the #VMEXIT. We can only save/restore
4862	* the #VMEXIT specific state if we used the same VMCB for both guest and nested-guest.
4863	*/
4864	#define NST_GST_VMEXIT_CALL_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4865	do { \
4866	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
4867	return IEMExecSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); \
4868	} while (0)
4869
4870	/*
4871	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected by the
4872	* nested-guest. If it isn't, it should be handled by the (outer) guest.
4873	*/
4874	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
4875	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4876	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4877	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
4878	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
4879	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
4880
4881	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
4882	switch (uExitCode)
4883	{
4884	case SVM_EXIT_CPUID:
4885	{
4886	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
4887	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4888	return hmR0SvmExitCpuid(pVCpu, pSvmTransient);
4889	}
4890
4891	case SVM_EXIT_RDTSC:
4892	{
4893	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
4894	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4895	return hmR0SvmExitRdtsc(pVCpu, pSvmTransient);
4896	}
4897
4898	case SVM_EXIT_RDTSCP:
4899	{
4900	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
4901	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4902	return hmR0SvmExitRdtscp(pVCpu, pSvmTransient);
4903	}
4904
4905	case SVM_EXIT_MONITOR:
4906	{
4907	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
4908	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4909	return hmR0SvmExitMonitor(pVCpu, pSvmTransient);
4910	}
4911
4912	case SVM_EXIT_MWAIT:
4913	{
4914	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
4915	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4916	return hmR0SvmExitMwait(pVCpu, pSvmTransient);
4917	}
4918
4919	case SVM_EXIT_HLT:
4920	{
4921	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
4922	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4923	return hmR0SvmExitHlt(pVCpu, pSvmTransient);
4924	}
4925
4926	case SVM_EXIT_MSR:
4927	{
4928	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
4929	{
4930	uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
4931	uint16_t offMsrpm;
4932	uint8_t uMsrpmBit;
4933	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
4934	if (RT_SUCCESS(rc))
4935	{
4936	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
4937	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
4938
4939	uint8_t const pbMsrBitmap = (uint8_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4940	pbMsrBitmap += offMsrpm;
4941	bool const fInterceptRead = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit));
4942	bool const fInterceptWrite = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
4943
4944	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4945	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
4946	{
4947	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4948	}
4949	}
4950	else
4951	{
4952	/*
4953	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
4954	* See AMD-V spec. "15.11 MSR Intercepts".
4955	*/
4956	Assert(rc == VERR_OUT_OF_RANGE);
4957	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4958	}
4959	}
4960	return hmR0SvmExitMsr(pVCpu, pSvmTransient);
4961	}
4962
4963	case SVM_EXIT_IOIO:
4964	{
4965	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
4966	{
4967	void *pvIoBitmap = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap);
4968	SVMIOIOEXITINFO IoExitInfo;
4969	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
4970	bool const fIntercept = hmR0SvmIsIoInterceptSet(pvIoBitmap, &IoExitInfo);
4971	if (fIntercept)
4972	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4973	}
4974	return hmR0SvmExitIOInstr(pVCpu, pSvmTransient);
4975	}
4976
4977	case SVM_EXIT_XCPT_PF:
4978	{
4979	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4980	if (pVM->hmr0.s.fNestedPaging)
4981	{
4982	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
4983	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
4984
4985	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
4986	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
4987	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
4988
4989	/* If the nested-guest is not intercepting #PFs, forward the #PF to the guest. */
4990	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
4991	hmR0SvmSetPendingXcptPF(pVCpu, u32ErrCode, uFaultAddress);
4992	return VINF_SUCCESS;
4993	}
4994	return hmR0SvmExitXcptPF(pVCpu, pSvmTransient);
4995	}
4996
4997	case SVM_EXIT_XCPT_UD:
4998	{
4999	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
5000	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5001	hmR0SvmSetPendingXcptUD(pVCpu);
5002	return VINF_SUCCESS;
5003	}
5004
5005	case SVM_EXIT_XCPT_MF:
5006	{
5007	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
5008	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5009	return hmR0SvmExitXcptMF(pVCpu, pSvmTransient);
5010	}
5011
5012	case SVM_EXIT_XCPT_DB:
5013	{
5014	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
5015	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5016	return hmR0SvmNestedExitXcptDB(pVCpu, pSvmTransient);
5017	}
5018
5019	case SVM_EXIT_XCPT_AC:
5020	{
5021	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
5022	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5023	return hmR0SvmExitXcptAC(pVCpu, pSvmTransient);
5024	}
5025
5026	case SVM_EXIT_XCPT_BP:
5027	{
5028	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
5029	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5030	return hmR0SvmNestedExitXcptBP(pVCpu, pSvmTransient);
5031	}
5032
5033	case SVM_EXIT_READ_CR0:
5034	case SVM_EXIT_READ_CR3:
5035	case SVM_EXIT_READ_CR4:
5036	{
5037	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5038	if (CPUMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
5039	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5040	return hmR0SvmExitReadCRx(pVCpu, pSvmTransient);
5041	}
5042
5043	case SVM_EXIT_CR0_SEL_WRITE:
5044	{
5045	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5046	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5047	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5048	}
5049
5050	case SVM_EXIT_WRITE_CR0:
5051	case SVM_EXIT_WRITE_CR3:
5052	case SVM_EXIT_WRITE_CR4:
5053	case SVM_EXIT_WRITE_CR8: /* CR8 writes would go to the V_TPR rather than here, since we run with V_INTR_MASKING. */
5054	{
5055	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5056	Log4Func(("Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
5057
5058	if (CPUMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
5059	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5060	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5061	}
5062
5063	case SVM_EXIT_PAUSE:
5064	{
5065	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
5066	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5067	return hmR0SvmExitPause(pVCpu, pSvmTransient);
5068	}
5069
5070	case SVM_EXIT_VINTR:
5071	{
5072	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
5073	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5074	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5075	}
5076
5077	case SVM_EXIT_INTR:
5078	case SVM_EXIT_NMI:
5079	case SVM_EXIT_SMI:
5080	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5081	{
5082	/*
5083	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5084	*
5085	* Although we don't intercept SMIs, the nested-guest might. Therefore, we might
5086	* get an SMI #VMEXIT here so simply ignore rather than causing a corresponding
5087	* nested-guest #VMEXIT.
5088	*
5089	* We shall import the complete state here as we may cause #VMEXITs from ring-3
5090	* while trying to inject interrupts, see comment at the top of this function.
5091	*/
5092	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_ALL);
5093	return hmR0SvmExitIntr(pVCpu, pSvmTransient);
5094	}
5095
5096	case SVM_EXIT_FERR_FREEZE:
5097	{
5098	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5099	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5100	return hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient);
5101	}
5102
5103	case SVM_EXIT_INVLPG:
5104	{
5105	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
5106	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5107	return hmR0SvmExitInvlpg(pVCpu, pSvmTransient);
5108	}
5109
5110	case SVM_EXIT_WBINVD:
5111	{
5112	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
5113	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5114	return hmR0SvmExitWbinvd(pVCpu, pSvmTransient);
5115	}
5116
5117	case SVM_EXIT_INVD:
5118	{
5119	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
5120	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5121	return hmR0SvmExitInvd(pVCpu, pSvmTransient);
5122	}
5123
5124	case SVM_EXIT_RDPMC:
5125	{
5126	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
5127	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5128	return hmR0SvmExitRdpmc(pVCpu, pSvmTransient);
5129	}
5130
5131	default:
5132	{
5133	switch (uExitCode)
5134	{
5135	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5136	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5137	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5138	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5139	{
5140	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5141	if (CPUMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
5142	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5143	return hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
5144	}
5145
5146	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5147	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5148	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5149	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5150	{
5151	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5152	if (CPUMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
5153	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5154	return hmR0SvmExitWriteDRx(pVCpu, pSvmTransient);
5155	}
5156
5157	case SVM_EXIT_XCPT_DE:
5158	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5159	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5160	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5161	case SVM_EXIT_XCPT_OF:
5162	case SVM_EXIT_XCPT_BR:
5163	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5164	case SVM_EXIT_XCPT_NM:
5165	case SVM_EXIT_XCPT_DF:
5166	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5167	case SVM_EXIT_XCPT_TS:
5168	case SVM_EXIT_XCPT_NP:
5169	case SVM_EXIT_XCPT_SS:
5170	case SVM_EXIT_XCPT_GP:
5171	/* SVM_EXIT_XCPT_PF: / / Handled above. */
5172	case SVM_EXIT_XCPT_15: /* Reserved. */
5173	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5174	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5175	case SVM_EXIT_XCPT_MC:
5176	case SVM_EXIT_XCPT_XF:
5177	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5178	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5179	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5180	{
5181	uint8_t const uVector = uExitCode - SVM_EXIT_XCPT_0;
5182	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5183	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5184	return hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient);
5185	}
5186
5187	case SVM_EXIT_XSETBV:
5188	{
5189	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5190	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5191	return hmR0SvmExitXsetbv(pVCpu, pSvmTransient);
5192	}
5193
5194	case SVM_EXIT_TASK_SWITCH:
5195	{
5196	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5197	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5198	return hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient);
5199	}
5200
5201	case SVM_EXIT_IRET:
5202	{
5203	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5204	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5205	return hmR0SvmExitIret(pVCpu, pSvmTransient);
5206	}
5207
5208	case SVM_EXIT_SHUTDOWN:
5209	{
5210	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5211	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5212	return hmR0SvmExitShutdown(pVCpu, pSvmTransient);
5213	}
5214
5215	case SVM_EXIT_VMMCALL:
5216	{
5217	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5218	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5219	return hmR0SvmExitVmmCall(pVCpu, pSvmTransient);
5220	}
5221
5222	case SVM_EXIT_CLGI:
5223	{
5224	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5225	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5226	return hmR0SvmExitClgi(pVCpu, pSvmTransient);
5227	}
5228
5229	case SVM_EXIT_STGI:
5230	{
5231	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5232	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5233	return hmR0SvmExitStgi(pVCpu, pSvmTransient);
5234	}
5235
5236	case SVM_EXIT_VMLOAD:
5237	{
5238	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5239	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5240	return hmR0SvmExitVmload(pVCpu, pSvmTransient);
5241	}
5242
5243	case SVM_EXIT_VMSAVE:
5244	{
5245	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5246	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5247	return hmR0SvmExitVmsave(pVCpu, pSvmTransient);
5248	}
5249
5250	case SVM_EXIT_INVLPGA:
5251	{
5252	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5253	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5254	return hmR0SvmExitInvlpga(pVCpu, pSvmTransient);
5255	}
5256
5257	case SVM_EXIT_VMRUN:
5258	{
5259	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5260	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5261	return hmR0SvmExitVmrun(pVCpu, pSvmTransient);
5262	}
5263
5264	case SVM_EXIT_RSM:
5265	{
5266	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5267	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5268	hmR0SvmSetPendingXcptUD(pVCpu);
5269	return VINF_SUCCESS;
5270	}
5271
5272	case SVM_EXIT_SKINIT:
5273	{
5274	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5275	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5276	hmR0SvmSetPendingXcptUD(pVCpu);
5277	return VINF_SUCCESS;
5278	}
5279
5280	case SVM_EXIT_NPF:
5281	{
5282	Assert(pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
5283	return hmR0SvmExitNestedPF(pVCpu, pSvmTransient);
5284	}
5285
5286	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5287	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5288
5289	default:
5290	{
5291	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5292	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5293	return VERR_SVM_UNKNOWN_EXIT;
5294	}
5295	}
5296	}
5297	}
5298	/* not reached */
5299
5300	#undef NST_GST_VMEXIT_CALL_RET
5301	}
5302	#endif
5303
5304
5305	/**
5306	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5307	*
5308	* @returns Strict VBox status code (informational status codes included).
5309	* @param pVCpu The cross context virtual CPU structure.
5310	* @param pSvmTransient Pointer to the SVM transient structure.
5311	*/
5312	static VBOXSTRICTRC hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5313	{
5314	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5315	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5316
5317	#ifdef DEBUG_ramshankar
5318	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) \
5319	do { \
5320	if ((a_fDbg) == 1) \
5321	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5322	int rc = a_CallExpr; \
5323	if ((a_fDbg) == 1) \
5324	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
5325	return rc; \
5326	} while (0)
5327	#else
5328	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) return a_CallExpr
5329	#endif
5330
5331	/*
5332	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs
5333	* for most guests under normal workloads (for some definition of "normal").
5334	*/
5335	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5336	switch (uExitCode)
5337	{
5338	case SVM_EXIT_NPF: VMEXIT_CALL_RET(0, hmR0SvmExitNestedPF(pVCpu, pSvmTransient));
5339	case SVM_EXIT_IOIO: VMEXIT_CALL_RET(0, hmR0SvmExitIOInstr(pVCpu, pSvmTransient));
5340	case SVM_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0SvmExitRdtsc(pVCpu, pSvmTransient));
5341	case SVM_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0SvmExitRdtscp(pVCpu, pSvmTransient));
5342	case SVM_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0SvmExitCpuid(pVCpu, pSvmTransient));
5343	case SVM_EXIT_XCPT_PF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptPF(pVCpu, pSvmTransient));
5344	case SVM_EXIT_MSR: VMEXIT_CALL_RET(0, hmR0SvmExitMsr(pVCpu, pSvmTransient));
5345	case SVM_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0SvmExitMonitor(pVCpu, pSvmTransient));
5346	case SVM_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0SvmExitMwait(pVCpu, pSvmTransient));
5347	case SVM_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0SvmExitHlt(pVCpu, pSvmTransient));
5348
5349	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5350	case SVM_EXIT_INTR:
5351	case SVM_EXIT_NMI: VMEXIT_CALL_RET(0, hmR0SvmExitIntr(pVCpu, pSvmTransient));
5352
5353	case SVM_EXIT_READ_CR0:
5354	case SVM_EXIT_READ_CR3:
5355	case SVM_EXIT_READ_CR4: VMEXIT_CALL_RET(0, hmR0SvmExitReadCRx(pVCpu, pSvmTransient));
5356
5357	case SVM_EXIT_CR0_SEL_WRITE:
5358	case SVM_EXIT_WRITE_CR0:
5359	case SVM_EXIT_WRITE_CR3:
5360	case SVM_EXIT_WRITE_CR4:
5361	case SVM_EXIT_WRITE_CR8: VMEXIT_CALL_RET(0, hmR0SvmExitWriteCRx(pVCpu, pSvmTransient));
5362
5363	case SVM_EXIT_VINTR: VMEXIT_CALL_RET(0, hmR0SvmExitVIntr(pVCpu, pSvmTransient));
5364	case SVM_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0SvmExitPause(pVCpu, pSvmTransient));
5365	case SVM_EXIT_VMMCALL: VMEXIT_CALL_RET(0, hmR0SvmExitVmmCall(pVCpu, pSvmTransient));
5366	case SVM_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpg(pVCpu, pSvmTransient));
5367	case SVM_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0SvmExitWbinvd(pVCpu, pSvmTransient));
5368	case SVM_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0SvmExitInvd(pVCpu, pSvmTransient));
5369	case SVM_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0SvmExitRdpmc(pVCpu, pSvmTransient));
5370	case SVM_EXIT_IRET: VMEXIT_CALL_RET(0, hmR0SvmExitIret(pVCpu, pSvmTransient));
5371	case SVM_EXIT_XCPT_UD: VMEXIT_CALL_RET(0, hmR0SvmExitXcptUD(pVCpu, pSvmTransient));
5372	case SVM_EXIT_XCPT_MF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptMF(pVCpu, pSvmTransient));
5373	case SVM_EXIT_XCPT_DB: VMEXIT_CALL_RET(0, hmR0SvmExitXcptDB(pVCpu, pSvmTransient));
5374	case SVM_EXIT_XCPT_AC: VMEXIT_CALL_RET(0, hmR0SvmExitXcptAC(pVCpu, pSvmTransient));
5375	case SVM_EXIT_XCPT_BP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptBP(pVCpu, pSvmTransient));
5376	case SVM_EXIT_XCPT_GP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptGP(pVCpu, pSvmTransient));
5377	case SVM_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0SvmExitXsetbv(pVCpu, pSvmTransient));
5378	case SVM_EXIT_FERR_FREEZE: VMEXIT_CALL_RET(0, hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient));
5379
5380	default:
5381	{
5382	switch (pSvmTransient->u64ExitCode)
5383	{
5384	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5385	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5386	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5387	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5388	VMEXIT_CALL_RET(0, hmR0SvmExitReadDRx(pVCpu, pSvmTransient));
5389
5390	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5391	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5392	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5393	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5394	VMEXIT_CALL_RET(0, hmR0SvmExitWriteDRx(pVCpu, pSvmTransient));
5395
5396	case SVM_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient));
5397	case SVM_EXIT_SHUTDOWN: VMEXIT_CALL_RET(0, hmR0SvmExitShutdown(pVCpu, pSvmTransient));
5398
5399	case SVM_EXIT_SMI:
5400	case SVM_EXIT_INIT:
5401	{
5402	/*
5403	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5404	* If it ever does, we want to know about it so log the exit code and bail.
5405	*/
5406	VMEXIT_CALL_RET(0, hmR0SvmExitUnexpected(pVCpu, pSvmTransient));
5407	}
5408
5409	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5410	case SVM_EXIT_CLGI: VMEXIT_CALL_RET(0, hmR0SvmExitClgi(pVCpu, pSvmTransient));
5411	case SVM_EXIT_STGI: VMEXIT_CALL_RET(0, hmR0SvmExitStgi(pVCpu, pSvmTransient));
5412	case SVM_EXIT_VMLOAD: VMEXIT_CALL_RET(0, hmR0SvmExitVmload(pVCpu, pSvmTransient));
5413	case SVM_EXIT_VMSAVE: VMEXIT_CALL_RET(0, hmR0SvmExitVmsave(pVCpu, pSvmTransient));
5414	case SVM_EXIT_INVLPGA: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpga(pVCpu, pSvmTransient));
5415	case SVM_EXIT_VMRUN: VMEXIT_CALL_RET(0, hmR0SvmExitVmrun(pVCpu, pSvmTransient));
5416	#else
5417	case SVM_EXIT_CLGI:
5418	case SVM_EXIT_STGI:
5419	case SVM_EXIT_VMLOAD:
5420	case SVM_EXIT_VMSAVE:
5421	case SVM_EXIT_INVLPGA:
5422	case SVM_EXIT_VMRUN:
5423	#endif
5424	case SVM_EXIT_RSM:
5425	case SVM_EXIT_SKINIT:
5426	{
5427	hmR0SvmSetPendingXcptUD(pVCpu);
5428	return VINF_SUCCESS;
5429	}
5430
5431	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5432	case SVM_EXIT_XCPT_DE:
5433	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5434	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5435	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5436	case SVM_EXIT_XCPT_OF:
5437	case SVM_EXIT_XCPT_BR:
5438	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5439	case SVM_EXIT_XCPT_NM:
5440	case SVM_EXIT_XCPT_DF:
5441	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5442	case SVM_EXIT_XCPT_TS:
5443	case SVM_EXIT_XCPT_NP:
5444	case SVM_EXIT_XCPT_SS:
5445	/* SVM_EXIT_XCPT_GP: / / Handled above. */
5446	/* SVM_EXIT_XCPT_PF: */
5447	case SVM_EXIT_XCPT_15: /* Reserved. */
5448	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5449	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5450	case SVM_EXIT_XCPT_MC:
5451	case SVM_EXIT_XCPT_XF:
5452	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5453	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5454	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5455	VMEXIT_CALL_RET(0, hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient));
5456	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5457
5458	default:
5459	{
5460	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5461	pVCpu->hm.s.u32HMError = uExitCode;
5462	return VERR_SVM_UNKNOWN_EXIT;
5463	}
5464	}
5465	}
5466	}
5467	/* not reached */
5468	#undef VMEXIT_CALL_RET
5469	}
5470
5471
5472	#ifdef VBOX_STRICT
5473	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5474	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5475	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5476
5477	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5478	do \
5479	{ \
5480	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5481	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5482	} while (0)
5483
5484	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5485	do { \
5486	AssertPtr((a_pVCpu)); \
5487	AssertPtr((a_pSvmTransient)); \
5488	Assert(ASMIntAreEnabled()); \
5489	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5490	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5491	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (a_pVCpu)->idCpu)); \
5492	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5493	if (!VMMRZCallRing3IsEnabled((a_pVCpu))) \
5494	HMSVM_ASSERT_PREEMPT_CPUID(); \
5495	} while (0)
5496	#else
5497	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5498	do { \
5499	RT_NOREF2(a_pVCpu, a_pSvmTransient); \
5500	} while (0)
5501	#endif
5502
5503
5504	/**
5505	* Gets the IEM exception flags for the specified SVM event.
5506	*
5507	* @returns The IEM exception flags.
5508	* @param pEvent Pointer to the SVM event.
5509	*
5510	* @remarks This function currently only constructs flags required for
5511	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5512	* and CR2 aspects of an exception are not included).
5513	*/
5514	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5515	{
5516	uint8_t const uEventType = pEvent->n.u3Type;
5517	uint32_t fIemXcptFlags;
5518	switch (uEventType)
5519	{
5520	case SVM_EVENT_EXCEPTION:
5521	/*
5522	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5523	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5524	*/
5525	if (pEvent->n.u8Vector == X86_XCPT_BP)
5526	{
5527	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5528	break;
5529	}
5530	if (pEvent->n.u8Vector == X86_XCPT_OF)
5531	{
5532	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5533	break;
5534	}
5535	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5536	RT_FALL_THRU();
5537	case SVM_EVENT_NMI:
5538	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5539	break;
5540
5541	case SVM_EVENT_EXTERNAL_IRQ:
5542	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5543	break;
5544
5545	case SVM_EVENT_SOFTWARE_INT:
5546	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5547	break;
5548
5549	default:
5550	fIemXcptFlags = 0;
5551	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5552	break;
5553	}
5554	return fIemXcptFlags;
5555	}
5556
5557
5558	/**
5559	* Handle a condition that occurred while delivering an event through the guest
5560	* IDT.
5561	*
5562	* @returns VBox status code (informational error codes included).
5563	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5564	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5565	* continue execution of the guest which will delivery the \#DF.
5566	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5567	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5568	*
5569	* @param pVCpu The cross context virtual CPU structure.
5570	* @param pSvmTransient Pointer to the SVM transient structure.
5571	*
5572	* @remarks No-long-jump zone!!!
5573	*/
5574	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5575	{
5576	int rc = VINF_SUCCESS;
5577	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5578	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5579
5580	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5581	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5582	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5583
5584	/*
5585	* The EXITINTINFO (if valid) contains the prior exception (IDT vector) that was trying to
5586	* be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector).
5587	*
5588	* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code".
5589	*/
5590	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5591	{
5592	IEMXCPTRAISE enmRaise;
5593	IEMXCPTRAISEINFO fRaiseInfo;
5594	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31;
5595	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5596	if (fExitIsHwXcpt)
5597	{
5598	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0;
5599	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5600	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5601	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5602	}
5603	else
5604	{
5605	/*
5606	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF)
5607	* then we end up here.
5608	*
5609	* If the event was:
5610	* - a software interrupt, we can re-execute the instruction which will
5611	* regenerate the event.
5612	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5613	* - a hardware exception or external interrupt, we re-inject it.
5614	*/
5615	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5616	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5617	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5618	else
5619	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5620	}
5621
5622	switch (enmRaise)
5623	{
5624	case IEMXCPTRAISE_CURRENT_XCPT:
5625	case IEMXCPTRAISE_PREV_EVENT:
5626	{
5627	/* For software interrupts, we shall re-execute the instruction. */
5628	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5629	{
5630	RTGCUINTPTR GCPtrFaultAddress = 0;
5631
5632	/* If we are re-injecting an NMI, clear NMI blocking. */
5633	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5634	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5635
5636	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5637	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5638	{
5639	pSvmTransient->fVectoringPF = true;
5640	Log4Func(("IDT: Pending vectoring #PF due to delivery of Ext-Int/NMI. uCR2=%#RX64\n",
5641	pVCpu->cpum.GstCtx.cr2));
5642	}
5643	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5644	&& uIdtVector == X86_XCPT_PF)
5645	{
5646	/*
5647	* If the previous exception was a #PF, we need to recover the CR2 value.
5648	* This can't happen with shadow paging.
5649	*/
5650	GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
5651	}
5652
5653	/*
5654	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5655	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5656	*/
5657	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5658	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflect);
5659	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5660
5661	Log4Func(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5662	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5663	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5664	}
5665	break;
5666	}
5667
5668	case IEMXCPTRAISE_REEXEC_INSTR:
5669	{
5670	Assert(rc == VINF_SUCCESS);
5671	break;
5672	}
5673
5674	case IEMXCPTRAISE_DOUBLE_FAULT:
5675	{
5676	/*
5677	* Determing a vectoring double #PF condition. Used later, when PGM evaluates
5678	* the second #PF as a guest #PF (and not a shadow #PF) and needs to be
5679	* converted into a #DF.
5680	*/
5681	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5682	{
5683	Log4Func(("IDT: Pending vectoring double #PF uCR2=%#RX64\n", pVCpu->cpum.GstCtx.cr2));
5684	pSvmTransient->fVectoringDoublePF = true;
5685	Assert(rc == VINF_SUCCESS);
5686	}
5687	else
5688	{
5689	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectConvertDF);
5690	hmR0SvmSetPendingXcptDF(pVCpu);
5691	rc = VINF_HM_DOUBLE_FAULT;
5692	}
5693	break;
5694	}
5695
5696	case IEMXCPTRAISE_TRIPLE_FAULT:
5697	{
5698	rc = VINF_EM_RESET;
5699	break;
5700	}
5701
5702	case IEMXCPTRAISE_CPU_HANG:
5703	{
5704	rc = VERR_EM_GUEST_CPU_HANG;
5705	break;
5706	}
5707
5708	default:
5709	AssertMsgFailedBreakStmt(("Bogus enmRaise value: %d (%#x)\n", enmRaise, enmRaise), rc = VERR_SVM_IPE_2);
5710	}
5711	}
5712	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
5713	return rc;
5714	}
5715
5716
5717	/**
5718	* Advances the guest RIP by the number of bytes specified in @a cb.
5719	*
5720	* @param pVCpu The cross context virtual CPU structure.
5721	* @param cb RIP increment value in bytes.
5722	*/
5723	DECLINLINE(void) hmR0SvmAdvanceRip(PVMCPUCC pVCpu, uint32_t cb)
5724	{
5725	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
5726	pCtx->rip += cb;
5727
5728	/* Update interrupt shadow. */
5729	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
5730	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
5731	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
5732	}
5733
5734
5735	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5736	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
5737	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5738
5739	/** @name \#VMEXIT handlers.
5740	* @{
5741	*/
5742
5743	/**
5744	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
5745	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
5746	*/
5747	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5748	{
5749	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5750
5751	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
5752	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
5753	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
5754	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
5755
5756	/*
5757	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to
5758	* signal -before- the timer fires if the current interrupt is our own timer or a some
5759	* other host interrupt. We also cannot examine what interrupt it is until the host
5760	* actually take the interrupt.
5761	*
5762	* Going back to executing guest code here unconditionally causes random scheduling
5763	* problems (observed on an AMD Phenom 9850 Quad-Core on Windows 64-bit host).
5764	*/
5765	return VINF_EM_RAW_INTERRUPT;
5766	}
5767
5768
5769	/**
5770	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
5771	*/
5772	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5773	{
5774	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5775
5776	VBOXSTRICTRC rcStrict;
5777	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5778	if (fSupportsNextRipSave)
5779	{
5780	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5781	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5782	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5783	rcStrict = IEMExecDecodedWbinvd(pVCpu, cbInstr);
5784	}
5785	else
5786	{
5787	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5788	rcStrict = IEMExecOne(pVCpu);
5789	}
5790
5791	if (rcStrict == VINF_IEM_RAISED_XCPT)
5792	{
5793	rcStrict = VINF_SUCCESS;
5794	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5795	}
5796	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5797	return rcStrict;
5798	}
5799
5800
5801	/**
5802	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
5803	*/
5804	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5805	{
5806	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5807
5808	VBOXSTRICTRC rcStrict;
5809	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5810	if (fSupportsNextRipSave)
5811	{
5812	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5813	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5814	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5815	rcStrict = IEMExecDecodedInvd(pVCpu, cbInstr);
5816	}
5817	else
5818	{
5819	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5820	rcStrict = IEMExecOne(pVCpu);
5821	}
5822
5823	if (rcStrict == VINF_IEM_RAISED_XCPT)
5824	{
5825	rcStrict = VINF_SUCCESS;
5826	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5827	}
5828	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5829	return rcStrict;
5830	}
5831
5832
5833	/**
5834	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
5835	*/
5836	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5837	{
5838	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5839
5840	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX);
5841	VBOXSTRICTRC rcStrict;
5842	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
5843	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_CPUID),
5844	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
5845	if (!pExitRec)
5846	{
5847	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5848	if (fSupportsNextRipSave)
5849	{
5850	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5851	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5852	rcStrict = IEMExecDecodedCpuid(pVCpu, cbInstr);
5853	}
5854	else
5855	{
5856	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5857	rcStrict = IEMExecOne(pVCpu);
5858	}
5859
5860	if (rcStrict == VINF_IEM_RAISED_XCPT)
5861	{
5862	rcStrict = VINF_SUCCESS;
5863	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5864	}
5865	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5866	}
5867	else
5868	{
5869	/*
5870	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
5871	*/
5872	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5873
5874	Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
5875	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
5876
5877	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
5878
5879	Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
5880	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
5881	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
5882	}
5883	return rcStrict;
5884	}
5885
5886
5887	/**
5888	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
5889	*/
5890	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5891	{
5892	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5893
5894	VBOXSTRICTRC rcStrict;
5895	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5896	if (fSupportsNextRipSave)
5897	{
5898	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
5899	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5900	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5901	rcStrict = IEMExecDecodedRdtsc(pVCpu, cbInstr);
5902	}
5903	else
5904	{
5905	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5906	rcStrict = IEMExecOne(pVCpu);
5907	}
5908
5909	if (rcStrict == VINF_SUCCESS)
5910	pSvmTransient->fUpdateTscOffsetting = true;
5911	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5912	{
5913	rcStrict = VINF_SUCCESS;
5914	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5915	}
5916	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5917	return rcStrict;
5918	}
5919
5920
5921	/**
5922	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
5923	*/
5924	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5925	{
5926	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5927
5928	VBOXSTRICTRC rcStrict;
5929	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5930	if (fSupportsNextRipSave)
5931	{
5932	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_TSC_AUX);
5933	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5934	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5935	rcStrict = IEMExecDecodedRdtscp(pVCpu, cbInstr);
5936	}
5937	else
5938	{
5939	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5940	rcStrict = IEMExecOne(pVCpu);
5941	}
5942
5943	if (rcStrict == VINF_SUCCESS)
5944	pSvmTransient->fUpdateTscOffsetting = true;
5945	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5946	{
5947	rcStrict = VINF_SUCCESS;
5948	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5949	}
5950	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5951	return rcStrict;
5952	}
5953
5954
5955	/**
5956	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
5957	*/
5958	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5959	{
5960	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5961
5962	VBOXSTRICTRC rcStrict;
5963	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5964	if (fSupportsNextRipSave)
5965	{
5966	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
5967	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5968	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5969	rcStrict = IEMExecDecodedRdpmc(pVCpu, cbInstr);
5970	}
5971	else
5972	{
5973	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5974	rcStrict = IEMExecOne(pVCpu);
5975	}
5976
5977	if (rcStrict == VINF_IEM_RAISED_XCPT)
5978	{
5979	rcStrict = VINF_SUCCESS;
5980	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5981	}
5982	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5983	return rcStrict;
5984	}
5985
5986
5987	/**
5988	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
5989	*/
5990	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5991	{
5992	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5993	Assert(!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
5994
5995	VBOXSTRICTRC rcStrict;
5996	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
5997	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5998	if ( fSupportsDecodeAssists
5999	&& fSupportsNextRipSave)
6000	{
6001	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
6002	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6003	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6004	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6005	rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6006	}
6007	else
6008	{
6009	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6010	rcStrict = IEMExecOne(pVCpu);
6011	}
6012
6013	if (rcStrict == VINF_IEM_RAISED_XCPT)
6014	{
6015	rcStrict = VINF_SUCCESS;
6016	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6017	}
6018	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6019	return VBOXSTRICTRC_VAL(rcStrict);
6020	}
6021
6022
6023	/**
6024	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6025	*/
6026	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6027	{
6028	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6029
6030	VBOXSTRICTRC rcStrict;
6031	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6032	if (fSupportsNextRipSave)
6033	{
6034	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6035	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6036	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6037	rcStrict = IEMExecDecodedHlt(pVCpu, cbInstr);
6038	}
6039	else
6040	{
6041	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6042	rcStrict = IEMExecOne(pVCpu);
6043	}
6044
6045	if ( rcStrict == VINF_EM_HALT
6046	\|\| rcStrict == VINF_SUCCESS)
6047	rcStrict = EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6048	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6049	{
6050	rcStrict = VINF_SUCCESS;
6051	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6052	}
6053	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6054	if (rcStrict != VINF_SUCCESS)
6055	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6056	return VBOXSTRICTRC_VAL(rcStrict);;
6057	}
6058
6059
6060	/**
6061	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6062	*/
6063	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6064	{
6065	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6066
6067	/*
6068	* If the instruction length is supplied by the CPU is 3 bytes, we can be certain that no
6069	* segment override prefix is present (and thus use the default segment DS). Otherwise, a
6070	* segment override prefix or other prefixes might be used, in which case we fallback to
6071	* IEMExecOne() to figure out.
6072	*/
6073	VBOXSTRICTRC rcStrict;
6074	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6075	uint8_t const cbInstr = hmR0SvmSupportsNextRipSave(pVCpu) ? pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip : 0;
6076	if (cbInstr)
6077	{
6078	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_DS);
6079	rcStrict = IEMExecDecodedMonitor(pVCpu, cbInstr);
6080	}
6081	else
6082	{
6083	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6084	rcStrict = IEMExecOne(pVCpu);
6085	}
6086
6087	if (rcStrict == VINF_IEM_RAISED_XCPT)
6088	{
6089	rcStrict = VINF_SUCCESS;
6090	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6091	}
6092	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6093	return rcStrict;
6094	}
6095
6096
6097	/**
6098	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6099	*/
6100	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6101	{
6102	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6103
6104	VBOXSTRICTRC rcStrict;
6105	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6106	if (fSupportsNextRipSave)
6107	{
6108	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6109	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6110	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6111	rcStrict = IEMExecDecodedMwait(pVCpu, cbInstr);
6112	}
6113	else
6114	{
6115	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6116	rcStrict = IEMExecOne(pVCpu);
6117	}
6118
6119	if ( rcStrict == VINF_EM_HALT
6120	&& EMMonitorWaitShouldContinue(pVCpu, &pVCpu->cpum.GstCtx))
6121	rcStrict = VINF_SUCCESS;
6122	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6123	{
6124	rcStrict = VINF_SUCCESS;
6125	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6126	}
6127	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6128	return rcStrict;
6129	}
6130
6131
6132	/**
6133	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6134	* \#VMEXIT.
6135	*/
6136	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6137	{
6138	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6139	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6140	return VINF_EM_RESET;
6141	}
6142
6143
6144	/**
6145	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6146	*/
6147	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6148	{
6149	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6150	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6151	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pSvmTransient->u64ExitCode,
6152	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2));
6153	RT_NOREF(pVmcb);
6154	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6155	return VERR_SVM_UNEXPECTED_EXIT;
6156	}
6157
6158
6159	/**
6160	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6161	*/
6162	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6163	{
6164	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6165
6166	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6167	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6168	#ifdef VBOX_WITH_STATISTICS
6169	switch (pSvmTransient->u64ExitCode)
6170	{
6171	case SVM_EXIT_READ_CR0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
6172	case SVM_EXIT_READ_CR2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
6173	case SVM_EXIT_READ_CR3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
6174	case SVM_EXIT_READ_CR4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
6175	case SVM_EXIT_READ_CR8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
6176	}
6177	#endif
6178
6179	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6180	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6181	if ( fSupportsDecodeAssists
6182	&& fSupportsNextRipSave)
6183	{
6184	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6185	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6186	if (fMovCRx)
6187	{
6188	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR_MASK
6189	\| CPUMCTX_EXTRN_APIC_TPR);
6190	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6191	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6192	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6193	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6194	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6195	return VBOXSTRICTRC_VAL(rcStrict);
6196	}
6197	/* else: SMSW instruction, fall back below to IEM for this. */
6198	}
6199
6200	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6201	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6202	AssertMsg( rcStrict == VINF_SUCCESS
6203	\|\| rcStrict == VINF_PGM_SYNC_CR3
6204	\|\| rcStrict == VINF_IEM_RAISED_XCPT,
6205	("hmR0SvmExitReadCRx: IEMExecOne failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6206	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6207	if (rcStrict == VINF_IEM_RAISED_XCPT)
6208	{
6209	rcStrict = VINF_SUCCESS;
6210	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6211	}
6212	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6213	return rcStrict;
6214	}
6215
6216
6217	/**
6218	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6219	*/
6220	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6221	{
6222	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6223
6224	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
6225	uint8_t const iCrReg = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0);
6226	Assert(iCrReg <= 15);
6227
6228	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6229	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6230	bool fDecodedInstr = false;
6231	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6232	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6233	if ( fSupportsDecodeAssists
6234	&& fSupportsNextRipSave)
6235	{
6236	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6237	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6238	if (fMovCRx)
6239	{
6240	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4
6241	\| CPUMCTX_EXTRN_APIC_TPR);
6242	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6243	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6244	Log4Func(("Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6245	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6246	fDecodedInstr = true;
6247	}
6248	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6249	}
6250
6251	if (!fDecodedInstr)
6252	{
6253	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6254	Log4Func(("iCrReg=%#x\n", iCrReg));
6255	rcStrict = IEMExecOne(pVCpu);
6256	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6257	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6258	rcStrict = VERR_EM_INTERPRETER;
6259	}
6260
6261	if (rcStrict == VINF_SUCCESS)
6262	{
6263	switch (iCrReg)
6264	{
6265	case 0:
6266	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
6267	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
6268	break;
6269
6270	case 2:
6271	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
6272	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
6273	break;
6274
6275	case 3:
6276	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR3);
6277	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
6278	break;
6279
6280	case 4:
6281	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
6282	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
6283	break;
6284
6285	case 8:
6286	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6287	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
6288	break;
6289
6290	default:
6291	{
6292	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6293	pSvmTransient->u64ExitCode, iCrReg));
6294	break;
6295	}
6296	}
6297	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6298	}
6299	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6300	{
6301	rcStrict = VINF_SUCCESS;
6302	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6303	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6304	}
6305	else
6306	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_SYNC_CR3);
6307	return rcStrict;
6308	}
6309
6310
6311	/**
6312	* \#VMEXIT helper for read MSRs, see hmR0SvmExitMsr.
6313	*
6314	* @returns Strict VBox status code.
6315	* @param pVCpu The cross context virtual CPU structure.
6316	* @param pVmcb Pointer to the VM control block.
6317	*/
6318	static VBOXSTRICTRC hmR0SvmExitReadMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
6319	{
6320	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6321	Log4Func(("idMsr=%#RX32\n", pVCpu->cpum.GstCtx.ecx));
6322
6323	VBOXSTRICTRC rcStrict;
6324	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6325	if (fSupportsNextRipSave)
6326	{
6327	/** @todo Optimize this: Only retrieve the MSR bits we need here. CPUMAllMsrs.cpp
6328	* can ask for what it needs instead of using CPUMCTX_EXTRN_ALL_MSRS. */
6329	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6330	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6331	rcStrict = IEMExecDecodedRdmsr(pVCpu, cbInstr);
6332	}
6333	else
6334	{
6335	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6336	rcStrict = IEMExecOne(pVCpu);
6337	}
6338
6339	AssertMsg( rcStrict == VINF_SUCCESS
6340	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6341	\|\| rcStrict == VINF_CPUM_R3_MSR_READ,
6342	("hmR0SvmExitReadMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6343
6344	if (rcStrict == VINF_IEM_RAISED_XCPT)
6345	{
6346	rcStrict = VINF_SUCCESS;
6347	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6348	}
6349	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6350	return rcStrict;
6351	}
6352
6353
6354	/**
6355	* \#VMEXIT helper for write MSRs, see hmR0SvmExitMsr.
6356	*
6357	* @returns Strict VBox status code.
6358	* @param pVCpu The cross context virtual CPU structure.
6359	* @param pVmcb Pointer to the VM control block.
6360	* @param pSvmTransient Pointer to the SVM-transient structure.
6361	*/
6362	static VBOXSTRICTRC hmR0SvmExitWriteMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMTRANSIENT pSvmTransient)
6363	{
6364	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6365	uint32_t const idMsr = pCtx->ecx;
6366	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6367	Log4Func(("idMsr=%#RX32\n", idMsr));
6368
6369	/*
6370	* Handle TPR patching MSR writes.
6371	* We utilitize the LSTAR MSR for patching.
6372	*/
6373	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6374	if ( idMsr == MSR_K8_LSTAR
6375	&& pVCpu->CTX_SUFF(pVM)->hm.s.fTprPatchingActive)
6376	{
6377	unsigned cbInstr;
6378	if (fSupportsNextRipSave)
6379	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6380	else
6381	{
6382	PDISCPUSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
6383	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
6384	if ( rc == VINF_SUCCESS
6385	&& pDis->pCurInstr->uOpcode == OP_WRMSR)
6386	Assert(cbInstr > 0);
6387	else
6388	cbInstr = 0;
6389	}
6390
6391	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6392	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6393	{
6394	int rc = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6395	AssertRCReturn(rc, rc);
6396	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6397	}
6398
6399	int rc = VINF_SUCCESS;
6400	hmR0SvmAdvanceRip(pVCpu, cbInstr);
6401	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6402	return rc;
6403	}
6404
6405	/*
6406	* Handle regular MSR writes.
6407	*/
6408	VBOXSTRICTRC rcStrict;
6409	if (fSupportsNextRipSave)
6410	{
6411	/** @todo Optimize this: We don't need to get much of the MSR state here
6412	* since we're only updating. CPUMAllMsrs.cpp can ask for what it needs and
6413	* clear the applicable extern flags. */
6414	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6415	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6416	rcStrict = IEMExecDecodedWrmsr(pVCpu, cbInstr);
6417	}
6418	else
6419	{
6420	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6421	rcStrict = IEMExecOne(pVCpu);
6422	}
6423
6424	AssertMsg( rcStrict == VINF_SUCCESS
6425	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6426	\|\| rcStrict == VINF_CPUM_R3_MSR_WRITE,
6427	("hmR0SvmExitWriteMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6428
6429	if (rcStrict == VINF_SUCCESS)
6430	{
6431	/* If this is an X2APIC WRMSR access, update the APIC TPR state. */
6432	if ( idMsr >= MSR_IA32_X2APIC_START
6433	&& idMsr <= MSR_IA32_X2APIC_END)
6434	{
6435	/*
6436	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest().
6437	* When full APIC register virtualization is implemented we'll have to make sure
6438	* APIC state is saved from the VMCB before IEM changes it.
6439	*/
6440	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6441	}
6442	else
6443	{
6444	switch (idMsr)
6445	{
6446	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6447	case MSR_K6_EFER: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR); break;
6448	case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
6449	case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
6450	case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6451	case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6452	case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6453	}
6454	}
6455	}
6456	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6457	{
6458	rcStrict = VINF_SUCCESS;
6459	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6460	}
6461	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6462	return rcStrict;
6463	}
6464
6465
6466	/**
6467	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6468	* \#VMEXIT.
6469	*/
6470	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6471	{
6472	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6473
6474	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6475	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ)
6476	return hmR0SvmExitReadMsr(pVCpu, pVmcb);
6477
6478	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE);
6479	return hmR0SvmExitWriteMsr(pVCpu, pVmcb, pSvmTransient);
6480	}
6481
6482
6483	/**
6484	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6485	*/
6486	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6487	{
6488	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6489	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6490
6491	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6492
6493	/** @todo Stepping with nested-guest. */
6494	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6495	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6496	{
6497	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6498	if (pSvmTransient->fWasGuestDebugStateActive)
6499	{
6500	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6501	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6502	return VERR_SVM_UNEXPECTED_EXIT;
6503	}
6504
6505	/*
6506	* Lazy DR0-3 loading.
6507	*/
6508	if (!pSvmTransient->fWasHyperDebugStateActive)
6509	{
6510	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6511	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6512
6513	/* Don't intercept DRx read and writes. */
6514	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
6515	pVmcb->ctrl.u16InterceptRdDRx = 0;
6516	pVmcb->ctrl.u16InterceptWrDRx = 0;
6517	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6518
6519	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6520	VMMRZCallRing3Disable(pVCpu);
6521	HM_DISABLE_PREEMPT(pVCpu);
6522
6523	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6524	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6525	Assert(CPUMIsGuestDebugStateActive(pVCpu));
6526
6527	HM_RESTORE_PREEMPT();
6528	VMMRZCallRing3Enable(pVCpu);
6529
6530	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6531	return VINF_SUCCESS;
6532	}
6533	}
6534
6535	/*
6536	* Interpret the read/writing of DRx.
6537	*/
6538	/** @todo Decode assist. */
6539	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6540	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6541	if (RT_LIKELY(rc == VINF_SUCCESS))
6542	{
6543	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6544	/** @todo CPUM should set this flag! */
6545	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR_MASK);
6546	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6547	}
6548	else
6549	Assert(rc == VERR_EM_INTERPRETER);
6550	return rc;
6551	}
6552
6553
6554	/**
6555	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6556	*/
6557	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6558	{
6559	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6560	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6561	VBOXSTRICTRC rc = hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
6562	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6563	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6564	return rc;
6565	}
6566
6567
6568	/**
6569	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6570	*/
6571	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6572	{
6573	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6574	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6575
6576	/** @todo decode assists... */
6577	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6578	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
6579	{
6580	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6581	bool const fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6582	Log4Func(("New XCR0=%#RX64 fLoadSaveGuestXcr0=%RTbool (cr4=%#RX64)\n", pCtx->aXcr[0], fLoadSaveGuestXcr0, pCtx->cr4));
6583	if (fLoadSaveGuestXcr0 != pVCpu->hmr0.s.fLoadSaveGuestXcr0)
6584	{
6585	pVCpu->hmr0.s.fLoadSaveGuestXcr0 = fLoadSaveGuestXcr0;
6586	hmR0SvmUpdateVmRunFunction(pVCpu);
6587	}
6588	}
6589	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6590	{
6591	rcStrict = VINF_SUCCESS;
6592	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6593	}
6594	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6595	return rcStrict;
6596	}
6597
6598
6599	/**
6600	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6601	*/
6602	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6603	{
6604	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6605	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_SREG_MASK);
6606
6607	/* I/O operation lookup arrays. */
6608	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6609	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6610	the result (in AL/AX/EAX). */
6611	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6612	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6613	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6614
6615	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6616
6617	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6618	SVMIOIOEXITINFO IoExitInfo;
6619	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6620	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6621	uint32_t cbValue = s_aIOSize[uIOWidth];
6622	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6623
6624	if (RT_UNLIKELY(!cbValue))
6625	{
6626	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6627	return VERR_EM_INTERPRETER;
6628	}
6629
6630	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
6631	VBOXSTRICTRC rcStrict;
6632	PCEMEXITREC pExitRec = NULL;
6633	if ( !pVCpu->hm.s.fSingleInstruction
6634	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1TF)
6635	pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6636	!IoExitInfo.n.u1Str
6637	? IoExitInfo.n.u1Type == SVM_IOIO_READ
6638	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
6639	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
6640	: IoExitInfo.n.u1Type == SVM_IOIO_READ
6641	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
6642	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
6643	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6644	if (!pExitRec)
6645	{
6646	bool fUpdateRipAlready = false;
6647	if (IoExitInfo.n.u1Str)
6648	{
6649	/* INS/OUTS - I/O String instruction. */
6650	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6651	* in EXITINFO1? Investigate once this thing is up and running. */
6652	Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6653	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6654	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6655	static IEMMODE const s_aenmAddrMode[8] =
6656	{
6657	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6658	};
6659	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6660	if (enmAddrMode != (IEMMODE)-1)
6661	{
6662	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6663	if (cbInstr <= 15 && cbInstr >= 1)
6664	{
6665	Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep);
6666	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6667	{
6668	/* Don't know exactly how to detect whether u3Seg is valid, currently
6669	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6670	2384 Opterons when only checking NRIP. */
6671	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6672	if ( fSupportsNextRipSave
6673	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6674	{
6675	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1Rep,
6676	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep));
6677	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6678	IoExitInfo.n.u3Seg, true /fIoChecked/);
6679	}
6680	else if (cbInstr == 1U + IoExitInfo.n.u1Rep)
6681	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6682	X86_SREG_DS, true /fIoChecked/);
6683	else
6684	rcStrict = IEMExecOne(pVCpu);
6685	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6686	}
6687	else
6688	{
6689	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3Seg));
6690	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6691	true /fIoChecked/);
6692	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6693	}
6694	}
6695	else
6696	{
6697	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6698	rcStrict = IEMExecOne(pVCpu);
6699	}
6700	}
6701	else
6702	{
6703	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6704	rcStrict = IEMExecOne(pVCpu);
6705	}
6706	fUpdateRipAlready = true;
6707	}
6708	else
6709	{
6710	/* IN/OUT - I/O instruction. */
6711	Assert(!IoExitInfo.n.u1Rep);
6712
6713	uint8_t const cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6714	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6715	{
6716	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6717	if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6718	&& !pCtx->eflags.Bits.u1TF)
6719	rcStrict = EMRZSetPendingIoPortWrite(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue, pCtx->eax & uAndVal);
6720	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6721	}
6722	else
6723	{
6724	uint32_t u32Val = 0;
6725	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6726	if (IOM_SUCCESS(rcStrict))
6727	{
6728	/* Save result of I/O IN instr. in AL/AX/EAX. */
6729	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6730	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6731	}
6732	else if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6733	&& !pCtx->eflags.Bits.u1TF)
6734	rcStrict = EMRZSetPendingIoPortRead(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue);
6735
6736	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6737	}
6738	}
6739
6740	if (IOM_SUCCESS(rcStrict))
6741	{
6742	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6743	if (!fUpdateRipAlready)
6744	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6745
6746	/*
6747	* If any I/O breakpoints are armed, we need to check if one triggered
6748	* and take appropriate action.
6749	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6750	*/
6751	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6752	* execution engines about whether hyper BPs and such are pending. */
6753	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
6754	uint32_t const uDr7 = pCtx->dr[7];
6755	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6756	&& X86_DR7_ANY_RW_IO(uDr7)
6757	&& (pCtx->cr4 & X86_CR4_DE))
6758	\|\| DBGFBpIsHwIoArmed(pVM)))
6759	{
6760	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6761	VMMRZCallRing3Disable(pVCpu);
6762	HM_DISABLE_PREEMPT(pVCpu);
6763
6764	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6765	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6766
6767	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, &pVCpu->cpum.GstCtx, IoExitInfo.n.u16Port, cbValue);
6768	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6769	{
6770	/* Raise #DB. */
6771	pVmcb->guest.u64DR6 = pCtx->dr[6];
6772	pVmcb->guest.u64DR7 = pCtx->dr[7];
6773	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6774	hmR0SvmSetPendingXcptDB(pVCpu);
6775	}
6776	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6777	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6778	else if ( rcStrict2 != VINF_SUCCESS
6779	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6780	rcStrict = rcStrict2;
6781	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6782
6783	HM_RESTORE_PREEMPT();
6784	VMMRZCallRing3Enable(pVCpu);
6785	}
6786
6787	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6788	}
6789
6790	#ifdef VBOX_STRICT
6791	if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6792	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
6793	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6794	else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6795	\|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
6796	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
6797	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6798	else
6799	{
6800	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6801	* statuses, that the VMM device and some others may return. See
6802	* IOM_SUCCESS() for guidance. */
6803	AssertMsg( RT_FAILURE(rcStrict)
6804	\|\| rcStrict == VINF_SUCCESS
6805	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6806	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6807	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6808	\|\| rcStrict == VINF_EM_DBG_STEPPED
6809	\|\| rcStrict == VINF_EM_RAW_TO_R3
6810	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
6811	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6812	}
6813	#endif
6814	}
6815	else
6816	{
6817	/*
6818	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6819	*/
6820	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6821	STAM_COUNTER_INC(!IoExitInfo.n.u1Str
6822	? IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
6823	: IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
6824	Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
6825	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IoExitInfo.n.u1Rep ? "REP " : "",
6826	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? "OUT" : "IN", IoExitInfo.n.u1Str ? "S" : "", IoExitInfo.n.u16Port, uIOWidth));
6827
6828	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6829	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
6830
6831	Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6832	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6833	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6834	}
6835	return rcStrict;
6836	}
6837
6838
6839	/**
6840	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
6841	*/
6842	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6843	{
6844	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6845	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6846	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
6847
6848	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6849	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6850	Assert(pVM->hmr0.s.fNestedPaging);
6851
6852	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
6853	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6854	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
6855	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1; /* Note! High bits in EXITINFO1 may contain additional info and are
6856	thus intentionally not copied into u32ErrCode. */
6857
6858	Log4Func(("#NPF at CS:RIP=%04x:%#RX64 GCPhysFaultAddr=%RGp ErrCode=%#x cbInstrFetched=%u %.15Rhxs\n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr,
6859	u32ErrCode, pVmcb->ctrl.cbInstrFetched, pVmcb->ctrl.abInstr));
6860
6861	/*
6862	* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions.
6863	*/
6864	if ( pVM->hm.s.fTprPatchingAllowed
6865	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
6866	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
6867	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
6868	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
6869	&& !CPUMIsGuestInLongModeEx(pCtx)
6870	&& !CPUMGetGuestCPL(pVCpu)
6871	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6872	{
6873	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6874	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6875
6876	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
6877	{
6878	/* Only attempt to patch the instruction once. */
6879	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6880	if (!pPatch)
6881	return VINF_EM_HM_PATCH_TPR_INSTR;
6882	}
6883	}
6884
6885	/*
6886	* Determine the nested paging mode.
6887	*/
6888	/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
6889	PGMMODE const enmNestedPagingMode = PGMGetHostMode(pVM);
6890
6891	/*
6892	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
6893	*/
6894	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
6895	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
6896	{
6897	/*
6898	* If event delivery causes an MMIO #NPF, go back to instruction emulation as otherwise
6899	* injecting the original pending event would most likely cause the same MMIO #NPF.
6900	*/
6901	if (pVCpu->hm.s.Event.fPending)
6902	{
6903	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
6904	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6905	}
6906
6907	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
6908	VBOXSTRICTRC rcStrict;
6909	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6910	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_MMIO),
6911	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6912	if (!pExitRec)
6913	{
6914
6915	rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
6916	u32ErrCode);
6917
6918	/*
6919	* If we succeed, resume guest execution.
6920	*
6921	* If we fail in interpreting the instruction because we couldn't get the guest
6922	* physical address of the page containing the instruction via the guest's page
6923	* tables (we would invalidate the guest page in the host TLB), resume execution
6924	* which would cause a guest page fault to let the guest handle this weird case.
6925	*
6926	* See @bugref{6043}.
6927	*/
6928	if ( rcStrict == VINF_SUCCESS
6929	\|\| rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
6930	\|\| rcStrict == VERR_PAGE_NOT_PRESENT)
6931	{
6932	/* Successfully handled MMIO operation. */
6933	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6934	rcStrict = VINF_SUCCESS;
6935	}
6936	}
6937	else
6938	{
6939	/*
6940	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6941	*/
6942	Assert(pCtx == &pVCpu->cpum.GstCtx);
6943	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6944	Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
6945	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysFaultAddr));
6946
6947	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6948	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
6949
6950	Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6951	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6952	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6953	}
6954	return rcStrict;
6955	}
6956
6957	/*
6958	* Nested page-fault.
6959	*/
6960	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
6961	int rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
6962	TRPMResetTrap(pVCpu);
6963
6964	Log4Func(("#NPF: PGMR0Trap0eHandlerNestedPaging returns %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
6965
6966	/*
6967	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
6968	*/
6969	if ( rc == VINF_SUCCESS
6970	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6971	\|\| rc == VERR_PAGE_NOT_PRESENT)
6972	{
6973	/* We've successfully synced our shadow page tables. */
6974	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6975	rc = VINF_SUCCESS;
6976	}
6977
6978	/*
6979	* If delivering an event causes an #NPF (and not MMIO), we shall resolve the fault and
6980	* re-inject the original event.
6981	*/
6982	if (pVCpu->hm.s.Event.fPending)
6983	{
6984	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflectNPF);
6985
6986	/*
6987	* If the #NPF handler requested emulation of the instruction, ignore it.
6988	* We need to re-inject the original event so as to not lose it.
6989	* Reproducible when booting ReactOS 0.4.12 with BTRFS (installed using BootCD,
6990	* LiveCD is broken for other reasons).
6991	*/
6992	if (rc == VINF_EM_RAW_EMULATE_INSTR)
6993	rc = VINF_EM_RAW_INJECT_TRPM_EVENT;
6994	}
6995
6996	return rc;
6997	}
6998
6999
7000	/**
7001	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
7002	* \#VMEXIT.
7003	*/
7004	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7005	{
7006	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7007	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7008
7009	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7010	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7011	hmR0SvmClearIntWindowExiting(pVCpu, pVmcb);
7012
7013	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7014	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
7015	return VINF_SUCCESS;
7016	}
7017
7018
7019	/**
7020	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
7021	* \#VMEXIT.
7022	*/
7023	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7024	{
7025	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7026	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7027
7028	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
7029	Assert(!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
7030	#endif
7031
7032	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
7033	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
7034	{
7035	/*
7036	* AMD-V provides us with the exception which caused the TS; we collect
7037	* the information in the call to hmR0SvmCheckExitDueToEventDelivery().
7038	*/
7039	Log4Func(("TS occurred during event delivery\n"));
7040	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7041	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7042	}
7043
7044	/** @todo Emulate task switch someday, currently just going back to ring-3 for
7045	* emulation. */
7046	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7047	return VERR_EM_INTERPRETER;
7048	}
7049
7050
7051	/**
7052	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7053	*/
7054	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7055	{
7056	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7057	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7058
7059	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7060	if (pVM->hm.s.fTprPatchingAllowed)
7061	{
7062	int rc = hmEmulateSvmMovTpr(pVM, pVCpu);
7063	if (rc != VERR_NOT_FOUND)
7064	{
7065	Log4Func(("hmEmulateSvmMovTpr returns %Rrc\n", rc));
7066	return rc;
7067	}
7068	}
7069
7070	if (EMAreHypercallInstructionsEnabled(pVCpu))
7071	{
7072	unsigned cbInstr;
7073	if (hmR0SvmSupportsNextRipSave(pVCpu))
7074	{
7075	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7076	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7077	}
7078	else
7079	{
7080	PDISCPUSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
7081	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7082	if ( rc == VINF_SUCCESS
7083	&& pDis->pCurInstr->uOpcode == OP_VMMCALL)
7084	Assert(cbInstr > 0);
7085	else
7086	cbInstr = 0;
7087	}
7088
7089	VBOXSTRICTRC rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
7090	if (RT_SUCCESS(rcStrict))
7091	{
7092	/* Only update the RIP if we're continuing guest execution and not in the case
7093	of say VINF_GIM_R3_HYPERCALL. */
7094	if (rcStrict == VINF_SUCCESS)
7095	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7096
7097	return VBOXSTRICTRC_VAL(rcStrict);
7098	}
7099	else
7100	Log4Func(("GIMHypercall returns %Rrc -> #UD\n", VBOXSTRICTRC_VAL(rcStrict)));
7101	}
7102
7103	hmR0SvmSetPendingXcptUD(pVCpu);
7104	return VINF_SUCCESS;
7105	}
7106
7107
7108	/**
7109	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7110	*/
7111	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7112	{
7113	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7114
7115	unsigned cbInstr;
7116	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7117	if (fSupportsNextRipSave)
7118	{
7119	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7120	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7121	}
7122	else
7123	{
7124	PDISCPUSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
7125	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7126	if ( rc == VINF_SUCCESS
7127	&& pDis->pCurInstr->uOpcode == OP_PAUSE)
7128	Assert(cbInstr > 0);
7129	else
7130	cbInstr = 0;
7131	}
7132
7133	/** @todo The guest has likely hit a contended spinlock. We might want to
7134	* poke a schedule different guest VCPU. */
7135	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7136	return VINF_EM_RAW_INTERRUPT;
7137	}
7138
7139
7140	/**
7141	* \#VMEXIT handler for FERR intercept (SVM_EXIT_FERR_FREEZE). Conditional
7142	* \#VMEXIT.
7143	*/
7144	HMSVM_EXIT_DECL hmR0SvmExitFerrFreeze(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7145	{
7146	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7147	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
7148	Assert(!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE));
7149
7150	Log4Func(("Raising IRQ 13 in response to #FERR\n"));
7151	return PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7152	}
7153
7154
7155	/**
7156	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7157	*/
7158	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7159	{
7160	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7161
7162	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now (almost) ready. */
7163	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7164	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_IRET);
7165
7166	/* Emulate the IRET. We have to execute the IRET before an NMI, but must potentially
7167	* deliver a pending NMI right after. If the IRET faults, an NMI can come before the
7168	* handler executes. Yes, x86 is ugly.
7169	*/
7170	return VINF_EM_RAW_EMULATE_INSTR;
7171	}
7172
7173
7174	/**
7175	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_XCPT_14).
7176	* Conditional \#VMEXIT.
7177	*/
7178	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7179	{
7180	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7181	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7182	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7183
7184	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7185	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7186	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7187	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7188	uint32_t uErrCode = pVmcb->ctrl.u64ExitInfo1;
7189	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7190
7191	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7192	if (pVM->hmr0.s.fNestedPaging)
7193	{
7194	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7195	if ( !pSvmTransient->fVectoringDoublePF
7196	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7197	{
7198	/* A genuine guest #PF, reflect it to the guest. */
7199	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7200	Log4Func(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RX64 ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7201	uFaultAddress, uErrCode));
7202	}
7203	else
7204	{
7205	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7206	hmR0SvmSetPendingXcptDF(pVCpu);
7207	Log4Func(("Pending #DF due to vectoring #PF. NP\n"));
7208	}
7209	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7210	return VINF_SUCCESS;
7211	}
7212	#endif
7213
7214	Assert(!pVM->hmr0.s.fNestedPaging);
7215
7216	/*
7217	* TPR patching shortcut for APIC TPR reads and writes; only applicable to 32-bit guests.
7218	*/
7219	if ( pVM->hm.s.fTprPatchingAllowed
7220	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7221	&& !(uErrCode & X86_TRAP_PF_P) /* Not present. */
7222	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7223	&& !CPUMIsGuestInLongModeEx(pCtx)
7224	&& !CPUMGetGuestCPL(pVCpu)
7225	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7226	{
7227	RTGCPHYS GCPhysApicBase;
7228	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7229	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7230
7231	/* Check if the page at the fault-address is the APIC base. */
7232	RTGCPHYS GCPhysPage;
7233	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7234	if ( rc2 == VINF_SUCCESS
7235	&& GCPhysPage == GCPhysApicBase)
7236	{
7237	/* Only attempt to patch the instruction once. */
7238	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7239	if (!pPatch)
7240	return VINF_EM_HM_PATCH_TPR_INSTR;
7241	}
7242	}
7243
7244	Log4Func(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7245	pCtx->rip, uErrCode, pCtx->cr3));
7246
7247	/*
7248	* If it's a vectoring #PF, emulate injecting the original event injection as
7249	* PGMTrap0eHandler() is incapable of differentiating between instruction emulation and
7250	* event injection that caused a #PF. See @bugref{6607}.
7251	*/
7252	if (pSvmTransient->fVectoringPF)
7253	{
7254	Assert(pVCpu->hm.s.Event.fPending);
7255	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7256	}
7257
7258	TRPMAssertXcptPF(pVCpu, uFaultAddress, uErrCode);
7259	int rc = PGMTrap0eHandler(pVCpu, uErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7260
7261	Log4Func(("#PF: rc=%Rrc\n", rc));
7262
7263	if (rc == VINF_SUCCESS)
7264	{
7265	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7266	TRPMResetTrap(pVCpu);
7267	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7268	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7269	return rc;
7270	}
7271
7272	if (rc == VINF_EM_RAW_GUEST_TRAP)
7273	{
7274	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7275
7276	/*
7277	* If a nested-guest delivers a #PF and that causes a #PF which is -not- a shadow #PF,
7278	* we should simply forward the #PF to the guest and is up to the nested-hypervisor to
7279	* determine whether it is a nested-shadow #PF or a #DF, see @bugref{7243#c121}.
7280	*/
7281	if ( !pSvmTransient->fVectoringDoublePF
7282	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7283	{
7284	/* It's a guest (or nested-guest) page fault and needs to be reflected. */
7285	uErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7286	TRPMResetTrap(pVCpu);
7287
7288	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7289	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
7290	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7291	&& CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
7292	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_XCPT_PF, uErrCode, uFaultAddress);
7293	#endif
7294
7295	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7296	}
7297	else
7298	{
7299	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7300	TRPMResetTrap(pVCpu);
7301	hmR0SvmSetPendingXcptDF(pVCpu);
7302	Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
7303	}
7304
7305	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7306	return VINF_SUCCESS;
7307	}
7308
7309	TRPMResetTrap(pVCpu);
7310	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7311	return rc;
7312	}
7313
7314
7315	/**
7316	* \#VMEXIT handler for undefined opcode (SVM_EXIT_XCPT_6).
7317	* Conditional \#VMEXIT.
7318	*/
7319	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7320	{
7321	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7322	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7323	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7324
7325	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7326	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
7327	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7328
7329	/** @todo if we accumulate more optional stuff here, we ought to combine the
7330	* reading of opcode bytes to avoid doing more than once. */
7331
7332	VBOXSTRICTRC rcStrict = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7333	if (pVCpu->hm.s.fGIMTrapXcptUD)
7334	{
7335	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7336	uint8_t cbInstr = 0;
7337	rcStrict = GIMXcptUD(pVCpu, &pVCpu->cpum.GstCtx, NULL /* pDis */, &cbInstr);
7338	if (rcStrict == VINF_SUCCESS)
7339	{
7340	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7341	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7342	rcStrict = VINF_SUCCESS;
7343	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7344	}
7345	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7346	rcStrict = VINF_SUCCESS;
7347	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7348	rcStrict = VINF_GIM_R3_HYPERCALL;
7349	else
7350	{
7351	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7352	rcStrict = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7353	}
7354	}
7355
7356	if (pVCpu->hm.s.svm.fEmulateLongModeSysEnterExit)
7357	{
7358	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_SS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS
7359	\| CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
7360	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
7361	{
7362	/* Ideally, IEM should just handle all these special #UD situations, but
7363	we don't quite trust things to behave optimially when doing that. So,
7364	for now we'll restrict ourselves to a handful of possible sysenter and
7365	sysexit encodings that we filter right here. */
7366	uint8_t abInstr[SVM_CTRL_GUEST_INSTR_BYTES_MAX];
7367	uint8_t cbInstr = pVmcb->ctrl.cbInstrFetched;
7368	uint32_t const uCpl = CPUMGetGuestCPL(pVCpu);
7369	uint8_t const cbMin = uCpl != 0 ? 2 : 1 + 2;
7370	RTGCPTR const GCPtrInstr = pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base;
7371	if (cbInstr < cbMin \|\| cbInstr > SVM_CTRL_GUEST_INSTR_BYTES_MAX)
7372	{
7373	cbInstr = cbMin;
7374	int rc2 = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, GCPtrInstr, cbInstr);
7375	AssertRCStmt(rc2, cbInstr = 0);
7376	}
7377	else
7378	memcpy(abInstr, pVmcb->ctrl.abInstr, cbInstr); /* unlikely */
7379	if ( cbInstr == 0 /* read error */
7380	\|\| (cbInstr >= 2 && abInstr[0] == 0x0f && abInstr[1] == 0x34) /* sysenter */
7381	\|\| ( uCpl == 0
7382	&& ( ( cbInstr >= 2 && abInstr[0] == 0x0f && abInstr[1] == 0x35) /* sysexit */
7383	\|\| ( cbInstr >= 3 && abInstr[1] == 0x0f && abInstr[2] == 0x35 /* rex.w sysexit */
7384	&& (abInstr[0] & (X86_OP_REX_W \| 0xf0)) == X86_OP_REX_W))))
7385	{
7386	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK
7387	\| CPUMCTX_EXTRN_SREG_MASK /* without ES+DS+GS the app will #GP later - go figure */);
7388	Log6(("hmR0SvmExitXcptUD: sysenter/sysexit: %.*Rhxs at %#llx CPL=%u\n", cbInstr, abInstr, GCPtrInstr, uCpl));
7389	rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), GCPtrInstr, abInstr, cbInstr);
7390	Log6(("hmR0SvmExitXcptUD: sysenter/sysexit: rcStrict=%Rrc %04x:%08RX64 %08RX64 %04x:%08RX64\n",
7391	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u,
7392	pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.rsp));
7393	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7394	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK); /** @todo Lazy bird. */
7395	if (rcStrict == VINF_IEM_RAISED_XCPT)
7396	rcStrict = VINF_SUCCESS;
7397	return rcStrict;
7398	}
7399	Log6(("hmR0SvmExitXcptUD: not sysenter/sysexit: %.*Rhxs at %#llx CPL=%u\n", cbInstr, abInstr, GCPtrInstr, uCpl));
7400	}
7401	else
7402	Log6(("hmR0SvmExitXcptUD: not in long mode at %04x:%llx\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
7403	}
7404
7405	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7406	if (RT_FAILURE(rcStrict))
7407	{
7408	hmR0SvmSetPendingXcptUD(pVCpu);
7409	rcStrict = VINF_SUCCESS;
7410	}
7411
7412	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7413	return rcStrict;
7414	}
7415
7416
7417	/**
7418	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_XCPT_16).
7419	* Conditional \#VMEXIT.
7420	*/
7421	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7422	{
7423	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7424	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7425	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7426
7427	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7428	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7429
7430	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7431	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7432
7433	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7434
7435	if (!(pCtx->cr0 & X86_CR0_NE))
7436	{
7437	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7438	PDISSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
7439	unsigned cbInstr;
7440	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbInstr);
7441	if (RT_SUCCESS(rc))
7442	{
7443	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7444	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7445	if (RT_SUCCESS(rc))
7446	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7447	}
7448	else
7449	Log4Func(("EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7450	return rc;
7451	}
7452
7453	hmR0SvmSetPendingXcptMF(pVCpu);
7454	return VINF_SUCCESS;
7455	}
7456
7457
7458	/**
7459	* \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1). Conditional
7460	* \#VMEXIT.
7461	*/
7462	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7463	{
7464	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7465	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7466	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7467	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7468
7469	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7470	{
7471	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7472	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7473	}
7474
7475	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7476
7477	/*
7478	* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data
7479	* breakpoint). However, for both cases DR6 and DR7 are updated to what the exception
7480	* handler expects. See AMD spec. 15.12.2 "#DB (Debug)".
7481	*/
7482	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7483	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
7484	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7485	int rc = DBGFTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7486	if (rc == VINF_EM_RAW_GUEST_TRAP)
7487	{
7488	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7489	if (CPUMIsHyperDebugStateActive(pVCpu))
7490	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7491
7492	/* Reflect the exception back to the guest. */
7493	hmR0SvmSetPendingXcptDB(pVCpu);
7494	rc = VINF_SUCCESS;
7495	}
7496
7497	/*
7498	* Update DR6.
7499	*/
7500	if (CPUMIsHyperDebugStateActive(pVCpu))
7501	{
7502	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7503	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7504	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7505	}
7506	else
7507	{
7508	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7509	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7510	}
7511
7512	return rc;
7513	}
7514
7515
7516	/**
7517	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_XCPT_17).
7518	* Conditional \#VMEXIT.
7519	*/
7520	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7521	{
7522	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7523	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7524	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC);
7525
7526	SVMEVENT Event;
7527	Event.u = 0;
7528	Event.n.u1Valid = 1;
7529	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7530	Event.n.u8Vector = X86_XCPT_AC;
7531	Event.n.u1ErrorCodeValid = 1;
7532	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7533	return VINF_SUCCESS;
7534	}
7535
7536
7537	/**
7538	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7539	* Conditional \#VMEXIT.
7540	*/
7541	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7542	{
7543	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7544	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7545	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7546	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
7547
7548	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7549	int rc = DBGFTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7550	if (rc == VINF_EM_RAW_GUEST_TRAP)
7551	{
7552	SVMEVENT Event;
7553	Event.u = 0;
7554	Event.n.u1Valid = 1;
7555	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7556	Event.n.u8Vector = X86_XCPT_BP;
7557	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7558	rc = VINF_SUCCESS;
7559	}
7560
7561	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_DBG_BREAKPOINT);
7562	return rc;
7563	}
7564
7565
7566	/**
7567	* Hacks its way around the lovely mesa driver's backdoor accesses.
7568	*
7569	* @sa hmR0VmxHandleMesaDrvGp
7570	*/
7571	static int hmR0SvmHandleMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7572	{
7573	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK);
7574	Log(("hmR0SvmHandleMesaDrvGp: at %04x:%08RX64 rcx=%RX64 rbx=%RX64\n",
7575	pVmcb->guest.CS.u16Sel, pVmcb->guest.u64RIP, pCtx->rcx, pCtx->rbx));
7576	RT_NOREF(pCtx, pVmcb);
7577
7578	/* For now we'll just skip the instruction. */
7579	hmR0SvmAdvanceRip(pVCpu, 1);
7580	return VINF_SUCCESS;
7581	}
7582
7583
7584	/**
7585	* Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
7586	* backdoor logging w/o checking what it is running inside.
7587	*
7588	* This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
7589	* backdoor port and magic numbers loaded in registers.
7590	*
7591	* @returns true if it is, false if it isn't.
7592	* @sa hmR0VmxIsMesaDrvGp
7593	*/
7594	DECLINLINE(bool) hmR0SvmIsMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7595	{
7596	/* Check magic and port. */
7597	Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RCX)));
7598	/Log8(("hmR0SvmIsMesaDrvGp: rax=%RX64 rdx=%RX64\n", pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax, pCtx->rdx));/
7599	if (pCtx->dx != UINT32_C(0x5658))
7600	return false;
7601	if ((pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax) != UINT32_C(0x564d5868))
7602	return false;
7603
7604	/* Check that it is #GP(0). */
7605	if (pVmcb->ctrl.u64ExitInfo1 != 0)
7606	return false;
7607
7608	/* Flat ring-3 CS. */
7609	/Log8(("hmR0SvmIsMesaDrvGp: u8CPL=%d base=%RX64\n", pVmcb->guest.u8CPL, pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base));/
7610	if (pVmcb->guest.u8CPL != 3)
7611	return false;
7612	if ((pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base) != 0)
7613	return false;
7614
7615	/* 0xed: IN eAX,dx */
7616	if (pVmcb->ctrl.cbInstrFetched < 1) /* unlikely, it turns out. */
7617	{
7618	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_GPRS_MASK
7619	\| CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
7620	uint8_t abInstr[1];
7621	int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pCtx->rip, sizeof(abInstr));
7622	/Log8(("hmR0SvmIsMesaDrvGp: PGMPhysSimpleReadGCPtr -> %Rrc %#x\n", rc, abInstr[0])); /
7623	if (RT_FAILURE(rc))
7624	return false;
7625	if (abInstr[0] != 0xed)
7626	return false;
7627	}
7628	else
7629	{
7630	/Log8(("hmR0SvmIsMesaDrvGp: %#x\n", pVmcb->ctrl.abInstr));/
7631	if (pVmcb->ctrl.abInstr[0] != 0xed)
7632	return false;
7633	}
7634	return true;
7635	}
7636
7637
7638	/**
7639	* \#VMEXIT handler for general protection faults (SVM_EXIT_XCPT_BP).
7640	* Conditional \#VMEXIT.
7641	*/
7642	HMSVM_EXIT_DECL hmR0SvmExitXcptGP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7643	{
7644	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7645	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7646	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
7647
7648	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7649	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7650
7651	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7652	if ( !pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv
7653	\|\| !hmR0SvmIsMesaDrvGp(pVCpu, pCtx, pVmcb))
7654	{
7655	SVMEVENT Event;
7656	Event.u = 0;
7657	Event.n.u1Valid = 1;
7658	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7659	Event.n.u8Vector = X86_XCPT_GP;
7660	Event.n.u1ErrorCodeValid = 1;
7661	Event.n.u32ErrorCode = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
7662	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7663	return VINF_SUCCESS;
7664	}
7665	return hmR0SvmHandleMesaDrvGp(pVCpu, pCtx, pVmcb);
7666	}
7667
7668
7669	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
7670	/**
7671	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7672	*/
7673	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7674	{
7675	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7676	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7677
7678	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7679	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_XCPT_0;
7680	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7681	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7682	Assert(uVector <= X86_XCPT_LAST);
7683	Log4Func(("uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7684
7685	SVMEVENT Event;
7686	Event.u = 0;
7687	Event.n.u1Valid = 1;
7688	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7689	Event.n.u8Vector = uVector;
7690	switch (uVector)
7691	{
7692	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7693	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7694	case X86_XCPT_DF:
7695	case X86_XCPT_TS:
7696	case X86_XCPT_NP:
7697	case X86_XCPT_SS:
7698	case X86_XCPT_GP:
7699	case X86_XCPT_AC:
7700	{
7701	Event.n.u1ErrorCodeValid = 1;
7702	Event.n.u32ErrorCode = uErrCode;
7703	break;
7704	}
7705	}
7706
7707	#ifdef VBOX_WITH_STATISTICS
7708	switch (uVector)
7709	{
7710	case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE); break;
7711	case X86_XCPT_DB: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB); break;
7712	case X86_XCPT_BP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP); break;
7713	case X86_XCPT_OF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7714	case X86_XCPT_BR: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBR); break;
7715	case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD); break;
7716	case X86_XCPT_NM: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7717	case X86_XCPT_DF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDF); break;
7718	case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS); break;
7719	case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP); break;
7720	case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS); break;
7721	case X86_XCPT_GP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP); break;
7722	case X86_XCPT_PF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF); break;
7723	case X86_XCPT_MF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF); break;
7724	case X86_XCPT_AC: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC); break;
7725	case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF); break;
7726	default:
7727	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
7728	break;
7729	}
7730	#endif
7731
7732	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7733	return VINF_SUCCESS;
7734	}
7735	#endif
7736
7737	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7738	/**
7739	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7740	*/
7741	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7742	{
7743	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7744
7745	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7746	Assert(pVmcb);
7747	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7748
7749	VBOXSTRICTRC rcStrict;
7750	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7751	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7752	if (fSupportsNextRipSave)
7753	{
7754	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7755	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7756	rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7757	}
7758	else
7759	{
7760	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7761	rcStrict = IEMExecOne(pVCpu);
7762	}
7763
7764	if (rcStrict == VINF_SUCCESS)
7765	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7766	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7767	{
7768	rcStrict = VINF_SUCCESS;
7769	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7770	}
7771	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7772	return rcStrict;
7773	}
7774
7775
7776	/**
7777	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7778	*/
7779	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7780	{
7781	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7782
7783	/*
7784	* When VGIF is not used we always intercept STGI instructions. When VGIF is used,
7785	* we only intercept STGI when events are pending for GIF to become 1.
7786	*/
7787	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7788	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
7789	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_STGI);
7790
7791	VBOXSTRICTRC rcStrict;
7792	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7793	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7794	if (fSupportsNextRipSave)
7795	{
7796	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7797	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7798	rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7799	}
7800	else
7801	{
7802	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7803	rcStrict = IEMExecOne(pVCpu);
7804	}
7805
7806	if (rcStrict == VINF_SUCCESS)
7807	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7808	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7809	{
7810	rcStrict = VINF_SUCCESS;
7811	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7812	}
7813	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7814	return rcStrict;
7815	}
7816
7817
7818	/**
7819	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7820	*/
7821	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7822	{
7823	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7824
7825	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7826	Assert(pVmcb);
7827	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7828
7829	VBOXSTRICTRC rcStrict;
7830	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7831	uint64_t const fImport = CPUMCTX_EXTRN_FS \| CPUMCTX_EXTRN_GS \| CPUMCTX_EXTRN_KERNEL_GS_BASE
7832	\| CPUMCTX_EXTRN_TR \| CPUMCTX_EXTRN_LDTR \| CPUMCTX_EXTRN_SYSCALL_MSRS
7833	\| CPUMCTX_EXTRN_SYSENTER_MSRS;
7834	if (fSupportsNextRipSave)
7835	{
7836	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7837	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7838	rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7839	}
7840	else
7841	{
7842	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7843	rcStrict = IEMExecOne(pVCpu);
7844	}
7845
7846	if (rcStrict == VINF_SUCCESS)
7847	{
7848	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS \| HM_CHANGED_GUEST_GS
7849	\| HM_CHANGED_GUEST_TR \| HM_CHANGED_GUEST_LDTR
7850	\| HM_CHANGED_GUEST_KERNEL_GS_BASE \| HM_CHANGED_GUEST_SYSCALL_MSRS
7851	\| HM_CHANGED_GUEST_SYSENTER_MSR_MASK);
7852	}
7853	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7854	{
7855	rcStrict = VINF_SUCCESS;
7856	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7857	}
7858	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7859	return rcStrict;
7860	}
7861
7862
7863	/**
7864	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7865	*/
7866	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7867	{
7868	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7869
7870	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7871	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7872
7873	VBOXSTRICTRC rcStrict;
7874	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7875	if (fSupportsNextRipSave)
7876	{
7877	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7878	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7879	rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7880	}
7881	else
7882	{
7883	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7884	rcStrict = IEMExecOne(pVCpu);
7885	}
7886
7887	if (rcStrict == VINF_IEM_RAISED_XCPT)
7888	{
7889	rcStrict = VINF_SUCCESS;
7890	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7891	}
7892	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7893	return rcStrict;
7894	}
7895
7896
7897	/**
7898	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7899	*/
7900	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7901	{
7902	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7903
7904	VBOXSTRICTRC rcStrict;
7905	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7906	if (fSupportsNextRipSave)
7907	{
7908	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7909	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7910	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7911	rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7912	}
7913	else
7914	{
7915	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7916	rcStrict = IEMExecOne(pVCpu);
7917	}
7918
7919	if (rcStrict == VINF_IEM_RAISED_XCPT)
7920	{
7921	rcStrict = VINF_SUCCESS;
7922	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7923	}
7924	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7925	return rcStrict;
7926	}
7927
7928
7929	/**
7930	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7931	*/
7932	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7933	{
7934	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7935	/* We shall import the entire state here, just in case we enter and continue execution of
7936	the nested-guest with hardware-assisted SVM in ring-0, we would be switching VMCBs and
7937	could lose lose part of CPU state. */
7938	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7939
7940	VBOXSTRICTRC rcStrict;
7941	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7942	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitVmentry, z);
7943	if (fSupportsNextRipSave)
7944	{
7945	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7946	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7947	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7948	}
7949	else
7950	{
7951	/* We use IEMExecOneBypassEx() here as it supresses attempt to continue emulating any
7952	instruction(s) when interrupt inhibition is set as part of emulating the VMRUN
7953	instruction itself, see @bugref{7243#c126} */
7954	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), NULL /* pcbWritten */);
7955	}
7956	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitVmentry, z);
7957
7958	if (rcStrict == VINF_SUCCESS)
7959	{
7960	rcStrict = VINF_SVM_VMRUN;
7961	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_SVM_VMRUN_MASK);
7962	}
7963	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7964	{
7965	rcStrict = VINF_SUCCESS;
7966	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7967	}
7968	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7969	return rcStrict;
7970	}
7971
7972
7973	/**
7974	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1).
7975	* Unconditional \#VMEXIT.
7976	*/
7977	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7978	{
7979	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7980	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7981
7982	if (pVCpu->hm.s.Event.fPending)
7983	{
7984	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7985	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7986	}
7987
7988	hmR0SvmSetPendingXcptDB(pVCpu);
7989	return VINF_SUCCESS;
7990	}
7991
7992
7993	/**
7994	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7995	* Conditional \#VMEXIT.
7996	*/
7997	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7998	{
7999	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8000	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
8001
8002	SVMEVENT Event;
8003	Event.u = 0;
8004	Event.n.u1Valid = 1;
8005	Event.n.u3Type = SVM_EVENT_EXCEPTION;
8006	Event.n.u8Vector = X86_XCPT_BP;
8007	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
8008	return VINF_SUCCESS;
8009	}
8010	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
8011
8012	/** @} */
8013

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 91286

Download in other formats: