VirtualBox

Changeset 91271 in vbox


Ignore:
Timestamp:
Sep 16, 2021 7:42:37 AM (4 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
146930
Message:

VMM: bugref:10092 Moved the PAE PDPTEs out of PGM into CPUMCTX.

Location:
trunk
Files:
20 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/cpum.h

    r91266 r91271  
    15391539VMM_INT_DECL(uint64_t) CPUMGetGuestSpecCtrl(PVMCPUCC pVCpu);
    15401540VMM_INT_DECL(uint64_t) CPUMGetGuestCR4ValidMask(PVM pVM);
     1541VMM_INT_DECL(void)     CPUMSetGuestPaePdpes(PVMCPU pVCpu, PCX86PDPE paPaePdpes);
    15411542/** @} */
    15421543

  • trunk/include/VBox/vmm/cpum.mac

    r87522 r91271  
    257257    alignb 8
    258258    .fExtrn             resq    1
     259    .aPaePdpes          resq    4
    259260    alignb 8
    260261    .hwvirt.svm.uMsrHSavePa            resq          1

  • trunk/include/VBox/vmm/cpumctx.h

    r87522 r91271  
    479479    uint64_t                    fExtrn;
    480480
    481     /** 0x2e0 - Hardware virtualization state.   */
     481    /** 0x2e0 - PAE PDPTEs. */
     482    X86PDPE                     aPaePdpes[4];
     483
     484    /** 0x300 - Hardware virtualization state.   */
    482485    struct
    483486    {
    … …  
    486489            struct
    487490            {
    488                 /** 0x2e0 - MSR holding physical address of the Guest's Host-state. */
     491                /** 0x300 - MSR holding physical address of the Guest's Host-state. */
    489492                uint64_t                uMsrHSavePa;
    490                 /** 0x2e8 - Guest physical address of the nested-guest VMCB. */
     493                /** 0x308 - Guest physical address of the nested-guest VMCB. */
    491494                RTGCPHYS                GCPhysVmcb;
    492                 /** 0x2f0 - Cache of the nested-guest VMCB - R0 ptr. */
     495                /** 0x310 - Cache of the nested-guest VMCB - R0 ptr. */
    493496                R0PTRTYPE(PSVMVMCB)     pVmcbR0;
    494                 /** 0x2f8 - Cache of the nested-guest VMCB - R3 ptr. */
     497                /** 0x318 - Cache of the nested-guest VMCB - R3 ptr. */
    495498                R3PTRTYPE(PSVMVMCB)     pVmcbR3;
    496                 /** 0x300 - Guest's host-state save area. */
     499                /** 0x320 - Guest's host-state save area. */
    497500                SVMHOSTSTATE            HostState;
    498                 /** 0x3b8 - Guest TSC time-stamp of when the previous PAUSE instr. was executed. */
     501                /** 0x3d8 - Guest TSC time-stamp of when the previous PAUSE instr. was executed. */
    499502                uint64_t                uPrevPauseTick;
    500                 /** 0x3c0 - Pause filter count. */
     503                /** 0x3e0 - Pause filter count. */
    501504                uint16_t                cPauseFilter;
    502                 /** 0x3c2 - Pause filter threshold. */
     505                /** 0x3e2 - Pause filter threshold. */
    503506                uint16_t                cPauseFilterThreshold;
    504                 /** 0x3c4 - Whether the injected event is subject to event intercepts. */
     507                /** 0x3e4 - Whether the injected event is subject to event intercepts. */
    505508                bool                    fInterceptEvents;
    506                 /** 0x3c5 - Padding. */
     509                /** 0x3e5 - Padding. */
    507510                bool                    afPadding[3];
    508                 /** 0x3c8 - MSR permission bitmap - R0 ptr. */
     511                /** 0x3e8 - MSR permission bitmap - R0 ptr. */
    509512                R0PTRTYPE(void *)       pvMsrBitmapR0;
    510                 /** 0x3d0 - MSR permission bitmap - R3 ptr. */
     513                /** 0x3f0 - MSR permission bitmap - R3 ptr. */
    511514                R3PTRTYPE(void *)       pvMsrBitmapR3;
    512                 /** 0x3d8 - IO permission bitmap - R0 ptr. */
     515                /** 0x3f8 - IO permission bitmap - R0 ptr. */
    513516                R0PTRTYPE(void *)       pvIoBitmapR0;
    514                 /** 0x3e0 - IO permission bitmap - R3 ptr. */
     517                /** 0x400 - IO permission bitmap - R3 ptr. */
    515518                R3PTRTYPE(void *)       pvIoBitmapR3;
    516                 /** 0x3e8 - Host physical address of the nested-guest VMCB.  */
     519                /** 0x408 - Host physical address of the nested-guest VMCB.  */
    517520                RTHCPHYS                HCPhysVmcb;
    518                 /** 0x3f0 - Padding. */
     521                /** 0x410 - Padding. */
    519522                uint8_t                 abPadding0[272];
    520523            } svm;
    … …  
    522525            struct
    523526            {
    524                 /** 0x2e4 - Guest physical address of the VMXON region. */
     527                /** 0x300 - Guest physical address of the VMXON region. */
    525528                RTGCPHYS                GCPhysVmxon;
    526                 /** 0x2e8 - Guest physical address of the current VMCS pointer. */
     529                /** 0x308 - Guest physical address of the current VMCS pointer. */
    527530                RTGCPHYS                GCPhysVmcs;
    528                 /** 0x2f0 - Guest physical address of the shadow VMCS pointer. */
     531                /** 0x310 - Guest physical address of the shadow VMCS pointer. */
    529532                RTGCPHYS                GCPhysShadowVmcs;
    530                 /** 0x2f8 - Last emulated VMX instruction/VM-exit diagnostic. */
     533                /** 0x318 - Last emulated VMX instruction/VM-exit diagnostic. */
    531534                VMXVDIAG                enmDiag;
    532                 /** 0x2fc - VMX abort reason. */
     535                /** 0x31c - VMX abort reason. */
    533536                VMXABORT                enmAbort;
    534                 /** 0x300 - Last emulated VMX instruction/VM-exit diagnostic auxiliary info. (mainly
     537                /** 0x320 - Last emulated VMX instruction/VM-exit diagnostic auxiliary info. (mainly
    535538                 *  used for info. that's not part of the VMCS). */
    536539                uint64_t                uDiagAux;
    537                 /** 0x308 - VMX abort auxiliary info. */
     540                /** 0x328 - VMX abort auxiliary info. */
    538541                uint32_t                uAbortAux;
    539                 /** 0x30c - Whether the guest is in VMX root mode. */
     542                /** 0x32c - Whether the guest is in VMX root mode. */
    540543                bool                    fInVmxRootMode;
    541                 /** 0x30d - Whether the guest is in VMX non-root mode. */
     544                /** 0x32d - Whether the guest is in VMX non-root mode. */
    542545                bool                    fInVmxNonRootMode;
    543                 /** 0x30e - Whether the injected events are subjected to event intercepts.  */
     546                /** 0x32e - Whether the injected events are subjected to event intercepts.  */
    544547                bool                    fInterceptEvents;
    545                 /** 0x30f - Whether blocking of NMI (or virtual-NMIs) was in effect in VMX non-root
     548                /** 0x32f - Whether blocking of NMI (or virtual-NMIs) was in effect in VMX non-root
    546549                 *  mode before execution of IRET. */
    547550                bool                    fNmiUnblockingIret;
    548                 /** 0x310 - The current VMCS - R0 ptr. */
     551                /** 0x330 - The current VMCS - R0 ptr. */
    549552                R0PTRTYPE(PVMXVVMCS)    pVmcsR0;
    550                 /** 0x318 - The curent VMCS - R3 ptr. */
     553                /** 0x338 - The curent VMCS - R3 ptr. */
    551554                R3PTRTYPE(PVMXVVMCS)    pVmcsR3;
    552                 /** 0X320 - The shadow VMCS - R0 ptr. */
     555                /** 0X340 - The shadow VMCS - R0 ptr. */
    553556                R0PTRTYPE(PVMXVVMCS)    pShadowVmcsR0;
    554                 /** 0x328 - The shadow VMCS - R3 ptr. */
     557                /** 0x348 - The shadow VMCS - R3 ptr. */
    555558                R3PTRTYPE(PVMXVVMCS)    pShadowVmcsR3;
    556                 /** 0x330 - The virtual-APIC page - R0 ptr. */
     559                /** 0x350 - The virtual-APIC page - R0 ptr. */
    557560                R0PTRTYPE(void *)       pvVirtApicPageR0;
    558                 /** 0x338 - The virtual-APIC page - R3 ptr. */
     561                /** 0x358 - The virtual-APIC page - R3 ptr. */
    559562                R3PTRTYPE(void *)       pvVirtApicPageR3;
    560                 /** 0x340 - The VMREAD bitmap - R0 ptr. */
     563                /** 0x360 - The VMREAD bitmap - R0 ptr. */
    561564                R0PTRTYPE(void *)       pvVmreadBitmapR0;
    562                 /** 0x348 - The VMREAD bitmap - R3 ptr. */
     565                /** 0x368 - The VMREAD bitmap - R3 ptr. */
    563566                R3PTRTYPE(void *)       pvVmreadBitmapR3;
    564                 /** 0x350 - The VMWRITE bitmap - R0 ptr. */
     567                /** 0x370 - The VMWRITE bitmap - R0 ptr. */
    565568                R0PTRTYPE(void *)       pvVmwriteBitmapR0;
    566                 /** 0x358 - The VMWRITE bitmap - R3 ptr. */
     569                /** 0x378 - The VMWRITE bitmap - R3 ptr. */
    567570                R3PTRTYPE(void *)       pvVmwriteBitmapR3;
    568                 /** 0x360 - The VM-entry MSR-load area - R0 ptr. */
     571                /** 0x380 - The VM-entry MSR-load area - R0 ptr. */
    569572                R0PTRTYPE(PVMXAUTOMSR)  pEntryMsrLoadAreaR0;
    570                 /** 0x368 - The VM-entry MSR-load area - R3 ptr. */
     573                /** 0x388 - The VM-entry MSR-load area - R3 ptr. */
    571574                R3PTRTYPE(PVMXAUTOMSR)  pEntryMsrLoadAreaR3;
    572                 /** 0x370 - The VM-exit MSR-store area - R0 ptr. */
     575                /** 0x390 - The VM-exit MSR-store area - R0 ptr. */
    573576                R0PTRTYPE(PVMXAUTOMSR)  pExitMsrStoreAreaR0;
    574                 /** 0x378 - The VM-exit MSR-store area - R3 ptr. */
     577                /** 0x398 - The VM-exit MSR-store area - R3 ptr. */
    575578                R3PTRTYPE(PVMXAUTOMSR)  pExitMsrStoreAreaR3;
    576                 /** 0x380 - The VM-exit MSR-load area - R0 ptr. */
     579                /** 0x3a0 - The VM-exit MSR-load area - R0 ptr. */
    577580                R0PTRTYPE(PVMXAUTOMSR)  pExitMsrLoadAreaR0;
    578                 /** 0x388 - The VM-exit MSR-load area - R3 ptr. */
     581                /** 0x3a8 - The VM-exit MSR-load area - R3 ptr. */
    579582                R3PTRTYPE(PVMXAUTOMSR)  pExitMsrLoadAreaR3;
    580                 /** 0x390 - MSR bitmap - R0 ptr. */
     583                /** 0x3b0 - MSR bitmap - R0 ptr. */
    581584                R0PTRTYPE(void *)       pvMsrBitmapR0;
    582                 /** 0x398 - The MSR bitmap - R3 ptr. */
     585                /** 0x3b8 - The MSR bitmap - R3 ptr. */
    583586                R3PTRTYPE(void *)       pvMsrBitmapR3;
    584                 /** 0x3a0 - The I/O bitmap - R0 ptr. */
     587                /** 0x3c0 - The I/O bitmap - R0 ptr. */
    585588                R0PTRTYPE(void *)       pvIoBitmapR0;
    586                 /** 0x3a8 - The I/O bitmap - R3 ptr. */
     589                /** 0x3c8 - The I/O bitmap - R3 ptr. */
    587590                R3PTRTYPE(void *)       pvIoBitmapR3;
    588                 /** 0x3b0 - Guest TSC timestamp of the first PAUSE instruction that is considered to
     591                /** 0x3d0 - Guest TSC timestamp of the first PAUSE instruction that is considered to
    589592                 *  be the first in a loop. */
    590593                uint64_t                uFirstPauseLoopTick;
    591                 /** 0x3b8 - Guest TSC timestamp of the previous PAUSE instruction. */
     594                /** 0x3d8 - Guest TSC timestamp of the previous PAUSE instruction. */
    592595                uint64_t                uPrevPauseTick;
    593                 /** 0x3c0 - Guest TSC timestamp of VM-entry (used for VMX-preemption timer). */
     596                /** 0x3e0 - Guest TSC timestamp of VM-entry (used for VMX-preemption timer). */
    594597                uint64_t                uEntryTick;
    595                 /** 0x3c8 - Virtual-APIC write offset (until trap-like VM-exit). */
     598                /** 0x3e8 - Virtual-APIC write offset (until trap-like VM-exit). */
    596599                uint16_t                offVirtApicWrite;
    597                 /** 0x3ca - Whether virtual-NMI blocking is in effect. */
     600                /** 0x3ea - Whether virtual-NMI blocking is in effect. */
    598601                bool                    fVirtNmiBlocking;
    599                 /** 0x3cc - Padding. */
     602                /** 0x3eb - Padding. */
    600603                uint8_t                 abPadding0[5];
    601                 /** 0x3d0 - Guest VMX MSRs. */
     604                /** 0x3f0 - Guest VMX MSRs. */
    602605                VMXMSRS                 Msrs;
    603                 /** 0x4b0 - Host physical address of the VMCS. */
     606                /** 0x4d0 - Host physical address of the VMCS. */
    604607                RTHCPHYS                HCPhysVmcs;
    605                 /** 0x4b8 - Host physical address of the shadow VMCS. */
     608                /** 0x4d8 - Host physical address of the shadow VMCS. */
    606609                RTHCPHYS                HCPhysShadowVmcs;
    607                 /** 0x4c0 - Host physical address of the virtual-APIC page. */
     610                /** 0x4e0 - Host physical address of the virtual-APIC page. */
    608611                RTHCPHYS                HCPhysVirtApicPage;
    609                 /** 0x4c8 - Host physical address of the VMREAD bitmap. */
     612                /** 0x4e8 - Host physical address of the VMREAD bitmap. */
    610613                RTHCPHYS                HCPhysVmreadBitmap;
    611                 /** 0x4d0 - Host physical address of the VMWRITE bitmap. */
     614                /** 0x4f0 - Host physical address of the VMWRITE bitmap. */
    612615                RTHCPHYS                HCPhysVmwriteBitmap;
    613                 /** 0x4d8 - Host physical address of the VM-entry MSR-load area. */
     616                /** 0x4f8 - Host physical address of the VM-entry MSR-load area. */
    614617                RTHCPHYS                HCPhysEntryMsrLoadArea;
    615                 /** 0x4e0 - Host physical address of the VM-exit MSR-store area. */
     618                /** 0x500 - Host physical address of the VM-exit MSR-store area. */
    616619                RTHCPHYS                HCPhysExitMsrStoreArea;
    617                 /** 0x4e8 - Host physical address of the VM-exit MSR-load area. */
     620                /** 0x508 - Host physical address of the VM-exit MSR-load area. */
    618621                RTHCPHYS                HCPhysExitMsrLoadArea;
    619                 /** 0x4f0 - Host physical address of the MSR bitmap. */
     622                /** 0x510 - Host physical address of the MSR bitmap. */
    620623                RTHCPHYS                HCPhysMsrBitmap;
    621                 /** 0x4f8 - Host physical address of the I/O bitmap. */
     624                /** 0x518 - Host physical address of the I/O bitmap. */
    622625                RTHCPHYS                HCPhysIoBitmap;
    623626            } vmx;
    624627        } CPUM_UNION_NM(s);
    625628
    626         /** 0x500 - Hardware virtualization type currently in use. */
     629        /** 0x520 - Hardware virtualization type currently in use. */
    627630        CPUMHWVIRT              enmHwvirt;
    628         /** 0x504 - Global interrupt flag - AMD only (always true on Intel). */
     631        /** 0x524 - Global interrupt flag - AMD only (always true on Intel). */
    629632        bool                    fGif;
    630633        bool                    afPadding1[3];
    631         /** 0x508 - A subset of guest force flags that are saved while running the
     634        /** 0x528 - A subset of guest force flags that are saved while running the
    632635         *  nested-guest. */
    633636#ifdef VMCPU_WITH_64_BIT_FFS
    … …  
    637640        uint32_t                fPadding;
    638641#endif
    639         /** 0x510 - Pad to 64 byte boundary. */
    640         uint8_t                 abPadding0[48];
     642        /** 0x530 - Pad to 64 byte boundary. */
     643        uint8_t                 abPadding0[16];
    641644    } hwvirt;
    642645} CPUMCTX;
    … …  
    691694AssertCompileMemberOffset(CPUMCTX,                  pXStateR3, 584);
    692695AssertCompileMemberOffset(CPUMCTX,                 aoffXState, 592);
    693 AssertCompileMemberOffset(CPUMCTX, hwvirt, 0x2e0);
    694 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.uMsrHSavePa,                 0x2e0);
    695 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pVmcbR0,                     0x2f0);
    696 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pVmcbR3,                     0x2f8);
    697 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.HostState,                   0x300);
    698 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.cPauseFilter,                0x3c0);
    699 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR0,               0x3c8);
    700 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR3,                0x3e0);
    701 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.HCPhysVmcb,                  0x3e8);
    702 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pVmcbR0,       8);
    703 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR0, 8);
    704 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR0,  8);
    705 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.GCPhysVmxon,                 0x2e0);
    706 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.GCPhysVmcs,                  0x2e8);
    707 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.GCPhysShadowVmcs,            0x2f0);
    708 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.enmDiag,                     0x2f8);
    709 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.enmAbort,                    0x2fc);
    710 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.uDiagAux,                    0x300);
    711 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.uAbortAux,                   0x308);
    712 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fInVmxRootMode,              0x30c);
    713 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fInVmxNonRootMode,           0x30d);
    714 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fInterceptEvents,            0x30e);
    715 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fNmiUnblockingIret,          0x30f);
    716 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pVmcsR0,                     0x310);
    717 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pVmcsR3,                     0x318);
    718 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pShadowVmcsR0,               0x320);
    719 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pShadowVmcsR3,               0x328);
    720 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVirtApicPageR0,            0x330);
    721 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVirtApicPageR3,            0x338);
    722 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVmreadBitmapR0,            0x340);
    723 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVmreadBitmapR3,            0x348);
    724 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVmwriteBitmapR0,           0x350);
    725 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVmwriteBitmapR3,           0x358);
    726 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pEntryMsrLoadAreaR0,         0x360);
    727 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pEntryMsrLoadAreaR3,         0x368);
    728 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pExitMsrStoreAreaR0,         0x370);
    729 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pExitMsrStoreAreaR3,         0x378);
    730 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pExitMsrLoadAreaR0,          0x380);
    731 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pExitMsrLoadAreaR3,          0x388);
    732 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvMsrBitmapR0,               0x390);
    733 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvMsrBitmapR3,               0x398);
    734 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvIoBitmapR0,                0x3a0);
    735 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvIoBitmapR3,                0x3a8);
    736 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.uFirstPauseLoopTick,         0x3b0);
    737 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.uPrevPauseTick,              0x3b8);
    738 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.uEntryTick,                  0x3c0);
    739 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.offVirtApicWrite,            0x3c8);
    740 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fVirtNmiBlocking,            0x3ca);
    741 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Msrs,                        0x3d0);
    742 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysVmcs,                  0x4b0);
    743 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysShadowVmcs,            0x4b8);
    744 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysVirtApicPage,          0x4c0);
    745 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysVmreadBitmap,          0x4c8);
    746 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysVmwriteBitmap,         0x4d0);
    747 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysEntryMsrLoadArea,      0x4d8);
    748 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysExitMsrStoreArea,      0x4e0);
    749 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysExitMsrLoadArea,       0x4e8);
    750 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysMsrBitmap,             0x4f0);
    751 AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysIoBitmap,              0x4f8);
    752 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pVmcsR0,               8);
    753 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pShadowVmcsR0,         8);
    754 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVmreadBitmapR0,      8);
    755 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVmwriteBitmapR0,     8);
    756 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pEntryMsrLoadAreaR0,   8);
    757 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pExitMsrStoreAreaR0,   8);
    758 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pExitMsrLoadAreaR0,    8);
    759 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvMsrBitmapR0,         8);
    760 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvIoBitmapR0,          8);
    761 AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Msrs,                  8);
    762 AssertCompileMemberOffset(CPUMCTX, hwvirt.enmHwvirt,           0x500);
    763 AssertCompileMemberOffset(CPUMCTX, hwvirt.fGif,                0x504);
    764 AssertCompileMemberOffset(CPUMCTX, hwvirt.fLocalForcedActions, 0x508);
     696AssertCompileMemberOffset(CPUMCTX, aPaePdpes, 0x2e0);
     697AssertCompileMemberOffset(CPUMCTX, hwvirt,    0x300);
     698AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.uMsrHSavePa,                 0x300);
     699AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.GCPhysVmcb,                  0x308);
     700AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pVmcbR0,                     0x310);
     701AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pVmcbR3,                     0x318);
     702AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.HostState,                   0x320);
     703AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.uPrevPauseTick,              0x3d8);
     704AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.cPauseFilter,                0x3e0);
     705AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR0,               0x3e8);
     706AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR3,               0x3f0);
     707AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR0,                0x3f8);
     708AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR3,                0x400);
     709AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.HCPhysVmcb,                  0x408);
     710AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.GCPhysVmxon,                 0x300);
     711AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.GCPhysVmcs,                  0x308);
     712AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.GCPhysShadowVmcs,            0x310);
     713AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.enmDiag,                     0x318);
     714AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.enmAbort,                    0x31c);
     715AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.uDiagAux,                    0x320);
     716AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.uAbortAux,                   0x328);
     717AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fInVmxRootMode,              0x32c);
     718AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fInVmxNonRootMode,           0x32d);
     719AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fInterceptEvents,            0x32e);
     720AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fNmiUnblockingIret,          0x32f);
     721AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pVmcsR0,                     0x330);
     722AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pVmcsR3,                     0x338);
     723AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pShadowVmcsR0,               0x340);
     724AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pShadowVmcsR3,               0x348);
     725AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVirtApicPageR0,            0x350);
     726AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVirtApicPageR3,            0x358);
     727AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVmreadBitmapR0,            0x360);
     728AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVmreadBitmapR3,            0x368);
     729AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVmwriteBitmapR0,           0x370);
     730AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVmwriteBitmapR3,           0x378);
     731AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pEntryMsrLoadAreaR0,         0x380);
     732AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pEntryMsrLoadAreaR3,         0x388);
     733AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pExitMsrStoreAreaR0,         0x390);
     734AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pExitMsrStoreAreaR3,         0x398);
     735AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pExitMsrLoadAreaR0,          0x3a0);
     736AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pExitMsrLoadAreaR3,          0x3a8);
     737AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvMsrBitmapR0,               0x3b0);
     738AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvMsrBitmapR3,               0x3b8);
     739AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvIoBitmapR0,                0x3c0);
     740AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvIoBitmapR3,                0x3c8);
     741AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.uFirstPauseLoopTick,         0x3d0);
     742AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.uPrevPauseTick,              0x3d8);
     743AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.uEntryTick,                  0x3e0);
     744AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.offVirtApicWrite,            0x3e8);
     745AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.fVirtNmiBlocking,            0x3ea);
     746AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Msrs,                        0x3f0);
     747AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysVmcs,                  0x4d0);
     748AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysShadowVmcs,            0x4d8);
     749AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysVirtApicPage,          0x4e0);
     750AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysVmreadBitmap,          0x4e8);
     751AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysVmwriteBitmap,         0x4f0);
     752AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysEntryMsrLoadArea,      0x4f8);
     753AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysExitMsrStoreArea,      0x500);
     754AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysExitMsrLoadArea,       0x508);
     755AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysMsrBitmap,             0x510);
     756AssertCompileMemberOffset(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.HCPhysIoBitmap,              0x518);
     757AssertCompileMemberOffset(CPUMCTX, hwvirt.enmHwvirt,           0x520);
     758AssertCompileMemberOffset(CPUMCTX, hwvirt.fGif,                0x524);
     759AssertCompileMemberOffset(CPUMCTX, hwvirt.fLocalForcedActions, 0x528);
    765760AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_NM(g.) aGRegs);
    766761AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw.) rax, CPUMCTX, CPUM_UNION_STRUCT_NM(g,qw2.)  r0);
    … …  
    845840AssertCompileMembersAtSameOffset(CPUMCTX, CPUM_UNION_STRUCT_NM(s,n.) gs,   CPUMCTX, CPUM_UNION_NM(s.) aSRegs[X86_SREG_GS]);
    846841# endif
     842AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pVmcbR0,               8);
     843AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvMsrBitmapR0,         8);
     844AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) svm.pvIoBitmapR0,          8);
     845AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pVmcsR0,               8);
     846AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pShadowVmcsR0,         8);
     847AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVmreadBitmapR0,      8);
     848AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvVmwriteBitmapR0,     8);
     849AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pEntryMsrLoadAreaR0,   8);
     850AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pExitMsrStoreAreaR0,   8);
     851AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pExitMsrLoadAreaR0,    8);
     852AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvMsrBitmapR0,         8);
     853AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.pvIoBitmapR0,          8);
     854AssertCompileMemberAlignment(CPUMCTX, hwvirt.CPUM_UNION_NM(s.) vmx.Msrs,                  8);
    847855
    848856/**

  • trunk/include/VBox/vmm/hm.h

    r87519 r91271  
    113113VMM_INT_DECL(int)               HMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt);
    114114VMM_INT_DECL(bool)              HMHasPendingIrq(PVMCC pVM);
    115 VMM_INT_DECL(PX86PDPE)          HMGetPaePdpes(PVMCPU pVCpu);
    116115VMM_INT_DECL(bool)              HMSetSingleInstruction(PVMCC pVM, PVMCPUCC pVCpu, bool fEnable);
    117116VMM_INT_DECL(bool)              HMIsSvmActive(PVM pVM);

  • trunk/include/VBox/vmm/pgm.h

    r91246 r91271  
    297297                                     || (enmMode) == PGMMODE_NESTED_PAE \
    298298                                     || (enmMode) == PGMMODE_NESTED_AMD64)
     299
     300/** Macro for checking if it's one of the PAE modes.
     301 * @param enmMode   PGMMODE_*.
     302 */
     303#define PGMMODE_IS_PAE(enmMode)     (   (enmMode) == PGMMODE_PAE \
     304                                     || (enmMode) == PGMMODE_PAE_NX)
    299305
    300306/**
    … …  
    348354VMMDECL(int)        PGMGstSetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
    349355VMMDECL(int)        PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
    350 VMM_INT_DECL(int)   PGMGstGetPaePdpes(PVMCPUCC pVCpu, PX86PDPE paPdpes);
    351 VMM_INT_DECL(void)  PGMGstUpdatePaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPdpes);
    352356
    353357VMMDECL(int)        PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);

  • trunk/include/VBox/vmm/vm.h

    r91266 r91271  
    485485#define VMCPU_FF_HM_UPDATE_CR3              RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
    486486#define VMCPU_FF_HM_UPDATE_CR3_BIT          12
    487 /** This action forces the VM to service any pending updates to PAE PDPEs (used
    488  *  only by HM)
    489  * @todo r=bird: This description is very unhelpful.  From the looks of things,
    490  *       when this flag is set the actual PDPE values live in HMCPU::aPdpes
    491  *       and PGM should fetch them from there before use. */
    492 #define VMCPU_FF_HM_UPDATE_PAE_PDPES        RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
    493 #define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT    13
     487/* Bit 13 used to be VMCPU_FF_HM_UPDATE_PAE_PDPES. */
    494488/** This action forces the VM to resync the page tables before going
    495489 * back to execute guest code. (GLOBAL FLUSH) */
    … …  
    582576#define VM_FF_HIGH_PRIORITY_POST_MASK           (  VM_FF_PGM_NO_MEMORY )
    583577/** High priority post-execution actions. */
    584 #define VMCPU_FF_HIGH_PRIORITY_POST_MASK        (  VMCPU_FF_PDM_CRITSECT \
    585                                                  | VMCPU_FF_HM_UPDATE_CR3  | VMCPU_FF_HM_UPDATE_PAE_PDPES \
    586                                                  | VMCPU_FF_IEM | VMCPU_FF_IOM )
     578#define VMCPU_FF_HIGH_PRIORITY_POST_MASK        (  VMCPU_FF_PDM_CRITSECT | VMCPU_FF_HM_UPDATE_CR3 | VMCPU_FF_IEM | VMCPU_FF_IOM )
    587579
    588580/** Normal priority VM post-execution actions. */

  • trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

    r91266 r91271  
    23312331        fMask |= X86_CR4_FSGSBASE;
    23322332    return fMask;
     2333}
     2334
     2335
     2336/**
     2337 * Sets the PAE PDPTEs for the guest.
     2338 *
     2339 * @param   pVCpu       The cross context virtual CPU structure of the calling thread.
     2340 * @param   pPaePdes    The PAE PDPTEs to set.
     2341 */
     2342VMM_INT_DECL(void) CPUMSetGuestPaePdpes(PVMCPU pVCpu, PCX86PDPE paPaePdpes)
     2343{
     2344    Assert(paPaePdpes);
     2345    for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->cpum.s.Guest.aPaePdpes); i++)
     2346        pVCpu->cpum.s.Guest.aPaePdpes[i].u = paPaePdpes[i].u;
     2347    pVCpu->cpum.s.Guest.fExtrn &= ~CPUMCTX_EXTRN_CR3;
    23332348}
    23342349

  • trunk/src/VBox/VMM/VMMAll/HMAll.cpp

    r91037 r91271  
    733733
    734734/**
    735  * Return the PAE PDPE entries.
    736  *
    737  * @returns Pointer to the PAE PDPE array.
    738  * @param   pVCpu       The cross context virtual CPU structure.
    739  */
    740 VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu)
    741 {
    742     return &pVCpu->hm.s.aPdpes[0];
    743 }
    744 
    745 
    746 /**
    747735 * Sets or clears the single instruction flag.
    748736 *

  • trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

    r91250 r91271  
    23632363
    23642364/**
    2365  * Gets the PAE PDPEs values cached by the CPU.
    2366  *
    2367  * @returns VBox status code.
    2368  * @param   pVCpu               The cross context virtual CPU structure.
    2369  * @param   paPdpes             Where to return the four PDPEs. The array
    2370  *                              pointed to must have 4 entries.
    2371  */
    2372 VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPUCC pVCpu, PX86PDPE paPdpes)
    2373 {
    2374     Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
    2375 
    2376     paPdpes[0] = pVCpu->pgm.s.aGstPaePdpeRegs[0];
    2377     paPdpes[1] = pVCpu->pgm.s.aGstPaePdpeRegs[1];
    2378     paPdpes[2] = pVCpu->pgm.s.aGstPaePdpeRegs[2];
    2379     paPdpes[3] = pVCpu->pgm.s.aGstPaePdpeRegs[3];
    2380     return VINF_SUCCESS;
    2381 }
    2382 
    2383 
    2384 /**
    2385  * Sets the PAE PDPEs values cached by the CPU.
    2386  *
    2387  * @remarks This must be called *AFTER* PGMUpdateCR3.
    2388  *
    2389  * @param   pVCpu               The cross context virtual CPU structure.
    2390  * @param   paPdpes             The four PDPE values. The array pointed to must
    2391  *                              have exactly 4 entries.
    2392  *
    2393  * @remarks No-long-jump zone!!!
    2394  */
    2395 VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPdpes)
    2396 {
    2397     Assert(pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT);
    2398 
    2399     for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.aGstPaePdpeRegs); i++)
    2400     {
    2401         if (pVCpu->pgm.s.aGstPaePdpeRegs[i].u != paPdpes[i].u)
    2402         {
    2403             pVCpu->pgm.s.aGstPaePdpeRegs[i] = paPdpes[i];
    2404 
    2405             /* Force lazy remapping if it changed in any way. */
    2406             pVCpu->pgm.s.apGstPaePDsR3[i]     = 0;
    2407             pVCpu->pgm.s.apGstPaePDsR0[i]     = 0;
    2408             pVCpu->pgm.s.aGCPhysGstPaePDs[i]  = NIL_RTGCPHYS;
    2409         }
    2410     }
    2411 
    2412     VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
    2413 }
    2414 
    2415 
    2416 /**
    24172365 * Gets the current CR3 register value for the shadow memory context.
    24182366 * @returns CR3 value.
    … …  
    24242372    AssertPtrReturn(pPoolPage, NIL_RTHCPHYS);
    24252373    return pPoolPage->Core.Key;
     2374}
     2375
     2376
     2377/**
     2378 * Forces lazy remapping of the guest's PAE page-directory structures.
     2379 *
     2380 * @param   pVCpu   The cross context virtual CPU structure.
     2381 */
     2382static void pgmGstUpdatePaePdpes(PVMCPU pVCpu)
     2383{
     2384    for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.aGCPhysGstPaePDs); i++)
     2385    {
     2386        pVCpu->pgm.s.apGstPaePDsR3[i]     = 0;
     2387        pVCpu->pgm.s.apGstPaePDsR0[i]     = 0;
     2388        pVCpu->pgm.s.aGCPhysGstPaePDs[i]  = NIL_RTGCPHYS;
     2389    }
    24262390}
    24272391
    … …  
    25282492        else
    25292493            STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,FlushTLBSameCR3));
     2494
     2495        /*
     2496         * Update PAE PDPTEs.
     2497         */
     2498        if (PGMMODE_IS_PAE(pVCpu->pgm.s.enmGuestMode))
     2499            pgmGstUpdatePaePdpes(pVCpu);
    25302500    }
    25312501
    … …  
    25952565        AssertRCSuccess(rc); /* Assumes VINF_PGM_SYNC_CR3 doesn't apply to nested paging. */ /** @todo this isn't true for the mac, but we need hw to test/fix this. */
    25962566    }
     2567    /*
     2568     * Update PAE PDPTEs.
     2569     */
     2570    else if (PGMMODE_IS_PAE(pVCpu->pgm.s.enmGuestMode))
     2571        pgmGstUpdatePaePdpes(pVCpu);
    25972572
    25982573    VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_CR3);

  • trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

    r91250 r91271  
    43434343         * Map the 4 PDs too.
    43444344         */
    4345         PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
     4345        X86PDPE aGstPaePdpes[X86_PG_PAE_PDPE_ENTRIES];
     4346        memcpy(&aGstPaePdpes, HCPtrGuestCR3, sizeof(aGstPaePdpes));
     4347        CPUMSetGuestPaePdpes(pVCpu, &aGstPaePdpes[0]);
    43464348        for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
    43474349        {
    4348             pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
    4349             if (pGuestPDPT->a[i].u & X86_PDPE_P)
     4350            X86PDPE PaePdpe = aGstPaePdpes[i];
     4351            if (PaePdpe.u & X86_PDPE_P)
    43504352            {
    43514353                RTHCPTR     HCPtr;
    4352                 RTGCPHYS    GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
     4354                RTGCPHYS    GCPhys = PGM_A20_APPLY(pVCpu, PaePdpe.u & X86_PDPE_PG_MASK);
    43534355                PGM_LOCK_VOID(pVM);
    43544356                PPGMPAGE    pPage  = pgmPhysGetPage(pVM, GCPhys);

  • trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

    r91265 r91271  
    39953995{
    39963996    Assert(VMMRZCallRing3IsEnabled(pVCpu));
    3997     Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
    39983997
    39993998    /* Could happen as a result of longjump. */

  • trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

    r91265 r91271  
    58985898                if (CPUMIsGuestInPAEModeEx(pCtx))
    58995899                {
    5900                     rc  = PGMGstGetPaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
    5901                     AssertRC(rc);
    5902                     rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, pVCpu->hm.s.aPdpes[0].u);     AssertRC(rc);
    5903                     rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, pVCpu->hm.s.aPdpes[1].u);     AssertRC(rc);
    5904                     rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, pVCpu->hm.s.aPdpes[2].u);     AssertRC(rc);
    5905                     rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, pVCpu->hm.s.aPdpes[3].u);     AssertRC(rc);
     5900                    rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, pCtx->aPaePdpes[0].u);     AssertRC(rc);
     5901                    rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, pCtx->aPaePdpes[1].u);     AssertRC(rc);
     5902                    rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, pCtx->aPaePdpes[2].u);     AssertRC(rc);
     5903                    rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, pCtx->aPaePdpes[3].u);     AssertRC(rc);
    59065904                }
    59075905
    … …  
    79647962                        }
    79657963
    7966                         /* If the guest is in PAE mode, sync back the PDPE's into the guest state.
    7967                            Note: CR4.PAE, CR0.PG, EFER MSR changes are always intercepted, so they're up to date. */
     7964                        /*
     7965                         * If the guest is in PAE mode, sync back the PDPE's into the guest state.
     7966                         * CR4.PAE, CR0.PG, EFER MSR changes are always intercepted, so they're up to date.
     7967                         */
    79687968                        if (CPUMIsGuestInPAEModeEx(pCtx))
    79697969                        {
    7970                             rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &pVCpu->hm.s.aPdpes[0].u);     AssertRC(rc);
    7971                             rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &pVCpu->hm.s.aPdpes[1].u);     AssertRC(rc);
    7972                             rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &pVCpu->hm.s.aPdpes[2].u);     AssertRC(rc);
    7973                             rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &pVCpu->hm.s.aPdpes[3].u);     AssertRC(rc);
    7974                             VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
     7970                            X86PDPE aPaePdpes[4];
     7971                            rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &aPaePdpes[0].u);     AssertRC(rc);
     7972                            rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &aPaePdpes[1].u);     AssertRC(rc);
     7973                            rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &aPaePdpes[2].u);     AssertRC(rc);
     7974                            rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &aPaePdpes[3].u);     AssertRC(rc);
     7975                            if (memcmp(&aPaePdpes[0], &pCtx->aPaePdpes[0], sizeof(aPaePdpes)))
     7976                            {
     7977                                memcpy(&pCtx->aPaePdpes[0], &aPaePdpes[0], sizeof(aPaePdpes));
     7978                                /* PGM now updates PAE PDPTEs while updating CR3. */
     7979                                VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
     7980                            }
    79757981                        }
    79767982                    }
    … …  
    80448050            PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
    80458051        }
    8046 
    8047         if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
    8048             PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
    8049 
    80508052        Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
    8051         Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
    80528053    }
    80538054
    … …  
    1090210903        Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
    1090310904    }
    10904     if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
    10905     {
    10906         PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
    10907         Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
    10908     }
    1090910905
    1091010906#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
    … …  
    1127911275        {
    1128011276            VMMRZCallRing3Enable(pVCpu);
    11281 
    1128211277            Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
    11283             Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
    1128411278
    1128511279#ifdef HMVMX_ALWAYS_SAVE_RO_GUEST_STATE
    … …  
    1563915633        case VMX_EXIT_QUAL_CRX_ACCESS_WRITE:
    1564015634        {
     15635            /*
     15636             * When PAE paging is used, the CPU will reload PAE PDPTEs from CR3 when the guest
     15637             * changes certain bits even in CR0, CR4 (and not just CR3). We are currently fine
     15638             * since IEM_CPUMCTX_EXTRN_MUST_MASK (used below) includes CR3 which will import
     15639             * PAE PDPTEs as well.
     15640             */
    1564115641            int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK);
    1564215642            AssertRCReturn(rc, rc);

  • trunk/src/VBox/VMM/VMMR0/VMMR0.cpp

    r91245 r91271  
    732732    uint64_t const fCpuFFs = VMCPU_FF_TIMER                   | VMCPU_FF_PDM_CRITSECT         | VMCPU_FF_IEM
    733733                           | VMCPU_FF_REQUEST                 | VMCPU_FF_DBGF                 | VMCPU_FF_HM_UPDATE_CR3
    734                            | VMCPU_FF_HM_UPDATE_PAE_PDPES     | VMCPU_FF_PGM_SYNC_CR3         | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
     734                           | VMCPU_FF_PGM_SYNC_CR3            | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
    735735                           | VMCPU_FF_TO_R3                   | VMCPU_FF_IOM;
    736736

  • trunk/src/VBox/VMM/VMMR3/CPUM.cpp

    r91120 r91271  
    26852685            SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
    26862686        }
     2687        SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
     2688        SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
     2689        SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
     2690        SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
    26872691        if (pVM->cpum.s.GuestFeatures.fSvm)
    26882692        {
    … …  
    29612965                    PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
    29622966                    SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
     2967                }
     2968                if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
     2969                {
     2970                    SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
     2971                    SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
     2972                    SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
     2973                    SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
    29632974                }
    29642975                if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
    … …  
    35893600                pszPrefix, pCtx->msrSFMASK,
    35903601                pszPrefix, pCtx->msrKERNELGSBASE);
     3602
     3603            if (CPUMIsGuestInPAEModeEx(pCtx))
     3604                for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
     3605                    pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u  =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
    35913606            break;
    35923607    }

  • trunk/src/VBox/VMM/VMMR3/EM.cpp

    r91264 r91271  
    14581458    }
    14591459
    1460     /* Update PAE PDPEs. This must be done *after* PGMUpdateCR3() and used only by the Nested Paging case for HM. */
    1461     if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
    1462     {
    1463         CPUM_IMPORT_EXTRN_RCSTRICT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER, rc);
    1464         if (CPUMIsGuestInPAEMode(pVCpu))
    1465         {
    1466             PX86PDPE pPdpes = HMGetPaePdpes(pVCpu);
    1467             AssertPtr(pPdpes);
    1468 
    1469             PGMGstUpdatePaePdpes(pVCpu, pPdpes);
    1470             Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
    1471         }
    1472         else
    1473             VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
    1474     }
    1475 
    14761460    /* IEM has pending work (typically memory write after INS instruction). */
    14771461    if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_IEM))

  • trunk/src/VBox/VMM/VMMR3/PGM.cpp

    r91249 r91271  
    801801            pPGM->apGstPaePDsR0[i]             = NIL_RTR0PTR;
    802802            pPGM->aGCPhysGstPaePDs[i]          = NIL_RTGCPHYS;
    803             pPGM->aGstPaePdpeRegs[i].u         = UINT64_MAX;
    804803            pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
    805804        }

  • trunk/src/VBox/VMM/VMMR3/VMM.cpp

    r91246 r91271  
    26482648        PRINT_FLAG(VMCPU_FF_,REQUEST);
    26492649        PRINT_FLAG(VMCPU_FF_,HM_UPDATE_CR3);
    2650         PRINT_FLAG(VMCPU_FF_,HM_UPDATE_PAE_PDPES);
    26512650        PRINT_FLAG(VMCPU_FF_,PGM_SYNC_CR3);
    26522651        PRINT_FLAG(VMCPU_FF_,PGM_SYNC_CR3_NON_GLOBAL);

  • trunk/src/VBox/VMM/include/CPUMInternal.h

    r91266 r91271  
    115115 * @{ */
    116116/** The current saved state version. */
    117 #define CPUM_SAVED_STATE_VERSION                CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
     117#define CPUM_SAVED_STATE_VERSION                CPUM_SAVED_STATE_VERSION_PAE_PDPES
     118/** The saved state version with PAE PDPEs added. */
     119#define CPUM_SAVED_STATE_VERSION_PAE_PDPES      21
    118120/** The saved state version with more virtual VMCS fields and CPUMCTX VMX fields. */
    119121#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2   20

  • trunk/src/VBox/VMM/include/CPUMInternal.mac

    r91266 r91271  
    224224    alignb 8
    225225    .Guest.fExtrn             resq    1
     226    .Guest.aPaePdpes          resq    4
    226227    alignb 8
    227228    .Guest.hwvirt.svm.uMsrHSavePa            resq         1

  • trunk/src/VBox/VMM/include/PGMInternal.h

    r91250 r91271  
    35543554    /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
    35553555    RTGCPHYS                        aGCPhysGstPaePDs[4];
    3556     /** The values of the 4 PDPE CPU registers (PAE).
    3557      * @todo Not really maintained by PGM atm, only by VT-x in EPT mode. Should
    3558      *       load on cr3 load and use instead of guest memory version like real
    3559      *       HW.  We probably should move these to the CPUMCTX and treat them
    3560      *       like the rest of the register wrt exporting to VT-x and import back. */
    3561     X86PDPE                         aGstPaePdpeRegs[4];
    35623556    /** The physical addresses of the monitored guest page directories (PAE). */
    35633557    RTGCPHYS                        aGCPhysGstPaePDsMonitored[4];
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