VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 22016

Last change on this file since 22016 was 22016, checked in by vboxsync, 16 years ago

MSR bitmap must be per-VCPU
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1/* $Id: HWSVMR0.cpp 22016 2009-08-06 09:07:11Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/hwacc_svm.h>
32#include <VBox/pgm.h>
33#include <VBox/pdm.h>
34#include <VBox/err.h>
35#include <VBox/log.h>
36#include <VBox/selm.h>
37#include <VBox/iom.h>
38#include <VBox/dis.h>
39#include <VBox/dbgf.h>
40#include <VBox/disopcode.h>
41#include <iprt/param.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/cpuset.h>
45#include <iprt/mp.h>
46#include <iprt/time.h>
47#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
48# include <iprt/thread.h>
49#endif
50#include "HWSVMR0.h"
51
52/*******************************************************************************
53* Internal Functions *
54*******************************************************************************/
55static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
56static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
57static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
58
59/*******************************************************************************
60* Global Variables *
61*******************************************************************************/
62/* IO operation lookup arrays. */
63static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
64
65/**
66 * Sets up and activates AMD-V on the current CPU
67 *
68 * @returns VBox status code.
69 * @param pCpu CPU info struct
70 * @param pVM The VM to operate on. (can be NULL after a resume!!)
71 * @param pvPageCpu Pointer to the global cpu page
72 * @param pPageCpuPhys Physical address of the global cpu page
73 */
74VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
75{
76 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
77 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
78
79 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
80
81#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
82 SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
83#endif
84
85 /* Turn on AMD-V in the EFER MSR. */
86 uint64_t val = ASMRdMsr(MSR_K6_EFER);
87 if (!(val & MSR_K6_EFER_SVME))
88 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
89
90 /* Write the physical page address where the CPU will store the host state while executing the VM. */
91 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
92
93 return VINF_SUCCESS;
94}
95
96/**
97 * Deactivates AMD-V on the current CPU
98 *
99 * @returns VBox status code.
100 * @param pCpu CPU info struct
101 * @param pvPageCpu Pointer to the global cpu page
102 * @param pPageCpuPhys Physical address of the global cpu page
103 */
104VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
105{
106 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
107 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
108
109#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
110 SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
111#endif
112
113 /* Turn off AMD-V in the EFER MSR. */
114 uint64_t val = ASMRdMsr(MSR_K6_EFER);
115 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
116
117 /* Invalidate host state physical address. */
118 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
119
120 return VINF_SUCCESS;
121}
122
123/**
124 * Does Ring-0 per VM AMD-V init.
125 *
126 * @returns VBox status code.
127 * @param pVM The VM to operate on.
128 */
129VMMR0DECL(int) SVMR0InitVM(PVM pVM)
130{
131 int rc;
132
133 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
134
135 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
136 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
137 if (RT_FAILURE(rc))
138 return rc;
139
140 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
141 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
142 /* Set all bits to intercept all IO accesses. */
143 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
144
145 /* Erratum 170 which requires a forced TLB flush for each world switch:
146 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
147 *
148 * All BH-G1/2 and DH-G1/2 models include a fix:
149 * Athlon X2: 0x6b 1/2
150 * 0x68 1/2
151 * Athlon 64: 0x7f 1
152 * 0x6f 2
153 * Sempron: 0x7f 1/2
154 * 0x6f 2
155 * 0x6c 2
156 * 0x7c 2
157 * Turion 64: 0x68 2
158 *
159 */
160 uint32_t u32Dummy;
161 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
162 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
163 u32BaseFamily= (u32Version >> 8) & 0xf;
164 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
165 u32Model = ((u32Version >> 4) & 0xf);
166 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
167 u32Stepping = u32Version & 0xf;
168 if ( u32Family == 0xf
169 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
170 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
171 {
172 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
173 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
174 }
175
176 /* Allocate VMCBs for all guest CPUs. */
177 for (unsigned i=0;i<pVM->cCPUs;i++)
178 {
179 PVMCPU pVCpu = &pVM->aCpus[i];
180
181 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
182 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
183 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
184
185 /* Allocate one page for the host context */
186 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
187 if (RT_FAILURE(rc))
188 return rc;
189
190 pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
191 pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
192 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
193
194 /* Allocate one page for the VM control block (VMCB). */
195 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
196 if (RT_FAILURE(rc))
197 return rc;
198
199 pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
200 pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
201 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
202
203 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
204 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 pVCpu->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);
209 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
210 /* Set all bits to intercept all MSR accesses. */
211 ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
212 }
213
214 return VINF_SUCCESS;
215}
216
217/**
218 * Does Ring-0 per VM AMD-V termination.
219 *
220 * @returns VBox status code.
221 * @param pVM The VM to operate on.
222 */
223VMMR0DECL(int) SVMR0TermVM(PVM pVM)
224{
225 for (unsigned i=0;i<pVM->cCPUs;i++)
226 {
227 PVMCPU pVCpu = &pVM->aCpus[i];
228
229 if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
230 {
231 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
232 pVCpu->hwaccm.s.svm.pVMCBHost = 0;
233 pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
234 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
235 }
236
237 if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
238 {
239 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
240 pVCpu->hwaccm.s.svm.pVMCB = 0;
241 pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
242 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
243 }
244 if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
245 {
246 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);
247 pVCpu->hwaccm.s.svm.pMSRBitmap = 0;
248 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = 0;
249 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
250 }
251 }
252 if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
253 {
254 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
255 pVM->hwaccm.s.svm.pIOBitmap = 0;
256 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
257 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
258 }
259 return VINF_SUCCESS;
260}
261
262/**
263 * Sets up AMD-V for the specified VM
264 *
265 * @returns VBox status code.
266 * @param pVM The VM to operate on.
267 */
268VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
269{
270 int rc = VINF_SUCCESS;
271
272 AssertReturn(pVM, VERR_INVALID_PARAMETER);
273
274 Assert(pVM->hwaccm.s.svm.fSupported);
275
276 for (unsigned i=0;i<pVM->cCPUs;i++)
277 {
278 PVMCPU pVCpu = &pVM->aCpus[i];
279 SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
280
281 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
282
283 /* Program the control fields. Most of them never have to be changed again. */
284 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
285 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
286 if (!pVM->hwaccm.s.fNestedPaging)
287 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
288 else
289 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
290
291 /*
292 * CR0/3/4 writes must be intercepted for obvious reasons.
293 */
294 if (!pVM->hwaccm.s.fNestedPaging)
295 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
296 else
297 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);
298
299 /* Intercept all DRx reads and writes by default. Changed later on. */
300 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
301 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
302
303 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
304 * All breakpoints are automatically cleared when the VM exits.
305 */
306
307 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
308#ifndef DEBUG
309 if (pVM->hwaccm.s.fNestedPaging)
310 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
311#endif
312
313 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
314 | SVM_CTRL1_INTERCEPT_VINTR
315 | SVM_CTRL1_INTERCEPT_NMI
316 | SVM_CTRL1_INTERCEPT_SMI
317 | SVM_CTRL1_INTERCEPT_INIT
318 | SVM_CTRL1_INTERCEPT_RDPMC
319 | SVM_CTRL1_INTERCEPT_CPUID
320 | SVM_CTRL1_INTERCEPT_RSM
321 | SVM_CTRL1_INTERCEPT_HLT
322 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
323 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
324 | SVM_CTRL1_INTERCEPT_INVLPG
325 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
326 | SVM_CTRL1_INTERCEPT_TASK_SWITCH
327 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
328 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
329 ;
330 /* With nested paging we don't care about invlpg anymore. */
331 if (pVM->hwaccm.s.fNestedPaging)
332 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
333
334 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
335 | SVM_CTRL2_INTERCEPT_VMMCALL
336 | SVM_CTRL2_INTERCEPT_VMLOAD
337 | SVM_CTRL2_INTERCEPT_VMSAVE
338 | SVM_CTRL2_INTERCEPT_STGI
339 | SVM_CTRL2_INTERCEPT_CLGI
340 | SVM_CTRL2_INTERCEPT_SKINIT
341 | SVM_CTRL2_INTERCEPT_WBINVD
342 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
343 ;
344 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
345 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
346 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
347
348 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
349 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
350 /* Ignore the priority in the TPR; just deliver it when we tell it to. */
351 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
352
353 /* Set IO and MSR bitmap addresses. */
354 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
355 pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;
356
357 /* No LBR virtualization. */
358 pVMCB->ctrl.u64LBRVirt = 0;
359
360 /** The ASID must start at 1; the host uses 0. */
361 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
362
363 /** Setup the PAT msr (nested paging only) */
364 pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
365 /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
366 * to modify them directly.
367 */
368 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
369 svmR0SetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
370 svmR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
371 svmR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
372 svmR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
373 svmR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
374 svmR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
375 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
376 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
377 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
378 }
379
380 return rc;
381}
382
383
384/**
385 * Sets the permission bits for the specified MSR
386 *
387 * @param pVCpu The VMCPU to operate on.
388 * @param ulMSR MSR value
389 * @param fRead Reading allowed/disallowed
390 * @param fWrite Writing allowed/disallowed
391 */
392static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
393{
394 unsigned ulBit;
395 uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.svm.pMSRBitmap;
396
397 if (ulMSR <= 0x00001FFF)
398 {
399 /* Pentium-compatible MSRs */
400 ulBit = ulMSR * 2;
401 }
402 else
403 if ( ulMSR >= 0xC0000000
404 && ulMSR <= 0xC0001FFF)
405 {
406 /* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
407 ulBit = (ulMSR - 0xC0000000) * 2;
408 pMSRBitmap += 0x800;
409 }
410 else
411 if ( ulMSR >= 0xC0010000
412 && ulMSR <= 0xC0011FFF)
413 {
414 /* AMD Seventh and Eighth Generation Processor MSRs */
415 ulBit = (ulMSR - 0xC0001000) * 2;
416 pMSRBitmap += 0x1000;
417 }
418 else
419 {
420 AssertFailed();
421 return;
422 }
423 Assert(ulBit < 16 * 1024 - 1);
424 if (fRead)
425 ASMBitClear(pMSRBitmap, ulBit);
426 else
427 ASMBitSet(pMSRBitmap, ulBit);
428
429 if (fWrite)
430 ASMBitClear(pMSRBitmap, ulBit + 1);
431 else
432 ASMBitSet(pMSRBitmap, ulBit + 1);
433}
434
435/**
436 * Injects an event (trap or external interrupt)
437 *
438 * @param pVCpu The VMCPU to operate on.
439 * @param pVMCB SVM control block
440 * @param pCtx CPU Context
441 * @param pIntInfo SVM interrupt info
442 */
443inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
444{
445#ifdef VBOX_WITH_STATISTICS
446 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
447#endif
448
449#ifdef VBOX_STRICT
450 if (pEvent->n.u8Vector == 0xE)
451 Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
452 else
453 if (pEvent->n.u8Vector < 0x20)
454 Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
455 else
456 {
457 Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
458 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
459 Assert(pCtx->eflags.u32 & X86_EFL_IF);
460 }
461#endif
462
463 /* Set event injection state. */
464 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
465}
466
467
468/**
469 * Checks for pending guest interrupts and injects them
470 *
471 * @returns VBox status code.
472 * @param pVM The VM to operate on.
473 * @param pVCpu The VM CPU to operate on.
474 * @param pVMCB SVM control block
475 * @param pCtx CPU Context
476 */
477static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
478{
479 int rc;
480
481 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
482 if (pVCpu->hwaccm.s.Event.fPending)
483 {
484 SVM_EVENT Event;
485
486 Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
487 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
488 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
489 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
490
491 pVCpu->hwaccm.s.Event.fPending = false;
492 return VINF_SUCCESS;
493 }
494
495 /* If an active trap is already pending, then we must forward it first! */
496 if (!TRPMHasTrap(pVCpu))
497 {
498 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
499 {
500 SVM_EVENT Event;
501
502 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
503 Event.n.u8Vector = X86_XCPT_NMI;
504 Event.n.u1Valid = 1;
505 Event.n.u32ErrorCode = 0;
506 Event.n.u3Type = SVM_EVENT_NMI;
507
508 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
509 return VINF_SUCCESS;
510 }
511
512 /* @todo SMI interrupts. */
513
514 /* When external interrupts are pending, we should exit the VM when IF is set. */
515 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
516 {
517 if ( !(pCtx->eflags.u32 & X86_EFL_IF)
518 || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
519 {
520 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
521 {
522 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
523 LogFlow(("Enable irq window exit!\n"));
524 else
525 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
526
527 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
528 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
529 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
530 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
531 }
532 }
533 else
534 {
535 uint8_t u8Interrupt;
536
537 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
538 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
539 if (RT_SUCCESS(rc))
540 {
541 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
542 AssertRC(rc);
543 }
544 else
545 {
546 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
547 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
548 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
549 /* Just continue */
550 }
551 }
552 }
553 }
554
555#ifdef VBOX_STRICT
556 if (TRPMHasTrap(pVCpu))
557 {
558 uint8_t u8Vector;
559 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
560 AssertRC(rc);
561 }
562#endif
563
564 if ( (pCtx->eflags.u32 & X86_EFL_IF)
565 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
566 && TRPMHasTrap(pVCpu)
567 )
568 {
569 uint8_t u8Vector;
570 int rc;
571 TRPMEVENT enmType;
572 SVM_EVENT Event;
573 RTGCUINT u32ErrorCode;
574
575 Event.au64[0] = 0;
576
577 /* If a new event is pending, then dispatch it now. */
578 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
579 AssertRC(rc);
580 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
581 Assert(enmType != TRPM_SOFTWARE_INT);
582
583 /* Clear the pending trap. */
584 rc = TRPMResetTrap(pVCpu);
585 AssertRC(rc);
586
587 Event.n.u8Vector = u8Vector;
588 Event.n.u1Valid = 1;
589 Event.n.u32ErrorCode = u32ErrorCode;
590
591 if (enmType == TRPM_TRAP)
592 {
593 switch (u8Vector) {
594 case 8:
595 case 10:
596 case 11:
597 case 12:
598 case 13:
599 case 14:
600 case 17:
601 /* Valid error codes. */
602 Event.n.u1ErrorCodeValid = 1;
603 break;
604 default:
605 break;
606 }
607 if (u8Vector == X86_XCPT_NMI)
608 Event.n.u3Type = SVM_EVENT_NMI;
609 else
610 Event.n.u3Type = SVM_EVENT_EXCEPTION;
611 }
612 else
613 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
614
615 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
616 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
617 } /* if (interrupts can be dispatched) */
618
619 return VINF_SUCCESS;
620}
621
622/**
623 * Save the host state
624 *
625 * @returns VBox status code.
626 * @param pVM The VM to operate on.
627 * @param pVCpu The VM CPU to operate on.
628 */
629VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
630{
631 NOREF(pVM);
632 NOREF(pVCpu);
633 /* Nothing to do here. */
634 return VINF_SUCCESS;
635}
636
637/**
638 * Loads the guest state
639 *
640 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
641 *
642 * @returns VBox status code.
643 * @param pVM The VM to operate on.
644 * @param pVCpu The VM CPU to operate on.
645 * @param pCtx Guest context
646 */
647VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
648{
649 RTGCUINTPTR val;
650 SVM_VMCB *pVMCB;
651
652 if (pVM == NULL)
653 return VERR_INVALID_PARAMETER;
654
655 /* Setup AMD SVM. */
656 Assert(pVM->hwaccm.s.svm.fSupported);
657
658 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
659 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
660
661 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
662 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
663 {
664 SVM_WRITE_SELREG(CS, cs);
665 SVM_WRITE_SELREG(SS, ss);
666 SVM_WRITE_SELREG(DS, ds);
667 SVM_WRITE_SELREG(ES, es);
668 SVM_WRITE_SELREG(FS, fs);
669 SVM_WRITE_SELREG(GS, gs);
670 }
671
672 /* Guest CPU context: LDTR. */
673 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
674 {
675 SVM_WRITE_SELREG(LDTR, ldtr);
676 }
677
678 /* Guest CPU context: TR. */
679 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
680 {
681 SVM_WRITE_SELREG(TR, tr);
682 }
683
684 /* Guest CPU context: GDTR. */
685 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
686 {
687 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
688 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
689 }
690
691 /* Guest CPU context: IDTR. */
692 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
693 {
694 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
695 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
696 }
697
698 /*
699 * Sysenter MSRs (unconditional)
700 */
701 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
702 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
703 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
704
705 /* Control registers */
706 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
707 {
708 val = pCtx->cr0;
709 if (!CPUMIsGuestFPUStateActive(pVCpu))
710 {
711 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
712 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
713 }
714 else
715 {
716 /** @todo check if we support the old style mess correctly. */
717 if (!(val & X86_CR0_NE))
718 {
719 Log(("Forcing X86_CR0_NE!!!\n"));
720
721 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
722 if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
723 {
724 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
725 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
726 }
727 }
728 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
729 }
730 /* Always enable caching. */
731 val &= ~(X86_CR0_CD|X86_CR0_NW);
732
733 /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
734 /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
735 if (!pVM->hwaccm.s.fNestedPaging)
736 {
737 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
738 val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
739 }
740 pVMCB->guest.u64CR0 = val;
741 }
742 /* CR2 as well */
743 pVMCB->guest.u64CR2 = pCtx->cr2;
744
745 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
746 {
747 /* Save our shadow CR3 register. */
748 if (pVM->hwaccm.s.fNestedPaging)
749 {
750 PGMMODE enmShwPagingMode;
751
752#if HC_ARCH_BITS == 32
753 if (CPUMIsGuestInLongModeEx(pCtx))
754 enmShwPagingMode = PGMMODE_AMD64_NX;
755 else
756#endif
757 enmShwPagingMode = PGMGetHostMode(pVM);
758
759 pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
760 Assert(pVMCB->ctrl.u64NestedPagingCR3);
761 pVMCB->guest.u64CR3 = pCtx->cr3;
762 }
763 else
764 {
765 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
766 Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
767 }
768 }
769
770 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
771 {
772 val = pCtx->cr4;
773 if (!pVM->hwaccm.s.fNestedPaging)
774 {
775 switch(pVCpu->hwaccm.s.enmShadowMode)
776 {
777 case PGMMODE_REAL:
778 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
779 AssertFailed();
780 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
781
782 case PGMMODE_32_BIT: /* 32-bit paging. */
783 val &= ~X86_CR4_PAE;
784 break;
785
786 case PGMMODE_PAE: /* PAE paging. */
787 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
788 /** @todo use normal 32 bits paging */
789 val |= X86_CR4_PAE;
790 break;
791
792 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
793 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
794#ifdef VBOX_ENABLE_64_BITS_GUESTS
795 break;
796#else
797 AssertFailed();
798 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
799#endif
800
801 default: /* shut up gcc */
802 AssertFailed();
803 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
804 }
805 }
806 pVMCB->guest.u64CR4 = val;
807 }
808
809 /* Debug registers. */
810 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
811 {
812 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
813 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
814
815 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
816 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
817 pCtx->dr[7] |= 0x400; /* must be one */
818
819 pVMCB->guest.u64DR7 = pCtx->dr[7];
820 pVMCB->guest.u64DR6 = pCtx->dr[6];
821
822#ifdef DEBUG
823 /* Sync the hypervisor debug state now if any breakpoint is armed. */
824 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
825 && !CPUMIsHyperDebugStateActive(pVCpu)
826 && !DBGFIsStepping(pVCpu))
827 {
828 /* Save the host and load the hypervisor debug state. */
829 int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
830 AssertRC(rc);
831
832 /* DRx intercepts remain enabled. */
833
834 /* Override dr6 & dr7 with the hypervisor values. */
835 pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
836 pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
837 }
838 else
839#endif
840 /* Sync the debug state now if any breakpoint is armed. */
841 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
842 && !CPUMIsGuestDebugStateActive(pVCpu)
843 && !DBGFIsStepping(pVCpu))
844 {
845 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
846
847 /* Disable drx move intercepts. */
848 pVMCB->ctrl.u16InterceptRdDRx = 0;
849 pVMCB->ctrl.u16InterceptWrDRx = 0;
850
851 /* Save the host and load the guest debug state. */
852 int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
853 AssertRC(rc);
854 }
855 }
856
857 /* EIP, ESP and EFLAGS */
858 pVMCB->guest.u64RIP = pCtx->rip;
859 pVMCB->guest.u64RSP = pCtx->rsp;
860 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
861
862 /* Set CPL */
863 pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
864
865 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
866 pVMCB->guest.u64RAX = pCtx->rax;
867
868 /* vmrun will fail without MSR_K6_EFER_SVME. */
869 pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
870
871 /* 64 bits guest mode? */
872 if (CPUMIsGuestInLongModeEx(pCtx))
873 {
874#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
875 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
876#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
877 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
878#else
879# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
880 if (!pVM->hwaccm.s.fAllow64BitGuests)
881 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
882# endif
883 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
884#endif
885 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
886 pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
887 pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
888 }
889 else
890 {
891 /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
892 pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
893
894 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
895 }
896
897 /* TSC offset. */
898 if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
899 {
900 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
901 pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
902 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
903 }
904 else
905 {
906 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
907 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
908 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
909 }
910
911 /* Sync the various msrs for 64 bits mode. */
912 pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
913 pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
914 pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
915 pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
916 pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
917
918#ifdef DEBUG
919 /* Intercept X86_XCPT_DB if stepping is enabled */
920 if ( DBGFIsStepping(pVCpu)
921 || CPUMIsHyperDebugStateActive(pVCpu))
922 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
923 else
924 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
925#endif
926
927 /* Done. */
928 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
929
930 return VINF_SUCCESS;
931}
932
933
934/**
935 * Runs guest code in an AMD-V VM.
936 *
937 * @returns VBox status code.
938 * @param pVM The VM to operate on.
939 * @param pVCpu The VM CPU to operate on.
940 * @param pCtx Guest context
941 */
942VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
943{
944 int rc = VINF_SUCCESS;
945 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
946 SVM_VMCB *pVMCB;
947 bool fSyncTPR = false;
948 unsigned cResume = 0;
949 uint8_t u8LastTPR;
950 PHWACCM_CPUINFO pCpu = 0;
951 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
952#ifdef VBOX_STRICT
953 RTCPUID idCpuCheck;
954#endif
955#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
956 uint64_t u64LastTime = RTTimeMilliTS();
957#endif
958
959 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
960
961 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
962 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
963
964 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
965 */
966ResumeExecution:
967 Assert(!HWACCMR0SuspendPending());
968
969 /* Safety precaution; looping for too long here can have a very bad effect on the host */
970 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
971 {
972 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
973 rc = VINF_EM_RAW_INTERRUPT;
974 goto end;
975 }
976
977 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
978 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
979 {
980 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
981 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
982 {
983 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
984 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
985 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
986 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
987 */
988 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
989 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
990 pVMCB->ctrl.u64IntShadow = 0;
991 }
992 }
993 else
994 {
995 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
996 pVMCB->ctrl.u64IntShadow = 0;
997 }
998
999#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1000 if (RT_UNLIKELY(cResume & 0xf) == 0)
1001 {
1002 uint64_t u64CurTime = RTTimeMilliTS();
1003
1004 if (RT_UNLIKELY(u64CurTime > u64LastTime))
1005 {
1006 u64LastTime = u64CurTime;
1007 TMTimerPollVoid(pVM, pVCpu);
1008 }
1009 }
1010#endif
1011
1012 /* Check for pending actions that force us to go back to ring 3. */
1013#ifdef DEBUG
1014 /* Intercept X86_XCPT_DB if stepping is enabled */
1015 if (!DBGFIsStepping(pVCpu))
1016#endif
1017 {
1018 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
1019 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
1020 {
1021 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
1022 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
1023 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1024 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
1025 goto end;
1026 }
1027 }
1028
1029 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1030 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
1031 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1032 {
1033 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1034 rc = VINF_EM_PENDING_REQUEST;
1035 goto end;
1036 }
1037
1038#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1039 /*
1040 * Exit to ring-3 preemption/work is pending.
1041 *
1042 * Interrupts are disabled before the call to make sure we don't miss any interrupt
1043 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
1044 * further down, but SVMR0CheckPendingInterrupt makes that impossible.)
1045 *
1046 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
1047 * shootdowns rely on this.
1048 */
1049 uOldEFlags = ASMIntDisableFlags();
1050 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
1051 {
1052 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
1053 rc = VINF_EM_RAW_INTERRUPT;
1054 goto end;
1055 }
1056 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1057#endif
1058
1059 /* When external interrupts are pending, we should exit the VM when IF is set. */
1060 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1061 rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
1062 if (RT_FAILURE(rc))
1063 {
1064 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1065 goto end;
1066 }
1067
1068 /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
1069 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)
1070 * @todo query and update the TPR only when it could have been changed (mmio access)
1071 */
1072 if (pVM->hwaccm.s.fHasIoApic)
1073 {
1074 bool fPending;
1075
1076 /* TPR caching in CR8 */
1077 int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
1078 AssertRC(rc);
1079
1080 if (pVM->hwaccm.s.svm.fTPRPatchingActive)
1081 {
1082 /* Our patch code uses LSTAR for TPR caching. */
1083 pCtx->msrLSTAR = u8LastTPR;
1084
1085 if (fPending)
1086 {
1087 /* A TPR change could activate a pending interrupt, so catch lstar writes. */
1088 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
1089 }
1090 else
1091 /* No interrupts are pending, so we don't need to be explicitely notified.
1092 * There are enough world switches for detecting pending interrupts.
1093 */
1094 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
1095 }
1096 else
1097 {
1098 pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1099
1100 if (fPending)
1101 {
1102 /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1103 pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
1104 }
1105 else
1106 /* No interrupts are pending, so we don't need to be explicitely notified.
1107 * There are enough world switches for detecting pending interrupts.
1108 */
1109 pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1110 }
1111 fSyncTPR = !fPending;
1112 }
1113
1114 /* All done! Let's start VM execution. */
1115 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
1116
1117 /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1118 pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1119
1120#ifdef LOG_ENABLED
1121 pCpu = HWACCMR0GetCurrentCpu();
1122 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1123 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1124 {
1125 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1126 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1127 else
1128 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1129 }
1130 if (pCpu->fFlushTLB)
1131 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1132#endif
1133
1134 /*
1135 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1136 * (until the actual world switch)
1137 */
1138#ifdef VBOX_STRICT
1139 idCpuCheck = RTMpCpuId();
1140#endif
1141 VMMR0LogFlushDisable(pVCpu);
1142
1143 /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
1144 rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1145 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1146 {
1147 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1148 VMMR0LogFlushEnable(pVCpu);
1149 goto end;
1150 }
1151
1152#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1153 /* Disable interrupts to make sure a poke will interrupt execution.
1154 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
1155 */
1156 uOldEFlags = ASMIntDisableFlags();
1157 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1158#endif
1159
1160 pCpu = HWACCMR0GetCurrentCpu();
1161 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1162 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1163 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1164 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1165 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1166 {
1167 /* Force a TLB flush on VM entry. */
1168 pVCpu->hwaccm.s.fForceTLBFlush = true;
1169 }
1170 else
1171 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1172
1173 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1174
1175 /* Check for tlb shootdown flushes. */
1176 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1177 pVCpu->hwaccm.s.fForceTLBFlush = true;
1178
1179 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1180 if ( pVCpu->hwaccm.s.fForceTLBFlush
1181 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1182 {
1183 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1184 || pCpu->fFlushTLB)
1185 {
1186 pCpu->fFlushTLB = false;
1187 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1188 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1189 pCpu->cTLBFlushes++;
1190 }
1191 else
1192 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1193
1194 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1195 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1196 }
1197 else
1198 {
1199 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1200
1201 /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1202 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1203 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1204
1205 Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
1206 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1207
1208 if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1209 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1210 {
1211 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1212 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1213 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1214 SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1215 }
1216 }
1217 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1218 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1219
1220 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1221 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1222 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1223 pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1224
1225#ifdef VBOX_WITH_STATISTICS
1226 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1227 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1228 else
1229 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1230#endif
1231
1232 /* In case we execute a goto ResumeExecution later on. */
1233 pVCpu->hwaccm.s.fResumeVM = true;
1234 pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1235
1236 Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1237 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1238 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1239 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);
1240 Assert(pVMCB->ctrl.u64LBRVirt == 0);
1241
1242#ifdef VBOX_STRICT
1243 Assert(idCpuCheck == RTMpCpuId());
1244#endif
1245 TMNotifyStartOfExecution(pVCpu);
1246#ifdef VBOX_WITH_KERNEL_USING_XMM
1247 hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
1248#else
1249 pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1250#endif
1251 TMNotifyEndOfExecution(pVCpu);
1252 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1253 ASMSetFlags(uOldEFlags);
1254#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1255 uOldEFlags = ~(RTCCUINTREG)0;
1256#endif
1257 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1258
1259 /*
1260 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1261 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1262 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1263 */
1264
1265 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, x);
1266
1267 /* Reason for the VM exit */
1268 exitCode = pVMCB->ctrl.u64ExitCode;
1269
1270 if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1271 {
1272 HWACCMDumpRegs(pVM, pVCpu, pCtx);
1273#ifdef DEBUG
1274 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1275 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1276 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1277 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1278 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1279 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1280 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1281 Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1282 Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1283 Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1284
1285 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1286 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1287 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1288 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1289
1290 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1291 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1292 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1293 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1294 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1295 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1296 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1297 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1298 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1299 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1300
1301 Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1302 Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1303 Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1304 Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1305 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1306 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1307 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1308 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1309 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1310 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1311 Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1312 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1313 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1314 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1315 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1316 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1317 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1318
1319 Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1320 Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1321
1322 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1323 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1324 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1325 Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1326 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1327 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1328 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1329 Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1330 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1331 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1332 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1333 Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1334 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1335 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1336 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1337 Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1338 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1339 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1340 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1341 Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1342
1343 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1344 Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1345
1346 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1347 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1348 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1349 Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1350
1351 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1352 Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1353
1354 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1355 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1356 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1357 Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1358
1359 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1360 Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1361 Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1362 Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1363 Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1364 Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1365 Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1366
1367 Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1368 Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1369 Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1370 Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1371
1372 Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1373 Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1374 Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1375
1376 Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1377 Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1378 Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1379 Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1380 Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1381 Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1382 Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1383 Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1384 Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1385 Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1386 Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1387 Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1388
1389#endif
1390 rc = VERR_SVM_UNABLE_TO_START_VM;
1391 VMMR0LogFlushEnable(pVCpu);
1392 goto end;
1393 }
1394
1395 /* Let's first sync back eip, esp, and eflags. */
1396 pCtx->rip = pVMCB->guest.u64RIP;
1397 pCtx->rsp = pVMCB->guest.u64RSP;
1398 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1399 /* eax is saved/restore across the vmrun instruction */
1400 pCtx->rax = pVMCB->guest.u64RAX;
1401
1402 /* Save all the MSRs that can be changed by the guest without causing a world switch. (fs & gs base are saved with SVM_READ_SELREG) */
1403 pCtx->msrSTAR = pVMCB->guest.u64STAR; /* legacy syscall eip, cs & ss */
1404 pCtx->msrLSTAR = pVMCB->guest.u64LSTAR; /* 64 bits mode syscall rip */
1405 pCtx->msrCSTAR = pVMCB->guest.u64CSTAR; /* compatibility mode syscall rip */
1406 pCtx->msrSFMASK = pVMCB->guest.u64SFMASK; /* syscall flag mask */
1407 pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1408 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1409 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1410 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1411
1412 /* Can be updated behind our back in the nested paging case. */
1413 pCtx->cr2 = pVMCB->guest.u64CR2;
1414
1415 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1416 SVM_READ_SELREG(SS, ss);
1417 SVM_READ_SELREG(CS, cs);
1418 SVM_READ_SELREG(DS, ds);
1419 SVM_READ_SELREG(ES, es);
1420 SVM_READ_SELREG(FS, fs);
1421 SVM_READ_SELREG(GS, gs);
1422
1423 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1424 SVM_READ_SELREG(LDTR, ldtr);
1425 SVM_READ_SELREG(TR, tr);
1426
1427 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1428 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1429
1430 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1431 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1432
1433 /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1434 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1435 if ( pVM->hwaccm.s.fNestedPaging
1436 && pCtx->cr3 != pVMCB->guest.u64CR3)
1437 {
1438 CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1439 PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1440 }
1441
1442 /* Note! NOW IT'S SAFE FOR LOGGING! */
1443 VMMR0LogFlushEnable(pVCpu);
1444
1445 /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1446 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1447 {
1448 Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1449 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1450 }
1451 else
1452 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1453
1454 Log2(("exitCode = %x\n", exitCode));
1455
1456 /* Sync back DR6 as it could have been changed by hitting breakpoints. */
1457 pCtx->dr[6] = pVMCB->guest.u64DR6;
1458 /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1459 pCtx->dr[7] = pVMCB->guest.u64DR7;
1460
1461 /* Check if an injected event was interrupted prematurely. */
1462 pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1463 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1464 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1465 {
1466 Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1467
1468#ifdef LOG_ENABLED
1469 SVM_EVENT Event;
1470 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1471
1472 if ( exitCode == SVM_EXIT_EXCEPTION_E
1473 && Event.n.u8Vector == 0xE)
1474 {
1475 Log(("Double fault!\n"));
1476 }
1477#endif
1478
1479 pVCpu->hwaccm.s.Event.fPending = true;
1480 /* Error code present? (redundant) */
1481 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1482 pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1483 else
1484 pVCpu->hwaccm.s.Event.errCode = 0;
1485 }
1486#ifdef VBOX_WITH_STATISTICS
1487 if (exitCode == SVM_EXIT_NPF)
1488 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1489 else
1490 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1491#endif
1492
1493 /* Sync back the TPR if it was changed. */
1494 if (fSyncTPR)
1495 {
1496 if (pVM->hwaccm.s.svm.fTPRPatchingActive)
1497 {
1498 if ((pCtx->msrLSTAR & 0xff) != u8LastTPR)
1499 {
1500 /* Our patch code uses LSTAR for TPR caching. */
1501 rc = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
1502 AssertRC(rc);
1503 }
1504 }
1505 else
1506 {
1507 if ((u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1508 {
1509 rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1510 AssertRC(rc);
1511 }
1512 }
1513 }
1514
1515 /* Deal with the reason of the VM-exit. */
1516 switch (exitCode)
1517 {
1518 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1519 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1520 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1521 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1522 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1523 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1524 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1525 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1526 {
1527 /* Pending trap. */
1528 SVM_EVENT Event;
1529 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1530
1531 Log2(("Hardware/software interrupt %d\n", vector));
1532 switch (vector)
1533 {
1534 case X86_XCPT_DB:
1535 {
1536 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1537
1538 /* Note that we don't support guest and host-initiated debugging at the same time. */
1539 Assert(DBGFIsStepping(pVCpu) || CPUMIsHyperDebugStateActive(pVCpu));
1540
1541 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1542 if (rc == VINF_EM_RAW_GUEST_TRAP)
1543 {
1544 Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1545
1546 /* Reinject the exception. */
1547 Event.au64[0] = 0;
1548 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1549 Event.n.u1Valid = 1;
1550 Event.n.u8Vector = X86_XCPT_DB;
1551
1552 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1553
1554 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1555 goto ResumeExecution;
1556 }
1557 /* Return to ring 3 to deal with the debug exit code. */
1558 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
1559 break;
1560 }
1561
1562 case X86_XCPT_NM:
1563 {
1564 Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1565
1566 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1567 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1568 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1569 if (rc == VINF_SUCCESS)
1570 {
1571 Assert(CPUMIsGuestFPUStateActive(pVCpu));
1572 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1573
1574 /* Continue execution. */
1575 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1576 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1577
1578 goto ResumeExecution;
1579 }
1580
1581 Log(("Forward #NM fault to the guest\n"));
1582 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1583
1584 Event.au64[0] = 0;
1585 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1586 Event.n.u1Valid = 1;
1587 Event.n.u8Vector = X86_XCPT_NM;
1588
1589 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1590 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1591 goto ResumeExecution;
1592 }
1593
1594 case X86_XCPT_PF: /* Page fault */
1595 {
1596 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1597 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1598
1599#ifdef DEBUG
1600 if (pVM->hwaccm.s.fNestedPaging)
1601 { /* A genuine pagefault.
1602 * Forward the trap to the guest by injecting the exception and resuming execution.
1603 */
1604 Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1605 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1606
1607 /* Now we must update CR2. */
1608 pCtx->cr2 = uFaultAddress;
1609
1610 Event.au64[0] = 0;
1611 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1612 Event.n.u1Valid = 1;
1613 Event.n.u8Vector = X86_XCPT_PF;
1614 Event.n.u1ErrorCodeValid = 1;
1615 Event.n.u32ErrorCode = errCode;
1616
1617 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1618
1619 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1620 goto ResumeExecution;
1621 }
1622#endif
1623 Assert(!pVM->hwaccm.s.fNestedPaging);
1624
1625#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1626 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1627 if ( (uFaultAddress & 0xfff) == 0x080
1628 && pVM->hwaccm.s.fHasIoApic
1629 && !(errCode & X86_TRAP_PF_P) /* not present */
1630 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1631 && !CPUMIsGuestInLongModeEx(pCtx)
1632 && pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches))
1633 {
1634 RTGCPHYS GCPhysApicBase, GCPhys;
1635 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1636 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1637
1638 rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1639 if ( rc == VINF_SUCCESS
1640 && GCPhys == GCPhysApicBase)
1641 {
1642 /* Only attempt to patch the instruction once. */
1643 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1644 if (!pPatch)
1645 {
1646 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1647 break;
1648 }
1649 }
1650 }
1651#endif
1652
1653 Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1654 /* Exit qualification contains the linear address of the page fault. */
1655 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1656 TRPMSetErrorCode(pVCpu, errCode);
1657 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1658
1659 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1660 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1661 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1662 if (rc == VINF_SUCCESS)
1663 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1664 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1665 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1666
1667 TRPMResetTrap(pVCpu);
1668
1669 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1670 goto ResumeExecution;
1671 }
1672 else
1673 if (rc == VINF_EM_RAW_GUEST_TRAP)
1674 { /* A genuine pagefault.
1675 * Forward the trap to the guest by injecting the exception and resuming execution.
1676 */
1677 Log2(("Forward page fault to the guest\n"));
1678 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1679 /* The error code might have been changed. */
1680 errCode = TRPMGetErrorCode(pVCpu);
1681
1682 TRPMResetTrap(pVCpu);
1683
1684 /* Now we must update CR2. */
1685 pCtx->cr2 = uFaultAddress;
1686
1687 Event.au64[0] = 0;
1688 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1689 Event.n.u1Valid = 1;
1690 Event.n.u8Vector = X86_XCPT_PF;
1691 Event.n.u1ErrorCodeValid = 1;
1692 Event.n.u32ErrorCode = errCode;
1693
1694 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1695
1696 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1697 goto ResumeExecution;
1698 }
1699#ifdef VBOX_STRICT
1700 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1701 LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1702#endif
1703 /* Need to go back to the recompiler to emulate the instruction. */
1704 TRPMResetTrap(pVCpu);
1705 break;
1706 }
1707
1708 case X86_XCPT_MF: /* Floating point exception. */
1709 {
1710 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1711 if (!(pCtx->cr0 & X86_CR0_NE))
1712 {
1713 /* old style FPU error reporting needs some extra work. */
1714 /** @todo don't fall back to the recompiler, but do it manually. */
1715 rc = VINF_EM_RAW_EMULATE_INSTR;
1716 break;
1717 }
1718 Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1719
1720 Event.au64[0] = 0;
1721 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1722 Event.n.u1Valid = 1;
1723 Event.n.u8Vector = X86_XCPT_MF;
1724
1725 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1726
1727 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1728 goto ResumeExecution;
1729 }
1730
1731#ifdef VBOX_STRICT
1732 case X86_XCPT_GP: /* General protection failure exception.*/
1733 case X86_XCPT_UD: /* Unknown opcode exception. */
1734 case X86_XCPT_DE: /* Divide error. */
1735 case X86_XCPT_SS: /* Stack segment exception. */
1736 case X86_XCPT_NP: /* Segment not present exception. */
1737 {
1738 Event.au64[0] = 0;
1739 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1740 Event.n.u1Valid = 1;
1741 Event.n.u8Vector = vector;
1742
1743 switch(vector)
1744 {
1745 case X86_XCPT_GP:
1746 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1747 Event.n.u1ErrorCodeValid = 1;
1748 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1749 break;
1750 case X86_XCPT_DE:
1751 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1752 break;
1753 case X86_XCPT_UD:
1754 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1755 break;
1756 case X86_XCPT_SS:
1757 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1758 Event.n.u1ErrorCodeValid = 1;
1759 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1760 break;
1761 case X86_XCPT_NP:
1762 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1763 Event.n.u1ErrorCodeValid = 1;
1764 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1765 break;
1766 }
1767 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1768 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1769
1770 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1771 goto ResumeExecution;
1772 }
1773#endif
1774 default:
1775 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1776 rc = VERR_EM_INTERNAL_ERROR;
1777 break;
1778
1779 } /* switch (vector) */
1780 break;
1781 }
1782
1783 case SVM_EXIT_NPF:
1784 {
1785 /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1786 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1787 RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1788 PGMMODE enmShwPagingMode;
1789
1790 Assert(pVM->hwaccm.s.fNestedPaging);
1791 LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1792
1793#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1794 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1795 if ( (uFaultAddress & 0xfff) == 0x080
1796 && pVM->hwaccm.s.fHasIoApic
1797 && !(errCode & X86_TRAP_PF_P) /* not present */
1798 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1799 && !CPUMIsGuestInLongModeEx(pCtx)
1800 && pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches))
1801 {
1802 RTGCPHYS GCPhysApicBase;
1803 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1804 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1805
1806 if (uFaultAddress == GCPhysApicBase + 0x80)
1807 {
1808 /* Only attempt to patch the instruction once. */
1809 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1810 if (!pPatch)
1811 {
1812 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1813 break;
1814 }
1815 }
1816 }
1817#endif
1818
1819 /* Exit qualification contains the linear address of the page fault. */
1820 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1821 TRPMSetErrorCode(pVCpu, errCode);
1822 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1823
1824 /* Handle the pagefault trap for the nested shadow table. */
1825#if HC_ARCH_BITS == 32
1826 if (CPUMIsGuestInLongModeEx(pCtx))
1827 enmShwPagingMode = PGMMODE_AMD64_NX;
1828 else
1829#endif
1830 enmShwPagingMode = PGMGetHostMode(pVM);
1831
1832 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1833 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1834 if (rc == VINF_SUCCESS)
1835 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1836 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1837 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1838
1839 TRPMResetTrap(pVCpu);
1840
1841 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1842 goto ResumeExecution;
1843 }
1844
1845#ifdef VBOX_STRICT
1846 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1847 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1848#endif
1849 /* Need to go back to the recompiler to emulate the instruction. */
1850 TRPMResetTrap(pVCpu);
1851 break;
1852 }
1853
1854 case SVM_EXIT_VINTR:
1855 /* A virtual interrupt is about to be delivered, which means IF=1. */
1856 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1857 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1858 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1859 goto ResumeExecution;
1860
1861 case SVM_EXIT_FERR_FREEZE:
1862 case SVM_EXIT_INTR:
1863 case SVM_EXIT_NMI:
1864 case SVM_EXIT_SMI:
1865 case SVM_EXIT_INIT:
1866 /* External interrupt; leave to allow it to be dispatched again. */
1867 rc = VINF_EM_RAW_INTERRUPT;
1868 break;
1869
1870 case SVM_EXIT_WBINVD:
1871 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1872 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1873 /* Skip instruction and continue directly. */
1874 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1875 /* Continue execution.*/
1876 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1877 goto ResumeExecution;
1878
1879 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1880 {
1881 Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1882 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1883 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1884 if (rc == VINF_SUCCESS)
1885 {
1886 /* Update EIP and continue execution. */
1887 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1888 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1889 goto ResumeExecution;
1890 }
1891 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1892 rc = VINF_EM_RAW_EMULATE_INSTR;
1893 break;
1894 }
1895
1896 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1897 {
1898 Log2(("SVM: Rdtsc\n"));
1899 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1900 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1901 if (rc == VINF_SUCCESS)
1902 {
1903 /* Update EIP and continue execution. */
1904 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1905 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1906 goto ResumeExecution;
1907 }
1908 rc = VINF_EM_RAW_EMULATE_INSTR;
1909 break;
1910 }
1911
1912 case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1913 {
1914 Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1915 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1916 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1917 if (rc == VINF_SUCCESS)
1918 {
1919 /* Update EIP and continue execution. */
1920 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1921 goto ResumeExecution;
1922 }
1923 rc = VINF_EM_RAW_EMULATE_INSTR;
1924 break;
1925 }
1926
1927 case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1928 {
1929 Log2(("SVM: Rdtscp\n"));
1930 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1931 rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
1932 if (rc == VINF_SUCCESS)
1933 {
1934 /* Update EIP and continue execution. */
1935 pCtx->rip += 3; /* Note! hardcoded opcode size! */
1936 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1937 goto ResumeExecution;
1938 }
1939 AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
1940 rc = VINF_EM_RAW_EMULATE_INSTR;
1941 break;
1942 }
1943
1944 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1945 {
1946 Log2(("SVM: invlpg\n"));
1947 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
1948
1949 Assert(!pVM->hwaccm.s.fNestedPaging);
1950
1951 /* Truly a pita. Why can't SVM give the same information as VT-x? */
1952 rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1953 if (rc == VINF_SUCCESS)
1954 {
1955 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
1956 goto ResumeExecution; /* eip already updated */
1957 }
1958 break;
1959 }
1960
1961 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1962 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1963 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1964 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1965 {
1966 uint32_t cbSize;
1967
1968 Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1969 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
1970 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
1971
1972 switch (exitCode - SVM_EXIT_WRITE_CR0)
1973 {
1974 case 0:
1975 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1976 break;
1977 case 2:
1978 break;
1979 case 3:
1980 Assert(!pVM->hwaccm.s.fNestedPaging);
1981 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1982 break;
1983 case 4:
1984 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1985 break;
1986 case 8:
1987 break;
1988 default:
1989 AssertFailed();
1990 }
1991 /* Check if a sync operation is pending. */
1992 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1993 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1994 {
1995 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1996 AssertRC(rc);
1997
1998 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBCRxChange);
1999
2000 /* Must be set by PGMSyncCR3 */
2001 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || PGMGetGuestMode(pVCpu) <= PGMMODE_PROTECTED || pVCpu->hwaccm.s.fForceTLBFlush,
2002 ("rc=%Rrc mode=%d fForceTLBFlush=%RTbool\n", rc, PGMGetGuestMode(pVCpu), pVCpu->hwaccm.s.fForceTLBFlush));
2003 }
2004 if (rc == VINF_SUCCESS)
2005 {
2006 /* EIP has been updated already. */
2007
2008 /* Only resume if successful. */
2009 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2010 goto ResumeExecution;
2011 }
2012 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2013 break;
2014 }
2015
2016 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
2017 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
2018 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
2019 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
2020 {
2021 uint32_t cbSize;
2022
2023 Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
2024 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
2025 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2026 if (rc == VINF_SUCCESS)
2027 {
2028 /* EIP has been updated already. */
2029
2030 /* Only resume if successful. */
2031 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2032 goto ResumeExecution;
2033 }
2034 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2035 break;
2036 }
2037
2038 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2039 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
2040 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2041 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2042 {
2043 uint32_t cbSize;
2044
2045 Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
2046 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2047
2048 if ( !DBGFIsStepping(pVCpu)
2049 && !CPUMIsHyperDebugStateActive(pVCpu))
2050 {
2051 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2052
2053 /* Disable drx move intercepts. */
2054 pVMCB->ctrl.u16InterceptRdDRx = 0;
2055 pVMCB->ctrl.u16InterceptWrDRx = 0;
2056
2057 /* Save the host and load the guest debug state. */
2058 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2059 AssertRC(rc);
2060
2061 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2062 goto ResumeExecution;
2063 }
2064
2065 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2066 if (rc == VINF_SUCCESS)
2067 {
2068 /* EIP has been updated already. */
2069 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2070
2071 /* Only resume if successful. */
2072 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2073 goto ResumeExecution;
2074 }
2075 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2076 break;
2077 }
2078
2079 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2080 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2081 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2082 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2083 {
2084 uint32_t cbSize;
2085
2086 Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2087 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2088
2089 if (!DBGFIsStepping(pVCpu))
2090 {
2091 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2092
2093 /* Disable drx move intercepts. */
2094 pVMCB->ctrl.u16InterceptRdDRx = 0;
2095 pVMCB->ctrl.u16InterceptWrDRx = 0;
2096
2097 /* Save the host and load the guest debug state. */
2098 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2099 AssertRC(rc);
2100
2101 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2102 goto ResumeExecution;
2103 }
2104
2105 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2106 if (rc == VINF_SUCCESS)
2107 {
2108 /* EIP has been updated already. */
2109
2110 /* Only resume if successful. */
2111 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2112 goto ResumeExecution;
2113 }
2114 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2115 break;
2116 }
2117
2118 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2119 case SVM_EXIT_IOIO: /* I/O instruction. */
2120 {
2121 SVM_IOIO_EXIT IoExitInfo;
2122 uint32_t uIOSize, uAndVal;
2123
2124 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2125
2126 /** @todo could use a lookup table here */
2127 if (IoExitInfo.n.u1OP8)
2128 {
2129 uIOSize = 1;
2130 uAndVal = 0xff;
2131 }
2132 else
2133 if (IoExitInfo.n.u1OP16)
2134 {
2135 uIOSize = 2;
2136 uAndVal = 0xffff;
2137 }
2138 else
2139 if (IoExitInfo.n.u1OP32)
2140 {
2141 uIOSize = 4;
2142 uAndVal = 0xffffffff;
2143 }
2144 else
2145 {
2146 AssertFailed(); /* should be fatal. */
2147 rc = VINF_EM_RAW_EMULATE_INSTR;
2148 break;
2149 }
2150
2151 if (IoExitInfo.n.u1STR)
2152 {
2153 /* ins/outs */
2154 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2155
2156 /* Disassemble manually to deal with segment prefixes. */
2157 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2158 if (rc == VINF_SUCCESS)
2159 {
2160 if (IoExitInfo.n.u1Type == 0)
2161 {
2162 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2163 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2164 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
2165 }
2166 else
2167 {
2168 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2169 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2170 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
2171 }
2172 }
2173 else
2174 rc = VINF_EM_RAW_EMULATE_INSTR;
2175 }
2176 else
2177 {
2178 /* normal in/out */
2179 Assert(!IoExitInfo.n.u1REP);
2180
2181 if (IoExitInfo.n.u1Type == 0)
2182 {
2183 Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2184 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2185 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
2186 if (rc == VINF_IOM_HC_IOPORT_WRITE)
2187 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2188 }
2189 else
2190 {
2191 uint32_t u32Val = 0;
2192
2193 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2194 rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
2195 if (IOM_SUCCESS(rc))
2196 {
2197 /* Write back to the EAX register. */
2198 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2199 Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2200 }
2201 else
2202 if (rc == VINF_IOM_HC_IOPORT_READ)
2203 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2204 }
2205 }
2206 /*
2207 * Handled the I/O return codes.
2208 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2209 */
2210 if (IOM_SUCCESS(rc))
2211 {
2212 /* Update EIP and continue execution. */
2213 pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2214 if (RT_LIKELY(rc == VINF_SUCCESS))
2215 {
2216 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2217 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2218 {
2219 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2220 for (unsigned i=0;i<4;i++)
2221 {
2222 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2223
2224 if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2225 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2226 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2227 {
2228 SVM_EVENT Event;
2229
2230 Assert(CPUMIsGuestDebugStateActive(pVCpu));
2231
2232 /* Clear all breakpoint status flags and set the one we just hit. */
2233 pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2234 pCtx->dr[6] |= (uint64_t)RT_BIT(i);
2235
2236 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2237 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2238 * the contents have been read.
2239 */
2240 pVMCB->guest.u64DR6 = pCtx->dr[6];
2241
2242 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2243 pCtx->dr[7] &= ~X86_DR7_GD;
2244
2245 /* Paranoia. */
2246 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2247 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2248 pCtx->dr[7] |= 0x400; /* must be one */
2249
2250 pVMCB->guest.u64DR7 = pCtx->dr[7];
2251
2252 /* Inject the exception. */
2253 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2254
2255 Event.au64[0] = 0;
2256 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2257 Event.n.u1Valid = 1;
2258 Event.n.u8Vector = X86_XCPT_DB;
2259
2260 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2261
2262 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2263 goto ResumeExecution;
2264 }
2265 }
2266 }
2267
2268 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2269 goto ResumeExecution;
2270 }
2271 Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
2272 break;
2273 }
2274
2275#ifdef VBOX_STRICT
2276 if (rc == VINF_IOM_HC_IOPORT_READ)
2277 Assert(IoExitInfo.n.u1Type != 0);
2278 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2279 Assert(IoExitInfo.n.u1Type == 0);
2280 else
2281 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
2282#endif
2283 Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2284 break;
2285 }
2286
2287 case SVM_EXIT_HLT:
2288 /** Check if external interrupts are pending; if so, don't switch back. */
2289 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2290 pCtx->rip++; /* skip hlt */
2291 if ( pCtx->eflags.Bits.u1IF
2292 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2293 goto ResumeExecution;
2294
2295 rc = VINF_EM_HALT;
2296 break;
2297
2298 case SVM_EXIT_MWAIT_UNCOND:
2299 Log2(("SVM: mwait\n"));
2300 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2301 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2302 if ( rc == VINF_EM_HALT
2303 || rc == VINF_SUCCESS)
2304 {
2305 /* Update EIP and continue execution. */
2306 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2307
2308 /** Check if external interrupts are pending; if so, don't switch back. */
2309 if ( rc == VINF_SUCCESS
2310 || ( rc == VINF_EM_HALT
2311 && pCtx->eflags.Bits.u1IF
2312 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2313 )
2314 goto ResumeExecution;
2315 }
2316 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
2317 break;
2318
2319 case SVM_EXIT_VMMCALL:
2320 rc = svmR0EmulateTprVMMCall(pVM, pVCpu, pCtx);
2321 if (rc == VINF_SUCCESS)
2322 {
2323 goto ResumeExecution; /* rip already updated. */
2324 }
2325 /* no break */
2326
2327 case SVM_EXIT_RSM:
2328 case SVM_EXIT_INVLPGA:
2329 case SVM_EXIT_VMRUN:
2330 case SVM_EXIT_VMLOAD:
2331 case SVM_EXIT_VMSAVE:
2332 case SVM_EXIT_STGI:
2333 case SVM_EXIT_CLGI:
2334 case SVM_EXIT_SKINIT:
2335 {
2336 /* Unsupported instructions. */
2337 SVM_EVENT Event;
2338
2339 Event.au64[0] = 0;
2340 Event.n.u3Type = SVM_EVENT_EXCEPTION;
2341 Event.n.u1Valid = 1;
2342 Event.n.u8Vector = X86_XCPT_UD;
2343
2344 Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2345 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2346
2347 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2348 goto ResumeExecution;
2349 }
2350
2351 /* Emulate in ring 3. */
2352 case SVM_EXIT_MSR:
2353 {
2354 uint32_t cbSize;
2355
2356 /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
2357 if ( pVM->hwaccm.s.svm.fTPRPatchingActive
2358 && pCtx->ecx == MSR_K8_LSTAR
2359 && pVMCB->ctrl.u64ExitInfo1 == 1 /* wrmsr */)
2360 {
2361 if ((pCtx->eax & 0xff) != u8LastTPR)
2362 {
2363 Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
2364
2365 /* Our patch code uses LSTAR for TPR caching. */
2366 rc = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
2367 AssertRC(rc);
2368 }
2369
2370 /* Skip the instruction and continue. */
2371 pCtx->rip += 2; /* wrmsr = [0F 30] */
2372
2373 /* Only resume if successful. */
2374 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2375 goto ResumeExecution;
2376 }
2377
2378 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2379 STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2380 Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2381 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2382 if (rc == VINF_SUCCESS)
2383 {
2384 /* EIP has been updated already. */
2385
2386 /* Only resume if successful. */
2387 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2388 goto ResumeExecution;
2389 }
2390 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2391 break;
2392 }
2393
2394 case SVM_EXIT_MONITOR:
2395 case SVM_EXIT_PAUSE:
2396 case SVM_EXIT_MWAIT_ARMED:
2397 case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
2398 rc = VERR_EM_INTERPRETER;
2399 break;
2400
2401 case SVM_EXIT_SHUTDOWN:
2402 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2403 break;
2404
2405 case SVM_EXIT_IDTR_READ:
2406 case SVM_EXIT_GDTR_READ:
2407 case SVM_EXIT_LDTR_READ:
2408 case SVM_EXIT_TR_READ:
2409 case SVM_EXIT_IDTR_WRITE:
2410 case SVM_EXIT_GDTR_WRITE:
2411 case SVM_EXIT_LDTR_WRITE:
2412 case SVM_EXIT_TR_WRITE:
2413 case SVM_EXIT_CR0_SEL_WRITE:
2414 default:
2415 /* Unexpected exit codes. */
2416 rc = VERR_EM_INTERNAL_ERROR;
2417 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2418 break;
2419 }
2420
2421end:
2422
2423 /* Signal changes for the recompiler. */
2424 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2425
2426 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2427 if (exitCode == SVM_EXIT_INTR)
2428 {
2429 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2430 /* On the next entry we'll only sync the host context. */
2431 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2432 }
2433 else
2434 {
2435 /* On the next entry we'll sync everything. */
2436 /** @todo we can do better than this */
2437 /* Not in the VINF_PGM_CHANGE_MODE though! */
2438 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2439 }
2440
2441 /* translate into a less severe return code */
2442 if (rc == VERR_EM_INTERPRETER)
2443 rc = VINF_EM_RAW_EMULATE_INSTR;
2444
2445 /* Just set the correct state here instead of trying to catch every goto above. */
2446 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2447
2448#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2449 /* Restore interrupts if we exitted after disabling them. */
2450 if (uOldEFlags != ~(RTCCUINTREG)0)
2451 ASMSetFlags(uOldEFlags);
2452#endif
2453
2454 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2455 return rc;
2456}
2457
2458/**
2459 * Emulate simple mov tpr instruction
2460 *
2461 * @returns VBox status code.
2462 * @param pVM The VM to operate on.
2463 * @param pVCpu The VM CPU to operate on.
2464 * @param pCtx CPU context
2465 */
2466static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2467{
2468 int rc;
2469
2470 LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2471
2472 while (true)
2473 {
2474 bool fPending;
2475 uint8_t u8Tpr;
2476
2477 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
2478 if (!pPatch)
2479 break;
2480
2481 switch(pPatch->enmType)
2482 {
2483 case HWACCMTPRINSTR_READ:
2484 /* TPR caching in CR8 */
2485 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2486 AssertRC(rc);
2487
2488 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2489 AssertRC(rc);
2490
2491 LogFlow(("Emulated read successfully\n"));
2492 pCtx->rip += pPatch->cbOp;
2493 break;
2494
2495 case HWACCMTPRINSTR_WRITE_REG:
2496 case HWACCMTPRINSTR_WRITE_IMM:
2497 /* Fetch the new TPR value */
2498 if (pPatch->enmType == HWACCMTPRINSTR_WRITE_REG)
2499 {
2500 uint32_t val;
2501
2502 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2503 AssertRC(rc);
2504 u8Tpr = val;
2505 }
2506 else
2507 u8Tpr = (uint8_t)pPatch->uSrcOperand;
2508
2509 rc = PDMApicSetTPR(pVCpu, u8Tpr);
2510 AssertRC(rc);
2511 LogFlow(("Emulated write successfully\n"));
2512 pCtx->rip += pPatch->cbOp;
2513 break;
2514 default:
2515 AssertFailedReturn(VERR_INTERNAL_ERROR);
2516 }
2517 }
2518 return VINF_SUCCESS;
2519}
2520
2521
2522/**
2523 * Enters the AMD-V session
2524 *
2525 * @returns VBox status code.
2526 * @param pVM The VM to operate on.
2527 * @param pVCpu The VM CPU to operate on.
2528 * @param pCpu CPU info struct
2529 */
2530VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2531{
2532 Assert(pVM->hwaccm.s.svm.fSupported);
2533
2534 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2535 pVCpu->hwaccm.s.fResumeVM = false;
2536
2537 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2538 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
2539
2540 return VINF_SUCCESS;
2541}
2542
2543
2544/**
2545 * Leaves the AMD-V session
2546 *
2547 * @returns VBox status code.
2548 * @param pVM The VM to operate on.
2549 * @param pVCpu The VM CPU to operate on.
2550 * @param pCtx CPU context
2551 */
2552VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2553{
2554 SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2555
2556 Assert(pVM->hwaccm.s.svm.fSupported);
2557
2558#ifdef DEBUG
2559 if (CPUMIsHyperDebugStateActive(pVCpu))
2560 {
2561 CPUMR0LoadHostDebugState(pVM, pVCpu);
2562 }
2563 else
2564#endif
2565 /* Save the guest debug state if necessary. */
2566 if (CPUMIsGuestDebugStateActive(pVCpu))
2567 {
2568 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2569
2570 /* Intercept all DRx reads and writes again. Changed later on. */
2571 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2572 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2573
2574 /* Resync the debug registers the next time. */
2575 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2576 }
2577 else
2578 Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2579
2580 return VINF_SUCCESS;
2581}
2582
2583
2584static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2585{
2586 OP_PARAMVAL param1;
2587 RTGCPTR addr;
2588
2589 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2590 if(RT_FAILURE(rc))
2591 return VERR_EM_INTERPRETER;
2592
2593 switch(param1.type)
2594 {
2595 case PARMTYPE_IMMEDIATE:
2596 case PARMTYPE_ADDRESS:
2597 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
2598 return VERR_EM_INTERPRETER;
2599 addr = param1.val.val64;
2600 break;
2601
2602 default:
2603 return VERR_EM_INTERPRETER;
2604 }
2605
2606 /** @todo is addr always a flat linear address or ds based
2607 * (in absence of segment override prefixes)????
2608 */
2609 rc = PGMInvalidatePage(pVCpu, addr);
2610 if (RT_SUCCESS(rc))
2611 {
2612 /* Manually invalidate the page for the VM's TLB. */
2613 Log(("SVMR0InvlpgA %RGv ASID=%d\n", addr, uASID));
2614 SVMR0InvlpgA(addr, uASID);
2615 return VINF_SUCCESS;
2616 }
2617 AssertRC(rc);
2618 return rc;
2619}
2620
2621/**
2622 * Interprets INVLPG
2623 *
2624 * @returns VBox status code.
2625 * @retval VINF_* Scheduling instructions.
2626 * @retval VERR_EM_INTERPRETER Something we can't cope with.
2627 * @retval VERR_* Fatal errors.
2628 *
2629 * @param pVM The VM handle.
2630 * @param pRegFrame The register frame.
2631 * @param ASID Tagged TLB id for the guest
2632 *
2633 * Updates the EIP if an instruction was executed successfully.
2634 */
2635static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2636{
2637 /*
2638 * Only allow 32 & 64 bits code.
2639 */
2640 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2641 if (enmMode != CPUMODE_16BIT)
2642 {
2643 RTGCPTR pbCode;
2644 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2645 if (RT_SUCCESS(rc))
2646 {
2647 uint32_t cbOp;
2648 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2649
2650 pDis->mode = enmMode;
2651 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2652 Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
2653 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2654 {
2655 Assert(cbOp == pDis->opsize);
2656 rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2657 if (RT_SUCCESS(rc))
2658 {
2659 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2660 }
2661 return rc;
2662 }
2663 }
2664 }
2665 return VERR_EM_INTERPRETER;
2666}
2667
2668
2669/**
2670 * Invalidates a guest page
2671 *
2672 * @returns VBox status code.
2673 * @param pVM The VM to operate on.
2674 * @param pVCpu The VM CPU to operate on.
2675 * @param GCVirt Page to invalidate
2676 */
2677VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2678{
2679 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
2680
2681 /* Skip it if a TLB flush is already pending. */
2682 if (!fFlushPending)
2683 {
2684 SVM_VMCB *pVMCB;
2685
2686 Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2687 AssertReturn(pVM, VERR_INVALID_PARAMETER);
2688 Assert(pVM->hwaccm.s.svm.fSupported);
2689
2690 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2691 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2692
2693#if HC_ARCH_BITS == 32
2694 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2695 if (CPUMIsGuestInLongMode(pVCpu))
2696 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2697 else
2698#endif
2699 SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2700 }
2701 return VINF_SUCCESS;
2702}
2703
2704
2705#if 0 /* obsolete, but left here for clarification. */
2706/**
2707 * Invalidates a guest page by physical address
2708 *
2709 * @returns VBox status code.
2710 * @param pVM The VM to operate on.
2711 * @param pVCpu The VM CPU to operate on.
2712 * @param GCPhys Page to invalidate
2713 */
2714VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2715{
2716 Assert(pVM->hwaccm.s.fNestedPaging);
2717 /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2718 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2719 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2720 return VINF_SUCCESS;
2721}
2722#endif
2723
2724#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2725/**
2726 * Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2727 *
2728 * @returns VBox status code.
2729 * @param pVMCBHostPhys Physical address of host VMCB.
2730 * @param pVMCBPhys Physical address of the VMCB.
2731 * @param pCtx Guest context.
2732 * @param pVM The VM to operate on.
2733 * @param pVCpu The VMCPU to operate on.
2734 */
2735DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2736{
2737 uint32_t aParam[4];
2738
2739 aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2740 aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2741 aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2742 aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2743
2744 return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2745}
2746
2747/**
2748 * Executes the specified handler in 64 mode
2749 *
2750 * @returns VBox status code.
2751 * @param pVM The VM to operate on.
2752 * @param pVCpu The VMCPU to operate on.
2753 * @param pCtx Guest context
2754 * @param pfnHandler RC handler
2755 * @param cbParam Number of parameters
2756 * @param paParam Array of 32 bits parameters
2757 */
2758VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2759{
2760 int rc;
2761 RTHCUINTREG uOldEFlags;
2762
2763 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
2764 AssertReturn(pVM->cCPUs == 1, VERR_TOO_MANY_CPUS);
2765 Assert(pfnHandler);
2766
2767 uOldEFlags = ASMIntDisableFlags();
2768
2769 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
2770 CPUMSetHyperEIP(pVCpu, pfnHandler);
2771 for (int i=(int)cbParam-1;i>=0;i--)
2772 CPUMPushHyper(pVCpu, paParam[i]);
2773
2774 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2775 /* Call switcher. */
2776 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
2777 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2778
2779 ASMSetFlags(uOldEFlags);
2780 return rc;
2781}
2782
2783#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
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