VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 32264

Last change on this file since 32264 was 31786, checked in by vboxsync, 14 years ago

PGM: AMD-V + NP optimization (IOM sometimes makes use of uErr).
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File size: 114.6 KB
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1/* $Id: HWSVMR0.cpp 31786 2010-08-19 12:18:48Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HWACCM
22#include <VBox/hwaccm.h>
23#include <VBox/pgm.h>
24#include <VBox/selm.h>
25#include <VBox/iom.h>
26#include <VBox/dbgf.h>
27#include <VBox/tm.h>
28#include <VBox/pdmapi.h>
29#include "HWACCMInternal.h"
30#include <VBox/vm.h>
31#include <VBox/x86.h>
32#include <VBox/hwacc_svm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/dis.h>
36#include <VBox/disopcode.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/asm-amd64-x86.h>
41#include <iprt/cpuset.h>
42#include <iprt/mp.h>
43#include <iprt/time.h>
44#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
45# include <iprt/thread.h>
46#endif
47#include "HWSVMR0.h"
48
49/*******************************************************************************
50* Internal Functions *
51*******************************************************************************/
52static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
53static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
54static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
55
56/*******************************************************************************
57* Global Variables *
58*******************************************************************************/
59
60/**
61 * Sets up and activates AMD-V on the current CPU
62 *
63 * @returns VBox status code.
64 * @param pCpu CPU info struct
65 * @param pVM The VM to operate on. (can be NULL after a resume!!)
66 * @param pvPageCpu Pointer to the global cpu page
67 * @param pPageCpuPhys Physical address of the global cpu page
68 */
69VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
70{
71 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
72 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
73
74 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
75 uint64_t val = ASMRdMsr(MSR_K6_EFER);
76 if (val & MSR_K6_EFER_SVME)
77 {
78 /* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active, then we blindly use AMD-V. */
79 if ( pVM
80 && pVM->hwaccm.s.svm.fIgnoreInUseError)
81 {
82 pCpu->fIgnoreAMDVInUseError = true;
83 }
84
85 if (!pCpu->fIgnoreAMDVInUseError)
86 return VERR_SVM_IN_USE;
87 }
88
89 /* Turn on AMD-V in the EFER MSR. */
90 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
91
92 /* Write the physical page address where the CPU will store the host state while executing the VM. */
93 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
94
95 return VINF_SUCCESS;
96}
97
98/**
99 * Deactivates AMD-V on the current CPU
100 *
101 * @returns VBox status code.
102 * @param pCpu CPU info struct
103 * @param pvPageCpu Pointer to the global cpu page
104 * @param pPageCpuPhys Physical address of the global cpu page
105 */
106VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
107{
108 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
109 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
110
111 /* Turn off AMD-V in the EFER MSR. */
112 uint64_t val = ASMRdMsr(MSR_K6_EFER);
113 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
114
115 /* Invalidate host state physical address. */
116 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
117
118 return VINF_SUCCESS;
119}
120
121/**
122 * Does Ring-0 per VM AMD-V init.
123 *
124 * @returns VBox status code.
125 * @param pVM The VM to operate on.
126 */
127VMMR0DECL(int) SVMR0InitVM(PVM pVM)
128{
129 int rc;
130
131 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
132
133 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
134 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
135 if (RT_FAILURE(rc))
136 return rc;
137
138 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
139 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
140 /* Set all bits to intercept all IO accesses. */
141 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
142
143 /* Erratum 170 which requires a forced TLB flush for each world switch:
144 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
145 *
146 * All BH-G1/2 and DH-G1/2 models include a fix:
147 * Athlon X2: 0x6b 1/2
148 * 0x68 1/2
149 * Athlon 64: 0x7f 1
150 * 0x6f 2
151 * Sempron: 0x7f 1/2
152 * 0x6f 2
153 * 0x6c 2
154 * 0x7c 2
155 * Turion 64: 0x68 2
156 *
157 */
158 uint32_t u32Dummy;
159 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
160 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
161 u32BaseFamily= (u32Version >> 8) & 0xf;
162 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
163 u32Model = ((u32Version >> 4) & 0xf);
164 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
165 u32Stepping = u32Version & 0xf;
166 if ( u32Family == 0xf
167 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
168 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
169 {
170 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
171 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
172 }
173
174 /* Allocate VMCBs for all guest CPUs. */
175 for (VMCPUID i = 0; i < pVM->cCpus; i++)
176 {
177 PVMCPU pVCpu = &pVM->aCpus[i];
178
179 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
180 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
181 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
182
183 /* Allocate one page for the host context */
184 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
185 if (RT_FAILURE(rc))
186 return rc;
187
188 pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
189 pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
190 Assert(pVCpu->hwaccm.s.svm.pVMCBHostPhys < _4G);
191 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
192
193 /* Allocate one page for the VM control block (VMCB). */
194 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
195 if (RT_FAILURE(rc))
196 return rc;
197
198 pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
199 pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
200 Assert(pVCpu->hwaccm.s.svm.pVMCBPhys < _4G);
201 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
202
203 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
204 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 pVCpu->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);
209 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
210 /* Set all bits to intercept all MSR accesses. */
211 ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
212 }
213
214 return VINF_SUCCESS;
215}
216
217/**
218 * Does Ring-0 per VM AMD-V termination.
219 *
220 * @returns VBox status code.
221 * @param pVM The VM to operate on.
222 */
223VMMR0DECL(int) SVMR0TermVM(PVM pVM)
224{
225 for (VMCPUID i = 0; i < pVM->cCpus; i++)
226 {
227 PVMCPU pVCpu = &pVM->aCpus[i];
228
229 if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
230 {
231 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
232 pVCpu->hwaccm.s.svm.pVMCBHost = 0;
233 pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
234 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
235 }
236
237 if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
238 {
239 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
240 pVCpu->hwaccm.s.svm.pVMCB = 0;
241 pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
242 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
243 }
244 if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
245 {
246 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);
247 pVCpu->hwaccm.s.svm.pMSRBitmap = 0;
248 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = 0;
249 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
250 }
251 }
252 if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
253 {
254 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
255 pVM->hwaccm.s.svm.pIOBitmap = 0;
256 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
257 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
258 }
259 return VINF_SUCCESS;
260}
261
262/**
263 * Sets up AMD-V for the specified VM
264 *
265 * @returns VBox status code.
266 * @param pVM The VM to operate on.
267 */
268VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
269{
270 int rc = VINF_SUCCESS;
271
272 AssertReturn(pVM, VERR_INVALID_PARAMETER);
273
274 Assert(pVM->hwaccm.s.svm.fSupported);
275
276 for (VMCPUID i = 0; i < pVM->cCpus; i++)
277 {
278 PVMCPU pVCpu = &pVM->aCpus[i];
279 SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
280
281 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
282
283 /* Program the control fields. Most of them never have to be changed again. */
284 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
285 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
286 if (!pVM->hwaccm.s.fNestedPaging)
287 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
288 else
289 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
290
291 /*
292 * CR0/3/4 writes must be intercepted for obvious reasons.
293 */
294 if (!pVM->hwaccm.s.fNestedPaging)
295 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
296 else
297 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4);
298
299 /* Intercept all DRx reads and writes by default. Changed later on. */
300 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
301 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
302
303 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
304 * All breakpoints are automatically cleared when the VM exits.
305 */
306
307 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
308#ifndef DEBUG
309 if (pVM->hwaccm.s.fNestedPaging)
310 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
311#endif
312
313 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
314 | SVM_CTRL1_INTERCEPT_VINTR
315 | SVM_CTRL1_INTERCEPT_NMI
316 | SVM_CTRL1_INTERCEPT_SMI
317 | SVM_CTRL1_INTERCEPT_INIT
318 | SVM_CTRL1_INTERCEPT_RDPMC
319 | SVM_CTRL1_INTERCEPT_CPUID
320 | SVM_CTRL1_INTERCEPT_RSM
321 | SVM_CTRL1_INTERCEPT_HLT
322 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
323 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
324 | SVM_CTRL1_INTERCEPT_INVLPG
325 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
326 | SVM_CTRL1_INTERCEPT_TASK_SWITCH
327 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
328 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
329 ;
330 /* With nested paging we don't care about invlpg anymore. */
331 if (pVM->hwaccm.s.fNestedPaging)
332 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
333
334 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
335 | SVM_CTRL2_INTERCEPT_VMMCALL
336 | SVM_CTRL2_INTERCEPT_VMLOAD
337 | SVM_CTRL2_INTERCEPT_VMSAVE
338 | SVM_CTRL2_INTERCEPT_STGI
339 | SVM_CTRL2_INTERCEPT_CLGI
340 | SVM_CTRL2_INTERCEPT_SKINIT
341 | SVM_CTRL2_INTERCEPT_WBINVD
342 | SVM_CTRL2_INTERCEPT_MONITOR
343 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
344 ;
345 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
346 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
347 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
348
349 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
350 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
351 /* Ignore the priority in the TPR; just deliver it when we tell it to. */
352 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
353
354 /* Set IO and MSR bitmap addresses. */
355 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
356 pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;
357
358 /* No LBR virtualization. */
359 pVMCB->ctrl.u64LBRVirt = 0;
360
361 /** The ASID must start at 1; the host uses 0. */
362 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
363
364 /** Setup the PAT msr (nested paging only) */
365 /* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB, so choose type 6 for all PAT slots. */
366 pVMCB->guest.u64GPAT = 0x0006060606060606ULL;
367
368 /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
369 * to modify them directly.
370 */
371 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
372 svmR0SetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
373 svmR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
374 svmR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
375 svmR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
376 svmR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
377 svmR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
378 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
379 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
380 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
381 }
382
383 return rc;
384}
385
386
387/**
388 * Sets the permission bits for the specified MSR
389 *
390 * @param pVCpu The VMCPU to operate on.
391 * @param ulMSR MSR value
392 * @param fRead Reading allowed/disallowed
393 * @param fWrite Writing allowed/disallowed
394 */
395static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
396{
397 unsigned ulBit;
398 uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.svm.pMSRBitmap;
399
400 if (ulMSR <= 0x00001FFF)
401 {
402 /* Pentium-compatible MSRs */
403 ulBit = ulMSR * 2;
404 }
405 else
406 if ( ulMSR >= 0xC0000000
407 && ulMSR <= 0xC0001FFF)
408 {
409 /* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
410 ulBit = (ulMSR - 0xC0000000) * 2;
411 pMSRBitmap += 0x800;
412 }
413 else
414 if ( ulMSR >= 0xC0010000
415 && ulMSR <= 0xC0011FFF)
416 {
417 /* AMD Seventh and Eighth Generation Processor MSRs */
418 ulBit = (ulMSR - 0xC0001000) * 2;
419 pMSRBitmap += 0x1000;
420 }
421 else
422 {
423 AssertFailed();
424 return;
425 }
426 Assert(ulBit < 16 * 1024 - 1);
427 if (fRead)
428 ASMBitClear(pMSRBitmap, ulBit);
429 else
430 ASMBitSet(pMSRBitmap, ulBit);
431
432 if (fWrite)
433 ASMBitClear(pMSRBitmap, ulBit + 1);
434 else
435 ASMBitSet(pMSRBitmap, ulBit + 1);
436}
437
438/**
439 * Injects an event (trap or external interrupt)
440 *
441 * @param pVCpu The VMCPU to operate on.
442 * @param pVMCB SVM control block
443 * @param pCtx CPU Context
444 * @param pIntInfo SVM interrupt info
445 */
446inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
447{
448#ifdef VBOX_WITH_STATISTICS
449 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
450#endif
451
452#ifdef VBOX_STRICT
453 if (pEvent->n.u8Vector == 0xE)
454 Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
455 else
456 if (pEvent->n.u8Vector < 0x20)
457 Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
458 else
459 {
460 Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
461 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
462 Assert(pCtx->eflags.u32 & X86_EFL_IF);
463 }
464#endif
465
466 /* Set event injection state. */
467 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
468}
469
470
471/**
472 * Checks for pending guest interrupts and injects them
473 *
474 * @returns VBox status code.
475 * @param pVM The VM to operate on.
476 * @param pVCpu The VM CPU to operate on.
477 * @param pVMCB SVM control block
478 * @param pCtx CPU Context
479 */
480static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
481{
482 int rc;
483
484 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
485 if (pVCpu->hwaccm.s.Event.fPending)
486 {
487 SVM_EVENT Event;
488
489 Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
490 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
491 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
492 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
493
494 pVCpu->hwaccm.s.Event.fPending = false;
495 return VINF_SUCCESS;
496 }
497
498 /* If an active trap is already pending, then we must forward it first! */
499 if (!TRPMHasTrap(pVCpu))
500 {
501 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
502 {
503 SVM_EVENT Event;
504
505 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
506 Event.n.u8Vector = X86_XCPT_NMI;
507 Event.n.u1Valid = 1;
508 Event.n.u32ErrorCode = 0;
509 Event.n.u3Type = SVM_EVENT_NMI;
510
511 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
512 return VINF_SUCCESS;
513 }
514
515 /* @todo SMI interrupts. */
516
517 /* When external interrupts are pending, we should exit the VM when IF is set. */
518 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
519 {
520 if ( !(pCtx->eflags.u32 & X86_EFL_IF)
521 || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
522 {
523 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
524 {
525 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
526 LogFlow(("Enable irq window exit!\n"));
527 else
528 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
529
530 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
531 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
532 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
533 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
534 }
535 }
536 else
537 {
538 uint8_t u8Interrupt;
539
540 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
541 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
542 if (RT_SUCCESS(rc))
543 {
544 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
545 AssertRC(rc);
546 }
547 else
548 {
549 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
550 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
551 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
552 /* Just continue */
553 }
554 }
555 }
556 }
557
558#ifdef VBOX_STRICT
559 if (TRPMHasTrap(pVCpu))
560 {
561 uint8_t u8Vector;
562 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
563 AssertRC(rc);
564 }
565#endif
566
567 if ( (pCtx->eflags.u32 & X86_EFL_IF)
568 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
569 && TRPMHasTrap(pVCpu)
570 )
571 {
572 uint8_t u8Vector;
573 TRPMEVENT enmType;
574 SVM_EVENT Event;
575 RTGCUINT u32ErrorCode;
576
577 Event.au64[0] = 0;
578
579 /* If a new event is pending, then dispatch it now. */
580 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
581 AssertRC(rc);
582 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
583 Assert(enmType != TRPM_SOFTWARE_INT);
584
585 /* Clear the pending trap. */
586 rc = TRPMResetTrap(pVCpu);
587 AssertRC(rc);
588
589 Event.n.u8Vector = u8Vector;
590 Event.n.u1Valid = 1;
591 Event.n.u32ErrorCode = u32ErrorCode;
592
593 if (enmType == TRPM_TRAP)
594 {
595 switch (u8Vector) {
596 case 8:
597 case 10:
598 case 11:
599 case 12:
600 case 13:
601 case 14:
602 case 17:
603 /* Valid error codes. */
604 Event.n.u1ErrorCodeValid = 1;
605 break;
606 default:
607 break;
608 }
609 if (u8Vector == X86_XCPT_NMI)
610 Event.n.u3Type = SVM_EVENT_NMI;
611 else
612 Event.n.u3Type = SVM_EVENT_EXCEPTION;
613 }
614 else
615 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
616
617 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
618 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
619 } /* if (interrupts can be dispatched) */
620
621 return VINF_SUCCESS;
622}
623
624/**
625 * Save the host state
626 *
627 * @returns VBox status code.
628 * @param pVM The VM to operate on.
629 * @param pVCpu The VM CPU to operate on.
630 */
631VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
632{
633 NOREF(pVM);
634 NOREF(pVCpu);
635 /* Nothing to do here. */
636 return VINF_SUCCESS;
637}
638
639/**
640 * Loads the guest state
641 *
642 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
643 *
644 * @returns VBox status code.
645 * @param pVM The VM to operate on.
646 * @param pVCpu The VM CPU to operate on.
647 * @param pCtx Guest context
648 */
649VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
650{
651 RTGCUINTPTR val;
652 SVM_VMCB *pVMCB;
653
654 if (pVM == NULL)
655 return VERR_INVALID_PARAMETER;
656
657 /* Setup AMD SVM. */
658 Assert(pVM->hwaccm.s.svm.fSupported);
659
660 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
661 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
662
663 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
664 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
665 {
666 SVM_WRITE_SELREG(CS, cs);
667 SVM_WRITE_SELREG(SS, ss);
668 SVM_WRITE_SELREG(DS, ds);
669 SVM_WRITE_SELREG(ES, es);
670 SVM_WRITE_SELREG(FS, fs);
671 SVM_WRITE_SELREG(GS, gs);
672 }
673
674 /* Guest CPU context: LDTR. */
675 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
676 {
677 SVM_WRITE_SELREG(LDTR, ldtr);
678 }
679
680 /* Guest CPU context: TR. */
681 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
682 {
683 SVM_WRITE_SELREG(TR, tr);
684 }
685
686 /* Guest CPU context: GDTR. */
687 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
688 {
689 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
690 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
691 }
692
693 /* Guest CPU context: IDTR. */
694 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
695 {
696 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
697 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
698 }
699
700 /*
701 * Sysenter MSRs (unconditional)
702 */
703 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
704 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
705 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
706
707 /* Control registers */
708 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
709 {
710 val = pCtx->cr0;
711 if (!CPUMIsGuestFPUStateActive(pVCpu))
712 {
713 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
714 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
715 }
716 else
717 {
718 /** @todo check if we support the old style mess correctly. */
719 if (!(val & X86_CR0_NE))
720 {
721 Log(("Forcing X86_CR0_NE!!!\n"));
722
723 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
724 if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
725 {
726 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
727 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
728 }
729 }
730 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
731 }
732 /* Always enable caching. */
733 val &= ~(X86_CR0_CD|X86_CR0_NW);
734
735 /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
736 /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
737 if (!pVM->hwaccm.s.fNestedPaging)
738 {
739 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
740 val |= X86_CR0_WP; /* Must set this as we rely on protecting various pages and supervisor writes must be caught. */
741 }
742 pVMCB->guest.u64CR0 = val;
743 }
744 /* CR2 as well */
745 pVMCB->guest.u64CR2 = pCtx->cr2;
746
747 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
748 {
749 /* Save our shadow CR3 register. */
750 if (pVM->hwaccm.s.fNestedPaging)
751 {
752 PGMMODE enmShwPagingMode;
753
754#if HC_ARCH_BITS == 32
755 if (CPUMIsGuestInLongModeEx(pCtx))
756 enmShwPagingMode = PGMMODE_AMD64_NX;
757 else
758#endif
759 enmShwPagingMode = PGMGetHostMode(pVM);
760
761 pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
762 Assert(pVMCB->ctrl.u64NestedPagingCR3);
763 pVMCB->guest.u64CR3 = pCtx->cr3;
764 }
765 else
766 {
767 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
768 Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
769 }
770 }
771
772 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
773 {
774 val = pCtx->cr4;
775 if (!pVM->hwaccm.s.fNestedPaging)
776 {
777 switch(pVCpu->hwaccm.s.enmShadowMode)
778 {
779 case PGMMODE_REAL:
780 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
781 AssertFailed();
782 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
783
784 case PGMMODE_32_BIT: /* 32-bit paging. */
785 val &= ~X86_CR4_PAE;
786 break;
787
788 case PGMMODE_PAE: /* PAE paging. */
789 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
790 /** @todo use normal 32 bits paging */
791 val |= X86_CR4_PAE;
792 break;
793
794 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
795 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
796#ifdef VBOX_ENABLE_64_BITS_GUESTS
797 break;
798#else
799 AssertFailed();
800 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
801#endif
802
803 default: /* shut up gcc */
804 AssertFailed();
805 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
806 }
807 }
808 pVMCB->guest.u64CR4 = val;
809 }
810
811 /* Debug registers. */
812 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
813 {
814 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
815 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
816
817 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
818 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
819 pCtx->dr[7] |= 0x400; /* must be one */
820
821 pVMCB->guest.u64DR7 = pCtx->dr[7];
822 pVMCB->guest.u64DR6 = pCtx->dr[6];
823
824#ifdef DEBUG
825 /* Sync the hypervisor debug state now if any breakpoint is armed. */
826 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
827 && !CPUMIsHyperDebugStateActive(pVCpu)
828 && !DBGFIsStepping(pVCpu))
829 {
830 /* Save the host and load the hypervisor debug state. */
831 int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
832 AssertRC(rc);
833
834 /* DRx intercepts remain enabled. */
835
836 /* Override dr6 & dr7 with the hypervisor values. */
837 pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
838 pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
839 }
840 else
841#endif
842 /* Sync the debug state now if any breakpoint is armed. */
843 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
844 && !CPUMIsGuestDebugStateActive(pVCpu)
845 && !DBGFIsStepping(pVCpu))
846 {
847 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
848
849 /* Disable drx move intercepts. */
850 pVMCB->ctrl.u16InterceptRdDRx = 0;
851 pVMCB->ctrl.u16InterceptWrDRx = 0;
852
853 /* Save the host and load the guest debug state. */
854 int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
855 AssertRC(rc);
856 }
857 }
858
859 /* EIP, ESP and EFLAGS */
860 pVMCB->guest.u64RIP = pCtx->rip;
861 pVMCB->guest.u64RSP = pCtx->rsp;
862 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
863
864 /* Set CPL */
865 pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
866
867 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
868 pVMCB->guest.u64RAX = pCtx->rax;
869
870 /* vmrun will fail without MSR_K6_EFER_SVME. */
871 pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
872
873 /* 64 bits guest mode? */
874 if (CPUMIsGuestInLongModeEx(pCtx))
875 {
876#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
877 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
878#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
879 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
880#else
881# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
882 if (!pVM->hwaccm.s.fAllow64BitGuests)
883 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
884# endif
885 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
886#endif
887 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
888 pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
889 pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
890 }
891 else
892 {
893 /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
894 pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
895
896 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
897 }
898
899 /* TSC offset. */
900 if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
901 {
902 uint64_t u64CurTSC = ASMReadTSC();
903 if (u64CurTSC + pVMCB->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
904 {
905 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
906 pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
907 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
908 }
909 else
910 {
911 /* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
912 LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVMCB->ctrl.u64TSCOffset, u64CurTSC + pVMCB->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVMCB->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
913 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
914 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
915 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow);
916 }
917 }
918 else
919 {
920 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
921 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
922 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
923 }
924
925 /* Sync the various msrs for 64 bits mode. */
926 pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
927 pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
928 pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
929 pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
930 pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
931
932#ifdef DEBUG
933 /* Intercept X86_XCPT_DB if stepping is enabled */
934 if ( DBGFIsStepping(pVCpu)
935 || CPUMIsHyperDebugStateActive(pVCpu))
936 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
937 else
938 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
939#endif
940
941 /* Done. */
942 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
943
944 return VINF_SUCCESS;
945}
946
947
948/**
949 * Runs guest code in an AMD-V VM.
950 *
951 * @returns VBox status code.
952 * @param pVM The VM to operate on.
953 * @param pVCpu The VM CPU to operate on.
954 * @param pCtx Guest context
955 */
956VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
957{
958 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
959 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hwaccm.s.StatExit1);
960 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hwaccm.s.StatExit2);
961
962 VBOXSTRICTRC rc = VINF_SUCCESS;
963 int rc2;
964 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
965 SVM_VMCB *pVMCB;
966 bool fSyncTPR = false;
967 unsigned cResume = 0;
968 uint8_t u8LastTPR;
969 PHWACCM_CPUINFO pCpu = 0;
970 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
971#ifdef VBOX_STRICT
972 RTCPUID idCpuCheck;
973#endif
974#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
975 uint64_t u64LastTime = RTTimeMilliTS();
976#endif
977
978 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
979 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
980
981 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
982 */
983ResumeExecution:
984 if (!STAM_PROFILE_ADV_IS_RUNNING(&pVCpu->hwaccm.s.StatEntry))
985 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit2, &pVCpu->hwaccm.s.StatEntry, x);
986 Assert(!HWACCMR0SuspendPending());
987
988 /* Safety precaution; looping for too long here can have a very bad effect on the host */
989 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
990 {
991 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
992 rc = VINF_EM_RAW_INTERRUPT;
993 goto end;
994 }
995
996 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
997 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
998 {
999 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
1000 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
1001 {
1002 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1003 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1004 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1005 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
1006 */
1007 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1008 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1009 pVMCB->ctrl.u64IntShadow = 0;
1010 }
1011 }
1012 else
1013 {
1014 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1015 pVMCB->ctrl.u64IntShadow = 0;
1016 }
1017
1018#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1019 if (RT_UNLIKELY((cResume & 0xf) == 0))
1020 {
1021 uint64_t u64CurTime = RTTimeMilliTS();
1022
1023 if (RT_UNLIKELY(u64CurTime > u64LastTime))
1024 {
1025 u64LastTime = u64CurTime;
1026 TMTimerPollVoid(pVM, pVCpu);
1027 }
1028 }
1029#endif
1030
1031 /* Check for pending actions that force us to go back to ring 3. */
1032 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING)
1033 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST))
1034 {
1035 /* Check if a sync operation is pending. */
1036 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1037 {
1038 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1039 AssertRC(VBOXSTRICTRC_VAL(rc));
1040 if (rc != VINF_SUCCESS)
1041 {
1042 Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", VBOXSTRICTRC_VAL(rc)));
1043 goto end;
1044 }
1045 }
1046
1047#ifdef DEBUG
1048 /* Intercept X86_XCPT_DB if stepping is enabled */
1049 if (!DBGFIsStepping(pVCpu))
1050#endif
1051 {
1052 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
1053 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
1054 {
1055 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
1056 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
1057 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
1058 goto end;
1059 }
1060 }
1061
1062 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1063 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
1064 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1065 {
1066 rc = VINF_EM_PENDING_REQUEST;
1067 goto end;
1068 }
1069
1070 /* Check if a pgm pool flush is in progress. */
1071 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
1072 {
1073 rc = VINF_PGM_POOL_FLUSH_PENDING;
1074 goto end;
1075 }
1076 }
1077
1078#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1079 /*
1080 * Exit to ring-3 preemption/work is pending.
1081 *
1082 * Interrupts are disabled before the call to make sure we don't miss any interrupt
1083 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
1084 * further down, but SVMR0CheckPendingInterrupt makes that impossible.)
1085 *
1086 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
1087 * shootdowns rely on this.
1088 */
1089 uOldEFlags = ASMIntDisableFlags();
1090 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
1091 {
1092 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
1093 rc = VINF_EM_RAW_INTERRUPT;
1094 goto end;
1095 }
1096 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1097#endif
1098
1099 /* When external interrupts are pending, we should exit the VM when IF is set. */
1100 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1101 rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
1102 if (RT_FAILURE(rc))
1103 goto end;
1104
1105 /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
1106 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)
1107 * @todo query and update the TPR only when it could have been changed (mmio access)
1108 */
1109 if (pVM->hwaccm.s.fHasIoApic)
1110 {
1111 bool fPending;
1112
1113 /* TPR caching in CR8 */
1114 rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
1115 AssertRC(rc2);
1116
1117 if (pVM->hwaccm.s.fTPRPatchingActive)
1118 {
1119 /* Our patch code uses LSTAR for TPR caching. */
1120 pCtx->msrLSTAR = u8LastTPR;
1121
1122 if (fPending)
1123 {
1124 /* A TPR change could activate a pending interrupt, so catch lstar writes. */
1125 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
1126 }
1127 else
1128 /* No interrupts are pending, so we don't need to be explicitely notified.
1129 * There are enough world switches for detecting pending interrupts.
1130 */
1131 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
1132 }
1133 else
1134 {
1135 pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1136
1137 if (fPending)
1138 {
1139 /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1140 pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
1141 }
1142 else
1143 /* No interrupts are pending, so we don't need to be explicitely notified.
1144 * There are enough world switches for detecting pending interrupts.
1145 */
1146 pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1147 }
1148 fSyncTPR = !fPending;
1149 }
1150
1151 /* All done! Let's start VM execution. */
1152
1153 /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1154 pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1155
1156#ifdef LOG_ENABLED
1157 pCpu = HWACCMR0GetCurrentCpu();
1158 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1159 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1160 {
1161 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1162 LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1163 else
1164 LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1165 }
1166 if (pCpu->fFlushTLB)
1167 LogFlow(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1168#endif
1169
1170 /*
1171 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1172 * (until the actual world switch)
1173 */
1174#ifdef VBOX_STRICT
1175 idCpuCheck = RTMpCpuId();
1176#endif
1177 VMMR0LogFlushDisable(pVCpu);
1178
1179 /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
1180 rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1181 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1182 {
1183 VMMR0LogFlushEnable(pVCpu);
1184 goto end;
1185 }
1186
1187#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1188 /* Disable interrupts to make sure a poke will interrupt execution.
1189 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
1190 */
1191 uOldEFlags = ASMIntDisableFlags();
1192 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1193#endif
1194 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatEntry, &pVCpu->hwaccm.s.StatInGC, x);
1195
1196 pCpu = HWACCMR0GetCurrentCpu();
1197 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1198 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1199 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1200 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1201 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1202 {
1203 /* Force a TLB flush on VM entry. */
1204 pVCpu->hwaccm.s.fForceTLBFlush = true;
1205 }
1206 else
1207 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1208
1209 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1210
1211 /** Set TLB flush state as checked until we return from the world switch. */
1212 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, true);
1213
1214 /* Check for tlb shootdown flushes. */
1215 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1216 pVCpu->hwaccm.s.fForceTLBFlush = true;
1217
1218 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1219 if ( pVCpu->hwaccm.s.fForceTLBFlush
1220 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1221 {
1222 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1223 || pCpu->fFlushTLB)
1224 {
1225 pCpu->fFlushTLB = false;
1226 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1227 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1228 pCpu->cTLBFlushes++;
1229 }
1230 else
1231 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1232
1233 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1234 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1235 }
1236 else
1237 {
1238 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1239
1240 /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1241 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1242 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1243
1244 Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
1245 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1246
1247 if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1248 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1249 {
1250 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1251 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1252 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1253 SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1254 }
1255 }
1256 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1257 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1258
1259 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1260 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1261 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1262 pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1263
1264#ifdef VBOX_WITH_STATISTICS
1265 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1266 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1267 else
1268 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1269#endif
1270
1271 /* In case we execute a goto ResumeExecution later on. */
1272 pVCpu->hwaccm.s.fResumeVM = true;
1273 pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1274
1275 Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1276 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1277 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1278 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);
1279 Assert(pVMCB->ctrl.u64LBRVirt == 0);
1280
1281#ifdef VBOX_STRICT
1282 Assert(idCpuCheck == RTMpCpuId());
1283#endif
1284 TMNotifyStartOfExecution(pVCpu);
1285#ifdef VBOX_WITH_KERNEL_USING_XMM
1286 hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
1287#else
1288 pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1289#endif
1290 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, false);
1291 ASMAtomicIncU32(&pVCpu->hwaccm.s.cWorldSwitchExit);
1292 /* Possibly the last TSC value seen by the guest (too high) (only when we're in tsc offset mode). */
1293 if (!(pVMCB->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
1294 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVMCB->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
1295 TMNotifyEndOfExecution(pVCpu);
1296 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1297 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatInGC, &pVCpu->hwaccm.s.StatExit1, x);
1298 ASMSetFlags(uOldEFlags);
1299#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1300 uOldEFlags = ~(RTCCUINTREG)0;
1301#endif
1302
1303 /*
1304 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1305 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1306 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1307 */
1308
1309 /* Reason for the VM exit */
1310 exitCode = pVMCB->ctrl.u64ExitCode;
1311
1312 if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1313 {
1314 HWACCMDumpRegs(pVM, pVCpu, pCtx);
1315#ifdef DEBUG
1316 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1317 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1318 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1319 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1320 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1321 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1322 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1323 Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1324 Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1325 Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1326
1327 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1328 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1329 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1330 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1331
1332 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1333 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1334 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1335 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1336 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1337 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1338 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1339 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1340 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1341 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1342
1343 Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1344 Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1345 Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1346 Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1347 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1348 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1349 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1350 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1351 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1352 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1353 Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1354 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1355 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1356 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1357 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1358 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1359 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1360
1361 Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1362 Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1363
1364 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1365 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1366 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1367 Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1368 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1369 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1370 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1371 Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1372 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1373 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1374 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1375 Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1376 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1377 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1378 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1379 Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1380 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1381 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1382 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1383 Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1384
1385 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1386 Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1387
1388 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1389 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1390 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1391 Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1392
1393 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1394 Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1395
1396 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1397 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1398 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1399 Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1400
1401 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1402 Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1403 Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1404 Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1405 Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1406 Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1407 Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1408
1409 Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1410 Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1411 Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1412 Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1413
1414 Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1415 Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1416 Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1417
1418 Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1419 Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1420 Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1421 Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1422 Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1423 Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1424 Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1425 Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1426 Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1427 Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1428 Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1429 Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1430
1431#endif
1432 rc = VERR_SVM_UNABLE_TO_START_VM;
1433 VMMR0LogFlushEnable(pVCpu);
1434 goto end;
1435 }
1436
1437 /* Let's first sync back eip, esp, and eflags. */
1438 pCtx->rip = pVMCB->guest.u64RIP;
1439 pCtx->rsp = pVMCB->guest.u64RSP;
1440 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1441 /* eax is saved/restore across the vmrun instruction */
1442 pCtx->rax = pVMCB->guest.u64RAX;
1443
1444 /* Save all the MSRs that can be changed by the guest without causing a world switch. (fs & gs base are saved with SVM_READ_SELREG) */
1445 pCtx->msrSTAR = pVMCB->guest.u64STAR; /* legacy syscall eip, cs & ss */
1446 pCtx->msrLSTAR = pVMCB->guest.u64LSTAR; /* 64 bits mode syscall rip */
1447 pCtx->msrCSTAR = pVMCB->guest.u64CSTAR; /* compatibility mode syscall rip */
1448 pCtx->msrSFMASK = pVMCB->guest.u64SFMASK; /* syscall flag mask */
1449 pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1450 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1451 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1452 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1453
1454 /* Can be updated behind our back in the nested paging case. */
1455 pCtx->cr2 = pVMCB->guest.u64CR2;
1456
1457 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1458 SVM_READ_SELREG(SS, ss);
1459 SVM_READ_SELREG(CS, cs);
1460 SVM_READ_SELREG(DS, ds);
1461 SVM_READ_SELREG(ES, es);
1462 SVM_READ_SELREG(FS, fs);
1463 SVM_READ_SELREG(GS, gs);
1464
1465 /* Correct the hidden CS granularity flag. Haven't seen it being wrong in
1466 any other register (yet). */
1467 if ( !pCtx->csHid.Attr.n.u1Granularity
1468 && pCtx->csHid.Attr.n.u1Present
1469 && pCtx->csHid.u32Limit > UINT32_C(0xfffff))
1470 {
1471 Assert((pCtx->csHid.u32Limit & 0xfff) == 0xfff);
1472 pCtx->csHid.Attr.n.u1Granularity = 1;
1473 }
1474#define SVM_ASSERT_SEL_GRANULARITY(reg) \
1475 AssertMsg( !pCtx->reg##Hid.Attr.n.u1Present \
1476 || ( pCtx->reg##Hid.Attr.n.u1Granularity \
1477 ? (pCtx->reg##Hid.u32Limit & 0xfff) == 0xfff \
1478 : pCtx->reg##Hid.u32Limit <= 0xfffff), \
1479 ("%#x %#x %#llx\n", pCtx->reg##Hid.u32Limit, pCtx->reg##Hid.Attr.u, pCtx->reg##Hid.u64Base))
1480 SVM_ASSERT_SEL_GRANULARITY(ss);
1481 SVM_ASSERT_SEL_GRANULARITY(cs);
1482 SVM_ASSERT_SEL_GRANULARITY(ds);
1483 SVM_ASSERT_SEL_GRANULARITY(es);
1484 SVM_ASSERT_SEL_GRANULARITY(fs);
1485 SVM_ASSERT_SEL_GRANULARITY(gs);
1486#undef SVM_ASSERT_SEL_GRANULARITY
1487
1488 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1489 SVM_READ_SELREG(LDTR, ldtr);
1490 SVM_READ_SELREG(TR, tr);
1491
1492 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1493 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1494
1495 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1496 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1497
1498 /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1499 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1500 if ( pVM->hwaccm.s.fNestedPaging
1501 && pCtx->cr3 != pVMCB->guest.u64CR3)
1502 {
1503 CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1504 PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1505 }
1506
1507 /* Note! NOW IT'S SAFE FOR LOGGING! */
1508 VMMR0LogFlushEnable(pVCpu);
1509
1510 /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1511 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1512 {
1513 Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1514 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1515 }
1516 else
1517 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1518
1519 Log2(("exitCode = %x\n", exitCode));
1520
1521 /* Sync back DR6 as it could have been changed by hitting breakpoints. */
1522 pCtx->dr[6] = pVMCB->guest.u64DR6;
1523 /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1524 pCtx->dr[7] = pVMCB->guest.u64DR7;
1525
1526 /* Check if an injected event was interrupted prematurely. */
1527 pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1528 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1529 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1530 {
1531 Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1532
1533#ifdef LOG_ENABLED
1534 SVM_EVENT Event;
1535 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1536
1537 if ( exitCode == SVM_EXIT_EXCEPTION_E
1538 && Event.n.u8Vector == 0xE)
1539 {
1540 Log(("Double fault!\n"));
1541 }
1542#endif
1543
1544 pVCpu->hwaccm.s.Event.fPending = true;
1545 /* Error code present? (redundant) */
1546 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1547 pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1548 else
1549 pVCpu->hwaccm.s.Event.errCode = 0;
1550 }
1551#ifdef VBOX_WITH_STATISTICS
1552 if (exitCode == SVM_EXIT_NPF)
1553 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1554 else
1555 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1556#endif
1557
1558 /* Sync back the TPR if it was changed. */
1559 if (fSyncTPR)
1560 {
1561 if (pVM->hwaccm.s.fTPRPatchingActive)
1562 {
1563 if ((pCtx->msrLSTAR & 0xff) != u8LastTPR)
1564 {
1565 /* Our patch code uses LSTAR for TPR caching. */
1566 rc2 = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
1567 AssertRC(rc2);
1568 }
1569 }
1570 else
1571 {
1572 if ((u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1573 {
1574 rc2 = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1575 AssertRC(rc2);
1576 }
1577 }
1578 }
1579
1580 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit1, &pVCpu->hwaccm.s.StatExit2, x);
1581
1582 /* Deal with the reason of the VM-exit. */
1583 switch (exitCode)
1584 {
1585 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1586 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1587 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1588 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1589 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1590 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1591 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1592 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1593 {
1594 /* Pending trap. */
1595 SVM_EVENT Event;
1596 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1597
1598 Log2(("Hardware/software interrupt %d\n", vector));
1599 switch (vector)
1600 {
1601 case X86_XCPT_DB:
1602 {
1603 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1604
1605 /* Note that we don't support guest and host-initiated debugging at the same time. */
1606 Assert(DBGFIsStepping(pVCpu) || CPUMIsHyperDebugStateActive(pVCpu));
1607
1608 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1609 if (rc == VINF_EM_RAW_GUEST_TRAP)
1610 {
1611 Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1612
1613 /* Reinject the exception. */
1614 Event.au64[0] = 0;
1615 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1616 Event.n.u1Valid = 1;
1617 Event.n.u8Vector = X86_XCPT_DB;
1618
1619 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1620 goto ResumeExecution;
1621 }
1622 /* Return to ring 3 to deal with the debug exit code. */
1623 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
1624 break;
1625 }
1626
1627 case X86_XCPT_NM:
1628 {
1629 Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1630
1631 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1632 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1633 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1634 if (rc == VINF_SUCCESS)
1635 {
1636 Assert(CPUMIsGuestFPUStateActive(pVCpu));
1637 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1638
1639 /* Continue execution. */
1640 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1641
1642 goto ResumeExecution;
1643 }
1644
1645 Log(("Forward #NM fault to the guest\n"));
1646 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1647
1648 Event.au64[0] = 0;
1649 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1650 Event.n.u1Valid = 1;
1651 Event.n.u8Vector = X86_XCPT_NM;
1652
1653 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1654 goto ResumeExecution;
1655 }
1656
1657 case X86_XCPT_PF: /* Page fault */
1658 {
1659 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1660 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1661
1662#ifdef DEBUG
1663 if (pVM->hwaccm.s.fNestedPaging)
1664 { /* A genuine pagefault.
1665 * Forward the trap to the guest by injecting the exception and resuming execution.
1666 */
1667 Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1668 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1669
1670 /* Now we must update CR2. */
1671 pCtx->cr2 = uFaultAddress;
1672
1673 Event.au64[0] = 0;
1674 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1675 Event.n.u1Valid = 1;
1676 Event.n.u8Vector = X86_XCPT_PF;
1677 Event.n.u1ErrorCodeValid = 1;
1678 Event.n.u32ErrorCode = errCode;
1679
1680 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1681 goto ResumeExecution;
1682 }
1683#endif
1684 Assert(!pVM->hwaccm.s.fNestedPaging);
1685
1686#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1687 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1688 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1689 && (uFaultAddress & 0xfff) == 0x080
1690 && !(errCode & X86_TRAP_PF_P) /* not present */
1691 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1692 && !CPUMIsGuestInLongModeEx(pCtx)
1693 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1694 {
1695 RTGCPHYS GCPhysApicBase, GCPhys;
1696 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1697 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1698
1699 rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1700 if ( rc == VINF_SUCCESS
1701 && GCPhys == GCPhysApicBase)
1702 {
1703 /* Only attempt to patch the instruction once. */
1704 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1705 if (!pPatch)
1706 {
1707 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1708 break;
1709 }
1710 }
1711 }
1712#endif
1713
1714 Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1715 /* Exit qualification contains the linear address of the page fault. */
1716 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1717 TRPMSetErrorCode(pVCpu, errCode);
1718 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1719
1720 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1721 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1722 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
1723 if (rc == VINF_SUCCESS)
1724 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1725 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1726 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1727
1728 TRPMResetTrap(pVCpu);
1729 goto ResumeExecution;
1730 }
1731 else
1732 if (rc == VINF_EM_RAW_GUEST_TRAP)
1733 { /* A genuine pagefault.
1734 * Forward the trap to the guest by injecting the exception and resuming execution.
1735 */
1736 Log2(("Forward page fault to the guest\n"));
1737 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1738 /* The error code might have been changed. */
1739 errCode = TRPMGetErrorCode(pVCpu);
1740
1741 TRPMResetTrap(pVCpu);
1742
1743 /* Now we must update CR2. */
1744 pCtx->cr2 = uFaultAddress;
1745
1746 Event.au64[0] = 0;
1747 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1748 Event.n.u1Valid = 1;
1749 Event.n.u8Vector = X86_XCPT_PF;
1750 Event.n.u1ErrorCodeValid = 1;
1751 Event.n.u32ErrorCode = errCode;
1752
1753 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1754 goto ResumeExecution;
1755 }
1756#ifdef VBOX_STRICT
1757 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1758 LogFlow(("PGMTrap0eHandler failed with %d\n", VBOXSTRICTRC_VAL(rc)));
1759#endif
1760 /* Need to go back to the recompiler to emulate the instruction. */
1761 TRPMResetTrap(pVCpu);
1762 break;
1763 }
1764
1765 case X86_XCPT_MF: /* Floating point exception. */
1766 {
1767 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1768 if (!(pCtx->cr0 & X86_CR0_NE))
1769 {
1770 /* old style FPU error reporting needs some extra work. */
1771 /** @todo don't fall back to the recompiler, but do it manually. */
1772 rc = VINF_EM_RAW_EMULATE_INSTR;
1773 break;
1774 }
1775 Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1776
1777 Event.au64[0] = 0;
1778 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1779 Event.n.u1Valid = 1;
1780 Event.n.u8Vector = X86_XCPT_MF;
1781
1782 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1783 goto ResumeExecution;
1784 }
1785
1786#ifdef VBOX_STRICT
1787 case X86_XCPT_BP: /* Breakpoint. */
1788 case X86_XCPT_GP: /* General protection failure exception.*/
1789 case X86_XCPT_UD: /* Unknown opcode exception. */
1790 case X86_XCPT_DE: /* Divide error. */
1791 case X86_XCPT_SS: /* Stack segment exception. */
1792 case X86_XCPT_NP: /* Segment not present exception. */
1793 {
1794 Event.au64[0] = 0;
1795 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1796 Event.n.u1Valid = 1;
1797 Event.n.u8Vector = vector;
1798
1799 switch(vector)
1800 {
1801 case X86_XCPT_GP:
1802 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1803 Event.n.u1ErrorCodeValid = 1;
1804 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1805 break;
1806 case X86_XCPT_BP:
1807 break;
1808 case X86_XCPT_DE:
1809 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1810 break;
1811 case X86_XCPT_UD:
1812 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1813 break;
1814 case X86_XCPT_SS:
1815 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1816 Event.n.u1ErrorCodeValid = 1;
1817 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1818 break;
1819 case X86_XCPT_NP:
1820 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1821 Event.n.u1ErrorCodeValid = 1;
1822 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1823 break;
1824 }
1825 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1826 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1827 goto ResumeExecution;
1828 }
1829#endif
1830 default:
1831 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1832 rc = VERR_EM_INTERNAL_ERROR;
1833 break;
1834
1835 } /* switch (vector) */
1836 break;
1837 }
1838
1839 case SVM_EXIT_NPF:
1840 {
1841 /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1842 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1843 RTGCPHYS GCPhysFault = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1844 PGMMODE enmShwPagingMode;
1845
1846 Assert(pVM->hwaccm.s.fNestedPaging);
1847 LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
1848
1849#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1850 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1851 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1852 && (GCPhysFault & PAGE_OFFSET_MASK) == 0x080
1853 && ( !(errCode & X86_TRAP_PF_P) /* not present */
1854 || (errCode & (X86_TRAP_PF_P | X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P | X86_TRAP_PF_RSVD) /* mmio optimization */)
1855 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1856 && !CPUMIsGuestInLongModeEx(pCtx)
1857 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1858 {
1859 RTGCPHYS GCPhysApicBase;
1860 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1861 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1862
1863 if (GCPhysFault == GCPhysApicBase + 0x80)
1864 {
1865 /* Only attempt to patch the instruction once. */
1866 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1867 if (!pPatch)
1868 {
1869 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1870 break;
1871 }
1872 }
1873 }
1874#endif
1875
1876 /* Handle the pagefault trap for the nested shadow table. */
1877#if HC_ARCH_BITS == 32 /** @todo shadow this in a variable. */
1878 if (CPUMIsGuestInLongModeEx(pCtx))
1879 enmShwPagingMode = PGMMODE_AMD64_NX;
1880 else
1881#endif
1882 enmShwPagingMode = PGMGetHostMode(pVM);
1883
1884 /* MMIO optimization */
1885 Assert((errCode & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
1886 if ((errCode & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD | X86_TRAP_PF_P))
1887 {
1888 rc = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmShwPagingMode, CPUMCTX2CORE(pCtx), GCPhysFault, errCode);
1889 if (rc == VINF_SUCCESS)
1890 {
1891 Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
1892 goto ResumeExecution;
1893 }
1894 Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
1895 break;
1896 }
1897
1898 /* Exit qualification contains the linear address of the page fault. */
1899 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1900 TRPMSetErrorCode(pVCpu, errCode);
1901 TRPMSetFaultAddress(pVCpu, GCPhysFault);
1902
1903 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), GCPhysFault);
1904 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
1905 if (rc == VINF_SUCCESS)
1906 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1907 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
1908 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1909
1910 TRPMResetTrap(pVCpu);
1911 goto ResumeExecution;
1912 }
1913
1914#ifdef VBOX_STRICT
1915 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1916 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", VBOXSTRICTRC_VAL(rc)));
1917#endif
1918 /* Need to go back to the recompiler to emulate the instruction. */
1919 TRPMResetTrap(pVCpu);
1920 break;
1921 }
1922
1923 case SVM_EXIT_VINTR:
1924 /* A virtual interrupt is about to be delivered, which means IF=1. */
1925 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1926 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1927 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1928 goto ResumeExecution;
1929
1930 case SVM_EXIT_FERR_FREEZE:
1931 case SVM_EXIT_INTR:
1932 case SVM_EXIT_NMI:
1933 case SVM_EXIT_SMI:
1934 case SVM_EXIT_INIT:
1935 /* External interrupt; leave to allow it to be dispatched again. */
1936 rc = VINF_EM_RAW_INTERRUPT;
1937 break;
1938
1939 case SVM_EXIT_WBINVD:
1940 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1941 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1942 /* Skip instruction and continue directly. */
1943 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1944 /* Continue execution.*/
1945 goto ResumeExecution;
1946
1947 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1948 {
1949 Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1950 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1951 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1952 if (rc == VINF_SUCCESS)
1953 {
1954 /* Update EIP and continue execution. */
1955 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1956 goto ResumeExecution;
1957 }
1958 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1959 rc = VINF_EM_RAW_EMULATE_INSTR;
1960 break;
1961 }
1962
1963 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1964 {
1965 Log2(("SVM: Rdtsc\n"));
1966 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1967 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1968 if (rc == VINF_SUCCESS)
1969 {
1970 /* Update EIP and continue execution. */
1971 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1972 goto ResumeExecution;
1973 }
1974 rc = VINF_EM_RAW_EMULATE_INSTR;
1975 break;
1976 }
1977
1978 case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1979 {
1980 Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1981 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1982 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1983 if (rc == VINF_SUCCESS)
1984 {
1985 /* Update EIP and continue execution. */
1986 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1987 goto ResumeExecution;
1988 }
1989 rc = VINF_EM_RAW_EMULATE_INSTR;
1990 break;
1991 }
1992
1993 case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1994 {
1995 Log2(("SVM: Rdtscp\n"));
1996 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1997 rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
1998 if (rc == VINF_SUCCESS)
1999 {
2000 /* Update EIP and continue execution. */
2001 pCtx->rip += 3; /* Note! hardcoded opcode size! */
2002 goto ResumeExecution;
2003 }
2004 AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2005 rc = VINF_EM_RAW_EMULATE_INSTR;
2006 break;
2007 }
2008
2009 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
2010 {
2011 Log2(("SVM: invlpg\n"));
2012 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
2013
2014 Assert(!pVM->hwaccm.s.fNestedPaging);
2015
2016 /* Truly a pita. Why can't SVM give the same information as VT-x? */
2017 rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
2018 if (rc == VINF_SUCCESS)
2019 {
2020 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
2021 goto ResumeExecution; /* eip already updated */
2022 }
2023 break;
2024 }
2025
2026 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
2027 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
2028 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
2029 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
2030 {
2031 uint32_t cbSize;
2032
2033 Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
2034 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
2035 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2036
2037 switch (exitCode - SVM_EXIT_WRITE_CR0)
2038 {
2039 case 0:
2040 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2041 break;
2042 case 2:
2043 break;
2044 case 3:
2045 Assert(!pVM->hwaccm.s.fNestedPaging);
2046 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2047 break;
2048 case 4:
2049 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2050 break;
2051 case 8:
2052 break;
2053 default:
2054 AssertFailed();
2055 }
2056 if (rc == VINF_SUCCESS)
2057 {
2058 /* EIP has been updated already. */
2059
2060 /* Only resume if successful. */
2061 goto ResumeExecution;
2062 }
2063 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2064 break;
2065 }
2066
2067 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
2068 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
2069 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
2070 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
2071 {
2072 uint32_t cbSize;
2073
2074 Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
2075 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
2076 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2077 if (rc == VINF_SUCCESS)
2078 {
2079 /* EIP has been updated already. */
2080
2081 /* Only resume if successful. */
2082 goto ResumeExecution;
2083 }
2084 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2085 break;
2086 }
2087
2088 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2089 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
2090 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2091 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2092 {
2093 uint32_t cbSize;
2094
2095 Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
2096 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2097
2098 if ( !DBGFIsStepping(pVCpu)
2099 && !CPUMIsHyperDebugStateActive(pVCpu))
2100 {
2101 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2102
2103 /* Disable drx move intercepts. */
2104 pVMCB->ctrl.u16InterceptRdDRx = 0;
2105 pVMCB->ctrl.u16InterceptWrDRx = 0;
2106
2107 /* Save the host and load the guest debug state. */
2108 rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2109 AssertRC(rc2);
2110 goto ResumeExecution;
2111 }
2112
2113 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2114 if (rc == VINF_SUCCESS)
2115 {
2116 /* EIP has been updated already. */
2117 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2118
2119 /* Only resume if successful. */
2120 goto ResumeExecution;
2121 }
2122 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2123 break;
2124 }
2125
2126 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2127 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2128 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2129 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2130 {
2131 uint32_t cbSize;
2132
2133 Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2134 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2135
2136 if (!DBGFIsStepping(pVCpu))
2137 {
2138 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2139
2140 /* Disable drx move intercepts. */
2141 pVMCB->ctrl.u16InterceptRdDRx = 0;
2142 pVMCB->ctrl.u16InterceptWrDRx = 0;
2143
2144 /* Save the host and load the guest debug state. */
2145 rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2146 AssertRC(rc2);
2147 goto ResumeExecution;
2148 }
2149
2150 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2151 if (rc == VINF_SUCCESS)
2152 {
2153 /* EIP has been updated already. */
2154
2155 /* Only resume if successful. */
2156 goto ResumeExecution;
2157 }
2158 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2159 break;
2160 }
2161
2162 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2163 case SVM_EXIT_IOIO: /* I/O instruction. */
2164 {
2165 SVM_IOIO_EXIT IoExitInfo;
2166 uint32_t uIOSize, uAndVal;
2167
2168 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2169
2170 /** @todo could use a lookup table here */
2171 if (IoExitInfo.n.u1OP8)
2172 {
2173 uIOSize = 1;
2174 uAndVal = 0xff;
2175 }
2176 else
2177 if (IoExitInfo.n.u1OP16)
2178 {
2179 uIOSize = 2;
2180 uAndVal = 0xffff;
2181 }
2182 else
2183 if (IoExitInfo.n.u1OP32)
2184 {
2185 uIOSize = 4;
2186 uAndVal = 0xffffffff;
2187 }
2188 else
2189 {
2190 AssertFailed(); /* should be fatal. */
2191 rc = VINF_EM_RAW_EMULATE_INSTR;
2192 break;
2193 }
2194
2195 if (IoExitInfo.n.u1STR)
2196 {
2197 /* ins/outs */
2198 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2199
2200 /* Disassemble manually to deal with segment prefixes. */
2201 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2202 if (rc == VINF_SUCCESS)
2203 {
2204 if (IoExitInfo.n.u1Type == 0)
2205 {
2206 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2207 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2208 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
2209 }
2210 else
2211 {
2212 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2213 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2214 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
2215 }
2216 }
2217 else
2218 rc = VINF_EM_RAW_EMULATE_INSTR;
2219 }
2220 else
2221 {
2222 /* normal in/out */
2223 Assert(!IoExitInfo.n.u1REP);
2224
2225 if (IoExitInfo.n.u1Type == 0)
2226 {
2227 Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2228 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2229 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
2230 if (rc == VINF_IOM_HC_IOPORT_WRITE)
2231 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2232 }
2233 else
2234 {
2235 uint32_t u32Val = 0;
2236
2237 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2238 rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
2239 if (IOM_SUCCESS(rc))
2240 {
2241 /* Write back to the EAX register. */
2242 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2243 Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2244 }
2245 else
2246 if (rc == VINF_IOM_HC_IOPORT_READ)
2247 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2248 }
2249 }
2250 /*
2251 * Handled the I/O return codes.
2252 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2253 */
2254 if (IOM_SUCCESS(rc))
2255 {
2256 /* Update EIP and continue execution. */
2257 pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2258 if (RT_LIKELY(rc == VINF_SUCCESS))
2259 {
2260 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2261 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2262 {
2263 /* IO operation lookup arrays. */
2264 static uint32_t const aIOSize[4] = {1, 2, 0, 4};
2265
2266 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2267 for (unsigned i=0;i<4;i++)
2268 {
2269 unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2270
2271 if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2272 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2273 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2274 {
2275 SVM_EVENT Event;
2276
2277 Assert(CPUMIsGuestDebugStateActive(pVCpu));
2278
2279 /* Clear all breakpoint status flags and set the one we just hit. */
2280 pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2281 pCtx->dr[6] |= (uint64_t)RT_BIT(i);
2282
2283 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2284 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2285 * the contents have been read.
2286 */
2287 pVMCB->guest.u64DR6 = pCtx->dr[6];
2288
2289 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2290 pCtx->dr[7] &= ~X86_DR7_GD;
2291
2292 /* Paranoia. */
2293 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2294 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2295 pCtx->dr[7] |= 0x400; /* must be one */
2296
2297 pVMCB->guest.u64DR7 = pCtx->dr[7];
2298
2299 /* Inject the exception. */
2300 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2301
2302 Event.au64[0] = 0;
2303 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2304 Event.n.u1Valid = 1;
2305 Event.n.u8Vector = X86_XCPT_DB;
2306
2307 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2308 goto ResumeExecution;
2309 }
2310 }
2311 }
2312 goto ResumeExecution;
2313 }
2314 Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, VBOXSTRICTRC_VAL(rc)));
2315 break;
2316 }
2317
2318#ifdef VBOX_STRICT
2319 if (rc == VINF_IOM_HC_IOPORT_READ)
2320 Assert(IoExitInfo.n.u1Type != 0);
2321 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2322 Assert(IoExitInfo.n.u1Type == 0);
2323 else
2324 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rc)));
2325#endif
2326 Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2327 break;
2328 }
2329
2330 case SVM_EXIT_HLT:
2331 /** Check if external interrupts are pending; if so, don't switch back. */
2332 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2333 pCtx->rip++; /* skip hlt */
2334 if (EMShouldContinueAfterHalt(pVCpu, pCtx))
2335 goto ResumeExecution;
2336
2337 rc = VINF_EM_HALT;
2338 break;
2339
2340 case SVM_EXIT_MWAIT_UNCOND:
2341 Log2(("SVM: mwait\n"));
2342 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2343 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2344 if ( rc == VINF_EM_HALT
2345 || rc == VINF_SUCCESS)
2346 {
2347 /* Update EIP and continue execution. */
2348 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2349
2350 /** Check if external interrupts are pending; if so, don't switch back. */
2351 if ( rc == VINF_SUCCESS
2352 || ( rc == VINF_EM_HALT
2353 && EMShouldContinueAfterHalt(pVCpu, pCtx))
2354 )
2355 goto ResumeExecution;
2356 }
2357 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2358 break;
2359
2360 case SVM_EXIT_MONITOR:
2361 {
2362 Log2(("SVM: monitor\n"));
2363
2364 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMonitor);
2365 rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2366 if (rc == VINF_SUCCESS)
2367 {
2368 /* Update EIP and continue execution. */
2369 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2370 goto ResumeExecution;
2371 }
2372 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: monitor failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2373 break;
2374 }
2375
2376
2377 case SVM_EXIT_VMMCALL:
2378 rc = svmR0EmulateTprVMMCall(pVM, pVCpu, pCtx);
2379 if (rc == VINF_SUCCESS)
2380 {
2381 goto ResumeExecution; /* rip already updated. */
2382 }
2383 /* no break */
2384
2385 case SVM_EXIT_RSM:
2386 case SVM_EXIT_INVLPGA:
2387 case SVM_EXIT_VMRUN:
2388 case SVM_EXIT_VMLOAD:
2389 case SVM_EXIT_VMSAVE:
2390 case SVM_EXIT_STGI:
2391 case SVM_EXIT_CLGI:
2392 case SVM_EXIT_SKINIT:
2393 {
2394 /* Unsupported instructions. */
2395 SVM_EVENT Event;
2396
2397 Event.au64[0] = 0;
2398 Event.n.u3Type = SVM_EVENT_EXCEPTION;
2399 Event.n.u1Valid = 1;
2400 Event.n.u8Vector = X86_XCPT_UD;
2401
2402 Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2403 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2404 goto ResumeExecution;
2405 }
2406
2407 /* Emulate in ring 3. */
2408 case SVM_EXIT_MSR:
2409 {
2410 uint32_t cbSize;
2411
2412 /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
2413 if ( pVM->hwaccm.s.fTPRPatchingActive
2414 && pCtx->ecx == MSR_K8_LSTAR
2415 && pVMCB->ctrl.u64ExitInfo1 == 1 /* wrmsr */)
2416 {
2417 if ((pCtx->eax & 0xff) != u8LastTPR)
2418 {
2419 Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
2420
2421 /* Our patch code uses LSTAR for TPR caching. */
2422 rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
2423 AssertRC(rc2);
2424 }
2425
2426 /* Skip the instruction and continue. */
2427 pCtx->rip += 2; /* wrmsr = [0F 30] */
2428
2429 /* Only resume if successful. */
2430 goto ResumeExecution;
2431 }
2432
2433 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2434 STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2435 Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2436 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2437 if (rc == VINF_SUCCESS)
2438 {
2439 /* EIP has been updated already. */
2440
2441 /* Only resume if successful. */
2442 goto ResumeExecution;
2443 }
2444 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", VBOXSTRICTRC_VAL(rc)));
2445 break;
2446 }
2447
2448 case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler*/
2449 Log(("SVM_EXIT_TASK_SWITCH: exit2=%RX64\n", pVMCB->ctrl.u64ExitInfo2));
2450 if ( !(pVMCB->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET | SVM_EXIT2_TASK_SWITCH_JMP))
2451 && pVCpu->hwaccm.s.Event.fPending)
2452 {
2453 SVM_EVENT Event;
2454
2455 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
2456
2457 /* Caused by an injected interrupt. */
2458 pVCpu->hwaccm.s.Event.fPending = false;
2459
2460 switch (Event.n.u3Type)
2461 {
2462 case SVM_EVENT_EXTERNAL_IRQ:
2463 case SVM_EVENT_NMI:
2464 Log(("SVM_EXIT_TASK_SWITCH: reassert trap %d\n", Event.n.u8Vector));
2465 Assert(!Event.n.u1ErrorCodeValid);
2466 rc2 = TRPMAssertTrap(pVCpu, Event.n.u8Vector, TRPM_HARDWARE_INT);
2467 AssertRC(rc2);
2468 break;
2469
2470 default:
2471 /* Exceptions and software interrupts can just be restarted. */
2472 break;
2473 }
2474 }
2475 rc = VERR_EM_INTERPRETER;
2476 break;
2477
2478 case SVM_EXIT_PAUSE:
2479 case SVM_EXIT_MWAIT_ARMED:
2480 rc = VERR_EM_INTERPRETER;
2481 break;
2482
2483 case SVM_EXIT_SHUTDOWN:
2484 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2485 break;
2486
2487 case SVM_EXIT_IDTR_READ:
2488 case SVM_EXIT_GDTR_READ:
2489 case SVM_EXIT_LDTR_READ:
2490 case SVM_EXIT_TR_READ:
2491 case SVM_EXIT_IDTR_WRITE:
2492 case SVM_EXIT_GDTR_WRITE:
2493 case SVM_EXIT_LDTR_WRITE:
2494 case SVM_EXIT_TR_WRITE:
2495 case SVM_EXIT_CR0_SEL_WRITE:
2496 default:
2497 /* Unexpected exit codes. */
2498 rc = VERR_EM_INTERNAL_ERROR;
2499 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2500 break;
2501 }
2502
2503end:
2504
2505 /* Signal changes for the recompiler. */
2506 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2507
2508 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2509 if (exitCode == SVM_EXIT_INTR)
2510 {
2511 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2512 /* On the next entry we'll only sync the host context. */
2513 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2514 }
2515 else
2516 {
2517 /* On the next entry we'll sync everything. */
2518 /** @todo we can do better than this */
2519 /* Not in the VINF_PGM_CHANGE_MODE though! */
2520 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2521 }
2522
2523 /* translate into a less severe return code */
2524 if (rc == VERR_EM_INTERPRETER)
2525 rc = VINF_EM_RAW_EMULATE_INSTR;
2526
2527 /* Just set the correct state here instead of trying to catch every goto above. */
2528 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2529
2530#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2531 /* Restore interrupts if we exitted after disabling them. */
2532 if (uOldEFlags != ~(RTCCUINTREG)0)
2533 ASMSetFlags(uOldEFlags);
2534#endif
2535
2536 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, x);
2537 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2538 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
2539 return VBOXSTRICTRC_TODO(rc);
2540}
2541
2542/**
2543 * Emulate simple mov tpr instruction
2544 *
2545 * @returns VBox status code.
2546 * @param pVM The VM to operate on.
2547 * @param pVCpu The VM CPU to operate on.
2548 * @param pCtx CPU context
2549 */
2550static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2551{
2552 int rc;
2553
2554 LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2555
2556 while (true)
2557 {
2558 bool fPending;
2559 uint8_t u8Tpr;
2560
2561 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2562 if (!pPatch)
2563 break;
2564
2565 switch(pPatch->enmType)
2566 {
2567 case HWACCMTPRINSTR_READ:
2568 /* TPR caching in CR8 */
2569 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2570 AssertRC(rc);
2571
2572 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2573 AssertRC(rc);
2574
2575 LogFlow(("Emulated read successfully\n"));
2576 pCtx->rip += pPatch->cbOp;
2577 break;
2578
2579 case HWACCMTPRINSTR_WRITE_REG:
2580 case HWACCMTPRINSTR_WRITE_IMM:
2581 /* Fetch the new TPR value */
2582 if (pPatch->enmType == HWACCMTPRINSTR_WRITE_REG)
2583 {
2584 uint32_t val;
2585
2586 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2587 AssertRC(rc);
2588 u8Tpr = val;
2589 }
2590 else
2591 u8Tpr = (uint8_t)pPatch->uSrcOperand;
2592
2593 rc = PDMApicSetTPR(pVCpu, u8Tpr);
2594 AssertRC(rc);
2595 LogFlow(("Emulated write successfully\n"));
2596 pCtx->rip += pPatch->cbOp;
2597 break;
2598 default:
2599 AssertMsgFailedReturn(("Unexpected type %d\n", pPatch->enmType), VERR_INTERNAL_ERROR);
2600 }
2601 }
2602 return VINF_SUCCESS;
2603}
2604
2605
2606/**
2607 * Enters the AMD-V session
2608 *
2609 * @returns VBox status code.
2610 * @param pVM The VM to operate on.
2611 * @param pVCpu The VM CPU to operate on.
2612 * @param pCpu CPU info struct
2613 */
2614VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2615{
2616 Assert(pVM->hwaccm.s.svm.fSupported);
2617
2618 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2619 pVCpu->hwaccm.s.fResumeVM = false;
2620
2621 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2622 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
2623
2624 return VINF_SUCCESS;
2625}
2626
2627
2628/**
2629 * Leaves the AMD-V session
2630 *
2631 * @returns VBox status code.
2632 * @param pVM The VM to operate on.
2633 * @param pVCpu The VM CPU to operate on.
2634 * @param pCtx CPU context
2635 */
2636VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2637{
2638 SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2639
2640 Assert(pVM->hwaccm.s.svm.fSupported);
2641
2642#ifdef DEBUG
2643 if (CPUMIsHyperDebugStateActive(pVCpu))
2644 {
2645 CPUMR0LoadHostDebugState(pVM, pVCpu);
2646 }
2647 else
2648#endif
2649 /* Save the guest debug state if necessary. */
2650 if (CPUMIsGuestDebugStateActive(pVCpu))
2651 {
2652 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2653
2654 /* Intercept all DRx reads and writes again. Changed later on. */
2655 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2656 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2657
2658 /* Resync the debug registers the next time. */
2659 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2660 }
2661 else
2662 Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2663
2664 return VINF_SUCCESS;
2665}
2666
2667
2668static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2669{
2670 OP_PARAMVAL param1;
2671 RTGCPTR addr;
2672
2673 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2674 if(RT_FAILURE(rc))
2675 return VERR_EM_INTERPRETER;
2676
2677 switch(param1.type)
2678 {
2679 case PARMTYPE_IMMEDIATE:
2680 case PARMTYPE_ADDRESS:
2681 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
2682 return VERR_EM_INTERPRETER;
2683 addr = param1.val.val64;
2684 break;
2685
2686 default:
2687 return VERR_EM_INTERPRETER;
2688 }
2689
2690 /** @todo is addr always a flat linear address or ds based
2691 * (in absence of segment override prefixes)????
2692 */
2693 rc = PGMInvalidatePage(pVCpu, addr);
2694 if (RT_SUCCESS(rc))
2695 return VINF_SUCCESS;
2696
2697 AssertRC(rc);
2698 return rc;
2699}
2700
2701/**
2702 * Interprets INVLPG
2703 *
2704 * @returns VBox status code.
2705 * @retval VINF_* Scheduling instructions.
2706 * @retval VERR_EM_INTERPRETER Something we can't cope with.
2707 * @retval VERR_* Fatal errors.
2708 *
2709 * @param pVM The VM handle.
2710 * @param pRegFrame The register frame.
2711 * @param ASID Tagged TLB id for the guest
2712 *
2713 * Updates the EIP if an instruction was executed successfully.
2714 */
2715static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2716{
2717 /*
2718 * Only allow 32 & 64 bits code.
2719 */
2720 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2721 if (enmMode != CPUMODE_16BIT)
2722 {
2723 RTGCPTR pbCode;
2724 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
2725 &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2726 if (RT_SUCCESS(rc))
2727 {
2728 uint32_t cbOp;
2729 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2730
2731 pDis->mode = enmMode;
2732 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2733 Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
2734 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2735 {
2736 Assert(cbOp == pDis->opsize);
2737 rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2738 if (RT_SUCCESS(rc))
2739 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2740
2741 return rc;
2742 }
2743 }
2744 }
2745 return VERR_EM_INTERPRETER;
2746}
2747
2748
2749/**
2750 * Invalidates a guest page
2751 *
2752 * @returns VBox status code.
2753 * @param pVM The VM to operate on.
2754 * @param pVCpu The VM CPU to operate on.
2755 * @param GCVirt Page to invalidate
2756 */
2757VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2758{
2759 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
2760
2761 /* Skip it if a TLB flush is already pending. */
2762 if (!fFlushPending)
2763 {
2764 SVM_VMCB *pVMCB;
2765
2766 Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2767 AssertReturn(pVM, VERR_INVALID_PARAMETER);
2768 Assert(pVM->hwaccm.s.svm.fSupported);
2769
2770 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2771 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2772
2773#if HC_ARCH_BITS == 32
2774 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2775 if (CPUMIsGuestInLongMode(pVCpu))
2776 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2777 else
2778#endif
2779 SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2780 }
2781 return VINF_SUCCESS;
2782}
2783
2784
2785#if 0 /* obsolete, but left here for clarification. */
2786/**
2787 * Invalidates a guest page by physical address
2788 *
2789 * @returns VBox status code.
2790 * @param pVM The VM to operate on.
2791 * @param pVCpu The VM CPU to operate on.
2792 * @param GCPhys Page to invalidate
2793 */
2794VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2795{
2796 Assert(pVM->hwaccm.s.fNestedPaging);
2797 /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2798 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2799 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2800 return VINF_SUCCESS;
2801}
2802#endif
2803
2804#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2805/**
2806 * Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2807 *
2808 * @returns VBox status code.
2809 * @param pVMCBHostPhys Physical address of host VMCB.
2810 * @param pVMCBPhys Physical address of the VMCB.
2811 * @param pCtx Guest context.
2812 * @param pVM The VM to operate on.
2813 * @param pVCpu The VMCPU to operate on.
2814 */
2815DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2816{
2817 uint32_t aParam[4];
2818
2819 aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2820 aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2821 aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2822 aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2823
2824 return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2825}
2826
2827/**
2828 * Executes the specified handler in 64 mode
2829 *
2830 * @returns VBox status code.
2831 * @param pVM The VM to operate on.
2832 * @param pVCpu The VMCPU to operate on.
2833 * @param pCtx Guest context
2834 * @param pfnHandler RC handler
2835 * @param cbParam Number of parameters
2836 * @param paParam Array of 32 bits parameters
2837 */
2838VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2839{
2840 int rc;
2841 RTHCUINTREG uOldEFlags;
2842
2843 Assert(pfnHandler);
2844
2845 /* Disable interrupts. */
2846 uOldEFlags = ASMIntDisableFlags();
2847
2848 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
2849 CPUMSetHyperEIP(pVCpu, pfnHandler);
2850 for (int i=(int)cbParam-1;i>=0;i--)
2851 CPUMPushHyper(pVCpu, paParam[i]);
2852
2853 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2854 /* Call switcher. */
2855 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
2856 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2857
2858 ASMSetFlags(uOldEFlags);
2859 return rc;
2860}
2861
2862#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
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