HWVMXR0.cpp@ 7932

Last change on this file since 7932 was 7717, checked in by vboxsync, 17 years ago
Some write protect changes
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1	/* $Id: HWVMXR0.cpp 7717 2008-04-03 09:54:12Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HWACCM
23	#include <VBox/hwaccm.h>
24	#include "HWACCMInternal.h"
25	#include <VBox/vm.h>
26	#include <VBox/x86.h>
27	#include <VBox/pgm.h>
28	#include <VBox/pdm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <VBox/selm.h>
32	#include <VBox/iom.h>
33	#include <iprt/param.h>
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36	#include <iprt/string.h>
37	#include "HWVMXR0.h"
38
39
40	/* IO operation lookup arrays. */
41	static uint32_t aIOSize[4] = {1, 2, 0, 4};
42	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
43
44
45	static void VMXR0CheckError(PVM pVM, int rc)
46	{
47	if (rc == VERR_VMX_GENERIC)
48	{
49	RTCCUINTREG instrError;
50
51	VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
52	pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
53	}
54	pVM->hwaccm.s.lLastError = rc;
55	}
56
57	/**
58	* Sets up and activates VT-x on the current CPU
59	*
60	* @returns VBox status code.
61	* @param idCpu The identifier for the CPU the function is called on.
62	* @param pVM The VM to operate on.
63	* @param pvPageCpu Pointer to the global cpu page
64	* @param pPageCpuPhys Physical address of the global cpu page
65	*/
66	HWACCMR0DECL(int) VMXR0EnableCpu(RTCPUID idCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
67	{
68	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
69	AssertReturn(pVM, VERR_INVALID_PARAMETER);
70	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
71
72	/* Setup Intel VMX. */
73	Assert(pVM->hwaccm.s.vmx.fSupported);
74
75	#ifdef LOG_ENABLED
76	SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
77	#endif
78	/* Set revision dword at the beginning of the VMXON structure. */
79	(uint32_t )pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
80
81	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
82	* (which can have very bad consequences!!!)
83	*/
84
85	/* Make sure the VMX instructions don't cause #UD faults. */
86	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
87
88	/* Enter VMX Root Mode */
89	int rc = VMXEnable(pPageCpuPhys);
90	if (VBOX_FAILURE(rc))
91	{
92	VMXR0CheckError(pVM, rc);
93	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
94	return VERR_VMX_VMXON_FAILED;
95	}
96	return VINF_SUCCESS;
97	}
98
99	/**
100	* Deactivates VT-x on the current CPU
101	*
102	* @returns VBox status code.
103	* @param idCpu The identifier for the CPU the function is called on.
104	* @param pvPageCpu Pointer to the global cpu page
105	* @param pPageCpuPhys Physical address of the global cpu page
106	*/
107	HWACCMR0DECL(int) VMXR0DisableCpu(RTCPUID idCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
108	{
109	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
110	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
111
112	/* Leave VMX Root Mode. */
113	VMXDisable();
114
115	/* And clear the X86_CR4_VMXE bit */
116	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
117
118	#ifdef LOG_ENABLED
119	SUPR0Printf("VMXR0DisableCpu cpu %d\n", idCpu);
120	#endif
121	return VINF_SUCCESS;
122	}
123
124	/**
125	* Does Ring-0 per VM VT-x init.
126	*
127	* @returns VBox status code.
128	* @param pVM The VM to operate on.
129	*/
130	HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
131	{
132	int rc;
133
134	#ifdef LOG_ENABLED
135	SUPR0Printf("VMXR0InitVM %x\n", pVM);
136	#endif
137
138	/* Allocate one page for the VM control structure (VMCS). */
139	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
140	AssertRC(rc);
141	if (RT_FAILURE(rc))
142	return rc;
143
144	pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
145	pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
146	ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
147
148	/* Allocate one page for the TSS we need for real mode emulation. */
149	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
150	AssertRC(rc);
151	if (RT_FAILURE(rc))
152	return rc;
153
154	pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
155	pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
156
157	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
158	* for I/O operations. */
159	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
160	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
161	/* Bit set to 0 means redirection enabled. */
162	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
163
164	#ifdef LOG_ENABLED
165	SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
166	#endif
167	return VINF_SUCCESS;
168	}
169
170	/**
171	* Does Ring-0 per VM VT-x termination.
172	*
173	* @returns VBox status code.
174	* @param pVM The VM to operate on.
175	*/
176	HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
177	{
178	if (pVM->hwaccm.s.vmx.pMemObjVMCS)
179	{
180	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
181	pVM->hwaccm.s.vmx.pMemObjVMCS = 0;
182	pVM->hwaccm.s.vmx.pVMCS = 0;
183	pVM->hwaccm.s.vmx.pVMCSPhys = 0;
184	}
185	if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS)
186	{
187	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
188	pVM->hwaccm.s.vmx.pMemObjRealModeTSS = 0;
189	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
190	pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
191	}
192	return VINF_SUCCESS;
193	}
194
195	/**
196	* Sets up VT-x for the specified VM
197	*
198	* @returns VBox status code.
199	* @param pVM The VM to operate on.
200	*/
201	HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
202	{
203	int rc = VINF_SUCCESS;
204	uint32_t val;
205
206	AssertReturn(pVM, VERR_INVALID_PARAMETER);
207	Assert(pVM->hwaccm.s.vmx.pVMCS);
208
209	/* Set revision dword at the beginning of the VMCS structure. */
210	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
211
212	/* Clear VM Control Structure. */
213	Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
214	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
215	if (VBOX_FAILURE(rc))
216	goto vmx_end;
217
218	/* Activate the VM Control Structure. */
219	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
220	if (VBOX_FAILURE(rc))
221	goto vmx_end;
222
223	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
224	* Set required bits to one and zero according to the MSR capabilities.
225	*/
226	val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
227	/* External and non-maskable interrupts cause VM-exits. */
228	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
229	val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
230
231	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
232	AssertRC(rc);
233
234	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
235	* Set required bits to one and zero according to the MSR capabilities.
236	*/
237	val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
238	/* Program which event cause VM-exits and which features we want to use. */
239	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
240	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
241	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
242	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
243	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
244	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
245
246	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
247
248	/*
249	if AMD64 guest mode
250	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
251	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
252	*/
253	#if HC_ARCH_BITS == 64
254	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
255	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
256	#endif
257	/* Mask away the bits that the CPU doesn't support */
258	/** @todo make sure they don't conflict with the above requirements. */
259	val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
260	pVM->hwaccm.s.vmx.proc_ctls = val;
261
262	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
263	AssertRC(rc);
264
265	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
266	* Set required bits to one and zero according to the MSR capabilities.
267	*/
268	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
269	AssertRC(rc);
270
271	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
272	* Set required bits to one and zero according to the MSR capabilities.
273	*/
274	val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
275	if (pVM->hwaccm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
276	{
277	/** @todo 32 bits guest mode only for now. */
278	/* val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE; */
279	}
280	/* Mask away the bits that the CPU doesn't support */
281	/** @todo make sure they don't conflict with the above requirements. */
282	val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
283	/* else Must be zero when AMD64 is not available. */
284	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
285	AssertRC(rc);
286
287	/* VMX_VMCS_CTRL_EXIT_CONTROLS
288	* Set required bits to one and zero according to the MSR capabilities.
289	*/
290	val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
291	#if HC_ARCH_BITS == 64
292	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
293	#else
294	/* else Must be zero when AMD64 is not available. */
295	#endif
296	val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
297	/* Don't acknowledge external interrupts on VM-exit. */
298	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
299	AssertRC(rc);
300
301	/* Forward all exception except #NM & #PF to the guest.
302	* We always need to check pagefaults since our shadow page table can be out of sync.
303	* And we always lazily sync the FPU & XMM state.
304	*/
305
306	/*
307	* @todo Possible optimization:
308	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
309	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
310	* registers ourselves of course.
311	*
312	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
313	*/
314	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
315	AssertRC(rc);
316
317	/* Don't filter page faults; all of them should cause a switch. */
318	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
319	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
320	AssertRC(rc);
321
322	/* Init TSC offset to zero. */
323	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
324	#if HC_ARCH_BITS == 32
325	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
326	#endif
327	AssertRC(rc);
328
329	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
330	#if HC_ARCH_BITS == 32
331	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
332	#endif
333	AssertRC(rc);
334
335	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
336	#if HC_ARCH_BITS == 32
337	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
338	#endif
339	AssertRC(rc);
340
341	/* Clear MSR controls. */
342	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
343	{
344	/* Optional */
345	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
346	#if HC_ARCH_BITS == 32
347	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
348	#endif
349	AssertRC(rc);
350	}
351	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
352	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
353	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
354	#if HC_ARCH_BITS == 32
355	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
356	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
357	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
358	#endif
359	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
360	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
361	AssertRC(rc);
362
363	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
364	{
365	/* Optional */
366	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
367	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
368	#if HC_ARCH_BITS == 32
369	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
370	#endif
371	AssertRC(rc);
372	}
373
374	/* Set link pointer to -1. Not currently used. */
375	#if HC_ARCH_BITS == 32
376	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
377	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
378	#else
379	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
380	#endif
381	AssertRC(rc);
382
383	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
384	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
385	AssertRC(rc);
386
387	vmx_end:
388	VMXR0CheckError(pVM, rc);
389	return rc;
390	}
391
392
393	/**
394	* Injects an event (trap or external interrupt)
395	*
396	* @returns VBox status code.
397	* @param pVM The VM to operate on.
398	* @param pCtx CPU Context
399	* @param intInfo VMX interrupt info
400	* @param cbInstr Opcode length of faulting instruction
401	* @param errCode Error code (optional)
402	*/
403	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
404	{
405	int rc;
406
407	#ifdef VBOX_STRICT
408	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
409	if (iGate == 0xE)
410	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->eip, errCode, pCtx->cr2, intInfo));
411	else
412	if (iGate < 0x20)
413	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->eip, errCode));
414	else
415	{
416	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->eip));
417	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
418	Assert(pCtx->eflags.u32 & X86_EFL_IF);
419	}
420	#endif
421
422	/* Set event injection state. */
423	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
424	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
425	);
426
427	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
428	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
429
430	AssertRC(rc);
431	return rc;
432	}
433
434
435	/**
436	* Checks for pending guest interrupts and injects them
437	*
438	* @returns VBox status code.
439	* @param pVM The VM to operate on.
440	* @param pCtx CPU Context
441	*/
442	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
443	{
444	int rc;
445
446	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
447	if (pVM->hwaccm.s.Event.fPending)
448	{
449	Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
450	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
451	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
452	AssertRC(rc);
453
454	pVM->hwaccm.s.Event.fPending = false;
455	return VINF_SUCCESS;
456	}
457
458	/* When external interrupts are pending, we should exit the VM when IF is set. */
459	if ( !TRPMHasTrap(pVM)
460	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
461	{
462	if (!(pCtx->eflags.u32 & X86_EFL_IF))
463	{
464	Log2(("Enable irq window exit!\n"));
465	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
466	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
467	AssertRC(rc);
468	}
469	else
470	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
471	{
472	uint8_t u8Interrupt;
473
474	rc = PDMGetInterrupt(pVM, &u8Interrupt);
475	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
476	if (VBOX_SUCCESS(rc))
477	{
478	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
479	AssertRC(rc);
480	}
481	else
482	{
483	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
484	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
485	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
486	/* Just continue */
487	}
488	}
489	else
490	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
491	}
492
493	#ifdef VBOX_STRICT
494	if (TRPMHasTrap(pVM))
495	{
496	uint8_t u8Vector;
497	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
498	AssertRC(rc);
499	}
500	#endif
501
502	if ( pCtx->eflags.u32 & X86_EFL_IF
503	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
504	&& TRPMHasTrap(pVM)
505	)
506	{
507	uint8_t u8Vector;
508	int rc;
509	TRPMEVENT enmType;
510	RTGCUINTPTR intInfo, errCode;
511
512	/* If a new event is pending, then dispatch it now. */
513	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
514	AssertRC(rc);
515	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
516	Assert(enmType != TRPM_SOFTWARE_INT);
517
518	/* Clear the pending trap. */
519	rc = TRPMResetTrap(pVM);
520	AssertRC(rc);
521
522	intInfo = u8Vector;
523	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
524
525	if (enmType == TRPM_TRAP)
526	{
527	switch (u8Vector) {
528	case 8:
529	case 10:
530	case 11:
531	case 12:
532	case 13:
533	case 14:
534	case 17:
535	/* Valid error codes. */
536	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
537	break;
538	default:
539	break;
540	}
541	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
542	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
543	else
544	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
545	}
546	else
547	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
548
549	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
550	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
551	AssertRC(rc);
552	} /* if (interrupts can be dispatched) */
553
554	return VINF_SUCCESS;
555	}
556
557	/**
558	* Save the host state
559	*
560	* @returns VBox status code.
561	* @param pVM The VM to operate on.
562	*/
563	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
564	{
565	int rc = VINF_SUCCESS;
566
567	/*
568	* Host CPU Context
569	*/
570	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
571	{
572	RTIDTR idtr;
573	RTGDTR gdtr;
574	RTSEL SelTR;
575	PX86DESCHC pDesc;
576	uintptr_t trBase;
577
578	/* Control registers */
579	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
580	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
581	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
582	AssertRC(rc);
583	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
584	Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
585	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
586
587	/* Selector registers. */
588	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
589	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
590	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
591	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
592	#if HC_ARCH_BITS == 32
593	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
594	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
595	#endif
596	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
597	SelTR = ASMGetTR();
598	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
599	AssertRC(rc);
600	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
601	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
602	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
603	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
604	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
605	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
606	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
607
608	/* GDTR & IDTR */
609	ASMGetGDTR(&gdtr);
610	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
611	ASMGetIDTR(&idtr);
612	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
613	AssertRC(rc);
614	Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
615	Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
616
617	/* Save the base address of the TR selector. */
618	if (SelTR > gdtr.cbGdt)
619	{
620	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
621	return VERR_VMX_INVALID_HOST_STATE;
622	}
623
624	pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
625	#if HC_ARCH_BITS == 64
626	trBase = pDesc->Gen.u16BaseLow \| (pDesc->Gen.u8BaseHigh1 << 16ULL) \| (pDesc->Gen.u8BaseHigh2 << 24ULL) \| ((uintptr_t)pDesc->Gen.u32BaseHigh3 << 32ULL);
627	#else
628	trBase = pDesc->Gen.u16BaseLow \| (pDesc->Gen.u8BaseHigh1 << 16) \| (pDesc->Gen.u8BaseHigh2 << 24);
629	#endif
630	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
631	AssertRC(rc);
632	Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
633
634	/* FS and GS base. */
635	#if HC_ARCH_BITS == 64
636	Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
637	Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
638	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
639	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
640	#endif
641	AssertRC(rc);
642
643	/* Sysenter MSRs. */
644	/** @todo expensive!! */
645	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
646	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
647	#if HC_ARCH_BITS == 32
648	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
649	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
650	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
651	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
652	#else
653	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
654	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
655	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
656	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
657	#endif
658	AssertRC(rc);
659
660	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
661	}
662	return rc;
663	}
664
665
666	/**
667	* Loads the guest state
668	*
669	* @returns VBox status code.
670	* @param pVM The VM to operate on.
671	* @param pCtx Guest context
672	*/
673	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
674	{
675	int rc = VINF_SUCCESS;
676	RTGCUINTPTR val;
677	X86EFLAGS eflags;
678
679	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
680	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
681	{
682	VMX_WRITE_SELREG(ES, es);
683	AssertRC(rc);
684
685	VMX_WRITE_SELREG(CS, cs);
686	AssertRC(rc);
687
688	VMX_WRITE_SELREG(SS, ss);
689	AssertRC(rc);
690
691	VMX_WRITE_SELREG(DS, ds);
692	AssertRC(rc);
693
694	VMX_WRITE_SELREG(FS, fs);
695	AssertRC(rc);
696
697	VMX_WRITE_SELREG(GS, gs);
698	AssertRC(rc);
699	}
700
701	/* Guest CPU context: LDTR. */
702	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
703	{
704	if (pCtx->ldtr == 0)
705	{
706	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
707	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
708	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
709	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
710	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
711	}
712	else
713	{
714	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
715	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
716	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u32Base);
717	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
718	}
719	AssertRC(rc);
720	}
721	/* Guest CPU context: TR. */
722	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
723	{
724	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
725
726	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
727	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
728	{
729	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
730	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
731	}
732	else
733	{
734	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
735	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u32Base);
736	}
737	val = pCtx->trHid.Attr.u;
738
739	/* The TSS selector must be busy. */
740	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
741	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
742	else
743	/* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
744	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
745
746	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
747	AssertRC(rc);
748	}
749	/* Guest CPU context: GDTR. */
750	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
751	{
752	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
753	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
754	AssertRC(rc);
755	}
756	/* Guest CPU context: IDTR. */
757	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
758	{
759	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
760	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
761	AssertRC(rc);
762	}
763
764	/*
765	* Sysenter MSRs
766	*/
767	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
768	{
769	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
770	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
771	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
772	AssertRC(rc);
773	}
774
775	/* Control registers */
776	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
777	{
778	val = pCtx->cr0;
779	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
780	Log2(("Guest CR0-shadow %08x\n", val));
781	if (CPUMIsGuestFPUStateActive(pVM) == false)
782	{
783	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
784	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
785	}
786	else
787	{
788	Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
789	/** @todo check if we support the old style mess correctly. */
790	if (!(val & X86_CR0_NE))
791	{
792	Log(("Forcing X86_CR0_NE!!!\n"));
793
794	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
795	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
796	{
797	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| RT_BIT(16));
798	AssertRC(rc);
799	pVM->hwaccm.s.fFPUOldStyleOverride = true;
800	}
801	}
802
803	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
804	}
805	/* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
806	val \|= X86_CR0_PE \| X86_CR0_PG;
807	/* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
808	val \|= X86_CR0_WP;
809
810	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
811	Log2(("Guest CR0 %08x\n", val));
812	/* CR0 flags owned by the host; if the guests attempts to change them, then
813	* the VM will exit.
814	*/
815	val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
816	\| X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
817	\| X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
818	\| X86_CR0_TS
819	\| X86_CR0_ET
820	\| X86_CR0_NE
821	\| X86_CR0_MP;
822	pVM->hwaccm.s.vmx.cr0_mask = val;
823
824	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
825	Log2(("Guest CR0-mask %08x\n", val));
826	AssertRC(rc);
827	}
828	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
829	{
830	/* CR4 */
831	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
832	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
833	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
834	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
835	switch(pVM->hwaccm.s.enmShadowMode)
836	{
837	case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
838	case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
839	case PGMMODE_32_BIT: /* 32-bit paging. */
840	break;
841
842	case PGMMODE_PAE: /* PAE paging. */
843	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
844	/** @todo use normal 32 bits paging */
845	val \|= X86_CR4_PAE;
846	break;
847
848	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
849	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
850	AssertFailed();
851	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
852
853	default: /* shut up gcc */
854	AssertFailed();
855	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
856	}
857	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
858	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
859	val \|= X86_CR4_VME;
860
861	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
862	Log2(("Guest CR4 %08x\n", val));
863	/* CR4 flags owned by the host; if the guests attempts to change them, then
864	* the VM will exit.
865	*/
866	val = X86_CR4_PAE
867	\| X86_CR4_PGE
868	\| X86_CR4_PSE
869	\| X86_CR4_VMXE;
870	pVM->hwaccm.s.vmx.cr4_mask = val;
871
872	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
873	Log2(("Guest CR4-mask %08x\n", val));
874	AssertRC(rc);
875	}
876
877	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
878	{
879	/* Save our shadow CR3 register. */
880	val = PGMGetHyperCR3(pVM);
881	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
882	AssertRC(rc);
883	}
884
885	/* Debug registers. */
886	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
887	{
888	/** @todo DR0-6 */
889	val = pCtx->dr7;
890	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
891	val \|= 0x400; /* must be one */
892	#ifdef VBOX_STRICT
893	val = 0x400;
894	#endif
895	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
896	AssertRC(rc);
897
898	/* IA32_DEBUGCTL MSR. */
899	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
900	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
901	AssertRC(rc);
902
903	/** @todo */
904	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
905	AssertRC(rc);
906	}
907
908	/* EIP, ESP and EFLAGS */
909	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->eip);
910	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->esp);
911	AssertRC(rc);
912
913	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
914	eflags = pCtx->eflags;
915	eflags.u32 &= VMX_EFLAGS_RESERVED_0;
916	eflags.u32 \|= VMX_EFLAGS_RESERVED_1;
917
918	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
919	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
920	{
921	eflags.Bits.u1VM = 1;
922	eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
923	eflags.Bits.u2IOPL = 3;
924	}
925
926	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
927	AssertRC(rc);
928
929	/** TSC offset. */
930	uint64_t u64TSCOffset;
931
932	if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
933	{
934	/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
935	#if HC_ARCH_BITS == 64
936	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
937	#else
938	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
939	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
940	#endif
941	AssertRC(rc);
942
943	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
944	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
945	AssertRC(rc);
946	}
947	else
948	{
949	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
950	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
951	AssertRC(rc);
952	}
953
954	/* Done. */
955	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
956
957	return rc;
958	}
959
960	/**
961	* Runs guest code in a VMX VM.
962	*
963	* @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
964	*
965	* @returns VBox status code.
966	* @param pVM The VM to operate on.
967	* @param pCtx Guest context
968	*/
969	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
970	{
971	int rc = VINF_SUCCESS;
972	RTCCUINTREG val, valShadow;
973	RTCCUINTREG exitReason, instrError, cbInstr;
974	RTGCUINTPTR exitQualification;
975	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
976	RTGCUINTPTR errCode, instrInfo, uInterruptState;
977	bool fGuestStateSynced = false;
978	unsigned cResume = 0;
979
980	Log2(("\nE"));
981
982	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
983
984	#ifdef VBOX_STRICT
985	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
986	AssertRC(rc);
987	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
988
989	/* allowed zero */
990	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
991	{
992	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
993	}
994	/* allowed one */
995	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
996	{
997	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
998	}
999
1000	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1001	AssertRC(rc);
1002	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1003
1004	/* allowed zero */
1005	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
1006	{
1007	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1008	}
1009	/* allowed one */
1010	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
1011	{
1012	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1013	}
1014
1015	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1016	AssertRC(rc);
1017	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1018
1019	/* allowed zero */
1020	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
1021	{
1022	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1023	}
1024	/* allowed one */
1025	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
1026	{
1027	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1028	}
1029
1030	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1031	AssertRC(rc);
1032	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1033
1034	/* allowed zero */
1035	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
1036	{
1037	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1038	}
1039	/* allowed one */
1040	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
1041	{
1042	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1043	}
1044	#endif
1045
1046	#if 0
1047	/*
1048	* Check if debug registers are armed.
1049	*/
1050	uint32_t u32DR7 = ASMGetDR7();
1051	if (u32DR7 & X86_DR7_ENABLED_MASK)
1052	{
1053	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
1054	}
1055	else
1056	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
1057	#endif
1058
1059	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1060	*/
1061	ResumeExecution:
1062	/* Safety precaution; looping for too long here can have a very bad effect on the host */
1063	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1064	{
1065	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1066	rc = VINF_EM_RAW_INTERRUPT;
1067	goto end;
1068	}
1069
1070	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1071	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1072	{
1073	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
1074	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
1075	{
1076	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1077	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1078	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1079	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1080	*/
1081	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1082	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1083	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1084	AssertRC(rc);
1085	}
1086	}
1087	else
1088	{
1089	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1090	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1091	AssertRC(rc);
1092	}
1093
1094	/* Check for pending actions that force us to go back to ring 3. */
1095	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
1096	{
1097	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1098	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1099	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1100	rc = VINF_EM_RAW_TO_R3;
1101	goto end;
1102	}
1103	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1104	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1105	{
1106	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1107	rc = VINF_EM_PENDING_REQUEST;
1108	goto end;
1109	}
1110
1111	/* When external interrupts are pending, we should exit the VM when IF is set. */
1112	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
1113	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1114	if (VBOX_FAILURE(rc))
1115	{
1116	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1117	goto end;
1118	}
1119
1120	/** @todo check timers?? */
1121
1122	/* Save the host state first. */
1123	rc = VMXR0SaveHostState(pVM);
1124	if (rc != VINF_SUCCESS)
1125	{
1126	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1127	goto end;
1128	}
1129	/* Load the guest state */
1130	rc = VMXR0LoadGuestState(pVM, pCtx);
1131	if (rc != VINF_SUCCESS)
1132	{
1133	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1134	goto end;
1135	}
1136	fGuestStateSynced = true;
1137
1138	/* Non-register state Guest Context */
1139	/** @todo change me according to cpu state */
1140	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1141	AssertRC(rc);
1142
1143	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1144
1145	/* Manual save and restore:
1146	* - General purpose registers except RIP, RSP
1147	*
1148	* Trashed:
1149	* - CR2 (we don't care)
1150	* - LDTR (reset to 0)
1151	* - DRx (presumably not changed at all)
1152	* - DR7 (reset to 0x400)
1153	* - EFLAGS (reset to RT_BIT(1); not relevant)
1154	*
1155	*/
1156
1157	/* All done! Let's start VM execution. */
1158	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1159	if (pVM->hwaccm.s.vmx.fResumeVM == false)
1160	rc = VMXStartVM(pCtx);
1161	else
1162	rc = VMXResumeVM(pCtx);
1163
1164	/* In case we execute a goto ResumeExecution later on. */
1165	pVM->hwaccm.s.vmx.fResumeVM = true;
1166
1167	/**
1168	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1169	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1170	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1171	*/
1172
1173	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1174	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1175
1176	switch (rc)
1177	{
1178	case VINF_SUCCESS:
1179	break;
1180
1181	case VERR_VMX_INVALID_VMXON_PTR:
1182	AssertFailed();
1183	goto end;
1184
1185	case VERR_VMX_UNABLE_TO_START_VM:
1186	case VERR_VMX_UNABLE_TO_RESUME_VM:
1187	{
1188	#ifdef VBOX_STRICT
1189	int rc1;
1190
1191	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1192	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1193	AssertRC(rc1);
1194	if (rc1 == VINF_SUCCESS)
1195	{
1196	RTGDTR gdtr;
1197	PX86DESCHC pDesc;
1198
1199	ASMGetGDTR(&gdtr);
1200
1201	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1202	Log(("Current stack %08x\n", &rc1));
1203
1204
1205	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1206	Log(("Old eip %VGv new %VGv\n", pCtx->eip, (RTGCPTR)val));
1207	VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1208	Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1209	VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1210	Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1211	VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1212	Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1213	VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1214	Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1215
1216	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1217	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1218
1219	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1220	Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1221
1222	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1223	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1224
1225	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1226	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1227	if (val < gdtr.cbGdt)
1228	{
1229	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1230	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1231	}
1232
1233	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1234	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1235	if (val < gdtr.cbGdt)
1236	{
1237	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1238	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1239	}
1240
1241	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1242	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1243	if (val < gdtr.cbGdt)
1244	{
1245	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1246	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1247	}
1248
1249	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1250	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1251	if (val < gdtr.cbGdt)
1252	{
1253	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1254	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1255	}
1256
1257	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1258	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1259	if (val < gdtr.cbGdt)
1260	{
1261	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1262	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1263	}
1264
1265	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1266	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1267	if (val < gdtr.cbGdt)
1268	{
1269	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1270	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1271	}
1272
1273	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1274	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1275	if (val < gdtr.cbGdt)
1276	{
1277	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1278	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1279	}
1280
1281	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1282	Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1283
1284	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1285	Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1286	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1287	Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1288
1289	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1290	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1291
1292	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1293	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1294
1295	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1296	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1297
1298	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1299	Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1300	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1301	Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1302
1303	#if HC_ARCH_BITS == 64
1304	Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1305	Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1306	Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1307	Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1308	Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1309	#endif
1310	}
1311	#endif /* VBOX_STRICT */
1312	goto end;
1313	}
1314
1315	default:
1316	/* impossible */
1317	AssertFailed();
1318	goto end;
1319	}
1320	/* Success. Query the guest state and figure out what has happened. */
1321
1322	/* Investigate why there was a VM-exit. */
1323	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1324	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1325
1326	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1327	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1328	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1329	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1330	intInfo = val;
1331	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1332	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1333	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1334	instrInfo = val;
1335	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1336	exitQualification = val;
1337	AssertRC(rc);
1338
1339	/* Take care of instruction fusing (sti, mov ss) */
1340	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1341	uInterruptState = val;
1342	if (uInterruptState != 0)
1343	{
1344	Assert(uInterruptState <= 2); /* only sti & mov ss */
1345	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->eip));
1346	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1347	}
1348	else
1349	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1350
1351	/* Let's first sync back eip, esp, and eflags. */
1352	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1353	AssertRC(rc);
1354	pCtx->eip = val;
1355	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1356	AssertRC(rc);
1357	pCtx->esp = val;
1358	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1359	AssertRC(rc);
1360	pCtx->eflags.u32 = val;
1361
1362	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1363	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1364	{
1365	/* Hide our emulation flags */
1366	pCtx->eflags.Bits.u1VM = 0;
1367	pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1368	pCtx->eflags.Bits.u1VIF = 0;
1369	pCtx->eflags.Bits.u2IOPL = 0;
1370	}
1371
1372	/* Control registers. */
1373	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1374	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1375	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1376	CPUMSetGuestCR0(pVM, val);
1377
1378	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1379	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1380	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1381	CPUMSetGuestCR4(pVM, val);
1382
1383	CPUMSetGuestCR2(pVM, ASMGetCR2());
1384
1385	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1386	CPUMSetGuestDR7(pVM, val);
1387
1388	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1389	VMX_READ_SELREG(ES, es);
1390	VMX_READ_SELREG(SS, ss);
1391	VMX_READ_SELREG(CS, cs);
1392	VMX_READ_SELREG(DS, ds);
1393	VMX_READ_SELREG(FS, fs);
1394	VMX_READ_SELREG(GS, gs);
1395
1396	/** @note NOW IT'S SAFE FOR LOGGING! */
1397	Log2(("Raw exit reason %08x\n", exitReason));
1398
1399	/* Check if an injected event was interrupted prematurely. */
1400	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1401	AssertRC(rc);
1402	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1403	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1404	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1405	{
1406	Log(("Pending inject %VX64 at %08x exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitReason, intInfo, exitQualification));
1407	pVM->hwaccm.s.Event.fPending = true;
1408	/* Error code present? */
1409	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1410	{
1411	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1412	AssertRC(rc);
1413	pVM->hwaccm.s.Event.errCode = val;
1414	}
1415	else
1416	pVM->hwaccm.s.Event.errCode = 0;
1417	}
1418
1419	#ifdef VBOX_STRICT
1420	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1421	HWACCMDumpRegs(pCtx);
1422	#endif
1423
1424	Log2(("E%d", exitReason));
1425	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1426	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1427	Log2(("Interruption error code %d\n", errCode));
1428	Log2(("IntInfo = %08x\n", intInfo));
1429	Log2(("New EIP=%VGv\n", pCtx->eip));
1430
1431	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1432	switch (exitReason)
1433	{
1434	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1435	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1436	{
1437	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1438
1439	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1440	{
1441	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1442	/* External interrupt; leave to allow it to be dispatched again. */
1443	rc = VINF_EM_RAW_INTERRUPT;
1444	break;
1445	}
1446	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1447	{
1448	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1449	/* External interrupt; leave to allow it to be dispatched again. */
1450	rc = VINF_EM_RAW_INTERRUPT;
1451	break;
1452
1453	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1454	AssertFailed(); /* can't come here; fails the first check. */
1455	break;
1456
1457	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1458	Assert(vector == 3 \|\| vector == 4);
1459	/* no break */
1460	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1461	Log2(("Hardware/software interrupt %d\n", vector));
1462	switch (vector)
1463	{
1464	case X86_XCPT_NM:
1465	{
1466	uint32_t oldCR0;
1467
1468	Log(("#NM fault at %VGv error code %x\n", pCtx->eip, errCode));
1469
1470	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1471	oldCR0 = ASMGetCR0();
1472	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1473	rc = CPUMHandleLazyFPU(pVM);
1474	if (rc == VINF_SUCCESS)
1475	{
1476	Assert(CPUMIsGuestFPUStateActive(pVM));
1477
1478	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1479	ASMSetCR0(oldCR0);
1480
1481	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1482
1483	/* Continue execution. */
1484	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1485	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1486
1487	goto ResumeExecution;
1488	}
1489
1490	Log(("Forward #NM fault to the guest\n"));
1491	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1492	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1493	AssertRC(rc);
1494	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1495	goto ResumeExecution;
1496	}
1497
1498	case X86_XCPT_PF: /* Page fault */
1499	{
1500	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1501	/* Exit qualification contains the linear address of the page fault. */
1502	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1503	TRPMSetErrorCode(pVM, errCode);
1504	TRPMSetFaultAddress(pVM, exitQualification);
1505
1506	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1507	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1508	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1509	if (rc == VINF_SUCCESS)
1510	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1511	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, exitQualification ,errCode));
1512	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1513
1514	TRPMResetTrap(pVM);
1515
1516	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1517	goto ResumeExecution;
1518	}
1519	else
1520	if (rc == VINF_EM_RAW_GUEST_TRAP)
1521	{ /* A genuine pagefault.
1522	* Forward the trap to the guest by injecting the exception and resuming execution.
1523	*/
1524	Log2(("Forward page fault to the guest\n"));
1525	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1526	/* The error code might have been changed. */
1527	errCode = TRPMGetErrorCode(pVM);
1528
1529	TRPMResetTrap(pVM);
1530
1531	/* Now we must update CR2. */
1532	pCtx->cr2 = exitQualification;
1533	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1534	AssertRC(rc);
1535
1536	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1537	goto ResumeExecution;
1538	}
1539	#ifdef VBOX_STRICT
1540	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1541	Log2(("PGMTrap0eHandler failed with %d\n", rc));
1542	#endif
1543	/* Need to go back to the recompiler to emulate the instruction. */
1544	TRPMResetTrap(pVM);
1545	break;
1546	}
1547
1548	case X86_XCPT_MF: /* Floating point exception. */
1549	{
1550	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1551	if (!(pCtx->cr0 & X86_CR0_NE))
1552	{
1553	/* old style FPU error reporting needs some extra work. */
1554	/** @todo don't fall back to the recompiler, but do it manually. */
1555	rc = VINF_EM_RAW_EMULATE_INSTR;
1556	break;
1557	}
1558	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1559	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1560	AssertRC(rc);
1561
1562	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1563	goto ResumeExecution;
1564	}
1565
1566	#ifdef VBOX_STRICT
1567	case X86_XCPT_GP: /* General protection failure exception.*/
1568	case X86_XCPT_UD: /* Unknown opcode exception. */
1569	case X86_XCPT_DE: /* Debug exception. */
1570	case X86_XCPT_SS: /* Stack segment exception. */
1571	case X86_XCPT_NP: /* Segment not present exception. */
1572	{
1573	switch(vector)
1574	{
1575	case X86_XCPT_DE:
1576	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1577	break;
1578	case X86_XCPT_UD:
1579	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1580	break;
1581	case X86_XCPT_SS:
1582	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1583	break;
1584	case X86_XCPT_NP:
1585	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1586	break;
1587	case X86_XCPT_GP:
1588	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1589	break;
1590	}
1591
1592	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1593	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1594	AssertRC(rc);
1595
1596	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1597	goto ResumeExecution;
1598	}
1599	#endif
1600	default:
1601	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1602	rc = VERR_EM_INTERNAL_ERROR;
1603	break;
1604	} /* switch (vector) */
1605
1606	break;
1607
1608	default:
1609	rc = VERR_EM_INTERNAL_ERROR;
1610	AssertFailed();
1611	break;
1612	}
1613
1614	break;
1615	}
1616
1617	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1618	/* Clear VM-exit on IF=1 change. */
1619	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->eip));
1620	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1621	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1622	AssertRC(rc);
1623	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1624	goto ResumeExecution; /* we check for pending guest interrupts there */
1625
1626	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1627	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1628	/* Skip instruction and continue directly. */
1629	pCtx->eip += cbInstr;
1630	/* Continue execution.*/
1631	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1632	goto ResumeExecution;
1633
1634	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1635	{
1636	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1637	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1638	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1639	if (rc == VINF_SUCCESS)
1640	{
1641	/* Update EIP and continue execution. */
1642	Assert(cbInstr == 2);
1643	pCtx->eip += cbInstr;
1644	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1645	goto ResumeExecution;
1646	}
1647	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1648	rc = VINF_EM_RAW_EMULATE_INSTR;
1649	break;
1650	}
1651
1652	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1653	{
1654	Log2(("VMX: Rdtsc\n"));
1655	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1656	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1657	if (rc == VINF_SUCCESS)
1658	{
1659	/* Update EIP and continue execution. */
1660	Assert(cbInstr == 2);
1661	pCtx->eip += cbInstr;
1662	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1663	goto ResumeExecution;
1664	}
1665	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1666	rc = VINF_EM_RAW_EMULATE_INSTR;
1667	break;
1668	}
1669
1670	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1671	{
1672	Log2(("VMX: invlpg\n"));
1673	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1674	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1675	if (rc == VINF_SUCCESS)
1676	{
1677	/* Update EIP and continue execution. */
1678	pCtx->eip += cbInstr;
1679	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1680	goto ResumeExecution;
1681	}
1682	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1683	break;
1684	}
1685
1686	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1687	{
1688	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1689	{
1690	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1691	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->eip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1692	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1693	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1694	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1695	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1696
1697	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1698	{
1699	case 0:
1700	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1701	break;
1702	case 2:
1703	break;
1704	case 3:
1705	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1706	break;
1707	case 4:
1708	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1709	break;
1710	default:
1711	AssertFailed();
1712	}
1713	/* Check if a sync operation is pending. */
1714	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1715	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1716	{
1717	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1718	AssertRC(rc);
1719	}
1720	break;
1721
1722	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1723	Log2(("VMX: mov x, crx\n"));
1724	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1725	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1726	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1727	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1728	break;
1729
1730	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1731	Log2(("VMX: clts\n"));
1732	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1733	rc = EMInterpretCLTS(pVM);
1734	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1735	break;
1736
1737	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1738	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1739	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1740	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1741	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1742	break;
1743	}
1744
1745	/* Update EIP if no error occurred. */
1746	if (VBOX_SUCCESS(rc))
1747	pCtx->eip += cbInstr;
1748
1749	if (rc == VINF_SUCCESS)
1750	{
1751	/* Only resume if successful. */
1752	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1753	goto ResumeExecution;
1754	}
1755	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1756	break;
1757	}
1758
1759	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1760	{
1761	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1762	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1763	{
1764	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1765	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1766	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1767	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1768	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1769	Log2(("DR7=%08x\n", pCtx->dr7));
1770	}
1771	else
1772	{
1773	Log2(("VMX: mov x, drx\n"));
1774	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1775	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1776	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1777	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1778	}
1779	/* Update EIP if no error occurred. */
1780	if (VBOX_SUCCESS(rc))
1781	pCtx->eip += cbInstr;
1782
1783	if (rc == VINF_SUCCESS)
1784	{
1785	/* Only resume if successful. */
1786	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1787	goto ResumeExecution;
1788	}
1789	Assert(rc == VERR_EM_INTERPRETER);
1790	break;
1791	}
1792
1793	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1794	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1795	{
1796	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1797	uint32_t uPort;
1798	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1799
1800	/** @todo necessary to make the distinction? */
1801	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1802	{
1803	uPort = pCtx->edx & 0xffff;
1804	}
1805	else
1806	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1807
1808	/* paranoia */
1809	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
1810	{
1811	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1812	break;
1813	}
1814
1815	uint32_t cbSize = aIOSize[uIOWidth];
1816
1817	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1818	{
1819	/* ins/outs */
1820	uint32_t prefix = 0;
1821	if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1822	prefix \|= PREFIX_REP;
1823
1824	if (fIOWrite)
1825	{
1826	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1827	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1828	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1829	}
1830	else
1831	{
1832	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1833	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1834	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1835	}
1836	}
1837	else
1838	{
1839	/* normal in/out */
1840	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1841
1842	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1843
1844	if (fIOWrite)
1845	{
1846	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1847	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1848	}
1849	else
1850	{
1851	uint32_t u32Val = 0;
1852
1853	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1854	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1855	if (IOM_SUCCESS(rc))
1856	{
1857	/* Write back to the EAX register. */
1858	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1859	}
1860	}
1861	}
1862	/*
1863	* Handled the I/O return codes.
1864	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1865	*/
1866	if (IOM_SUCCESS(rc))
1867	{
1868	/* Update EIP and continue execution. */
1869	pCtx->eip += cbInstr;
1870	if (RT_LIKELY(rc == VINF_SUCCESS))
1871	{
1872	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1873	goto ResumeExecution;
1874	}
1875	break;
1876	}
1877
1878	#ifdef VBOX_STRICT
1879	if (rc == VINF_IOM_HC_IOPORT_READ)
1880	Assert(!fIOWrite);
1881	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1882	Assert(fIOWrite);
1883	else
1884	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1885	#endif
1886	break;
1887	}
1888
1889	default:
1890	/* The rest is handled after syncing the entire CPU state. */
1891	break;
1892	}
1893
1894	/* Note: the guest state isn't entirely synced back at this stage. */
1895
1896	/* Investigate why there was a VM-exit. (part 2) */
1897	switch (exitReason)
1898	{
1899	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1900	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1901	/* Already handled above. */
1902	break;
1903
1904	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1905	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1906	break;
1907
1908	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1909	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1910	rc = VINF_EM_RAW_INTERRUPT;
1911	AssertFailed(); /* Can't happen. Yet. */
1912	break;
1913
1914	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1915	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1916	rc = VINF_EM_RAW_INTERRUPT;
1917	AssertFailed(); /* Can't happen afaik. */
1918	break;
1919
1920	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1921	rc = VERR_EM_INTERPRETER;
1922	break;
1923
1924	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1925	/** Check if external interrupts are pending; if so, don't switch back. */
1926	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1927	{
1928	pCtx->eip++; /* skip hlt */
1929	goto ResumeExecution;
1930	}
1931
1932	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1933	break;
1934
1935	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1936	AssertFailed(); /* can't happen. */
1937	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1938	break;
1939
1940	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1941	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1942	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1943	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1944	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1945	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1946	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
1947	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
1948	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
1949	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
1950	/** @todo inject #UD immediately */
1951	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1952	break;
1953
1954	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1955	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1956	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1957	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1958	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1959	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1960	/* already handled above */
1961	AssertMsg( rc == VINF_PGM_CHANGE_MODE
1962	\|\| rc == VINF_EM_RAW_INTERRUPT
1963	\|\| rc == VERR_EM_INTERPRETER
1964	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
1965	\|\| rc == VINF_PGM_SYNC_CR3
1966	\|\| rc == VINF_IOM_HC_IOPORT_READ
1967	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
1968	\|\| rc == VINF_EM_RAW_GUEST_TRAP
1969	\|\| rc == VINF_TRPM_XCPT_DISPATCHED
1970	\|\| rc == VINF_EM_RESCHEDULE_REM,
1971	("rc = %d\n", rc));
1972	break;
1973
1974	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
1975	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1976	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1977	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
1978	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
1979	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
1980	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1981	break;
1982
1983	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1984	Assert(rc == VINF_EM_RAW_INTERRUPT);
1985	break;
1986
1987	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
1988	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
1989	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
1990	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
1991	default:
1992	rc = VERR_EM_INTERNAL_ERROR;
1993	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
1994	break;
1995
1996	}
1997	end:
1998	if (fGuestStateSynced)
1999	{
2000	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
2001	VMX_READ_SELREG(LDTR, ldtr);
2002	VMX_READ_SELREG(TR, tr);
2003
2004	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
2005	pCtx->gdtr.cbGdt = val;
2006	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2007	pCtx->gdtr.pGdt = val;
2008
2009	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
2010	pCtx->idtr.cbIdt = val;
2011	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2012	pCtx->idtr.pIdt = val;
2013
2014	/*
2015	* System MSRs
2016	*/
2017	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
2018	pCtx->SysEnter.cs = val;
2019	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
2020	pCtx->SysEnter.eip = val;
2021	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
2022	pCtx->SysEnter.esp = val;
2023	}
2024
2025	/* Signal changes for the recompiler. */
2026	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2027
2028	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2029	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2030	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2031	{
2032	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2033	/* On the next entry we'll only sync the host context. */
2034	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2035	}
2036	else
2037	{
2038	/* On the next entry we'll sync everything. */
2039	/** @todo we can do better than this */
2040	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2041	}
2042
2043	/* translate into a less severe return code */
2044	if (rc == VERR_EM_INTERPRETER)
2045	rc = VINF_EM_RAW_EMULATE_INSTR;
2046
2047	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2048	Log2(("X"));
2049	return rc;
2050	}
2051
2052
2053	/**
2054	* Enters the VT-x session
2055	*
2056	* @returns VBox status code.
2057	* @param pVM The VM to operate on.
2058	*/
2059	HWACCMR0DECL(int) VMXR0Enter(PVM pVM)
2060	{
2061	Assert(pVM->hwaccm.s.vmx.fSupported);
2062
2063	unsigned cr4 = ASMGetCR4();
2064	if (!(cr4 & X86_CR4_VMXE))
2065	{
2066	AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2067	return VERR_VMX_X86_CR4_VMXE_CLEARED;
2068	}
2069
2070	/* Activate the VM Control Structure. */
2071	int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2072	if (VBOX_FAILURE(rc))
2073	return rc;
2074
2075	pVM->hwaccm.s.vmx.fResumeVM = false;
2076	return VINF_SUCCESS;
2077	}
2078
2079
2080	/**
2081	* Leaves the VT-x session
2082	*
2083	* @returns VBox status code.
2084	* @param pVM The VM to operate on.
2085	*/
2086	HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2087	{
2088	Assert(pVM->hwaccm.s.vmx.fSupported);
2089
2090	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2091	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2092	AssertRC(rc);
2093
2094	return VINF_SUCCESS;
2095	}
2096

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 7932

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