VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 37319

Last change on this file since 37319 was 37319, checked in by vboxsync, 14 years ago

HWACCM: Use RTOnce to serialize the enabling so that no CPU can start execute code before it has been fully enabled to do so...
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1/* $Id: HWVMXR0.cpp 37319 2011-06-03 13:12:37Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HWACCM
23#include <iprt/asm-amd64-x86.h>
24#include <VBox/vmm/hwaccm.h>
25#include <VBox/vmm/pgm.h>
26#include <VBox/vmm/dbgf.h>
27#include <VBox/vmm/selm.h>
28#include <VBox/vmm/iom.h>
29#include <VBox/vmm/rem.h>
30#include <VBox/vmm/tm.h>
31#include "HWACCMInternal.h"
32#include <VBox/vmm/vm.h>
33#include <VBox/x86.h>
34#include <VBox/vmm/pdmapi.h>
35#include <VBox/err.h>
36#include <VBox/log.h>
37#include <iprt/assert.h>
38#include <iprt/param.h>
39#include <iprt/string.h>
40#include <iprt/time.h>
41#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
42# include <iprt/thread.h>
43#endif
44#include "HWVMXR0.h"
45
46/*******************************************************************************
47* Defined Constants And Macros *
48*******************************************************************************/
49#if defined(RT_ARCH_AMD64)
50# define VMX_IS_64BIT_HOST_MODE() (true)
51#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
52# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
53#else
54# define VMX_IS_64BIT_HOST_MODE() (false)
55#endif
56
57/*******************************************************************************
58* Global Variables *
59*******************************************************************************/
60/* IO operation lookup arrays. */
61static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
62static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
63
64#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
65/** See HWACCMR0A.asm. */
66extern "C" uint32_t g_fVMXIs64bitHost;
67#endif
68
69/*******************************************************************************
70* Local Functions *
71*******************************************************************************/
72static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc, PCPUMCTX pCtx);
73static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
74static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
75static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
76static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
77static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
78static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
79#ifdef VBOX_STRICT
80static bool vmxR0IsValidReadField(uint32_t idxField);
81static bool vmxR0IsValidWriteField(uint32_t idxField);
82#endif
83static void vmxR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
84
85static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
86{
87 if (rc == VERR_VMX_GENERIC)
88 {
89 RTCCUINTREG instrError;
90
91 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
92 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
93 }
94 pVM->hwaccm.s.lLastError = rc;
95}
96
97/**
98 * Sets up and activates VT-x on the current CPU
99 *
100 * @returns VBox status code.
101 * @param pCpu CPU info struct
102 * @param pVM The VM to operate on. (can be NULL after a resume!!)
103 * @param pvCpuPage Pointer to the global cpu page.
104 * @param HCPhysCpuPage Physical address of the global cpu page.
105 */
106VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
107{
108 AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
109 AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
110
111 if (pVM)
112 {
113 /* Set revision dword at the beginning of the VMXON structure. */
114 *(uint32_t *)pvCpuPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
115 }
116
117 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
118 * (which can have very bad consequences!!!)
119 */
120
121 if (ASMGetCR4() & X86_CR4_VMXE)
122 return VERR_VMX_IN_VMX_ROOT_MODE;
123
124 /* Make sure the VMX instructions don't cause #UD faults. */
125 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
126
127 /* Enter VMX Root Mode. */
128 int rc = VMXEnable(HCPhysCpuPage);
129 if (RT_FAILURE(rc))
130 {
131 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
132 return VERR_VMX_VMXON_FAILED;
133 }
134 return VINF_SUCCESS;
135}
136
137/**
138 * Deactivates VT-x on the current CPU
139 *
140 * @returns VBox status code.
141 * @param pCpu CPU info struct
142 * @param pvCpuPage Pointer to the global cpu page.
143 * @param HCPhysCpuPage Physical address of the global cpu page.
144 */
145VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
146{
147 AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
148 AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
149
150 /* If we're somehow not in VMX root mode, then we shouldn't dare leaving it. */
151 if (!(ASMGetCR4() & X86_CR4_VMXE))
152 return VERR_VMX_NOT_IN_VMX_ROOT_MODE;
153
154 /* Leave VMX Root Mode. */
155 VMXDisable();
156
157 /* And clear the X86_CR4_VMXE bit. */
158 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
159 return VINF_SUCCESS;
160}
161
162/**
163 * Does Ring-0 per VM VT-x init.
164 *
165 * @returns VBox status code.
166 * @param pVM The VM to operate on.
167 */
168VMMR0DECL(int) VMXR0InitVM(PVM pVM)
169{
170 int rc;
171
172#ifdef LOG_ENABLED
173 SUPR0Printf("VMXR0InitVM %x\n", pVM);
174#endif
175
176 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
177
178 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
179 {
180 /* Allocate one page for the APIC physical page (serves for filtering accesses). */
181 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
182 AssertRC(rc);
183 if (RT_FAILURE(rc))
184 return rc;
185
186 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
187 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
188 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
189 }
190 else
191 {
192 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
193 pVM->hwaccm.s.vmx.pAPIC = 0;
194 pVM->hwaccm.s.vmx.pAPICPhys = 0;
195 }
196
197#ifdef VBOX_WITH_CRASHDUMP_MAGIC
198 {
199 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
200 AssertRC(rc);
201 if (RT_FAILURE(rc))
202 return rc;
203
204 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
205 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
206
207 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
208 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
209 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
210 }
211#endif
212
213 /* Allocate VMCBs for all guest CPUs. */
214 for (VMCPUID i = 0; i < pVM->cCpus; i++)
215 {
216 PVMCPU pVCpu = &pVM->aCpus[i];
217
218 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
219
220 /* Allocate one page for the VM control structure (VMCS). */
221 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
222 AssertRC(rc);
223 if (RT_FAILURE(rc))
224 return rc;
225
226 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
227 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
228 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
229
230 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
231 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
232
233 /* Allocate one page for the virtual APIC page for TPR caching. */
234 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
235 AssertRC(rc);
236 if (RT_FAILURE(rc))
237 return rc;
238
239 pVCpu->hwaccm.s.vmx.pVAPIC = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVAPIC);
240 pVCpu->hwaccm.s.vmx.pVAPICPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 0);
241 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVAPIC, PAGE_SIZE);
242
243 /* Allocate the MSR bitmap if this feature is supported. */
244 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
245 {
246 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
247 AssertRC(rc);
248 if (RT_FAILURE(rc))
249 return rc;
250
251 pVCpu->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjMSRBitmap);
252 pVCpu->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
253 memset(pVCpu->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
254 }
255
256#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
257 /* Allocate one page for the guest MSR load area (for preloading guest MSRs during the world switch). */
258 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjGuestMSR, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
259 AssertRC(rc);
260 if (RT_FAILURE(rc))
261 return rc;
262
263 pVCpu->hwaccm.s.vmx.pGuestMSR = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjGuestMSR);
264 pVCpu->hwaccm.s.vmx.pGuestMSRPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjGuestMSR, 0);
265 memset(pVCpu->hwaccm.s.vmx.pGuestMSR, 0, PAGE_SIZE);
266
267 /* Allocate one page for the host MSR load area (for restoring host MSRs after the world switch back). */
268 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjHostMSR, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
269 AssertRC(rc);
270 if (RT_FAILURE(rc))
271 return rc;
272
273 pVCpu->hwaccm.s.vmx.pHostMSR = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjHostMSR);
274 pVCpu->hwaccm.s.vmx.pHostMSRPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjHostMSR, 0);
275 memset(pVCpu->hwaccm.s.vmx.pHostMSR, 0, PAGE_SIZE);
276#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
277
278 /* Current guest paging mode. */
279 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
280
281#ifdef LOG_ENABLED
282 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
283#endif
284 }
285
286 return VINF_SUCCESS;
287}
288
289/**
290 * Does Ring-0 per VM VT-x termination.
291 *
292 * @returns VBox status code.
293 * @param pVM The VM to operate on.
294 */
295VMMR0DECL(int) VMXR0TermVM(PVM pVM)
296{
297 for (VMCPUID i = 0; i < pVM->cCpus; i++)
298 {
299 PVMCPU pVCpu = &pVM->aCpus[i];
300
301 if (pVCpu->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
302 {
303 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVMCS, false);
304 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
305 pVCpu->hwaccm.s.vmx.pVMCS = 0;
306 pVCpu->hwaccm.s.vmx.pVMCSPhys = 0;
307 }
308 if (pVCpu->hwaccm.s.vmx.pMemObjVAPIC != NIL_RTR0MEMOBJ)
309 {
310 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, false);
311 pVCpu->hwaccm.s.vmx.pMemObjVAPIC = NIL_RTR0MEMOBJ;
312 pVCpu->hwaccm.s.vmx.pVAPIC = 0;
313 pVCpu->hwaccm.s.vmx.pVAPICPhys = 0;
314 }
315 if (pVCpu->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
316 {
317 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjMSRBitmap, false);
318 pVCpu->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
319 pVCpu->hwaccm.s.vmx.pMSRBitmap = 0;
320 pVCpu->hwaccm.s.vmx.pMSRBitmapPhys = 0;
321 }
322#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
323 if (pVCpu->hwaccm.s.vmx.pMemObjHostMSR != NIL_RTR0MEMOBJ)
324 {
325 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjHostMSR, false);
326 pVCpu->hwaccm.s.vmx.pMemObjHostMSR = NIL_RTR0MEMOBJ;
327 pVCpu->hwaccm.s.vmx.pHostMSR = 0;
328 pVCpu->hwaccm.s.vmx.pHostMSRPhys = 0;
329 }
330 if (pVCpu->hwaccm.s.vmx.pMemObjGuestMSR != NIL_RTR0MEMOBJ)
331 {
332 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjGuestMSR, false);
333 pVCpu->hwaccm.s.vmx.pMemObjGuestMSR = NIL_RTR0MEMOBJ;
334 pVCpu->hwaccm.s.vmx.pGuestMSR = 0;
335 pVCpu->hwaccm.s.vmx.pGuestMSRPhys = 0;
336 }
337#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
338 }
339 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
340 {
341 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
342 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
343 pVM->hwaccm.s.vmx.pAPIC = 0;
344 pVM->hwaccm.s.vmx.pAPICPhys = 0;
345 }
346#ifdef VBOX_WITH_CRASHDUMP_MAGIC
347 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
348 {
349 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
350 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
351 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
352 pVM->hwaccm.s.vmx.pScratch = 0;
353 pVM->hwaccm.s.vmx.pScratchPhys = 0;
354 }
355#endif
356 return VINF_SUCCESS;
357}
358
359/**
360 * Sets up VT-x for the specified VM
361 *
362 * @returns VBox status code.
363 * @param pVM The VM to operate on.
364 */
365VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
366{
367 int rc = VINF_SUCCESS;
368 uint32_t val;
369
370 AssertReturn(pVM, VERR_INVALID_PARAMETER);
371
372 for (VMCPUID i = 0; i < pVM->cCpus; i++)
373 {
374 PVMCPU pVCpu = &pVM->aCpus[i];
375
376 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
377
378 /* Set revision dword at the beginning of the VMCS structure. */
379 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
380
381 /* Clear VM Control Structure. */
382 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
383 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
384 if (RT_FAILURE(rc))
385 goto vmx_end;
386
387 /* Activate the VM Control Structure. */
388 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
389 if (RT_FAILURE(rc))
390 goto vmx_end;
391
392 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
393 * Set required bits to one and zero according to the MSR capabilities.
394 */
395 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
396 /* External and non-maskable interrupts cause VM-exits. */
397 val |= VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
398 /* enable the preemption timer. */
399 if (pVM->hwaccm.s.vmx.fUsePreemptTimer)
400 val |= VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER;
401 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
402
403 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
404 AssertRC(rc);
405
406 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
407 * Set required bits to one and zero according to the MSR capabilities.
408 */
409 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
410 /* Program which event cause VM-exits and which features we want to use. */
411 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
412 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
413 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
414 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
415 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
416 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT
417 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
418
419 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
420 if (!pVM->hwaccm.s.fNestedPaging)
421 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
422 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
423 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
424
425 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
426 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
427 {
428 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
429 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
430 Assert(pVM->hwaccm.s.vmx.pAPIC);
431 }
432 else
433 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
434 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
435
436 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
437 {
438 Assert(pVCpu->hwaccm.s.vmx.pMSRBitmapPhys);
439 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
440 }
441
442 /* We will use the secondary control if it's present. */
443 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
444
445 /* Mask away the bits that the CPU doesn't support */
446 /** @todo make sure they don't conflict with the above requirements. */
447 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
448 pVCpu->hwaccm.s.vmx.proc_ctls = val;
449
450 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
451 AssertRC(rc);
452
453 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
454 {
455 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
456 * Set required bits to one and zero according to the MSR capabilities.
457 */
458 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
459 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
460
461#ifdef HWACCM_VTX_WITH_EPT
462 if (pVM->hwaccm.s.fNestedPaging)
463 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
464#endif /* HWACCM_VTX_WITH_EPT */
465#ifdef HWACCM_VTX_WITH_VPID
466 else
467 if (pVM->hwaccm.s.vmx.fVPID)
468 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
469#endif /* HWACCM_VTX_WITH_VPID */
470
471 if (pVM->hwaccm.s.fHasIoApic)
472 val |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC;
473
474 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
475 val |= VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE;
476
477 /* Mask away the bits that the CPU doesn't support */
478 /** @todo make sure they don't conflict with the above requirements. */
479 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
480 pVCpu->hwaccm.s.vmx.proc_ctls2 = val;
481 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
482 AssertRC(rc);
483 }
484
485 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
486 * Set required bits to one and zero according to the MSR capabilities.
487 */
488 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
489 AssertRC(rc);
490
491 /* Forward all exception except #NM & #PF to the guest.
492 * We always need to check pagefaults since our shadow page table can be out of sync.
493 * And we always lazily sync the FPU & XMM state.
494 */
495
496 /** @todo Possible optimization:
497 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
498 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
499 * registers ourselves of course.
500 *
501 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
502 */
503
504 /* Don't filter page faults; all of them should cause a switch. */
505 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
506 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
507 AssertRC(rc);
508
509 /* Init TSC offset to zero. */
510 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
511 AssertRC(rc);
512
513 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
514 AssertRC(rc);
515
516 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
517 AssertRC(rc);
518
519 /* Set the MSR bitmap address. */
520 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
521 {
522 Assert(pVCpu->hwaccm.s.vmx.pMSRBitmapPhys);
523
524 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVCpu->hwaccm.s.vmx.pMSRBitmapPhys);
525 AssertRC(rc);
526
527 /* Allow the guest to directly modify these MSRs; they are restored and saved automatically. */
528 vmxR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
529 vmxR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
530 vmxR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
531 vmxR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
532 vmxR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
533 vmxR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
534 vmxR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
535 vmxR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
536 vmxR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
537 }
538
539#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
540 /* Set the guest & host MSR load/store physical addresses. */
541 Assert(pVCpu->hwaccm.s.vmx.pGuestMSRPhys);
542 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, pVCpu->hwaccm.s.vmx.pGuestMSRPhys);
543 AssertRC(rc);
544 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, pVCpu->hwaccm.s.vmx.pGuestMSRPhys);
545 AssertRC(rc);
546
547 Assert(pVCpu->hwaccm.s.vmx.pHostMSRPhys);
548 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, pVCpu->hwaccm.s.vmx.pHostMSRPhys);
549 AssertRC(rc);
550#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
551
552 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT, 0);
553 AssertRC(rc);
554
555 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
556 AssertRC(rc);
557
558 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
559 {
560 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
561 /* Optional */
562 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
563 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hwaccm.s.vmx.pVAPICPhys);
564
565 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
566 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
567
568 AssertRC(rc);
569 }
570
571 /* Set link pointer to -1. Not currently used. */
572 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
573 AssertRC(rc);
574
575 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
576 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
577 AssertRC(rc);
578
579 /* Configure the VMCS read cache. */
580 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
581
582 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
583 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
584 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
585 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
586 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
587 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
588 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
589 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
590 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
591 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
592 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
593 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
594 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
595 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
596 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
597 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
598
599 VMX_SETUP_SELREG(ES, pCache);
600 VMX_SETUP_SELREG(SS, pCache);
601 VMX_SETUP_SELREG(CS, pCache);
602 VMX_SETUP_SELREG(DS, pCache);
603 VMX_SETUP_SELREG(FS, pCache);
604 VMX_SETUP_SELREG(GS, pCache);
605 VMX_SETUP_SELREG(LDTR, pCache);
606 VMX_SETUP_SELREG(TR, pCache);
607
608 /* Status code VMCS reads. */
609 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
610 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
611 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
612 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
613 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
614 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
615 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
616 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
617 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
618
619 if (pVM->hwaccm.s.fNestedPaging)
620 {
621 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
622 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
623 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
624 }
625 else
626 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
627 } /* for each VMCPU */
628
629 /* Choose the right TLB setup function. */
630 if (pVM->hwaccm.s.fNestedPaging)
631 {
632 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
633
634 /* Default values for flushing. */
635 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
636 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
637
638 /* If the capabilities specify we can do more, then make use of it. */
639 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
640 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
641 else
642 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
643 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
644
645 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
646 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
647 }
648#ifdef HWACCM_VTX_WITH_VPID
649 else
650 if (pVM->hwaccm.s.vmx.fVPID)
651 {
652 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
653
654 /* Default values for flushing. */
655 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
656 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
657
658 /* If the capabilities specify we can do more, then make use of it. */
659 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
660 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
661 else
662 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
663 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
664
665 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
666 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
667 }
668#endif /* HWACCM_VTX_WITH_VPID */
669 else
670 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
671
672vmx_end:
673 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
674 return rc;
675}
676
677/**
678 * Sets the permission bits for the specified MSR
679 *
680 * @param pVCpu The VMCPU to operate on.
681 * @param ulMSR MSR value
682 * @param fRead Reading allowed/disallowed
683 * @param fWrite Writing allowed/disallowed
684 */
685static void vmxR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
686{
687 unsigned ulBit;
688 uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.vmx.pMSRBitmap;
689
690 /* Layout:
691 * 0x000 - 0x3ff - Low MSR read bits
692 * 0x400 - 0x7ff - High MSR read bits
693 * 0x800 - 0xbff - Low MSR write bits
694 * 0xc00 - 0xfff - High MSR write bits
695 */
696 if (ulMSR <= 0x00001FFF)
697 {
698 /* Pentium-compatible MSRs */
699 ulBit = ulMSR;
700 }
701 else
702 if ( ulMSR >= 0xC0000000
703 && ulMSR <= 0xC0001FFF)
704 {
705 /* AMD Sixth Generation x86 Processor MSRs */
706 ulBit = (ulMSR - 0xC0000000);
707 pMSRBitmap += 0x400;
708 }
709 else
710 {
711 AssertFailed();
712 return;
713 }
714
715 Assert(ulBit <= 0x1fff);
716 if (fRead)
717 ASMBitClear(pMSRBitmap, ulBit);
718 else
719 ASMBitSet(pMSRBitmap, ulBit);
720
721 if (fWrite)
722 ASMBitClear(pMSRBitmap + 0x800, ulBit);
723 else
724 ASMBitSet(pMSRBitmap + 0x800, ulBit);
725}
726
727
728/**
729 * Injects an event (trap or external interrupt)
730 *
731 * @returns VBox status code. Note that it may return VINF_EM_RESET to
732 * indicate a triple fault when injecting X86_XCPT_DF.
733 *
734 * @param pVM The VM to operate on.
735 * @param pVCpu The VMCPU to operate on.
736 * @param pCtx CPU Context
737 * @param intInfo VMX interrupt info
738 * @param cbInstr Opcode length of faulting instruction
739 * @param errCode Error code (optional)
740 */
741static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
742{
743 int rc;
744 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
745
746#ifdef VBOX_WITH_STATISTICS
747 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[iGate & MASK_INJECT_IRQ_STAT]);
748#endif
749
750#ifdef VBOX_STRICT
751 if (iGate == 0xE)
752 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
753 else
754 if (iGate < 0x20)
755 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
756 else
757 {
758 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
759 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
760 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || pCtx->eflags.u32 & X86_EFL_IF);
761 }
762#endif
763
764 if ( CPUMIsGuestInRealModeEx(pCtx)
765 && pVM->hwaccm.s.vmx.pRealModeTSS)
766 {
767 RTGCPHYS GCPhysHandler;
768 uint16_t offset, ip;
769 RTSEL sel;
770
771 /* Injecting events doesn't work right with real mode emulation.
772 * (#GP if we try to inject external hardware interrupts)
773 * Inject the interrupt or trap directly instead.
774 *
775 * ASSUMES no access handlers for the bits we read or write below (should be safe).
776 */
777 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
778
779 /* Check if the interrupt handler is present. */
780 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
781 {
782 Log(("IDT cbIdt violation\n"));
783 if (iGate != X86_XCPT_DF)
784 {
785 uint32_t intInfo2;
786
787 intInfo2 = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
788 intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
789 intInfo2 |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
790 intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
791
792 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, 0, 0 /* no error code according to the Intel docs */);
793 }
794 Log(("Triple fault -> reset the VM!\n"));
795 return VINF_EM_RESET;
796 }
797 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
798 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
799 || iGate == 4)
800 {
801 ip = pCtx->ip + cbInstr;
802 }
803 else
804 ip = pCtx->ip;
805
806 /* Read the selector:offset pair of the interrupt handler. */
807 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
808 rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
809 rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
810
811 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
812
813 /* Construct the stack frame. */
814 /** @todo should check stack limit. */
815 pCtx->sp -= 2;
816 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
817 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
818 pCtx->sp -= 2;
819 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
820 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
821 pCtx->sp -= 2;
822 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
823 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
824
825 /* Update the CPU state for executing the handler. */
826 pCtx->rip = offset;
827 pCtx->cs = sel;
828 pCtx->csHid.u64Base = sel << 4;
829 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
830
831 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
832 return VINF_SUCCESS;
833 }
834
835 /* Set event injection state. */
836 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
837
838 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
839 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
840
841 AssertRC(rc);
842 return rc;
843}
844
845
846/**
847 * Checks for pending guest interrupts and injects them
848 *
849 * @returns VBox status code.
850 * @param pVM The VM to operate on.
851 * @param pVCpu The VMCPU to operate on.
852 * @param pCtx CPU Context
853 */
854static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
855{
856 int rc;
857
858 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
859 if (pVCpu->hwaccm.s.Event.fPending)
860 {
861 Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
862 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
863 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
864 AssertRC(rc);
865
866 pVCpu->hwaccm.s.Event.fPending = false;
867 return VINF_SUCCESS;
868 }
869
870 /* If an active trap is already pending, then we must forward it first! */
871 if (!TRPMHasTrap(pVCpu))
872 {
873 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
874 {
875 RTGCUINTPTR intInfo;
876
877 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
878
879 intInfo = X86_XCPT_NMI;
880 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
881 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
882
883 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
884 AssertRC(rc);
885
886 return VINF_SUCCESS;
887 }
888
889 /* @todo SMI interrupts. */
890
891 /* When external interrupts are pending, we should exit the VM when IF is set. */
892 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
893 {
894 if (!(pCtx->eflags.u32 & X86_EFL_IF))
895 {
896 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
897 {
898 LogFlow(("Enable irq window exit!\n"));
899 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
900 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
901 AssertRC(rc);
902 }
903 /* else nothing to do but wait */
904 }
905 else
906 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
907 {
908 uint8_t u8Interrupt;
909
910 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
911 Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
912 if (RT_SUCCESS(rc))
913 {
914 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
915 AssertRC(rc);
916 }
917 else
918 {
919 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
920 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
921 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
922 /* Just continue */
923 }
924 }
925 else
926 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
927 }
928 }
929
930#ifdef VBOX_STRICT
931 if (TRPMHasTrap(pVCpu))
932 {
933 uint8_t u8Vector;
934 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
935 AssertRC(rc);
936 }
937#endif
938
939 if ( (pCtx->eflags.u32 & X86_EFL_IF)
940 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
941 && TRPMHasTrap(pVCpu)
942 )
943 {
944 uint8_t u8Vector;
945 TRPMEVENT enmType;
946 RTGCUINTPTR intInfo;
947 RTGCUINT errCode;
948
949 /* If a new event is pending, then dispatch it now. */
950 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
951 AssertRC(rc);
952 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
953 Assert(enmType != TRPM_SOFTWARE_INT);
954
955 /* Clear the pending trap. */
956 rc = TRPMResetTrap(pVCpu);
957 AssertRC(rc);
958
959 intInfo = u8Vector;
960 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
961
962 if (enmType == TRPM_TRAP)
963 {
964 switch (u8Vector) {
965 case 8:
966 case 10:
967 case 11:
968 case 12:
969 case 13:
970 case 14:
971 case 17:
972 /* Valid error codes. */
973 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
974 break;
975 default:
976 break;
977 }
978 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
979 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
980 else
981 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
982 }
983 else
984 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
985
986 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
987 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
988 AssertRC(rc);
989 } /* if (interrupts can be dispatched) */
990
991 return VINF_SUCCESS;
992}
993
994/**
995 * Save the host state
996 *
997 * @returns VBox status code.
998 * @param pVM The VM to operate on.
999 * @param pVCpu The VMCPU to operate on.
1000 */
1001VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1002{
1003 int rc = VINF_SUCCESS;
1004
1005 /*
1006 * Host CPU Context
1007 */
1008 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
1009 {
1010 RTIDTR idtr;
1011 RTGDTR gdtr;
1012 RTSEL SelTR;
1013 PCX86DESCHC pDesc;
1014 uintptr_t trBase;
1015 RTSEL cs;
1016 RTSEL ss;
1017 uint64_t cr3;
1018
1019 /* Control registers */
1020 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
1021#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1022 if (VMX_IS_64BIT_HOST_MODE())
1023 {
1024 cr3 = hwaccmR0Get64bitCR3();
1025 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
1026 }
1027 else
1028#endif
1029 {
1030 cr3 = ASMGetCR3();
1031 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
1032 }
1033 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
1034 AssertRC(rc);
1035 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
1036 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
1037 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
1038
1039 /* Selector registers. */
1040#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1041 if (VMX_IS_64BIT_HOST_MODE())
1042 {
1043 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
1044 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
1045 }
1046 else
1047 {
1048 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
1049 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
1050 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
1051 }
1052#else
1053 cs = ASMGetCS();
1054 ss = ASMGetSS();
1055#endif
1056 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
1057 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
1058 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
1059 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
1060 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
1061 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
1062#if HC_ARCH_BITS == 32
1063 if (!VMX_IS_64BIT_HOST_MODE())
1064 {
1065 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
1066 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
1067 }
1068#endif
1069 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
1070 SelTR = ASMGetTR();
1071 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
1072 AssertRC(rc);
1073 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
1074 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
1075 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
1076 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
1077 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
1078 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
1079 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
1080
1081 /* GDTR & IDTR */
1082#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1083 if (VMX_IS_64BIT_HOST_MODE())
1084 {
1085 X86XDTR64 gdtr64, idtr64;
1086 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
1087 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
1088 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
1089 AssertRC(rc);
1090 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
1091 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
1092 gdtr.cbGdt = gdtr64.cb;
1093 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
1094 }
1095 else
1096#endif
1097 {
1098 ASMGetGDTR(&gdtr);
1099 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
1100 ASMGetIDTR(&idtr);
1101 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
1102 AssertRC(rc);
1103 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
1104 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
1105 }
1106
1107 /* Save the base address of the TR selector. */
1108 if (SelTR > gdtr.cbGdt)
1109 {
1110 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
1111 return VERR_VMX_INVALID_HOST_STATE;
1112 }
1113
1114 pDesc = (PCX86DESCHC)(gdtr.pGdt + (SelTR & X86_SEL_MASK));
1115#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1116 if (VMX_IS_64BIT_HOST_MODE())
1117 {
1118 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
1119 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
1120 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
1121 AssertRC(rc);
1122 }
1123 else
1124#endif
1125 {
1126#if HC_ARCH_BITS == 64
1127 trBase = X86DESC64_BASE(*pDesc);
1128#else
1129 trBase = X86DESC_BASE(*pDesc);
1130#endif
1131 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
1132 AssertRC(rc);
1133 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
1134 }
1135
1136 /* FS and GS base. */
1137#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1138 if (VMX_IS_64BIT_HOST_MODE())
1139 {
1140 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
1141 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
1142 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
1143 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
1144 }
1145#endif
1146 AssertRC(rc);
1147
1148 /* Sysenter MSRs. */
1149 /** @todo expensive!! */
1150 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
1151 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
1152#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1153 if (VMX_IS_64BIT_HOST_MODE())
1154 {
1155 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1156 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1157 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1158 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1159 }
1160 else
1161 {
1162 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1163 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1164 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1165 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1166 }
1167#elif HC_ARCH_BITS == 32
1168 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1169 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1170 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1171 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1172#else
1173 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1174 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1175 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1176 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1177#endif
1178 AssertRC(rc);
1179
1180#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
1181 /* Store all host MSRs in the VM-Exit load area, so they will be reloaded after the world switch back to the host. */
1182 PVMXMSR pMsr = (PVMXMSR)pVCpu->hwaccm.s.vmx.pHostMSR;
1183 unsigned idxMsr = 0;
1184
1185 /* EFER MSR present? */
1186 if (ASMCpuId_EDX(0x80000001) & (X86_CPUID_AMD_FEATURE_EDX_NX|X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1187 {
1188 if (ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_SEP)
1189 {
1190 pMsr->u32IndexMSR = MSR_K6_STAR;
1191 pMsr->u32Reserved = 0;
1192 pMsr->u64Value = ASMRdMsr(MSR_K6_STAR); /* legacy syscall eip, cs & ss */
1193 pMsr++; idxMsr++;
1194 }
1195
1196 pMsr->u32IndexMSR = MSR_K6_EFER;
1197 pMsr->u32Reserved = 0;
1198# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1199 if (CPUMIsGuestInLongMode(pVCpu))
1200 {
1201 /* Must match the efer value in our 64 bits switcher. */
1202 pMsr->u64Value = ASMRdMsr(MSR_K6_EFER) | MSR_K6_EFER_LME | MSR_K6_EFER_SCE | MSR_K6_EFER_NXE;
1203 }
1204 else
1205# endif
1206 pMsr->u64Value = ASMRdMsr(MSR_K6_EFER);
1207 pMsr++; idxMsr++;
1208 }
1209
1210# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1211 if (VMX_IS_64BIT_HOST_MODE())
1212 {
1213 pMsr->u32IndexMSR = MSR_K8_LSTAR;
1214 pMsr->u32Reserved = 0;
1215 pMsr->u64Value = ASMRdMsr(MSR_K8_LSTAR); /* 64 bits mode syscall rip */
1216 pMsr++; idxMsr++;
1217 pMsr->u32IndexMSR = MSR_K8_SF_MASK;
1218 pMsr->u32Reserved = 0;
1219 pMsr->u64Value = ASMRdMsr(MSR_K8_SF_MASK); /* syscall flag mask */
1220 pMsr++; idxMsr++;
1221 pMsr->u32IndexMSR = MSR_K8_KERNEL_GS_BASE;
1222 pMsr->u32Reserved = 0;
1223 pMsr->u64Value = ASMRdMsr(MSR_K8_KERNEL_GS_BASE); /* swapgs exchange value */
1224 pMsr++; idxMsr++;
1225 }
1226# endif
1227 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, idxMsr);
1228 AssertRC(rc);
1229#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
1230
1231 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1232 }
1233 return rc;
1234}
1235
1236/**
1237 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1238 *
1239 * @returns VINF_SUCCESS or fatal error.
1240 * @param pVM The VM to operate on.
1241 * @param pVCpu The VMCPU to operate on.
1242 * @param pCtx Guest context
1243 */
1244static int vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1245{
1246 if (CPUMIsGuestInPAEModeEx(pCtx))
1247 {
1248 for (unsigned i=0;i<4;i++)
1249 {
1250 X86PDPE Pdpe;
1251 int rc = PGMGstQueryPaePDPtr(pVCpu, i, &Pdpe);
1252 AssertRCReturn(rc, rc);
1253
1254 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1255 AssertRC(rc);
1256 }
1257 }
1258 return VINF_SUCCESS;
1259}
1260
1261/**
1262 * Update the exception bitmap according to the current CPU state
1263 *
1264 * @param pVM The VM to operate on.
1265 * @param pVCpu The VMCPU to operate on.
1266 * @param pCtx Guest context
1267 */
1268static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1269{
1270 uint32_t u32TrapMask;
1271 Assert(pCtx);
1272
1273 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1274#ifndef DEBUG
1275 if (pVM->hwaccm.s.fNestedPaging)
1276 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1277#endif
1278
1279 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1280 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1281 && !(pCtx->cr0 & X86_CR0_NE)
1282 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1283 {
1284 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1285 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1286 }
1287
1288#ifdef VBOX_STRICT
1289 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1290#endif
1291
1292 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1293 if ( CPUMIsGuestInRealModeEx(pCtx)
1294 && pVM->hwaccm.s.vmx.pRealModeTSS)
1295 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1296
1297 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1298 AssertRC(rc);
1299}
1300
1301/**
1302 * Loads a minimal guest state
1303 *
1304 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1305 *
1306 * @param pVM The VM to operate on.
1307 * @param pVCpu The VMCPU to operate on.
1308 * @param pCtx Guest context
1309 */
1310VMMR0DECL(void) VMXR0LoadMinimalGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1311{
1312 int rc;
1313 X86EFLAGS eflags;
1314
1315 Assert(!(pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_ALL_GUEST));
1316
1317 /* EIP, ESP and EFLAGS */
1318 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1319 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1320 AssertRC(rc);
1321
1322 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1323 eflags = pCtx->eflags;
1324 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1325 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1326
1327 /* Real mode emulation using v86 mode. */
1328 if ( CPUMIsGuestInRealModeEx(pCtx)
1329 && pVM->hwaccm.s.vmx.pRealModeTSS)
1330 {
1331 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1332
1333 eflags.Bits.u1VM = 1;
1334 eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
1335 }
1336 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1337 AssertRC(rc);
1338}
1339
1340/**
1341 * Loads the guest state
1342 *
1343 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1344 *
1345 * @returns VBox status code.
1346 * @param pVM The VM to operate on.
1347 * @param pVCpu The VMCPU to operate on.
1348 * @param pCtx Guest context
1349 */
1350VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1351{
1352 int rc = VINF_SUCCESS;
1353 RTGCUINTPTR val;
1354
1355 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1356 * Set required bits to one and zero according to the MSR capabilities.
1357 */
1358 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1359 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1360 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1361 /* 64 bits guest mode? */
1362 if (CPUMIsGuestInLongModeEx(pCtx))
1363 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1364 /* else Must be zero when AMD64 is not available. */
1365
1366 /* Mask away the bits that the CPU doesn't support */
1367 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1368 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1369 AssertRC(rc);
1370
1371 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1372 * Set required bits to one and zero according to the MSR capabilities.
1373 */
1374 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1375
1376 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1377 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1378
1379#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1380 if (VMX_IS_64BIT_HOST_MODE())
1381 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1382 /* else: Must be zero when AMD64 is not available. */
1383#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1384 if (CPUMIsGuestInLongModeEx(pCtx))
1385 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1386 else
1387 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1388#endif
1389 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1390 /* Don't acknowledge external interrupts on VM-exit. */
1391 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1392 AssertRC(rc);
1393
1394 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1395 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1396 {
1397 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1398 {
1399 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1400 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1401 {
1402 /* Correct weird requirements for switching to protected mode. */
1403 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1404 && enmGuestMode >= PGMMODE_PROTECTED)
1405 {
1406 /* Flush the recompiler code cache as it's not unlikely
1407 * the guest will rewrite code it will later execute in real
1408 * mode (OpenBSD 4.0 is one such example)
1409 */
1410 REMFlushTBs(pVM);
1411
1412 /* DPL of all hidden selector registers must match the current CPL (0). */
1413 pCtx->csHid.Attr.n.u2Dpl = 0;
1414 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1415
1416 pCtx->dsHid.Attr.n.u2Dpl = 0;
1417 pCtx->esHid.Attr.n.u2Dpl = 0;
1418 pCtx->fsHid.Attr.n.u2Dpl = 0;
1419 pCtx->gsHid.Attr.n.u2Dpl = 0;
1420 pCtx->ssHid.Attr.n.u2Dpl = 0;
1421
1422 /* The limit must correspond to the 32 bits setting. */
1423 if (!pCtx->csHid.Attr.n.u1DefBig)
1424 pCtx->csHid.u32Limit &= 0xffff;
1425 if (!pCtx->dsHid.Attr.n.u1DefBig)
1426 pCtx->dsHid.u32Limit &= 0xffff;
1427 if (!pCtx->esHid.Attr.n.u1DefBig)
1428 pCtx->esHid.u32Limit &= 0xffff;
1429 if (!pCtx->fsHid.Attr.n.u1DefBig)
1430 pCtx->fsHid.u32Limit &= 0xffff;
1431 if (!pCtx->gsHid.Attr.n.u1DefBig)
1432 pCtx->gsHid.u32Limit &= 0xffff;
1433 if (!pCtx->ssHid.Attr.n.u1DefBig)
1434 pCtx->ssHid.u32Limit &= 0xffff;
1435 }
1436 else
1437 /* Switching from protected mode to real mode. */
1438 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1439 && enmGuestMode == PGMMODE_REAL)
1440 {
1441 /* The limit must also be set to 0xffff. */
1442 pCtx->csHid.u32Limit = 0xffff;
1443 pCtx->dsHid.u32Limit = 0xffff;
1444 pCtx->esHid.u32Limit = 0xffff;
1445 pCtx->fsHid.u32Limit = 0xffff;
1446 pCtx->gsHid.u32Limit = 0xffff;
1447 pCtx->ssHid.u32Limit = 0xffff;
1448
1449 Assert(pCtx->csHid.u64Base <= 0xfffff);
1450 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1451 Assert(pCtx->esHid.u64Base <= 0xfffff);
1452 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1453 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1454 }
1455 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1456 }
1457 else
1458 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1459 if ( CPUMIsGuestInRealModeEx(pCtx)
1460 && pCtx->csHid.u64Base == 0xffff0000)
1461 {
1462 pCtx->csHid.u64Base = 0xf0000;
1463 pCtx->cs = 0xf000;
1464 }
1465 }
1466
1467 VMX_WRITE_SELREG(ES, es);
1468 AssertRC(rc);
1469
1470 VMX_WRITE_SELREG(CS, cs);
1471 AssertRC(rc);
1472
1473 VMX_WRITE_SELREG(SS, ss);
1474 AssertRC(rc);
1475
1476 VMX_WRITE_SELREG(DS, ds);
1477 AssertRC(rc);
1478
1479 VMX_WRITE_SELREG(FS, fs);
1480 AssertRC(rc);
1481
1482 VMX_WRITE_SELREG(GS, gs);
1483 AssertRC(rc);
1484 }
1485
1486 /* Guest CPU context: LDTR. */
1487 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1488 {
1489 if (pCtx->ldtr == 0)
1490 {
1491 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1492 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1493 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1494 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1495 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1496 }
1497 else
1498 {
1499 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1500 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1501 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1502 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1503 }
1504 AssertRC(rc);
1505 }
1506 /* Guest CPU context: TR. */
1507 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1508 {
1509 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1510 if ( CPUMIsGuestInRealModeEx(pCtx)
1511 && pVM->hwaccm.s.vmx.pRealModeTSS)
1512 {
1513 RTGCPHYS GCPhys;
1514
1515 /* We convert it here every time as pci regions could be reconfigured. */
1516 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1517 AssertRC(rc);
1518
1519 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1520 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1521 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1522
1523 X86DESCATTR attr;
1524
1525 attr.u = 0;
1526 attr.n.u1Present = 1;
1527 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1528 val = attr.u;
1529 }
1530 else
1531 {
1532 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1533 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1534 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1535
1536 val = pCtx->trHid.Attr.u;
1537
1538 /* The TSS selector must be busy (REM bugs? see defect #XXXX). */
1539 if (!(val & X86_SEL_TYPE_SYS_TSS_BUSY_MASK))
1540 {
1541 if (val & 0xf)
1542 val |= X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
1543 else
1544 /* Default if no TR selector has been set (otherwise vmlaunch will fail!) */
1545 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1546 }
1547 AssertMsg((val & 0xf) == X86_SEL_TYPE_SYS_386_TSS_BUSY || (val & 0xf) == X86_SEL_TYPE_SYS_286_TSS_BUSY, ("%#x\n", val));
1548 }
1549 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1550 AssertRC(rc);
1551 }
1552 /* Guest CPU context: GDTR. */
1553 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1554 {
1555 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1556 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1557 AssertRC(rc);
1558 }
1559 /* Guest CPU context: IDTR. */
1560 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1561 {
1562 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1563 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1564 AssertRC(rc);
1565 }
1566
1567 /*
1568 * Sysenter MSRs
1569 */
1570 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_MSR)
1571 {
1572 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1573 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1574 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1575 AssertRC(rc);
1576 }
1577
1578 /* Control registers */
1579 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1580 {
1581 val = pCtx->cr0;
1582 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1583 Log2(("Guest CR0-shadow %08x\n", val));
1584 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1585 {
1586 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1587 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1588 }
1589 else
1590 {
1591 /** @todo check if we support the old style mess correctly. */
1592 if (!(val & X86_CR0_NE))
1593 Log(("Forcing X86_CR0_NE!!!\n"));
1594
1595 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1596 }
1597 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1598 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1599 val |= X86_CR0_PE | X86_CR0_PG;
1600
1601 if (pVM->hwaccm.s.fNestedPaging)
1602 {
1603 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1604 {
1605 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1606 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1607 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1608 }
1609 else
1610 {
1611 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1612 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1613 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1614 }
1615 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1616 AssertRC(rc);
1617 }
1618 else
1619 {
1620 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1621 val |= X86_CR0_WP;
1622 }
1623
1624 /* Always enable caching. */
1625 val &= ~(X86_CR0_CD|X86_CR0_NW);
1626
1627 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1628 Log2(("Guest CR0 %08x\n", val));
1629 /* CR0 flags owned by the host; if the guests attempts to change them, then
1630 * the VM will exit.
1631 */
1632 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1633 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1634 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1635 | X86_CR0_CD /* Bit not restored during VM-exit! */
1636 | X86_CR0_NW /* Bit not restored during VM-exit! */
1637 | X86_CR0_NE;
1638
1639 /* When the guest's FPU state is active, then we no longer care about
1640 * the FPU related bits.
1641 */
1642 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1643 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_MP;
1644
1645 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1646
1647 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1648 Log2(("Guest CR0-mask %08x\n", val));
1649 AssertRC(rc);
1650 }
1651 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1652 {
1653 /* CR4 */
1654 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1655 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1656 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1657 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1658
1659 if (!pVM->hwaccm.s.fNestedPaging)
1660 {
1661 switch(pVCpu->hwaccm.s.enmShadowMode)
1662 {
1663 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1664 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1665 case PGMMODE_32_BIT: /* 32-bit paging. */
1666 val &= ~X86_CR4_PAE;
1667 break;
1668
1669 case PGMMODE_PAE: /* PAE paging. */
1670 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1671 /** Must use PAE paging as we could use physical memory > 4 GB */
1672 val |= X86_CR4_PAE;
1673 break;
1674
1675 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1676 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1677#ifdef VBOX_ENABLE_64_BITS_GUESTS
1678 break;
1679#else
1680 AssertFailed();
1681 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1682#endif
1683 default: /* shut up gcc */
1684 AssertFailed();
1685 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1686 }
1687 }
1688 else
1689 if ( !CPUMIsGuestInPagedProtectedModeEx(pCtx)
1690 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1691 {
1692 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1693 val |= X86_CR4_PSE;
1694 /* Our identity mapping is a 32 bits page directory. */
1695 val &= ~X86_CR4_PAE;
1696 }
1697
1698 /* Turn off VME if we're in emulated real mode. */
1699 if ( CPUMIsGuestInRealModeEx(pCtx)
1700 && pVM->hwaccm.s.vmx.pRealModeTSS)
1701 val &= ~X86_CR4_VME;
1702
1703 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1704 Log2(("Guest CR4 %08x\n", val));
1705 /* CR4 flags owned by the host; if the guests attempts to change them, then
1706 * the VM will exit.
1707 */
1708 val = 0
1709 | X86_CR4_VME
1710 | X86_CR4_PAE
1711 | X86_CR4_PGE
1712 | X86_CR4_PSE
1713 | X86_CR4_VMXE;
1714 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1715
1716 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1717 Log2(("Guest CR4-mask %08x\n", val));
1718 AssertRC(rc);
1719 }
1720
1721 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1722 {
1723 if (pVM->hwaccm.s.fNestedPaging)
1724 {
1725 Assert(PGMGetHyperCR3(pVCpu));
1726 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVCpu);
1727
1728 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1729 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1730 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1731 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1732
1733 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1734 AssertRC(rc);
1735
1736 if ( !CPUMIsGuestInPagedProtectedModeEx(pCtx)
1737 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1738 {
1739 RTGCPHYS GCPhys;
1740
1741 /* We convert it here every time as pci regions could be reconfigured. */
1742 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1743 AssertMsgRC(rc, ("pNonPagingModeEPTPageTable = %RGv\n", pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable));
1744
1745 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1746 * take care of the translation to host physical addresses.
1747 */
1748 val = GCPhys;
1749 }
1750 else
1751 {
1752 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1753 val = pCtx->cr3;
1754 /* Prefetch the four PDPT entries in PAE mode. */
1755 rc = vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1756 AssertRCReturn(rc, rc);
1757 }
1758 }
1759 else
1760 {
1761 val = PGMGetHyperCR3(pVCpu);
1762 Assert(val || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1763 }
1764
1765 /* Save our shadow CR3 register. */
1766 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1767 AssertRC(rc);
1768 }
1769
1770 /* Debug registers. */
1771 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1772 {
1773 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1774 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1775
1776 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1777 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1778 pCtx->dr[7] |= 0x400; /* must be one */
1779
1780 /* Resync DR7 */
1781 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1782 AssertRC(rc);
1783
1784#ifdef DEBUG
1785 /* Sync the hypervisor debug state now if any breakpoint is armed. */
1786 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
1787 && !CPUMIsHyperDebugStateActive(pVCpu)
1788 && !DBGFIsStepping(pVCpu))
1789 {
1790 /* Save the host and load the hypervisor debug state. */
1791 rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1792 AssertRC(rc);
1793
1794 /* DRx intercepts remain enabled. */
1795
1796 /* Override dr7 with the hypervisor value. */
1797 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, CPUMGetHyperDR7(pVCpu));
1798 AssertRC(rc);
1799 }
1800 else
1801#endif
1802 /* Sync the debug state now if any breakpoint is armed. */
1803 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1804 && !CPUMIsGuestDebugStateActive(pVCpu)
1805 && !DBGFIsStepping(pVCpu))
1806 {
1807 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1808
1809 /* Disable drx move intercepts. */
1810 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1811 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1812 AssertRC(rc);
1813
1814 /* Save the host and load the guest debug state. */
1815 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1816 AssertRC(rc);
1817 }
1818
1819 /* IA32_DEBUGCTL MSR. */
1820 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1821 AssertRC(rc);
1822
1823 /** @todo do we really ever need this? */
1824 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1825 AssertRC(rc);
1826 }
1827
1828 /* 64 bits guest mode? */
1829 if (CPUMIsGuestInLongModeEx(pCtx))
1830 {
1831#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1832 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1833#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1834 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1835#else
1836# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1837 if (!pVM->hwaccm.s.fAllow64BitGuests)
1838 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1839# endif
1840 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1841#endif
1842 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_MSR)
1843 {
1844 /* Update these as wrmsr might have changed them. */
1845 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1846 AssertRC(rc);
1847 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1848 AssertRC(rc);
1849 }
1850 }
1851 else
1852 {
1853 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1854 }
1855
1856 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1857
1858#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
1859 /* Store all guest MSRs in the VM-Entry load area, so they will be loaded during the world switch. */
1860 PVMXMSR pMsr = (PVMXMSR)pVCpu->hwaccm.s.vmx.pGuestMSR;
1861 unsigned idxMsr = 0;
1862
1863 uint32_t ulEdx;
1864 uint32_t ulTemp;
1865 CPUMGetGuestCpuId(pVCpu, 0x80000001, &ulTemp, &ulTemp, &ulTemp, &ulEdx);
1866 /* EFER MSR present? */
1867 if (ulEdx & (X86_CPUID_AMD_FEATURE_EDX_NX|X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1868 {
1869 pMsr->u32IndexMSR = MSR_K6_EFER;
1870 pMsr->u32Reserved = 0;
1871 pMsr->u64Value = pCtx->msrEFER;
1872 /* VT-x will complain if only MSR_K6_EFER_LME is set. */
1873 if (!CPUMIsGuestInLongModeEx(pCtx))
1874 pMsr->u64Value &= ~(MSR_K6_EFER_LMA|MSR_K6_EFER_LME);
1875 pMsr++; idxMsr++;
1876
1877 if (ulEdx & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
1878 {
1879 pMsr->u32IndexMSR = MSR_K8_LSTAR;
1880 pMsr->u32Reserved = 0;
1881 pMsr->u64Value = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
1882 pMsr++; idxMsr++;
1883 pMsr->u32IndexMSR = MSR_K6_STAR;
1884 pMsr->u32Reserved = 0;
1885 pMsr->u64Value = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
1886 pMsr++; idxMsr++;
1887 pMsr->u32IndexMSR = MSR_K8_SF_MASK;
1888 pMsr->u32Reserved = 0;
1889 pMsr->u64Value = pCtx->msrSFMASK; /* syscall flag mask */
1890 pMsr++; idxMsr++;
1891 pMsr->u32IndexMSR = MSR_K8_KERNEL_GS_BASE;
1892 pMsr->u32Reserved = 0;
1893 pMsr->u64Value = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
1894 pMsr++; idxMsr++;
1895 }
1896 }
1897 pVCpu->hwaccm.s.vmx.cCachedMSRs = idxMsr;
1898
1899 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_MSR_LOAD_COUNT, idxMsr);
1900 AssertRC(rc);
1901
1902 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, idxMsr);
1903 AssertRC(rc);
1904#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
1905
1906 bool fOffsettedTsc;
1907 if (pVM->hwaccm.s.vmx.fUsePreemptTimer)
1908 {
1909 uint64_t cTicksToDeadline = TMCpuTickGetDeadlineAndTscOffset(pVCpu, &fOffsettedTsc, &pVCpu->hwaccm.s.vmx.u64TSCOffset);
1910
1911 /* Make sure the returned values have sane upper and lower boundaries. */
1912 uint64_t u64CpuHz = SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage);
1913
1914 cTicksToDeadline = RT_MIN(cTicksToDeadline, u64CpuHz / 64); /* 1/64 of a second */
1915 cTicksToDeadline = RT_MAX(cTicksToDeadline, u64CpuHz / 2048); /* 1/2048th of a second */
1916
1917 cTicksToDeadline >>= pVM->hwaccm.s.vmx.cPreemptTimerShift;
1918 uint32_t cPreemptionTickCount = (uint32_t)RT_MIN(cTicksToDeadline, UINT32_MAX - 16);
1919 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE, cPreemptionTickCount);
1920 AssertRC(rc);
1921 }
1922 else
1923 fOffsettedTsc = TMCpuTickCanUseRealTSC(pVCpu, &pVCpu->hwaccm.s.vmx.u64TSCOffset);
1924 if (fOffsettedTsc)
1925 {
1926 uint64_t u64CurTSC = ASMReadTSC();
1927 if (u64CurTSC + pVCpu->hwaccm.s.vmx.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
1928 {
1929 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1930 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, pVCpu->hwaccm.s.vmx.u64TSCOffset);
1931 AssertRC(rc);
1932
1933 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1934 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1935 AssertRC(rc);
1936 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1937 }
1938 else
1939 {
1940 /* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
1941 LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVCpu->hwaccm.s.vmx.u64TSCOffset, u64CurTSC + pVCpu->hwaccm.s.vmx.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVCpu->hwaccm.s.vmx.u64TSCOffset, TMCpuTickGet(pVCpu)));
1942 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1943 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1944 AssertRC(rc);
1945 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow);
1946 }
1947 }
1948 else
1949 {
1950 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1951 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1952 AssertRC(rc);
1953 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1954 }
1955
1956 /* Done with the major changes */
1957 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1958
1959 /* Minimal guest state update (esp, eip, eflags mostly) */
1960 VMXR0LoadMinimalGuestState(pVM, pVCpu, pCtx);
1961 return rc;
1962}
1963
1964/**
1965 * Syncs back the guest state
1966 *
1967 * @returns VBox status code.
1968 * @param pVM The VM to operate on.
1969 * @param pVCpu The VMCPU to operate on.
1970 * @param pCtx Guest context
1971 */
1972DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1973{
1974 RTGCUINTREG val, valShadow;
1975 RTGCUINTPTR uInterruptState;
1976 int rc;
1977
1978 /* Let's first sync back eip, esp, and eflags. */
1979 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1980 AssertRC(rc);
1981 pCtx->rip = val;
1982 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1983 AssertRC(rc);
1984 pCtx->rsp = val;
1985 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1986 AssertRC(rc);
1987 pCtx->eflags.u32 = val;
1988
1989 /* Take care of instruction fusing (sti, mov ss) */
1990 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1991 uInterruptState = val;
1992 if (uInterruptState != 0)
1993 {
1994 Assert(uInterruptState <= 2); /* only sti & mov ss */
1995 Log(("uInterruptState %x eip=%RGv\n", (uint32_t)uInterruptState, pCtx->rip));
1996 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1997 }
1998 else
1999 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2000
2001 /* Control registers. */
2002 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
2003 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
2004 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
2005 CPUMSetGuestCR0(pVCpu, val);
2006
2007 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
2008 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
2009 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
2010 CPUMSetGuestCR4(pVCpu, val);
2011
2012 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
2013 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
2014 if ( pVM->hwaccm.s.fNestedPaging
2015 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
2016 {
2017 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
2018
2019 /* Can be updated behind our back in the nested paging case. */
2020 CPUMSetGuestCR2(pVCpu, pCache->cr2);
2021
2022 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
2023
2024 if (val != pCtx->cr3)
2025 {
2026 CPUMSetGuestCR3(pVCpu, val);
2027 PGMUpdateCR3(pVCpu, val);
2028 }
2029 /* Prefetch the four PDPT entries in PAE mode. */
2030 rc = vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
2031 AssertRCReturn(rc, rc);
2032 }
2033
2034 /* Sync back DR7 here. */
2035 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
2036 pCtx->dr[7] = val;
2037
2038 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
2039 VMX_READ_SELREG(ES, es);
2040 VMX_READ_SELREG(SS, ss);
2041 VMX_READ_SELREG(CS, cs);
2042 VMX_READ_SELREG(DS, ds);
2043 VMX_READ_SELREG(FS, fs);
2044 VMX_READ_SELREG(GS, gs);
2045
2046 /*
2047 * System MSRs
2048 */
2049 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
2050 pCtx->SysEnter.cs = val;
2051 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
2052 pCtx->SysEnter.eip = val;
2053 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
2054 pCtx->SysEnter.esp = val;
2055
2056 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
2057 VMX_READ_SELREG(LDTR, ldtr);
2058
2059 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
2060 pCtx->gdtr.cbGdt = val;
2061 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
2062 pCtx->gdtr.pGdt = val;
2063
2064 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
2065 pCtx->idtr.cbIdt = val;
2066 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
2067 pCtx->idtr.pIdt = val;
2068
2069 /* Real mode emulation using v86 mode. */
2070 if ( CPUMIsGuestInRealModeEx(pCtx)
2071 && pVM->hwaccm.s.vmx.pRealModeTSS)
2072 {
2073 /* Hide our emulation flags */
2074 pCtx->eflags.Bits.u1VM = 0;
2075
2076 /* Restore original IOPL setting as we always use 0. */
2077 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
2078
2079 /* Force a TR resync every time in case we switch modes. */
2080 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
2081 }
2082 else
2083 {
2084 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
2085 VMX_READ_SELREG(TR, tr);
2086 }
2087
2088#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2089 /* Save the possibly changed MSRs that we automatically restore and save during a world switch. */
2090 for (unsigned i = 0; i < pVCpu->hwaccm.s.vmx.cCachedMSRs; i++)
2091 {
2092 PVMXMSR pMsr = (PVMXMSR)pVCpu->hwaccm.s.vmx.pGuestMSR;
2093 pMsr += i;
2094
2095 switch (pMsr->u32IndexMSR)
2096 {
2097 case MSR_K8_LSTAR:
2098 pCtx->msrLSTAR = pMsr->u64Value;
2099 break;
2100 case MSR_K6_STAR:
2101 pCtx->msrSTAR = pMsr->u64Value;
2102 break;
2103 case MSR_K8_SF_MASK:
2104 pCtx->msrSFMASK = pMsr->u64Value;
2105 break;
2106 case MSR_K8_KERNEL_GS_BASE:
2107 pCtx->msrKERNELGSBASE = pMsr->u64Value;
2108 break;
2109 case MSR_K6_EFER:
2110 /* EFER can't be changed without causing a VM-exit. */
2111// Assert(pCtx->msrEFER == pMsr->u64Value);
2112 break;
2113 default:
2114 AssertFailed();
2115 return VERR_INTERNAL_ERROR;
2116 }
2117 }
2118#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
2119 return VINF_SUCCESS;
2120}
2121
2122/**
2123 * Dummy placeholder
2124 *
2125 * @param pVM The VM to operate on.
2126 * @param pVCpu The VMCPU to operate on.
2127 */
2128static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
2129{
2130 NOREF(pVM);
2131 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
2132 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
2133 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
2134 return;
2135}
2136
2137/**
2138 * Setup the tagged TLB for EPT
2139 *
2140 * @returns VBox status code.
2141 * @param pVM The VM to operate on.
2142 * @param pVCpu The VMCPU to operate on.
2143 */
2144static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
2145{
2146 PHWACCM_CPUINFO pCpu;
2147
2148 Assert(pVM->hwaccm.s.fNestedPaging);
2149 Assert(!pVM->hwaccm.s.vmx.fVPID);
2150
2151 /* Deal with tagged TLBs if VPID or EPT is supported. */
2152 pCpu = HWACCMR0GetCurrentCpu();
2153 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
2154 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
2155 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2156 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
2157 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2158 {
2159 /* Force a TLB flush on VM entry. */
2160 pVCpu->hwaccm.s.fForceTLBFlush = true;
2161 }
2162 else
2163 Assert(!pCpu->fFlushTLB);
2164
2165 /* Check for tlb shootdown flushes. */
2166 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2167 pVCpu->hwaccm.s.fForceTLBFlush = true;
2168
2169 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
2170 pCpu->fFlushTLB = false;
2171
2172 if (pVCpu->hwaccm.s.fForceTLBFlush)
2173 {
2174 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
2175 }
2176 else
2177 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
2178 {
2179 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
2180 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
2181
2182 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
2183 {
2184 /* aTlbShootdownPages contains physical addresses in this case. */
2185 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
2186 }
2187 }
2188 pVCpu->hwaccm.s.TlbShootdown.cPages= 0;
2189 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
2190
2191#ifdef VBOX_WITH_STATISTICS
2192 if (pVCpu->hwaccm.s.fForceTLBFlush)
2193 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
2194 else
2195 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
2196#endif
2197}
2198
2199#ifdef HWACCM_VTX_WITH_VPID
2200/**
2201 * Setup the tagged TLB for VPID
2202 *
2203 * @returns VBox status code.
2204 * @param pVM The VM to operate on.
2205 * @param pVCpu The VMCPU to operate on.
2206 */
2207static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
2208{
2209 PHWACCM_CPUINFO pCpu;
2210
2211 Assert(pVM->hwaccm.s.vmx.fVPID);
2212 Assert(!pVM->hwaccm.s.fNestedPaging);
2213
2214 /* Deal with tagged TLBs if VPID or EPT is supported. */
2215 pCpu = HWACCMR0GetCurrentCpu();
2216 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
2217 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
2218 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2219 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
2220 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2221 {
2222 /* Force a TLB flush on VM entry. */
2223 pVCpu->hwaccm.s.fForceTLBFlush = true;
2224 }
2225 else
2226 Assert(!pCpu->fFlushTLB);
2227
2228 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
2229
2230 /* Check for tlb shootdown flushes. */
2231 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2232 pVCpu->hwaccm.s.fForceTLBFlush = true;
2233
2234 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
2235 if (pVCpu->hwaccm.s.fForceTLBFlush)
2236 {
2237 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
2238 || pCpu->fFlushTLB)
2239 {
2240 pCpu->fFlushTLB = false;
2241 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
2242 pCpu->cTLBFlushes++;
2243 vmxR0FlushVPID(pVM, pVCpu, VMX_FLUSH_ALL_CONTEXTS, 0);
2244 }
2245 else
2246 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
2247
2248 pVCpu->hwaccm.s.fForceTLBFlush = false;
2249 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
2250 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
2251 }
2252 else
2253 {
2254 Assert(!pCpu->fFlushTLB);
2255 Assert(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID);
2256
2257 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
2258 {
2259 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
2260 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
2261 for (unsigned i = 0; i < pVCpu->hwaccm.s.TlbShootdown.cPages; i++)
2262 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
2263 }
2264 }
2265 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
2266 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
2267
2268 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2269 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
2270 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
2271
2272 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
2273 AssertRC(rc);
2274
2275 if (pVCpu->hwaccm.s.fForceTLBFlush)
2276 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
2277
2278# ifdef VBOX_WITH_STATISTICS
2279 if (pVCpu->hwaccm.s.fForceTLBFlush)
2280 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
2281 else
2282 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
2283# endif
2284}
2285#endif /* HWACCM_VTX_WITH_VPID */
2286
2287/**
2288 * Runs guest code in a VT-x VM.
2289 *
2290 * @returns VBox status code.
2291 * @param pVM The VM to operate on.
2292 * @param pVCpu The VMCPU to operate on.
2293 * @param pCtx Guest context
2294 */
2295VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2296{
2297 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
2298 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hwaccm.s.StatExit1);
2299 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hwaccm.s.StatExit2);
2300
2301 VBOXSTRICTRC rc = VINF_SUCCESS;
2302 int rc2;
2303 RTGCUINTREG val;
2304 RTGCUINTREG exitReason = (RTGCUINTREG)VMX_EXIT_INVALID;
2305 RTGCUINTREG instrError, cbInstr;
2306 RTGCUINTPTR exitQualification = 0;
2307 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
2308 RTGCUINTPTR errCode, instrInfo;
2309 bool fSetupTPRCaching = false;
2310 uint64_t u64OldLSTAR = 0;
2311 uint8_t u8LastTPR = 0;
2312 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
2313 unsigned cResume = 0;
2314#ifdef VBOX_STRICT
2315 RTCPUID idCpuCheck;
2316 bool fWasInLongMode = false;
2317#endif
2318#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2319 uint64_t u64LastTime = RTTimeMilliTS();
2320#endif
2321
2322 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) || (pVCpu->hwaccm.s.vmx.pVAPIC && pVM->hwaccm.s.vmx.pAPIC));
2323
2324 /* Check if we need to use TPR shadowing. */
2325 if ( CPUMIsGuestInLongModeEx(pCtx)
2326 || ( ((pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) || pVM->hwaccm.s.fTRPPatchingAllowed)
2327 && pVM->hwaccm.s.fHasIoApic)
2328 )
2329 {
2330 fSetupTPRCaching = true;
2331 }
2332
2333 Log2(("\nE"));
2334
2335#ifdef VBOX_STRICT
2336 {
2337 RTCCUINTREG val2;
2338
2339 rc2 = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val2);
2340 AssertRC(rc2);
2341 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val2));
2342
2343 /* allowed zero */
2344 if ((val2 & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
2345 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
2346
2347 /* allowed one */
2348 if ((val2 & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
2349 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
2350
2351 rc2 = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val2);
2352 AssertRC(rc2);
2353 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val2));
2354
2355 /* Must be set according to the MSR, but can be cleared in case of EPT. */
2356 if (pVM->hwaccm.s.fNestedPaging)
2357 val2 |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
2358 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
2359 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
2360
2361 /* allowed zero */
2362 if ((val2 & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
2363 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
2364
2365 /* allowed one */
2366 if ((val2 & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
2367 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
2368
2369 rc2 = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val2);
2370 AssertRC(rc2);
2371 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val2));
2372
2373 /* allowed zero */
2374 if ((val2 & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
2375 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
2376
2377 /* allowed one */
2378 if ((val2 & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
2379 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
2380
2381 rc2 = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val2);
2382 AssertRC(rc2);
2383 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val2));
2384
2385 /* allowed zero */
2386 if ((val2 & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2387 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2388
2389 /* allowed one */
2390 if ((val2 & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2391 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2392 }
2393 fWasInLongMode = CPUMIsGuestInLongModeEx(pCtx);
2394#endif /* VBOX_STRICT */
2395
2396#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2397 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2398#endif
2399
2400 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2401 */
2402ResumeExecution:
2403 if (!STAM_REL_PROFILE_ADV_IS_RUNNING(&pVCpu->hwaccm.s.StatEntry))
2404 STAM_REL_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit2, &pVCpu->hwaccm.s.StatEntry, x);
2405 AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2406 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2407 (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2408 Assert(!HWACCMR0SuspendPending());
2409 /* Not allowed to switch modes without reloading the host state (32->64 switcher)!! */
2410 Assert(fWasInLongMode == CPUMIsGuestInLongModeEx(pCtx));
2411
2412 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2413 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
2414 {
2415 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2416 rc = VINF_EM_RAW_INTERRUPT;
2417 goto end;
2418 }
2419
2420 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2421 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2422 {
2423 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2424 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2425 {
2426 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2427 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2428 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2429 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2430 */
2431 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2432 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2433 rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2434 AssertRC(rc2);
2435 }
2436 }
2437 else
2438 {
2439 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2440 rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2441 AssertRC(rc2);
2442 }
2443
2444#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2445 if (RT_UNLIKELY((cResume & 0xf) == 0))
2446 {
2447 uint64_t u64CurTime = RTTimeMilliTS();
2448
2449 if (RT_UNLIKELY(u64CurTime > u64LastTime))
2450 {
2451 u64LastTime = u64CurTime;
2452 TMTimerPollVoid(pVM, pVCpu);
2453 }
2454 }
2455#endif
2456
2457 /* Check for pending actions that force us to go back to ring 3. */
2458 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
2459 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST))
2460 {
2461 /* Check if a sync operation is pending. */
2462 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2463 {
2464 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2465 if (rc != VINF_SUCCESS)
2466 {
2467 AssertRC(VBOXSTRICTRC_VAL(rc));
2468 Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", VBOXSTRICTRC_VAL(rc)));
2469 goto end;
2470 }
2471 }
2472
2473#ifdef DEBUG
2474 /* Intercept X86_XCPT_DB if stepping is enabled */
2475 if (!DBGFIsStepping(pVCpu))
2476#endif
2477 {
2478 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
2479 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
2480 {
2481 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2482 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2483 goto end;
2484 }
2485 }
2486
2487 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2488 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
2489 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
2490 {
2491 rc = VINF_EM_PENDING_REQUEST;
2492 goto end;
2493 }
2494
2495 /* Check if a pgm pool flush is in progress. */
2496 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2497 {
2498 rc = VINF_PGM_POOL_FLUSH_PENDING;
2499 goto end;
2500 }
2501
2502 /* Check if DMA work is pending (2nd+ run). */
2503 if (VM_FF_ISPENDING(pVM, VM_FF_PDM_DMA) && cResume > 1)
2504 {
2505 rc = VINF_EM_RAW_TO_R3;
2506 goto end;
2507 }
2508 }
2509
2510#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2511 /*
2512 * Exit to ring-3 preemption/work is pending.
2513 *
2514 * Interrupts are disabled before the call to make sure we don't miss any interrupt
2515 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
2516 * further down, but VMXR0CheckPendingInterrupt makes that impossible.)
2517 *
2518 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
2519 * shootdowns rely on this.
2520 */
2521 uOldEFlags = ASMIntDisableFlags();
2522 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2523 {
2524 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
2525 rc = VINF_EM_RAW_INTERRUPT;
2526 goto end;
2527 }
2528 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2529#endif
2530
2531 /* When external interrupts are pending, we should exit the VM when IF is set. */
2532 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2533 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2534 if (RT_FAILURE(rc))
2535 goto end;
2536
2537 /** @todo check timers?? */
2538
2539 /* TPR caching using CR8 is only available in 64 bits mode */
2540 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2541 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! (no longer true) */
2542 /**
2543 * @todo query and update the TPR only when it could have been changed (mmio access & wrmsr (x2apic))
2544 */
2545 if (fSetupTPRCaching)
2546 {
2547 /* TPR caching in CR8 */
2548 bool fPending;
2549
2550 rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
2551 AssertRC(rc2);
2552 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2553 pVCpu->hwaccm.s.vmx.pVAPIC[0x80] = u8LastTPR;
2554
2555 /* Two options here:
2556 * - external interrupt pending, but masked by the TPR value.
2557 * -> a CR8 update that lower the current TPR value should cause an exit
2558 * - no pending interrupts
2559 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2560 */
2561 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
2562 AssertRC(VBOXSTRICTRC_VAL(rc));
2563
2564 if (pVM->hwaccm.s.fTPRPatchingActive)
2565 {
2566 Assert(!CPUMIsGuestInLongModeEx(pCtx));
2567 /* Our patch code uses LSTAR for TPR caching. */
2568 pCtx->msrLSTAR = u8LastTPR;
2569
2570 if (fPending)
2571 {
2572 /* A TPR change could activate a pending interrupt, so catch lstar writes. */
2573 vmxR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
2574 }
2575 else
2576 {
2577 /* No interrupts are pending, so we don't need to be explicitely notified.
2578 * There are enough world switches for detecting pending interrupts.
2579 */
2580 vmxR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
2581 }
2582 }
2583 }
2584
2585#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2586 if ( pVM->hwaccm.s.fNestedPaging
2587# ifdef HWACCM_VTX_WITH_VPID
2588 || pVM->hwaccm.s.vmx.fVPID
2589# endif /* HWACCM_VTX_WITH_VPID */
2590 )
2591 {
2592 PHWACCM_CPUINFO pCpu;
2593
2594 pCpu = HWACCMR0GetCurrentCpu();
2595 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2596 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2597 {
2598 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2599 LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2600 else
2601 LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2602 }
2603 if (pCpu->fFlushTLB)
2604 LogFlow(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2605 else
2606 if (pVCpu->hwaccm.s.fForceTLBFlush)
2607 LogFlow(("Manual TLB flush\n"));
2608 }
2609#endif
2610#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2611 PGMRZDynMapFlushAutoSet(pVCpu);
2612#endif
2613
2614 /*
2615 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2616 * (until the actual world switch)
2617 */
2618#ifdef VBOX_STRICT
2619 idCpuCheck = RTMpCpuId();
2620#endif
2621#ifdef LOG_ENABLED
2622 VMMR0LogFlushDisable(pVCpu);
2623#endif
2624 /* Save the host state first. */
2625 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
2626 {
2627 rc = VMXR0SaveHostState(pVM, pVCpu);
2628 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2629 {
2630 VMMR0LogFlushEnable(pVCpu);
2631 goto end;
2632 }
2633 }
2634
2635 /* Load the guest state */
2636 if (!pVCpu->hwaccm.s.fContextUseFlags)
2637 {
2638 VMXR0LoadMinimalGuestState(pVM, pVCpu, pCtx);
2639 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatLoadMinimal);
2640 }
2641 else
2642 {
2643 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2644 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2645 {
2646 VMMR0LogFlushEnable(pVCpu);
2647 goto end;
2648 }
2649 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatLoadFull);
2650 }
2651
2652#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2653 /* Disable interrupts to make sure a poke will interrupt execution.
2654 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
2655 */
2656 uOldEFlags = ASMIntDisableFlags();
2657 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2658#endif
2659
2660 /* Non-register state Guest Context */
2661 /** @todo change me according to cpu state */
2662 rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2663 AssertRC(rc2);
2664
2665 /** Set TLB flush state as checked until we return from the world switch. */
2666 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, true);
2667 /* Deal with tagged TLB setup and invalidation. */
2668 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2669
2670 /* Manual save and restore:
2671 * - General purpose registers except RIP, RSP
2672 *
2673 * Trashed:
2674 * - CR2 (we don't care)
2675 * - LDTR (reset to 0)
2676 * - DRx (presumably not changed at all)
2677 * - DR7 (reset to 0x400)
2678 * - EFLAGS (reset to RT_BIT(1); not relevant)
2679 *
2680 */
2681
2682 /* All done! Let's start VM execution. */
2683 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatEntry, &pVCpu->hwaccm.s.StatInGC, x);
2684 Assert(idCpuCheck == RTMpCpuId());
2685
2686#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2687 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2688 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2689#endif
2690
2691 /* Save the current TPR value in the LSTAR msr so our patches can access it. */
2692 if (pVM->hwaccm.s.fTPRPatchingActive)
2693 {
2694 Assert(pVM->hwaccm.s.fTPRPatchingActive);
2695 u64OldLSTAR = ASMRdMsr(MSR_K8_LSTAR);
2696 ASMWrMsr(MSR_K8_LSTAR, u8LastTPR);
2697 }
2698
2699 TMNotifyStartOfExecution(pVCpu);
2700#ifdef VBOX_WITH_KERNEL_USING_XMM
2701 rc = hwaccmR0VMXStartVMWrapXMM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu, pVCpu->hwaccm.s.vmx.pfnStartVM);
2702#else
2703 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2704#endif
2705 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, false);
2706 ASMAtomicIncU32(&pVCpu->hwaccm.s.cWorldSwitchExit);
2707 /* Possibly the last TSC value seen by the guest (too high) (only when we're in tsc offset mode). */
2708 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT))
2709 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVCpu->hwaccm.s.vmx.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
2710
2711 TMNotifyEndOfExecution(pVCpu);
2712 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
2713 Assert(!(ASMGetFlags() & X86_EFL_IF));
2714
2715 /* Restore the host LSTAR msr if the guest could have changed it. */
2716 if (pVM->hwaccm.s.fTPRPatchingActive)
2717 {
2718 Assert(pVM->hwaccm.s.fTPRPatchingActive);
2719 pVCpu->hwaccm.s.vmx.pVAPIC[0x80] = pCtx->msrLSTAR = ASMRdMsr(MSR_K8_LSTAR);
2720 ASMWrMsr(MSR_K8_LSTAR, u64OldLSTAR);
2721 }
2722
2723 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatInGC, &pVCpu->hwaccm.s.StatExit1, x);
2724 ASMSetFlags(uOldEFlags);
2725#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2726 uOldEFlags = ~(RTCCUINTREG)0;
2727#endif
2728
2729 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2730
2731 /* In case we execute a goto ResumeExecution later on. */
2732 pVCpu->hwaccm.s.fResumeVM = true;
2733 pVCpu->hwaccm.s.fForceTLBFlush = false;
2734
2735 /*
2736 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2737 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2738 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2739 */
2740
2741 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2742 {
2743 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2744 VMMR0LogFlushEnable(pVCpu);
2745 goto end;
2746 }
2747
2748 /* Success. Query the guest state and figure out what has happened. */
2749
2750 /* Investigate why there was a VM-exit. */
2751 rc2 = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2752 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2753
2754 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2755 rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2756 rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2757 rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2758 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2759 rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2760 rc2 |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2761 rc2 |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2762 AssertRC(rc2);
2763
2764 /* Sync back the guest state */
2765 rc2 = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2766 AssertRC(rc2);
2767
2768 /* Note! NOW IT'S SAFE FOR LOGGING! */
2769 VMMR0LogFlushEnable(pVCpu);
2770 Log2(("Raw exit reason %08x\n", exitReason));
2771
2772 /* Check if an injected event was interrupted prematurely. */
2773 rc2 = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2774 AssertRC(rc2);
2775 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2776 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2777 /* Ignore 'int xx' as they'll be restarted anyway. */
2778 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2779 /* Ignore software exceptions (such as int3) as they'll reoccur when we restart the instruction anyway. */
2780 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2781 {
2782 Assert(!pVCpu->hwaccm.s.Event.fPending);
2783 pVCpu->hwaccm.s.Event.fPending = true;
2784 /* Error code present? */
2785 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2786 {
2787 rc2 = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2788 AssertRC(rc2);
2789 pVCpu->hwaccm.s.Event.errCode = val;
2790 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2791 }
2792 else
2793 {
2794 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2795 pVCpu->hwaccm.s.Event.errCode = 0;
2796 }
2797 }
2798#ifdef VBOX_STRICT
2799 else
2800 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2801 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2802 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2803 {
2804 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2805 }
2806
2807 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2808 HWACCMDumpRegs(pVM, pVCpu, pCtx);
2809#endif
2810
2811 Log2(("E%d: New EIP=%x:%RGv\n", (uint32_t)exitReason, pCtx->cs, (RTGCPTR)pCtx->rip));
2812 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2813 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2814 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2815 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2816
2817 /* Sync back the TPR if it was changed. */
2818 if ( fSetupTPRCaching
2819 && u8LastTPR != pVCpu->hwaccm.s.vmx.pVAPIC[0x80])
2820 {
2821 rc2 = PDMApicSetTPR(pVCpu, pVCpu->hwaccm.s.vmx.pVAPIC[0x80]);
2822 AssertRC(rc2);
2823 }
2824
2825 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit1, &pVCpu->hwaccm.s.StatExit2, x);
2826
2827 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2828 Assert(rc == VINF_SUCCESS); /* might consider VERR_IPE_UNINITIALIZED_STATUS here later... */
2829 switch (exitReason)
2830 {
2831 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2832 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2833 {
2834 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2835
2836 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2837 {
2838 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2839#if 0 //def VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2840 if ( RTThreadPreemptIsPendingTrusty()
2841 && !RTThreadPreemptIsPending(NIL_RTTHREAD))
2842 goto ResumeExecution;
2843#endif
2844 /* External interrupt; leave to allow it to be dispatched again. */
2845 rc = VINF_EM_RAW_INTERRUPT;
2846 break;
2847 }
2848 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2849 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2850 {
2851 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2852 /* External interrupt; leave to allow it to be dispatched again. */
2853 rc = VINF_EM_RAW_INTERRUPT;
2854 break;
2855
2856 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2857 AssertFailed(); /* can't come here; fails the first check. */
2858 break;
2859
2860 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2861 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2862 Assert(vector == 1 || vector == 3 || vector == 4);
2863 /* no break */
2864 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2865 Log2(("Hardware/software interrupt %d\n", vector));
2866 switch (vector)
2867 {
2868 case X86_XCPT_NM:
2869 {
2870 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2871
2872 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2873 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2874 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2875 if (rc == VINF_SUCCESS)
2876 {
2877 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2878
2879 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2880
2881 /* Continue execution. */
2882 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2883
2884 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2885 goto ResumeExecution;
2886 }
2887
2888 Log(("Forward #NM fault to the guest\n"));
2889 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2890 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2891 AssertRC(rc2);
2892 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2893 goto ResumeExecution;
2894 }
2895
2896 case X86_XCPT_PF: /* Page fault */
2897 {
2898#ifdef DEBUG
2899 if (pVM->hwaccm.s.fNestedPaging)
2900 { /* A genuine pagefault.
2901 * Forward the trap to the guest by injecting the exception and resuming execution.
2902 */
2903 Log(("Guest page fault at %RGv cr2=%RGv error code %RGv rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2904
2905 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2906
2907 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2908
2909 /* Now we must update CR2. */
2910 pCtx->cr2 = exitQualification;
2911 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2912 AssertRC(rc2);
2913
2914 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2915 goto ResumeExecution;
2916 }
2917#endif
2918 Assert(!pVM->hwaccm.s.fNestedPaging);
2919
2920#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2921 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
2922 if ( pVM->hwaccm.s.fTRPPatchingAllowed
2923 && pVM->hwaccm.s.pGuestPatchMem
2924 && (exitQualification & 0xfff) == 0x080
2925 && !(errCode & X86_TRAP_PF_P) /* not present */
2926 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
2927 && !CPUMIsGuestInLongModeEx(pCtx)
2928 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
2929 {
2930 RTGCPHYS GCPhysApicBase, GCPhys;
2931 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
2932 GCPhysApicBase &= PAGE_BASE_GC_MASK;
2933
2934 rc = PGMGstGetPage(pVCpu, (RTGCPTR)exitQualification, NULL, &GCPhys);
2935 if ( rc == VINF_SUCCESS
2936 && GCPhys == GCPhysApicBase)
2937 {
2938 /* Only attempt to patch the instruction once. */
2939 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2940 if (!pPatch)
2941 {
2942 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
2943 break;
2944 }
2945 }
2946 }
2947#endif
2948
2949 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2950 /* Exit qualification contains the linear address of the page fault. */
2951 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2952 TRPMSetErrorCode(pVCpu, errCode);
2953 TRPMSetFaultAddress(pVCpu, exitQualification);
2954
2955 /* Shortcut for APIC TPR reads and writes. */
2956 if ( (exitQualification & 0xfff) == 0x080
2957 && !(errCode & X86_TRAP_PF_P) /* not present */
2958 && fSetupTPRCaching
2959 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
2960 {
2961 RTGCPHYS GCPhysApicBase, GCPhys;
2962 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
2963 GCPhysApicBase &= PAGE_BASE_GC_MASK;
2964
2965 rc = PGMGstGetPage(pVCpu, (RTGCPTR)exitQualification, NULL, &GCPhys);
2966 if ( rc == VINF_SUCCESS
2967 && GCPhys == GCPhysApicBase)
2968 {
2969 Log(("Enable VT-x virtual APIC access filtering\n"));
2970 rc2 = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
2971 AssertRC(rc2);
2972 }
2973 }
2974
2975 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2976 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2977 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
2978
2979 if (rc == VINF_SUCCESS)
2980 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2981 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2982 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2983
2984 TRPMResetTrap(pVCpu);
2985 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2986 goto ResumeExecution;
2987 }
2988 else
2989 if (rc == VINF_EM_RAW_GUEST_TRAP)
2990 { /* A genuine pagefault.
2991 * Forward the trap to the guest by injecting the exception and resuming execution.
2992 */
2993 Log2(("Forward page fault to the guest\n"));
2994
2995 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2996 /* The error code might have been changed. */
2997 errCode = TRPMGetErrorCode(pVCpu);
2998
2999 TRPMResetTrap(pVCpu);
3000
3001 /* Now we must update CR2. */
3002 pCtx->cr2 = exitQualification;
3003 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
3004 AssertRC(rc2);
3005
3006 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
3007 goto ResumeExecution;
3008 }
3009#ifdef VBOX_STRICT
3010 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
3011 Log2(("PGMTrap0eHandler failed with %d\n", VBOXSTRICTRC_VAL(rc)));
3012#endif
3013 /* Need to go back to the recompiler to emulate the instruction. */
3014 TRPMResetTrap(pVCpu);
3015 break;
3016 }
3017
3018 case X86_XCPT_MF: /* Floating point exception. */
3019 {
3020 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
3021 if (!(pCtx->cr0 & X86_CR0_NE))
3022 {
3023 /* old style FPU error reporting needs some extra work. */
3024 /** @todo don't fall back to the recompiler, but do it manually. */
3025 rc = VINF_EM_RAW_EMULATE_INSTR;
3026 break;
3027 }
3028 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
3029 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
3030 AssertRC(rc2);
3031
3032 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
3033 goto ResumeExecution;
3034 }
3035
3036 case X86_XCPT_DB: /* Debug exception. */
3037 {
3038 uint64_t uDR6;
3039
3040 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
3041 *
3042 * Exit qualification bits:
3043 * 3:0 B0-B3 which breakpoint condition was met
3044 * 12:4 Reserved (0)
3045 * 13 BD - debug register access detected
3046 * 14 BS - single step execution or branch taken
3047 * 63:15 Reserved (0)
3048 */
3049 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
3050
3051 /* Note that we don't support guest and host-initiated debugging at the same time. */
3052
3053 uDR6 = X86_DR6_INIT_VAL;
3054 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
3055 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), uDR6);
3056 if (rc == VINF_EM_RAW_GUEST_TRAP)
3057 {
3058 /* Update DR6 here. */
3059 pCtx->dr[6] = uDR6;
3060
3061 /* Resync DR6 if the debug state is active. */
3062 if (CPUMIsGuestDebugStateActive(pVCpu))
3063 ASMSetDR6(pCtx->dr[6]);
3064
3065 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3066 pCtx->dr[7] &= ~X86_DR7_GD;
3067
3068 /* Paranoia. */
3069 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3070 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3071 pCtx->dr[7] |= 0x400; /* must be one */
3072
3073 /* Resync DR7 */
3074 rc2 = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3075 AssertRC(rc2);
3076
3077 Log(("Trap %x (debug) at %RGv exit qualification %RX64 dr6=%x dr7=%x\n", vector, (RTGCPTR)pCtx->rip, exitQualification, (uint32_t)pCtx->dr[6], (uint32_t)pCtx->dr[7]));
3078 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
3079 AssertRC(rc2);
3080
3081 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
3082 goto ResumeExecution;
3083 }
3084 /* Return to ring 3 to deal with the debug exit code. */
3085 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
3086 break;
3087 }
3088
3089 case X86_XCPT_BP: /* Breakpoint. */
3090 {
3091 rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3092 if (rc == VINF_EM_RAW_GUEST_TRAP)
3093 {
3094 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
3095 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
3096 AssertRC(rc2);
3097 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
3098 goto ResumeExecution;
3099 }
3100 if (rc == VINF_SUCCESS)
3101 {
3102 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
3103 goto ResumeExecution;
3104 }
3105 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
3106 break;
3107 }
3108
3109 case X86_XCPT_GP: /* General protection failure exception.*/
3110 {
3111 uint32_t cbOp;
3112 uint32_t cbSize;
3113 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
3114
3115 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
3116#ifdef VBOX_STRICT
3117 if ( !CPUMIsGuestInRealModeEx(pCtx)
3118 || !pVM->hwaccm.s.vmx.pRealModeTSS)
3119 {
3120 Log(("Trap %x at %04X:%RGv errorCode=%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
3121 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
3122 AssertRC(rc2);
3123 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
3124 goto ResumeExecution;
3125 }
3126#endif
3127 Assert(CPUMIsGuestInRealModeEx(pCtx));
3128
3129 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %x:%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip));
3130
3131 rc2 = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
3132 if (RT_SUCCESS(rc2))
3133 {
3134 bool fUpdateRIP = true;
3135
3136 rc = VINF_SUCCESS;
3137 Assert(cbOp == pDis->opsize);
3138 switch (pDis->pCurInstr->opcode)
3139 {
3140 case OP_CLI:
3141 pCtx->eflags.Bits.u1IF = 0;
3142 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCli);
3143 break;
3144
3145 case OP_STI:
3146 pCtx->eflags.Bits.u1IF = 1;
3147 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + pDis->opsize);
3148 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
3149 rc2 = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
3150 AssertRC(rc2);
3151 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti);
3152 break;
3153
3154 case OP_HLT:
3155 fUpdateRIP = false;
3156 rc = VINF_EM_HALT;
3157 pCtx->rip += pDis->opsize;
3158 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
3159 break;
3160
3161 case OP_POPF:
3162 {
3163 RTGCPTR GCPtrStack;
3164 uint32_t cbParm;
3165 uint32_t uMask;
3166 X86EFLAGS eflags;
3167
3168 if (pDis->prefix & PREFIX_OPSIZE)
3169 {
3170 cbParm = 4;
3171 uMask = 0xffffffff;
3172 }
3173 else
3174 {
3175 cbParm = 2;
3176 uMask = 0xffff;
3177 }
3178
3179 rc2 = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
3180 if (RT_FAILURE(rc2))
3181 {
3182 rc = VERR_EM_INTERPRETER;
3183 break;
3184 }
3185 eflags.u = 0;
3186 rc2 = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
3187 if (RT_FAILURE(rc2))
3188 {
3189 rc = VERR_EM_INTERPRETER;
3190 break;
3191 }
3192 LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask));
3193 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (eflags.u & X86_EFL_POPF_BITS & uMask);
3194 /* RF cleared when popped in real mode; see pushf description in AMD manual. */
3195 pCtx->eflags.Bits.u1RF = 0;
3196 pCtx->esp += cbParm;
3197 pCtx->esp &= uMask;
3198
3199 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPopf);
3200 break;
3201 }
3202
3203 case OP_PUSHF:
3204 {
3205 RTGCPTR GCPtrStack;
3206 uint32_t cbParm;
3207 uint32_t uMask;
3208 X86EFLAGS eflags;
3209
3210 if (pDis->prefix & PREFIX_OPSIZE)
3211 {
3212 cbParm = 4;
3213 uMask = 0xffffffff;
3214 }
3215 else
3216 {
3217 cbParm = 2;
3218 uMask = 0xffff;
3219 }
3220
3221 rc2 = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
3222 if (RT_FAILURE(rc2))
3223 {
3224 rc = VERR_EM_INTERPRETER;
3225 break;
3226 }
3227 eflags = pCtx->eflags;
3228 /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
3229 eflags.Bits.u1RF = 0;
3230 eflags.Bits.u1VM = 0;
3231
3232 rc2 = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
3233 if (RT_FAILURE(rc2))
3234 {
3235 rc = VERR_EM_INTERPRETER;
3236 break;
3237 }
3238 LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack));
3239 pCtx->esp -= cbParm;
3240 pCtx->esp &= uMask;
3241 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPushf);
3242 break;
3243 }
3244
3245 case OP_IRET:
3246 {
3247 RTGCPTR GCPtrStack;
3248 uint32_t uMask = 0xffff;
3249 uint16_t aIretFrame[3];
3250
3251 if (pDis->prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))
3252 {
3253 rc = VERR_EM_INTERPRETER;
3254 break;
3255 }
3256
3257 rc2 = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
3258 if (RT_FAILURE(rc2))
3259 {
3260 rc = VERR_EM_INTERPRETER;
3261 break;
3262 }
3263 rc2 = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
3264 if (RT_FAILURE(rc2))
3265 {
3266 rc = VERR_EM_INTERPRETER;
3267 break;
3268 }
3269 pCtx->ip = aIretFrame[0];
3270 pCtx->cs = aIretFrame[1];
3271 pCtx->csHid.u64Base = pCtx->cs << 4;
3272 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
3273 pCtx->sp += sizeof(aIretFrame);
3274
3275 LogFlow(("iret to %04x:%x\n", pCtx->cs, pCtx->ip));
3276 fUpdateRIP = false;
3277 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret);
3278 break;
3279 }
3280
3281 case OP_INT:
3282 {
3283 uint32_t intInfo2;
3284
3285 LogFlow(("Realmode: INT %x\n", pDis->param1.parval & 0xff));
3286 intInfo2 = pDis->param1.parval & 0xff;
3287 intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3288 intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3289
3290 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
3291 AssertRC(VBOXSTRICTRC_VAL(rc));
3292 fUpdateRIP = false;
3293 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
3294 break;
3295 }
3296
3297 case OP_INTO:
3298 {
3299 if (pCtx->eflags.Bits.u1OF)
3300 {
3301 uint32_t intInfo2;
3302
3303 LogFlow(("Realmode: INTO\n"));
3304 intInfo2 = X86_XCPT_OF;
3305 intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3306 intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3307
3308 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
3309 AssertRC(VBOXSTRICTRC_VAL(rc));
3310 fUpdateRIP = false;
3311 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
3312 }
3313 break;
3314 }
3315
3316 case OP_INT3:
3317 {
3318 uint32_t intInfo2;
3319
3320 LogFlow(("Realmode: INT 3\n"));
3321 intInfo2 = 3;
3322 intInfo2 |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3323 intInfo2 |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3324
3325 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo2, cbOp, 0);
3326 AssertRC(VBOXSTRICTRC_VAL(rc));
3327 fUpdateRIP = false;
3328 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
3329 break;
3330 }
3331
3332 default:
3333 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR, &cbSize);
3334 break;
3335 }
3336
3337 if (rc == VINF_SUCCESS)
3338 {
3339 if (fUpdateRIP)
3340 pCtx->rip += cbOp; /* Move on to the next instruction. */
3341
3342 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
3343 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3344
3345 /* Only resume if successful. */
3346 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
3347 goto ResumeExecution;
3348 }
3349 }
3350 else
3351 rc = VERR_EM_INTERPRETER;
3352
3353 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
3354 break;
3355 }
3356
3357#ifdef VBOX_STRICT
3358 case X86_XCPT_XF: /* SIMD exception. */
3359 case X86_XCPT_DE: /* Divide error. */
3360 case X86_XCPT_UD: /* Unknown opcode exception. */
3361 case X86_XCPT_SS: /* Stack segment exception. */
3362 case X86_XCPT_NP: /* Segment not present exception. */
3363 {
3364 switch(vector)
3365 {
3366 case X86_XCPT_DE:
3367 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
3368 break;
3369 case X86_XCPT_UD:
3370 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
3371 break;
3372 case X86_XCPT_SS:
3373 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
3374 break;
3375 case X86_XCPT_NP:
3376 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
3377 break;
3378 }
3379
3380 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
3381 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
3382 AssertRC(rc2);
3383
3384 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
3385 goto ResumeExecution;
3386 }
3387#endif
3388 default:
3389 if ( CPUMIsGuestInRealModeEx(pCtx)
3390 && pVM->hwaccm.s.vmx.pRealModeTSS)
3391 {
3392 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
3393 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
3394 AssertRC(VBOXSTRICTRC_VAL(rc)); /* Strict RC check below. */
3395
3396 /* Go back to ring 3 in case of a triple fault. */
3397 if ( vector == X86_XCPT_DF
3398 && rc == VINF_EM_RESET)
3399 break;
3400
3401 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
3402 goto ResumeExecution;
3403 }
3404 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
3405 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
3406 break;
3407 } /* switch (vector) */
3408
3409 break;
3410
3411 default:
3412 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
3413 AssertMsgFailed(("Unexpected interruption code %x\n", intInfo));
3414 break;
3415 }
3416
3417 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
3418 break;
3419 }
3420
3421 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
3422 {
3423 RTGCPHYS GCPhys;
3424
3425 Assert(pVM->hwaccm.s.fNestedPaging);
3426
3427 rc2 = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
3428 AssertRC(rc2);
3429 Assert(((exitQualification >> 7) & 3) != 2);
3430
3431 /* Determine the kind of violation. */
3432 errCode = 0;
3433 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
3434 errCode |= X86_TRAP_PF_ID;
3435
3436 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
3437 errCode |= X86_TRAP_PF_RW;
3438
3439 /* If the page is present, then it's a page level protection fault. */
3440 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
3441 {
3442 errCode |= X86_TRAP_PF_P;
3443 }
3444 else
3445 {
3446 /* Shortcut for APIC TPR reads and writes. */
3447 if ( (GCPhys & 0xfff) == 0x080
3448 && GCPhys > 0x1000000 /* to skip VGA frame buffer accesses */
3449 && fSetupTPRCaching
3450 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
3451 {
3452 RTGCPHYS GCPhysApicBase;
3453 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
3454 GCPhysApicBase &= PAGE_BASE_GC_MASK;
3455 if (GCPhys == GCPhysApicBase + 0x80)
3456 {
3457 Log(("Enable VT-x virtual APIC access filtering\n"));
3458 rc2 = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
3459 AssertRC(rc2);
3460 }
3461 }
3462 }
3463 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
3464
3465 /* GCPhys contains the guest physical address of the page fault. */
3466 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
3467 TRPMSetErrorCode(pVCpu, errCode);
3468 TRPMSetFaultAddress(pVCpu, GCPhys);
3469
3470 /* Handle the pagefault trap for the nested shadow table. */
3471 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
3472 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
3473 if (rc == VINF_SUCCESS)
3474 { /* We've successfully synced our shadow pages, so let's just continue execution. */
3475 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
3476 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
3477
3478 TRPMResetTrap(pVCpu);
3479 goto ResumeExecution;
3480 }
3481
3482#ifdef VBOX_STRICT
3483 if (rc != VINF_EM_RAW_EMULATE_INSTR)
3484 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", VBOXSTRICTRC_VAL(rc)));
3485#endif
3486 /* Need to go back to the recompiler to emulate the instruction. */
3487 TRPMResetTrap(pVCpu);
3488 break;
3489 }
3490
3491 case VMX_EXIT_EPT_MISCONFIG:
3492 {
3493 RTGCPHYS GCPhys;
3494
3495 Assert(pVM->hwaccm.s.fNestedPaging);
3496
3497 rc2 = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
3498 AssertRC(rc2);
3499 Log(("VMX_EXIT_EPT_MISCONFIG for %RGp\n", GCPhys));
3500
3501 /* Shortcut for APIC TPR reads and writes. */
3502 if ( (GCPhys & 0xfff) == 0x080
3503 && GCPhys > 0x1000000 /* to skip VGA frame buffer accesses */
3504 && fSetupTPRCaching
3505 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
3506 {
3507 RTGCPHYS GCPhysApicBase;
3508 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
3509 GCPhysApicBase &= PAGE_BASE_GC_MASK;
3510 if (GCPhys == GCPhysApicBase + 0x80)
3511 {
3512 Log(("Enable VT-x virtual APIC access filtering\n"));
3513 rc2 = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
3514 AssertRC(rc2);
3515 }
3516 }
3517
3518 rc = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, CPUMCTX2CORE(pCtx), GCPhys, UINT32_MAX);
3519 if (rc == VINF_SUCCESS)
3520 {
3521 Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhys, (RTGCPTR)pCtx->rip));
3522 goto ResumeExecution;
3523 }
3524
3525 Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> %Rrc\n", GCPhys, (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
3526 break;
3527 }
3528
3529 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3530 /* Clear VM-exit on IF=1 change. */
3531 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
3532 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
3533 rc2 = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3534 AssertRC(rc2);
3535 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
3536 goto ResumeExecution; /* we check for pending guest interrupts there */
3537
3538 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
3539 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
3540 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
3541 /* Skip instruction and continue directly. */
3542 pCtx->rip += cbInstr;
3543 /* Continue execution.*/
3544 goto ResumeExecution;
3545
3546 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3547 {
3548 Log2(("VMX: Cpuid %x\n", pCtx->eax));
3549 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
3550 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3551 if (rc == VINF_SUCCESS)
3552 {
3553 /* Update EIP and continue execution. */
3554 Assert(cbInstr == 2);
3555 pCtx->rip += cbInstr;
3556 goto ResumeExecution;
3557 }
3558 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
3559 rc = VINF_EM_RAW_EMULATE_INSTR;
3560 break;
3561 }
3562
3563 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3564 {
3565 Log2(("VMX: Rdpmc %x\n", pCtx->ecx));
3566 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
3567 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3568 if (rc == VINF_SUCCESS)
3569 {
3570 /* Update EIP and continue execution. */
3571 Assert(cbInstr == 2);
3572 pCtx->rip += cbInstr;
3573 goto ResumeExecution;
3574 }
3575 rc = VINF_EM_RAW_EMULATE_INSTR;
3576 break;
3577 }
3578
3579 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3580 {
3581 Log2(("VMX: Rdtsc\n"));
3582 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
3583 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3584 if (rc == VINF_SUCCESS)
3585 {
3586 /* Update EIP and continue execution. */
3587 Assert(cbInstr == 2);
3588 pCtx->rip += cbInstr;
3589 goto ResumeExecution;
3590 }
3591 rc = VINF_EM_RAW_EMULATE_INSTR;
3592 break;
3593 }
3594
3595 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3596 {
3597 Log2(("VMX: invlpg\n"));
3598 Assert(!pVM->hwaccm.s.fNestedPaging);
3599
3600 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
3601 rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification);
3602 if (rc == VINF_SUCCESS)
3603 {
3604 /* Update EIP and continue execution. */
3605 pCtx->rip += cbInstr;
3606 goto ResumeExecution;
3607 }
3608 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, VBOXSTRICTRC_VAL(rc)));
3609 break;
3610 }
3611
3612 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3613 {
3614 Log2(("VMX: monitor\n"));
3615
3616 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMonitor);
3617 rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3618 if (rc == VINF_SUCCESS)
3619 {
3620 /* Update EIP and continue execution. */
3621 pCtx->rip += cbInstr;
3622 goto ResumeExecution;
3623 }
3624 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: monitor failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
3625 break;
3626 }
3627
3628 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3629 /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
3630 if ( pVM->hwaccm.s.fTPRPatchingActive
3631 && pCtx->ecx == MSR_K8_LSTAR)
3632 {
3633 Assert(!CPUMIsGuestInLongModeEx(pCtx));
3634 if ((pCtx->eax & 0xff) != u8LastTPR)
3635 {
3636 Log(("VMX: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
3637
3638 /* Our patch code uses LSTAR for TPR caching. */
3639 rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
3640 AssertRC(rc2);
3641 }
3642
3643 /* Skip the instruction and continue. */
3644 pCtx->rip += cbInstr; /* wrmsr = [0F 30] */
3645
3646 /* Only resume if successful. */
3647 goto ResumeExecution;
3648 }
3649 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_MSR;
3650 /* no break */
3651 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3652 {
3653 uint32_t cbSize;
3654
3655 STAM_COUNTER_INC((exitReason == VMX_EXIT_RDMSR) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
3656
3657 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
3658 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
3659 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
3660 if (rc == VINF_SUCCESS)
3661 {
3662 /* EIP has been updated already. */
3663
3664 /* Only resume if successful. */
3665 goto ResumeExecution;
3666 }
3667 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", VBOXSTRICTRC_VAL(rc)));
3668 break;
3669 }
3670
3671 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3672 {
3673 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3674
3675 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
3676 {
3677 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
3678 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
3679 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3680 rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3681 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
3682 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
3683
3684 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
3685 {
3686 case 0:
3687 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
3688 break;
3689 case 2:
3690 break;
3691 case 3:
3692 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
3693 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
3694 break;
3695 case 4:
3696 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
3697 break;
3698 case 8:
3699 /* CR8 contains the APIC TPR */
3700 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3701 break;
3702
3703 default:
3704 AssertFailed();
3705 break;
3706 }
3707 break;
3708
3709 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
3710 Log2(("VMX: mov x, crx\n"));
3711 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3712
3713 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
3714
3715 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
3716 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3717
3718 rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3719 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
3720 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
3721 break;
3722
3723 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
3724 Log2(("VMX: clts\n"));
3725 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
3726 rc = EMInterpretCLTS(pVM, pVCpu);
3727 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3728 break;
3729
3730 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
3731 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
3732 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
3733 rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
3734 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3735 break;
3736 }
3737
3738 /* Update EIP if no error occurred. */
3739 if (RT_SUCCESS(rc))
3740 pCtx->rip += cbInstr;
3741
3742 if (rc == VINF_SUCCESS)
3743 {
3744 /* Only resume if successful. */
3745 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3746 goto ResumeExecution;
3747 }
3748 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
3749 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3750 break;
3751 }
3752
3753 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3754 {
3755 if ( !DBGFIsStepping(pVCpu)
3756 && !CPUMIsHyperDebugStateActive(pVCpu))
3757 {
3758 /* Disable drx move intercepts. */
3759 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3760 rc2 = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3761 AssertRC(rc2);
3762
3763 /* Save the host and load the guest debug state. */
3764 rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3765 AssertRC(rc2);
3766
3767#ifdef LOG_ENABLED
3768 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3769 Log(("VMX_EXIT_DRX_MOVE: write DR%d genreg %d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
3770 else
3771 Log(("VMX_EXIT_DRX_MOVE: read DR%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification)));
3772#endif
3773
3774#ifdef VBOX_WITH_STATISTICS
3775 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
3776 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3777 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3778 else
3779 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3780#endif
3781
3782 goto ResumeExecution;
3783 }
3784
3785 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
3786 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3787 {
3788 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
3789 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3790 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3791 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
3792 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
3793 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3794 Log2(("DR7=%08x\n", pCtx->dr[7]));
3795 }
3796 else
3797 {
3798 Log2(("VMX: mov x, drx\n"));
3799 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3800 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3801 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
3802 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
3803 }
3804 /* Update EIP if no error occurred. */
3805 if (RT_SUCCESS(rc))
3806 pCtx->rip += cbInstr;
3807
3808 if (rc == VINF_SUCCESS)
3809 {
3810 /* Only resume if successful. */
3811 goto ResumeExecution;
3812 }
3813 Assert(rc == VERR_EM_INTERPRETER);
3814 break;
3815 }
3816
3817 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
3818 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3819 {
3820 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3821 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
3822 uint32_t uPort;
3823 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
3824
3825 /** @todo necessary to make the distinction? */
3826 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
3827 {
3828 uPort = pCtx->edx & 0xffff;
3829 }
3830 else
3831 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
3832
3833 /* paranoia */
3834 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
3835 {
3836 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
3837 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3838 break;
3839 }
3840
3841 uint32_t cbSize = g_aIOSize[uIOWidth];
3842
3843 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
3844 {
3845 /* ins/outs */
3846 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
3847
3848 /* Disassemble manually to deal with segment prefixes. */
3849 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
3850 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
3851 rc2 = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
3852 if (RT_SUCCESS(rc))
3853 {
3854 if (fIOWrite)
3855 {
3856 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3857 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
3858 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3859 }
3860 else
3861 {
3862 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3863 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
3864 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3865 }
3866 }
3867 else
3868 rc = VINF_EM_RAW_EMULATE_INSTR;
3869 }
3870 else
3871 {
3872 /* normal in/out */
3873 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
3874
3875 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
3876
3877 if (fIOWrite)
3878 {
3879 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
3880 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
3881 if (rc == VINF_IOM_HC_IOPORT_WRITE)
3882 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pCtx->rip + cbInstr, uPort, uAndVal, cbSize);
3883 }
3884 else
3885 {
3886 uint32_t u32Val = 0;
3887
3888 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
3889 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
3890 if (IOM_SUCCESS(rc))
3891 {
3892 /* Write back to the EAX register. */
3893 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3894 }
3895 else
3896 if (rc == VINF_IOM_HC_IOPORT_READ)
3897 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pCtx->rip + cbInstr, uPort, uAndVal, cbSize);
3898 }
3899 }
3900 /*
3901 * Handled the I/O return codes.
3902 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
3903 */
3904 if (IOM_SUCCESS(rc))
3905 {
3906 /* Update EIP and continue execution. */
3907 pCtx->rip += cbInstr;
3908 if (RT_LIKELY(rc == VINF_SUCCESS))
3909 {
3910 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3911 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3912 {
3913 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3914 for (unsigned i=0;i<4;i++)
3915 {
3916 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3917
3918 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3919 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
3920 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3921 {
3922 uint64_t uDR6;
3923
3924 Assert(CPUMIsGuestDebugStateActive(pVCpu));
3925
3926 uDR6 = ASMGetDR6();
3927
3928 /* Clear all breakpoint status flags and set the one we just hit. */
3929 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3930 uDR6 |= (uint64_t)RT_BIT(i);
3931
3932 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3933 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3934 * the contents have been read.
3935 */
3936 ASMSetDR6(uDR6);
3937
3938 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3939 pCtx->dr[7] &= ~X86_DR7_GD;
3940
3941 /* Paranoia. */
3942 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3943 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3944 pCtx->dr[7] |= 0x400; /* must be one */
3945
3946 /* Resync DR7 */
3947 rc2 = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3948 AssertRC(rc2);
3949
3950 /* Construct inject info. */
3951 intInfo = X86_XCPT_DB;
3952 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3953 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3954
3955 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3956 rc2 = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3957 AssertRC(rc2);
3958
3959 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3960 goto ResumeExecution;
3961 }
3962 }
3963 }
3964 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3965 goto ResumeExecution;
3966 }
3967 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3968 break;
3969 }
3970
3971#ifdef VBOX_STRICT
3972 if (rc == VINF_IOM_HC_IOPORT_READ)
3973 Assert(!fIOWrite);
3974 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3975 Assert(fIOWrite);
3976 else
3977 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rc)));
3978#endif
3979 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3980 break;
3981 }
3982
3983 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3984 LogFlow(("VMX_EXIT_TPR\n"));
3985 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3986 goto ResumeExecution;
3987
3988 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3989 {
3990 LogFlow(("VMX_EXIT_APIC_ACCESS\n"));
3991 unsigned uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(exitQualification);
3992
3993 switch(uAccessType)
3994 {
3995 case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
3996 case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
3997 {
3998 RTGCPHYS GCPhys;
3999 PDMApicGetBase(pVM, &GCPhys);
4000 GCPhys &= PAGE_BASE_GC_MASK;
4001 GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification);
4002
4003 LogFlow(("Apic access at %RGp\n", GCPhys));
4004 rc = IOMMMIOPhysHandler(pVM, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW, CPUMCTX2CORE(pCtx), GCPhys);
4005 if (rc == VINF_SUCCESS)
4006 goto ResumeExecution; /* rip already updated */
4007 break;
4008 }
4009
4010 default:
4011 rc = VINF_EM_RAW_EMULATE_INSTR;
4012 break;
4013 }
4014 break;
4015 }
4016
4017 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
4018 if (!TMTimerPollBool(pVM, pVCpu))
4019 goto ResumeExecution;
4020 rc = VINF_EM_RAW_TIMER_PENDING;
4021 break;
4022
4023 default:
4024 /* The rest is handled after syncing the entire CPU state. */
4025 break;
4026 }
4027
4028 /* Note: the guest state isn't entirely synced back at this stage. */
4029
4030 /* Investigate why there was a VM-exit. (part 2) */
4031 switch (exitReason)
4032 {
4033 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
4034 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
4035 case VMX_EXIT_EPT_VIOLATION:
4036 case VMX_EXIT_EPT_MISCONFIG: /* 49 EPT misconfig is used by the PGM/MMIO optimizations. */
4037 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
4038 /* Already handled above. */
4039 break;
4040
4041 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
4042 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
4043 break;
4044
4045 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
4046 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
4047 rc = VINF_EM_RAW_INTERRUPT;
4048 AssertFailed(); /* Can't happen. Yet. */
4049 break;
4050
4051 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
4052 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
4053 rc = VINF_EM_RAW_INTERRUPT;
4054 AssertFailed(); /* Can't happen afaik. */
4055 break;
4056
4057 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch: too complicated to emulate, so fall back to the recompiler */
4058 Log(("VMX_EXIT_TASK_SWITCH: exit=%RX64\n", exitQualification));
4059 if ( (VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(exitQualification) == VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT)
4060 && pVCpu->hwaccm.s.Event.fPending)
4061 {
4062 /* Caused by an injected interrupt. */
4063 pVCpu->hwaccm.s.Event.fPending = false;
4064
4065 Log(("VMX_EXIT_TASK_SWITCH: reassert trap %d\n", VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hwaccm.s.Event.intInfo)));
4066 Assert(!VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo));
4067 rc2 = TRPMAssertTrap(pVCpu, VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVCpu->hwaccm.s.Event.intInfo), TRPM_HARDWARE_INT);
4068 AssertRC(rc2);
4069 }
4070 /* else Exceptions and software interrupts can just be restarted. */
4071 rc = VERR_EM_INTERPRETER;
4072 break;
4073
4074 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
4075 /** Check if external interrupts are pending; if so, don't switch back. */
4076 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
4077 pCtx->rip++; /* skip hlt */
4078 if (EMShouldContinueAfterHalt(pVCpu, pCtx))
4079 goto ResumeExecution;
4080
4081 rc = VINF_EM_HALT;
4082 break;
4083
4084 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
4085 Log2(("VMX: mwait\n"));
4086 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
4087 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4088 if ( rc == VINF_EM_HALT
4089 || rc == VINF_SUCCESS)
4090 {
4091 /* Update EIP and continue execution. */
4092 pCtx->rip += cbInstr;
4093
4094 /** Check if external interrupts are pending; if so, don't switch back. */
4095 if ( rc == VINF_SUCCESS
4096 || ( rc == VINF_EM_HALT
4097 && EMShouldContinueAfterHalt(pVCpu, pCtx))
4098 )
4099 goto ResumeExecution;
4100 }
4101 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
4102 break;
4103
4104 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
4105 AssertFailed(); /* can't happen. */
4106 rc = VERR_EM_INTERPRETER;
4107 break;
4108
4109 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
4110 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
4111 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
4112 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
4113 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
4114 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
4115 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
4116 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
4117 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
4118 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
4119 /** @todo inject #UD immediately */
4120 rc = VERR_EM_INTERPRETER;
4121 break;
4122
4123 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
4124 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
4125 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
4126 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
4127 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
4128 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
4129 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
4130 /* already handled above */
4131 AssertMsg( rc == VINF_PGM_CHANGE_MODE
4132 || rc == VINF_EM_RAW_INTERRUPT
4133 || rc == VERR_EM_INTERPRETER
4134 || rc == VINF_EM_RAW_EMULATE_INSTR
4135 || rc == VINF_PGM_SYNC_CR3
4136 || rc == VINF_IOM_HC_IOPORT_READ
4137 || rc == VINF_IOM_HC_IOPORT_WRITE
4138 || rc == VINF_EM_RAW_GUEST_TRAP
4139 || rc == VINF_TRPM_XCPT_DISPATCHED
4140 || rc == VINF_EM_RESCHEDULE_REM,
4141 ("rc = %d\n", VBOXSTRICTRC_VAL(rc)));
4142 break;
4143
4144 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
4145 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
4146 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
4147 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
4148 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
4149 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
4150 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
4151 rc = VERR_EM_INTERPRETER;
4152 break;
4153
4154 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
4155 Assert(rc == VINF_EM_RAW_INTERRUPT);
4156 break;
4157
4158 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
4159 {
4160#ifdef VBOX_STRICT
4161 RTCCUINTREG val2 = 0;
4162
4163 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
4164
4165 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val2);
4166 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val2));
4167
4168 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val2);
4169 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val2));
4170
4171 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val2);
4172 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val2));
4173
4174 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val2);
4175 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val2));
4176
4177 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val2);
4178 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val2));
4179
4180 VMX_LOG_SELREG(CS, "CS", val2);
4181 VMX_LOG_SELREG(DS, "DS", val2);
4182 VMX_LOG_SELREG(ES, "ES", val2);
4183 VMX_LOG_SELREG(FS, "FS", val2);
4184 VMX_LOG_SELREG(GS, "GS", val2);
4185 VMX_LOG_SELREG(SS, "SS", val2);
4186 VMX_LOG_SELREG(TR, "TR", val2);
4187 VMX_LOG_SELREG(LDTR, "LDTR", val2);
4188
4189 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val2);
4190 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val2));
4191 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val2);
4192 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val2));
4193#endif /* VBOX_STRICT */
4194 rc = VERR_VMX_INVALID_GUEST_STATE;
4195 break;
4196 }
4197
4198 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
4199 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
4200 default:
4201 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
4202 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
4203 break;
4204
4205 }
4206end:
4207
4208 /* We now going back to ring-3, so clear the action flag. */
4209 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
4210
4211 /* Signal changes for the recompiler. */
4212 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
4213
4214 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
4215 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
4216 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
4217 {
4218 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
4219 /* On the next entry we'll only sync the host context. */
4220 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
4221 }
4222 else
4223 {
4224 /* On the next entry we'll sync everything. */
4225 /** @todo we can do better than this */
4226 /* Not in the VINF_PGM_CHANGE_MODE though! */
4227 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
4228 }
4229
4230 /* translate into a less severe return code */
4231 if (rc == VERR_EM_INTERPRETER)
4232 rc = VINF_EM_RAW_EMULATE_INSTR;
4233 else
4234 /* Try to extract more information about what might have gone wrong here. */
4235 if (rc == VERR_VMX_INVALID_VMCS_PTR)
4236 {
4237 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
4238 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
4239 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
4240 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
4241 }
4242
4243 /* Just set the correct state here instead of trying to catch every goto above. */
4244 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
4245
4246#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
4247 /* Restore interrupts if we exitted after disabling them. */
4248 if (uOldEFlags != ~(RTCCUINTREG)0)
4249 ASMSetFlags(uOldEFlags);
4250#endif
4251
4252 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, x);
4253 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
4254 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
4255 Log2(("X"));
4256 return VBOXSTRICTRC_TODO(rc);
4257}
4258
4259
4260/**
4261 * Enters the VT-x session
4262 *
4263 * @returns VBox status code.
4264 * @param pVM The VM to operate on.
4265 * @param pVCpu The VMCPU to operate on.
4266 * @param pCpu CPU info struct
4267 */
4268VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
4269{
4270 Assert(pVM->hwaccm.s.vmx.fSupported);
4271
4272 unsigned cr4 = ASMGetCR4();
4273 if (!(cr4 & X86_CR4_VMXE))
4274 {
4275 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
4276 return VERR_VMX_X86_CR4_VMXE_CLEARED;
4277 }
4278
4279 /* Activate the VM Control Structure. */
4280 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4281 if (RT_FAILURE(rc))
4282 return rc;
4283
4284 pVCpu->hwaccm.s.fResumeVM = false;
4285 return VINF_SUCCESS;
4286}
4287
4288
4289/**
4290 * Leaves the VT-x session
4291 *
4292 * @returns VBox status code.
4293 * @param pVM The VM to operate on.
4294 * @param pVCpu The VMCPU to operate on.
4295 * @param pCtx CPU context
4296 */
4297VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4298{
4299 Assert(pVM->hwaccm.s.vmx.fSupported);
4300
4301#ifdef DEBUG
4302 if (CPUMIsHyperDebugStateActive(pVCpu))
4303 {
4304 CPUMR0LoadHostDebugState(pVM, pVCpu);
4305 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
4306 }
4307 else
4308#endif
4309 /* Save the guest debug state if necessary. */
4310 if (CPUMIsGuestDebugStateActive(pVCpu))
4311 {
4312 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
4313
4314 /* Enable drx move intercepts again. */
4315 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
4316 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
4317 AssertRC(rc);
4318
4319 /* Resync the debug registers the next time. */
4320 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
4321 }
4322 else
4323 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
4324
4325 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
4326 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4327 AssertRC(rc);
4328
4329 return VINF_SUCCESS;
4330}
4331
4332/**
4333 * Flush the TLB (EPT)
4334 *
4335 * @returns VBox status code.
4336 * @param pVM The VM to operate on.
4337 * @param pVCpu The VM CPU to operate on.
4338 * @param enmFlush Type of flush
4339 * @param GCPhys Physical address of the page to flush
4340 */
4341static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
4342{
4343 uint64_t descriptor[2];
4344
4345 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
4346 Assert(pVM->hwaccm.s.fNestedPaging);
4347 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
4348 descriptor[1] = GCPhys;
4349 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
4350 AssertRC(rc);
4351}
4352
4353#ifdef HWACCM_VTX_WITH_VPID
4354/**
4355 * Flush the TLB (EPT)
4356 *
4357 * @returns VBox status code.
4358 * @param pVM The VM to operate on.
4359 * @param pVCpu The VM CPU to operate on.
4360 * @param enmFlush Type of flush
4361 * @param GCPtr Virtual address of the page to flush
4362 */
4363static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
4364{
4365#if HC_ARCH_BITS == 32
4366 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
4367 if ( CPUMIsGuestInLongMode(pVCpu)
4368 && !VMX_IS_64BIT_HOST_MODE())
4369 {
4370 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
4371 }
4372 else
4373#endif
4374 {
4375 uint64_t descriptor[2];
4376
4377 Assert(pVM->hwaccm.s.vmx.fVPID);
4378 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
4379 descriptor[1] = GCPtr;
4380 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
4381 AssertMsg(rc == VINF_SUCCESS, ("VMXR0InvVPID %x %x %RGv failed with %d\n", enmFlush, pVCpu->hwaccm.s.uCurrentASID, GCPtr, rc));
4382 }
4383}
4384#endif /* HWACCM_VTX_WITH_VPID */
4385
4386/**
4387 * Invalidates a guest page
4388 *
4389 * @returns VBox status code.
4390 * @param pVM The VM to operate on.
4391 * @param pVCpu The VM CPU to operate on.
4392 * @param GCVirt Page to invalidate
4393 */
4394VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
4395{
4396 bool fFlushPending = VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
4397
4398 Log2(("VMXR0InvalidatePage %RGv\n", GCVirt));
4399
4400 /* Only relevant if we want to use VPID.
4401 * In the nested paging case we still see such calls, but
4402 * can safely ignore them. (e.g. after cr3 updates)
4403 */
4404#ifdef HWACCM_VTX_WITH_VPID
4405 /* Skip it if a TLB flush is already pending. */
4406 if ( !fFlushPending
4407 && pVM->hwaccm.s.vmx.fVPID)
4408 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
4409#endif /* HWACCM_VTX_WITH_VPID */
4410
4411 return VINF_SUCCESS;
4412}
4413
4414/**
4415 * Invalidates a guest page by physical address
4416 *
4417 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
4418 *
4419 * @returns VBox status code.
4420 * @param pVM The VM to operate on.
4421 * @param pVCpu The VM CPU to operate on.
4422 * @param GCPhys Page to invalidate
4423 */
4424VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
4425{
4426 bool fFlushPending = VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
4427
4428 Assert(pVM->hwaccm.s.fNestedPaging);
4429
4430 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
4431
4432 /* Skip it if a TLB flush is already pending. */
4433 if (!fFlushPending)
4434 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
4435
4436 return VINF_SUCCESS;
4437}
4438
4439/**
4440 * Report world switch error and dump some useful debug info
4441 *
4442 * @param pVM The VM to operate on.
4443 * @param pVCpu The VMCPU to operate on.
4444 * @param rc Return code
4445 * @param pCtx Current CPU context (not updated)
4446 */
4447static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc, PCPUMCTX pCtx)
4448{
4449 switch (VBOXSTRICTRC_VAL(rc))
4450 {
4451 case VERR_VMX_INVALID_VMXON_PTR:
4452 AssertFailed();
4453 break;
4454
4455 case VERR_VMX_UNABLE_TO_START_VM:
4456 case VERR_VMX_UNABLE_TO_RESUME_VM:
4457 {
4458 int rc2;
4459 RTCCUINTREG exitReason, instrError;
4460
4461 rc2 = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
4462 rc2 |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
4463 AssertRC(rc2);
4464 if (rc2 == VINF_SUCCESS)
4465 {
4466 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
4467 Log(("Current stack %08x\n", &rc2));
4468
4469 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
4470 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
4471
4472#ifdef VBOX_STRICT
4473 RTGDTR gdtr;
4474 PCX86DESCHC pDesc;
4475 RTCCUINTREG val;
4476
4477 ASMGetGDTR(&gdtr);
4478
4479 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
4480 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
4481 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
4482 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
4483 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
4484 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
4485 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
4486 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
4487 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
4488 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
4489
4490 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
4491 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
4492
4493 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
4494 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
4495
4496 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
4497 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
4498
4499 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
4500 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
4501
4502 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
4503 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
4504
4505 if (val < gdtr.cbGdt)
4506 {
4507 pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
4508 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
4509 }
4510
4511 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
4512 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
4513 if (val < gdtr.cbGdt)
4514 {
4515 pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
4516 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
4517 }
4518
4519 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
4520 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
4521 if (val < gdtr.cbGdt)
4522 {
4523 pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
4524 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
4525 }
4526
4527 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
4528 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
4529 if (val < gdtr.cbGdt)
4530 {
4531 pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
4532 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
4533 }
4534
4535 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
4536 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
4537 if (val < gdtr.cbGdt)
4538 {
4539 pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
4540 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
4541 }
4542
4543 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
4544 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
4545 if (val < gdtr.cbGdt)
4546 {
4547 pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
4548 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
4549 }
4550
4551 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
4552 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
4553 if (val < gdtr.cbGdt)
4554 {
4555 pDesc = (PCX86DESCHC)(gdtr.pGdt + (val & X86_SEL_MASK));
4556 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
4557 }
4558
4559 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
4560 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
4561
4562 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
4563 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
4564 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
4565 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
4566
4567 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
4568 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
4569
4570 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
4571 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
4572
4573 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
4574 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
4575
4576 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
4577 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
4578 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
4579 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
4580
4581# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4582 if (VMX_IS_64BIT_HOST_MODE())
4583 {
4584 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
4585 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
4586 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
4587 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
4588 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
4589 }
4590# endif
4591#endif /* VBOX_STRICT */
4592 }
4593 break;
4594 }
4595
4596 default:
4597 /* impossible */
4598 AssertMsgFailed(("%Rrc (%#x)\n", VBOXSTRICTRC_VAL(rc), VBOXSTRICTRC_VAL(rc)));
4599 break;
4600 }
4601}
4602
4603#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4604/**
4605 * Prepares for and executes VMLAUNCH (64 bits guest mode)
4606 *
4607 * @returns VBox status code
4608 * @param fResume vmlauch/vmresume
4609 * @param pCtx Guest context
4610 * @param pCache VMCS cache
4611 * @param pVM The VM to operate on.
4612 * @param pVCpu The VMCPU to operate on.
4613 */
4614DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
4615{
4616 uint32_t aParam[6];
4617 PHWACCM_CPUINFO pCpu;
4618 RTHCPHYS HCPhysCpuPage;
4619 int rc;
4620
4621 pCpu = HWACCMR0GetCurrentCpu();
4622 HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
4623
4624#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4625 pCache->uPos = 1;
4626 pCache->interPD = PGMGetInterPaeCR3(pVM);
4627 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
4628#endif
4629
4630#ifdef DEBUG
4631 pCache->TestIn.HCPhysCpuPage= 0;
4632 pCache->TestIn.pVMCSPhys = 0;
4633 pCache->TestIn.pCache = 0;
4634 pCache->TestOut.pVMCSPhys = 0;
4635 pCache->TestOut.pCache = 0;
4636 pCache->TestOut.pCtx = 0;
4637 pCache->TestOut.eflags = 0;
4638#endif
4639
4640 aParam[0] = (uint32_t)(HCPhysCpuPage); /* Param 1: VMXON physical address - Lo. */
4641 aParam[1] = (uint32_t)(HCPhysCpuPage >> 32); /* Param 1: VMXON physical address - Hi. */
4642 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
4643 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
4644 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
4645 aParam[5] = 0;
4646
4647#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4648 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
4649 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
4650#endif
4651 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
4652
4653#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4654 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
4655 Assert(pCtx->dr[4] == 10);
4656 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
4657#endif
4658
4659#ifdef DEBUG
4660 AssertMsg(pCache->TestIn.HCPhysCpuPage== HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage));
4661 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
4662 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
4663 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
4664 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
4665 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
4666 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
4667#endif
4668 return rc;
4669}
4670
4671/**
4672 * Executes the specified handler in 64 mode
4673 *
4674 * @returns VBox status code.
4675 * @param pVM The VM to operate on.
4676 * @param pVCpu The VMCPU to operate on.
4677 * @param pCtx Guest context
4678 * @param pfnHandler RC handler
4679 * @param cbParam Number of parameters
4680 * @param paParam Array of 32 bits parameters
4681 */
4682VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
4683{
4684 int rc, rc2;
4685 PHWACCM_CPUINFO pCpu;
4686 RTHCPHYS HCPhysCpuPage;
4687 RTHCUINTREG uOldEFlags;
4688
4689 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
4690 Assert(pfnHandler);
4691 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
4692 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
4693
4694#ifdef VBOX_STRICT
4695 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
4696 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
4697
4698 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
4699 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
4700#endif
4701
4702 /* Disable interrupts. */
4703 uOldEFlags = ASMIntDisableFlags();
4704
4705 pCpu = HWACCMR0GetCurrentCpu();
4706 HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
4707
4708 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
4709 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4710
4711 /* Leave VMX Root Mode. */
4712 VMXDisable();
4713
4714 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4715
4716 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
4717 CPUMSetHyperEIP(pVCpu, pfnHandler);
4718 for (int i=(int)cbParam-1;i>=0;i--)
4719 CPUMPushHyper(pVCpu, paParam[i]);
4720
4721 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4722 /* Call switcher. */
4723 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
4724 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4725
4726 /* Make sure the VMX instructions don't cause #UD faults. */
4727 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
4728
4729 /* Enter VMX Root Mode */
4730 rc2 = VMXEnable(HCPhysCpuPage);
4731 if (RT_FAILURE(rc2))
4732 {
4733 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4734 ASMSetFlags(uOldEFlags);
4735 return VERR_VMX_VMXON_FAILED;
4736 }
4737
4738 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4739 AssertRC(rc2);
4740 Assert(!(ASMGetFlags() & X86_EFL_IF));
4741 ASMSetFlags(uOldEFlags);
4742 return rc;
4743}
4744
4745#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
4746
4747
4748#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4749/**
4750 * Executes VMWRITE
4751 *
4752 * @returns VBox status code
4753 * @param pVCpu The VMCPU to operate on.
4754 * @param idxField VMCS index
4755 * @param u64Val 16, 32 or 64 bits value
4756 */
4757VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4758{
4759 int rc;
4760
4761 switch (idxField)
4762 {
4763 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
4764 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
4765 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
4766 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
4767 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
4768 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
4769 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
4770 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
4771 case VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL:
4772 case VMX_VMCS_GUEST_LINK_PTR_FULL:
4773 case VMX_VMCS_GUEST_PDPTR0_FULL:
4774 case VMX_VMCS_GUEST_PDPTR1_FULL:
4775 case VMX_VMCS_GUEST_PDPTR2_FULL:
4776 case VMX_VMCS_GUEST_PDPTR3_FULL:
4777 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
4778 case VMX_VMCS_GUEST_EFER_FULL:
4779 case VMX_VMCS_CTRL_EPTP_FULL:
4780 /* These fields consist of two parts, which are both writable in 32 bits mode. */
4781 rc = VMXWriteVMCS32(idxField, u64Val);
4782 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
4783 AssertRC(rc);
4784 return rc;
4785
4786 case VMX_VMCS64_GUEST_LDTR_BASE:
4787 case VMX_VMCS64_GUEST_TR_BASE:
4788 case VMX_VMCS64_GUEST_GDTR_BASE:
4789 case VMX_VMCS64_GUEST_IDTR_BASE:
4790 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4791 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4792 case VMX_VMCS64_GUEST_CR0:
4793 case VMX_VMCS64_GUEST_CR4:
4794 case VMX_VMCS64_GUEST_CR3:
4795 case VMX_VMCS64_GUEST_DR7:
4796 case VMX_VMCS64_GUEST_RIP:
4797 case VMX_VMCS64_GUEST_RSP:
4798 case VMX_VMCS64_GUEST_CS_BASE:
4799 case VMX_VMCS64_GUEST_DS_BASE:
4800 case VMX_VMCS64_GUEST_ES_BASE:
4801 case VMX_VMCS64_GUEST_FS_BASE:
4802 case VMX_VMCS64_GUEST_GS_BASE:
4803 case VMX_VMCS64_GUEST_SS_BASE:
4804 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
4805 if (u64Val >> 32ULL)
4806 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
4807 else
4808 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
4809
4810 return rc;
4811
4812 default:
4813 AssertMsgFailed(("Unexpected field %x\n", idxField));
4814 return VERR_INVALID_PARAMETER;
4815 }
4816}
4817
4818/**
4819 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
4820 *
4821 * @param pVCpu The VMCPU to operate on.
4822 * @param idxField VMCS field
4823 * @param u64Val Value
4824 */
4825VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4826{
4827 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
4828
4829 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
4830
4831 /* Make sure there are no duplicates. */
4832 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
4833 {
4834 if (pCache->Write.aField[i] == idxField)
4835 {
4836 pCache->Write.aFieldVal[i] = u64Val;
4837 return VINF_SUCCESS;
4838 }
4839 }
4840
4841 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
4842 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
4843 pCache->Write.cValidEntries++;
4844 return VINF_SUCCESS;
4845}
4846
4847#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
4848
4849#ifdef VBOX_STRICT
4850static bool vmxR0IsValidReadField(uint32_t idxField)
4851{
4852 switch(idxField)
4853 {
4854 case VMX_VMCS64_GUEST_RIP:
4855 case VMX_VMCS64_GUEST_RSP:
4856 case VMX_VMCS_GUEST_RFLAGS:
4857 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
4858 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
4859 case VMX_VMCS64_GUEST_CR0:
4860 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
4861 case VMX_VMCS64_GUEST_CR4:
4862 case VMX_VMCS64_GUEST_DR7:
4863 case VMX_VMCS32_GUEST_SYSENTER_CS:
4864 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4865 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4866 case VMX_VMCS32_GUEST_GDTR_LIMIT:
4867 case VMX_VMCS64_GUEST_GDTR_BASE:
4868 case VMX_VMCS32_GUEST_IDTR_LIMIT:
4869 case VMX_VMCS64_GUEST_IDTR_BASE:
4870 case VMX_VMCS16_GUEST_FIELD_CS:
4871 case VMX_VMCS32_GUEST_CS_LIMIT:
4872 case VMX_VMCS64_GUEST_CS_BASE:
4873 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
4874 case VMX_VMCS16_GUEST_FIELD_DS:
4875 case VMX_VMCS32_GUEST_DS_LIMIT:
4876 case VMX_VMCS64_GUEST_DS_BASE:
4877 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
4878 case VMX_VMCS16_GUEST_FIELD_ES:
4879 case VMX_VMCS32_GUEST_ES_LIMIT:
4880 case VMX_VMCS64_GUEST_ES_BASE:
4881 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
4882 case VMX_VMCS16_GUEST_FIELD_FS:
4883 case VMX_VMCS32_GUEST_FS_LIMIT:
4884 case VMX_VMCS64_GUEST_FS_BASE:
4885 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
4886 case VMX_VMCS16_GUEST_FIELD_GS:
4887 case VMX_VMCS32_GUEST_GS_LIMIT:
4888 case VMX_VMCS64_GUEST_GS_BASE:
4889 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
4890 case VMX_VMCS16_GUEST_FIELD_SS:
4891 case VMX_VMCS32_GUEST_SS_LIMIT:
4892 case VMX_VMCS64_GUEST_SS_BASE:
4893 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
4894 case VMX_VMCS16_GUEST_FIELD_LDTR:
4895 case VMX_VMCS32_GUEST_LDTR_LIMIT:
4896 case VMX_VMCS64_GUEST_LDTR_BASE:
4897 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
4898 case VMX_VMCS16_GUEST_FIELD_TR:
4899 case VMX_VMCS32_GUEST_TR_LIMIT:
4900 case VMX_VMCS64_GUEST_TR_BASE:
4901 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
4902 case VMX_VMCS32_RO_EXIT_REASON:
4903 case VMX_VMCS32_RO_VM_INSTR_ERROR:
4904 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
4905 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
4906 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
4907 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
4908 case VMX_VMCS_RO_EXIT_QUALIFICATION:
4909 case VMX_VMCS32_RO_IDT_INFO:
4910 case VMX_VMCS32_RO_IDT_ERRCODE:
4911 case VMX_VMCS64_GUEST_CR3:
4912 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
4913 return true;
4914 }
4915 return false;
4916}
4917
4918static bool vmxR0IsValidWriteField(uint32_t idxField)
4919{
4920 switch(idxField)
4921 {
4922 case VMX_VMCS64_GUEST_LDTR_BASE:
4923 case VMX_VMCS64_GUEST_TR_BASE:
4924 case VMX_VMCS64_GUEST_GDTR_BASE:
4925 case VMX_VMCS64_GUEST_IDTR_BASE:
4926 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4927 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4928 case VMX_VMCS64_GUEST_CR0:
4929 case VMX_VMCS64_GUEST_CR4:
4930 case VMX_VMCS64_GUEST_CR3:
4931 case VMX_VMCS64_GUEST_DR7:
4932 case VMX_VMCS64_GUEST_RIP:
4933 case VMX_VMCS64_GUEST_RSP:
4934 case VMX_VMCS64_GUEST_CS_BASE:
4935 case VMX_VMCS64_GUEST_DS_BASE:
4936 case VMX_VMCS64_GUEST_ES_BASE:
4937 case VMX_VMCS64_GUEST_FS_BASE:
4938 case VMX_VMCS64_GUEST_GS_BASE:
4939 case VMX_VMCS64_GUEST_SS_BASE:
4940 return true;
4941 }
4942 return false;
4943}
4944
4945#endif
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