Changeset 37319 in vbox

Timestamp:

Jun 3, 2011 1:12:37 PM (14 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

72074

Message:

HWACCM: Use RTOnce to serialize the enabling so that no CPU can start execute code before it has been fully enabled to do so...

Location:

trunk

Files:

• include/VBox/vmm/hwaccm.h (modified) (1 diff)
• src/VBox/VMM/VMMR0/HWACCMR0.cpp (modified) (47 diffs)
• src/VBox/VMM/VMMR0/HWSVMR0.cpp (modified) (5 diffs)
• src/VBox/VMM/VMMR0/HWSVMR0.h (modified) (1 diff)
• src/VBox/VMM/VMMR0/HWVMXR0.cpp (modified) (13 diffs)
• src/VBox/VMM/include/HWACCMInternal.h (modified) (2 diffs)

trunk/include/VBox/vmm/hwaccm.h

@@ -35 +35 @@
  * @{
  */
-
-/**
- * HWACCM state
- */
-typedef enum HWACCMSTATE
-{
-    /* Not yet set */
-    HWACCMSTATE_UNINITIALIZED = 0,
-    /* Enabled */
-    HWACCMSTATE_ENABLED,
-    /* Disabled */
-    HWACCMSTATE_DISABLED,
-    /** The usual 32-bit hack. */
-    HWACCMSTATE_32BIT_HACK = 0x7fffffff
-} HWACCMSTATE;
 
 RT_C_DECLS_BEGIN

trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp

@@ -5 +5 @@
 
 /*
- * Copyright (C) 2006-2007 Oracle Corporation
+ * Copyright (C) 2006-2011 Oracle Corporation
  *
  * This file is part of VirtualBox Open Source Edition (OSE), as
@@ -36 +36 @@
 #include <iprt/mem.h>
 #include <iprt/memobj.h>
+#include <iprt/once.h>
 #include <iprt/param.h>
 #include <iprt/power.h>
@@ -42 +43 @@
 #include "HWVMXR0.h"
 #include "HWSVMR0.h"
+
 
 /*******************************************************************************
@@ -53 +55 @@
 static DECLCALLBACK(void) hwaccmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
 
+
 /*******************************************************************************
 *   Global Variables                                                           *
@@ -67 +70 @@
     DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
     DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
-    DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
-    DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
+    DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
+    DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
     DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
     DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
@@ -114 +117 @@
         uint32_t                    ulLastInstrError;
     } vmx;
+
     struct
     {
@@ -137 +141 @@
     } cpuid;
 
-    HWACCMSTATE                     enmHwAccmState;
-
+    /** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
+     * enabled and disabled each time it's used to execute guest code. */
     bool                            fGlobalInit;
+    /** Indicates whether the host is suspending or not.  We'll refuse a few
+     *  actions when the host is being suspended to speed up the suspending and
+     *  avoid trouble. */
     volatile        bool            fSuspended;
+
+    /** Whether we've already initialized all CPUs.
+     * @remarks We could check the EnableAllCpusOnce state, but this is
+     *          simpler and hopefully easier to understand. */
+    bool                            fEnabled;
+    /** Serialize initialization in HWACCMR0EnableAllCpus. */
+    RTONCE                          EnableAllCpusOnce;
 } HWACCMR0Globals;
 
@@ -222 +236 @@
 }
 
-static DECLCALLBACK(int) hwaccmR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
+static DECLCALLBACK(int) hwaccmR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
 {
     return VINF_SUCCESS;
 }
 
-static DECLCALLBACK(int) hwaccmR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
+static DECLCALLBACK(int) hwaccmR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
 {
     return VINF_SUCCESS;
@@ -267 +281 @@
 
 /**
- * Does global Ring-0 HWACCM initialization.
+ * Does global Ring-0 HWACCM initialization (at module init).
  *
  * @returns VBox status code.
@@ -273 +287 @@
 VMMR0DECL(int) HWACCMR0Init(void)
 {
-    int     rc;
-    bool    fAMDVPresent = false;
-
-    HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
+
+    /*
+     * Initialize the globals.
+     */
+    HWACCMR0Globals.fEnabled = false;
+    static RTONCE s_OnceInit = RTONCE_INITIALIZER;
+    HWACCMR0Globals.EnableAllCpusOnce = s_OnceInit;
     for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
-        HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
+        HWACCMR0Globals.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
 
     /* Fill in all callbacks with placeholders. */
@@ -307 +324 @@
      * Check for VT-x and AMD-V capabilities
      */
+    int rc;
     if (ASMHasCpuId())
     {
-        uint32_t u32FeaturesECX;
+        uint32_t u32FeaturesECX, u32FeaturesEDX;
+        uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
         uint32_t u32Dummy;
-        uint32_t u32FeaturesEDX;
-        uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
-
+
+        /* STandard features. */
         ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
         ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
+
         /* Query AMD features. */
-        ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
-
-        if (    u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
-            &&  u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
-            &&  u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
+        ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX,
+                 &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
+
+        /*
+         * Intel CPU?
+         */
+        if (   u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
+            && u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
+            && u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
            )
         {
@@ -333 +356 @@
                )
             {
+                /** @todo move this into a separate function. */
                 HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
 
@@ -400 +424 @@
                             HWACCMR0Globals.vmx.hostEFER            = ASMRdMsr(MSR_K6_EFER);
 
-                            rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
+                            rc = RTR0MemObjAllocCont(&pScatchMemObj, PAGE_SIZE, true /* executable R0 mapping */);
                             if (RT_FAILURE(rc))
                                 return rc;
@@ -470 +494 @@
                         HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
                     }
+
+                    if (HWACCMR0Globals.vmx.fSupported)
+                    {
+                        HWACCMR0Globals.pfnEnterSession     = VMXR0Enter;
+                        HWACCMR0Globals.pfnLeaveSession     = VMXR0Leave;
+                        HWACCMR0Globals.pfnSaveHostState    = VMXR0SaveHostState;
+                        HWACCMR0Globals.pfnLoadGuestState   = VMXR0LoadGuestState;
+                        HWACCMR0Globals.pfnRunGuestCode     = VMXR0RunGuestCode;
+                        HWACCMR0Globals.pfnEnableCpu        = VMXR0EnableCpu;
+                        HWACCMR0Globals.pfnDisableCpu       = VMXR0DisableCpu;
+                        HWACCMR0Globals.pfnInitVM           = VMXR0InitVM;
+                        HWACCMR0Globals.pfnTermVM           = VMXR0TermVM;
+                        HWACCMR0Globals.pfnSetupVM          = VMXR0SetupVM;
+                    }
                 }
 #ifdef LOG_ENABLED
@@ -479 +517 @@
                 HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
         }
-        else
-        if (    u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
-            &&  u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
-            &&  u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
-           )
+        /*
+         * AMD CPU?
+         */
+        else if (   u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
+                 && u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
+                 && u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
+                )
         {
+            /** @todo move this into a separate function. */
+
             /*
              * Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
@@ -494 +536 @@
                )
             {
-                fAMDVPresent = true;
+                HWACCMR0Globals.pfnEnterSession     = SVMR0Enter;
+                HWACCMR0Globals.pfnLeaveSession     = SVMR0Leave;
+                HWACCMR0Globals.pfnSaveHostState    = SVMR0SaveHostState;
+                HWACCMR0Globals.pfnLoadGuestState   = SVMR0LoadGuestState;
+                HWACCMR0Globals.pfnRunGuestCode     = SVMR0RunGuestCode;
+                HWACCMR0Globals.pfnEnableCpu        = SVMR0EnableCpu;
+                HWACCMR0Globals.pfnDisableCpu       = SVMR0DisableCpu;
+                HWACCMR0Globals.pfnInitVM           = SVMR0InitVM;
+                HWACCMR0Globals.pfnTermVM           = SVMR0TermVM;
+                HWACCMR0Globals.pfnSetupVM          = SVMR0SetupVM;
 
                 /* Query AMD features. */
-                ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
+                ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID,
+                         &u32Dummy, &HWACCMR0Globals.svm.u32Features);
 
                 /* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
@@ -506 +558 @@
                     rc = hwaccmR0FirstRcGetStatus(&FirstRc);
 #ifndef DEBUG_bird
-                AssertMsg(rc == VINF_SUCCESS || rc == VERR_SVM_IN_USE, ("hwaccmR0InitCpu failed for cpu %d with rc=%d\n", hwaccmR0FirstRcGetCpuId(&FirstRc), rc));
+                AssertMsg(rc == VINF_SUCCESS || rc == VERR_SVM_IN_USE,
+                          ("hwaccmR0InitCpu failed for cpu %d with rc=%d\n", hwaccmR0FirstRcGetCpuId(&FirstRc), rc));
 #endif
                 if (RT_SUCCESS(rc))
@@ -520 +573 @@
                 HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
         }
+        /*
+         * Unknown CPU.
+         */
         else
             HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
@@ -526 +582 @@
         HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
 
-    if (HWACCMR0Globals.vmx.fSupported)
-    {
-        HWACCMR0Globals.pfnEnterSession     = VMXR0Enter;
-        HWACCMR0Globals.pfnLeaveSession     = VMXR0Leave;
-        HWACCMR0Globals.pfnSaveHostState    = VMXR0SaveHostState;
-        HWACCMR0Globals.pfnLoadGuestState   = VMXR0LoadGuestState;
-        HWACCMR0Globals.pfnRunGuestCode     = VMXR0RunGuestCode;
-        HWACCMR0Globals.pfnEnableCpu        = VMXR0EnableCpu;
-        HWACCMR0Globals.pfnDisableCpu       = VMXR0DisableCpu;
-        HWACCMR0Globals.pfnInitVM           = VMXR0InitVM;
-        HWACCMR0Globals.pfnTermVM           = VMXR0TermVM;
-        HWACCMR0Globals.pfnSetupVM          = VMXR0SetupVM;
-    }
-    else
-    if (fAMDVPresent)
-    {
-        HWACCMR0Globals.pfnEnterSession     = SVMR0Enter;
-        HWACCMR0Globals.pfnLeaveSession     = SVMR0Leave;
-        HWACCMR0Globals.pfnSaveHostState    = SVMR0SaveHostState;
-        HWACCMR0Globals.pfnLoadGuestState   = SVMR0LoadGuestState;
-        HWACCMR0Globals.pfnRunGuestCode     = SVMR0RunGuestCode;
-        HWACCMR0Globals.pfnEnableCpu        = SVMR0EnableCpu;
-        HWACCMR0Globals.pfnDisableCpu       = SVMR0DisableCpu;
-        HWACCMR0Globals.pfnInitVM           = SVMR0InitVM;
-        HWACCMR0Globals.pfnTermVM           = SVMR0TermVM;
-        HWACCMR0Globals.pfnSetupVM          = SVMR0SetupVM;
-    }
-
+    /*
+     * Register notification callbacks that we can use to disable/enable CPUs
+     * when brought offline/online or suspending/resuming.
+     */
     if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
     {
@@ -563 +595 @@
     }
 
+    /* We return success here because module init shall not fail if HWACCM
+       fails to initialize. */
     return VINF_SUCCESS;
 }
@@ -623 +657 @@
         && HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
     {
+        /*
+         * Simple if the host OS manages VT-x.
+         */
         Assert(HWACCMR0Globals.fGlobalInit);
         rc = SUPR0EnableVTx(false /* fEnable */);
+
         for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
         {
             HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = false;
-            Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
+            Assert(HWACCMR0Globals.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
         }
     }
@@ -660 +698 @@
         for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
         {
-            if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
+            if (HWACCMR0Globals.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
             {
-                RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
-                HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
+                RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].hMemObj, false);
+                HWACCMR0Globals.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
             }
         }
@@ -671 +709 @@
 
 
-/**
- * Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
- * is to be called on the target cpus.
+
+/**
+ * Worker function used by hwaccmR0PowerCallback  and HWACCMR0Init to initalize
+ * VT-x / AMD-V on a CPU.
  *
  * @param   idCpu       The identifier for the CPU the function is called on.
- * @param   pvUser1     The 1st user argument.
- * @param   pvUser2     The 2nd user argument.
+ * @param   pvUser1     The EBX value of CPUID(0).
+ * @param   pvUser2     Pointer to the first RC structure.
  */
 static DECLCALLBACK(void) hwaccmR0InitCpu(RTCPUID idCpu, void *pvUser1, void *pvUser2)
@@ -696 +735 @@
          * Once the lock bit is set, this MSR can no longer be modified.
          */
-        if (    !(val & (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK))
-            ||  ((val & (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK)) == MSR_IA32_FEATURE_CONTROL_VMXON) /* Some BIOSes forget to set the locked bit. */
+        if (   !(val    & (MSR_IA32_FEATURE_CONTROL_VMXON | MSR_IA32_FEATURE_CONTROL_LOCK))
+            || (   (val & (MSR_IA32_FEATURE_CONTROL_VMXON | MSR_IA32_FEATURE_CONTROL_LOCK))
+                == MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
            )
         {
@@ -704 +744 @@
             val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
         }
-        if (   (val & (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK))
-                   == (MSR_IA32_FEATURE_CONTROL_VMXON|MSR_IA32_FEATURE_CONTROL_LOCK))
+        if (   (val & (MSR_IA32_FEATURE_CONTROL_VMXON | MSR_IA32_FEATURE_CONTROL_LOCK))
+            == (MSR_IA32_FEATURE_CONTROL_VMXON | MSR_IA32_FEATURE_CONTROL_LOCK))
             rc = VINF_SUCCESS;
         else
@@ -750 +790 @@
 
 /**
- * Sets up HWACCM on all cpus.
- *
- * @returns VBox status code.
- * @param   pVM                 The VM to operate on.
- *
- */
-VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
-{
-    AssertCompile(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
-
-    /* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
-    if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
-        return VERR_HWACCM_SUSPEND_PENDING;
-
-/** @todo r=bird: Here be dragons and they are racing one another...
- *  The problem is that allocating memory for the 128 CPUs might take longer
- *  than for the 2nd and 3rd cpu to get into the HWACCMR0SetupVM code. So, they
- *  may end up there without having enabled VT-x and #UD on a VMCLEAN for
- *  instance.   Or that's what it looks like at least. */
-    if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, HWACCMSTATE_ENABLED, HWACCMSTATE_UNINITIALIZED))
-    {
-        int rc;
-
-        HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
-
-        if (   HWACCMR0Globals.vmx.fSupported
-            && HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
-        {
-            rc = SUPR0EnableVTx(true /* fEnable */);
-            if (RT_SUCCESS(rc))
-            {
-                for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
-                {
-                    HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
-                    Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
-                }
-                /* If the host provides a VT-x init API, then we'll rely on that for global init. */
-                HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
-            }
-            else
-                AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
-        }
-        else
-        {
-            /* Allocate one page per cpu for the global vt-x and amd-v pages */
-            for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
-            {
-                Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
-
-                if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
-                {
-                    rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
-                    AssertRC(rc);
-                    if (RT_FAILURE(rc))
-                        return rc;
-
-                    void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
-                    Assert(pvR0);
-                    ASMMemZeroPage(pvR0);
-
-#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
-                    SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
-#endif
-                }
-                HWACCMR0Globals.aCpuInfo[i].fConfigured = false;
-            }
-            if (HWACCMR0Globals.fGlobalInit)
-            {
-                /* First time, so initialize each cpu/core */
-                HWACCMR0FIRSTRC FirstRc;
-                hwaccmR0FirstRcInit(&FirstRc);
-                rc = RTMpOnAll(hwaccmR0EnableCpuCallback, (void *)pVM, &FirstRc);
-                if (RT_SUCCESS(rc))
-                    rc = hwaccmR0FirstRcGetStatus(&FirstRc);
-                AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", hwaccmR0FirstRcGetCpuId(&FirstRc), rc));
-            }
-            else
-                rc = VINF_SUCCESS;
-        }
-
-        return rc;
-    }
-    return VINF_SUCCESS;
-}
-
-/**
  * Disable VT-x or AMD-V on the current CPU
  *
@@ -844 +798 @@
 static int hwaccmR0EnableCpu(PVM pVM, RTCPUID idCpu)
 {
-    void           *pvPageCpu;
-    RTHCPHYS        pPageCpuPhys;
     PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
 
@@ -854 +806 @@
     Assert(!HWACCMR0Globals.fGlobalInit || ASMAtomicReadBool(&pCpu->fInUse) == false);
 
-    pCpu->idCpu     = idCpu;
+    pCpu->idCpu         = idCpu;
 
     /* Make sure we start with a clean TLB. */
-    pCpu->fFlushTLB = true;
-
-    pCpu->uCurrentASID = 0;   /* we'll aways increment this the first time (host uses ASID 0) */
-    pCpu->cTLBFlushes  = 0;
+    pCpu->fFlushTLB     = true;
+
+    pCpu->uCurrentASID  = 0;    /* we'll aways increment this the first time (host uses ASID 0) */
+    pCpu->cTLBFlushes   = 0;
 
     /* Should never happen */
-    if (!pCpu->pMemObj)
+    if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
     {
         AssertLogRelMsgFailed(("hwaccmR0EnableCpu failed idCpu=%u.\n", idCpu));
@@ -869 +821 @@
     }
 
-    pvPageCpu    = RTR0MemObjAddress(pCpu->pMemObj);
-    pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
-
-    int rc  = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
+    void    *pvCpuPage     = RTR0MemObjAddress(pCpu->hMemObj);
+    RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
+
+    int rc = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage);
     AssertRC(rc);
     if (RT_SUCCESS(rc))
@@ -899 +851 @@
 
 /**
+ * RTOnce callback employed by HWACCMR0EnableAllCpus.
+ *
+ * @returns VBox status code
+ * @param   pvUser          The VM handle.
+ * @param   pvUserIgnore    NULL, ignored.
+ */
+static DECLCALLBACK(int32_t) hwaccmR0EnableAllCpuOnce(void *pvUser, void *pvUserIgnore)
+{
+    PVM pVM = (PVM)pvUser;
+    NOREF(pvUserIgnore);
+
+    /*
+     * Indicate that we've initialized.
+     *
+     * Note! There is a potential race between this function and the suspend
+     *       notification.  Kind of unlikely though, so ignored for now.
+     */
+    AssertReturn(!HWACCMR0Globals.fEnabled, VERR_INTERNAL_ERROR_3);
+    ASMAtomicWriteBool(&HWACCMR0Globals.fEnabled, true);
+
+    /*
+     * The global init variable is set by the first VM.
+     */
+    HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
+
+    int rc;
+    if (   HWACCMR0Globals.vmx.fSupported
+        && HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
+    {
+        /*
+         * Global VT-x initialization API (only darwin for now).
+         */
+        rc = SUPR0EnableVTx(true /* fEnable */);
+        if (RT_SUCCESS(rc))
+        {
+            for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
+            {
+                HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
+                Assert(HWACCMR0Globals.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
+            }
+
+            /* If the host provides a VT-x init API, then we'll rely on that for global init. */
+            HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
+        }
+        else
+            AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
+    }
+    else
+    {
+        /*
+         * We're doing the job ourselves.
+         */
+        /* Allocate one page per cpu for the global vt-x and amd-v pages */
+        for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
+        {
+            Assert(HWACCMR0Globals.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
+
+            if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
+            {
+                rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
+                AssertLogRelRCReturn(rc, rc);
+
+                void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].hMemObj); Assert(pvR0);
+                ASMMemZeroPage(pvR0);
+            }
+            HWACCMR0Globals.aCpuInfo[i].fConfigured = false;
+        }
+
+        if (HWACCMR0Globals.fGlobalInit)
+        {
+            /* First time, so initialize each cpu/core. */
+            HWACCMR0FIRSTRC FirstRc;
+            hwaccmR0FirstRcInit(&FirstRc);
+            rc = RTMpOnAll(hwaccmR0EnableCpuCallback, (void *)pVM, &FirstRc);
+            if (RT_SUCCESS(rc))
+                rc = hwaccmR0FirstRcGetStatus(&FirstRc);
+            AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", hwaccmR0FirstRcGetCpuId(&FirstRc), rc));
+        }
+        else
+            rc = VINF_SUCCESS;
+    }
+
+    return rc;
+}
+
+
+/**
+ * Sets up HWACCM on all cpus.
+ *
+ * @returns VBox status code.
+ * @param   pVM                 The VM handle.
+ */
+VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
+{
+    /* Make sure we don't touch hwaccm after we've disabled hwaccm in
+       preparation of a suspend. */
+    if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
+        return VERR_HWACCM_SUSPEND_PENDING;
+
+    return RTOnce(&HWACCMR0Globals.EnableAllCpusOnce, hwaccmR0EnableAllCpuOnce, pVM, NULL);
+}
+
+
+/**
  * Disable VT-x or AMD-V on the current CPU
  *
@@ -906 +962 @@
 static int hwaccmR0DisableCpu(RTCPUID idCpu)
 {
-    void           *pvPageCpu;
-    RTHCPHYS        pPageCpuPhys;
-    int             rc;
     PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
 
@@ -915 +968 @@
     Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
     Assert(!HWACCMR0Globals.fGlobalInit || ASMAtomicReadBool(&pCpu->fInUse) == false);
-    Assert(!pCpu->fConfigured || pCpu->pMemObj);
-
-    if (!pCpu->pMemObj)
-        return (pCpu->fConfigured) ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
-
-    pvPageCpu    = RTR0MemObjAddress(pCpu->pMemObj);
-    pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
-
+    Assert(!pCpu->fConfigured || pCpu->hMemObj != NIL_RTR0MEMOBJ);
+
+    if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
+        return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
+
+    int rc;
     if (pCpu->fConfigured)
     {
-        rc = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
+        void    *pvCpuPage     = RTR0MemObjAddress(pCpu->hMemObj);
+        RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
+        rc = HWACCMR0Globals.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
         AssertRC(rc);
         pCpu->fConfigured = false;
@@ -935 +988 @@
     return rc;
 }
+
 
 /**
@@ -1003 +1057 @@
         ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
 
-    if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
+    if (HWACCMR0Globals.fEnabled)
     {
         int             rc;
@@ -1041 +1095 @@
         }
     }
+
     if (enmEvent == RTPOWEREVENT_RESUME)
         ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
@@ -1057 +1112 @@
 VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
 {
-    int             rc;
-
     AssertReturn(pVM, VERR_INVALID_PARAMETER);
 
@@ -1113 +1166 @@
         PVMCPU pVCpu = &pVM->aCpus[i];
 
-        pVCpu->hwaccm.s.idEnteredCpu              = NIL_RTCPUID;
+        pVCpu->hwaccm.s.idEnteredCpu        = NIL_RTCPUID;
 
         /* Invalidate the last cpu we were running on. */
-        pVCpu->hwaccm.s.idLastCpu                 = NIL_RTCPUID;
+        pVCpu->hwaccm.s.idLastCpu           = NIL_RTCPUID;
 
         /* we'll aways increment this the first time (host uses ASID 0) */
-        pVCpu->hwaccm.s.uCurrentASID              = 0;
+        pVCpu->hwaccm.s.uCurrentASID        = 0;
     }
 
@@ -1125 +1178 @@
     PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
 
-    /* Note: Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
+    /* Note: Not correct as we can be rescheduled to a different cpu, but the
+       fInUse case is mostly for debugging. */
     ASMAtomicWriteBool(&pCpu->fInUse, true);
     ASMSetFlags(fFlags);
 
     /* Init a VT-x or AMD-V VM. */
-    rc = HWACCMR0Globals.pfnInitVM(pVM);
+    int rc = HWACCMR0Globals.pfnInitVM(pVM);
 
     ASMAtomicWriteBool(&pCpu->fInUse, false);
@@ -1302 +1356 @@
 VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
 {
-    PCPUMCTX        pCtx;
     int             rc;
     RTCPUID         idCpu = RTMpCpuId();
-    PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
-
+    PHWACCM_CPUINFO pCpu  = &HWACCMR0Globals.aCpuInfo[idCpu];
+    PCPUMCTX        pCtx  = CPUMQueryGuestCtxPtr(pVCpu);
+
+
+    /** @todo r=bird: This can't be entirely right? */
     AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
-
-    pCtx = CPUMQueryGuestCtxPtr(pVCpu);
 
     /* Note:  It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
@@ -1332 +1386 @@
     if (    pVM->hwaccm.s.fNestedPaging
         &&  CPUMIsGuestInPagedProtectedModeEx(pCtx))
-    {
         CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
-    }
 
     /* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
 #ifdef RT_STRICT
-    if (RT_UNLIKELY(    pVCpu->hwaccm.s.idEnteredCpu != idCpu
-                    &&  RT_FAILURE(rc)))
+    if (RT_UNLIKELY(   pVCpu->hwaccm.s.idEnteredCpu != idCpu
+                    && RT_FAILURE(rc)))
     {
         AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
@@ -1372 +1424 @@
 VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
 {
-    CPUMCTX *pCtx;
-    int      rc;
 #ifdef VBOX_STRICT
-    RTCPUID  idCpu = RTMpCpuId(); NOREF(idCpu);
-    PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
-#endif
-
+    PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[RTMpCpuId()];
     Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
-    Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
+    Assert(pCpu->fConfigured);
     AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
     Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
+#endif
 
 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
@@ -1388 +1436 @@
 #endif
 
-    pCtx = CPUMQueryGuestCtxPtr(pVCpu);
-
-    rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
+    int rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
 
 #ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
@@ -1398 +1444 @@
 }
 
-
 #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
+
 /**
  * Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
@@ -1476 +1522 @@
  * @returns cpu structure pointer
  */
-VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
-{
-    RTCPUID  idCpu = RTMpCpuId();
-
+VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu(void)
+{
+    RTCPUID idCpu = RTMpCpuId();
+    Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
     return &HWACCMR0Globals.aCpuInfo[idCpu];
 }
@@ -1536 +1582 @@
 }
 
-/**
- * Disable VT-x if it's active *and* the current switcher turns off paging
+
+/**
+ * Raw-mode switcher hook - disable VT-x if it's active *and* the current
+ * switcher turns off paging.
  *
  * @returns VBox status code.
  * @param   pVM             VM handle.
- * @param   pfVTxDisabled   VT-x was disabled or not (out)
+ * @param   pfVTxDisabled   VT-x was disabled or not (out).
  */
 VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
@@ -1549 +1597 @@
     *pfVTxDisabled = false;
 
-    if (    HWACCMR0Globals.enmHwAccmState != HWACCMSTATE_ENABLED
-        ||  !HWACCMR0Globals.vmx.fSupported /* no such issues with AMD-V */
-        ||  !HWACCMR0Globals.fGlobalInit    /* Local init implies the CPU is currently not in VMX root mode. */)
+    if (   !HWACCMR0Globals.fEnabled
+        || !HWACCMR0Globals.vmx.fSupported /* no such issues with AMD-V */
+        || !HWACCMR0Globals.fGlobalInit    /* Local init implies the CPU is currently not in VMX root mode. */)
         return VINF_SUCCESS;    /* nothing to do */
 
     switch(VMMGetSwitcher(pVM))
     {
-    case VMMSWITCHER_32_TO_32:
-    case VMMSWITCHER_PAE_TO_PAE:
-        return VINF_SUCCESS;    /* safe switchers as they don't turn off paging */
-
-    case VMMSWITCHER_32_TO_PAE:
-    case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
-    case VMMSWITCHER_AMD64_TO_32:
-    case VMMSWITCHER_AMD64_TO_PAE:
-        break;                  /* unsafe switchers */
-
-    default:
-        AssertFailed();
-        return VERR_INTERNAL_ERROR;
+        case VMMSWITCHER_32_TO_32:
+        case VMMSWITCHER_PAE_TO_PAE:
+            return VINF_SUCCESS;    /* safe switchers as they don't turn off paging */
+
+        case VMMSWITCHER_32_TO_PAE:
+        case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
+        case VMMSWITCHER_AMD64_TO_32:
+        case VMMSWITCHER_AMD64_TO_PAE:
+            break;                  /* unsafe switchers */
+
+        default:
+            AssertFailed();
+            return VERR_INTERNAL_ERROR;
     }
 
     PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
-    void           *pvPageCpu;
-    RTHCPHYS        pPageCpuPhys;
-
-    AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
-    pvPageCpu    = RTR0MemObjAddress(pCpu->pMemObj);
-    pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
+    AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_INTERNAL_ERROR);
 
     *pfVTxDisabled = true;
-    return VMXR0DisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
-}
-
-/**
- * Enable VT-x if was active *and* the current switcher turned off paging
+    void    *pvCpuPage     = RTR0MemObjAddress(pCpu->hMemObj);
+    RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
+    return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
+}
+
+/**
+ * Raw-mode switcher hook - re-enable VT-x if was active *and* the current
+ * switcher turned off paging.
  *
  * @returns VBox status code.
- * @param   pVM          VM handle.
- * @param   fVTxDisabled VT-x was disabled or not
+ * @param   pVM             VM handle.
+ * @param   fVTxDisabled    VT-x was disabled or not.
  */
 VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
@@ -1597 +1643 @@
         return VINF_SUCCESS;    /* nothing to do */
 
-    Assert(   HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED
-           && HWACCMR0Globals.vmx.fSupported
-           && HWACCMR0Globals.fGlobalInit);
+    Assert(HWACCMR0Globals.fEnabled);
+    Assert(HWACCMR0Globals.vmx.fSupported);
+    Assert(HWACCMR0Globals.fGlobalInit);
 
     PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
-    void           *pvPageCpu;
-    RTHCPHYS        pPageCpuPhys;
-
-    AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
-    pvPageCpu    = RTR0MemObjAddress(pCpu->pMemObj);
-    pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
-
-    return VMXR0EnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
+    AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_INTERNAL_ERROR);
+
+    void           *pvCpuPage     = RTR0MemObjAddress(pCpu->hMemObj);
+    RTHCPHYS        HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
+    return VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage);
 }
 

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -64 +64 @@
  * @param   pCpu            CPU info struct
  * @param   pVM             The VM to operate on. (can be NULL after a resume!!)
- * @param   pvPageCpu       Pointer to the global cpu page
- * @param   pPageCpuPhys    Physical address of the global cpu page
+ * @param   pvCpuPage       Pointer to the global cpu page.
+ * @param   HCPhysCpuPage   Physical address of the global cpu page.
  */
-VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
+VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
 {
-    AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
-    AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
-
-    /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
-    uint64_t val = ASMRdMsr(MSR_K6_EFER);
-    if (val & MSR_K6_EFER_SVME)
-    {
-        /* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active, then we blindly use AMD-V. */
+    AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
+    AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
+
+    /* We must turn on AMD-V and setup the host state physical address, as
+       those MSRs are per-cpu/core. */
+    uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
+    if (fEfer & MSR_K6_EFER_SVME)
+    {
+        /* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active, then we
+           blindly use AMD-V. */
         if (    pVM
             &&  pVM->hwaccm.s.svm.fIgnoreInUseError)
-        {
             pCpu->fIgnoreAMDVInUseError = true;
-        }
-
         if (!pCpu->fIgnoreAMDVInUseError)
             return VERR_SVM_IN_USE;
@@ -88 +87 @@
 
     /* Turn on AMD-V in the EFER MSR. */
-    ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
-
-    /* Write the physical page address where the CPU will store the host state while executing the VM. */
-    ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
+    ASMWrMsr(MSR_K6_EFER, fEfer | MSR_K6_EFER_SVME);
+
+    /* Write the physical page address where the CPU will store the host state
+       while executing the VM. */
+    ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
 
     return VINF_SUCCESS;
@@ -101 +101 @@
  * @returns VBox status code.
  * @param   pCpu            CPU info struct
- * @param   pvPageCpu       Pointer to the global cpu page
- * @param   pPageCpuPhys    Physical address of the global cpu page
+ * @param   pvCpuPage       Pointer to the global cpu page.
+ * @param   HCPhysCpuPage   Physical address of the global cpu page.
  */
-VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
+VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
 {
-    AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
-    AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
+    AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
+    AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
 
     /* Turn off AMD-V in the EFER MSR. */
-    uint64_t val = ASMRdMsr(MSR_K6_EFER);
-    ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
+    uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
+    ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
 
     /* Invalidate host state physical address. */
@@ -1215 +1215 @@
     pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
 
-    /** Set TLB flush state as checked until we return from the world switch. */
+    /* Set TLB flush state as checked until we return from the world switch. */
     ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, true);
 
@@ -1222 +1222 @@
         pVCpu->hwaccm.s.fForceTLBFlush = true;
 
-    /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
+    /* Make sure we flush the TLB when required.  Switch ASID to achieve the
+       same thing, but without actually flushing the whole TLB (which is
+       expensive). */
     if (    pVCpu->hwaccm.s.fForceTLBFlush
         && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)

trunk/src/VBox/VMM/VMMR0/HWSVMR0.h

@@ -67 +67 @@
  * @param   pPageCpuPhys    Physical address of the global cpu page
  */
-VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
+VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS HCPhysCpuPage);
 
 /**

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -101 +101 @@
  * @param   pCpu            CPU info struct
  * @param   pVM             The VM to operate on. (can be NULL after a resume!!)
- * @param   pvPageCpu       Pointer to the global cpu page
- * @param   pPageCpuPhys    Physical address of the global cpu page
+ * @param   pvCpuPage       Pointer to the global cpu page.
+ * @param   HCPhysCpuPage   Physical address of the global cpu page.
  */
-VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
+VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
 {
-    AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
-    AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
+    AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
+    AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
 
     if (pVM)
     {
         /* Set revision dword at the beginning of the VMXON structure. */
-        *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
+        *(uint32_t *)pvCpuPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
     }
 
@@ -125 +125 @@
     ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
 
-    /* Enter VMX Root Mode */
-    int rc = VMXEnable(pPageCpuPhys);
+    /* Enter VMX Root Mode. */
+    int rc = VMXEnable(HCPhysCpuPage);
     if (RT_FAILURE(rc))
     {
@@ -140 +140 @@
  * @returns VBox status code.
  * @param   pCpu            CPU info struct
- * @param   pvPageCpu       Pointer to the global cpu page
- * @param   pPageCpuPhys    Physical address of the global cpu page
+ * @param   pvCpuPage       Pointer to the global cpu page.
+ * @param   HCPhysCpuPage   Physical address of the global cpu page.
  */
-VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
+VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
 {
-    AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
-    AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
+    AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
+    AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
 
     /* If we're somehow not in VMX root mode, then we shouldn't dare leaving it. */
@@ -155 +155 @@
     VMXDisable();
 
-    /* And clear the X86_CR4_VMXE bit */
+    /* And clear the X86_CR4_VMXE bit. */
     ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
     return VINF_SUCCESS;
@@ -2259 +2259 @@
             /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
             STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
-            for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
+            for (unsigned i = 0; i < pVCpu->hwaccm.s.TlbShootdown.cPages; i++)
                 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
         }
@@ -2276 +2276 @@
         vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
 
-#ifdef VBOX_WITH_STATISTICS
+# ifdef VBOX_WITH_STATISTICS
     if (pVCpu->hwaccm.s.fForceTLBFlush)
         STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
     else
         STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
-#endif
+# endif
 }
 #endif /* HWACCM_VTX_WITH_VPID */
@@ -4616 +4616 @@
     uint32_t        aParam[6];
     PHWACCM_CPUINFO pCpu;
-    RTHCPHYS        pPageCpuPhys;
+    RTHCPHYS        HCPhysCpuPage;
     int             rc;
 
     pCpu = HWACCMR0GetCurrentCpu();
-    pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
+    HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
 
 #ifdef VBOX_WITH_CRASHDUMP_MAGIC
@@ -4629 +4629 @@
 
 #ifdef DEBUG
-    pCache->TestIn.pPageCpuPhys = 0;
+    pCache->TestIn.HCPhysCpuPage= 0;
     pCache->TestIn.pVMCSPhys    = 0;
     pCache->TestIn.pCache       = 0;
@@ -4638 +4638 @@
 #endif
 
-    aParam[0] = (uint32_t)(pPageCpuPhys);                                   /* Param 1: VMXON physical address - Lo. */
-    aParam[1] = (uint32_t)(pPageCpuPhys >> 32);                             /* Param 1: VMXON physical address - Hi. */
+    aParam[0] = (uint32_t)(HCPhysCpuPage);                                  /* Param 1: VMXON physical address - Lo. */
+    aParam[1] = (uint32_t)(HCPhysCpuPage >> 32);                            /* Param 1: VMXON physical address - Hi. */
     aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys);                  /* Param 2: VMCS physical address - Lo. */
     aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32);            /* Param 2: VMCS physical address - Hi. */
@@ -4658 +4658 @@
 
 #ifdef DEBUG
-    AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
+    AssertMsg(pCache->TestIn.HCPhysCpuPage== HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage));
     AssertMsg(pCache->TestIn.pVMCSPhys    == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
     AssertMsg(pCache->TestIn.pVMCSPhys    == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
@@ -4684 +4684 @@
     int             rc, rc2;
     PHWACCM_CPUINFO pCpu;
-    RTHCPHYS        pPageCpuPhys;
+    RTHCPHYS        HCPhysCpuPage;
     RTHCUINTREG     uOldEFlags;
 
@@ -4704 +4704 @@
 
     pCpu = HWACCMR0GetCurrentCpu();
-    pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
+    HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
 
     /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
@@ -4728 +4728 @@
 
     /* Enter VMX Root Mode */
-    rc2 = VMXEnable(pPageCpuPhys);
+    rc2 = VMXEnable(HCPhysCpuPage);
     if (RT_FAILURE(rc2))
     {

trunk/src/VBox/VMM/include/HWACCMInternal.h

@@ -154 +154 @@
 #define HWACCM_SSM_VERSION_2_0_X            3
 
-/* Per-cpu information. (host) */
+/**
+ * Global per-cpu information. (host)
+ */
 typedef struct
 {
+    /** The CPU ID. */
     RTCPUID             idCpu;
-
-    RTR0MEMOBJ          pMemObj;
+    /** The memory object   */
+    RTR0MEMOBJ          hMemObj;
     /* Current ASID (AMD-V)/VPID (Intel) */
     uint32_t            uCurrentASID;
@@ -883 +886 @@
 #ifdef IN_RING0
 
-VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
+VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu(void);
 VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);