VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 49975

Last change on this file since 49975 was 49972, checked in by vboxsync, 11 years ago

CPUM: More msr hacking.
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1/* $Id: CPUM.cpp 49972 2013-12-18 13:10:58Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/selm.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/patm.h>
48#include <VBox/vmm/hm.h>
49#include <VBox/vmm/ssm.h>
50#include "CPUMInternal.h"
51#include <VBox/vmm/vm.h>
52
53#include <VBox/param.h>
54#include <VBox/dis.h>
55#include <VBox/err.h>
56#include <VBox/log.h>
57#include <iprt/asm-amd64-x86.h>
58#include <iprt/assert.h>
59#include <iprt/cpuset.h>
60#include <iprt/mem.h>
61#include <iprt/mp.h>
62#include <iprt/string.h>
63#include "internal/pgm.h"
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The current saved state version. */
70#define CPUM_SAVED_STATE_VERSION 14
71/** The current saved state version before using SSMR3PutStruct. */
72#define CPUM_SAVED_STATE_VERSION_MEM 13
73/** The saved state version before introducing the MSR size field. */
74#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
75/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
76 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
77#define CPUM_SAVED_STATE_VERSION_VER3_2 11
78/** The saved state version of 3.0 and 3.1 trunk before the teleportation
79 * changes. */
80#define CPUM_SAVED_STATE_VERSION_VER3_0 10
81/** The saved state version for the 2.1 trunk before the MSR changes. */
82#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
83/** The saved state version of 2.0, used for backwards compatibility. */
84#define CPUM_SAVED_STATE_VERSION_VER2_0 8
85/** The saved state version of 1.6, used for backwards compatibility. */
86#define CPUM_SAVED_STATE_VERSION_VER1_6 6
87
88
89/**
90 * This was used in the saved state up to the early life of version 14.
91 *
92 * It indicates that we may have some out-of-sync hidden segement registers.
93 * It is only relevant for raw-mode.
94 */
95#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
96
97
98/*******************************************************************************
99* Structures and Typedefs *
100*******************************************************************************/
101
102/**
103 * What kind of cpu info dump to perform.
104 */
105typedef enum CPUMDUMPTYPE
106{
107 CPUMDUMPTYPE_TERSE,
108 CPUMDUMPTYPE_DEFAULT,
109 CPUMDUMPTYPE_VERBOSE
110} CPUMDUMPTYPE;
111/** Pointer to a cpu info dump type. */
112typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
113
114
115/*******************************************************************************
116* Internal Functions *
117*******************************************************************************/
118static int cpumR3CpuIdInit(PVM pVM);
119static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
120static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
121static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
122static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
123static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
124static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
129static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
130
131
132/*******************************************************************************
133* Global Variables *
134*******************************************************************************/
135/** Saved state field descriptors for CPUMCTX. */
136static const SSMFIELD g_aCpumCtxFields[] =
137{
138 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
139 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
140 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
141 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
142 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
143 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
144 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
145 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
146 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
147 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
148 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
149 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
150 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
151 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
152 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
153 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
154 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
155 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
156 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
157 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
158 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
159 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
160 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
161 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
162 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
163 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
164 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
165 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
166 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
167 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
168 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
169 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
170 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
171 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
172 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
173 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
174 SSMFIELD_ENTRY( CPUMCTX, rdi),
175 SSMFIELD_ENTRY( CPUMCTX, rsi),
176 SSMFIELD_ENTRY( CPUMCTX, rbp),
177 SSMFIELD_ENTRY( CPUMCTX, rax),
178 SSMFIELD_ENTRY( CPUMCTX, rbx),
179 SSMFIELD_ENTRY( CPUMCTX, rdx),
180 SSMFIELD_ENTRY( CPUMCTX, rcx),
181 SSMFIELD_ENTRY( CPUMCTX, rsp),
182 SSMFIELD_ENTRY( CPUMCTX, rflags),
183 SSMFIELD_ENTRY( CPUMCTX, rip),
184 SSMFIELD_ENTRY( CPUMCTX, r8),
185 SSMFIELD_ENTRY( CPUMCTX, r9),
186 SSMFIELD_ENTRY( CPUMCTX, r10),
187 SSMFIELD_ENTRY( CPUMCTX, r11),
188 SSMFIELD_ENTRY( CPUMCTX, r12),
189 SSMFIELD_ENTRY( CPUMCTX, r13),
190 SSMFIELD_ENTRY( CPUMCTX, r14),
191 SSMFIELD_ENTRY( CPUMCTX, r15),
192 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
193 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
194 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
195 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
196 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
197 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
198 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
199 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
200 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
201 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
202 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
203 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
204 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
205 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
206 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
207 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
208 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
209 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
210 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
211 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
212 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
213 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
214 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
215 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
216 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
217 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
218 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
219 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
220 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
221 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
222 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
223 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
224 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
225 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
226 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
227 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
228 SSMFIELD_ENTRY( CPUMCTX, cr0),
229 SSMFIELD_ENTRY( CPUMCTX, cr2),
230 SSMFIELD_ENTRY( CPUMCTX, cr3),
231 SSMFIELD_ENTRY( CPUMCTX, cr4),
232 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
233 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
234 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
235 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
236 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
237 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
238 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
239 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
240 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
241 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
242 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
243 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
244 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
245 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
246 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
247 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
248 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
249 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
250 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
251 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
252 /* msrApicBase is not included here, it resides in the APIC device state. */
253 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
254 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
255 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
256 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
257 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
258 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
259 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
260 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
261 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
262 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
263 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
264 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
265 SSMFIELD_ENTRY_TERM()
266};
267
268/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
269 * registeres changed. */
270static const SSMFIELD g_aCpumCtxFieldsMem[] =
271{
272 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
273 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
274 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
275 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
276 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
277 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
278 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
279 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
280 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
281 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
282 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
283 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
284 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
285 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
286 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
287 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
288 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
289 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
290 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
291 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
292 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
293 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
294 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
295 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
296 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
297 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
298 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
299 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
300 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
301 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
302 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
303 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
304 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
305 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
306 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
307 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
308 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
309 SSMFIELD_ENTRY( CPUMCTX, rdi),
310 SSMFIELD_ENTRY( CPUMCTX, rsi),
311 SSMFIELD_ENTRY( CPUMCTX, rbp),
312 SSMFIELD_ENTRY( CPUMCTX, rax),
313 SSMFIELD_ENTRY( CPUMCTX, rbx),
314 SSMFIELD_ENTRY( CPUMCTX, rdx),
315 SSMFIELD_ENTRY( CPUMCTX, rcx),
316 SSMFIELD_ENTRY( CPUMCTX, rsp),
317 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
318 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
319 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
320 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
321 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
322 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
323 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
324 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
325 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
326 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
327 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
328 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
329 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
330 SSMFIELD_ENTRY( CPUMCTX, rflags),
331 SSMFIELD_ENTRY( CPUMCTX, rip),
332 SSMFIELD_ENTRY( CPUMCTX, r8),
333 SSMFIELD_ENTRY( CPUMCTX, r9),
334 SSMFIELD_ENTRY( CPUMCTX, r10),
335 SSMFIELD_ENTRY( CPUMCTX, r11),
336 SSMFIELD_ENTRY( CPUMCTX, r12),
337 SSMFIELD_ENTRY( CPUMCTX, r13),
338 SSMFIELD_ENTRY( CPUMCTX, r14),
339 SSMFIELD_ENTRY( CPUMCTX, r15),
340 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
341 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
342 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
343 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
344 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
345 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
346 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
347 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
348 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
349 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
350 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
351 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
352 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
353 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
354 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
355 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
356 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
357 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
358 SSMFIELD_ENTRY( CPUMCTX, cr0),
359 SSMFIELD_ENTRY( CPUMCTX, cr2),
360 SSMFIELD_ENTRY( CPUMCTX, cr3),
361 SSMFIELD_ENTRY( CPUMCTX, cr4),
362 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
363 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
364 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
365 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
366 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
367 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
368 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
369 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
370 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
371 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
372 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
373 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
374 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
375 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
376 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
377 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
378 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
379 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
380 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
381 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
382 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
383 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
384 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
385 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
386 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
387 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
388 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
389 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
390 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
391 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
392 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
393 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
394 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
395 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
396 SSMFIELD_ENTRY_TERM()
397};
398
399/** Saved state field descriptors for CPUMCTX_VER1_6. */
400static const SSMFIELD g_aCpumCtxFieldsV16[] =
401{
402 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
403 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
404 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
405 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
406 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
407 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
408 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
409 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
410 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
411 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
412 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
413 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
414 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
415 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
416 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
417 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
418 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
419 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
420 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
421 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
422 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
423 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
424 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
425 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
426 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
427 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
428 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
429 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
430 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
431 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
432 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
433 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
434 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
435 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
436 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
437 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
438 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
439 SSMFIELD_ENTRY( CPUMCTX, rdi),
440 SSMFIELD_ENTRY( CPUMCTX, rsi),
441 SSMFIELD_ENTRY( CPUMCTX, rbp),
442 SSMFIELD_ENTRY( CPUMCTX, rax),
443 SSMFIELD_ENTRY( CPUMCTX, rbx),
444 SSMFIELD_ENTRY( CPUMCTX, rdx),
445 SSMFIELD_ENTRY( CPUMCTX, rcx),
446 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
447 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
448 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
449 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
450 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
451 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
452 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
453 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
454 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
455 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
456 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
457 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
458 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
459 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
460 SSMFIELD_ENTRY( CPUMCTX, rflags),
461 SSMFIELD_ENTRY( CPUMCTX, rip),
462 SSMFIELD_ENTRY( CPUMCTX, r8),
463 SSMFIELD_ENTRY( CPUMCTX, r9),
464 SSMFIELD_ENTRY( CPUMCTX, r10),
465 SSMFIELD_ENTRY( CPUMCTX, r11),
466 SSMFIELD_ENTRY( CPUMCTX, r12),
467 SSMFIELD_ENTRY( CPUMCTX, r13),
468 SSMFIELD_ENTRY( CPUMCTX, r14),
469 SSMFIELD_ENTRY( CPUMCTX, r15),
470 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
471 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
472 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
473 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
474 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
475 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
476 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
477 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
478 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
479 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
480 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
481 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
482 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
483 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
484 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
485 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
486 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
487 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
488 SSMFIELD_ENTRY( CPUMCTX, cr0),
489 SSMFIELD_ENTRY( CPUMCTX, cr2),
490 SSMFIELD_ENTRY( CPUMCTX, cr3),
491 SSMFIELD_ENTRY( CPUMCTX, cr4),
492 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
493 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
494 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
495 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
496 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
497 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
498 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
499 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
500 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
501 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
502 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
503 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
504 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
505 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
506 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
507 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
508 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
509 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
510 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
511 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
512 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
513 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
514 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
515 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
516 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
517 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
519 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
520 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
521 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
522 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
523 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
524 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
525 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
526 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
527 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
528 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
529 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
530 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
531 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
532 SSMFIELD_ENTRY_TERM()
533};
534
535
536/**
537 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
538 *
539 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error
540 * pointers (last instruction pointer, last data pointer, last opcode)
541 * except when the ES bit (Exception Summary) in x87 FSW (FPU Status
542 * Word) is set. Thus if we don't clear these registers there is
543 * potential, local FPU leakage from a process using the FPU to
544 * another.
545 *
546 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
547 *
548 * @param pVM Pointer to the VM.
549 */
550static void cpumR3CheckLeakyFpu(PVM pVM)
551{
552 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
553 uint32_t const u32Family = u32CpuVersion >> 8;
554 if ( u32Family >= 6 /* K7 and higher */
555 && ASMIsAmdCpu())
556 {
557 uint32_t cExt = ASMCpuId_EAX(0x80000000);
558 if (ASMIsValidExtRange(cExt))
559 {
560 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
561 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
562 {
563 for (VMCPUID i = 0; i < pVM->cCpus; i++)
564 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
565 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
566 }
567 }
568 }
569}
570
571
572/**
573 * Initializes the CPUM.
574 *
575 * @returns VBox status code.
576 * @param pVM Pointer to the VM.
577 */
578VMMR3DECL(int) CPUMR3Init(PVM pVM)
579{
580 LogFlow(("CPUMR3Init\n"));
581
582 /*
583 * Assert alignment, sizes and tables.
584 */
585 AssertCompileMemberAlignment(VM, cpum.s, 32);
586 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
587 AssertCompileSizeAlignment(CPUMCTX, 64);
588 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
589 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
590 AssertCompileMemberAlignment(VM, cpum, 64);
591 AssertCompileMemberAlignment(VM, aCpus, 64);
592 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
593 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
594#ifdef VBOX_STRICT
595 int rc2 = cpumR3MsrStrictInitChecks();
596 AssertRCReturn(rc2, rc2);
597#endif
598
599 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
600 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
601 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
602
603
604 /* Calculate the offset from CPUMCPU to CPUM. */
605 for (VMCPUID i = 0; i < pVM->cCpus; i++)
606 {
607 PVMCPU pVCpu = &pVM->aCpus[i];
608
609 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
610 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
611 }
612
613 /*
614 * Check that the CPU supports the minimum features we require.
615 */
616 if (!ASMHasCpuId())
617 {
618 Log(("The CPU doesn't support CPUID!\n"));
619 return VERR_UNSUPPORTED_CPU;
620 }
621 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
622 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
623
624 /* Setup the CR4 AND and OR masks used in the switcher */
625 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
626 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
627 {
628 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
629 /* No FXSAVE implies no SSE */
630 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
631 pVM->cpum.s.CR4.OrMask = 0;
632 }
633 else
634 {
635 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
636 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
637 }
638
639 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
640 {
641 Log(("The CPU doesn't support MMX!\n"));
642 return VERR_UNSUPPORTED_CPU;
643 }
644 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
645 {
646 Log(("The CPU doesn't support TSC!\n"));
647 return VERR_UNSUPPORTED_CPU;
648 }
649 /* Bogus on AMD? */
650 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
651 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
652
653 /*
654 * Gather info about the host CPU.
655 */
656 PCPUMCPUIDLEAF paLeaves;
657 uint32_t cLeaves;
658 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
659 AssertLogRelRCReturn(rc, rc);
660
661 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
662 RTMemFree(paLeaves);
663 AssertLogRelRCReturn(rc, rc);
664 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
665
666 /*
667 * Setup hypervisor startup values.
668 */
669
670 /*
671 * Register saved state data item.
672 */
673 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
674 NULL, cpumR3LiveExec, NULL,
675 NULL, cpumR3SaveExec, NULL,
676 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
677 if (RT_FAILURE(rc))
678 return rc;
679
680 /*
681 * Register info handlers and registers with the debugger facility.
682 */
683 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
684 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
685 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
686 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
687 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
688 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
689
690 rc = cpumR3DbgInit(pVM);
691 if (RT_FAILURE(rc))
692 return rc;
693
694 /*
695 * Check if we need to workaround partial/leaky FPU handling.
696 */
697 cpumR3CheckLeakyFpu(pVM);
698
699 /*
700 * Initialize the Guest CPUID state.
701 */
702 rc = cpumR3CpuIdInit(pVM);
703 if (RT_FAILURE(rc))
704 return rc;
705 CPUMR3Reset(pVM);
706 return VINF_SUCCESS;
707}
708
709
710/**
711 * Loads MSR range overrides.
712 *
713 * This must be called before the MSR ranges are moved from the normal heap to
714 * the hyper heap!
715 *
716 * @returns VBox status code (VMSetError called).
717 * @param pVM Pointer to the cross context VM structure
718 * @param pMsrNode The CFGM node with the MSR overrides.
719 */
720static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
721{
722 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
723 {
724 /*
725 * Assemble a valid MSR range.
726 */
727 CPUMMSRRANGE MsrRange;
728 MsrRange.offCpumCpu = 0;
729 MsrRange.fReserved = 0;
730
731 int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
732 if (RT_FAILURE(rc))
733 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
734
735 rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
736 if (RT_FAILURE(rc))
737 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
738 MsrRange.szName, rc);
739
740 rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
741 if (RT_FAILURE(rc))
742 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
743 MsrRange.szName, rc);
744
745 char szType[32];
746 rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
747 if (RT_FAILURE(rc))
748 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
749 MsrRange.szName, rc);
750 if (!RTStrICmp(szType, "FixedValue"))
751 {
752 MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
753 MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
754
755 rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
756 if (RT_FAILURE(rc))
757 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
758 MsrRange.szName, rc);
759
760 rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
761 if (RT_FAILURE(rc))
762 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
763 MsrRange.szName, rc);
764
765 rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
766 if (RT_FAILURE(rc))
767 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
768 MsrRange.szName, rc);
769 }
770 else
771 return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
772 "Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
773
774 /*
775 * Insert the range into the table (replaces/splits/shrinks existing
776 * MSR ranges).
777 */
778 rc = cpumR3MsrRangesInsert(&pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges, &MsrRange);
779 if (RT_FAILURE(rc))
780 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
781 }
782
783 return VINF_SUCCESS;
784}
785
786
787/**
788 * Loads CPUID leaf overrides.
789 *
790 * This must be called before the CPUID leaves are moved from the normal
791 * heap to the hyper heap!
792 *
793 * @returns VBox status code (VMSetError called).
794 * @param pVM Pointer to the cross context VM structure
795 * @param pParentNode The CFGM node with the CPUID leaves.
796 * @param pszLabel How to label the overrides we're loading.
797 */
798static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
799{
800 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
801 {
802 /*
803 * Get the leaf and subleaf numbers.
804 */
805 char szName[128];
806 int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
807 if (RT_FAILURE(rc))
808 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
809
810 /* The leaf number is either specified directly or thru the node name. */
811 uint32_t uLeaf;
812 rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
813 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
814 {
815 rc = RTStrToUInt32Full(szName, 16, &uLeaf);
816 if (rc != VINF_SUCCESS)
817 return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
818 "Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
819 }
820 else if (RT_FAILURE(rc))
821 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
822 pszLabel, szName, rc);
823
824 uint32_t uSubLeaf;
825 rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
826 if (RT_FAILURE(rc))
827 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
828 pszLabel, szName, rc);
829
830 uint32_t fSubLeafMask;
831 rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
832 if (RT_FAILURE(rc))
833 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
834 pszLabel, szName, rc);
835
836 /*
837 * Look up the specified leaf, since the output register values
838 * defaults to any existing values. This allows overriding a single
839 * register, without needing to know the other values.
840 */
841 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
842 uLeaf, uSubLeaf);
843 CPUMCPUIDLEAF Leaf;
844 if (pLeaf)
845 Leaf = *pLeaf;
846 else
847 RT_ZERO(Leaf);
848 Leaf.uLeaf = uLeaf;
849 Leaf.uSubLeaf = uSubLeaf;
850 Leaf.fSubLeafMask = fSubLeafMask;
851
852 rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
853 if (RT_FAILURE(rc))
854 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
855 pszLabel, szName, rc);
856 rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
857 if (RT_FAILURE(rc))
858 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
859 pszLabel, szName, rc);
860 rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
861 if (RT_FAILURE(rc))
862 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
863 pszLabel, szName, rc);
864 rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
865 if (RT_FAILURE(rc))
866 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
867 pszLabel, szName, rc);
868
869 /*
870 * Insert the leaf into the table (replaces existing ones).
871 */
872 rc = cpumR3CpuIdInsert(&pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves, &Leaf);
873 if (RT_FAILURE(rc))
874 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
875 }
876
877 return VINF_SUCCESS;
878}
879
880
881
882/**
883 * Fetches overrides for a CPUID leaf.
884 *
885 * @returns VBox status code.
886 * @param pLeaf The leaf to load the overrides into.
887 * @param pCfgNode The CFGM node containing the overrides
888 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
889 * @param iLeaf The CPUID leaf number.
890 */
891static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
892{
893 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
894 if (pLeafNode)
895 {
896 uint32_t u32;
897 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
898 if (RT_SUCCESS(rc))
899 pLeaf->eax = u32;
900 else
901 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
902
903 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
904 if (RT_SUCCESS(rc))
905 pLeaf->ebx = u32;
906 else
907 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
908
909 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
910 if (RT_SUCCESS(rc))
911 pLeaf->ecx = u32;
912 else
913 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
914
915 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
916 if (RT_SUCCESS(rc))
917 pLeaf->edx = u32;
918 else
919 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
920
921 }
922 return VINF_SUCCESS;
923}
924
925
926/**
927 * Load the overrides for a set of CPUID leaves.
928 *
929 * @returns VBox status code.
930 * @param paLeaves The leaf array.
931 * @param cLeaves The number of leaves.
932 * @param uStart The start leaf number.
933 * @param pCfgNode The CFGM node containing the overrides
934 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
935 */
936static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
937{
938 for (uint32_t i = 0; i < cLeaves; i++)
939 {
940 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
941 if (RT_FAILURE(rc))
942 return rc;
943 }
944
945 return VINF_SUCCESS;
946}
947
948/**
949 * Init a set of host CPUID leaves.
950 *
951 * @returns VBox status code.
952 * @param paLeaves The leaf array.
953 * @param cLeaves The number of leaves.
954 * @param uStart The start leaf number.
955 * @param pCfgNode The /CPUM/HostCPUID/ node.
956 */
957static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
958{
959 /* Using the ECX variant for all of them can't hurt... */
960 for (uint32_t i = 0; i < cLeaves; i++)
961 ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
962
963 /* Load CPUID leaf override; we currently don't care if the user
964 specifies features the host CPU doesn't support. */
965 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
966}
967
968
969static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCPUM, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
970{
971 /*
972 * Install the CPUID information.
973 */
974 int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
975 MM_TAG_CPUM_CPUID, (void **)&pCPUM->GuestInfo.paCpuIdLeavesR3);
976
977 AssertLogRelRCReturn(rc, rc);
978
979 pCPUM->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCPUM->GuestInfo.paCpuIdLeavesR3);
980 pCPUM->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCPUM->GuestInfo.paCpuIdLeavesR3);
981 Assert(MMHyperR0ToR3(pVM, pCPUM->GuestInfo.paCpuIdLeavesR0) == (void *)pCPUM->GuestInfo.paCpuIdLeavesR3);
982 Assert(MMHyperRCToR3(pVM, pCPUM->GuestInfo.paCpuIdLeavesRC) == (void *)pCPUM->GuestInfo.paCpuIdLeavesR3);
983
984 /*
985 * Explode the guest CPU features.
986 */
987 rc = cpumR3CpuIdExplodeFeatures(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, &pCPUM->GuestFeatures);
988 AssertLogRelRCReturn(rc, rc);
989
990
991 /*
992 * Populate the legacy arrays. Currently used for everything, later only
993 * for patch manager.
994 */
995 struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
996 {
997 { pCPUM->aGuestCpuIdStd, RT_ELEMENTS(pCPUM->aGuestCpuIdStd), 0x00000000 },
998 { pCPUM->aGuestCpuIdExt, RT_ELEMENTS(pCPUM->aGuestCpuIdExt), 0x80000000 },
999 { pCPUM->aGuestCpuIdCentaur, RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), 0xc0000000 },
1000 { pCPUM->aGuestCpuIdHyper, RT_ELEMENTS(pCPUM->aGuestCpuIdHyper), 0x40000000 },
1001 };
1002 for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
1003 {
1004 uint32_t cLeft = aOldRanges[i].cCpuIds;
1005 uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
1006 PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
1007 while (cLeft-- > 0)
1008 {
1009 uLeaf--;
1010 pLegacyLeaf--;
1011
1012 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, uLeaf, 0);
1013 if (pLeaf)
1014 {
1015 pLegacyLeaf->eax = pLeaf->uEax;
1016 pLegacyLeaf->ebx = pLeaf->uEbx;
1017 pLegacyLeaf->ecx = pLeaf->uEcx;
1018 pLegacyLeaf->edx = pLeaf->uEdx;
1019 }
1020 else
1021 *pLegacyLeaf = pCPUM->GuestInfo.DefCpuId;
1022 }
1023 }
1024
1025 pCPUM->GuestCpuIdDef = pCPUM->GuestInfo.DefCpuId;
1026
1027 return VINF_SUCCESS;
1028}
1029
1030
1031/**
1032 * Initializes the emulated CPU's cpuid information.
1033 *
1034 * @returns VBox status code.
1035 * @param pVM Pointer to the VM.
1036 */
1037static int cpumR3CpuIdInit(PVM pVM)
1038{
1039 PCPUM pCPUM = &pVM->cpum.s;
1040 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
1041 int rc;
1042
1043#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
1044 if ( pCPUM->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
1045 { \
1046 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
1047 (a_pLeafReg) &= ~(uint32_t)(fMask); \
1048 }
1049#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
1050 if ( pCPUM->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
1051 { \
1052 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1053 (a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1054 }
1055
1056 /*
1057 * Read the configuration.
1058 */
1059 /** @cfgm{CPUM/SyntheticCpu, boolean, false}
1060 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
1061 * completely overridden by VirtualBox custom strings. Some
1062 * CPUID information is withheld, like the cache info.
1063 *
1064 * This is obsoleted by PortableCpuIdLevel. */
1065 bool fSyntheticCpu;
1066 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &fSyntheticCpu, false);
1067 AssertRCReturn(rc, rc);
1068
1069 /** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
1070 * When non-zero CPUID features that could cause portability issues will be
1071 * stripped. The higher the value the more features gets stripped. Higher
1072 * values should only be used when older CPUs are involved since it may
1073 * harm performance and maybe also cause problems with specific guests. */
1074 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, fSyntheticCpu ? 1 : 0);
1075 AssertLogRelRCReturn(rc, rc);
1076
1077 /** @cfgm{CPUM/GuestCpuName, string}
1078 * The name of of the CPU we're to emulate. The default is the host CPU.
1079 * Note! CPUs other than "host" one is currently unsupported. */
1080 char szCpuName[128];
1081 rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", szCpuName, sizeof(szCpuName), "host");
1082 AssertLogRelRCReturn(rc, rc);
1083
1084 /** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
1085 * Expose CMPXCHG16B to the guest if supported by the host.
1086 */
1087 bool fCmpXchg16b;
1088 rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &fCmpXchg16b, false);
1089 AssertLogRelRCReturn(rc, rc);
1090
1091 /** @cfgm{/CPUM/MONITOR, boolean, true}
1092 * Expose MONITOR/MWAIT instructions to the guest.
1093 */
1094 bool fMonitor;
1095 rc = CFGMR3QueryBoolDef(pCpumCfg, "MONITOR", &fMonitor, true);
1096 AssertLogRelRCReturn(rc, rc);
1097
1098 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
1099 * Expose MWAIT extended features to the guest. For now we expose just MWAIT
1100 * break on interrupt feature (bit 1).
1101 */
1102 bool fMWaitExtensions;
1103 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false);
1104 AssertLogRelRCReturn(rc, rc);
1105
1106 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
1107 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
1108 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
1109 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
1110 */
1111 bool fNt4LeafLimit;
1112 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false);
1113 AssertLogRelRCReturn(rc, rc);
1114
1115 /** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
1116 * Restrict the reported CPU family+model+stepping of intel CPUs. This is
1117 * probably going to be a temporary hack, so don't depend on this.
1118 * The 1st byte of the value is the stepping, the 2nd byte value is the model
1119 * number and the 3rd byte value is the family, and the 4th value must be zero.
1120 */
1121 uint32_t uMaxIntelFamilyModelStep;
1122 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &uMaxIntelFamilyModelStep, UINT32_MAX);
1123 AssertLogRelRCReturn(rc, rc);
1124
1125 /*
1126 * Get the guest CPU data from the database and/or the host.
1127 */
1128 rc = cpumR3DbGetCpuInfo(szCpuName, &pCPUM->GuestInfo);
1129 if (RT_FAILURE(rc))
1130 return rc == VERR_CPUM_DB_CPU_NOT_FOUND
1131 ? VMSetError(pVM, rc, RT_SRC_POS,
1132 "Info on guest CPU '%s' could not be found. Please, select a different CPU.", szCpuName)
1133 : rc;
1134
1135 /** @cfgm{CPUM/MSRs/[Name]/[First|Last|Type|Value|...],}
1136 * Overrides the guest MSRs.
1137 */
1138 rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
1139
1140 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
1141 * Overrides the CPUID leaf values (from the host CPU usually) used for
1142 * calculating the guest CPUID leaves. This can be used to preserve the CPUID
1143 * values when moving a VM to a different machine. Another use is restricting
1144 * (or extending) the feature set exposed to the guest. */
1145 if (RT_SUCCESS(rc))
1146 rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
1147
1148 if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
1149 rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
1150 "Found unsupported configuration node '/CPUM/CPUID/'. "
1151 "Please use IMachine::setCPUIDLeaf() instead.");
1152
1153 /*
1154 * Pre-exploded the CPUID info.
1155 */
1156 if (RT_SUCCESS(rc))
1157 rc = cpumR3CpuIdExplodeFeatures(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, &pCPUM->GuestFeatures);
1158 if (RT_FAILURE(rc))
1159 {
1160 RTMemFree(pCPUM->GuestInfo.paCpuIdLeavesR3);
1161 pCPUM->GuestInfo.paCpuIdLeavesR3 = NULL;
1162 RTMemFree(pCPUM->GuestInfo.paMsrRangesR3);
1163 pCPUM->GuestInfo.paMsrRangesR3 = NULL;
1164 return rc;
1165 }
1166
1167
1168 /* ... split this function about here ... */
1169
1170
1171 PCPUMCPUIDLEAF pStdLeaf0 = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 0, 0);
1172 AssertLogRelReturn(pStdLeaf0, VERR_CPUM_IPE_2);
1173
1174
1175 /* Cpuid 1:
1176 * Only report features we can support.
1177 *
1178 * Note! When enabling new features the Synthetic CPU and Portable CPUID
1179 * options may require adjusting (i.e. stripping what was enabled).
1180 */
1181 PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 1, 0);
1182 AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
1183 pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
1184 | X86_CPUID_FEATURE_EDX_VME
1185 | X86_CPUID_FEATURE_EDX_DE
1186 | X86_CPUID_FEATURE_EDX_PSE
1187 | X86_CPUID_FEATURE_EDX_TSC
1188 | X86_CPUID_FEATURE_EDX_MSR
1189 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
1190 | X86_CPUID_FEATURE_EDX_MCE
1191 | X86_CPUID_FEATURE_EDX_CX8
1192 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
1193 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
1194 //| X86_CPUID_FEATURE_EDX_SEP
1195 | X86_CPUID_FEATURE_EDX_MTRR
1196 | X86_CPUID_FEATURE_EDX_PGE
1197 | X86_CPUID_FEATURE_EDX_MCA
1198 | X86_CPUID_FEATURE_EDX_CMOV
1199 | X86_CPUID_FEATURE_EDX_PAT
1200 | X86_CPUID_FEATURE_EDX_PSE36
1201 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
1202 | X86_CPUID_FEATURE_EDX_CLFSH
1203 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
1204 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
1205 | X86_CPUID_FEATURE_EDX_MMX
1206 | X86_CPUID_FEATURE_EDX_FXSR
1207 | X86_CPUID_FEATURE_EDX_SSE
1208 | X86_CPUID_FEATURE_EDX_SSE2
1209 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
1210 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
1211 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
1212 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
1213 | 0;
1214 pStdFeatureLeaf->uEcx &= 0
1215 | X86_CPUID_FEATURE_ECX_SSE3
1216 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
1217 | ((fMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
1218 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
1219 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
1220 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
1221 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
1222 | X86_CPUID_FEATURE_ECX_SSSE3
1223 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
1224 | (fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
1225 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
1226 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
1227 /* ECX Bit 21 - x2APIC support - not yet. */
1228 // | X86_CPUID_FEATURE_ECX_X2APIC
1229 /* ECX Bit 23 - POPCNT instruction. */
1230 //| X86_CPUID_FEATURE_ECX_POPCNT
1231 | 0;
1232 if (pCPUM->u8PortableCpuIdLevel > 0)
1233 {
1234 PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
1235 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
1236 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
1237 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16);
1238 PORTABLE_DISABLE_FEATURE_BIT(2, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
1239 PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
1240 PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
1241 PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
1242
1243 Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
1244 | X86_CPUID_FEATURE_EDX_PSN
1245 | X86_CPUID_FEATURE_EDX_DS
1246 | X86_CPUID_FEATURE_EDX_ACPI
1247 | X86_CPUID_FEATURE_EDX_SS
1248 | X86_CPUID_FEATURE_EDX_TM
1249 | X86_CPUID_FEATURE_EDX_PBE
1250 )));
1251 Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_PCLMUL
1252 | X86_CPUID_FEATURE_ECX_DTES64
1253 | X86_CPUID_FEATURE_ECX_CPLDS
1254 | X86_CPUID_FEATURE_ECX_VMX
1255 | X86_CPUID_FEATURE_ECX_SMX
1256 | X86_CPUID_FEATURE_ECX_EST
1257 | X86_CPUID_FEATURE_ECX_TM2
1258 | X86_CPUID_FEATURE_ECX_CNTXID
1259 | X86_CPUID_FEATURE_ECX_FMA
1260 | X86_CPUID_FEATURE_ECX_CX16
1261 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1262 | X86_CPUID_FEATURE_ECX_PDCM
1263 | X86_CPUID_FEATURE_ECX_DCA
1264 | X86_CPUID_FEATURE_ECX_MOVBE
1265 | X86_CPUID_FEATURE_ECX_AES
1266 | X86_CPUID_FEATURE_ECX_POPCNT
1267 | X86_CPUID_FEATURE_ECX_XSAVE
1268 | X86_CPUID_FEATURE_ECX_OSXSAVE
1269 | X86_CPUID_FEATURE_ECX_AVX
1270 )));
1271 }
1272
1273 /* Cpuid 0x80000001:
1274 * Only report features we can support.
1275 *
1276 * Note! When enabling new features the Synthetic CPU and Portable CPUID
1277 * options may require adjusting (i.e. stripping what was enabled).
1278 *
1279 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
1280 */
1281 PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
1282 UINT32_C(0x80000001), 0);
1283 if (pExtFeatureLeaf)
1284 {
1285 pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
1286 | X86_CPUID_AMD_FEATURE_EDX_VME
1287 | X86_CPUID_AMD_FEATURE_EDX_DE
1288 | X86_CPUID_AMD_FEATURE_EDX_PSE
1289 | X86_CPUID_AMD_FEATURE_EDX_TSC
1290 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
1291 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
1292 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
1293 | X86_CPUID_AMD_FEATURE_EDX_CX8
1294 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
1295 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
1296 //| X86_CPUID_EXT_FEATURE_EDX_SEP
1297 | X86_CPUID_AMD_FEATURE_EDX_MTRR
1298 | X86_CPUID_AMD_FEATURE_EDX_PGE
1299 | X86_CPUID_AMD_FEATURE_EDX_MCA
1300 | X86_CPUID_AMD_FEATURE_EDX_CMOV
1301 | X86_CPUID_AMD_FEATURE_EDX_PAT
1302 | X86_CPUID_AMD_FEATURE_EDX_PSE36
1303 //| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE.
1304 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
1305 | X86_CPUID_AMD_FEATURE_EDX_MMX
1306 | X86_CPUID_AMD_FEATURE_EDX_FXSR
1307 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
1308 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1309 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
1310 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
1311 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
1312 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
1313 | 0;
1314 pExtFeatureLeaf->uEcx &= 0
1315 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1316 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
1317 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
1318 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1319 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
1320 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1321 //| X86_CPUID_AMD_FEATURE_ECX_ABM
1322 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
1323 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1324 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1325 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
1326 //| X86_CPUID_AMD_FEATURE_ECX_IBS
1327 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
1328 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1329 //| X86_CPUID_AMD_FEATURE_ECX_WDT
1330 | 0;
1331 if (pCPUM->u8PortableCpuIdLevel > 0)
1332 {
1333 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1334 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1335 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1336 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1337 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1338 PORTABLE_DISABLE_FEATURE_BIT(2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1339 PORTABLE_DISABLE_FEATURE_BIT(3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1340
1341 Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
1342 | X86_CPUID_AMD_FEATURE_ECX_SVM
1343 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1344 | X86_CPUID_AMD_FEATURE_ECX_CR8L
1345 | X86_CPUID_AMD_FEATURE_ECX_ABM
1346 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
1347 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1348 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1349 | X86_CPUID_AMD_FEATURE_ECX_OSVW
1350 | X86_CPUID_AMD_FEATURE_ECX_IBS
1351 | X86_CPUID_AMD_FEATURE_ECX_SSE5
1352 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
1353 | X86_CPUID_AMD_FEATURE_ECX_WDT
1354 | UINT32_C(0xffffc000)
1355 )));
1356 Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
1357 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1358 | RT_BIT(18)
1359 | RT_BIT(19)
1360 | RT_BIT(21)
1361 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
1362 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1363 | RT_BIT(28)
1364 )));
1365 }
1366 }
1367
1368 /*
1369 * Hide HTT, multicode, SMP, whatever.
1370 * (APIC-ID := 0 and #LogCpus := 0)
1371 */
1372 pStdFeatureLeaf->uEbx &= 0x0000ffff;
1373#ifdef VBOX_WITH_MULTI_CORE
1374 if (pVM->cCpus > 1)
1375 {
1376 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
1377 pStdFeatureLeaf->uEbx |= (pVM->cCpus << 16);
1378 pStdFeatureLeaf->uEdx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
1379 }
1380#endif
1381
1382 /* Cpuid 2:
1383 * Intel: Cache and TLB information
1384 * AMD: Reserved
1385 * VIA: Reserved
1386 * Safe to expose; restrict the number of calls to 1 for the portable case.
1387 */
1388 PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 2, 0);
1389 if ( pCPUM->u8PortableCpuIdLevel > 0
1390 && pCurLeaf
1391 && (pCurLeaf->uEax & 0xff) > 1)
1392 {
1393 LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
1394 pCurLeaf->uEax &= UINT32_C(0xfffffffe);
1395 }
1396
1397 /* Cpuid 3:
1398 * Intel: EAX, EBX - reserved (transmeta uses these)
1399 * ECX, EDX - Processor Serial Number if available, otherwise reserved
1400 * AMD: Reserved
1401 * VIA: Reserved
1402 * Safe to expose
1403 */
1404 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 3, 0);
1405 if ( !(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN)
1406 && pCurLeaf)
1407 {
1408 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1409 if (pCPUM->u8PortableCpuIdLevel > 0)
1410 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1411 }
1412
1413 /* Cpuid 4:
1414 * Intel: Deterministic Cache Parameters Leaf
1415 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
1416 * AMD: Reserved
1417 * VIA: Reserved
1418 * Safe to expose, except for EAX:
1419 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1420 * Bits 31-26: Maximum number of processor cores in this physical package**
1421 * Note: These SMP values are constant regardless of ECX
1422 */
1423 CPUMCPUIDLEAF NewLeaf;
1424 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 4, 0);
1425 if (pCurLeaf)
1426 {
1427 NewLeaf.uLeaf = 4;
1428 NewLeaf.uSubLeaf = 0;
1429 NewLeaf.fSubLeafMask = 0;
1430 NewLeaf.uEax = 0;
1431 NewLeaf.uEbx = 0;
1432 NewLeaf.uEcx = 0;
1433 NewLeaf.uEdx = 0;
1434 NewLeaf.fFlags = 0;
1435#ifdef VBOX_WITH_MULTI_CORE
1436 if ( pVM->cCpus > 1
1437 && pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1438 {
1439 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1440 /* One logical processor with possibly multiple cores. */
1441 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1442 NewLeaf.uEax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
1443 }
1444#endif
1445 rc = cpumR3CpuIdInsert(&pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
1446 AssertLogRelRCReturn(rc, rc);
1447 }
1448
1449 /* Cpuid 5: Monitor/mwait Leaf
1450 * Intel: ECX, EDX - reserved
1451 * EAX, EBX - Smallest and largest monitor line size
1452 * AMD: EDX - reserved
1453 * EAX, EBX - Smallest and largest monitor line size
1454 * ECX - extensions (ignored for now)
1455 * VIA: Reserved
1456 * Safe to expose
1457 */
1458 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 5, 0);
1459 if (pCurLeaf)
1460 {
1461 if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
1462 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1463
1464 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1465 if (fMWaitExtensions)
1466 {
1467 pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1468 /** @todo: for now we just expose host's MWAIT C-states, although conceptually
1469 it shall be part of our power management virtualization model */
1470#if 0
1471 /* MWAIT sub C-states */
1472 pCurLeaf->uEdx =
1473 (0 << 0) /* 0 in C0 */ |
1474 (2 << 4) /* 2 in C1 */ |
1475 (2 << 8) /* 2 in C2 */ |
1476 (2 << 12) /* 2 in C3 */ |
1477 (0 << 16) /* 0 in C4 */
1478 ;
1479#endif
1480 }
1481 else
1482 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1483 }
1484
1485 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
1486 * Safe to pass on to the guest.
1487 *
1488 * Intel: 0x800000005 reserved
1489 * 0x800000006 L2 cache information
1490 * AMD: 0x800000005 L1 cache information
1491 * 0x800000006 L2/L3 cache information
1492 * VIA: 0x800000005 TLB and L1 cache information
1493 * 0x800000006 L2 cache information
1494 */
1495
1496 /* Cpuid 0x800000007:
1497 * Intel: Reserved
1498 * AMD: EAX, EBX, ECX - reserved
1499 * EDX: Advanced Power Management Information
1500 * VIA: Reserved
1501 */
1502 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000007), 0);
1503 if (pCurLeaf)
1504 {
1505 Assert(pCPUM->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
1506
1507 pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
1508
1509 if (pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
1510 {
1511 /* Only expose the TSC invariant capability bit to the guest. */
1512 pCurLeaf->uEdx &= 0
1513 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
1514 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
1515 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
1516 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
1517 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
1518 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
1519 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
1520 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
1521#if 0
1522 /*
1523 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
1524 * Linux kernels blindly assume that the AMD performance counters work
1525 * if this is set for 64 bits guests. (Can't really find a CPUID feature
1526 * bit for them though.)
1527 */
1528 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
1529#endif
1530 | 0;
1531 }
1532 else
1533 pCurLeaf->uEdx = 0;
1534 }
1535
1536 /* Cpuid 0x800000008:
1537 * Intel: EAX: Virtual/Physical address Size
1538 * EBX, ECX, EDX - reserved
1539 * AMD: EBX, EDX - reserved
1540 * EAX: Virtual/Physical/Guest address Size
1541 * ECX: Number of cores + APICIdCoreIdSize
1542 * VIA: EAX: Virtual/Physical address Size
1543 * EBX, ECX, EDX - reserved
1544 */
1545 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000008), 0);
1546 if (pCurLeaf)
1547 {
1548 /* Only expose the virtual and physical address sizes to the guest. */
1549 pCurLeaf->uEax &= UINT32_C(0x0000ffff);
1550 pCurLeaf->uEbx = pCurLeaf->uEdx = 0; /* reserved */
1551 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
1552 * NC (0-7) Number of cores; 0 equals 1 core */
1553 pCurLeaf->uEcx = 0;
1554#ifdef VBOX_WITH_MULTI_CORE
1555 if ( pVM->cCpus > 1
1556 && pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
1557 {
1558 /* Legacy method to determine the number of cores. */
1559 pCurLeaf->uEcx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
1560 if (pExtFeatureLeaf)
1561 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
1562 }
1563#endif
1564 }
1565
1566
1567 /*
1568 * Limit it the number of entries, zapping the remainder.
1569 *
1570 * The limits are masking off stuff about power saving and similar, this
1571 * is perhaps a bit crudely done as there is probably some relatively harmless
1572 * info too in these leaves (like words about having a constant TSC).
1573 */
1574 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 0, 0);
1575 if (pCurLeaf)
1576 {
1577 if (pCurLeaf->uEax > 5)
1578 {
1579 pCurLeaf->uEax = 5;
1580 cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
1581 pCurLeaf->uEax + 1, UINT32_C(0x000fffff));
1582 }
1583
1584 /* NT4 hack, no zapping of extra leaves here. */
1585 if (fNt4LeafLimit && pCurLeaf->uEax > 3)
1586 pCurLeaf->uEax = 3;
1587 }
1588
1589 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000000), 0);
1590 if (pCurLeaf)
1591 {
1592 if (pCurLeaf->uEax > UINT32_C(0x80000008))
1593 {
1594 pCurLeaf->uEax = UINT32_C(0x80000008);
1595 cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
1596 pCurLeaf->uEax + 1, UINT32_C(0x800fffff));
1597 }
1598 }
1599
1600 /*
1601 * Centaur stuff (VIA).
1602 *
1603 * The important part here (we think) is to make sure the 0xc0000000
1604 * function returns 0xc0000001. As for the features, we don't currently
1605 * let on about any of those... 0xc0000002 seems to be some
1606 * temperature/hz/++ stuff, include it as well (static).
1607 */
1608 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0xc0000000), 0);
1609 if (pCurLeaf)
1610 {
1611 if ( pCurLeaf->uEax >= UINT32_C(0xc0000000)
1612 && pCurLeaf->uEax <= UINT32_C(0xc0000004))
1613 {
1614 pCurLeaf->uEax = RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000002));
1615 cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
1616 UINT32_C(0xc0000002), UINT32_C(0xc00fffff));
1617
1618 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
1619 UINT32_C(0xc0000001), 0);
1620 if (pCurLeaf)
1621 pCurLeaf->uEdx = 0; /* all features hidden */
1622 }
1623 else
1624 cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
1625 UINT32_C(0xc0000000), UINT32_C(0xc00fffff));
1626 }
1627
1628 /*
1629 * Hypervisor identification.
1630 *
1631 * We only return minimal information, primarily ensuring that the
1632 * 0x40000000 function returns 0x40000001 and identifying ourselves.
1633 * Currently we do not support any hypervisor-specific interface.
1634 */
1635 NewLeaf.uLeaf = UINT32_C(0x40000000);
1636 NewLeaf.uSubLeaf = 0;
1637 NewLeaf.fSubLeafMask = 0;
1638 NewLeaf.uEax = UINT32_C(0x40000001);
1639 NewLeaf.uEbx = 0x786f4256 /* 'VBox' */;
1640 NewLeaf.uEcx = 0x786f4256 /* 'VBox' */;
1641 NewLeaf.uEdx = 0x786f4256 /* 'VBox' */;
1642 NewLeaf.fFlags = 0;
1643 rc = cpumR3CpuIdInsert(&pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
1644 AssertLogRelRCReturn(rc, rc);
1645
1646 NewLeaf.uLeaf = UINT32_C(0x40000001);
1647 NewLeaf.uEax = 0x656e6f6e; /* 'none' */
1648 NewLeaf.uEbx = 0;
1649 NewLeaf.uEcx = 0;
1650 NewLeaf.uEdx = 0;
1651 NewLeaf.fFlags = 0;
1652 rc = cpumR3CpuIdInsert(&pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
1653 AssertLogRelRCReturn(rc, rc);
1654
1655 /*
1656 * Mini CPU selection support for making Mac OS X happy.
1657 */
1658 if (pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1659 {
1660 uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
1661 ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
1662 ASMGetCpuFamily(pStdFeatureLeaf->uEax),
1663 0);
1664 if (uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1665 {
1666 uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
1667 uNew |= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1668 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1669 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1670 uNew |= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1671 if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1672 uNew |= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1673 LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1674 pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1675 pStdFeatureLeaf->uEax = uNew;
1676 }
1677 }
1678
1679
1680 /*
1681 * Move the MSR and CPUID arrays over on the hypervisor heap, and explode
1682 * guest CPU features again.
1683 */
1684 void *pvFree = pCPUM->GuestInfo.paCpuIdLeavesR3;
1685 int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCPUM, pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves);
1686 RTMemFree(pvFree);
1687
1688 pvFree = pCPUM->GuestInfo.paMsrRangesR3;
1689 int rc2 = MMHyperDupMem(pVM, pvFree,
1690 sizeof(pCPUM->GuestInfo.paMsrRangesR3[0]) * pCPUM->GuestInfo.cMsrRanges, 32,
1691 MM_TAG_CPUM_MSRS, (void **)&pCPUM->GuestInfo.paMsrRangesR3);
1692 RTMemFree(pvFree);
1693 AssertLogRelRCReturn(rc1, rc1);
1694 AssertLogRelRCReturn(rc2, rc2);
1695
1696 pCPUM->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCPUM->GuestInfo.paMsrRangesR3);
1697 pCPUM->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCPUM->GuestInfo.paMsrRangesR3);
1698 cpumR3MsrRegStats(pVM);
1699
1700 /*
1701 * Some more configuration that we're applying at the end of everything
1702 * via the CPUMSetGuestCpuIdFeature API.
1703 */
1704
1705 /* Check if PAE was explicitely enabled by the user. */
1706 bool fEnable;
1707 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
1708 if (fEnable)
1709 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1710
1711 /* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
1712 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
1713 if (fEnable)
1714 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1715
1716 /* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
1717 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
1718 if (fEnable)
1719 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
1720
1721#undef PORTABLE_DISABLE_FEATURE_BIT
1722#undef PORTABLE_CLEAR_BITS_WHEN
1723
1724 return VINF_SUCCESS;
1725}
1726
1727
1728/**
1729 * Applies relocations to data and code managed by this
1730 * component. This function will be called at init and
1731 * whenever the VMM need to relocate it self inside the GC.
1732 *
1733 * The CPUM will update the addresses used by the switcher.
1734 *
1735 * @param pVM The VM.
1736 */
1737VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1738{
1739 LogFlow(("CPUMR3Relocate\n"));
1740
1741 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
1742 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
1743
1744 /* Recheck the guest DRx values in raw-mode. */
1745 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1746 CPUMRecalcHyperDRx(&pVM->aCpus[iCpu], UINT8_MAX, false);
1747}
1748
1749
1750/**
1751 * Apply late CPUM property changes based on the fHWVirtEx setting
1752 *
1753 * @param pVM Pointer to the VM.
1754 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
1755 */
1756VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1757{
1758 /*
1759 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1760 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1761 * of processors from (cpuid(4).eax >> 26) + 1.
1762 *
1763 * Note: this code is obsolete, but let's keep it here for reference.
1764 * Purpose is valid when we artificially cap the max std id to less than 4.
1765 */
1766 if (!fHWVirtExEnabled)
1767 {
1768 Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1769 || pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1770 pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1771 }
1772}
1773
1774/**
1775 * Terminates the CPUM.
1776 *
1777 * Termination means cleaning up and freeing all resources,
1778 * the VM it self is at this point powered off or suspended.
1779 *
1780 * @returns VBox status code.
1781 * @param pVM Pointer to the VM.
1782 */
1783VMMR3DECL(int) CPUMR3Term(PVM pVM)
1784{
1785#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1786 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1787 {
1788 PVMCPU pVCpu = &pVM->aCpus[i];
1789 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1790
1791 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1792 pVCpu->cpum.s.uMagic = 0;
1793 pCtx->dr[5] = 0;
1794 }
1795#else
1796 NOREF(pVM);
1797#endif
1798 return VINF_SUCCESS;
1799}
1800
1801
1802/**
1803 * Resets a virtual CPU.
1804 *
1805 * Used by CPUMR3Reset and CPU hot plugging.
1806 *
1807 * @param pVM Pointer to the cross context VM structure.
1808 * @param pVCpu Pointer to the cross context virtual CPU structure of
1809 * the CPU that is being reset. This may differ from the
1810 * current EMT.
1811 */
1812VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1813{
1814 /** @todo anything different for VCPU > 0? */
1815 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1816
1817 /*
1818 * Initialize everything to ZERO first.
1819 */
1820 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1821 memset(pCtx, 0, sizeof(*pCtx));
1822 pVCpu->cpum.s.fUseFlags = fUseFlags;
1823
1824 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1825 pCtx->eip = 0x0000fff0;
1826 pCtx->edx = 0x00000600; /* P6 processor */
1827 pCtx->eflags.Bits.u1Reserved0 = 1;
1828
1829 pCtx->cs.Sel = 0xf000;
1830 pCtx->cs.ValidSel = 0xf000;
1831 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1832 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1833 pCtx->cs.u32Limit = 0x0000ffff;
1834 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1835 pCtx->cs.Attr.n.u1Present = 1;
1836 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1837
1838 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1839 pCtx->ds.u32Limit = 0x0000ffff;
1840 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1841 pCtx->ds.Attr.n.u1Present = 1;
1842 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1843
1844 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1845 pCtx->es.u32Limit = 0x0000ffff;
1846 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1847 pCtx->es.Attr.n.u1Present = 1;
1848 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1849
1850 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1851 pCtx->fs.u32Limit = 0x0000ffff;
1852 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1853 pCtx->fs.Attr.n.u1Present = 1;
1854 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1855
1856 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1857 pCtx->gs.u32Limit = 0x0000ffff;
1858 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1859 pCtx->gs.Attr.n.u1Present = 1;
1860 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1861
1862 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1863 pCtx->ss.u32Limit = 0x0000ffff;
1864 pCtx->ss.Attr.n.u1Present = 1;
1865 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1866 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1867
1868 pCtx->idtr.cbIdt = 0xffff;
1869 pCtx->gdtr.cbGdt = 0xffff;
1870
1871 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1872 pCtx->ldtr.u32Limit = 0xffff;
1873 pCtx->ldtr.Attr.n.u1Present = 1;
1874 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1875
1876 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1877 pCtx->tr.u32Limit = 0xffff;
1878 pCtx->tr.Attr.n.u1Present = 1;
1879 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1880
1881 pCtx->dr[6] = X86_DR6_INIT_VAL;
1882 pCtx->dr[7] = X86_DR7_INIT_VAL;
1883
1884 pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1885 pCtx->fpu.FCW = 0x37f;
1886
1887 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1888 IA-32 Processor States Following Power-up, Reset, or INIT */
1889 pCtx->fpu.MXCSR = 0x1F80;
1890 pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1891 supports all bits, since a zero value here should be read as 0xffbf. */
1892
1893 /*
1894 * MSRs.
1895 */
1896 /* Init PAT MSR */
1897 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1898
1899 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1900 * The Intel docs don't mention it. */
1901 Assert(!pCtx->msrEFER);
1902
1903 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1904 is supposed to be here, just trying provide useful/sensible values. */
1905 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1906 if (pRange)
1907 {
1908 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1909 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1910 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1911 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1912 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1913 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1914 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1915 }
1916
1917 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1918
1919 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1920 * called from each EMT while we're getting called by CPUMR3Reset()
1921 * iteratively on the same thread. Fix later. */
1922#if 0 /** @todo r=bird: This we will do in TM, not here. */
1923 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1924 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1925#endif
1926
1927
1928 /* C-state control. Guesses. */
1929 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1930
1931
1932 /*
1933 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1934 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1935 */
1936 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
1937}
1938
1939
1940/**
1941 * Resets the CPU.
1942 *
1943 * @returns VINF_SUCCESS.
1944 * @param pVM Pointer to the VM.
1945 */
1946VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1947{
1948 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1949 {
1950 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1951
1952#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1953 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1954
1955 /* Magic marker for searching in crash dumps. */
1956 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1957 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1958 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1959#endif
1960 }
1961}
1962
1963
1964/**
1965 * Called both in pass 0 and the final pass.
1966 *
1967 * @param pVM Pointer to the VM.
1968 * @param pSSM The saved state handle.
1969 */
1970static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1971{
1972 /*
1973 * Save all the CPU ID leaves here so we can check them for compatibility
1974 * upon loading.
1975 */
1976 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1977 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1978
1979 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1980 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1981
1982 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1983 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1984
1985 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1986
1987 /*
1988 * Save a good portion of the raw CPU IDs as well as they may come in
1989 * handy when validating features for raw mode.
1990 */
1991 CPUMCPUID aRawStd[16];
1992 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1993 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1994 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1995 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1996
1997 CPUMCPUID aRawExt[32];
1998 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1999 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
2000 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
2001 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
2002}
2003
2004
2005static int cpumR3LoadCpuIdOneGuestArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
2006{
2007 uint32_t cCpuIds;
2008 int rc = SSMR3GetU32(pSSM, &cCpuIds);
2009 if (RT_SUCCESS(rc))
2010 {
2011 if (cCpuIds < 64)
2012 {
2013 for (uint32_t i = 0; i < cCpuIds; i++)
2014 {
2015 CPUMCPUID CpuId;
2016 rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
2017 if (RT_FAILURE(rc))
2018 break;
2019
2020 CPUMCPUIDLEAF NewLeaf;
2021 NewLeaf.uLeaf = uBase + i;
2022 NewLeaf.uSubLeaf = 0;
2023 NewLeaf.fSubLeafMask = 0;
2024 NewLeaf.uEax = CpuId.eax;
2025 NewLeaf.uEbx = CpuId.ebx;
2026 NewLeaf.uEcx = CpuId.ecx;
2027 NewLeaf.uEdx = CpuId.edx;
2028 NewLeaf.fFlags = 0;
2029 rc = cpumR3CpuIdInsert(ppaLeaves, pcLeaves, &NewLeaf);
2030 }
2031 }
2032 else
2033 rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2034 }
2035 if (RT_FAILURE(rc))
2036 {
2037 RTMemFree(*ppaLeaves);
2038 *ppaLeaves = NULL;
2039 *pcLeaves = 0;
2040 }
2041 return rc;
2042}
2043
2044
2045static int cpumR3LoadCpuIdGuestArrays(PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
2046{
2047 *ppaLeaves = NULL;
2048 *pcLeaves = 0;
2049
2050 int rc = cpumR3LoadCpuIdOneGuestArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
2051 if (RT_SUCCESS(rc))
2052 rc = cpumR3LoadCpuIdOneGuestArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
2053 if (RT_SUCCESS(rc))
2054 rc = cpumR3LoadCpuIdOneGuestArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
2055
2056 return rc;
2057}
2058
2059
2060/**
2061 * Loads the CPU ID leaves saved by pass 0.
2062 *
2063 * @returns VBox status code.
2064 * @param pVM Pointer to the VM.
2065 * @param pSSM The saved state handle.
2066 * @param uVersion The format version.
2067 */
2068static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2069{
2070 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
2071
2072 /*
2073 * Define a bunch of macros for simplifying the code.
2074 */
2075 /* Generic expression + failure message. */
2076#define CPUID_CHECK_RET(expr, fmt) \
2077 do { \
2078 if (!(expr)) \
2079 { \
2080 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
2081 if (fStrictCpuIdChecks) \
2082 { \
2083 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
2084 RTStrFree(pszMsg); \
2085 return rcCpuid; \
2086 } \
2087 LogRel(("CPUM: %s\n", pszMsg)); \
2088 RTStrFree(pszMsg); \
2089 } \
2090 } while (0)
2091#define CPUID_CHECK_WRN(expr, fmt) \
2092 do { \
2093 if (!(expr)) \
2094 LogRel(fmt); \
2095 } while (0)
2096
2097 /* For comparing two values and bitch if they differs. */
2098#define CPUID_CHECK2_RET(what, host, saved) \
2099 do { \
2100 if ((host) != (saved)) \
2101 { \
2102 if (fStrictCpuIdChecks) \
2103 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2104 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
2105 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
2106 } \
2107 } while (0)
2108#define CPUID_CHECK2_WRN(what, host, saved) \
2109 do { \
2110 if ((host) != (saved)) \
2111 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
2112 } while (0)
2113
2114 /* For checking raw cpu features (raw mode). */
2115#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
2116 do { \
2117 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
2118 { \
2119 if (fStrictCpuIdChecks) \
2120 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2121 N_(#bit " mismatch: host=%d saved=%d"), \
2122 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
2123 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
2124 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
2125 } \
2126 } while (0)
2127#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
2128 do { \
2129 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
2130 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
2131 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
2132 } while (0)
2133#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
2134
2135 /* For checking guest features. */
2136#define CPUID_GST_FEATURE_RET(set, reg, bit) \
2137 do { \
2138 if ( (aGuestCpuId##set [1].reg & bit) \
2139 && !(aHostRaw##set [1].reg & bit) \
2140 && !(aHostOverride##set [1].reg & bit) \
2141 ) \
2142 { \
2143 if (fStrictCpuIdChecks) \
2144 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2145 N_(#bit " is not supported by the host but has already exposed to the guest")); \
2146 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
2147 } \
2148 } while (0)
2149#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
2150 do { \
2151 if ( (aGuestCpuId##set [1].reg & bit) \
2152 && !(aHostRaw##set [1].reg & bit) \
2153 && !(aHostOverride##set [1].reg & bit) \
2154 ) \
2155 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
2156 } while (0)
2157#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
2158 do { \
2159 if ( (aGuestCpuId##set [1].reg & bit) \
2160 && !(aHostRaw##set [1].reg & bit) \
2161 && !(aHostOverride##set [1].reg & bit) \
2162 ) \
2163 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
2164 } while (0)
2165#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
2166
2167 /* For checking guest features if AMD guest CPU. */
2168#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
2169 do { \
2170 if ( (aGuestCpuId##set [1].reg & bit) \
2171 && fGuestAmd \
2172 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
2173 && !(aHostOverride##set [1].reg & bit) \
2174 ) \
2175 { \
2176 if (fStrictCpuIdChecks) \
2177 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2178 N_(#bit " is not supported by the host but has already exposed to the guest")); \
2179 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
2180 } \
2181 } while (0)
2182#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
2183 do { \
2184 if ( (aGuestCpuId##set [1].reg & bit) \
2185 && fGuestAmd \
2186 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
2187 && !(aHostOverride##set [1].reg & bit) \
2188 ) \
2189 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
2190 } while (0)
2191#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
2192 do { \
2193 if ( (aGuestCpuId##set [1].reg & bit) \
2194 && fGuestAmd \
2195 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
2196 && !(aHostOverride##set [1].reg & bit) \
2197 ) \
2198 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
2199 } while (0)
2200#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
2201
2202 /* For checking AMD features which have a corresponding bit in the standard
2203 range. (Intel defines very few bits in the extended feature sets.) */
2204#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
2205 do { \
2206 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
2207 && !(fHostAmd \
2208 ? aHostRawExt[1].reg & (ExtBit) \
2209 : aHostRawStd[1].reg & (StdBit)) \
2210 && !(aHostOverrideExt[1].reg & (ExtBit)) \
2211 ) \
2212 { \
2213 if (fStrictCpuIdChecks) \
2214 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2215 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
2216 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
2217 } \
2218 } while (0)
2219#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
2220 do { \
2221 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
2222 && !(fHostAmd \
2223 ? aHostRawExt[1].reg & (ExtBit) \
2224 : aHostRawStd[1].reg & (StdBit)) \
2225 && !(aHostOverrideExt[1].reg & (ExtBit)) \
2226 ) \
2227 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
2228 } while (0)
2229#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
2230 do { \
2231 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
2232 && !(fHostAmd \
2233 ? aHostRawExt[1].reg & (ExtBit) \
2234 : aHostRawStd[1].reg & (StdBit)) \
2235 && !(aHostOverrideExt[1].reg & (ExtBit)) \
2236 ) \
2237 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
2238 } while (0)
2239#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
2240
2241 /*
2242 * Load them into stack buffers first.
2243 */
2244 PCPUMCPUIDLEAF paLeaves;
2245 uint32_t cLeaves;
2246 int rc = cpumR3LoadCpuIdGuestArrays(pSSM, uVersion, &paLeaves, &cLeaves);
2247 AssertRCReturn(rc, rc);
2248
2249 /** @todo we'll be leaking paLeaves on error return... */
2250
2251 CPUMCPUID GuestCpuIdDef;
2252 rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
2253 AssertRCReturn(rc, rc);
2254
2255 CPUMCPUID aRawStd[16];
2256 uint32_t cRawStd;
2257 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
2258 if (cRawStd > RT_ELEMENTS(aRawStd))
2259 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2260 rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
2261 AssertRCReturn(rc, rc);
2262 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
2263 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
2264
2265 CPUMCPUID aRawExt[32];
2266 uint32_t cRawExt;
2267 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
2268 if (cRawExt > RT_ELEMENTS(aRawExt))
2269 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2270 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
2271 AssertRCReturn(rc, rc);
2272 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
2273 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
2274
2275 /*
2276 * Get the raw CPU IDs for the current host.
2277 */
2278 CPUMCPUID aHostRawStd[16];
2279 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
2280 ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
2281
2282 CPUMCPUID aHostRawExt[32];
2283 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
2284 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0,
2285 &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
2286
2287 /*
2288 * Get the host and guest overrides so we don't reject the state because
2289 * some feature was enabled thru these interfaces.
2290 * Note! We currently only need the feature leaves, so skip rest.
2291 */
2292 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
2293 CPUMCPUID aHostOverrideStd[2];
2294 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
2295 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
2296
2297 CPUMCPUID aHostOverrideExt[2];
2298 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
2299 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
2300
2301 /*
2302 * This can be skipped.
2303 */
2304 bool fStrictCpuIdChecks;
2305 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
2306
2307
2308
2309 /*
2310 * For raw-mode we'll require that the CPUs are very similar since we don't
2311 * intercept CPUID instructions for user mode applications.
2312 */
2313 if (!HMIsEnabled(pVM))
2314 {
2315 /* CPUID(0) */
2316 CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
2317 && aHostRawStd[0].ecx == aRawStd[0].ecx
2318 && aHostRawStd[0].edx == aRawStd[0].edx,
2319 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2320 &aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
2321 &aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
2322 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
2323 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
2324 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2325
2326 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
2327
2328 /* CPUID(1).eax */
2329 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
2330 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
2331 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
2332
2333 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
2334 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
2335 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
2336
2337 /* CPUID(1).ecx */
2338 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
2339 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
2340 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
2341 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2342 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
2343 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
2344 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
2345 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
2346 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
2347 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
2348 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
2349 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2350 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
2351 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
2352 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
2353 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
2354 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2355 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2356 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
2357 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
2358 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
2359 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2360 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
2361 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
2362 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2363 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
2364 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
2365 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
2366 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
2367 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2368 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2369 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_HVP);
2370
2371 /* CPUID(1).edx */
2372 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2373 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2374 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
2375 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2376 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
2377 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
2378 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2379 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2380 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
2381 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2382 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2383 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2384 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2385 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2386 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2387 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
2388 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2389 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2390 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2391 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
2392 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2393 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
2394 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
2395 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
2396 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
2397 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
2398 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
2399 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
2400 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
2401 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
2402 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/);
2403 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
2404
2405 /* CPUID(2) - config, mostly about caches. ignore. */
2406 /* CPUID(3) - processor serial number. ignore. */
2407 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
2408 /* CPUID(5) - mwait/monitor config. ignore. */
2409 /* CPUID(6) - power management. ignore. */
2410 /* CPUID(7) - ???. ignore. */
2411 /* CPUID(8) - ???. ignore. */
2412 /* CPUID(9) - DCA. ignore for now. */
2413 /* CPUID(a) - PeMo info. ignore for now. */
2414 /* CPUID(b) - topology info - takes ECX as input. ignore. */
2415
2416 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
2417 CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
2418 || aHostRawStd[0].eax >= UINT32_C(0x0000000d),
2419 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
2420 if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
2421 && aHostRawStd[0].eax >= UINT32_C(0x0000000d))
2422 {
2423 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
2424 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
2425 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
2426 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
2427 }
2428
2429 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
2430 Note! Intel have/is marking many of the fields here as reserved. We
2431 will verify them as if it's an AMD CPU. */
2432 CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
2433 || !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
2434 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
2435 if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
2436 {
2437 CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
2438 && aHostRawExt[0].ecx == aRawExt[0].ecx
2439 && aHostRawExt[0].edx == aRawExt[0].edx,
2440 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2441 &aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
2442 &aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
2443 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
2444
2445 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
2446 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
2447 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
2448 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
2449 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
2450 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2451
2452 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
2453 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
2454 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
2455 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
2456
2457 /* CPUID(0x80000001).ecx */
2458 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2459 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
2460 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
2461 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
2462 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2463 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
2464 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
2465 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
2466 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
2467 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
2468 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
2469 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
2470 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
2471 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
2472 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2473 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2474 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2475 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2476 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2477 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2478 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2479 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2480 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2481 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2482 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2483 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2484 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2485 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2486 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2487 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2488 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2489 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2490
2491 /* CPUID(0x80000001).edx */
2492 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
2493 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
2494 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
2495 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
2496 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
2497 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
2498 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
2499 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
2500 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
2501 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
2502 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2503 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SEP);
2504 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
2505 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
2506 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
2507 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2508 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
2509 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
2510 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2511 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2512 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2513 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/);
2514 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2515 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
2516 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
2517 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2518 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2519 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2520 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/);
2521 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2522 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2523 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2524
2525 /** @todo verify the rest as well. */
2526 }
2527 }
2528
2529
2530
2531 /*
2532 * Verify that we can support the features already exposed to the guest on
2533 * this host.
2534 *
2535 * Most of the features we're emulating requires intercepting instruction
2536 * and doing it the slow way, so there is no need to warn when they aren't
2537 * present in the host CPU. Thus we use IGN instead of EMU on these.
2538 *
2539 * Trailing comments:
2540 * "EMU" - Possible to emulate, could be lots of work and very slow.
2541 * "EMU?" - Can this be emulated?
2542 */
2543 CPUMCPUID aGuestCpuIdStd[2];
2544 RT_ZERO(aGuestCpuIdStd);
2545 cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
2546
2547 /* CPUID(1).ecx */
2548 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
2549 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
2550 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
2551 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2552 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
2553 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
2554 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
2555 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
2556 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
2557 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
2558 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
2559 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2560 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
2561 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
2562 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
2563 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
2564 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2565 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2566 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
2567 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
2568 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
2569 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2570 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
2571 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
2572 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2573 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
2574 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
2575 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
2576 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
2577 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2578 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2579 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
2580
2581 /* CPUID(1).edx */
2582 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2583 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2584 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
2585 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2586 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2587 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2588 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2589 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2590 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2591 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2592 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2593 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2594 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2595 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2596 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2597 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2598 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2599 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2600 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2601 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
2602 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2603 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
2604 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
2605 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2606 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2607 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
2608 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
2609 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
2610 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
2611 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
2612 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
2613 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
2614
2615 /* CPUID(0x80000000). */
2616 CPUMCPUID aGuestCpuIdExt[2];
2617 RT_ZERO(aGuestCpuIdExt);
2618 if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
2619 {
2620 /** @todo deal with no 0x80000001 on the host. */
2621 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
2622 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
2623
2624 /* CPUID(0x80000001).ecx */
2625 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
2626 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
2627 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
2628 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
2629 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
2630 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
2631 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
2632 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
2633 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
2634 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
2635 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
2636 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
2637 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
2638 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
2639 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2640 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2641 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2642 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2643 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2644 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2645 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2646 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2647 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2648 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2649 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2650 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2651 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2652 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2653 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2654 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2655 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2656 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2657
2658 /* CPUID(0x80000001).edx */
2659 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
2660 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
2661 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
2662 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
2663 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2664 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2665 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
2666 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
2667 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2668 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
2669 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2670 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
2671 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
2672 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
2673 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
2674 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2675 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
2676 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
2677 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2678 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2679 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2680 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/);
2681 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2682 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2683 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2684 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2685 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2686 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2687 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/);
2688 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2689 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2690 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2691 }
2692
2693 /*
2694 * We're good, commit the CPU ID leaves.
2695 */
2696 MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
2697 pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
2698 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
2699 pVM->cpum.s.GuestInfo.DefCpuId = GuestCpuIdDef;
2700 rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
2701 RTMemFree(paLeaves);
2702 AssertLogRelRCReturn(rc, rc);
2703
2704
2705#undef CPUID_CHECK_RET
2706#undef CPUID_CHECK_WRN
2707#undef CPUID_CHECK2_RET
2708#undef CPUID_CHECK2_WRN
2709#undef CPUID_RAW_FEATURE_RET
2710#undef CPUID_RAW_FEATURE_WRN
2711#undef CPUID_RAW_FEATURE_IGN
2712#undef CPUID_GST_FEATURE_RET
2713#undef CPUID_GST_FEATURE_WRN
2714#undef CPUID_GST_FEATURE_EMU
2715#undef CPUID_GST_FEATURE_IGN
2716#undef CPUID_GST_FEATURE2_RET
2717#undef CPUID_GST_FEATURE2_WRN
2718#undef CPUID_GST_FEATURE2_EMU
2719#undef CPUID_GST_FEATURE2_IGN
2720#undef CPUID_GST_AMD_FEATURE_RET
2721#undef CPUID_GST_AMD_FEATURE_WRN
2722#undef CPUID_GST_AMD_FEATURE_EMU
2723#undef CPUID_GST_AMD_FEATURE_IGN
2724
2725 return VINF_SUCCESS;
2726}
2727
2728
2729/**
2730 * Pass 0 live exec callback.
2731 *
2732 * @returns VINF_SSM_DONT_CALL_AGAIN.
2733 * @param pVM Pointer to the VM.
2734 * @param pSSM The saved state handle.
2735 * @param uPass The pass (0).
2736 */
2737static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2738{
2739 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2740 cpumR3SaveCpuId(pVM, pSSM);
2741 return VINF_SSM_DONT_CALL_AGAIN;
2742}
2743
2744
2745/**
2746 * Execute state save operation.
2747 *
2748 * @returns VBox status code.
2749 * @param pVM Pointer to the VM.
2750 * @param pSSM SSM operation handle.
2751 */
2752static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2753{
2754 /*
2755 * Save.
2756 */
2757 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2758 {
2759 PVMCPU pVCpu = &pVM->aCpus[i];
2760 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2761 }
2762
2763 SSMR3PutU32(pSSM, pVM->cCpus);
2764 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2765 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2766 {
2767 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2768
2769 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), 0, g_aCpumCtxFields, NULL);
2770 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2771 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2772 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2773 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2774 }
2775
2776 cpumR3SaveCpuId(pVM, pSSM);
2777 return VINF_SUCCESS;
2778}
2779
2780
2781/**
2782 * @copydoc FNSSMINTLOADPREP
2783 */
2784static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2785{
2786 NOREF(pSSM);
2787 pVM->cpum.s.fPendingRestore = true;
2788 return VINF_SUCCESS;
2789}
2790
2791
2792/**
2793 * @copydoc FNSSMINTLOADEXEC
2794 */
2795static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2796{
2797 /*
2798 * Validate version.
2799 */
2800 if ( uVersion != CPUM_SAVED_STATE_VERSION
2801 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2802 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2803 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2804 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2805 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2806 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2807 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2808 {
2809 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2810 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2811 }
2812
2813 if (uPass == SSM_PASS_FINAL)
2814 {
2815 /*
2816 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2817 * really old SSM file versions.)
2818 */
2819 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2820 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2821 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2822 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2823
2824 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2825 PCSSMFIELD paCpumCtxFields = g_aCpumCtxFields;
2826 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2827 paCpumCtxFields = g_aCpumCtxFieldsV16;
2828 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2829 paCpumCtxFields = g_aCpumCtxFieldsMem;
2830
2831 /*
2832 * Restore.
2833 */
2834 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2835 {
2836 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2837 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2838 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2839 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), fLoad, paCpumCtxFields, NULL);
2840 pVCpu->cpum.s.Hyper.cr3 = uCR3;
2841 pVCpu->cpum.s.Hyper.rsp = uRSP;
2842 }
2843
2844 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2845 {
2846 uint32_t cCpus;
2847 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2848 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2849 VERR_SSM_UNEXPECTED_DATA);
2850 }
2851 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2852 || pVM->cCpus == 1,
2853 ("cCpus=%u\n", pVM->cCpus),
2854 VERR_SSM_UNEXPECTED_DATA);
2855
2856 uint32_t cbMsrs = 0;
2857 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2858 {
2859 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2860 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2861 VERR_SSM_UNEXPECTED_DATA);
2862 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2863 VERR_SSM_UNEXPECTED_DATA);
2864 }
2865
2866 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2867 {
2868 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2869 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), fLoad,
2870 paCpumCtxFields, NULL);
2871 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2872 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2873 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2874 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2875 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2876 {
2877 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2878 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2879 }
2880
2881 /* REM and other may have cleared must-be-one fields in DR6 and
2882 DR7, fix these. */
2883 pVCpu->cpum.s.Guest.dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
2884 pVCpu->cpum.s.Guest.dr[6] |= X86_DR6_RA1_MASK;
2885 pVCpu->cpum.s.Guest.dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2886 pVCpu->cpum.s.Guest.dr[7] |= X86_DR7_RA1_MASK;
2887 }
2888
2889 /* Older states does not have the internal selector register flags
2890 and valid selector value. Supply those. */
2891 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2892 {
2893 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2894 {
2895 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2896 bool const fValid = HMIsEnabled(pVM)
2897 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2898 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2899 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2900 if (fValid)
2901 {
2902 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2903 {
2904 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2905 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2906 }
2907
2908 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2909 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2910 }
2911 else
2912 {
2913 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2914 {
2915 paSelReg[iSelReg].fFlags = 0;
2916 paSelReg[iSelReg].ValidSel = 0;
2917 }
2918
2919 /* This might not be 104% correct, but I think it's close
2920 enough for all practical purposes... (REM always loaded
2921 LDTR registers.) */
2922 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2923 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2924 }
2925 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2926 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2927 }
2928 }
2929
2930 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2931 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2932 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2933 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2934 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2935
2936 /*
2937 * A quick sanity check.
2938 */
2939 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2940 {
2941 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2942 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2943 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2944 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2945 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2946 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2947 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2948 }
2949 }
2950
2951 pVM->cpum.s.fPendingRestore = false;
2952
2953 /*
2954 * Guest CPUIDs.
2955 */
2956 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2957 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2958
2959 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2960 * actually required. */
2961
2962 /*
2963 * Restore the CPUID leaves.
2964 *
2965 * Note that we support restoring less than the current amount of standard
2966 * leaves because we've been allowed more is newer version of VBox.
2967 */
2968 uint32_t cElements;
2969 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2970 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2971 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2972 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2973
2974 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2975 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2976 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2977 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2978
2979 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2980 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2981 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2982 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2983
2984 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2985
2986 /*
2987 * Check that the basic cpuid id information is unchanged.
2988 */
2989 /** @todo we should check the 64 bits capabilities too! */
2990 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2991 ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2992 ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2993 uint32_t au32CpuIdSaved[8];
2994 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2995 if (RT_SUCCESS(rc))
2996 {
2997 /* Ignore CPU stepping. */
2998 au32CpuId[4] &= 0xfffffff0;
2999 au32CpuIdSaved[4] &= 0xfffffff0;
3000
3001 /* Ignore APIC ID (AMD specs). */
3002 au32CpuId[5] &= ~0xff000000;
3003 au32CpuIdSaved[5] &= ~0xff000000;
3004
3005 /* Ignore the number of Logical CPUs (AMD specs). */
3006 au32CpuId[5] &= ~0x00ff0000;
3007 au32CpuIdSaved[5] &= ~0x00ff0000;
3008
3009 /* Ignore some advanced capability bits, that we don't expose to the guest. */
3010 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
3011 | X86_CPUID_FEATURE_ECX_VMX
3012 | X86_CPUID_FEATURE_ECX_SMX
3013 | X86_CPUID_FEATURE_ECX_EST
3014 | X86_CPUID_FEATURE_ECX_TM2
3015 | X86_CPUID_FEATURE_ECX_CNTXID
3016 | X86_CPUID_FEATURE_ECX_TPRUPDATE
3017 | X86_CPUID_FEATURE_ECX_PDCM
3018 | X86_CPUID_FEATURE_ECX_DCA
3019 | X86_CPUID_FEATURE_ECX_X2APIC
3020 );
3021 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
3022 | X86_CPUID_FEATURE_ECX_VMX
3023 | X86_CPUID_FEATURE_ECX_SMX
3024 | X86_CPUID_FEATURE_ECX_EST
3025 | X86_CPUID_FEATURE_ECX_TM2
3026 | X86_CPUID_FEATURE_ECX_CNTXID
3027 | X86_CPUID_FEATURE_ECX_TPRUPDATE
3028 | X86_CPUID_FEATURE_ECX_PDCM
3029 | X86_CPUID_FEATURE_ECX_DCA
3030 | X86_CPUID_FEATURE_ECX_X2APIC
3031 );
3032
3033 /* Make sure we don't forget to update the masks when enabling
3034 * features in the future.
3035 */
3036 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
3037 ( X86_CPUID_FEATURE_ECX_DTES64
3038 | X86_CPUID_FEATURE_ECX_VMX
3039 | X86_CPUID_FEATURE_ECX_SMX
3040 | X86_CPUID_FEATURE_ECX_EST
3041 | X86_CPUID_FEATURE_ECX_TM2
3042 | X86_CPUID_FEATURE_ECX_CNTXID
3043 | X86_CPUID_FEATURE_ECX_TPRUPDATE
3044 | X86_CPUID_FEATURE_ECX_PDCM
3045 | X86_CPUID_FEATURE_ECX_DCA
3046 | X86_CPUID_FEATURE_ECX_X2APIC
3047 )));
3048 /* do the compare */
3049 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
3050 {
3051 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
3052 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
3053 "Saved=%.*Rhxs\n"
3054 "Real =%.*Rhxs\n",
3055 sizeof(au32CpuIdSaved), au32CpuIdSaved,
3056 sizeof(au32CpuId), au32CpuId));
3057 else
3058 {
3059 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
3060 "Saved=%.*Rhxs\n"
3061 "Real =%.*Rhxs\n",
3062 sizeof(au32CpuIdSaved), au32CpuIdSaved,
3063 sizeof(au32CpuId), au32CpuId));
3064 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
3065 }
3066 }
3067 }
3068
3069 return rc;
3070}
3071
3072
3073/**
3074 * @copydoc FNSSMINTLOADPREP
3075 */
3076static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3077{
3078 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3079 return VINF_SUCCESS;
3080
3081 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3082 if (pVM->cpum.s.fPendingRestore)
3083 {
3084 LogRel(("CPUM: Missing state!\n"));
3085 return VERR_INTERNAL_ERROR_2;
3086 }
3087
3088 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
3089 {
3090 /* Notify PGM of the NXE states in case they've changed. */
3091 PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3092
3093 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
3094 PDMApicGetBase(&pVM->aCpus[iCpu], &pVM->aCpus[iCpu].cpum.s.Guest.msrApicBase);
3095 }
3096 return VINF_SUCCESS;
3097}
3098
3099
3100/**
3101 * Checks if the CPUM state restore is still pending.
3102 *
3103 * @returns true / false.
3104 * @param pVM Pointer to the VM.
3105 */
3106VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3107{
3108 return pVM->cpum.s.fPendingRestore;
3109}
3110
3111
3112/**
3113 * Formats the EFLAGS value into mnemonics.
3114 *
3115 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3116 * @param efl The EFLAGS value.
3117 */
3118static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3119{
3120 /*
3121 * Format the flags.
3122 */
3123 static const struct
3124 {
3125 const char *pszSet; const char *pszClear; uint32_t fFlag;
3126 } s_aFlags[] =
3127 {
3128 { "vip",NULL, X86_EFL_VIP },
3129 { "vif",NULL, X86_EFL_VIF },
3130 { "ac", NULL, X86_EFL_AC },
3131 { "vm", NULL, X86_EFL_VM },
3132 { "rf", NULL, X86_EFL_RF },
3133 { "nt", NULL, X86_EFL_NT },
3134 { "ov", "nv", X86_EFL_OF },
3135 { "dn", "up", X86_EFL_DF },
3136 { "ei", "di", X86_EFL_IF },
3137 { "tf", NULL, X86_EFL_TF },
3138 { "nt", "pl", X86_EFL_SF },
3139 { "nz", "zr", X86_EFL_ZF },
3140 { "ac", "na", X86_EFL_AF },
3141 { "po", "pe", X86_EFL_PF },
3142 { "cy", "nc", X86_EFL_CF },
3143 };
3144 char *psz = pszEFlags;
3145 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3146 {
3147 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3148 if (pszAdd)
3149 {
3150 strcpy(psz, pszAdd);
3151 psz += strlen(pszAdd);
3152 *psz++ = ' ';
3153 }
3154 }
3155 psz[-1] = '\0';
3156}
3157
3158
3159/**
3160 * Formats a full register dump.
3161 *
3162 * @param pVM Pointer to the VM.
3163 * @param pCtx The context to format.
3164 * @param pCtxCore The context core to format.
3165 * @param pHlp Output functions.
3166 * @param enmType The dump type.
3167 * @param pszPrefix Register name prefix.
3168 */
3169static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3170 const char *pszPrefix)
3171{
3172 NOREF(pVM);
3173
3174 /*
3175 * Format the EFLAGS.
3176 */
3177 uint32_t efl = pCtxCore->eflags.u32;
3178 char szEFlags[80];
3179 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3180
3181 /*
3182 * Format the registers.
3183 */
3184 switch (enmType)
3185 {
3186 case CPUMDUMPTYPE_TERSE:
3187 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3188 pHlp->pfnPrintf(pHlp,
3189 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3190 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3191 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3192 "%sr14=%016RX64 %sr15=%016RX64\n"
3193 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3194 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3195 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3196 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3197 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3198 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3199 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3200 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3201 else
3202 pHlp->pfnPrintf(pHlp,
3203 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3204 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3205 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3206 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3207 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3208 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3209 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3210 break;
3211
3212 case CPUMDUMPTYPE_DEFAULT:
3213 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3214 pHlp->pfnPrintf(pHlp,
3215 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3216 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3217 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3218 "%sr14=%016RX64 %sr15=%016RX64\n"
3219 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3220 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3221 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3222 ,
3223 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3224 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3225 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3226 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3227 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3228 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3229 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3230 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3231 else
3232 pHlp->pfnPrintf(pHlp,
3233 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3234 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3235 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3236 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3237 ,
3238 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3239 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3240 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3241 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3242 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3243 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3244 break;
3245
3246 case CPUMDUMPTYPE_VERBOSE:
3247 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3248 pHlp->pfnPrintf(pHlp,
3249 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3250 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3251 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3252 "%sr14=%016RX64 %sr15=%016RX64\n"
3253 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3254 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3255 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3256 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3257 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3258 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3259 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3260 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3261 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3262 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3263 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3264 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3265 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3266 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3267 ,
3268 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3269 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3270 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3271 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3272 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3273 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3274 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3275 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3276 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3277 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3278 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3279 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3280 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3281 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3282 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3283 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3284 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3285 else
3286 pHlp->pfnPrintf(pHlp,
3287 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3288 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3289 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3290 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3291 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3292 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3293 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3294 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3295 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3296 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3297 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3298 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3299 ,
3300 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3301 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3302 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3303 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3304 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3305 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3306 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3307 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3308 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3309 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3310 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3311 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3312
3313 pHlp->pfnPrintf(pHlp,
3314 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3315 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3316 ,
3317 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
3318 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
3319 pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
3320 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
3321 );
3322 unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
3323 for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
3324 {
3325 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
3326 unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
3327 char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
3328 unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
3329 uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
3330 unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
3331 /** @todo This isn't entirenly correct and needs more work! */
3332 pHlp->pfnPrintf(pHlp,
3333 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
3334 pszPrefix, iST, pszPrefix, iFPR,
3335 pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
3336 uTag, chSign, iInteger, u64Fraction, uExponent);
3337 if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
3338 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3339 pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
3340 else
3341 pHlp->pfnPrintf(pHlp, "\n");
3342 }
3343 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
3344 pHlp->pfnPrintf(pHlp,
3345 iXMM & 1
3346 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3347 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3348 pszPrefix, iXMM, iXMM < 10 ? " " : "",
3349 pCtx->fpu.aXMM[iXMM].au32[3],
3350 pCtx->fpu.aXMM[iXMM].au32[2],
3351 pCtx->fpu.aXMM[iXMM].au32[1],
3352 pCtx->fpu.aXMM[iXMM].au32[0]);
3353 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
3354 if (pCtx->fpu.au32RsrvdRest[i])
3355 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
3356 pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
3357
3358 pHlp->pfnPrintf(pHlp,
3359 "%sEFER =%016RX64\n"
3360 "%sPAT =%016RX64\n"
3361 "%sSTAR =%016RX64\n"
3362 "%sCSTAR =%016RX64\n"
3363 "%sLSTAR =%016RX64\n"
3364 "%sSFMASK =%016RX64\n"
3365 "%sKERNELGSBASE =%016RX64\n",
3366 pszPrefix, pCtx->msrEFER,
3367 pszPrefix, pCtx->msrPAT,
3368 pszPrefix, pCtx->msrSTAR,
3369 pszPrefix, pCtx->msrCSTAR,
3370 pszPrefix, pCtx->msrLSTAR,
3371 pszPrefix, pCtx->msrSFMASK,
3372 pszPrefix, pCtx->msrKERNELGSBASE);
3373 break;
3374 }
3375}
3376
3377
3378/**
3379 * Display all cpu states and any other cpum info.
3380 *
3381 * @param pVM Pointer to the VM.
3382 * @param pHlp The info helper functions.
3383 * @param pszArgs Arguments, ignored.
3384 */
3385static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3386{
3387 cpumR3InfoGuest(pVM, pHlp, pszArgs);
3388 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3389 cpumR3InfoHyper(pVM, pHlp, pszArgs);
3390 cpumR3InfoHost(pVM, pHlp, pszArgs);
3391}
3392
3393
3394/**
3395 * Parses the info argument.
3396 *
3397 * The argument starts with 'verbose', 'terse' or 'default' and then
3398 * continues with the comment string.
3399 *
3400 * @param pszArgs The pointer to the argument string.
3401 * @param penmType Where to store the dump type request.
3402 * @param ppszComment Where to store the pointer to the comment string.
3403 */
3404static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3405{
3406 if (!pszArgs)
3407 {
3408 *penmType = CPUMDUMPTYPE_DEFAULT;
3409 *ppszComment = "";
3410 }
3411 else
3412 {
3413 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3414 {
3415 pszArgs += 7;
3416 *penmType = CPUMDUMPTYPE_VERBOSE;
3417 }
3418 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3419 {
3420 pszArgs += 5;
3421 *penmType = CPUMDUMPTYPE_TERSE;
3422 }
3423 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3424 {
3425 pszArgs += 7;
3426 *penmType = CPUMDUMPTYPE_DEFAULT;
3427 }
3428 else
3429 *penmType = CPUMDUMPTYPE_DEFAULT;
3430 *ppszComment = RTStrStripL(pszArgs);
3431 }
3432}
3433
3434
3435/**
3436 * Display the guest cpu state.
3437 *
3438 * @param pVM Pointer to the VM.
3439 * @param pHlp The info helper functions.
3440 * @param pszArgs Arguments, ignored.
3441 */
3442static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3443{
3444 CPUMDUMPTYPE enmType;
3445 const char *pszComment;
3446 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3447
3448 /* @todo SMP support! */
3449 PVMCPU pVCpu = VMMGetCpu(pVM);
3450 if (!pVCpu)
3451 pVCpu = &pVM->aCpus[0];
3452
3453 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3454
3455 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3456 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3457}
3458
3459
3460/**
3461 * Display the current guest instruction
3462 *
3463 * @param pVM Pointer to the VM.
3464 * @param pHlp The info helper functions.
3465 * @param pszArgs Arguments, ignored.
3466 */
3467static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3468{
3469 NOREF(pszArgs);
3470
3471 /** @todo SMP support! */
3472 PVMCPU pVCpu = VMMGetCpu(pVM);
3473 if (!pVCpu)
3474 pVCpu = &pVM->aCpus[0];
3475
3476 char szInstruction[256];
3477 szInstruction[0] = '\0';
3478 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3479 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
3480}
3481
3482
3483/**
3484 * Display the hypervisor cpu state.
3485 *
3486 * @param pVM Pointer to the VM.
3487 * @param pHlp The info helper functions.
3488 * @param pszArgs Arguments, ignored.
3489 */
3490static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3491{
3492 CPUMDUMPTYPE enmType;
3493 const char *pszComment;
3494 /* @todo SMP */
3495 PVMCPU pVCpu = &pVM->aCpus[0];
3496
3497 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3498 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3499 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3500 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3501}
3502
3503
3504/**
3505 * Display the host cpu state.
3506 *
3507 * @param pVM Pointer to the VM.
3508 * @param pHlp The info helper functions.
3509 * @param pszArgs Arguments, ignored.
3510 */
3511static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3512{
3513 CPUMDUMPTYPE enmType;
3514 const char *pszComment;
3515 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3516 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3517
3518 /*
3519 * Format the EFLAGS.
3520 */
3521 /* @todo SMP */
3522 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
3523#if HC_ARCH_BITS == 32
3524 uint32_t efl = pCtx->eflags.u32;
3525#else
3526 uint64_t efl = pCtx->rflags;
3527#endif
3528 char szEFlags[80];
3529 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3530
3531 /*
3532 * Format the registers.
3533 */
3534#if HC_ARCH_BITS == 32
3535# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3536 if (!(pCtx->efer & MSR_K6_EFER_LMA))
3537# endif
3538 {
3539 pHlp->pfnPrintf(pHlp,
3540 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3541 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3542 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3543 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3544 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3545 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3546 ,
3547 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
3548 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3549 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3550 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
3551 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3552 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3553 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3554 }
3555# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3556 else
3557# endif
3558#endif
3559#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3560 {
3561 pHlp->pfnPrintf(pHlp,
3562 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3563 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3564 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3565 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3566 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3567 "r14=%016RX64 r15=%016RX64\n"
3568 "iopl=%d %31s\n"
3569 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3570 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3571 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
3572 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3573 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3574 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3575 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3576 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3577 ,
3578 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
3579 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3580 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
3581 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
3582 pCtx->r11, pCtx->r12, pCtx->r13,
3583 pCtx->r14, pCtx->r15,
3584 X86_EFL_GET_IOPL(efl), szEFlags,
3585 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3586 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
3587 pCtx->cr4, pCtx->ldtr, pCtx->tr,
3588 pCtx->dr0, pCtx->dr1, pCtx->dr2,
3589 pCtx->dr3, pCtx->dr6, pCtx->dr7,
3590 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3591 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3592 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3593 }
3594#endif
3595}
3596
3597
3598/**
3599 * Get L1 cache / TLS associativity.
3600 */
3601static const char *getCacheAss(unsigned u, char *pszBuf)
3602{
3603 if (u == 0)
3604 return "res0 ";
3605 if (u == 1)
3606 return "direct";
3607 if (u == 255)
3608 return "fully";
3609 if (u >= 256)
3610 return "???";
3611
3612 RTStrPrintf(pszBuf, 16, "%d way", u);
3613 return pszBuf;
3614}
3615
3616
3617/**
3618 * Get L2 cache associativity.
3619 */
3620const char *getL2CacheAss(unsigned u)
3621{
3622 switch (u)
3623 {
3624 case 0: return "off ";
3625 case 1: return "direct";
3626 case 2: return "2 way ";
3627 case 3: return "res3 ";
3628 case 4: return "4 way ";
3629 case 5: return "res5 ";
3630 case 6: return "8 way ";
3631 case 7: return "res7 ";
3632 case 8: return "16 way";
3633 case 9: return "res9 ";
3634 case 10: return "res10 ";
3635 case 11: return "res11 ";
3636 case 12: return "res12 ";
3637 case 13: return "res13 ";
3638 case 14: return "res14 ";
3639 case 15: return "fully ";
3640 default: return "????";
3641 }
3642}
3643
3644
3645/**
3646 * Display the guest CpuId leaves.
3647 *
3648 * @param pVM Pointer to the VM.
3649 * @param pHlp The info helper functions.
3650 * @param pszArgs "terse", "default" or "verbose".
3651 */
3652static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3653{
3654 /*
3655 * Parse the argument.
3656 */
3657 unsigned iVerbosity = 1;
3658 if (pszArgs)
3659 {
3660 pszArgs = RTStrStripL(pszArgs);
3661 if (!strcmp(pszArgs, "terse"))
3662 iVerbosity--;
3663 else if (!strcmp(pszArgs, "verbose"))
3664 iVerbosity++;
3665 }
3666
3667 /*
3668 * Start cracking.
3669 */
3670 CPUMCPUID Host;
3671 CPUMCPUID Guest;
3672 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
3673
3674 uint32_t cStdHstMax;
3675 uint32_t dummy;
3676 ASMCpuIdExSlow(0, 0, 0, 0, &cStdHstMax, &dummy, &dummy, &dummy);
3677
3678 unsigned cStdLstMax = RT_MAX(RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd), cStdHstMax);
3679
3680 pHlp->pfnPrintf(pHlp,
3681 " RAW Standard CPUIDs\n"
3682 " Function eax ebx ecx edx\n");
3683 for (unsigned i = 0; i <= cStdLstMax ; i++)
3684 {
3685 if (i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
3686 {
3687 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
3688 ASMCpuIdExSlow(i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3689
3690 pHlp->pfnPrintf(pHlp,
3691 "Gst: %08x %08x %08x %08x %08x%s\n"
3692 "Hst: %08x %08x %08x %08x\n",
3693 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3694 i <= cStdMax ? "" : "*",
3695 Host.eax, Host.ebx, Host.ecx, Host.edx);
3696 }
3697 else
3698 {
3699 ASMCpuIdExSlow(i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3700
3701 pHlp->pfnPrintf(pHlp,
3702 "Hst: %08x %08x %08x %08x %08x\n",
3703 i, Host.eax, Host.ebx, Host.ecx, Host.edx);
3704 }
3705 }
3706
3707 /*
3708 * If verbose, decode it.
3709 */
3710 if (iVerbosity)
3711 {
3712 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
3713 pHlp->pfnPrintf(pHlp,
3714 "Name: %.04s%.04s%.04s\n"
3715 "Supports: 0-%x\n",
3716 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3717 }
3718
3719 /*
3720 * Get Features.
3721 */
3722 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
3723 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
3724 pVM->cpum.s.aGuestCpuIdStd[0].edx);
3725 if (cStdMax >= 1 && iVerbosity)
3726 {
3727 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
3728
3729 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
3730 uint32_t uEAX = Guest.eax;
3731
3732 pHlp->pfnPrintf(pHlp,
3733 "Family: %d \tExtended: %d \tEffective: %d\n"
3734 "Model: %d \tExtended: %d \tEffective: %d\n"
3735 "Stepping: %d\n"
3736 "Type: %d (%s)\n"
3737 "APIC ID: %#04x\n"
3738 "Logical CPUs: %d\n"
3739 "CLFLUSH Size: %d\n"
3740 "Brand ID: %#04x\n",
3741 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3742 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3743 ASMGetCpuStepping(uEAX),
3744 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
3745 (Guest.ebx >> 24) & 0xff,
3746 (Guest.ebx >> 16) & 0xff,
3747 (Guest.ebx >> 8) & 0xff,
3748 (Guest.ebx >> 0) & 0xff);
3749 if (iVerbosity == 1)
3750 {
3751 uint32_t uEDX = Guest.edx;
3752 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3753 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3754 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3755 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3756 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3757 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3758 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3759 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3760 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3761 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3762 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3763 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3764 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
3765 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3766 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3767 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3768 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3769 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3770 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3771 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
3772 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
3773 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
3774 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
3775 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
3776 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3777 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3778 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
3779 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
3780 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
3781 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
3782 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
3783 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3784 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
3785 pHlp->pfnPrintf(pHlp, "\n");
3786
3787 uint32_t uECX = Guest.ecx;
3788 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3789 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
3790 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
3791 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
3792 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
3793 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
3794 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
3795 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
3796 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
3797 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
3798 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
3799 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
3800 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
3801 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
3802 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
3803 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
3804 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
3805 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
3806 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
3807 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
3808 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
3809 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
3810 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
3811 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
3812 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
3813 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
3814 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
3815 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
3816 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
3817 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
3818 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
3819 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3820 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " HVP");
3821 pHlp->pfnPrintf(pHlp, "\n");
3822 }
3823 else
3824 {
3825 ASMCpuIdExSlow(1, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3826
3827 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3828 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3829 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3830 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3831
3832 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3833 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3834 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3835 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3836 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3837 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3838 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3839 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3840 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3841 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3842 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3843 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3844 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3845 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3846 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3847 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3848 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3849 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3850 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3851 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3852 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3853 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3854 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3855 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3856 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3857 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3858 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3859 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3860 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3861 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3862 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3863 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3864 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3865
3866 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3867 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3868 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3869 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3870 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3871 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3872 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3873 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3874 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3875 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3876 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3877 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3878 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3879 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3880 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3881 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3882 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3883 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3884 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3885 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3886 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3887 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3888 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3889 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3890 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3891 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3892 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3893 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3894 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3895 pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3896 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3897 }
3898 }
3899 if (cStdMax >= 2 && iVerbosity)
3900 {
3901 /** @todo */
3902 }
3903
3904 /*
3905 * Extended.
3906 * Implemented after AMD specs.
3907 */
3908 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3909
3910 pHlp->pfnPrintf(pHlp,
3911 "\n"
3912 " RAW Extended CPUIDs\n"
3913 " Function eax ebx ecx edx\n");
3914 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3915 {
3916 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3917 ASMCpuIdExSlow(0x80000000 | i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3918
3919 pHlp->pfnPrintf(pHlp,
3920 "Gst: %08x %08x %08x %08x %08x%s\n"
3921 "Hst: %08x %08x %08x %08x\n",
3922 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3923 i <= cExtMax ? "" : "*",
3924 Host.eax, Host.ebx, Host.ecx, Host.edx);
3925 }
3926
3927 /*
3928 * Understandable output
3929 */
3930 if (iVerbosity)
3931 {
3932 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3933 pHlp->pfnPrintf(pHlp,
3934 "Ext Name: %.4s%.4s%.4s\n"
3935 "Ext Supports: 0x80000000-%#010x\n",
3936 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3937 }
3938
3939 if (iVerbosity && cExtMax >= 1)
3940 {
3941 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3942 uint32_t uEAX = Guest.eax;
3943 pHlp->pfnPrintf(pHlp,
3944 "Family: %d \tExtended: %d \tEffective: %d\n"
3945 "Model: %d \tExtended: %d \tEffective: %d\n"
3946 "Stepping: %d\n"
3947 "Brand ID: %#05x\n",
3948 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3949 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3950 ASMGetCpuStepping(uEAX),
3951 Guest.ebx & 0xfff);
3952
3953 if (iVerbosity == 1)
3954 {
3955 uint32_t uEDX = Guest.edx;
3956 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3957 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3958 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3959 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3960 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3961 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3962 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3963 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3964 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3965 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3966 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3967 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3968 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3969 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3970 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3971 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3972 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3973 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3974 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3975 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3976 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3977 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3978 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3979 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3980 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3981 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3982 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3983 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3984 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3985 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3986 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3987 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3988 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3989 pHlp->pfnPrintf(pHlp, "\n");
3990
3991 uint32_t uECX = Guest.ecx;
3992 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3993 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3994 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3995 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3996 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3997 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3998 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3999 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
4000 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
4001 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
4002 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
4003 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
4004 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
4005 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
4006 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
4007 for (unsigned iBit = 5; iBit < 32; iBit++)
4008 if (uECX & RT_BIT(iBit))
4009 pHlp->pfnPrintf(pHlp, " %d", iBit);
4010 pHlp->pfnPrintf(pHlp, "\n");
4011 }
4012 else
4013 {
4014 ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
4015
4016 uint32_t uEdxGst = Guest.edx;
4017 uint32_t uEdxHst = Host.edx;
4018 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
4019 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
4020 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
4021 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
4022 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
4023 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
4024 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
4025 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
4026 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
4027 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
4028 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
4029 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
4030 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
4031 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
4032 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
4033 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
4034 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
4035 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
4036 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
4037 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
4038 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
4039 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
4040 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
4041 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
4042 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
4043 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
4044 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
4045 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
4046 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
4047 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
4048 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
4049 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
4050 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
4051
4052 uint32_t uEcxGst = Guest.ecx;
4053 uint32_t uEcxHst = Host.ecx;
4054 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
4055 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
4056 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
4057 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
4058 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
4059 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
4060 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
4061 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
4062 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
4063 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
4064 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
4065 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
4066 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
4067 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
4068 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
4069 }
4070 }
4071
4072 if (iVerbosity && cExtMax >= 2)
4073 {
4074 char szString[4*4*3+1] = {0};
4075 uint32_t *pu32 = (uint32_t *)szString;
4076 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
4077 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
4078 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
4079 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
4080 if (cExtMax >= 3)
4081 {
4082 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
4083 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
4084 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
4085 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
4086 }
4087 if (cExtMax >= 4)
4088 {
4089 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
4090 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
4091 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
4092 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
4093 }
4094 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
4095 }
4096
4097 if (iVerbosity && cExtMax >= 5)
4098 {
4099 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
4100 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
4101 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
4102 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
4103 char sz1[32];
4104 char sz2[32];
4105
4106 pHlp->pfnPrintf(pHlp,
4107 "TLB 2/4M Instr/Uni: %s %3d entries\n"
4108 "TLB 2/4M Data: %s %3d entries\n",
4109 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
4110 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
4111 pHlp->pfnPrintf(pHlp,
4112 "TLB 4K Instr/Uni: %s %3d entries\n"
4113 "TLB 4K Data: %s %3d entries\n",
4114 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
4115 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
4116 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
4117 "L1 Instr Cache Lines Per Tag: %d\n"
4118 "L1 Instr Cache Associativity: %s\n"
4119 "L1 Instr Cache Size: %d KB\n",
4120 (uEDX >> 0) & 0xff,
4121 (uEDX >> 8) & 0xff,
4122 getCacheAss((uEDX >> 16) & 0xff, sz1),
4123 (uEDX >> 24) & 0xff);
4124 pHlp->pfnPrintf(pHlp,
4125 "L1 Data Cache Line Size: %d bytes\n"
4126 "L1 Data Cache Lines Per Tag: %d\n"
4127 "L1 Data Cache Associativity: %s\n"
4128 "L1 Data Cache Size: %d KB\n",
4129 (uECX >> 0) & 0xff,
4130 (uECX >> 8) & 0xff,
4131 getCacheAss((uECX >> 16) & 0xff, sz1),
4132 (uECX >> 24) & 0xff);
4133 }
4134
4135 if (iVerbosity && cExtMax >= 6)
4136 {
4137 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
4138 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
4139 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
4140
4141 pHlp->pfnPrintf(pHlp,
4142 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
4143 "L2 TLB 2/4M Data: %s %4d entries\n",
4144 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
4145 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
4146 pHlp->pfnPrintf(pHlp,
4147 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
4148 "L2 TLB 4K Data: %s %4d entries\n",
4149 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
4150 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
4151 pHlp->pfnPrintf(pHlp,
4152 "L2 Cache Line Size: %d bytes\n"
4153 "L2 Cache Lines Per Tag: %d\n"
4154 "L2 Cache Associativity: %s\n"
4155 "L2 Cache Size: %d KB\n",
4156 (uEDX >> 0) & 0xff,
4157 (uEDX >> 8) & 0xf,
4158 getL2CacheAss((uEDX >> 12) & 0xf),
4159 (uEDX >> 16) & 0xffff);
4160 }
4161
4162 if (iVerbosity && cExtMax >= 7)
4163 {
4164 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
4165
4166 pHlp->pfnPrintf(pHlp, "APM Features: ");
4167 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
4168 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
4169 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
4170 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
4171 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
4172 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
4173 for (unsigned iBit = 6; iBit < 32; iBit++)
4174 if (uEDX & RT_BIT(iBit))
4175 pHlp->pfnPrintf(pHlp, " %d", iBit);
4176 pHlp->pfnPrintf(pHlp, "\n");
4177 }
4178
4179 if (iVerbosity && cExtMax >= 8)
4180 {
4181 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
4182 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
4183
4184 pHlp->pfnPrintf(pHlp,
4185 "Physical Address Width: %d bits\n"
4186 "Virtual Address Width: %d bits\n"
4187 "Guest Physical Address Width: %d bits\n",
4188 (uEAX >> 0) & 0xff,
4189 (uEAX >> 8) & 0xff,
4190 (uEAX >> 16) & 0xff);
4191 pHlp->pfnPrintf(pHlp,
4192 "Physical Core Count: %d\n",
4193 (uECX >> 0) & 0xff);
4194 }
4195
4196
4197 /*
4198 * Centaur.
4199 */
4200 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
4201
4202 pHlp->pfnPrintf(pHlp,
4203 "\n"
4204 " RAW Centaur CPUIDs\n"
4205 " Function eax ebx ecx edx\n");
4206 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
4207 {
4208 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
4209 ASMCpuIdExSlow(0xc0000000 | i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
4210
4211 pHlp->pfnPrintf(pHlp,
4212 "Gst: %08x %08x %08x %08x %08x%s\n"
4213 "Hst: %08x %08x %08x %08x\n",
4214 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
4215 i <= cCentaurMax ? "" : "*",
4216 Host.eax, Host.ebx, Host.ecx, Host.edx);
4217 }
4218
4219 /*
4220 * Understandable output
4221 */
4222 if (iVerbosity)
4223 {
4224 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
4225 pHlp->pfnPrintf(pHlp,
4226 "Centaur Supports: 0xc0000000-%#010x\n",
4227 Guest.eax);
4228 }
4229
4230 if (iVerbosity && cCentaurMax >= 1)
4231 {
4232 ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
4233 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdCentaur[1].edx;
4234 uint32_t uEdxHst = Host.edx;
4235
4236 if (iVerbosity == 1)
4237 {
4238 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
4239 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
4240 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
4241 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
4242 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
4243 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
4244 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
4245 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
4246 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
4247 /* possibly indicating MM/HE and MM/HE-E on older chips... */
4248 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
4249 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
4250 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
4251 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
4252 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
4253 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
4254 for (unsigned iBit = 14; iBit < 32; iBit++)
4255 if (uEdxGst & RT_BIT(iBit))
4256 pHlp->pfnPrintf(pHlp, " %d", iBit);
4257 pHlp->pfnPrintf(pHlp, "\n");
4258 }
4259 else
4260 {
4261 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
4262 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
4263 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
4264 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
4265 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
4266 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
4267 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
4268 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
4269 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
4270 /* possibly indicating MM/HE and MM/HE-E on older chips... */
4271 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
4272 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
4273 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
4274 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
4275 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
4276 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
4277 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
4278 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
4279 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
4280 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
4281 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
4282 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
4283 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
4284 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
4285 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
4286 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
4287 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
4288 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
4289 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
4290 for (unsigned iBit = 27; iBit < 32; iBit++)
4291 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
4292 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
4293 pHlp->pfnPrintf(pHlp, "\n");
4294 }
4295 }
4296}
4297
4298
4299/**
4300 * Structure used when disassembling and instructions in DBGF.
4301 * This is used so the reader function can get the stuff it needs.
4302 */
4303typedef struct CPUMDISASSTATE
4304{
4305 /** Pointer to the CPU structure. */
4306 PDISCPUSTATE pCpu;
4307 /** Pointer to the VM. */
4308 PVM pVM;
4309 /** Pointer to the VMCPU. */
4310 PVMCPU pVCpu;
4311 /** Pointer to the first byte in the segment. */
4312 RTGCUINTPTR GCPtrSegBase;
4313 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
4314 RTGCUINTPTR GCPtrSegEnd;
4315 /** The size of the segment minus 1. */
4316 RTGCUINTPTR cbSegLimit;
4317 /** Pointer to the current page - R3 Ptr. */
4318 void const *pvPageR3;
4319 /** Pointer to the current page - GC Ptr. */
4320 RTGCPTR pvPageGC;
4321 /** The lock information that PGMPhysReleasePageMappingLock needs. */
4322 PGMPAGEMAPLOCK PageMapLock;
4323 /** Whether the PageMapLock is valid or not. */
4324 bool fLocked;
4325 /** 64 bits mode or not. */
4326 bool f64Bits;
4327} CPUMDISASSTATE, *PCPUMDISASSTATE;
4328
4329
4330/**
4331 * @callback_method_impl{FNDISREADBYTES}
4332 */
4333static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4334{
4335 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4336 for (;;)
4337 {
4338 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4339
4340 /*
4341 * Need to update the page translation?
4342 */
4343 if ( !pState->pvPageR3
4344 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4345 {
4346 int rc = VINF_SUCCESS;
4347
4348 /* translate the address */
4349 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4350 if ( !HMIsEnabled(pState->pVM)
4351 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
4352 {
4353 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
4354 if (!pState->pvPageR3)
4355 rc = VERR_INVALID_POINTER;
4356 }
4357 else
4358 {
4359 /* Release mapping lock previously acquired. */
4360 if (pState->fLocked)
4361 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4362 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4363 pState->fLocked = RT_SUCCESS_NP(rc);
4364 }
4365 if (RT_FAILURE(rc))
4366 {
4367 pState->pvPageR3 = NULL;
4368 return rc;
4369 }
4370 }
4371
4372 /*
4373 * Check the segment limit.
4374 */
4375 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4376 return VERR_OUT_OF_SELECTOR_BOUNDS;
4377
4378 /*
4379 * Calc how much we can read.
4380 */
4381 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4382 if (!pState->f64Bits)
4383 {
4384 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4385 if (cb > cbSeg && cbSeg)
4386 cb = cbSeg;
4387 }
4388 if (cb > cbMaxRead)
4389 cb = cbMaxRead;
4390
4391 /*
4392 * Read and advance or exit.
4393 */
4394 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4395 offInstr += (uint8_t)cb;
4396 if (cb >= cbMinRead)
4397 {
4398 pDis->cbCachedInstr = offInstr;
4399 return VINF_SUCCESS;
4400 }
4401 cbMinRead -= (uint8_t)cb;
4402 cbMaxRead -= (uint8_t)cb;
4403 }
4404}
4405
4406
4407/**
4408 * Disassemble an instruction and return the information in the provided structure.
4409 *
4410 * @returns VBox status code.
4411 * @param pVM Pointer to the VM.
4412 * @param pVCpu Pointer to the VMCPU.
4413 * @param pCtx Pointer to the guest CPU context.
4414 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4415 * @param pCpu Disassembly state.
4416 * @param pszPrefix String prefix for logging (debug only).
4417 *
4418 */
4419VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
4420{
4421 CPUMDISASSTATE State;
4422 int rc;
4423
4424 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4425 State.pCpu = pCpu;
4426 State.pvPageGC = 0;
4427 State.pvPageR3 = NULL;
4428 State.pVM = pVM;
4429 State.pVCpu = pVCpu;
4430 State.fLocked = false;
4431 State.f64Bits = false;
4432
4433 /*
4434 * Get selector information.
4435 */
4436 DISCPUMODE enmDisCpuMode;
4437 if ( (pCtx->cr0 & X86_CR0_PE)
4438 && pCtx->eflags.Bits.u1VM == 0)
4439 {
4440 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4441 {
4442# ifdef VBOX_WITH_RAW_MODE_NOT_R0
4443 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4444# endif
4445 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4446 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4447 }
4448 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4449 State.GCPtrSegBase = pCtx->cs.u64Base;
4450 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4451 State.cbSegLimit = pCtx->cs.u32Limit;
4452 enmDisCpuMode = (State.f64Bits)
4453 ? DISCPUMODE_64BIT
4454 : pCtx->cs.Attr.n.u1DefBig
4455 ? DISCPUMODE_32BIT
4456 : DISCPUMODE_16BIT;
4457 }
4458 else
4459 {
4460 /* real or V86 mode */
4461 enmDisCpuMode = DISCPUMODE_16BIT;
4462 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4463 State.GCPtrSegEnd = 0xFFFFFFFF;
4464 State.cbSegLimit = 0xFFFFFFFF;
4465 }
4466
4467 /*
4468 * Disassemble the instruction.
4469 */
4470 uint32_t cbInstr;
4471#ifndef LOG_ENABLED
4472 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4473 if (RT_SUCCESS(rc))
4474 {
4475#else
4476 char szOutput[160];
4477 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4478 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4479 if (RT_SUCCESS(rc))
4480 {
4481 /* log it */
4482 if (pszPrefix)
4483 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4484 else
4485 Log(("%s", szOutput));
4486#endif
4487 rc = VINF_SUCCESS;
4488 }
4489 else
4490 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4491
4492 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4493 if (State.fLocked)
4494 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4495
4496 return rc;
4497}
4498
4499
4500
4501/**
4502 * API for controlling a few of the CPU features found in CR4.
4503 *
4504 * Currently only X86_CR4_TSD is accepted as input.
4505 *
4506 * @returns VBox status code.
4507 *
4508 * @param pVM Pointer to the VM.
4509 * @param fOr The CR4 OR mask.
4510 * @param fAnd The CR4 AND mask.
4511 */
4512VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4513{
4514 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4515 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4516
4517 pVM->cpum.s.CR4.OrMask &= fAnd;
4518 pVM->cpum.s.CR4.OrMask |= fOr;
4519
4520 return VINF_SUCCESS;
4521}
4522
4523
4524/**
4525 * Gets a pointer to the array of standard CPUID leaves.
4526 *
4527 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
4528 *
4529 * @returns Pointer to the standard CPUID leaves (read-only).
4530 * @param pVM Pointer to the VM.
4531 * @remark Intended for PATM.
4532 */
4533VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
4534{
4535 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
4536}
4537
4538
4539/**
4540 * Gets a pointer to the array of extended CPUID leaves.
4541 *
4542 * CPUMGetGuestCpuIdExtMax() give the size of the array.
4543 *
4544 * @returns Pointer to the extended CPUID leaves (read-only).
4545 * @param pVM Pointer to the VM.
4546 * @remark Intended for PATM.
4547 */
4548VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
4549{
4550 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
4551}
4552
4553
4554/**
4555 * Gets a pointer to the array of centaur CPUID leaves.
4556 *
4557 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
4558 *
4559 * @returns Pointer to the centaur CPUID leaves (read-only).
4560 * @param pVM Pointer to the VM.
4561 * @remark Intended for PATM.
4562 */
4563VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
4564{
4565 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
4566}
4567
4568
4569/**
4570 * Gets a pointer to the default CPUID leaf.
4571 *
4572 * @returns Pointer to the default CPUID leaf (read-only).
4573 * @param pVM Pointer to the VM.
4574 * @remark Intended for PATM.
4575 */
4576VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
4577{
4578 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
4579}
4580
4581
4582/**
4583 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4584 *
4585 * Only REM should ever call this function!
4586 *
4587 * @returns The changed flags.
4588 * @param pVCpu Pointer to the VMCPU.
4589 * @param puCpl Where to return the current privilege level (CPL).
4590 */
4591VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4592{
4593 Assert(!pVCpu->cpum.s.fRawEntered);
4594 Assert(!pVCpu->cpum.s.fRemEntered);
4595
4596 /*
4597 * Get the CPL first.
4598 */
4599 *puCpl = CPUMGetGuestCPL(pVCpu);
4600
4601 /*
4602 * Get and reset the flags.
4603 */
4604 uint32_t fFlags = pVCpu->cpum.s.fChanged;
4605 pVCpu->cpum.s.fChanged = 0;
4606
4607 /** @todo change the switcher to use the fChanged flags. */
4608 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4609 {
4610 fFlags |= CPUM_CHANGED_FPU_REM;
4611 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4612 }
4613
4614 pVCpu->cpum.s.fRemEntered = true;
4615 return fFlags;
4616}
4617
4618
4619/**
4620 * Leaves REM.
4621 *
4622 * @param pVCpu Pointer to the VMCPU.
4623 * @param fNoOutOfSyncSels This is @c false if there are out of sync
4624 * registers.
4625 */
4626VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4627{
4628 Assert(!pVCpu->cpum.s.fRawEntered);
4629 Assert(pVCpu->cpum.s.fRemEntered);
4630
4631 pVCpu->cpum.s.fRemEntered = false;
4632}
4633
4634
4635/**
4636 * Called when the ring-3 init phase completes.
4637 *
4638 * @returns VBox status code.
4639 * @param pVM Pointer to the VM.
4640 */
4641VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
4642{
4643 for (VMCPUID i = 0; i < pVM->cCpus; i++)
4644 {
4645 /* Cache the APIC base (from the APIC device) once it has been initialized. */
4646 PDMApicGetBase(&pVM->aCpus[i], &pVM->aCpus[i].cpum.s.Guest.msrApicBase);
4647 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVM->aCpus[i].cpum.s.Guest.msrApicBase));
4648 }
4649 return VINF_SUCCESS;
4650}
4651
4652/**
4653 * Called when the ring-0 init phases comleted.
4654 *
4655 * @param pVM Pointer to the VM.
4656 */
4657VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
4658{
4659 /*
4660 * Log the cpuid.
4661 */
4662 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
4663 RTCPUSET OnlineSet;
4664 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4665 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4666 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4667 RTCPUID cCores = RTMpGetCoreCount();
4668 if (cCores)
4669 LogRel(("Physical host cores: %u\n", (unsigned)cCores));
4670 LogRel(("************************* CPUID dump ************************\n"));
4671 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4672 LogRel(("\n"));
4673 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
4674 RTLogRelSetBuffering(fOldBuffered);
4675 LogRel(("******************** End of CPUID dump **********************\n"));
4676}
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