VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 42504

Last change on this file since 42504 was 42504, checked in by vboxsync, 13 years ago

VMM/VMMR3/CPUMR3: VIA CpuId comments.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 211.0 KB
Line 
1/* $Id: CPUM.cpp 42504 2012-08-01 12:35:11Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/mm.h>
43#include <VBox/vmm/selm.h>
44#include <VBox/vmm/dbgf.h>
45#include <VBox/vmm/patm.h>
46#include <VBox/vmm/hwaccm.h>
47#include <VBox/vmm/ssm.h>
48#include "CPUMInternal.h"
49#include <VBox/vmm/vm.h>
50
51#include <VBox/param.h>
52#include <VBox/dis.h>
53#include <VBox/err.h>
54#include <VBox/log.h>
55#include <iprt/assert.h>
56#include <iprt/asm-amd64-x86.h>
57#include <iprt/string.h>
58#include <iprt/mp.h>
59#include <iprt/cpuset.h>
60#include "internal/pgm.h"
61
62
63/*******************************************************************************
64* Defined Constants And Macros *
65*******************************************************************************/
66/** The current saved state version. */
67#define CPUM_SAVED_STATE_VERSION 14
68/** The current saved state version before using SSMR3PutStruct. */
69#define CPUM_SAVED_STATE_VERSION_MEM 13
70/** The saved state version before introducing the MSR size field. */
71#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
72/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
73 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
74#define CPUM_SAVED_STATE_VERSION_VER3_2 11
75/** The saved state version of 3.0 and 3.1 trunk before the teleportation
76 * changes. */
77#define CPUM_SAVED_STATE_VERSION_VER3_0 10
78/** The saved state version for the 2.1 trunk before the MSR changes. */
79#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
80/** The saved state version of 2.0, used for backwards compatibility. */
81#define CPUM_SAVED_STATE_VERSION_VER2_0 8
82/** The saved state version of 1.6, used for backwards compatibility. */
83#define CPUM_SAVED_STATE_VERSION_VER1_6 6
84
85
86/**
87 * This was used in the saved state up to the early life of version 14.
88 *
89 * It indicates that we may have some out-of-sync hidden segement registers.
90 * It is only relevant for raw-mode.
91 */
92#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
93
94
95/*******************************************************************************
96* Structures and Typedefs *
97*******************************************************************************/
98
99/**
100 * What kind of cpu info dump to perform.
101 */
102typedef enum CPUMDUMPTYPE
103{
104 CPUMDUMPTYPE_TERSE,
105 CPUMDUMPTYPE_DEFAULT,
106 CPUMDUMPTYPE_VERBOSE
107} CPUMDUMPTYPE;
108/** Pointer to a cpu info dump type. */
109typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
110
111
112/*******************************************************************************
113* Internal Functions *
114*******************************************************************************/
115static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
116static int cpumR3CpuIdInit(PVM pVM);
117static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
118static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
119static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
120static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
121static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
122static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
123static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
124static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128
129
130/*******************************************************************************
131* Global Variables *
132*******************************************************************************/
133/** Saved state field descriptors for CPUMCTX. */
134static const SSMFIELD g_aCpumCtxFields[] =
135{
136 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
137 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
138 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
139 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
140 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
141 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
142 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
143 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
144 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
145 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
146 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
147 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
148 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
149 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
150 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
151 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
152 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
153 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
154 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
155 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
156 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
157 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
158 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
159 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
160 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
161 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
162 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
163 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
164 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
165 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
166 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
167 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
168 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
169 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
170 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
171 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
172 SSMFIELD_ENTRY( CPUMCTX, rdi),
173 SSMFIELD_ENTRY( CPUMCTX, rsi),
174 SSMFIELD_ENTRY( CPUMCTX, rbp),
175 SSMFIELD_ENTRY( CPUMCTX, rax),
176 SSMFIELD_ENTRY( CPUMCTX, rbx),
177 SSMFIELD_ENTRY( CPUMCTX, rdx),
178 SSMFIELD_ENTRY( CPUMCTX, rcx),
179 SSMFIELD_ENTRY( CPUMCTX, rsp),
180 SSMFIELD_ENTRY( CPUMCTX, rflags),
181 SSMFIELD_ENTRY( CPUMCTX, rip),
182 SSMFIELD_ENTRY( CPUMCTX, r8),
183 SSMFIELD_ENTRY( CPUMCTX, r9),
184 SSMFIELD_ENTRY( CPUMCTX, r10),
185 SSMFIELD_ENTRY( CPUMCTX, r11),
186 SSMFIELD_ENTRY( CPUMCTX, r12),
187 SSMFIELD_ENTRY( CPUMCTX, r13),
188 SSMFIELD_ENTRY( CPUMCTX, r14),
189 SSMFIELD_ENTRY( CPUMCTX, r15),
190 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
191 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
192 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
193 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
194 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
195 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
196 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
197 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
198 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
199 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
200 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
201 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
202 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
203 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
204 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
205 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
206 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
207 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
208 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
209 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
210 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
211 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
212 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
213 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
214 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
215 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
216 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
217 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
218 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
219 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
220 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
221 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
222 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
223 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
224 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
225 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
226 SSMFIELD_ENTRY( CPUMCTX, cr0),
227 SSMFIELD_ENTRY( CPUMCTX, cr2),
228 SSMFIELD_ENTRY( CPUMCTX, cr3),
229 SSMFIELD_ENTRY( CPUMCTX, cr4),
230 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
231 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
232 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
233 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
234 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
235 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
236 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
237 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
238 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
239 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
240 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
241 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
242 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
243 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
244 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
245 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
246 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
247 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
248 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
249 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
250 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
251 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
252 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
253 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
254 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
255 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
256 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
257 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
258 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
259 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
260 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
261 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
262 SSMFIELD_ENTRY_TERM()
263};
264
265/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
266 * registeres changed. */
267static const SSMFIELD g_aCpumCtxFieldsMem[] =
268{
269 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
270 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
271 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
272 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
273 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
274 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
275 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
276 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
277 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
278 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
279 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
280 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
281 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
282 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
283 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
284 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
285 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
286 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
287 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
288 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
289 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
290 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
291 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
292 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
293 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
294 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
295 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
296 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
297 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
298 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
299 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
300 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
301 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
302 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
303 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
304 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
305 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
306 SSMFIELD_ENTRY( CPUMCTX, rdi),
307 SSMFIELD_ENTRY( CPUMCTX, rsi),
308 SSMFIELD_ENTRY( CPUMCTX, rbp),
309 SSMFIELD_ENTRY( CPUMCTX, rax),
310 SSMFIELD_ENTRY( CPUMCTX, rbx),
311 SSMFIELD_ENTRY( CPUMCTX, rdx),
312 SSMFIELD_ENTRY( CPUMCTX, rcx),
313 SSMFIELD_ENTRY( CPUMCTX, rsp),
314 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
315 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
316 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
317 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
318 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
319 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
320 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
321 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
322 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
323 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
324 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
325 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
326 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
327 SSMFIELD_ENTRY( CPUMCTX, rflags),
328 SSMFIELD_ENTRY( CPUMCTX, rip),
329 SSMFIELD_ENTRY( CPUMCTX, r8),
330 SSMFIELD_ENTRY( CPUMCTX, r9),
331 SSMFIELD_ENTRY( CPUMCTX, r10),
332 SSMFIELD_ENTRY( CPUMCTX, r11),
333 SSMFIELD_ENTRY( CPUMCTX, r12),
334 SSMFIELD_ENTRY( CPUMCTX, r13),
335 SSMFIELD_ENTRY( CPUMCTX, r14),
336 SSMFIELD_ENTRY( CPUMCTX, r15),
337 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
338 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
339 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
340 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
341 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
342 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
343 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
344 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
345 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
346 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
347 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
348 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
349 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
350 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
351 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
352 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
353 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
354 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
355 SSMFIELD_ENTRY( CPUMCTX, cr0),
356 SSMFIELD_ENTRY( CPUMCTX, cr2),
357 SSMFIELD_ENTRY( CPUMCTX, cr3),
358 SSMFIELD_ENTRY( CPUMCTX, cr4),
359 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
360 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
361 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
362 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
363 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
364 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
365 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
366 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
367 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
368 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
369 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
370 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
371 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
372 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
373 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
374 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
375 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
376 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
377 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
378 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
379 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
380 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
381 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
382 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
383 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
384 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
385 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
386 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
387 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
388 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
389 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
390 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
391 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
392 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
393 SSMFIELD_ENTRY_TERM()
394};
395
396/** Saved state field descriptors for CPUMCTX_VER1_6. */
397static const SSMFIELD g_aCpumCtxFieldsV16[] =
398{
399 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
400 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
401 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
402 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
403 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
404 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
405 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
406 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
407 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
408 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
409 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
410 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
411 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
412 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
413 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
414 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
415 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
416 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
417 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
418 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
419 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
420 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
421 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
422 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
423 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
424 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
425 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
426 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
427 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
428 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
429 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
430 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
431 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
432 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
433 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
434 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
435 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
436 SSMFIELD_ENTRY( CPUMCTX, rdi),
437 SSMFIELD_ENTRY( CPUMCTX, rsi),
438 SSMFIELD_ENTRY( CPUMCTX, rbp),
439 SSMFIELD_ENTRY( CPUMCTX, rax),
440 SSMFIELD_ENTRY( CPUMCTX, rbx),
441 SSMFIELD_ENTRY( CPUMCTX, rdx),
442 SSMFIELD_ENTRY( CPUMCTX, rcx),
443 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
444 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
445 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
446 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
447 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
448 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
449 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
450 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
451 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
452 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
453 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
454 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
455 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
456 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
457 SSMFIELD_ENTRY( CPUMCTX, rflags),
458 SSMFIELD_ENTRY( CPUMCTX, rip),
459 SSMFIELD_ENTRY( CPUMCTX, r8),
460 SSMFIELD_ENTRY( CPUMCTX, r9),
461 SSMFIELD_ENTRY( CPUMCTX, r10),
462 SSMFIELD_ENTRY( CPUMCTX, r11),
463 SSMFIELD_ENTRY( CPUMCTX, r12),
464 SSMFIELD_ENTRY( CPUMCTX, r13),
465 SSMFIELD_ENTRY( CPUMCTX, r14),
466 SSMFIELD_ENTRY( CPUMCTX, r15),
467 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
468 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
469 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
470 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
471 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
472 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
473 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
474 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
475 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
476 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
477 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
478 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
479 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
480 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
481 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
482 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
483 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
484 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
485 SSMFIELD_ENTRY( CPUMCTX, cr0),
486 SSMFIELD_ENTRY( CPUMCTX, cr2),
487 SSMFIELD_ENTRY( CPUMCTX, cr3),
488 SSMFIELD_ENTRY( CPUMCTX, cr4),
489 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
490 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
491 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
492 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
493 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
494 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
495 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
496 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
497 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
498 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
499 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
500 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
501 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
502 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
503 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
504 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
505 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
506 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
507 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
508 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
509 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
510 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
511 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
512 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
513 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
514 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
515 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
516 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
517 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
519 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
520 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
521 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
522 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
523 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
524 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
525 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
526 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
527 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
528 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
529 SSMFIELD_ENTRY_TERM()
530};
531
532
533/**
534 * Initializes the CPUM.
535 *
536 * @returns VBox status code.
537 * @param pVM Pointer to the VM.
538 */
539VMMR3DECL(int) CPUMR3Init(PVM pVM)
540{
541 LogFlow(("CPUMR3Init\n"));
542
543 /*
544 * Assert alignment and sizes.
545 */
546 AssertCompileMemberAlignment(VM, cpum.s, 32);
547 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
548 AssertCompileSizeAlignment(CPUMCTX, 64);
549 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
550 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
551 AssertCompileMemberAlignment(VM, cpum, 64);
552 AssertCompileMemberAlignment(VM, aCpus, 64);
553 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
554 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
555
556 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
557 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
558 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
559
560 /* Calculate the offset from CPUMCPU to CPUM. */
561 for (VMCPUID i = 0; i < pVM->cCpus; i++)
562 {
563 PVMCPU pVCpu = &pVM->aCpus[i];
564
565 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
566 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
567 }
568
569 /*
570 * Check that the CPU supports the minimum features we require.
571 */
572 if (!ASMHasCpuId())
573 {
574 Log(("The CPU doesn't support CPUID!\n"));
575 return VERR_UNSUPPORTED_CPU;
576 }
577 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
578 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
579
580 /* Setup the CR4 AND and OR masks used in the switcher */
581 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
582 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
583 {
584 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
585 /* No FXSAVE implies no SSE */
586 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
587 pVM->cpum.s.CR4.OrMask = 0;
588 }
589 else
590 {
591 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
592 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
593 }
594
595 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
596 {
597 Log(("The CPU doesn't support MMX!\n"));
598 return VERR_UNSUPPORTED_CPU;
599 }
600 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
601 {
602 Log(("The CPU doesn't support TSC!\n"));
603 return VERR_UNSUPPORTED_CPU;
604 }
605 /* Bogus on AMD? */
606 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
607 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
608
609 /*
610 * Detect the host CPU vendor.
611 * (The guest CPU vendor is re-detected later on.)
612 */
613 uint32_t uEAX, uEBX, uECX, uEDX;
614 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
615 pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
616 pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
617
618 /*
619 * Setup hypervisor startup values.
620 */
621
622 /*
623 * Register saved state data item.
624 */
625 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
626 NULL, cpumR3LiveExec, NULL,
627 NULL, cpumR3SaveExec, NULL,
628 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
629 if (RT_FAILURE(rc))
630 return rc;
631
632 /*
633 * Register info handlers and registers with the debugger facility.
634 */
635 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
636 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
637 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
638 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
639 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
640 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
641
642 rc = cpumR3DbgInit(pVM);
643 if (RT_FAILURE(rc))
644 return rc;
645
646 /*
647 * Initialize the Guest CPUID state.
648 */
649 rc = cpumR3CpuIdInit(pVM);
650 if (RT_FAILURE(rc))
651 return rc;
652 CPUMR3Reset(pVM);
653 return VINF_SUCCESS;
654}
655
656
657/**
658 * Detect the CPU vendor give n the
659 *
660 * @returns The vendor.
661 * @param uEAX EAX from CPUID(0).
662 * @param uEBX EBX from CPUID(0).
663 * @param uECX ECX from CPUID(0).
664 * @param uEDX EDX from CPUID(0).
665 */
666static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
667{
668 if ( uEAX >= 1
669 && uEBX == X86_CPUID_VENDOR_AMD_EBX
670 && uECX == X86_CPUID_VENDOR_AMD_ECX
671 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
672 return CPUMCPUVENDOR_AMD;
673
674 if ( uEAX >= 1
675 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
676 && uECX == X86_CPUID_VENDOR_INTEL_ECX
677 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
678 return CPUMCPUVENDOR_INTEL;
679
680 if ( uEAX >= 1
681 && uEBX == X86_CPUID_VENDOR_VIA_EBX
682 && uECX == X86_CPUID_VENDOR_VIA_ECX
683 && uEDX == X86_CPUID_VENDOR_VIA_EDX)
684 return CPUMCPUVENDOR_VIA;
685
686 /** @todo detect the other buggers... */
687 return CPUMCPUVENDOR_UNKNOWN;
688}
689
690
691/**
692 * Fetches overrides for a CPUID leaf.
693 *
694 * @returns VBox status code.
695 * @param pLeaf The leaf to load the overrides into.
696 * @param pCfgNode The CFGM node containing the overrides
697 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
698 * @param iLeaf The CPUID leaf number.
699 */
700static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
701{
702 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
703 if (pLeafNode)
704 {
705 uint32_t u32;
706 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
707 if (RT_SUCCESS(rc))
708 pLeaf->eax = u32;
709 else
710 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
711
712 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
713 if (RT_SUCCESS(rc))
714 pLeaf->ebx = u32;
715 else
716 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
717
718 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
719 if (RT_SUCCESS(rc))
720 pLeaf->ecx = u32;
721 else
722 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
723
724 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
725 if (RT_SUCCESS(rc))
726 pLeaf->edx = u32;
727 else
728 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
729
730 }
731 return VINF_SUCCESS;
732}
733
734
735/**
736 * Load the overrides for a set of CPUID leaves.
737 *
738 * @returns VBox status code.
739 * @param paLeaves The leaf array.
740 * @param cLeaves The number of leaves.
741 * @param uStart The start leaf number.
742 * @param pCfgNode The CFGM node containing the overrides
743 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
744 */
745static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
746{
747 for (uint32_t i = 0; i < cLeaves; i++)
748 {
749 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
750 if (RT_FAILURE(rc))
751 return rc;
752 }
753
754 return VINF_SUCCESS;
755}
756
757/**
758 * Init a set of host CPUID leaves.
759 *
760 * @returns VBox status code.
761 * @param paLeaves The leaf array.
762 * @param cLeaves The number of leaves.
763 * @param uStart The start leaf number.
764 * @param pCfgNode The /CPUM/HostCPUID/ node.
765 */
766static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
767{
768 /* Using the ECX variant for all of them can't hurt... */
769 for (uint32_t i = 0; i < cLeaves; i++)
770 ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
771
772 /* Load CPUID leaf override; we currently don't care if the user
773 specifies features the host CPU doesn't support. */
774 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
775}
776
777
778/**
779 * Initializes the emulated CPU's cpuid information.
780 *
781 * @returns VBox status code.
782 * @param pVM Pointer to the VM.
783 */
784static int cpumR3CpuIdInit(PVM pVM)
785{
786 PCPUM pCPUM = &pVM->cpum.s;
787 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
788 uint32_t i;
789 int rc;
790
791#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
792 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
793 { \
794 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
795 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
796 }
797#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
798 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
799 { \
800 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
801 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
802 }
803
804 /*
805 * Read the configuration.
806 */
807 /** @cfgm{CPUM/SyntheticCpu, boolean, false}
808 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
809 * completely overridden by VirtualBox custom strings. Some
810 * CPUID information is withheld, like the cache info. */
811 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
812 AssertRCReturn(rc, rc);
813
814 /** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
815 * When non-zero CPUID features that could cause portability issues will be
816 * stripped. The higher the value the more features gets stripped. Higher
817 * values should only be used when older CPUs are involved since it may
818 * harm performance and maybe also cause problems with specific guests. */
819 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
820 AssertRCReturn(rc, rc);
821
822 AssertLogRelReturn(!pCPUM->fSyntheticCpu || !pCPUM->u8PortableCpuIdLevel, VERR_CPUM_INCOMPATIBLE_CONFIG);
823
824 /*
825 * Get the host CPUID leaves and redetect the guest CPU vendor (could've
826 * been overridden).
827 */
828 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
829 * Overrides the host CPUID leaf values used for calculating the guest CPUID
830 * leaves. This can be used to preserve the CPUID values when moving a VM to a
831 * different machine. Another use is restricting (or extending) the feature set
832 * exposed to the guest. */
833 PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
834 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
835 AssertRCReturn(rc, rc);
836 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
837 AssertRCReturn(rc, rc);
838 rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
839 AssertRCReturn(rc, rc);
840
841 pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
842 pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
843
844 /*
845 * Determine the default leaf.
846 *
847 * Intel returns values of the highest standard function, while AMD
848 * returns zeros. VIA on the other hand seems to returning nothing or
849 * perhaps some random garbage, we don't try to duplicate this behavior.
850 */
851 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
852 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
853 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
854
855
856 /* Cpuid 1 & 0x80000001:
857 * Only report features we can support.
858 *
859 * Note! When enabling new features the Synthetic CPU and Portable CPUID
860 * options may require adjusting (i.e. stripping what was enabled).
861 */
862 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
863 | X86_CPUID_FEATURE_EDX_VME
864 | X86_CPUID_FEATURE_EDX_DE
865 | X86_CPUID_FEATURE_EDX_PSE
866 | X86_CPUID_FEATURE_EDX_TSC
867 | X86_CPUID_FEATURE_EDX_MSR
868 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
869 | X86_CPUID_FEATURE_EDX_MCE
870 | X86_CPUID_FEATURE_EDX_CX8
871 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
872 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
873 //| X86_CPUID_FEATURE_EDX_SEP
874 | X86_CPUID_FEATURE_EDX_MTRR
875 | X86_CPUID_FEATURE_EDX_PGE
876 | X86_CPUID_FEATURE_EDX_MCA
877 | X86_CPUID_FEATURE_EDX_CMOV
878 | X86_CPUID_FEATURE_EDX_PAT
879 | X86_CPUID_FEATURE_EDX_PSE36
880 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
881 | X86_CPUID_FEATURE_EDX_CLFSH
882 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
883 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
884 | X86_CPUID_FEATURE_EDX_MMX
885 | X86_CPUID_FEATURE_EDX_FXSR
886 | X86_CPUID_FEATURE_EDX_SSE
887 | X86_CPUID_FEATURE_EDX_SSE2
888 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
889 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
890 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
891 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
892 | 0;
893 pCPUM->aGuestCpuIdStd[1].ecx &= 0
894 | X86_CPUID_FEATURE_ECX_SSE3
895 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
896 | ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
897 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
898 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
899 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
900 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
901 | X86_CPUID_FEATURE_ECX_SSSE3
902 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
903 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
904 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
905 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
906 /* ECX Bit 21 - x2APIC support - not yet. */
907 // | X86_CPUID_FEATURE_ECX_X2APIC
908 /* ECX Bit 23 - POPCNT instruction. */
909 //| X86_CPUID_FEATURE_ECX_POPCNT
910 | 0;
911 if (pCPUM->u8PortableCpuIdLevel > 0)
912 {
913 PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
914 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
915 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
916 PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
917 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
918 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
919 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
920
921 Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
922 | X86_CPUID_FEATURE_EDX_PSN
923 | X86_CPUID_FEATURE_EDX_DS
924 | X86_CPUID_FEATURE_EDX_ACPI
925 | X86_CPUID_FEATURE_EDX_SS
926 | X86_CPUID_FEATURE_EDX_TM
927 | X86_CPUID_FEATURE_EDX_PBE
928 )));
929 Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
930 | X86_CPUID_FEATURE_ECX_DTES64
931 | X86_CPUID_FEATURE_ECX_CPLDS
932 | X86_CPUID_FEATURE_ECX_VMX
933 | X86_CPUID_FEATURE_ECX_SMX
934 | X86_CPUID_FEATURE_ECX_EST
935 | X86_CPUID_FEATURE_ECX_TM2
936 | X86_CPUID_FEATURE_ECX_CNTXID
937 | X86_CPUID_FEATURE_ECX_FMA
938 | X86_CPUID_FEATURE_ECX_CX16
939 | X86_CPUID_FEATURE_ECX_TPRUPDATE
940 | X86_CPUID_FEATURE_ECX_PDCM
941 | X86_CPUID_FEATURE_ECX_DCA
942 | X86_CPUID_FEATURE_ECX_MOVBE
943 | X86_CPUID_FEATURE_ECX_AES
944 | X86_CPUID_FEATURE_ECX_POPCNT
945 | X86_CPUID_FEATURE_ECX_XSAVE
946 | X86_CPUID_FEATURE_ECX_OSXSAVE
947 | X86_CPUID_FEATURE_ECX_AVX
948 )));
949 }
950
951 /* Cpuid 0x80000001:
952 * Only report features we can support.
953 *
954 * Note! When enabling new features the Synthetic CPU and Portable CPUID
955 * options may require adjusting (i.e. stripping what was enabled).
956 *
957 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
958 */
959 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
960 | X86_CPUID_AMD_FEATURE_EDX_VME
961 | X86_CPUID_AMD_FEATURE_EDX_DE
962 | X86_CPUID_AMD_FEATURE_EDX_PSE
963 | X86_CPUID_AMD_FEATURE_EDX_TSC
964 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
965 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
966 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
967 | X86_CPUID_AMD_FEATURE_EDX_CX8
968 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
969 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
970 //| X86_CPUID_EXT_FEATURE_EDX_SEP
971 | X86_CPUID_AMD_FEATURE_EDX_MTRR
972 | X86_CPUID_AMD_FEATURE_EDX_PGE
973 | X86_CPUID_AMD_FEATURE_EDX_MCA
974 | X86_CPUID_AMD_FEATURE_EDX_CMOV
975 | X86_CPUID_AMD_FEATURE_EDX_PAT
976 | X86_CPUID_AMD_FEATURE_EDX_PSE36
977 //| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE.
978 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
979 | X86_CPUID_AMD_FEATURE_EDX_MMX
980 | X86_CPUID_AMD_FEATURE_EDX_FXSR
981 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
982 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
983 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
984 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
985 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
986 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
987 | 0;
988 pCPUM->aGuestCpuIdExt[1].ecx &= 0
989 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
990 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
991 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
992 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
993 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
994 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
995 //| X86_CPUID_AMD_FEATURE_ECX_ABM
996 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
997 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
998 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
999 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
1000 //| X86_CPUID_AMD_FEATURE_ECX_IBS
1001 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
1002 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1003 //| X86_CPUID_AMD_FEATURE_ECX_WDT
1004 | 0;
1005 if (pCPUM->u8PortableCpuIdLevel > 0)
1006 {
1007 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1008 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1009 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1010 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1011 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1012 PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1013 PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1014
1015 Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
1016 | X86_CPUID_AMD_FEATURE_ECX_SVM
1017 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1018 | X86_CPUID_AMD_FEATURE_ECX_CR8L
1019 | X86_CPUID_AMD_FEATURE_ECX_ABM
1020 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
1021 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1022 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1023 | X86_CPUID_AMD_FEATURE_ECX_OSVW
1024 | X86_CPUID_AMD_FEATURE_ECX_IBS
1025 | X86_CPUID_AMD_FEATURE_ECX_SSE5
1026 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
1027 | X86_CPUID_AMD_FEATURE_ECX_WDT
1028 | UINT32_C(0xffffc000)
1029 )));
1030 Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
1031 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1032 | RT_BIT(18)
1033 | RT_BIT(19)
1034 | RT_BIT(21)
1035 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
1036 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1037 | RT_BIT(28)
1038 )));
1039 }
1040
1041 /*
1042 * Apply the Synthetic CPU modifications. (TODO: move this up)
1043 */
1044 if (pCPUM->fSyntheticCpu)
1045 {
1046 static const char s_szVendor[13] = "VirtualBox ";
1047 static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
1048
1049 pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
1050
1051 /* Limit the nr of standard leaves; 5 for monitor/mwait */
1052 pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
1053
1054 /* 0: Vendor */
1055 pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
1056 pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
1057 pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
1058
1059 /* 1.eax: Version information. family : model : stepping */
1060 pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
1061
1062 /* Leaves 2 - 4 are Intel only - zero them out */
1063 memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
1064 memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
1065 memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
1066
1067 /* Leaf 5 = monitor/mwait */
1068
1069 /* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
1070 pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
1071 /* AMD only - set to zero. */
1072 pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
1073
1074 /* 0x800000001: shared feature bits are set dynamically. */
1075 memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
1076
1077 /* 0x800000002-4: Processor Name String Identifier. */
1078 pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
1079 pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
1080 pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
1081 pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
1082 pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
1083 pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
1084 pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
1085 pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
1086 pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
1087 pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
1088 pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
1089 pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
1090
1091 /* 0x800000005-7 - reserved -> zero */
1092 memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
1093 memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
1094 memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
1095
1096 /* 0x800000008: only the max virtual and physical address size. */
1097 pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1098 }
1099
1100 /*
1101 * Hide HTT, multicode, SMP, whatever.
1102 * (APIC-ID := 0 and #LogCpus := 0)
1103 */
1104 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
1105#ifdef VBOX_WITH_MULTI_CORE
1106 if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
1107 && pVM->cCpus > 1)
1108 {
1109 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
1110 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCpus << 16);
1111 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
1112 }
1113#endif
1114
1115 /* Cpuid 2:
1116 * Intel: Cache and TLB information
1117 * AMD: Reserved
1118 * VIA: Reserved
1119 * Safe to expose; restrict the number of calls to 1 for the portable case.
1120 */
1121 if ( pCPUM->u8PortableCpuIdLevel > 0
1122 && pCPUM->aGuestCpuIdStd[0].eax >= 2
1123 && (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
1124 {
1125 LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
1126 pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
1127 }
1128
1129 /* Cpuid 3:
1130 * Intel: EAX, EBX - reserved (transmeta uses these)
1131 * ECX, EDX - Processor Serial Number if available, otherwise reserved
1132 * AMD: Reserved
1133 * VIA: Reserved
1134 * Safe to expose
1135 */
1136 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
1137 {
1138 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
1139 if (pCPUM->u8PortableCpuIdLevel > 0)
1140 pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
1141 }
1142
1143 /* Cpuid 4:
1144 * Intel: Deterministic Cache Parameters Leaf
1145 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
1146 * AMD: Reserved
1147 * VIA: Reserved
1148 * Safe to expose, except for EAX:
1149 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1150 * Bits 31-26: Maximum number of processor cores in this physical package**
1151 * Note: These SMP values are constant regardless of ECX
1152 */
1153 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
1154 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
1155#ifdef VBOX_WITH_MULTI_CORE
1156 if ( pVM->cCpus > 1
1157 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1158 {
1159 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1160 /* One logical processor with possibly multiple cores. */
1161 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1162 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
1163 }
1164#endif
1165
1166 /* Cpuid 5: Monitor/mwait Leaf
1167 * Intel: ECX, EDX - reserved
1168 * EAX, EBX - Smallest and largest monitor line size
1169 * AMD: EDX - reserved
1170 * EAX, EBX - Smallest and largest monitor line size
1171 * ECX - extensions (ignored for now)
1172 * VIA: Reserved
1173 * Safe to expose
1174 */
1175 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
1176 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
1177
1178 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1179 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
1180 * Expose MWAIT extended features to the guest. For now we expose
1181 * just MWAIT break on interrupt feature (bit 1).
1182 */
1183 bool fMWaitExtensions;
1184 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
1185 if (fMWaitExtensions)
1186 {
1187 pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1188 /* @todo: for now we just expose host's MWAIT C-states, although conceptually
1189 it shall be part of our power management virtualization model */
1190#if 0
1191 /* MWAIT sub C-states */
1192 pCPUM->aGuestCpuIdStd[5].edx =
1193 (0 << 0) /* 0 in C0 */ |
1194 (2 << 4) /* 2 in C1 */ |
1195 (2 << 8) /* 2 in C2 */ |
1196 (2 << 12) /* 2 in C3 */ |
1197 (0 << 16) /* 0 in C4 */
1198 ;
1199#endif
1200 }
1201 else
1202 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1203
1204 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
1205 * Safe to pass on to the guest.
1206 *
1207 * Intel: 0x800000005 reserved
1208 * 0x800000006 L2 cache information
1209 * AMD: 0x800000005 L1 cache information
1210 * 0x800000006 L2/L3 cache information
1211 * VIA: 0x800000005 TLB and L1 cache information
1212 * 0x800000006 L2 cache information
1213 */
1214
1215 /* Cpuid 0x800000007:
1216 * Intel: Reserved
1217 * AMD: EAX, EBX, ECX - reserved
1218 * EDX: Advanced Power Management Information
1219 * VIA: Reserved
1220 */
1221 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
1222 {
1223 Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
1224
1225 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
1226
1227 if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1228 {
1229 /* Only expose the TSC invariant capability bit to the guest. */
1230 pCPUM->aGuestCpuIdExt[7].edx &= 0
1231 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
1232 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
1233 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
1234 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
1235 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
1236 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
1237 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
1238 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
1239#if 0 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
1240 * Linux kernels blindly assume that the AMD performance counters work
1241 * if this is set for 64 bits guests. (Can't really find a CPUID feature
1242 * bit for them though.) */
1243 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
1244#endif
1245 | 0;
1246 }
1247 else
1248 pCPUM->aGuestCpuIdExt[7].edx = 0;
1249 }
1250
1251 /* Cpuid 0x800000008:
1252 * Intel: EAX: Virtual/Physical address Size
1253 * EBX, ECX, EDX - reserved
1254 * AMD: EBX, EDX - reserved
1255 * EAX: Virtual/Physical/Guest address Size
1256 * ECX: Number of cores + APICIdCoreIdSize
1257 * VIA: EAX: Virtual/Physical address size
1258 * EBX, ECX, EDX - reserved
1259 */
1260 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
1261 {
1262 /* Only expose the virtual and physical address sizes to the guest. */
1263 pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
1264 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1265 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
1266 * NC (0-7) Number of cores; 0 equals 1 core */
1267 pCPUM->aGuestCpuIdExt[8].ecx = 0;
1268#ifdef VBOX_WITH_MULTI_CORE
1269 if ( pVM->cCpus > 1
1270 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1271 {
1272 /* Legacy method to determine the number of cores. */
1273 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
1274 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
1275 }
1276#endif
1277 }
1278
1279 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
1280 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
1281 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
1282 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
1283 */
1284 bool fNt4LeafLimit;
1285 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
1286 if (fNt4LeafLimit)
1287 pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
1288
1289 /*
1290 * Limit it the number of entries and fill the remaining with the defaults.
1291 *
1292 * The limits are masking off stuff about power saving and similar, this
1293 * is perhaps a bit crudely done as there is probably some relatively harmless
1294 * info too in these leaves (like words about having a constant TSC).
1295 */
1296 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
1297 pCPUM->aGuestCpuIdStd[0].eax = 5;
1298 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
1299 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
1300
1301 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
1302 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
1303 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
1304 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
1305 : 0;
1306 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
1307 i++)
1308 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
1309
1310 /*
1311 * Centaur stuff (VIA).
1312 *
1313 * The important part here (we think) is to make sure the 0xc0000000
1314 * function returns 0xc0000001. As for the features, we don't currently
1315 * let on about any of those... 0xc0000002 seems to be some
1316 * temperature/hz/++ stuff, include it as well (static).
1317 */
1318 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
1319 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
1320 {
1321 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
1322 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
1323 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
1324 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
1325 i++)
1326 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1327 }
1328 else
1329 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
1330 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1331
1332 /*
1333 * Hypervisor identification.
1334 *
1335 * We only return minimal information, primarily ensuring that the
1336 * 0x40000000 function returns 0x40000001 and identifying ourselves.
1337 * Currently we do not support any hypervisor-specific interface.
1338 */
1339 pCPUM->aGuestCpuIdHyper[0].eax = UINT32_C(0x40000001);
1340 pCPUM->aGuestCpuIdHyper[0].ebx = pCPUM->aGuestCpuIdHyper[0].ecx
1341 = pCPUM->aGuestCpuIdHyper[0].edx = 0x786f4256; /* 'VBox' */
1342 pCPUM->aGuestCpuIdHyper[1].eax = 0x656e6f6e; /* 'none' */
1343 pCPUM->aGuestCpuIdHyper[1].ebx = pCPUM->aGuestCpuIdHyper[1].ecx
1344 = pCPUM->aGuestCpuIdHyper[1].edx = 0; /* Reserved */
1345
1346 /*
1347 * Load CPUID overrides from configuration.
1348 * Note: Kind of redundant now, but allows unchanged overrides
1349 */
1350 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
1351 * Overrides the CPUID leaf values. */
1352 PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
1353 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
1354 AssertRCReturn(rc, rc);
1355 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
1356 AssertRCReturn(rc, rc);
1357 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
1358 AssertRCReturn(rc, rc);
1359
1360 /*
1361 * Check if PAE was explicitely enabled by the user.
1362 */
1363 bool fEnable;
1364 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
1365 if (fEnable)
1366 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1367
1368 /*
1369 * We don't normally enable NX for raw-mode, so give the user a chance to
1370 * force it on.
1371 */
1372 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
1373 if (fEnable)
1374 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1375
1376 /*
1377 * We don't enable the Hypervisor Present bit by default, but it may
1378 * be needed by some guests.
1379 */
1380 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
1381 if (fEnable)
1382 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
1383 /*
1384 * Log the cpuid and we're good.
1385 */
1386 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1387 RTCPUSET OnlineSet;
1388 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
1389 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
1390 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
1391 LogRel(("************************* CPUID dump ************************\n"));
1392 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
1393 LogRel(("\n"));
1394 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
1395 RTLogRelSetBuffering(fOldBuffered);
1396 LogRel(("******************** End of CPUID dump **********************\n"));
1397
1398#undef PORTABLE_DISABLE_FEATURE_BIT
1399#undef PORTABLE_CLEAR_BITS_WHEN
1400
1401 return VINF_SUCCESS;
1402}
1403
1404
1405/**
1406 * Applies relocations to data and code managed by this
1407 * component. This function will be called at init and
1408 * whenever the VMM need to relocate it self inside the GC.
1409 *
1410 * The CPUM will update the addresses used by the switcher.
1411 *
1412 * @param pVM The VM.
1413 */
1414VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1415{
1416 LogFlow(("CPUMR3Relocate\n"));
1417 /* nothing to do any more. */
1418}
1419
1420
1421/**
1422 * Apply late CPUM property changes based on the fHWVirtEx setting
1423 *
1424 * @param pVM Pointer to the VM.
1425 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
1426 */
1427VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1428{
1429 /*
1430 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1431 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1432 * of processors from (cpuid(4).eax >> 26) + 1.
1433 *
1434 * Note: this code is obsolete, but let's keep it here for reference.
1435 * Purpose is valid when we artificially cap the max std id to less than 4.
1436 */
1437 if (!fHWVirtExEnabled)
1438 {
1439 Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1440 || pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1441 pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1442 }
1443}
1444
1445/**
1446 * Terminates the CPUM.
1447 *
1448 * Termination means cleaning up and freeing all resources,
1449 * the VM it self is at this point powered off or suspended.
1450 *
1451 * @returns VBox status code.
1452 * @param pVM Pointer to the VM.
1453 */
1454VMMR3DECL(int) CPUMR3Term(PVM pVM)
1455{
1456#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1457 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1458 {
1459 PVMCPU pVCpu = &pVM->aCpus[i];
1460 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1461
1462 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1463 pVCpu->cpum.s.uMagic = 0;
1464 pCtx->dr[5] = 0;
1465 }
1466#else
1467 NOREF(pVM);
1468#endif
1469 return VINF_SUCCESS;
1470}
1471
1472
1473/**
1474 * Resets a virtual CPU.
1475 *
1476 * Used by CPUMR3Reset and CPU hot plugging.
1477 *
1478 * @param pVCpu Pointer to the VMCPU.
1479 */
1480VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1481{
1482 /** @todo anything different for VCPU > 0? */
1483 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1484
1485 /*
1486 * Initialize everything to ZERO first.
1487 */
1488 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1489 memset(pCtx, 0, sizeof(*pCtx));
1490 pVCpu->cpum.s.fUseFlags = fUseFlags;
1491
1492 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1493 pCtx->eip = 0x0000fff0;
1494 pCtx->edx = 0x00000600; /* P6 processor */
1495 pCtx->eflags.Bits.u1Reserved0 = 1;
1496
1497 pCtx->cs.Sel = 0xf000;
1498 pCtx->cs.ValidSel = 0xf000;
1499 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1500 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1501 pCtx->cs.u32Limit = 0x0000ffff;
1502 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1503 pCtx->cs.Attr.n.u1Present = 1;
1504 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1505
1506 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1507 pCtx->ds.u32Limit = 0x0000ffff;
1508 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1509 pCtx->ds.Attr.n.u1Present = 1;
1510 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1511
1512 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1513 pCtx->es.u32Limit = 0x0000ffff;
1514 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1515 pCtx->es.Attr.n.u1Present = 1;
1516 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1517
1518 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1519 pCtx->fs.u32Limit = 0x0000ffff;
1520 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1521 pCtx->fs.Attr.n.u1Present = 1;
1522 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1523
1524 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1525 pCtx->gs.u32Limit = 0x0000ffff;
1526 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1527 pCtx->gs.Attr.n.u1Present = 1;
1528 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1529
1530 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1531 pCtx->ss.u32Limit = 0x0000ffff;
1532 pCtx->ss.Attr.n.u1Present = 1;
1533 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1534 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1535
1536 pCtx->idtr.cbIdt = 0xffff;
1537 pCtx->gdtr.cbGdt = 0xffff;
1538
1539 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1540 pCtx->ldtr.u32Limit = 0xffff;
1541 pCtx->ldtr.Attr.n.u1Present = 1;
1542 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1543
1544 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1545 pCtx->tr.u32Limit = 0xffff;
1546 pCtx->tr.Attr.n.u1Present = 1;
1547 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1548
1549 pCtx->dr[6] = X86_DR6_INIT_VAL;
1550 pCtx->dr[7] = X86_DR7_INIT_VAL;
1551
1552 pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1553 pCtx->fpu.FCW = 0x37f;
1554
1555 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1556 IA-32 Processor States Following Power-up, Reset, or INIT */
1557 pCtx->fpu.MXCSR = 0x1F80;
1558 pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1559 supports all bits, since a zero value here should be read as 0xffbf. */
1560
1561 /* Init PAT MSR */
1562 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1563
1564 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1565 * The Intel docs don't mention it.
1566 */
1567 pCtx->msrEFER = 0;
1568}
1569
1570
1571/**
1572 * Resets the CPU.
1573 *
1574 * @returns VINF_SUCCESS.
1575 * @param pVM Pointer to the VM.
1576 */
1577VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1578{
1579 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1580 {
1581 CPUMR3ResetCpu(&pVM->aCpus[i]);
1582
1583#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1584 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
1585
1586 /* Magic marker for searching in crash dumps. */
1587 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1588 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1589 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1590#endif
1591 }
1592}
1593
1594
1595/**
1596 * Called both in pass 0 and the final pass.
1597 *
1598 * @param pVM Pointer to the VM.
1599 * @param pSSM The saved state handle.
1600 */
1601static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1602{
1603 /*
1604 * Save all the CPU ID leaves here so we can check them for compatibility
1605 * upon loading.
1606 */
1607 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1608 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1609
1610 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1611 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1612
1613 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1614 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1615
1616 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1617
1618 /*
1619 * Save a good portion of the raw CPU IDs as well as they may come in
1620 * handy when validating features for raw mode.
1621 */
1622 CPUMCPUID aRawStd[16];
1623 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1624 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1625 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1626 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1627
1628 CPUMCPUID aRawExt[32];
1629 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1630 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1631 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1632 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1633}
1634
1635
1636/**
1637 * Loads the CPU ID leaves saved by pass 0.
1638 *
1639 * @returns VBox status code.
1640 * @param pVM Pointer to the VM.
1641 * @param pSSM The saved state handle.
1642 * @param uVersion The format version.
1643 */
1644static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1645{
1646 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1647
1648 /*
1649 * Define a bunch of macros for simplifying the code.
1650 */
1651 /* Generic expression + failure message. */
1652#define CPUID_CHECK_RET(expr, fmt) \
1653 do { \
1654 if (!(expr)) \
1655 { \
1656 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
1657 if (fStrictCpuIdChecks) \
1658 { \
1659 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1660 RTStrFree(pszMsg); \
1661 return rcCpuid; \
1662 } \
1663 LogRel(("CPUM: %s\n", pszMsg)); \
1664 RTStrFree(pszMsg); \
1665 } \
1666 } while (0)
1667#define CPUID_CHECK_WRN(expr, fmt) \
1668 do { \
1669 if (!(expr)) \
1670 LogRel(fmt); \
1671 } while (0)
1672
1673 /* For comparing two values and bitch if they differs. */
1674#define CPUID_CHECK2_RET(what, host, saved) \
1675 do { \
1676 if ((host) != (saved)) \
1677 { \
1678 if (fStrictCpuIdChecks) \
1679 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1680 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1681 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1682 } \
1683 } while (0)
1684#define CPUID_CHECK2_WRN(what, host, saved) \
1685 do { \
1686 if ((host) != (saved)) \
1687 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1688 } while (0)
1689
1690 /* For checking raw cpu features (raw mode). */
1691#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1692 do { \
1693 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1694 { \
1695 if (fStrictCpuIdChecks) \
1696 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1697 N_(#bit " mismatch: host=%d saved=%d"), \
1698 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1699 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1700 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1701 } \
1702 } while (0)
1703#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1704 do { \
1705 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1706 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1707 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1708 } while (0)
1709#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1710
1711 /* For checking guest features. */
1712#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1713 do { \
1714 if ( (aGuestCpuId##set [1].reg & bit) \
1715 && !(aHostRaw##set [1].reg & bit) \
1716 && !(aHostOverride##set [1].reg & bit) \
1717 && !(aGuestOverride##set [1].reg & bit) \
1718 ) \
1719 { \
1720 if (fStrictCpuIdChecks) \
1721 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1722 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1723 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1724 } \
1725 } while (0)
1726#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1727 do { \
1728 if ( (aGuestCpuId##set [1].reg & bit) \
1729 && !(aHostRaw##set [1].reg & bit) \
1730 && !(aHostOverride##set [1].reg & bit) \
1731 && !(aGuestOverride##set [1].reg & bit) \
1732 ) \
1733 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1734 } while (0)
1735#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1736 do { \
1737 if ( (aGuestCpuId##set [1].reg & bit) \
1738 && !(aHostRaw##set [1].reg & bit) \
1739 && !(aHostOverride##set [1].reg & bit) \
1740 && !(aGuestOverride##set [1].reg & bit) \
1741 ) \
1742 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1743 } while (0)
1744#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1745
1746 /* For checking guest features if AMD guest CPU. */
1747#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1748 do { \
1749 if ( (aGuestCpuId##set [1].reg & bit) \
1750 && fGuestAmd \
1751 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1752 && !(aHostOverride##set [1].reg & bit) \
1753 && !(aGuestOverride##set [1].reg & bit) \
1754 ) \
1755 { \
1756 if (fStrictCpuIdChecks) \
1757 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1758 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1759 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1760 } \
1761 } while (0)
1762#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1763 do { \
1764 if ( (aGuestCpuId##set [1].reg & bit) \
1765 && fGuestAmd \
1766 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1767 && !(aHostOverride##set [1].reg & bit) \
1768 && !(aGuestOverride##set [1].reg & bit) \
1769 ) \
1770 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1771 } while (0)
1772#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1773 do { \
1774 if ( (aGuestCpuId##set [1].reg & bit) \
1775 && fGuestAmd \
1776 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1777 && !(aHostOverride##set [1].reg & bit) \
1778 && !(aGuestOverride##set [1].reg & bit) \
1779 ) \
1780 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1781 } while (0)
1782#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1783
1784 /* For checking AMD features which have a corresponding bit in the standard
1785 range. (Intel defines very few bits in the extended feature sets.) */
1786#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1787 do { \
1788 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1789 && !(fHostAmd \
1790 ? aHostRawExt[1].reg & (ExtBit) \
1791 : aHostRawStd[1].reg & (StdBit)) \
1792 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1793 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1794 ) \
1795 { \
1796 if (fStrictCpuIdChecks) \
1797 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1798 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1799 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1800 } \
1801 } while (0)
1802#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1803 do { \
1804 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1805 && !(fHostAmd \
1806 ? aHostRawExt[1].reg & (ExtBit) \
1807 : aHostRawStd[1].reg & (StdBit)) \
1808 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1809 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1810 ) \
1811 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1812 } while (0)
1813#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1814 do { \
1815 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1816 && !(fHostAmd \
1817 ? aHostRawExt[1].reg & (ExtBit) \
1818 : aHostRawStd[1].reg & (StdBit)) \
1819 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1820 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1821 ) \
1822 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1823 } while (0)
1824#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1825
1826 /*
1827 * Load them into stack buffers first.
1828 */
1829 CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1830 uint32_t cGuestCpuIdStd;
1831 int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1832 if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1833 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1834 SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1835
1836 CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1837 uint32_t cGuestCpuIdExt;
1838 rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1839 if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1840 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1841 SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1842
1843 CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1844 uint32_t cGuestCpuIdCentaur;
1845 rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1846 if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1847 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1848 SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1849
1850 CPUMCPUID GuestCpuIdDef;
1851 rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1852 AssertRCReturn(rc, rc);
1853
1854 CPUMCPUID aRawStd[16];
1855 uint32_t cRawStd;
1856 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1857 if (cRawStd > RT_ELEMENTS(aRawStd))
1858 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1859 SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1860
1861 CPUMCPUID aRawExt[32];
1862 uint32_t cRawExt;
1863 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1864 if (cRawExt > RT_ELEMENTS(aRawExt))
1865 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1866 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1867 AssertRCReturn(rc, rc);
1868
1869 /*
1870 * Note that we support restoring less than the current amount of standard
1871 * leaves because we've been allowed more is newer version of VBox.
1872 *
1873 * So, pad new entries with the default.
1874 */
1875 for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1876 aGuestCpuIdStd[i] = GuestCpuIdDef;
1877
1878 for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1879 aGuestCpuIdExt[i] = GuestCpuIdDef;
1880
1881 for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1882 aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1883
1884 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1885 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1886
1887 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1888 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1889
1890 /*
1891 * Get the raw CPU IDs for the current host.
1892 */
1893 CPUMCPUID aHostRawStd[16];
1894 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1895 ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1896
1897 CPUMCPUID aHostRawExt[32];
1898 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1899 ASMCpuId(i | UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1900
1901 /*
1902 * Get the host and guest overrides so we don't reject the state because
1903 * some feature was enabled thru these interfaces.
1904 * Note! We currently only need the feature leaves, so skip rest.
1905 */
1906 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1907 CPUMCPUID aGuestOverrideStd[2];
1908 memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1909 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1910
1911 CPUMCPUID aGuestOverrideExt[2];
1912 memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1913 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1914
1915 pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1916 CPUMCPUID aHostOverrideStd[2];
1917 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1918 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1919
1920 CPUMCPUID aHostOverrideExt[2];
1921 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1922 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1923
1924 /*
1925 * This can be skipped.
1926 */
1927 bool fStrictCpuIdChecks;
1928 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1929
1930
1931
1932 /*
1933 * For raw-mode we'll require that the CPUs are very similar since we don't
1934 * intercept CPUID instructions for user mode applications.
1935 */
1936 if (!HWACCMIsEnabled(pVM))
1937 {
1938 /* CPUID(0) */
1939 CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1940 && aHostRawStd[0].ecx == aRawStd[0].ecx
1941 && aHostRawStd[0].edx == aRawStd[0].edx,
1942 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1943 &aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1944 &aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1945 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1946 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1947 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1948
1949 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1950
1951 /* CPUID(1).eax */
1952 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1953 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1954 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1955
1956 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1957 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1958 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1959
1960 /* CPUID(1).ecx */
1961 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1962 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1963 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1964 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1965 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1966 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1967 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1968 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1969 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1970 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1971 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1972 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
1973 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1974 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1975 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1976 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1977 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
1978 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
1979 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1980 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1981 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1982 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1983 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1984 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1985 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
1986 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1987 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1988 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1989 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1990 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
1991 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
1992 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_HVP);
1993
1994 /* CPUID(1).edx */
1995 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1996 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1997 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1998 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1999 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
2000 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
2001 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2002 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2003 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
2004 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2005 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2006 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2007 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2008 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2009 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2010 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
2011 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2012 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2013 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2014 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
2015 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2016 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
2017 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
2018 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
2019 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
2020 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
2021 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
2022 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
2023 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
2024 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
2025 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/);
2026 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
2027
2028 /* CPUID(2) - config, mostly about caches. ignore. */
2029 /* CPUID(3) - processor serial number. ignore. */
2030 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
2031 /* CPUID(5) - mwait/monitor config. ignore. */
2032 /* CPUID(6) - power management. ignore. */
2033 /* CPUID(7) - ???. ignore. */
2034 /* CPUID(8) - ???. ignore. */
2035 /* CPUID(9) - DCA. ignore for now. */
2036 /* CPUID(a) - PeMo info. ignore for now. */
2037 /* CPUID(b) - topology info - takes ECX as input. ignore. */
2038
2039 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
2040 CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
2041 || aHostRawStd[0].eax >= UINT32_C(0x0000000d),
2042 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
2043 if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
2044 && aHostRawStd[0].eax >= UINT32_C(0x0000000d))
2045 {
2046 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
2047 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
2048 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
2049 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
2050 }
2051
2052 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
2053 Note! Intel have/is marking many of the fields here as reserved. We
2054 will verify them as if it's an AMD CPU. */
2055 CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
2056 || !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
2057 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
2058 if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
2059 {
2060 CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
2061 && aHostRawExt[0].ecx == aRawExt[0].ecx
2062 && aHostRawExt[0].edx == aRawExt[0].edx,
2063 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2064 &aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
2065 &aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
2066 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
2067
2068 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
2069 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
2070 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
2071 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
2072 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
2073 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2074
2075 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
2076 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
2077 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
2078 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
2079
2080 /* CPUID(0x80000001).ecx */
2081 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2082 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
2083 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
2084 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
2085 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2086 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
2087 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
2088 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
2089 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
2090 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
2091 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
2092 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
2093 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
2094 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
2095 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2096 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2097 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2098 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2099 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2100 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2101 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2102 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2103 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2104 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2105 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2106 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2107 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2108 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2109 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2110 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2111 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2112 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2113
2114 /* CPUID(0x80000001).edx */
2115 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
2116 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
2117 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
2118 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
2119 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
2120 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
2121 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
2122 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
2123 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
2124 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
2125 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2126 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SEP);
2127 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
2128 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
2129 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
2130 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2131 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
2132 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
2133 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2134 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2135 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2136 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/);
2137 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2138 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
2139 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
2140 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2141 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2142 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2143 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/);
2144 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2145 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2146 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2147
2148 /** @todo verify the rest as well. */
2149 }
2150 }
2151
2152
2153
2154 /*
2155 * Verify that we can support the features already exposed to the guest on
2156 * this host.
2157 *
2158 * Most of the features we're emulating requires intercepting instruction
2159 * and doing it the slow way, so there is no need to warn when they aren't
2160 * present in the host CPU. Thus we use IGN instead of EMU on these.
2161 *
2162 * Trailing comments:
2163 * "EMU" - Possible to emulate, could be lots of work and very slow.
2164 * "EMU?" - Can this be emulated?
2165 */
2166 /* CPUID(1).ecx */
2167 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
2168 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
2169 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
2170 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2171 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
2172 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
2173 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
2174 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
2175 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
2176 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
2177 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
2178 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2179 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
2180 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
2181 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
2182 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
2183 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2184 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2185 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
2186 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
2187 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
2188 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2189 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
2190 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
2191 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2192 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
2193 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
2194 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
2195 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
2196 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2197 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2198 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
2199
2200 /* CPUID(1).edx */
2201 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2202 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2203 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
2204 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2205 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2206 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2207 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2208 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2209 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2210 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2211 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2212 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2213 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2214 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2215 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2216 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2217 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2218 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2219 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2220 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
2221 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2222 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
2223 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
2224 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2225 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2226 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
2227 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
2228 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
2229 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
2230 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
2231 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
2232 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
2233
2234 /* CPUID(0x80000000). */
2235 if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
2236 && aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
2237 {
2238 /** @todo deal with no 0x80000001 on the host. */
2239 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
2240 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
2241
2242 /* CPUID(0x80000001).ecx */
2243 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
2244 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
2245 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
2246 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
2247 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
2248 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
2249 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
2250 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
2251 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
2252 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
2253 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
2254 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
2255 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
2256 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
2257 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2258 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2259 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2260 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2261 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2262 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2263 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2264 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2265 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2266 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2267 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2268 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2269 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2270 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2271 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2272 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2273 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2274 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2275
2276 /* CPUID(0x80000001).edx */
2277 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
2278 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
2279 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
2280 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
2281 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2282 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2283 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
2284 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
2285 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2286 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
2287 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2288 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
2289 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
2290 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
2291 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
2292 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2293 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
2294 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
2295 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2296 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2297 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2298 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/);
2299 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2300 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2301 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2302 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2303 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2304 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2305 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/);
2306 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2307 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2308 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2309 }
2310
2311 /*
2312 * We're good, commit the CPU ID leaves.
2313 */
2314 memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
2315 memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
2316 memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
2317 pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
2318
2319#undef CPUID_CHECK_RET
2320#undef CPUID_CHECK_WRN
2321#undef CPUID_CHECK2_RET
2322#undef CPUID_CHECK2_WRN
2323#undef CPUID_RAW_FEATURE_RET
2324#undef CPUID_RAW_FEATURE_WRN
2325#undef CPUID_RAW_FEATURE_IGN
2326#undef CPUID_GST_FEATURE_RET
2327#undef CPUID_GST_FEATURE_WRN
2328#undef CPUID_GST_FEATURE_EMU
2329#undef CPUID_GST_FEATURE_IGN
2330#undef CPUID_GST_FEATURE2_RET
2331#undef CPUID_GST_FEATURE2_WRN
2332#undef CPUID_GST_FEATURE2_EMU
2333#undef CPUID_GST_FEATURE2_IGN
2334#undef CPUID_GST_AMD_FEATURE_RET
2335#undef CPUID_GST_AMD_FEATURE_WRN
2336#undef CPUID_GST_AMD_FEATURE_EMU
2337#undef CPUID_GST_AMD_FEATURE_IGN
2338
2339 return VINF_SUCCESS;
2340}
2341
2342
2343/**
2344 * Pass 0 live exec callback.
2345 *
2346 * @returns VINF_SSM_DONT_CALL_AGAIN.
2347 * @param pVM Pointer to the VM.
2348 * @param pSSM The saved state handle.
2349 * @param uPass The pass (0).
2350 */
2351static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2352{
2353 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2354 cpumR3SaveCpuId(pVM, pSSM);
2355 return VINF_SSM_DONT_CALL_AGAIN;
2356}
2357
2358
2359/**
2360 * Execute state save operation.
2361 *
2362 * @returns VBox status code.
2363 * @param pVM Pointer to the VM.
2364 * @param pSSM SSM operation handle.
2365 */
2366static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2367{
2368 /*
2369 * Save.
2370 */
2371 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2372 {
2373 PVMCPU pVCpu = &pVM->aCpus[i];
2374 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2375 }
2376
2377 SSMR3PutU32(pSSM, pVM->cCpus);
2378 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2379 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2380 {
2381 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2382
2383 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), 0, g_aCpumCtxFields, NULL);
2384 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2385 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2386 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2387 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2388 }
2389
2390 cpumR3SaveCpuId(pVM, pSSM);
2391 return VINF_SUCCESS;
2392}
2393
2394
2395/**
2396 * @copydoc FNSSMINTLOADPREP
2397 */
2398static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2399{
2400 NOREF(pSSM);
2401 pVM->cpum.s.fPendingRestore = true;
2402 return VINF_SUCCESS;
2403}
2404
2405
2406/**
2407 * @copydoc FNSSMINTLOADEXEC
2408 */
2409static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2410{
2411 /*
2412 * Validate version.
2413 */
2414 if ( uVersion != CPUM_SAVED_STATE_VERSION
2415 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2416 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2417 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2418 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2419 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2420 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2421 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2422 {
2423 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2424 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2425 }
2426
2427 if (uPass == SSM_PASS_FINAL)
2428 {
2429 /*
2430 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2431 * really old SSM file versions.)
2432 */
2433 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2434 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2435 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2436 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2437
2438 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2439 PCSSMFIELD paCpumCtxFields = g_aCpumCtxFields;
2440 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2441 paCpumCtxFields = g_aCpumCtxFieldsV16;
2442 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2443 paCpumCtxFields = g_aCpumCtxFieldsMem;
2444
2445 /*
2446 * Restore.
2447 */
2448 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2449 {
2450 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2451 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2452 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2453 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), fLoad, paCpumCtxFields, NULL);
2454 pVCpu->cpum.s.Hyper.cr3 = uCR3;
2455 pVCpu->cpum.s.Hyper.rsp = uRSP;
2456 }
2457
2458 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2459 {
2460 uint32_t cCpus;
2461 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2462 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2463 VERR_SSM_UNEXPECTED_DATA);
2464 }
2465 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2466 || pVM->cCpus == 1,
2467 ("cCpus=%u\n", pVM->cCpus),
2468 VERR_SSM_UNEXPECTED_DATA);
2469
2470 uint32_t cbMsrs = 0;
2471 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2472 {
2473 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2474 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2475 VERR_SSM_UNEXPECTED_DATA);
2476 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2477 VERR_SSM_UNEXPECTED_DATA);
2478 }
2479
2480 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2481 {
2482 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2483 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), fLoad,
2484 paCpumCtxFields, NULL);
2485 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2486 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2487 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2488 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2489 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2490 {
2491 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2492 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2493 }
2494 }
2495
2496 /* Older states does not have the internal selector register flags
2497 and valid selector value. Supply those. */
2498 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2499 {
2500 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2501 {
2502 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2503 bool const fValid = HWACCMIsEnabled(pVM)
2504 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2505 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2506 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2507 if (fValid)
2508 {
2509 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2510 {
2511 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2512 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2513 }
2514
2515 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2516 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2517 }
2518 else
2519 {
2520 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2521 {
2522 paSelReg[iSelReg].fFlags = 0;
2523 paSelReg[iSelReg].ValidSel = 0;
2524 }
2525
2526 /* This might not be 104% correct, but I think it's close
2527 enough for all practical purposes... (REM always loaded
2528 LDTR registers.) */
2529 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2530 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2531 }
2532 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2533 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2534 }
2535 }
2536
2537 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2538 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2539 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2540 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2541 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2542
2543 /*
2544 * A quick sanity check.
2545 */
2546 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2547 {
2548 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2549 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2550 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2551 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2552 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2553 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2554 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2555 }
2556 }
2557
2558 pVM->cpum.s.fPendingRestore = false;
2559
2560 /*
2561 * Guest CPUIDs.
2562 */
2563 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2564 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2565
2566 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2567 * actually required. */
2568
2569 /*
2570 * Restore the CPUID leaves.
2571 *
2572 * Note that we support restoring less than the current amount of standard
2573 * leaves because we've been allowed more is newer version of VBox.
2574 */
2575 uint32_t cElements;
2576 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2577 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2578 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2579 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2580
2581 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2582 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2583 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2584 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2585
2586 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2587 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2588 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2589 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2590
2591 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2592
2593 /*
2594 * Check that the basic cpuid id information is unchanged.
2595 */
2596 /** @todo we should check the 64 bits capabilities too! */
2597 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2598 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2599 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2600 uint32_t au32CpuIdSaved[8];
2601 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2602 if (RT_SUCCESS(rc))
2603 {
2604 /* Ignore CPU stepping. */
2605 au32CpuId[4] &= 0xfffffff0;
2606 au32CpuIdSaved[4] &= 0xfffffff0;
2607
2608 /* Ignore APIC ID (AMD specs). */
2609 au32CpuId[5] &= ~0xff000000;
2610 au32CpuIdSaved[5] &= ~0xff000000;
2611
2612 /* Ignore the number of Logical CPUs (AMD specs). */
2613 au32CpuId[5] &= ~0x00ff0000;
2614 au32CpuIdSaved[5] &= ~0x00ff0000;
2615
2616 /* Ignore some advanced capability bits, that we don't expose to the guest. */
2617 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2618 | X86_CPUID_FEATURE_ECX_VMX
2619 | X86_CPUID_FEATURE_ECX_SMX
2620 | X86_CPUID_FEATURE_ECX_EST
2621 | X86_CPUID_FEATURE_ECX_TM2
2622 | X86_CPUID_FEATURE_ECX_CNTXID
2623 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2624 | X86_CPUID_FEATURE_ECX_PDCM
2625 | X86_CPUID_FEATURE_ECX_DCA
2626 | X86_CPUID_FEATURE_ECX_X2APIC
2627 );
2628 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2629 | X86_CPUID_FEATURE_ECX_VMX
2630 | X86_CPUID_FEATURE_ECX_SMX
2631 | X86_CPUID_FEATURE_ECX_EST
2632 | X86_CPUID_FEATURE_ECX_TM2
2633 | X86_CPUID_FEATURE_ECX_CNTXID
2634 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2635 | X86_CPUID_FEATURE_ECX_PDCM
2636 | X86_CPUID_FEATURE_ECX_DCA
2637 | X86_CPUID_FEATURE_ECX_X2APIC
2638 );
2639
2640 /* Make sure we don't forget to update the masks when enabling
2641 * features in the future.
2642 */
2643 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2644 ( X86_CPUID_FEATURE_ECX_DTES64
2645 | X86_CPUID_FEATURE_ECX_VMX
2646 | X86_CPUID_FEATURE_ECX_SMX
2647 | X86_CPUID_FEATURE_ECX_EST
2648 | X86_CPUID_FEATURE_ECX_TM2
2649 | X86_CPUID_FEATURE_ECX_CNTXID
2650 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2651 | X86_CPUID_FEATURE_ECX_PDCM
2652 | X86_CPUID_FEATURE_ECX_DCA
2653 | X86_CPUID_FEATURE_ECX_X2APIC
2654 )));
2655 /* do the compare */
2656 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2657 {
2658 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2659 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2660 "Saved=%.*Rhxs\n"
2661 "Real =%.*Rhxs\n",
2662 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2663 sizeof(au32CpuId), au32CpuId));
2664 else
2665 {
2666 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2667 "Saved=%.*Rhxs\n"
2668 "Real =%.*Rhxs\n",
2669 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2670 sizeof(au32CpuId), au32CpuId));
2671 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2672 }
2673 }
2674 }
2675
2676 return rc;
2677}
2678
2679
2680/**
2681 * @copydoc FNSSMINTLOADPREP
2682 */
2683static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2684{
2685 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2686 return VINF_SUCCESS;
2687
2688 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2689 if (pVM->cpum.s.fPendingRestore)
2690 {
2691 LogRel(("CPUM: Missing state!\n"));
2692 return VERR_INTERNAL_ERROR_2;
2693 }
2694
2695 /* Notify PGM of the NXE states in case they've changed. */
2696 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2697 PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2698 return VINF_SUCCESS;
2699}
2700
2701
2702/**
2703 * Checks if the CPUM state restore is still pending.
2704 *
2705 * @returns true / false.
2706 * @param pVM Pointer to the VM.
2707 */
2708VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2709{
2710 return pVM->cpum.s.fPendingRestore;
2711}
2712
2713
2714/**
2715 * Formats the EFLAGS value into mnemonics.
2716 *
2717 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2718 * @param efl The EFLAGS value.
2719 */
2720static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2721{
2722 /*
2723 * Format the flags.
2724 */
2725 static const struct
2726 {
2727 const char *pszSet; const char *pszClear; uint32_t fFlag;
2728 } s_aFlags[] =
2729 {
2730 { "vip",NULL, X86_EFL_VIP },
2731 { "vif",NULL, X86_EFL_VIF },
2732 { "ac", NULL, X86_EFL_AC },
2733 { "vm", NULL, X86_EFL_VM },
2734 { "rf", NULL, X86_EFL_RF },
2735 { "nt", NULL, X86_EFL_NT },
2736 { "ov", "nv", X86_EFL_OF },
2737 { "dn", "up", X86_EFL_DF },
2738 { "ei", "di", X86_EFL_IF },
2739 { "tf", NULL, X86_EFL_TF },
2740 { "nt", "pl", X86_EFL_SF },
2741 { "nz", "zr", X86_EFL_ZF },
2742 { "ac", "na", X86_EFL_AF },
2743 { "po", "pe", X86_EFL_PF },
2744 { "cy", "nc", X86_EFL_CF },
2745 };
2746 char *psz = pszEFlags;
2747 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2748 {
2749 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2750 if (pszAdd)
2751 {
2752 strcpy(psz, pszAdd);
2753 psz += strlen(pszAdd);
2754 *psz++ = ' ';
2755 }
2756 }
2757 psz[-1] = '\0';
2758}
2759
2760
2761/**
2762 * Formats a full register dump.
2763 *
2764 * @param pVM Pointer to the VM.
2765 * @param pCtx The context to format.
2766 * @param pCtxCore The context core to format.
2767 * @param pHlp Output functions.
2768 * @param enmType The dump type.
2769 * @param pszPrefix Register name prefix.
2770 */
2771static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2772 const char *pszPrefix)
2773{
2774 NOREF(pVM);
2775
2776 /*
2777 * Format the EFLAGS.
2778 */
2779 uint32_t efl = pCtxCore->eflags.u32;
2780 char szEFlags[80];
2781 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2782
2783 /*
2784 * Format the registers.
2785 */
2786 switch (enmType)
2787 {
2788 case CPUMDUMPTYPE_TERSE:
2789 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2790 pHlp->pfnPrintf(pHlp,
2791 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2792 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2793 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2794 "%sr14=%016RX64 %sr15=%016RX64\n"
2795 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2796 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2797 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2798 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2799 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2800 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2801 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2802 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2803 else
2804 pHlp->pfnPrintf(pHlp,
2805 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2806 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2807 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2808 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2809 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2810 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2811 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2812 break;
2813
2814 case CPUMDUMPTYPE_DEFAULT:
2815 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2816 pHlp->pfnPrintf(pHlp,
2817 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2818 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2819 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2820 "%sr14=%016RX64 %sr15=%016RX64\n"
2821 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2822 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2823 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2824 ,
2825 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2826 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2827 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2828 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2829 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2830 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2831 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2832 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2833 else
2834 pHlp->pfnPrintf(pHlp,
2835 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2836 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2837 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2838 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2839 ,
2840 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2841 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2842 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2843 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2844 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2845 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2846 break;
2847
2848 case CPUMDUMPTYPE_VERBOSE:
2849 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2850 pHlp->pfnPrintf(pHlp,
2851 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2852 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2853 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2854 "%sr14=%016RX64 %sr15=%016RX64\n"
2855 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2856 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2857 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2858 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2859 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2860 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2861 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2862 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2863 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2864 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2865 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2866 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2867 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2868 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2869 ,
2870 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2871 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2872 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2873 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2874 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2875 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2876 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2877 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2878 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2879 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2880 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2881 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2882 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2883 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2884 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2885 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2886 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2887 else
2888 pHlp->pfnPrintf(pHlp,
2889 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2890 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2891 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2892 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2893 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2894 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2895 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2896 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2897 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2898 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2899 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2900 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2901 ,
2902 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2903 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2904 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2905 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2906 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2907 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2908 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2909 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2910 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2911 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2912 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2913 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2914
2915 pHlp->pfnPrintf(pHlp,
2916 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2917 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2918 ,
2919 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2920 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2921 pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
2922 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2923 );
2924 unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2925 for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2926 {
2927 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2928 unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2929 char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2930 unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2931 uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2932 unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2933 /** @todo This isn't entirenly correct and needs more work! */
2934 pHlp->pfnPrintf(pHlp,
2935 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2936 pszPrefix, iST, pszPrefix, iFPR,
2937 pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2938 uTag, chSign, iInteger, u64Fraction, uExponent);
2939 if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
2940 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2941 pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2942 else
2943 pHlp->pfnPrintf(pHlp, "\n");
2944 }
2945 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2946 pHlp->pfnPrintf(pHlp,
2947 iXMM & 1
2948 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2949 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2950 pszPrefix, iXMM, iXMM < 10 ? " " : "",
2951 pCtx->fpu.aXMM[iXMM].au32[3],
2952 pCtx->fpu.aXMM[iXMM].au32[2],
2953 pCtx->fpu.aXMM[iXMM].au32[1],
2954 pCtx->fpu.aXMM[iXMM].au32[0]);
2955 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2956 if (pCtx->fpu.au32RsrvdRest[i])
2957 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2958 pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2959
2960 pHlp->pfnPrintf(pHlp,
2961 "%sEFER =%016RX64\n"
2962 "%sPAT =%016RX64\n"
2963 "%sSTAR =%016RX64\n"
2964 "%sCSTAR =%016RX64\n"
2965 "%sLSTAR =%016RX64\n"
2966 "%sSFMASK =%016RX64\n"
2967 "%sKERNELGSBASE =%016RX64\n",
2968 pszPrefix, pCtx->msrEFER,
2969 pszPrefix, pCtx->msrPAT,
2970 pszPrefix, pCtx->msrSTAR,
2971 pszPrefix, pCtx->msrCSTAR,
2972 pszPrefix, pCtx->msrLSTAR,
2973 pszPrefix, pCtx->msrSFMASK,
2974 pszPrefix, pCtx->msrKERNELGSBASE);
2975 break;
2976 }
2977}
2978
2979
2980/**
2981 * Display all cpu states and any other cpum info.
2982 *
2983 * @param pVM Pointer to the VM.
2984 * @param pHlp The info helper functions.
2985 * @param pszArgs Arguments, ignored.
2986 */
2987static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2988{
2989 cpumR3InfoGuest(pVM, pHlp, pszArgs);
2990 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2991 cpumR3InfoHyper(pVM, pHlp, pszArgs);
2992 cpumR3InfoHost(pVM, pHlp, pszArgs);
2993}
2994
2995
2996/**
2997 * Parses the info argument.
2998 *
2999 * The argument starts with 'verbose', 'terse' or 'default' and then
3000 * continues with the comment string.
3001 *
3002 * @param pszArgs The pointer to the argument string.
3003 * @param penmType Where to store the dump type request.
3004 * @param ppszComment Where to store the pointer to the comment string.
3005 */
3006static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3007{
3008 if (!pszArgs)
3009 {
3010 *penmType = CPUMDUMPTYPE_DEFAULT;
3011 *ppszComment = "";
3012 }
3013 else
3014 {
3015 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
3016 {
3017 pszArgs += 7;
3018 *penmType = CPUMDUMPTYPE_VERBOSE;
3019 }
3020 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
3021 {
3022 pszArgs += 5;
3023 *penmType = CPUMDUMPTYPE_TERSE;
3024 }
3025 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
3026 {
3027 pszArgs += 7;
3028 *penmType = CPUMDUMPTYPE_DEFAULT;
3029 }
3030 else
3031 *penmType = CPUMDUMPTYPE_DEFAULT;
3032 *ppszComment = RTStrStripL(pszArgs);
3033 }
3034}
3035
3036
3037/**
3038 * Display the guest cpu state.
3039 *
3040 * @param pVM Pointer to the VM.
3041 * @param pHlp The info helper functions.
3042 * @param pszArgs Arguments, ignored.
3043 */
3044static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3045{
3046 CPUMDUMPTYPE enmType;
3047 const char *pszComment;
3048 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3049
3050 /* @todo SMP support! */
3051 PVMCPU pVCpu = VMMGetCpu(pVM);
3052 if (!pVCpu)
3053 pVCpu = &pVM->aCpus[0];
3054
3055 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3056
3057 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
3058 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3059}
3060
3061
3062/**
3063 * Display the current guest instruction
3064 *
3065 * @param pVM Pointer to the VM.
3066 * @param pHlp The info helper functions.
3067 * @param pszArgs Arguments, ignored.
3068 */
3069static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3070{
3071 NOREF(pszArgs);
3072
3073 /** @todo SMP support! */
3074 PVMCPU pVCpu = VMMGetCpu(pVM);
3075 if (!pVCpu)
3076 pVCpu = &pVM->aCpus[0];
3077
3078 char szInstruction[256];
3079 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3080 if (RT_SUCCESS(rc))
3081 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
3082}
3083
3084
3085/**
3086 * Display the hypervisor cpu state.
3087 *
3088 * @param pVM Pointer to the VM.
3089 * @param pHlp The info helper functions.
3090 * @param pszArgs Arguments, ignored.
3091 */
3092static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3093{
3094 CPUMDUMPTYPE enmType;
3095 const char *pszComment;
3096 /* @todo SMP */
3097 PVMCPU pVCpu = &pVM->aCpus[0];
3098
3099 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3100 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3101 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3102 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3103}
3104
3105
3106/**
3107 * Display the host cpu state.
3108 *
3109 * @param pVM Pointer to the VM.
3110 * @param pHlp The info helper functions.
3111 * @param pszArgs Arguments, ignored.
3112 */
3113static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3114{
3115 CPUMDUMPTYPE enmType;
3116 const char *pszComment;
3117 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3118 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3119
3120 /*
3121 * Format the EFLAGS.
3122 */
3123 /* @todo SMP */
3124 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
3125#if HC_ARCH_BITS == 32
3126 uint32_t efl = pCtx->eflags.u32;
3127#else
3128 uint64_t efl = pCtx->rflags;
3129#endif
3130 char szEFlags[80];
3131 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3132
3133 /*
3134 * Format the registers.
3135 */
3136#if HC_ARCH_BITS == 32
3137# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3138 if (!(pCtx->efer & MSR_K6_EFER_LMA))
3139# endif
3140 {
3141 pHlp->pfnPrintf(pHlp,
3142 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3143 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3144 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3145 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3146 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3147 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3148 ,
3149 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
3150 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3151 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3152 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
3153 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3154 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3155 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3156 }
3157# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3158 else
3159# endif
3160#endif
3161#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3162 {
3163 pHlp->pfnPrintf(pHlp,
3164 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3165 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3166 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3167 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3168 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3169 "r14=%016RX64 r15=%016RX64\n"
3170 "iopl=%d %31s\n"
3171 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3172 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3173 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
3174 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3175 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3176 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3177 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3178 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3179 ,
3180 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
3181 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3182 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
3183 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
3184 pCtx->r11, pCtx->r12, pCtx->r13,
3185 pCtx->r14, pCtx->r15,
3186 X86_EFL_GET_IOPL(efl), szEFlags,
3187 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3188 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
3189 pCtx->cr4, pCtx->ldtr, pCtx->tr,
3190 pCtx->dr0, pCtx->dr1, pCtx->dr2,
3191 pCtx->dr3, pCtx->dr6, pCtx->dr7,
3192 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3193 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3194 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3195 }
3196#endif
3197}
3198
3199
3200/**
3201 * Get L1 cache / TLS associativity.
3202 */
3203static const char *getCacheAss(unsigned u, char *pszBuf)
3204{
3205 if (u == 0)
3206 return "res0 ";
3207 if (u == 1)
3208 return "direct";
3209 if (u == 255)
3210 return "fully";
3211 if (u >= 256)
3212 return "???";
3213
3214 RTStrPrintf(pszBuf, 16, "%d way", u);
3215 return pszBuf;
3216}
3217
3218
3219/**
3220 * Get L2 cache associativity.
3221 */
3222const char *getL2CacheAss(unsigned u)
3223{
3224 switch (u)
3225 {
3226 case 0: return "off ";
3227 case 1: return "direct";
3228 case 2: return "2 way ";
3229 case 3: return "res3 ";
3230 case 4: return "4 way ";
3231 case 5: return "res5 ";
3232 case 6: return "8 way ";
3233 case 7: return "res7 ";
3234 case 8: return "16 way";
3235 case 9: return "res9 ";
3236 case 10: return "res10 ";
3237 case 11: return "res11 ";
3238 case 12: return "res12 ";
3239 case 13: return "res13 ";
3240 case 14: return "res14 ";
3241 case 15: return "fully ";
3242 default: return "????";
3243 }
3244}
3245
3246
3247/**
3248 * Display the guest CpuId leaves.
3249 *
3250 * @param pVM Pointer to the VM.
3251 * @param pHlp The info helper functions.
3252 * @param pszArgs "terse", "default" or "verbose".
3253 */
3254static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3255{
3256 /*
3257 * Parse the argument.
3258 */
3259 unsigned iVerbosity = 1;
3260 if (pszArgs)
3261 {
3262 pszArgs = RTStrStripL(pszArgs);
3263 if (!strcmp(pszArgs, "terse"))
3264 iVerbosity--;
3265 else if (!strcmp(pszArgs, "verbose"))
3266 iVerbosity++;
3267 }
3268
3269 /*
3270 * Start cracking.
3271 */
3272 CPUMCPUID Host;
3273 CPUMCPUID Guest;
3274 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
3275
3276 pHlp->pfnPrintf(pHlp,
3277 " RAW Standard CPUIDs\n"
3278 " Function eax ebx ecx edx\n");
3279 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
3280 {
3281 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
3282 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3283
3284 pHlp->pfnPrintf(pHlp,
3285 "Gst: %08x %08x %08x %08x %08x%s\n"
3286 "Hst: %08x %08x %08x %08x\n",
3287 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3288 i <= cStdMax ? "" : "*",
3289 Host.eax, Host.ebx, Host.ecx, Host.edx);
3290 }
3291
3292 /*
3293 * If verbose, decode it.
3294 */
3295 if (iVerbosity)
3296 {
3297 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
3298 pHlp->pfnPrintf(pHlp,
3299 "Name: %.04s%.04s%.04s\n"
3300 "Supports: 0-%x\n",
3301 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3302 }
3303
3304 /*
3305 * Get Features.
3306 */
3307 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
3308 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
3309 pVM->cpum.s.aGuestCpuIdStd[0].edx);
3310 if (cStdMax >= 1 && iVerbosity)
3311 {
3312 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
3313
3314 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
3315 uint32_t uEAX = Guest.eax;
3316
3317 pHlp->pfnPrintf(pHlp,
3318 "Family: %d \tExtended: %d \tEffective: %d\n"
3319 "Model: %d \tExtended: %d \tEffective: %d\n"
3320 "Stepping: %d\n"
3321 "Type: %d (%s)\n"
3322 "APIC ID: %#04x\n"
3323 "Logical CPUs: %d\n"
3324 "CLFLUSH Size: %d\n"
3325 "Brand ID: %#04x\n",
3326 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3327 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3328 ASMGetCpuStepping(uEAX),
3329 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
3330 (Guest.ebx >> 24) & 0xff,
3331 (Guest.ebx >> 16) & 0xff,
3332 (Guest.ebx >> 8) & 0xff,
3333 (Guest.ebx >> 0) & 0xff);
3334 if (iVerbosity == 1)
3335 {
3336 uint32_t uEDX = Guest.edx;
3337 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3338 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3339 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3340 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3341 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3342 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3343 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3344 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3345 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3346 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3347 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3348 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3349 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
3350 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3351 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3352 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3353 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3354 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3355 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3356 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
3357 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
3358 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
3359 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
3360 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
3361 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3362 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3363 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
3364 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
3365 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
3366 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
3367 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
3368 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3369 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
3370 pHlp->pfnPrintf(pHlp, "\n");
3371
3372 uint32_t uECX = Guest.ecx;
3373 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3374 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
3375 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
3376 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
3377 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
3378 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
3379 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
3380 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
3381 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
3382 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
3383 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
3384 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
3385 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
3386 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
3387 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
3388 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
3389 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
3390 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
3391 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
3392 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
3393 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
3394 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
3395 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
3396 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
3397 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
3398 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
3399 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
3400 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
3401 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
3402 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
3403 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
3404 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3405 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
3406 pHlp->pfnPrintf(pHlp, "\n");
3407 }
3408 else
3409 {
3410 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3411
3412 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3413 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3414 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3415 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3416
3417 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3418 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3419 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3420 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3421 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3422 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3423 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3424 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3425 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3426 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3427 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3428 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3429 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3430 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3431 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3432 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3433 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3434 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3435 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3436 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3437 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3438 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3439 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3440 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3441 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3442 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3443 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3444 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3445 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3446 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3447 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3448 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3449 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3450
3451 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3452 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3453 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3454 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3455 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3456 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3457 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3458 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3459 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3460 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3461 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3462 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3463 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3464 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3465 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3466 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3467 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3468 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3469 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3470 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3471 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3472 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3473 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3474 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3475 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3476 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3477 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3478 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3479 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3480 pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3481 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3482 }
3483 }
3484 if (cStdMax >= 2 && iVerbosity)
3485 {
3486 /** @todo */
3487 }
3488
3489 /*
3490 * Extended.
3491 * Implemented after AMD specs.
3492 */
3493 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3494
3495 pHlp->pfnPrintf(pHlp,
3496 "\n"
3497 " RAW Extended CPUIDs\n"
3498 " Function eax ebx ecx edx\n");
3499 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3500 {
3501 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3502 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3503
3504 pHlp->pfnPrintf(pHlp,
3505 "Gst: %08x %08x %08x %08x %08x%s\n"
3506 "Hst: %08x %08x %08x %08x\n",
3507 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3508 i <= cExtMax ? "" : "*",
3509 Host.eax, Host.ebx, Host.ecx, Host.edx);
3510 }
3511
3512 /*
3513 * Understandable output
3514 */
3515 if (iVerbosity)
3516 {
3517 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3518 pHlp->pfnPrintf(pHlp,
3519 "Ext Name: %.4s%.4s%.4s\n"
3520 "Ext Supports: 0x80000000-%#010x\n",
3521 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3522 }
3523
3524 if (iVerbosity && cExtMax >= 1)
3525 {
3526 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3527 uint32_t uEAX = Guest.eax;
3528 pHlp->pfnPrintf(pHlp,
3529 "Family: %d \tExtended: %d \tEffective: %d\n"
3530 "Model: %d \tExtended: %d \tEffective: %d\n"
3531 "Stepping: %d\n"
3532 "Brand ID: %#05x\n",
3533 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3534 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3535 ASMGetCpuStepping(uEAX),
3536 Guest.ebx & 0xfff);
3537
3538 if (iVerbosity == 1)
3539 {
3540 uint32_t uEDX = Guest.edx;
3541 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3542 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3543 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3544 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3545 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3546 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3547 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3548 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3549 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3550 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3551 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3552 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3553 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3554 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3555 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3556 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3557 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3558 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3559 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3560 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3561 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3562 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3563 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3564 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3565 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3566 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3567 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3568 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3569 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3570 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3571 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3572 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3573 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3574 pHlp->pfnPrintf(pHlp, "\n");
3575
3576 uint32_t uECX = Guest.ecx;
3577 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3578 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3579 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3580 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3581 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3582 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3583 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3584 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3585 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3586 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3587 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3588 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3589 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3590 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3591 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3592 for (unsigned iBit = 5; iBit < 32; iBit++)
3593 if (uECX & RT_BIT(iBit))
3594 pHlp->pfnPrintf(pHlp, " %d", iBit);
3595 pHlp->pfnPrintf(pHlp, "\n");
3596 }
3597 else
3598 {
3599 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3600
3601 uint32_t uEdxGst = Guest.edx;
3602 uint32_t uEdxHst = Host.edx;
3603 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3604 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3605 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3606 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3607 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3608 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3609 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3610 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3611 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3612 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3613 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3614 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3615 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3616 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3617 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3618 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3619 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3620 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3621 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3622 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3623 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3624 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3625 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3626 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3627 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3628 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3629 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3630 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3631 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3632 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3633 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3634 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3635 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3636
3637 uint32_t uEcxGst = Guest.ecx;
3638 uint32_t uEcxHst = Host.ecx;
3639 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3640 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3641 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3642 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3643 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3644 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3645 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3646 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3647 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3648 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3649 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3650 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3651 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3652 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3653 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3654 }
3655 }
3656
3657 if (iVerbosity && cExtMax >= 2)
3658 {
3659 char szString[4*4*3+1] = {0};
3660 uint32_t *pu32 = (uint32_t *)szString;
3661 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3662 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3663 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3664 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3665 if (cExtMax >= 3)
3666 {
3667 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3668 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3669 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3670 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3671 }
3672 if (cExtMax >= 4)
3673 {
3674 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3675 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3676 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3677 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3678 }
3679 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3680 }
3681
3682 if (iVerbosity && cExtMax >= 5)
3683 {
3684 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3685 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3686 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3687 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3688 char sz1[32];
3689 char sz2[32];
3690
3691 pHlp->pfnPrintf(pHlp,
3692 "TLB 2/4M Instr/Uni: %s %3d entries\n"
3693 "TLB 2/4M Data: %s %3d entries\n",
3694 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3695 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3696 pHlp->pfnPrintf(pHlp,
3697 "TLB 4K Instr/Uni: %s %3d entries\n"
3698 "TLB 4K Data: %s %3d entries\n",
3699 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3700 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3701 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3702 "L1 Instr Cache Lines Per Tag: %d\n"
3703 "L1 Instr Cache Associativity: %s\n"
3704 "L1 Instr Cache Size: %d KB\n",
3705 (uEDX >> 0) & 0xff,
3706 (uEDX >> 8) & 0xff,
3707 getCacheAss((uEDX >> 16) & 0xff, sz1),
3708 (uEDX >> 24) & 0xff);
3709 pHlp->pfnPrintf(pHlp,
3710 "L1 Data Cache Line Size: %d bytes\n"
3711 "L1 Data Cache Lines Per Tag: %d\n"
3712 "L1 Data Cache Associativity: %s\n"
3713 "L1 Data Cache Size: %d KB\n",
3714 (uECX >> 0) & 0xff,
3715 (uECX >> 8) & 0xff,
3716 getCacheAss((uECX >> 16) & 0xff, sz1),
3717 (uECX >> 24) & 0xff);
3718 }
3719
3720 if (iVerbosity && cExtMax >= 6)
3721 {
3722 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3723 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3724 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3725
3726 pHlp->pfnPrintf(pHlp,
3727 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3728 "L2 TLB 2/4M Data: %s %4d entries\n",
3729 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3730 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3731 pHlp->pfnPrintf(pHlp,
3732 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
3733 "L2 TLB 4K Data: %s %4d entries\n",
3734 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3735 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3736 pHlp->pfnPrintf(pHlp,
3737 "L2 Cache Line Size: %d bytes\n"
3738 "L2 Cache Lines Per Tag: %d\n"
3739 "L2 Cache Associativity: %s\n"
3740 "L2 Cache Size: %d KB\n",
3741 (uEDX >> 0) & 0xff,
3742 (uEDX >> 8) & 0xf,
3743 getL2CacheAss((uEDX >> 12) & 0xf),
3744 (uEDX >> 16) & 0xffff);
3745 }
3746
3747 if (iVerbosity && cExtMax >= 7)
3748 {
3749 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3750
3751 pHlp->pfnPrintf(pHlp, "APM Features: ");
3752 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3753 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3754 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3755 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3756 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3757 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3758 for (unsigned iBit = 6; iBit < 32; iBit++)
3759 if (uEDX & RT_BIT(iBit))
3760 pHlp->pfnPrintf(pHlp, " %d", iBit);
3761 pHlp->pfnPrintf(pHlp, "\n");
3762 }
3763
3764 if (iVerbosity && cExtMax >= 8)
3765 {
3766 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3767 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3768
3769 pHlp->pfnPrintf(pHlp,
3770 "Physical Address Width: %d bits\n"
3771 "Virtual Address Width: %d bits\n"
3772 "Guest Physical Address Width: %d bits\n",
3773 (uEAX >> 0) & 0xff,
3774 (uEAX >> 8) & 0xff,
3775 (uEAX >> 16) & 0xff);
3776 pHlp->pfnPrintf(pHlp,
3777 "Physical Core Count: %d\n",
3778 (uECX >> 0) & 0xff);
3779 }
3780
3781
3782 /*
3783 * Centaur.
3784 */
3785 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3786
3787 pHlp->pfnPrintf(pHlp,
3788 "\n"
3789 " RAW Centaur CPUIDs\n"
3790 " Function eax ebx ecx edx\n");
3791 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3792 {
3793 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3794 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3795
3796 pHlp->pfnPrintf(pHlp,
3797 "Gst: %08x %08x %08x %08x %08x%s\n"
3798 "Hst: %08x %08x %08x %08x\n",
3799 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3800 i <= cCentaurMax ? "" : "*",
3801 Host.eax, Host.ebx, Host.ecx, Host.edx);
3802 }
3803
3804 /*
3805 * Understandable output
3806 */
3807 if (iVerbosity)
3808 {
3809 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3810 pHlp->pfnPrintf(pHlp,
3811 "Centaur Supports: 0xc0000000-%#010x\n",
3812 Guest.eax);
3813 }
3814
3815 if (iVerbosity && cCentaurMax >= 1)
3816 {
3817 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3818 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3819 uint32_t uEdxHst = Host.edx;
3820
3821 if (iVerbosity == 1)
3822 {
3823 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3824 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3825 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3826 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3827 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3828 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3829 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3830 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3831 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3832 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3833 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3834 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3835 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3836 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3837 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3838 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3839 for (unsigned iBit = 14; iBit < 32; iBit++)
3840 if (uEdxGst & RT_BIT(iBit))
3841 pHlp->pfnPrintf(pHlp, " %d", iBit);
3842 pHlp->pfnPrintf(pHlp, "\n");
3843 }
3844 else
3845 {
3846 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3847 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3848 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3849 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3850 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3851 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3852 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3853 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3854 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3855 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3856 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3857 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3858 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3859 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3860 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3861 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3862 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3863 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3864 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3865 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3866 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3867 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3868 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3869 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3870 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3871 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3872 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3873 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3874 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3875 for (unsigned iBit = 27; iBit < 32; iBit++)
3876 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
3877 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3878 pHlp->pfnPrintf(pHlp, "\n");
3879 }
3880 }
3881}
3882
3883
3884/**
3885 * Structure used when disassembling and instructions in DBGF.
3886 * This is used so the reader function can get the stuff it needs.
3887 */
3888typedef struct CPUMDISASSTATE
3889{
3890 /** Pointer to the CPU structure. */
3891 PDISCPUSTATE pCpu;
3892 /** Pointer to the VM. */
3893 PVM pVM;
3894 /** Pointer to the VMCPU. */
3895 PVMCPU pVCpu;
3896 /** Pointer to the first byte in the segment. */
3897 RTGCUINTPTR GCPtrSegBase;
3898 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
3899 RTGCUINTPTR GCPtrSegEnd;
3900 /** The size of the segment minus 1. */
3901 RTGCUINTPTR cbSegLimit;
3902 /** Pointer to the current page - R3 Ptr. */
3903 void const *pvPageR3;
3904 /** Pointer to the current page - GC Ptr. */
3905 RTGCPTR pvPageGC;
3906 /** The lock information that PGMPhysReleasePageMappingLock needs. */
3907 PGMPAGEMAPLOCK PageMapLock;
3908 /** Whether the PageMapLock is valid or not. */
3909 bool fLocked;
3910 /** 64 bits mode or not. */
3911 bool f64Bits;
3912} CPUMDISASSTATE, *PCPUMDISASSTATE;
3913
3914
3915/**
3916 * @callback_method_impl{FNDISREADBYTES}
3917 */
3918static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
3919{
3920 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
3921 for (;;)
3922 {
3923 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
3924
3925 /*
3926 * Need to update the page translation?
3927 */
3928 if ( !pState->pvPageR3
3929 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3930 {
3931 int rc = VINF_SUCCESS;
3932
3933 /* translate the address */
3934 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3935 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3936 && !HWACCMIsEnabled(pState->pVM))
3937 {
3938 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3939 if (!pState->pvPageR3)
3940 rc = VERR_INVALID_POINTER;
3941 }
3942 else
3943 {
3944 /* Release mapping lock previously acquired. */
3945 if (pState->fLocked)
3946 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3947 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3948 pState->fLocked = RT_SUCCESS_NP(rc);
3949 }
3950 if (RT_FAILURE(rc))
3951 {
3952 pState->pvPageR3 = NULL;
3953 return rc;
3954 }
3955 }
3956
3957 /*
3958 * Check the segment limit.
3959 */
3960 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
3961 return VERR_OUT_OF_SELECTOR_BOUNDS;
3962
3963 /*
3964 * Calc how much we can read.
3965 */
3966 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3967 if (!pState->f64Bits)
3968 {
3969 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3970 if (cb > cbSeg && cbSeg)
3971 cb = cbSeg;
3972 }
3973 if (cb > cbMaxRead)
3974 cb = cbMaxRead;
3975
3976 /*
3977 * Read and advance or exit.
3978 */
3979 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3980 offInstr += (uint8_t)cb;
3981 if (cb >= cbMinRead)
3982 {
3983 pDis->cbCachedInstr = offInstr;
3984 return VINF_SUCCESS;
3985 }
3986 cbMinRead -= (uint8_t)cb;
3987 cbMaxRead -= (uint8_t)cb;
3988 }
3989}
3990
3991
3992/**
3993 * Disassemble an instruction and return the information in the provided structure.
3994 *
3995 * @returns VBox status code.
3996 * @param pVM Pointer to the VM.
3997 * @param pVCpu Pointer to the VMCPU.
3998 * @param pCtx Pointer to the guest CPU context.
3999 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4000 * @param pCpu Disassembly state.
4001 * @param pszPrefix String prefix for logging (debug only).
4002 *
4003 */
4004VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
4005{
4006 CPUMDISASSTATE State;
4007 int rc;
4008
4009 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4010 State.pCpu = pCpu;
4011 State.pvPageGC = 0;
4012 State.pvPageR3 = NULL;
4013 State.pVM = pVM;
4014 State.pVCpu = pVCpu;
4015 State.fLocked = false;
4016 State.f64Bits = false;
4017
4018 /*
4019 * Get selector information.
4020 */
4021 DISCPUMODE enmDisCpuMode;
4022 if ( (pCtx->cr0 & X86_CR0_PE)
4023 && pCtx->eflags.Bits.u1VM == 0)
4024 {
4025 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4026 {
4027 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4028 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4029 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4030 }
4031 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4032 State.GCPtrSegBase = pCtx->cs.u64Base;
4033 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4034 State.cbSegLimit = pCtx->cs.u32Limit;
4035 enmDisCpuMode = (State.f64Bits)
4036 ? DISCPUMODE_64BIT
4037 : pCtx->cs.Attr.n.u1DefBig
4038 ? DISCPUMODE_32BIT
4039 : DISCPUMODE_16BIT;
4040 }
4041 else
4042 {
4043 /* real or V86 mode */
4044 enmDisCpuMode = DISCPUMODE_16BIT;
4045 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4046 State.GCPtrSegEnd = 0xFFFFFFFF;
4047 State.cbSegLimit = 0xFFFFFFFF;
4048 }
4049
4050 /*
4051 * Disassemble the instruction.
4052 */
4053 uint32_t cbInstr;
4054#ifndef LOG_ENABLED
4055 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4056 if (RT_SUCCESS(rc))
4057 {
4058#else
4059 char szOutput[160];
4060 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4061 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4062 if (RT_SUCCESS(rc))
4063 {
4064 /* log it */
4065 if (pszPrefix)
4066 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4067 else
4068 Log(("%s", szOutput));
4069#endif
4070 rc = VINF_SUCCESS;
4071 }
4072 else
4073 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4074
4075 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4076 if (State.fLocked)
4077 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4078
4079 return rc;
4080}
4081
4082
4083
4084/**
4085 * API for controlling a few of the CPU features found in CR4.
4086 *
4087 * Currently only X86_CR4_TSD is accepted as input.
4088 *
4089 * @returns VBox status code.
4090 *
4091 * @param pVM Pointer to the VM.
4092 * @param fOr The CR4 OR mask.
4093 * @param fAnd The CR4 AND mask.
4094 */
4095VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4096{
4097 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4098 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4099
4100 pVM->cpum.s.CR4.OrMask &= fAnd;
4101 pVM->cpum.s.CR4.OrMask |= fOr;
4102
4103 return VINF_SUCCESS;
4104}
4105
4106
4107/**
4108 * Gets a pointer to the array of standard CPUID leaves.
4109 *
4110 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
4111 *
4112 * @returns Pointer to the standard CPUID leaves (read-only).
4113 * @param pVM Pointer to the VM.
4114 * @remark Intended for PATM.
4115 */
4116VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
4117{
4118 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
4119}
4120
4121
4122/**
4123 * Gets a pointer to the array of extended CPUID leaves.
4124 *
4125 * CPUMGetGuestCpuIdExtMax() give the size of the array.
4126 *
4127 * @returns Pointer to the extended CPUID leaves (read-only).
4128 * @param pVM Pointer to the VM.
4129 * @remark Intended for PATM.
4130 */
4131VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
4132{
4133 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
4134}
4135
4136
4137/**
4138 * Gets a pointer to the array of centaur CPUID leaves.
4139 *
4140 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
4141 *
4142 * @returns Pointer to the centaur CPUID leaves (read-only).
4143 * @param pVM Pointer to the VM.
4144 * @remark Intended for PATM.
4145 */
4146VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
4147{
4148 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
4149}
4150
4151
4152/**
4153 * Gets a pointer to the default CPUID leaf.
4154 *
4155 * @returns Pointer to the default CPUID leaf (read-only).
4156 * @param pVM Pointer to the VM.
4157 * @remark Intended for PATM.
4158 */
4159VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
4160{
4161 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
4162}
4163
4164
4165/**
4166 * Transforms the guest CPU state to raw-ring mode.
4167 *
4168 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
4169 *
4170 * @returns VBox status. (recompiler failure)
4171 * @param pVCpu Pointer to the VMCPU.
4172 * @param pCtxCore The context core (for trap usage).
4173 * @see @ref pg_raw
4174 */
4175VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
4176{
4177 PVM pVM = pVCpu->CTX_SUFF(pVM);
4178
4179 Assert(!pVCpu->cpum.s.fRawEntered);
4180 Assert(!pVCpu->cpum.s.fRemEntered);
4181 if (!pCtxCore)
4182 pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
4183
4184 /*
4185 * Are we in Ring-0?
4186 */
4187 if ( pCtxCore->ss.Sel && (pCtxCore->ss.Sel & X86_SEL_RPL) == 0
4188 && !pCtxCore->eflags.Bits.u1VM)
4189 {
4190 /*
4191 * Enter execution mode.
4192 */
4193 PATMRawEnter(pVM, pCtxCore);
4194
4195 /*
4196 * Set CPL to Ring-1.
4197 */
4198 pCtxCore->ss.Sel |= 1;
4199 if (pCtxCore->cs.Sel && (pCtxCore->cs.Sel & X86_SEL_RPL) == 0)
4200 pCtxCore->cs.Sel |= 1;
4201 }
4202 else
4203 {
4204 AssertMsg((pCtxCore->ss.Sel & X86_SEL_RPL) >= 2 || pCtxCore->eflags.Bits.u1VM,
4205 ("ring-1 code not supported\n"));
4206 /*
4207 * PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
4208 */
4209 PATMRawEnter(pVM, pCtxCore);
4210 }
4211
4212 /*
4213 * Assert sanity.
4214 */
4215 AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
4216 AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL)
4217 || pCtxCore->eflags.Bits.u1VM,
4218 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
4219 Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) == (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP));
4220
4221 pCtxCore->eflags.u32 |= X86_EFL_IF; /* paranoia */
4222
4223 pVCpu->cpum.s.fRawEntered = true;
4224 return VINF_SUCCESS;
4225}
4226
4227
4228/**
4229 * Transforms the guest CPU state from raw-ring mode to correct values.
4230 *
4231 * This function will change any selector registers with DPL=1 to DPL=0.
4232 *
4233 * @returns Adjusted rc.
4234 * @param pVCpu Pointer to the VMCPU.
4235 * @param rc Raw mode return code
4236 * @param pCtxCore The context core (for trap usage).
4237 * @see @ref pg_raw
4238 */
4239VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
4240{
4241 PVM pVM = pVCpu->CTX_SUFF(pVM);
4242
4243 /*
4244 * Don't leave if we've already left (in GC).
4245 */
4246 Assert(pVCpu->cpum.s.fRawEntered);
4247 Assert(!pVCpu->cpum.s.fRemEntered);
4248 if (!pVCpu->cpum.s.fRawEntered)
4249 return rc;
4250 pVCpu->cpum.s.fRawEntered = false;
4251
4252 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4253 if (!pCtxCore)
4254 pCtxCore = CPUMCTX2CORE(pCtx);
4255 Assert(pCtxCore->eflags.Bits.u1VM || (pCtxCore->ss.Sel & X86_SEL_RPL));
4256 AssertMsg(pCtxCore->eflags.Bits.u1VM || pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss.Sel & X86_SEL_RPL),
4257 ("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss.Sel & X86_SEL_RPL));
4258
4259 /*
4260 * Are we executing in raw ring-1?
4261 */
4262 if ( (pCtxCore->ss.Sel & X86_SEL_RPL) == 1
4263 && !pCtxCore->eflags.Bits.u1VM)
4264 {
4265 /*
4266 * Leave execution mode.
4267 */
4268 PATMRawLeave(pVM, pCtxCore, rc);
4269 /* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
4270 /** @todo See what happens if we remove this. */
4271 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
4272 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
4273 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
4274 pCtxCore->es.Sel &= ~X86_SEL_RPL;
4275 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
4276 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
4277 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
4278 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
4279
4280 /*
4281 * Ring-1 selector => Ring-0.
4282 */
4283 pCtxCore->ss.Sel &= ~X86_SEL_RPL;
4284 if ((pCtxCore->cs.Sel & X86_SEL_RPL) == 1)
4285 pCtxCore->cs.Sel &= ~X86_SEL_RPL;
4286 }
4287 else
4288 {
4289 /*
4290 * PATM is taking care of the IOPL and IF flags for us.
4291 */
4292 PATMRawLeave(pVM, pCtxCore, rc);
4293 if (!pCtxCore->eflags.Bits.u1VM)
4294 {
4295 /** @todo See what happens if we remove this. */
4296 if ((pCtxCore->ds.Sel & X86_SEL_RPL) == 1)
4297 pCtxCore->ds.Sel &= ~X86_SEL_RPL;
4298 if ((pCtxCore->es.Sel & X86_SEL_RPL) == 1)
4299 pCtxCore->es.Sel &= ~X86_SEL_RPL;
4300 if ((pCtxCore->fs.Sel & X86_SEL_RPL) == 1)
4301 pCtxCore->fs.Sel &= ~X86_SEL_RPL;
4302 if ((pCtxCore->gs.Sel & X86_SEL_RPL) == 1)
4303 pCtxCore->gs.Sel &= ~X86_SEL_RPL;
4304 }
4305 }
4306
4307 return rc;
4308}
4309
4310
4311/**
4312 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4313 *
4314 * Only REM should ever call this function!
4315 *
4316 * @returns The changed flags.
4317 * @param pVCpu Pointer to the VMCPU.
4318 * @param puCpl Where to return the current privilege level (CPL).
4319 */
4320VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4321{
4322 Assert(!pVCpu->cpum.s.fRawEntered);
4323 Assert(!pVCpu->cpum.s.fRemEntered);
4324
4325 /*
4326 * Get the CPL first.
4327 */
4328 *puCpl = CPUMGetGuestCPL(pVCpu);
4329
4330 /*
4331 * Get and reset the flags.
4332 */
4333 uint32_t fFlags = pVCpu->cpum.s.fChanged;
4334 pVCpu->cpum.s.fChanged = 0;
4335
4336 /** @todo change the switcher to use the fChanged flags. */
4337 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4338 {
4339 fFlags |= CPUM_CHANGED_FPU_REM;
4340 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4341 }
4342
4343 pVCpu->cpum.s.fRemEntered = true;
4344 return fFlags;
4345}
4346
4347
4348/**
4349 * Leaves REM.
4350 *
4351 * @param pVCpu Pointer to the VMCPU.
4352 * @param fNoOutOfSyncSels This is @c false if there are out of sync
4353 * registers.
4354 */
4355VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4356{
4357 Assert(!pVCpu->cpum.s.fRawEntered);
4358 Assert(pVCpu->cpum.s.fRemEntered);
4359
4360 pVCpu->cpum.s.fRemEntered = false;
4361}
4362
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette