CPUM.cpp@ 76397

Last change on this file since 76397 was 76310, checked in by vboxsync, 6 years ago
VMM/CPUM: Nested VMX: bugref:9180 Initialize VMX CPU features as part of CPUMR3Init now.
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File size: 204.6 KB

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1	/* $Id: CPUM.cpp 76310 2018-12-20 09:57:15Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/patm.h>
120	#include <VBox/vmm/hm.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for CPUMCTX. */
329	static const SSMFIELD g_aCpumX87Fields[] =
330	{
331	SSMFIELD_ENTRY( X86FXSTATE, FCW),
332	SSMFIELD_ENTRY( X86FXSTATE, FSW),
333	SSMFIELD_ENTRY( X86FXSTATE, FTW),
334	SSMFIELD_ENTRY( X86FXSTATE, FOP),
335	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
336	SSMFIELD_ENTRY( X86FXSTATE, CS),
337	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
338	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
339	SSMFIELD_ENTRY( X86FXSTATE, DS),
340	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
341	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
342	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
343	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
344	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
345	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
346	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
347	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
348	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
349	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
350	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
351	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
352	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
353	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
354	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
355	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
356	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
357	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
358	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
359	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
360	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
361	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
362	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
363	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
364	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
365	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
366	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
367	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
368	SSMFIELD_ENTRY_TERM()
369	};
370
371	/** Saved state field descriptors for X86XSAVEHDR. */
372	static const SSMFIELD g_aCpumXSaveHdrFields[] =
373	{
374	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
375	SSMFIELD_ENTRY_TERM()
376	};
377
378	/** Saved state field descriptors for X86XSAVEYMMHI. */
379	static const SSMFIELD g_aCpumYmmHiFields[] =
380	{
381	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
382	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
383	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
384	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
385	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
386	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
387	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
388	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
389	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
390	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
391	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
392	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
393	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
394	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
395	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
396	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
397	SSMFIELD_ENTRY_TERM()
398	};
399
400	/** Saved state field descriptors for X86XSAVEBNDREGS. */
401	static const SSMFIELD g_aCpumBndRegsFields[] =
402	{
403	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
404	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
405	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
406	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
407	SSMFIELD_ENTRY_TERM()
408	};
409
410	/** Saved state field descriptors for X86XSAVEBNDCFG. */
411	static const SSMFIELD g_aCpumBndCfgFields[] =
412	{
413	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
414	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
415	SSMFIELD_ENTRY_TERM()
416	};
417
418	#if 0 /** @todo */
419	/** Saved state field descriptors for X86XSAVEOPMASK. */
420	static const SSMFIELD g_aCpumOpmaskFields[] =
421	{
422	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
423	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
424	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
425	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
426	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
427	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
428	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
429	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
430	SSMFIELD_ENTRY_TERM()
431	};
432	#endif
433
434	/** Saved state field descriptors for X86XSAVEZMMHI256. */
435	static const SSMFIELD g_aCpumZmmHi256Fields[] =
436	{
437	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
438	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
439	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
440	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
441	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
442	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
443	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
444	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
445	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
446	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
447	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
448	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
449	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
450	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
451	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
452	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
453	SSMFIELD_ENTRY_TERM()
454	};
455
456	/** Saved state field descriptors for X86XSAVEZMM16HI. */
457	static const SSMFIELD g_aCpumZmm16HiFields[] =
458	{
459	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
460	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
461	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
462	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
463	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
464	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
465	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
466	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
467	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
468	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
469	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
470	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
471	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
472	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
473	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
474	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
475	SSMFIELD_ENTRY_TERM()
476	};
477
478
479
480	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
481	* registeres changed. */
482	static const SSMFIELD g_aCpumX87FieldsMem[] =
483	{
484	SSMFIELD_ENTRY( X86FXSTATE, FCW),
485	SSMFIELD_ENTRY( X86FXSTATE, FSW),
486	SSMFIELD_ENTRY( X86FXSTATE, FTW),
487	SSMFIELD_ENTRY( X86FXSTATE, FOP),
488	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
489	SSMFIELD_ENTRY( X86FXSTATE, CS),
490	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
491	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
492	SSMFIELD_ENTRY( X86FXSTATE, DS),
493	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
494	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
495	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
496	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
497	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
498	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
499	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
500	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
501	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
502	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
503	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
504	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
505	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
506	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
507	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
508	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
509	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
510	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
511	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
512	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
513	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
514	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
515	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
516	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
517	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
518	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
519	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
520	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
521	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
522	};
523
524	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
525	* registeres changed. */
526	static const SSMFIELD g_aCpumCtxFieldsMem[] =
527	{
528	SSMFIELD_ENTRY( CPUMCTX, rdi),
529	SSMFIELD_ENTRY( CPUMCTX, rsi),
530	SSMFIELD_ENTRY( CPUMCTX, rbp),
531	SSMFIELD_ENTRY( CPUMCTX, rax),
532	SSMFIELD_ENTRY( CPUMCTX, rbx),
533	SSMFIELD_ENTRY( CPUMCTX, rdx),
534	SSMFIELD_ENTRY( CPUMCTX, rcx),
535	SSMFIELD_ENTRY( CPUMCTX, rsp),
536	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
537	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
538	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
539	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
540	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
541	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
542	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
543	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
544	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
545	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
546	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
547	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
548	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
549	SSMFIELD_ENTRY( CPUMCTX, rflags),
550	SSMFIELD_ENTRY( CPUMCTX, rip),
551	SSMFIELD_ENTRY( CPUMCTX, r8),
552	SSMFIELD_ENTRY( CPUMCTX, r9),
553	SSMFIELD_ENTRY( CPUMCTX, r10),
554	SSMFIELD_ENTRY( CPUMCTX, r11),
555	SSMFIELD_ENTRY( CPUMCTX, r12),
556	SSMFIELD_ENTRY( CPUMCTX, r13),
557	SSMFIELD_ENTRY( CPUMCTX, r14),
558	SSMFIELD_ENTRY( CPUMCTX, r15),
559	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
560	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
561	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
562	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
563	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
564	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
565	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
566	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
567	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
568	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
569	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
570	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
571	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
572	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
573	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
574	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
575	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
576	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
577	SSMFIELD_ENTRY( CPUMCTX, cr0),
578	SSMFIELD_ENTRY( CPUMCTX, cr2),
579	SSMFIELD_ENTRY( CPUMCTX, cr3),
580	SSMFIELD_ENTRY( CPUMCTX, cr4),
581	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
582	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
583	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
584	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
585	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
586	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
587	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
588	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
589	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
590	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
591	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
592	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
593	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
594	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
595	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
596	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
597	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
598	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
599	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
600	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
601	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
602	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
603	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
604	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
605	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
606	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
607	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
608	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
609	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
610	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
611	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
612	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
613	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
614	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
615	SSMFIELD_ENTRY_TERM()
616	};
617
618	/** Saved state field descriptors for CPUMCTX_VER1_6. */
619	static const SSMFIELD g_aCpumX87FieldsV16[] =
620	{
621	SSMFIELD_ENTRY( X86FXSTATE, FCW),
622	SSMFIELD_ENTRY( X86FXSTATE, FSW),
623	SSMFIELD_ENTRY( X86FXSTATE, FTW),
624	SSMFIELD_ENTRY( X86FXSTATE, FOP),
625	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
626	SSMFIELD_ENTRY( X86FXSTATE, CS),
627	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
628	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
629	SSMFIELD_ENTRY( X86FXSTATE, DS),
630	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
631	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
632	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
633	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
634	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
635	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
636	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
637	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
638	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
639	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
640	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
641	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
642	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
643	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
644	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
645	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
646	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
647	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
648	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
649	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
650	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
651	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
652	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
653	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
654	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
655	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
656	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
657	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
658	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
659	SSMFIELD_ENTRY_TERM()
660	};
661
662	/** Saved state field descriptors for CPUMCTX_VER1_6. */
663	static const SSMFIELD g_aCpumCtxFieldsV16[] =
664	{
665	SSMFIELD_ENTRY( CPUMCTX, rdi),
666	SSMFIELD_ENTRY( CPUMCTX, rsi),
667	SSMFIELD_ENTRY( CPUMCTX, rbp),
668	SSMFIELD_ENTRY( CPUMCTX, rax),
669	SSMFIELD_ENTRY( CPUMCTX, rbx),
670	SSMFIELD_ENTRY( CPUMCTX, rdx),
671	SSMFIELD_ENTRY( CPUMCTX, rcx),
672	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
673	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
674	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
675	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
676	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
677	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
678	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
679	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
680	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
681	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
682	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
683	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
684	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
685	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
686	SSMFIELD_ENTRY( CPUMCTX, rflags),
687	SSMFIELD_ENTRY( CPUMCTX, rip),
688	SSMFIELD_ENTRY( CPUMCTX, r8),
689	SSMFIELD_ENTRY( CPUMCTX, r9),
690	SSMFIELD_ENTRY( CPUMCTX, r10),
691	SSMFIELD_ENTRY( CPUMCTX, r11),
692	SSMFIELD_ENTRY( CPUMCTX, r12),
693	SSMFIELD_ENTRY( CPUMCTX, r13),
694	SSMFIELD_ENTRY( CPUMCTX, r14),
695	SSMFIELD_ENTRY( CPUMCTX, r15),
696	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
697	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
698	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
699	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
700	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
701	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
702	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
703	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
704	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
705	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
706	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
707	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
708	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
709	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
710	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
711	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
712	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
713	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
714	SSMFIELD_ENTRY( CPUMCTX, cr0),
715	SSMFIELD_ENTRY( CPUMCTX, cr2),
716	SSMFIELD_ENTRY( CPUMCTX, cr3),
717	SSMFIELD_ENTRY( CPUMCTX, cr4),
718	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
719	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
720	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
721	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
722	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
723	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
724	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
725	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
726	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
727	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
728	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
729	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
730	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
731	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
732	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
733	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
734	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
735	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
736	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
737	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
738	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
739	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
740	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
741	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
742	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
743	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
744	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
745	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
746	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
747	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
748	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
749	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
750	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
751	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
752	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
753	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
754	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
755	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
756	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
757	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
758	SSMFIELD_ENTRY_TERM()
759	};
760
761
762	/**
763	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
764	*
765	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
766	* (last instruction pointer, last data pointer, last opcode) except when the ES
767	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
768	* clear these registers there is potential, local FPU leakage from a process
769	* using the FPU to another.
770	*
771	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
772	*
773	* @param pVM The cross context VM structure.
774	*/
775	static void cpumR3CheckLeakyFpu(PVM pVM)
776	{
777	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
778	uint32_t const u32Family = u32CpuVersion >> 8;
779	if ( u32Family >= 6 /* K7 and higher */
780	&& ASMIsAmdCpu())
781	{
782	uint32_t cExt = ASMCpuId_EAX(0x80000000);
783	if (ASMIsValidExtRange(cExt))
784	{
785	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
786	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
787	{
788	for (VMCPUID i = 0; i < pVM->cCpus; i++)
789	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
790	Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
791	}
792	}
793	}
794	}
795
796
797	/**
798	* Frees memory allocated for the SVM hardware virtualization state.
799	*
800	* @param pVM The cross context VM structure.
801	*/
802	static void cpumR3FreeSvmHwVirtState(PVM pVM)
803	{
804	Assert(pVM->cpum.s.GuestFeatures.fSvm);
805	for (VMCPUID i = 0; i < pVM->cCpus; i++)
806	{
807	PVMCPU pVCpu = &pVM->aCpus[i];
808	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
809	{
810	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
811	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
812	}
813	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
814
815	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
816	{
817	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
818	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
819	}
820
821	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
822	{
823	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
824	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
825	}
826	}
827	}
828
829
830	/**
831	* Allocates memory for the SVM hardware virtualization state.
832	*
833	* @returns VBox status code.
834	* @param pVM The cross context VM structure.
835	*/
836	static int cpumR3AllocSvmHwVirtState(PVM pVM)
837	{
838	Assert(pVM->cpum.s.GuestFeatures.fSvm);
839
840	int rc = VINF_SUCCESS;
841	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
842	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
843	for (VMCPUID i = 0; i < pVM->cCpus; i++)
844	{
845	PVMCPU pVCpu = &pVM->aCpus[i];
846	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
847
848	/*
849	* Allocate the nested-guest VMCB.
850	*/
851	SUPPAGE SupNstGstVmcbPage;
852	RT_ZERO(SupNstGstVmcbPage);
853	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
854	Assert(SVM_VMCB_PAGES == 1);
855	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
856	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
857	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
858	if (RT_FAILURE(rc))
859	{
860	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
861	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
862	break;
863	}
864	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
865
866	/*
867	* Allocate the MSRPM (MSR Permission bitmap).
868	*/
869	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
870	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
871	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
872	if (RT_FAILURE(rc))
873	{
874	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
875	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
876	SVM_MSRPM_PAGES));
877	break;
878	}
879
880	/*
881	* Allocate the IOPM (IO Permission bitmap).
882	*/
883	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
884	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
885	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
886	if (RT_FAILURE(rc))
887	{
888	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
889	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
890	SVM_IOPM_PAGES));
891	break;
892	}
893	}
894
895	/* On any failure, cleanup. */
896	if (RT_FAILURE(rc))
897	cpumR3FreeSvmHwVirtState(pVM);
898
899	return rc;
900	}
901
902
903	/**
904	* Initializes (or re-initializes) per-VCPU SVM hardware virtualization state.
905	*
906	* @param pVCpu The cross context virtual CPU structure.
907	*/
908	DECLINLINE(void) cpumR3InitSvmHwVirtState(PVMCPU pVCpu)
909	{
910	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
911	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
912	Assert(pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
913
914	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
915	pCtx->hwvirt.svm.uMsrHSavePa = 0;
916	pCtx->hwvirt.svm.uPrevPauseTick = 0;
917	}
918
919
920	/**
921	* Frees memory allocated for the VMX hardware virtualization state.
922	*
923	* @param pVM The cross context VM structure.
924	*/
925	static void cpumR3FreeVmxHwVirtState(PVM pVM)
926	{
927	Assert(pVM->cpum.s.GuestFeatures.fVmx);
928	for (VMCPUID i = 0; i < pVM->cCpus; i++)
929	{
930	PVMCPU pVCpu = &pVM->aCpus[i];
931	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3)
932	{
933	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3, VMX_V_VMCS_PAGES);
934	pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3 = NULL;
935	}
936	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR3)
937	{
938	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR3, VMX_V_VMCS_PAGES);
939	pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR3 = NULL;
940	}
941	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3)
942	{
943	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3, VMX_V_VIRT_APIC_PAGES);
944	pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3 = NULL;
945	}
946	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3)
947	{
948	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
949	pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3 = NULL;
950	}
951	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3)
952	{
953	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
954	pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3 = NULL;
955	}
956	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3)
957	{
958	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
959	pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3 = NULL;
960	}
961	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR3)
962	{
963	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_PAGES);
964	pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR3 = NULL;
965	}
966	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR3)
967	{
968	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
969	pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR3 = NULL;
970	}
971	}
972	}
973
974
975	/**
976	* Allocates memory for the VMX hardware virtualization state.
977	*
978	* @returns VBox status code.
979	* @param pVM The cross context VM structure.
980	*/
981	static int cpumR3AllocVmxHwVirtState(PVM pVM)
982	{
983	int rc = VINF_SUCCESS;
984	LogRel(("CPUM: Allocating %u pages for the nested-guest VMCS and related structures\n",
985	pVM->cCpus * ( VMX_V_VMCS_PAGES + VMX_V_VIRT_APIC_PAGES + VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * 2
986	+ VMX_V_AUTOMSR_AREA_PAGES)));
987	for (VMCPUID i = 0; i < pVM->cCpus; i++)
988	{
989	PVMCPU pVCpu = &pVM->aCpus[i];
990	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
991
992	/*
993	* Allocate the nested-guest current VMCS.
994	*/
995	Assert(VMX_V_VMCS_PAGES == 1);
996	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3);
997	rc = SUPR3PageAllocEx(VMX_V_VMCS_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3,
998	&pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR0, NULL /* paPages */);
999	if (RT_FAILURE(rc))
1000	{
1001	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3);
1002	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1003	break;
1004	}
1005
1006	/*
1007	* Allocate the nested-guest shadow VMCS.
1008	*/
1009	Assert(VMX_V_VMCS_PAGES == 1);
1010	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR3);
1011	rc = SUPR3PageAllocEx(VMX_V_VMCS_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR3,
1012	&pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR0, NULL /* paPages */);
1013	if (RT_FAILURE(rc))
1014	{
1015	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pShadowVmcsR3);
1016	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's shadow VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1017	break;
1018	}
1019
1020	/*
1021	* Allocate the Virtual-APIC page.
1022	*/
1023	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3);
1024	rc = SUPR3PageAllocEx(VMX_V_VIRT_APIC_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3,
1025	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR0, NULL /* paPages */);
1026	if (RT_FAILURE(rc))
1027	{
1028	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3);
1029	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's Virtual-APIC page\n", pVCpu->idCpu,
1030	VMX_V_VIRT_APIC_PAGES));
1031	break;
1032	}
1033
1034	/*
1035	* Allocate the VMREAD-bitmap.
1036	*/
1037	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3);
1038	rc = SUPR3PageAllocEx(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3,
1039	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR0, NULL /* paPages */);
1040	if (RT_FAILURE(rc))
1041	{
1042	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3);
1043	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMREAD-bitmap\n", pVCpu->idCpu,
1044	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1045	break;
1046	}
1047
1048	/*
1049	* Allocatge the VMWRITE-bitmap.
1050	*/
1051	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3);
1052	rc = SUPR3PageAllocEx(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES, 0 /* fFlags */,
1053	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3,
1054	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR0, NULL /* paPages */);
1055	if (RT_FAILURE(rc))
1056	{
1057	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3);
1058	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMWRITE-bitmap\n", pVCpu->idCpu,
1059	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1060	break;
1061	}
1062
1063	/*
1064	* Allocate the MSR auto-load/store area.
1065	*/
1066	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3);
1067	rc = SUPR3PageAllocEx(VMX_V_AUTOMSR_AREA_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3,
1068	&pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR0, NULL /* paPages */);
1069	if (RT_FAILURE(rc))
1070	{
1071	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3);
1072	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's auto-load/store MSR area\n", pVCpu->idCpu,
1073	VMX_V_AUTOMSR_AREA_PAGES));
1074	break;
1075	}
1076
1077	/*
1078	* Allocate the MSR bitmap.
1079	*/
1080	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR3);
1081	rc = SUPR3PageAllocEx(VMX_V_MSR_BITMAP_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR3,
1082	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR0, NULL /* paPages */);
1083	if (RT_FAILURE(rc))
1084	{
1085	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvMsrBitmapR3);
1086	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR bitmap\n", pVCpu->idCpu,
1087	VMX_V_MSR_BITMAP_PAGES));
1088	break;
1089	}
1090
1091	/*
1092	* Allocate the I/O bitmaps (A and B).
1093	*/
1094	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR3);
1095	rc = SUPR3PageAllocEx(VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES, 0 /* fFlags */,
1096	(void **)&pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR3,
1097	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR0, NULL /* paPages */);
1098	if (RT_FAILURE(rc))
1099	{
1100	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvIoBitmapR3);
1101	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's I/O bitmaps\n", pVCpu->idCpu,
1102	VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES));
1103	break;
1104	}
1105	}
1106
1107	/* On any failure, cleanup. */
1108	if (RT_FAILURE(rc))
1109	cpumR3FreeVmxHwVirtState(pVM);
1110
1111	return rc;
1112	}
1113
1114
1115	/**
1116	* Initializes (or re-initializes) per-VCPU VMX hardware virtualization state.
1117	*
1118	* @param pVCpu The cross context virtual CPU structure.
1119	*/
1120	DECLINLINE(void) cpumR3InitVmxHwVirtState(PVMCPU pVCpu)
1121	{
1122	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1123	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1124	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
1125	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs));
1126
1127	memset(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs), 0, VMX_V_VMCS_SIZE);
1128	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_VMCS_SIZE);
1129	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1130	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1131	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1132	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1133	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1134	/* Don't reset diagnostics here. */
1135	}
1136
1137
1138	/**
1139	* Displays the host and guest VMX features.
1140	*
1141	* @param pVM The cross context VM structure.
1142	* @param pHlp The info helper functions.
1143	* @param pszArgs "terse", "default" or "verbose".
1144	*/
1145	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1146	{
1147	RT_NOREF(pszArgs);
1148	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1149	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1150	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1151	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA)
1152	{
1153	#define VMXFEATDUMP(a_szDesc, a_Var) \
1154	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1155
1156	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1157	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1158	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1159	if (!pGuestFeatures->fVmx)
1160	return;
1161	/* Basic. */
1162	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1163	/* Pin-based controls. */
1164	VMXFEATDUMP("ExtIntExit - External interrupt VM-exit ", fVmxExtIntExit);
1165	VMXFEATDUMP("NmiExit - NMI VM-exit ", fVmxNmiExit);
1166	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1167	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1168	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1169	/* Processor-based controls. */
1170	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1171	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1172	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1173	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1174	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1175	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1176	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1177	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1178	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1179	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1180	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1181	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1182	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1183	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1184	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1185	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1186	VMXFEATDUMP("MonitorTrapFlag - Monitor trap flag ", fVmxMonitorTrapFlag);
1187	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1188	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1189	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1190	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1191	/* Secondary processor-based controls. */
1192	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1193	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1194	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1195	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1196	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1197	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1198	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1199	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1200	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1201	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1202	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1203	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1204	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1205	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1206	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1207	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1208	VMXFEATDUMP("PML - Supports Page-Modification Log (PML) ", fVmxPml);
1209	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1210	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1211	/* VM-entry controls. */
1212	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1213	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1214	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER on VM-entry ", fVmxEntryLoadEferMsr);
1215	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT on VM-entry ", fVmxEntryLoadPatMsr);
1216	/* VM-exit controls. */
1217	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1218	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1219	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1220	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT on VM-exit ", fVmxExitSavePatMsr);
1221	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT on VM-exit ", fVmxExitLoadPatMsr);
1222	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER on VM-exit ", fVmxExitSaveEferMsr);
1223	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER on VM-exit ", fVmxExitLoadEferMsr);
1224	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1225	/* Miscellaneous data. */
1226	VMXFEATDUMP("ExitSaveEferLma - Save EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1227	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxIntelPt);
1228	VMXFEATDUMP("VmwriteAll - Inject softint. with 0-len instr. ", fVmxVmwriteAll);
1229	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1230	#undef VMXFEATDUMP
1231	}
1232	else
1233	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1234	}
1235
1236
1237	/**
1238	* Checks whether VMX nested-guest may be executed using hardware-assisted VMX (e.g,
1239	* using HM or NEM).
1240	*
1241	* @returns @c true if hardware-assisted VMX nested-guest is allowed, @c false
1242	* otherwise.
1243	* @param pVM The cross context VM structure.
1244	*/
1245	static bool cpumR3IsHwAssistVmxNstGstExecAllowed(PVM pVM)
1246	{
1247	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1248	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1249	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1250	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1251	return true;
1252	#endif
1253	return false;
1254	}
1255
1256
1257	/**
1258	* Initializes the guest VMX MSRs from guest-CPU features.
1259	*
1260	* @param pVM The cross context VM structure.
1261	*/
1262	static void cpumR3InitGuestVmxMsrs(PVM pVM)
1263	{
1264	PVMCPU pVCpu0 = &pVM->aCpus[0];
1265	PCCPUMFEATURES pFeatures = &pVM->cpum.s.GuestFeatures;
1266	PVMXMSRS pVmxMsrs = &pVCpu0->cpum.s.Guest.hwvirt.vmx.Msrs;
1267
1268	Assert(pFeatures->fVmx);
1269	RT_ZERO(*pVmxMsrs);
1270
1271	/* Feature control. */
1272	pVmxMsrs->u64FeatCtrl = MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON;
1273
1274	/* Basic information. */
1275	{
1276	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1277	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1278	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pFeatures->fLongMode )
1279	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1280	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1281	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pFeatures->fVmxInsOutInfo)
1282	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, 0 );
1283	pVmxMsrs->u64Basic = u64Basic;
1284	}
1285
1286	/* Pin-based VM-execution controls. */
1287	{
1288	uint32_t const fFeatures = (pFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1289	\| (pFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1290	\| (pFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1291	\| (pFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1292	\| (pFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1293	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1294	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1295	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1296	fAllowed0, fAllowed1, fFeatures));
1297	pVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1298	}
1299
1300	/* Processor-based VM-execution controls. */
1301	{
1302	uint32_t const fFeatures = (pFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1303	\| (pFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1304	\| (pFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1305	\| (pFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1306	\| (pFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1307	\| (pFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1308	\| (pFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1309	\| (pFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1310	\| (pFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1311	\| (pFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1312	\| (pFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1313	\| (pFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1314	\| (pFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1315	\| (pFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1316	\| (pFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1317	\| (pFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1318	\| (pFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1319	\| (pFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1320	\| (pFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1321	\| (pFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1322	\| (pFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1323	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1324	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1325	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1326	fAllowed1, fFeatures));
1327	pVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1328	}
1329
1330	/* Secondary processor-based VM-execution controls. */
1331	if (pFeatures->fVmxSecondaryExecCtls)
1332	{
1333	uint32_t const fFeatures = (pFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1334	\| (pFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1335	\| (pFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1336	\| (pFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1337	\| (pFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1338	\| (pFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1339	\| (pFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1340	\| (pFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT)
1341	\| (pFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1342	\| (pFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1343	\| (pFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1344	\| (pFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1345	\| (pFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1346	\| (pFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1347	\| (pFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1348	\| (pFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1349	\| (pFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1350	\| (pFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1351	\| (pFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1352	\| (pFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT );
1353	uint32_t const fAllowed0 = 0;
1354	uint32_t const fAllowed1 = fFeatures;
1355	pVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1356	}
1357
1358	/* VM-exit controls. */
1359	{
1360	uint32_t const fFeatures = (pFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1361	\| (pFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1362	\| (pFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1363	\| (pFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1364	\| (pFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1365	\| (pFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1366	\| (pFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1367	\| (pFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1368	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1369	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1370	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1371	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1372	fAllowed1, fFeatures));
1373	pVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1374	}
1375
1376	/* VM-entry controls. */
1377	{
1378	uint32_t const fFeatures = (pFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1379	\| (pFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1380	\| (pFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1381	\| (pFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1382	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1383	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1384	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1385	fAllowed1, fFeatures));
1386	pVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1387	}
1388
1389	/* Miscellaneous data. */
1390	{
1391	uint64_t uHostMsr = 0;
1392	if (cpumR3IsHwAssistVmxNstGstExecAllowed(pVM))
1393	HMVmxGetHostMsr(pVM, MSR_IA32_VMX_MISC, &uHostMsr);
1394	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1395	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1396	pVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1397	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pFeatures->fVmxExitSaveEferLma )
1398	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1399	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pFeatures->fVmxIntelPt )
1400	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1401	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1402	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1403	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1404	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pFeatures->fVmxVmwriteAll )
1405	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pFeatures->fVmxEntryInjectSoftInt)
1406	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1407	}
1408
1409	/* CR0 Fixed-0. */
1410	pVmxMsrs->u64Cr0Fixed0 = pFeatures->fVmxUnrestrictedGuest ? VMX_V_CR0_FIXED0_UX: VMX_V_CR0_FIXED0;
1411
1412	/* CR0 Fixed-1. */
1413	{
1414	uint64_t uHostMsr = 0;
1415	if (cpumR3IsHwAssistVmxNstGstExecAllowed(pVM))
1416	HMVmxGetHostMsr(pVM, MSR_IA32_VMX_CR0_FIXED1, &uHostMsr);
1417	pVmxMsrs->u64Cr0Fixed1 = uHostMsr \| VMX_V_CR0_FIXED0; /* Make sure the CR0 MB1 bits are not clear. */
1418	}
1419
1420	/* CR4 Fixed-0. */
1421	pVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1422
1423	/* CR4 Fixed-1. */
1424	{
1425	uint64_t uHostMsr = 0;
1426	if (cpumR3IsHwAssistVmxNstGstExecAllowed(pVM))
1427	HMVmxGetHostMsr(pVM, MSR_IA32_VMX_CR4_FIXED1, &uHostMsr);
1428	pVmxMsrs->u64Cr4Fixed1 = uHostMsr \| VMX_V_CR4_FIXED0; /* Make sure the CR4 MB1 bits are not clear. */
1429	}
1430
1431	/* VMCS Enumeration. */
1432	pVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1433
1434	/* VM Functions. */
1435	if (pFeatures->fVmxVmFunc)
1436	pVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1437
1438	/*
1439	* We don't support the following MSRs yet:
1440	* - True Pin-based VM-execution controls.
1441	* - True Processor-based VM-execution controls.
1442	* - True VM-entry VM-execution controls.
1443	* - True VM-exit VM-execution controls.
1444	* - EPT/VPID capabilities.
1445	*/
1446
1447	/*
1448	* Copy the MSRs values initialized in VCPU 0 to all other VCPUs.
1449	*/
1450	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
1451	{
1452	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1453	Assert(pVCpu);
1454	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
1455	}
1456	}
1457
1458
1459	/**
1460	* Explode VMX features from the provided MSRs.
1461	*
1462	* @param pVmxMsrs Pointer to the VMX MSRs.
1463	* @param pFeatures Pointer to the features struct. to populate.
1464	*/
1465	static void cpumR3ExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURES pFeatures)
1466	{
1467	Assert(pVmxMsrs);
1468	Assert(pFeatures);
1469	Assert(pFeatures->fVmx);
1470
1471	/* Basic information. */
1472	{
1473	uint64_t const u64Basic = pVmxMsrs->u64Basic;
1474	pFeatures->fVmxInsOutInfo = RT_BF_GET(u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1475	}
1476
1477	/* Pin-based VM-execution controls. */
1478	{
1479	uint32_t const fPinCtls = pVmxMsrs->PinCtls.n.allowed1;
1480	pFeatures->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1481	pFeatures->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1482	pFeatures->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1483	pFeatures->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1484	pFeatures->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1485	}
1486
1487	/* Processor-based VM-execution controls. */
1488	{
1489	uint32_t const fProcCtls = pVmxMsrs->ProcCtls.n.allowed1;
1490	pFeatures->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1491	pFeatures->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1492	pFeatures->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1493	pFeatures->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1494	pFeatures->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1495	pFeatures->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1496	pFeatures->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1497	pFeatures->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1498	pFeatures->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1499	pFeatures->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1500	pFeatures->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1501	pFeatures->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1502	pFeatures->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1503	pFeatures->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1504	pFeatures->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1505	pFeatures->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1506	pFeatures->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1507	pFeatures->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1508	pFeatures->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1509	pFeatures->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1510	pFeatures->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1511	}
1512
1513	/* Secondary processor-based VM-execution controls. */
1514	{
1515	uint32_t const fProcCtls2 = pFeatures->fVmxSecondaryExecCtls ? pVmxMsrs->ProcCtls2.n.allowed1 : 0;
1516	pFeatures->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1517	pFeatures->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1518	pFeatures->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1519	pFeatures->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1520	pFeatures->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1521	pFeatures->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1522	pFeatures->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1523	pFeatures->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1524	pFeatures->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1525	pFeatures->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1526	pFeatures->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1527	pFeatures->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1528	pFeatures->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1529	pFeatures->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1530	pFeatures->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1531	pFeatures->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1532	pFeatures->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1533	pFeatures->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_VE);
1534	pFeatures->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1535	pFeatures->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1536	}
1537
1538	/* VM-exit controls. */
1539	{
1540	uint32_t const fExitCtls = pVmxMsrs->ExitCtls.n.allowed1;
1541	pFeatures->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1542	pFeatures->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1543	pFeatures->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1544	pFeatures->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1545	pFeatures->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1546	pFeatures->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1547	pFeatures->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1548	pFeatures->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1549	}
1550
1551	/* VM-entry controls. */
1552	{
1553	uint32_t const fEntryCtls = pVmxMsrs->EntryCtls.n.allowed1;
1554	pFeatures->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1555	pFeatures->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1556	pFeatures->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1557	pFeatures->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1558	}
1559
1560	/* Miscellaneous data. */
1561	{
1562	uint32_t const fMiscData = pVmxMsrs->u64Misc;
1563	pFeatures->fVmxExitSaveEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_SAVE_EFER_LMA);
1564	pFeatures->fVmxIntelPt = RT_BOOL(fMiscData & VMX_MISC_INTEL_PT);
1565	pFeatures->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1566	pFeatures->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1567	}
1568	}
1569
1570
1571	#if 0
1572	/**
1573	* Checks whether the given guest CPU VMX features are compatible with the provided
1574	* base features.
1575	*
1576	* @returns @c true if compatible, @c false otherwise.
1577	* @param pVM The cross context VM structure.
1578	* @param pBase The base VMX CPU features.
1579	* @param pGst The guest VMX CPU features.
1580	*
1581	* @remarks Only VMX feature bits are examined.
1582	*/
1583	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1584	{
1585	if (cpumR3IsHwAssistVmxNstGstExecAllowed(pVM))
1586	{
1587	uint64_t const fBase = ((uint64_t)pBase->fVmxInsOutInfo << 0) \| ((uint64_t)pBase->fVmxExtIntExit << 1)
1588	\| ((uint64_t)pBase->fVmxNmiExit << 2) \| ((uint64_t)pBase->fVmxVirtNmi << 3)
1589	\| ((uint64_t)pBase->fVmxPreemptTimer << 4) \| ((uint64_t)pBase->fVmxPostedInt << 5)
1590	\| ((uint64_t)pBase->fVmxIntWindowExit << 6) \| ((uint64_t)pBase->fVmxTscOffsetting << 7)
1591	\| ((uint64_t)pBase->fVmxHltExit << 8) \| ((uint64_t)pBase->fVmxInvlpgExit << 9)
1592	\| ((uint64_t)pBase->fVmxMwaitExit << 10) \| ((uint64_t)pBase->fVmxRdpmcExit << 11)
1593	\| ((uint64_t)pBase->fVmxRdtscExit << 12) \| ((uint64_t)pBase->fVmxCr3LoadExit << 13)
1594	\| ((uint64_t)pBase->fVmxCr3StoreExit << 14) \| ((uint64_t)pBase->fVmxCr8LoadExit << 15)
1595	\| ((uint64_t)pBase->fVmxCr8StoreExit << 16) \| ((uint64_t)pBase->fVmxUseTprShadow << 17)
1596	\| ((uint64_t)pBase->fVmxNmiWindowExit << 18) \| ((uint64_t)pBase->fVmxMovDRxExit << 19)
1597	\| ((uint64_t)pBase->fVmxUncondIoExit << 20) \| ((uint64_t)pBase->fVmxUseIoBitmaps << 21)
1598	\| ((uint64_t)pBase->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pBase->fVmxUseMsrBitmaps << 23)
1599	\| ((uint64_t)pBase->fVmxMonitorExit << 24) \| ((uint64_t)pBase->fVmxPauseExit << 25)
1600	\| ((uint64_t)pBase->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pBase->fVmxVirtApicAccess << 27)
1601	\| ((uint64_t)pBase->fVmxEpt << 28) \| ((uint64_t)pBase->fVmxDescTableExit << 29)
1602	\| ((uint64_t)pBase->fVmxRdtscp << 30) \| ((uint64_t)pBase->fVmxVirtX2ApicMode << 31)
1603	\| ((uint64_t)pBase->fVmxVpid << 32) \| ((uint64_t)pBase->fVmxWbinvdExit << 33)
1604	\| ((uint64_t)pBase->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pBase->fVmxApicRegVirt << 35)
1605	\| ((uint64_t)pBase->fVmxVirtIntDelivery << 36) \| ((uint64_t)pBase->fVmxPauseLoopExit << 37)
1606	\| ((uint64_t)pBase->fVmxRdrandExit << 38) \| ((uint64_t)pBase->fVmxInvpcid << 39)
1607	\| ((uint64_t)pBase->fVmxVmFunc << 40) \| ((uint64_t)pBase->fVmxVmcsShadowing << 41)
1608	\| ((uint64_t)pBase->fVmxRdseedExit << 42) \| ((uint64_t)pBase->fVmxPml << 43)
1609	\| ((uint64_t)pBase->fVmxEptXcptVe << 44) \| ((uint64_t)pBase->fVmxXsavesXrstors << 45)
1610	\| ((uint64_t)pBase->fVmxUseTscScaling << 46) \| ((uint64_t)pBase->fVmxEntryLoadDebugCtls << 47)
1611	\| ((uint64_t)pBase->fVmxIa32eModeGuest << 48) \| ((uint64_t)pBase->fVmxEntryLoadEferMsr << 49)
1612	\| ((uint64_t)pBase->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pBase->fVmxExitSaveDebugCtls << 51)
1613	\| ((uint64_t)pBase->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pBase->fVmxExitAckExtInt << 53)
1614	\| ((uint64_t)pBase->fVmxExitSavePatMsr << 54) \| ((uint64_t)pBase->fVmxExitLoadPatMsr << 55)
1615	\| ((uint64_t)pBase->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pBase->fVmxExitLoadEferMsr << 57)
1616	\| ((uint64_t)pBase->fVmxSavePreemptTimer << 58) \| ((uint64_t)pBase->fVmxExitSaveEferLma << 59)
1617	\| ((uint64_t)pBase->fVmxIntelPt << 60) \| ((uint64_t)pBase->fVmxVmwriteAll << 61)
1618	\| ((uint64_t)pBase->fVmxEntryInjectSoftInt << 62);
1619
1620	uint64_t const fGst = ((uint64_t)pGst->fVmxInsOutInfo << 0) \| ((uint64_t)pGst->fVmxExtIntExit << 1)
1621	\| ((uint64_t)pGst->fVmxNmiExit << 2) \| ((uint64_t)pGst->fVmxVirtNmi << 3)
1622	\| ((uint64_t)pGst->fVmxPreemptTimer << 4) \| ((uint64_t)pGst->fVmxPostedInt << 5)
1623	\| ((uint64_t)pGst->fVmxIntWindowExit << 6) \| ((uint64_t)pGst->fVmxTscOffsetting << 7)
1624	\| ((uint64_t)pGst->fVmxHltExit << 8) \| ((uint64_t)pGst->fVmxInvlpgExit << 9)
1625	\| ((uint64_t)pGst->fVmxMwaitExit << 10) \| ((uint64_t)pGst->fVmxRdpmcExit << 11)
1626	\| ((uint64_t)pGst->fVmxRdtscExit << 12) \| ((uint64_t)pGst->fVmxCr3LoadExit << 13)
1627	\| ((uint64_t)pGst->fVmxCr3StoreExit << 14) \| ((uint64_t)pGst->fVmxCr8LoadExit << 15)
1628	\| ((uint64_t)pGst->fVmxCr8StoreExit << 16) \| ((uint64_t)pGst->fVmxUseTprShadow << 17)
1629	\| ((uint64_t)pGst->fVmxNmiWindowExit << 18) \| ((uint64_t)pGst->fVmxMovDRxExit << 19)
1630	\| ((uint64_t)pGst->fVmxUncondIoExit << 20) \| ((uint64_t)pGst->fVmxUseIoBitmaps << 21)
1631	\| ((uint64_t)pGst->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pGst->fVmxUseMsrBitmaps << 23)
1632	\| ((uint64_t)pGst->fVmxMonitorExit << 24) \| ((uint64_t)pGst->fVmxPauseExit << 25)
1633	\| ((uint64_t)pGst->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pGst->fVmxVirtApicAccess << 27)
1634	\| ((uint64_t)pGst->fVmxEpt << 28) \| ((uint64_t)pGst->fVmxDescTableExit << 29)
1635	\| ((uint64_t)pGst->fVmxRdtscp << 30) \| ((uint64_t)pGst->fVmxVirtX2ApicMode << 31)
1636	\| ((uint64_t)pGst->fVmxVpid << 32) \| ((uint64_t)pGst->fVmxWbinvdExit << 33)
1637	\| ((uint64_t)pGst->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pGst->fVmxApicRegVirt << 35)
1638	\| ((uint64_t)pGst->fVmxVirtIntDelivery << 36) \| ((uint64_t)pGst->fVmxPauseLoopExit << 37)
1639	\| ((uint64_t)pGst->fVmxRdrandExit << 38) \| ((uint64_t)pGst->fVmxInvpcid << 39)
1640	\| ((uint64_t)pGst->fVmxVmFunc << 40) \| ((uint64_t)pGst->fVmxVmcsShadowing << 41)
1641	\| ((uint64_t)pGst->fVmxRdseedExit << 42) \| ((uint64_t)pGst->fVmxPml << 43)
1642	\| ((uint64_t)pGst->fVmxEptXcptVe << 44) \| ((uint64_t)pGst->fVmxXsavesXrstors << 45)
1643	\| ((uint64_t)pGst->fVmxUseTscScaling << 46) \| ((uint64_t)pGst->fVmxEntryLoadDebugCtls << 47)
1644	\| ((uint64_t)pGst->fVmxIa32eModeGuest << 48) \| ((uint64_t)pGst->fVmxEntryLoadEferMsr << 49)
1645	\| ((uint64_t)pGst->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pGst->fVmxExitSaveDebugCtls << 51)
1646	\| ((uint64_t)pGst->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pGst->fVmxExitAckExtInt << 53)
1647	\| ((uint64_t)pGst->fVmxExitSavePatMsr << 54) \| ((uint64_t)pGst->fVmxExitLoadPatMsr << 55)
1648	\| ((uint64_t)pGst->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pGst->fVmxExitLoadEferMsr << 57)
1649	\| ((uint64_t)pGst->fVmxSavePreemptTimer << 58) \| ((uint64_t)pGst->fVmxExitSaveEferLma << 59)
1650	\| ((uint64_t)pGst->fVmxIntelPt << 60) \| ((uint64_t)pGst->fVmxVmwriteAll << 61)
1651	\| ((uint64_t)pGst->fVmxEntryInjectSoftInt << 62);
1652
1653	if ((fBase \| fGst) != fBase)
1654	return false;
1655	return true;
1656	}
1657	return true;
1658	}
1659	#endif
1660
1661	/**
1662	* Initializes VMX host and guest features.
1663	*
1664	* @param pVM The cross context VM structure.
1665	*
1666	* @remarks This must be called only after HM has fully initialized since it calls
1667	* into HM to retrieve VMX and related MSRs.
1668	*/
1669	static void cpumR3InitVmxCpuFeatures(PVM pVM)
1670	{
1671	/*
1672	* Init. host features.
1673	*/
1674	PCPUMFEATURES pHostFeat = &pVM->cpum.s.HostFeatures;
1675	VMXMSRS VmxMsrs;
1676	if (cpumR3IsHwAssistVmxNstGstExecAllowed(pVM))
1677	{
1678	/** @todo NSTVMX: When NEM support for nested-VMX is there, we'll need to fetch
1679	* the MSRs from NEM or do the support driver IOCTL route, see patch in
1680	* @bugref{9180}. */
1681	if (HMIsEnabled(pVM))
1682	{
1683	int rc = HMVmxGetHostMsrs(pVM, &VmxMsrs);
1684	if (RT_SUCCESS(rc))
1685	cpumR3ExplodeVmxFeatures(&VmxMsrs, pHostFeat);
1686	}
1687	else
1688	AssertMsgFailed(("NEM support for nested-VMX is not implemented yet\n"));
1689	}
1690
1691	/*
1692	* Initialize the set of VMX features we emulate.
1693	* Note! Some bits might be reported as 1 always if they fall under the default1 class bits
1694	* (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1695	*/
1696	CPUMFEATURES EmuFeat;
1697	RT_ZERO(EmuFeat);
1698	EmuFeat.fVmx = 1;
1699	EmuFeat.fVmxInsOutInfo = 0;
1700	EmuFeat.fVmxExtIntExit = 1;
1701	EmuFeat.fVmxNmiExit = 1;
1702	EmuFeat.fVmxVirtNmi = 0;
1703	EmuFeat.fVmxPreemptTimer = 0; /** @todo NSTVMX: enable this. */
1704	EmuFeat.fVmxPostedInt = 0;
1705	EmuFeat.fVmxIntWindowExit = 1;
1706	EmuFeat.fVmxTscOffsetting = 1;
1707	EmuFeat.fVmxHltExit = 1;
1708	EmuFeat.fVmxInvlpgExit = 1;
1709	EmuFeat.fVmxMwaitExit = 1;
1710	EmuFeat.fVmxRdpmcExit = 1;
1711	EmuFeat.fVmxRdtscExit = 1;
1712	EmuFeat.fVmxCr3LoadExit = 1;
1713	EmuFeat.fVmxCr3StoreExit = 1;
1714	EmuFeat.fVmxCr8LoadExit = 1;
1715	EmuFeat.fVmxCr8StoreExit = 1;
1716	EmuFeat.fVmxUseTprShadow = 0;
1717	EmuFeat.fVmxNmiWindowExit = 0;
1718	EmuFeat.fVmxMovDRxExit = 1;
1719	EmuFeat.fVmxUncondIoExit = 1;
1720	EmuFeat.fVmxUseIoBitmaps = 1;
1721	EmuFeat.fVmxMonitorTrapFlag = 0;
1722	EmuFeat.fVmxUseMsrBitmaps = 0;
1723	EmuFeat.fVmxMonitorExit = 1;
1724	EmuFeat.fVmxPauseExit = 1;
1725	EmuFeat.fVmxSecondaryExecCtls = 1;
1726	EmuFeat.fVmxVirtApicAccess = 0;
1727	EmuFeat.fVmxEpt = 0;
1728	EmuFeat.fVmxDescTableExit = 1;
1729	EmuFeat.fVmxRdtscp = 1;
1730	EmuFeat.fVmxVirtX2ApicMode = 0;
1731	EmuFeat.fVmxVpid = 0;
1732	EmuFeat.fVmxWbinvdExit = 1;
1733	EmuFeat.fVmxUnrestrictedGuest = 0;
1734	EmuFeat.fVmxApicRegVirt = 0;
1735	EmuFeat.fVmxVirtIntDelivery = 0;
1736	EmuFeat.fVmxPauseLoopExit = 0;
1737	EmuFeat.fVmxRdrandExit = 0;
1738	EmuFeat.fVmxInvpcid = 1;
1739	EmuFeat.fVmxVmFunc = 0;
1740	EmuFeat.fVmxVmcsShadowing = 0;
1741	EmuFeat.fVmxRdseedExit = 0;
1742	EmuFeat.fVmxPml = 0;
1743	EmuFeat.fVmxEptXcptVe = 0;
1744	EmuFeat.fVmxXsavesXrstors = 0;
1745	EmuFeat.fVmxUseTscScaling = 0;
1746	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1747	EmuFeat.fVmxIa32eModeGuest = 1;
1748	EmuFeat.fVmxEntryLoadEferMsr = 1;
1749	EmuFeat.fVmxEntryLoadPatMsr = 0;
1750	EmuFeat.fVmxExitSaveDebugCtls = 1;
1751	EmuFeat.fVmxHostAddrSpaceSize = 1;
1752	EmuFeat.fVmxExitAckExtInt = 0;
1753	EmuFeat.fVmxExitSavePatMsr = 0;
1754	EmuFeat.fVmxExitLoadPatMsr = 0;
1755	EmuFeat.fVmxExitSaveEferMsr = 1;
1756	EmuFeat.fVmxExitLoadEferMsr = 1;
1757	EmuFeat.fVmxSavePreemptTimer = 0;
1758	EmuFeat.fVmxExitSaveEferLma = 1;
1759	EmuFeat.fVmxIntelPt = 0;
1760	EmuFeat.fVmxVmwriteAll = 0;
1761	EmuFeat.fVmxEntryInjectSoftInt = 0;
1762
1763	/*
1764	* Merge guest features.
1765	*
1766	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1767	* by the hardware, hence we merge our emulated features with the host features below.
1768	*/
1769	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistVmxNstGstExecAllowed(pVM) ? pHostFeat : &EmuFeat;
1770	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1771	pGuestFeat->fVmx = (pBaseFeat->fVmx & EmuFeat.fVmx );
1772	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1773	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1774	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1775	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1776	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1777	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1778	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1779	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1780	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1781	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1782	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1783	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1784	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1785	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1786	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1787	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1788	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1789	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1790	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1791	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1792	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1793	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1794	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1795	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1796	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1797	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1798	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1799	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1800	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1801	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1802	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1803	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1804	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1805	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1806	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1807	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1808	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1809	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1810	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1811	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1812	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1813	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1814	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1815	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1816	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1817	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1818	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1819	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1820	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1821	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1822	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1823	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1824	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1825	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1826	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1827	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1828	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1829	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1830	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1831	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1832	pGuestFeat->fVmxIntelPt = (pBaseFeat->fVmxIntelPt & EmuFeat.fVmxIntelPt );
1833	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1834	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1835
1836	/* Paranoia. */
1837	if (!pGuestFeat->fVmxSecondaryExecCtls)
1838	{
1839	Assert(!pGuestFeat->fVmxVirtApicAccess);
1840	Assert(!pGuestFeat->fVmxEpt);
1841	Assert(!pGuestFeat->fVmxDescTableExit);
1842	Assert(!pGuestFeat->fVmxRdtscp);
1843	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1844	Assert(!pGuestFeat->fVmxVpid);
1845	Assert(!pGuestFeat->fVmxWbinvdExit);
1846	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1847	Assert(!pGuestFeat->fVmxApicRegVirt);
1848	Assert(!pGuestFeat->fVmxVirtIntDelivery);
1849	Assert(!pGuestFeat->fVmxPauseLoopExit);
1850	Assert(!pGuestFeat->fVmxRdrandExit);
1851	Assert(!pGuestFeat->fVmxInvpcid);
1852	Assert(!pGuestFeat->fVmxVmFunc);
1853	Assert(!pGuestFeat->fVmxVmcsShadowing);
1854	Assert(!pGuestFeat->fVmxRdseedExit);
1855	Assert(!pGuestFeat->fVmxPml);
1856	Assert(!pGuestFeat->fVmxEptXcptVe);
1857	Assert(!pGuestFeat->fVmxXsavesXrstors);
1858	Assert(!pGuestFeat->fVmxUseTscScaling);
1859	}
1860
1861	/*
1862	* Finally initialize the VMX guest MSRs after merging the guest features.
1863	*/
1864	cpumR3InitGuestVmxMsrs(pVM);
1865	}
1866
1867
1868	/**
1869	* Initializes the CPUM.
1870	*
1871	* @returns VBox status code.
1872	* @param pVM The cross context VM structure.
1873	*/
1874	VMMR3DECL(int) CPUMR3Init(PVM pVM)
1875	{
1876	LogFlow(("CPUMR3Init\n"));
1877
1878	/*
1879	* Assert alignment, sizes and tables.
1880	*/
1881	AssertCompileMemberAlignment(VM, cpum.s, 32);
1882	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
1883	AssertCompileSizeAlignment(CPUMCTX, 64);
1884	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
1885	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
1886	AssertCompileMemberAlignment(VM, cpum, 64);
1887	AssertCompileMemberAlignment(VM, aCpus, 64);
1888	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
1889	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
1890	#ifdef VBOX_STRICT
1891	int rc2 = cpumR3MsrStrictInitChecks();
1892	AssertRCReturn(rc2, rc2);
1893	#endif
1894
1895	/*
1896	* Initialize offsets.
1897	*/
1898
1899	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
1900	pVM->cpum.s.offCPUMCPU0 = RT_UOFFSETOF(VM, aCpus[0].cpum) - RT_UOFFSETOF(VM, cpum);
1901	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
1902
1903
1904	/* Calculate the offset from CPUMCPU to CPUM. */
1905	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1906	{
1907	PVMCPU pVCpu = &pVM->aCpus[i];
1908
1909	pVCpu->cpum.s.offCPUM = RT_UOFFSETOF_DYN(VM, aCpus[i].cpum) - RT_UOFFSETOF(VM, cpum);
1910	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
1911	}
1912
1913	/*
1914	* Gather info about the host CPU.
1915	*/
1916	if (!ASMHasCpuId())
1917	{
1918	Log(("The CPU doesn't support CPUID!\n"));
1919	return VERR_UNSUPPORTED_CPU;
1920	}
1921
1922	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
1923
1924	PCPUMCPUIDLEAF paLeaves;
1925	uint32_t cLeaves;
1926	int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
1927	AssertLogRelRCReturn(rc, rc);
1928
1929	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
1930	RTMemFree(paLeaves);
1931	AssertLogRelRCReturn(rc, rc);
1932	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
1933
1934	/*
1935	* Check that the CPU supports the minimum features we require.
1936	*/
1937	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
1938	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
1939	if (!pVM->cpum.s.HostFeatures.fMmx)
1940	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
1941	if (!pVM->cpum.s.HostFeatures.fTsc)
1942	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
1943
1944	/*
1945	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
1946	*/
1947	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
1948	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
1949
1950	/*
1951	* Figure out which XSAVE/XRSTOR features are available on the host.
1952	*/
1953	uint64_t fXcr0Host = 0;
1954	uint64_t fXStateHostMask = 0;
1955	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
1956	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
1957	{
1958	fXStateHostMask = fXcr0Host = ASMGetXcr0();
1959	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
1960	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
1961	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
1962	}
1963	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
1964	if (VM_IS_RAW_MODE_ENABLED(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
1965	fXStateHostMask = 0;
1966	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
1967	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
1968
1969	/*
1970	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
1971	*/
1972	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
1973	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
1974	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
1975
1976	uint8_t *pbXStates;
1977	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
1978	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
1979	AssertLogRelRCReturn(rc, rc);
1980
1981	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1982	{
1983	PVMCPU pVCpu = &pVM->aCpus[i];
1984
1985	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1986	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1987	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1988	pbXStates += cbMaxXState;
1989
1990	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1991	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1992	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1993	pbXStates += cbMaxXState;
1994
1995	pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1996	pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1997	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1998	pbXStates += cbMaxXState;
1999
2000	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2001	}
2002
2003	/*
2004	* Register saved state data item.
2005	*/
2006	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2007	NULL, cpumR3LiveExec, NULL,
2008	NULL, cpumR3SaveExec, NULL,
2009	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2010	if (RT_FAILURE(rc))
2011	return rc;
2012
2013	/*
2014	* Register info handlers and registers with the debugger facility.
2015	*/
2016	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2017	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2018	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2019	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2020	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2021	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2022	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2023	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2024	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2025	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2026	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2027	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2028	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
2029	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2030	&cpumR3InfoVmxFeatures);
2031
2032	rc = cpumR3DbgInit(pVM);
2033	if (RT_FAILURE(rc))
2034	return rc;
2035
2036	/*
2037	* Check if we need to workaround partial/leaky FPU handling.
2038	*/
2039	cpumR3CheckLeakyFpu(pVM);
2040
2041	/*
2042	* Initialize the Guest CPUID and MSR states.
2043	*/
2044	rc = cpumR3InitCpuIdAndMsrs(pVM);
2045	if (RT_FAILURE(rc))
2046	return rc;
2047
2048	/*
2049	* Allocate memory required by the guest hardware virtualization state.
2050	*/
2051	if (pVM->cpum.s.GuestFeatures.fVmx)
2052	rc = cpumR3AllocVmxHwVirtState(pVM);
2053	else if (pVM->cpum.s.GuestFeatures.fSvm)
2054	rc = cpumR3AllocSvmHwVirtState(pVM);
2055	else
2056	Assert(pVM->aCpus[0].cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2057	if (RT_FAILURE(rc))
2058	return rc;
2059
2060	/*
2061	* Initialize guest hardware virtualization state.
2062	*/
2063	CPUMHWVIRT const enmHwvirt = pVM->aCpus[0].cpum.s.Guest.hwvirt.enmHwvirt;
2064	if (enmHwvirt == CPUMHWVIRT_VMX)
2065	{
2066	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2067	cpumR3InitVmxHwVirtState(&pVM->aCpus[i]);
2068
2069	/* Initialize VMX features. */
2070	cpumR3InitVmxCpuFeatures(pVM);
2071	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
2072	}
2073	else if (enmHwvirt == CPUMHWVIRT_SVM)
2074	{
2075	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2076	cpumR3InitSvmHwVirtState(&pVM->aCpus[i]);
2077	}
2078
2079	/*
2080	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
2081	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
2082	* of processors from (cpuid(4).eax >> 26) + 1.
2083	*
2084	* Note: this code is obsolete, but let's keep it here for reference.
2085	* Purpose is valid when we artificially cap the max std id to less than 4.
2086	*
2087	* Note: This used to be a separate function CPUMR3SetHwVirt that was called
2088	* after VMINITCOMPLETED_HM.
2089	*/
2090	if (VM_IS_RAW_MODE_ENABLED(pVM))
2091	{
2092	Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
2093	\|\| pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
2094	pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
2095	}
2096
2097	CPUMR3Reset(pVM);
2098	return VINF_SUCCESS;
2099	}
2100
2101
2102	/**
2103	* Applies relocations to data and code managed by this
2104	* component. This function will be called at init and
2105	* whenever the VMM need to relocate it self inside the GC.
2106	*
2107	* The CPUM will update the addresses used by the switcher.
2108	*
2109	* @param pVM The cross context VM structure.
2110	*/
2111	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2112	{
2113	LogFlow(("CPUMR3Relocate\n"));
2114
2115	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
2116	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
2117
2118	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2119	{
2120	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2121	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
2122	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
2123	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
2124
2125	/* Recheck the guest DRx values in raw-mode. */
2126	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
2127	}
2128	}
2129
2130
2131	/**
2132	* Terminates the CPUM.
2133	*
2134	* Termination means cleaning up and freeing all resources,
2135	* the VM it self is at this point powered off or suspended.
2136	*
2137	* @returns VBox status code.
2138	* @param pVM The cross context VM structure.
2139	*/
2140	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2141	{
2142	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2143	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2144	{
2145	PVMCPU pVCpu = &pVM->aCpus[i];
2146	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2147
2148	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2149	pVCpu->cpum.s.uMagic = 0;
2150	pCtx->dr[5] = 0;
2151	}
2152	#endif
2153
2154	if (pVM->cpum.s.GuestFeatures.fVmx)
2155	cpumR3FreeVmxHwVirtState(pVM);
2156	else if (pVM->cpum.s.GuestFeatures.fSvm)
2157	cpumR3FreeSvmHwVirtState(pVM);
2158	return VINF_SUCCESS;
2159	}
2160
2161
2162	/**
2163	* Resets a virtual CPU.
2164	*
2165	* Used by CPUMR3Reset and CPU hot plugging.
2166	*
2167	* @param pVM The cross context VM structure.
2168	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2169	* being reset. This may differ from the current EMT.
2170	*/
2171	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2172	{
2173	/** @todo anything different for VCPU > 0? */
2174	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2175
2176	/*
2177	* Initialize everything to ZERO first.
2178	*/
2179	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2180
2181	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
2182	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
2183	memset(pCtx, 0, RT_UOFFSETOF(CPUMCTX, pXStateR0));
2184
2185	pVCpu->cpum.s.fUseFlags = fUseFlags;
2186
2187	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2188	pCtx->eip = 0x0000fff0;
2189	pCtx->edx = 0x00000600; /* P6 processor */
2190	pCtx->eflags.Bits.u1Reserved0 = 1;
2191
2192	pCtx->cs.Sel = 0xf000;
2193	pCtx->cs.ValidSel = 0xf000;
2194	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2195	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2196	pCtx->cs.u32Limit = 0x0000ffff;
2197	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2198	pCtx->cs.Attr.n.u1Present = 1;
2199	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2200
2201	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2202	pCtx->ds.u32Limit = 0x0000ffff;
2203	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2204	pCtx->ds.Attr.n.u1Present = 1;
2205	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2206
2207	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2208	pCtx->es.u32Limit = 0x0000ffff;
2209	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2210	pCtx->es.Attr.n.u1Present = 1;
2211	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2212
2213	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2214	pCtx->fs.u32Limit = 0x0000ffff;
2215	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2216	pCtx->fs.Attr.n.u1Present = 1;
2217	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2218
2219	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2220	pCtx->gs.u32Limit = 0x0000ffff;
2221	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2222	pCtx->gs.Attr.n.u1Present = 1;
2223	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2224
2225	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2226	pCtx->ss.u32Limit = 0x0000ffff;
2227	pCtx->ss.Attr.n.u1Present = 1;
2228	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2229	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2230
2231	pCtx->idtr.cbIdt = 0xffff;
2232	pCtx->gdtr.cbGdt = 0xffff;
2233
2234	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2235	pCtx->ldtr.u32Limit = 0xffff;
2236	pCtx->ldtr.Attr.n.u1Present = 1;
2237	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2238
2239	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2240	pCtx->tr.u32Limit = 0xffff;
2241	pCtx->tr.Attr.n.u1Present = 1;
2242	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2243
2244	pCtx->dr[6] = X86_DR6_INIT_VAL;
2245	pCtx->dr[7] = X86_DR7_INIT_VAL;
2246
2247	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
2248	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2249	pFpuCtx->FCW = 0x37f;
2250
2251	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2252	IA-32 Processor States Following Power-up, Reset, or INIT */
2253	pFpuCtx->MXCSR = 0x1F80;
2254	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2255
2256	pCtx->aXcr[0] = XSAVE_C_X87;
2257	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2258	{
2259	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2260	as we don't know what happened before. (Bother optimize later?) */
2261	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2262	}
2263
2264	/*
2265	* MSRs.
2266	*/
2267	/* Init PAT MSR */
2268	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2269
2270	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2271	* The Intel docs don't mention it. */
2272	Assert(!pCtx->msrEFER);
2273
2274	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2275	is supposed to be here, just trying provide useful/sensible values. */
2276	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2277	if (pRange)
2278	{
2279	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2280	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2281	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2282	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2283	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2284	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2285	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2286	}
2287
2288	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2289
2290	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2291	* called from each EMT while we're getting called by CPUMR3Reset()
2292	* iteratively on the same thread. Fix later. */
2293	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2294	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2295	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2296	#endif
2297
2298
2299	/* C-state control. Guesses. */
2300	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2301	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2302	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2303	* functionality. The default value must be different due to incompatible write mask.
2304	*/
2305	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2306	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2307	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2308	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2309
2310	/*
2311	* Hardware virtualization state.
2312	*/
2313	CPUMSetGuestGif(pCtx, true);
2314	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2315	if (pVM->cpum.s.GuestFeatures.fVmx)
2316	cpumR3InitVmxHwVirtState(pVCpu);
2317	else if (pVM->cpum.s.GuestFeatures.fSvm)
2318	cpumR3InitSvmHwVirtState(pVCpu);
2319	}
2320
2321
2322	/**
2323	* Resets the CPU.
2324	*
2325	* @returns VINF_SUCCESS.
2326	* @param pVM The cross context VM structure.
2327	*/
2328	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2329	{
2330	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2331	{
2332	CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
2333
2334	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2335	PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
2336
2337	/* Magic marker for searching in crash dumps. */
2338	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
2339	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2340	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2341	#endif
2342	}
2343	}
2344
2345
2346
2347
2348	/**
2349	* Pass 0 live exec callback.
2350	*
2351	* @returns VINF_SSM_DONT_CALL_AGAIN.
2352	* @param pVM The cross context VM structure.
2353	* @param pSSM The saved state handle.
2354	* @param uPass The pass (0).
2355	*/
2356	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2357	{
2358	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2359	cpumR3SaveCpuId(pVM, pSSM);
2360	return VINF_SSM_DONT_CALL_AGAIN;
2361	}
2362
2363
2364	/**
2365	* Execute state save operation.
2366	*
2367	* @returns VBox status code.
2368	* @param pVM The cross context VM structure.
2369	* @param pSSM SSM operation handle.
2370	*/
2371	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2372	{
2373	/*
2374	* Save.
2375	*/
2376	SSMR3PutU32(pSSM, pVM->cCpus);
2377	SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2378	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2379	{
2380	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2381
2382	SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2383
2384	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2385	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2386	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2387	if (pGstCtx->fXStateMask != 0)
2388	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2389	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2390	{
2391	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2392	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2393	}
2394	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2395	{
2396	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2397	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2398	}
2399	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2400	{
2401	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2402	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2403	}
2404	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2405	{
2406	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2407	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2408	}
2409	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2410	{
2411	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2412	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2413	}
2414	if (pVM->cpum.s.GuestFeatures.fSvm)
2415	{
2416	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2417	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2418	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2419	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2420	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2421	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2422	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2423	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2424	g_aSvmHwvirtHostState, NULL /* pvUser */);
2425	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2426	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2427	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2428	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2429	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2430	}
2431	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2432	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2433	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2434	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2435	}
2436
2437	cpumR3SaveCpuId(pVM, pSSM);
2438	return VINF_SUCCESS;
2439	}
2440
2441
2442	/**
2443	* @callback_method_impl{FNSSMINTLOADPREP}
2444	*/
2445	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2446	{
2447	NOREF(pSSM);
2448	pVM->cpum.s.fPendingRestore = true;
2449	return VINF_SUCCESS;
2450	}
2451
2452
2453	/**
2454	* @callback_method_impl{FNSSMINTLOADEXEC}
2455	*/
2456	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2457	{
2458	int rc; /* Only for AssertRCReturn use. */
2459
2460	/*
2461	* Validate version.
2462	*/
2463	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2464	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2465	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2466	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2467	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2468	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2469	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2470	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2471	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2472	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2473	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2474	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2475	{
2476	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2477	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2478	}
2479
2480	if (uPass == SSM_PASS_FINAL)
2481	{
2482	/*
2483	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2484	* really old SSM file versions.)
2485	*/
2486	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2487	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2488	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2489	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2490
2491	/*
2492	* Figure x86 and ctx field definitions to use for older states.
2493	*/
2494	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2495	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2496	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2497	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2498	{
2499	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2500	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2501	}
2502	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2503	{
2504	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2505	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2506	}
2507
2508	/*
2509	* The hyper state used to preceed the CPU count. Starting with
2510	* XSAVE it was moved down till after we've got the count.
2511	*/
2512	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2513	{
2514	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2515	{
2516	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2517	X86FXSTATE Ign;
2518	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2519	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2520	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2521	SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
2522	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2523	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2524	pVCpu->cpum.s.Hyper.rsp = uRSP;
2525	}
2526	}
2527
2528	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2529	{
2530	uint32_t cCpus;
2531	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2532	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2533	VERR_SSM_UNEXPECTED_DATA);
2534	}
2535	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2536	\|\| pVM->cCpus == 1,
2537	("cCpus=%u\n", pVM->cCpus),
2538	VERR_SSM_UNEXPECTED_DATA);
2539
2540	uint32_t cbMsrs = 0;
2541	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2542	{
2543	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2544	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2545	VERR_SSM_UNEXPECTED_DATA);
2546	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2547	VERR_SSM_UNEXPECTED_DATA);
2548	}
2549
2550	/*
2551	* Do the per-CPU restoring.
2552	*/
2553	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2554	{
2555	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2556	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2557
2558	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2559	{
2560	/*
2561	* The XSAVE saved state layout moved the hyper state down here.
2562	*/
2563	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2564	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2565	rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2566	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2567	pVCpu->cpum.s.Hyper.rsp = uRSP;
2568	AssertRCReturn(rc, rc);
2569
2570	/*
2571	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2572	*/
2573	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2574	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2575	AssertRCReturn(rc, rc);
2576
2577	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2578	if (pGstCtx->fXStateMask != 0)
2579	{
2580	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2581	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2582	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2583	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2584	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2585	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2586	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2587	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2588	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2589	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2590	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2591	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2592	}
2593
2594	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2595	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2596	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2597	{
2598	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2599	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2600	VERR_CPUM_INVALID_XCR0);
2601	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2602	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2603	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2604	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2605	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2606	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2607	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2608	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2609	}
2610
2611	/* Check that the XCR1 is zero, as we don't implement it yet. */
2612	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2613
2614	/*
2615	* Restore the individual extended state components we support.
2616	*/
2617	if (pGstCtx->fXStateMask != 0)
2618	{
2619	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
2620	0, g_aCpumXSaveHdrFields, NULL);
2621	AssertRCReturn(rc, rc);
2622	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
2623	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2624	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
2625	VERR_CPUM_INVALID_XSAVE_HDR);
2626	}
2627	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2628	{
2629	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2630	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2631	}
2632	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2633	{
2634	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2635	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2636	}
2637	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2638	{
2639	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2640	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2641	}
2642	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2643	{
2644	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2645	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2646	}
2647	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2648	{
2649	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2650	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2651	}
2652	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2653	{
2654	if (pVM->cpum.s.GuestFeatures.fSvm)
2655	{
2656	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2657	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2658	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2659	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2660	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2661	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2662	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2663	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2664	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2665	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2666	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2667	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2668	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2669	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2670	}
2671	}
2672	}
2673	else
2674	{
2675	/*
2676	* Pre XSAVE saved state.
2677	*/
2678	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
2679	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2680	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2681	}
2682
2683	/*
2684	* Restore a couple of flags and the MSRs.
2685	*/
2686	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2687	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2688
2689	rc = VINF_SUCCESS;
2690	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2691	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2692	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2693	{
2694	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2695	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2696	}
2697	AssertRCReturn(rc, rc);
2698
2699	/* REM and other may have cleared must-be-one fields in DR6 and
2700	DR7, fix these. */
2701	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2702	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2703	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2704	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2705	}
2706
2707	/* Older states does not have the internal selector register flags
2708	and valid selector value. Supply those. */
2709	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2710	{
2711	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2712	{
2713	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2714	bool const fValid = !VM_IS_RAW_MODE_ENABLED(pVM)
2715	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2716	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2717	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2718	if (fValid)
2719	{
2720	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2721	{
2722	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2723	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2724	}
2725
2726	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2727	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2728	}
2729	else
2730	{
2731	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2732	{
2733	paSelReg[iSelReg].fFlags = 0;
2734	paSelReg[iSelReg].ValidSel = 0;
2735	}
2736
2737	/* This might not be 104% correct, but I think it's close
2738	enough for all practical purposes... (REM always loaded
2739	LDTR registers.) */
2740	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2741	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2742	}
2743	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2744	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2745	}
2746	}
2747
2748	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2749	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2750	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2751	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2752	pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2753
2754	/*
2755	* A quick sanity check.
2756	*/
2757	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2758	{
2759	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2760	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2761	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2762	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2763	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2764	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2765	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2766	}
2767	}
2768
2769	pVM->cpum.s.fPendingRestore = false;
2770
2771	/*
2772	* Guest CPUIDs.
2773	*/
2774	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
2775	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2776	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
2777	}
2778
2779
2780	/**
2781	* @callback_method_impl{FNSSMINTLOADDONE}
2782	*/
2783	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2784	{
2785	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2786	return VINF_SUCCESS;
2787
2788	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2789	if (pVM->cpum.s.fPendingRestore)
2790	{
2791	LogRel(("CPUM: Missing state!\n"));
2792	return VERR_INTERNAL_ERROR_2;
2793	}
2794
2795	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2796	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2797	{
2798	PVMCPU pVCpu = &pVM->aCpus[idCpu];
2799
2800	/* Notify PGM of the NXE states in case they've changed. */
2801	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2802
2803	/* During init. this is done in CPUMR3InitCompleted(). */
2804	if (fSupportsLongMode)
2805	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
2806	}
2807	return VINF_SUCCESS;
2808	}
2809
2810
2811	/**
2812	* Checks if the CPUM state restore is still pending.
2813	*
2814	* @returns true / false.
2815	* @param pVM The cross context VM structure.
2816	*/
2817	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2818	{
2819	return pVM->cpum.s.fPendingRestore;
2820	}
2821
2822
2823	/**
2824	* Formats the EFLAGS value into mnemonics.
2825	*
2826	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2827	* @param efl The EFLAGS value.
2828	*/
2829	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2830	{
2831	/*
2832	* Format the flags.
2833	*/
2834	static const struct
2835	{
2836	const char pszSet; const char pszClear; uint32_t fFlag;
2837	} s_aFlags[] =
2838	{
2839	{ "vip",NULL, X86_EFL_VIP },
2840	{ "vif",NULL, X86_EFL_VIF },
2841	{ "ac", NULL, X86_EFL_AC },
2842	{ "vm", NULL, X86_EFL_VM },
2843	{ "rf", NULL, X86_EFL_RF },
2844	{ "nt", NULL, X86_EFL_NT },
2845	{ "ov", "nv", X86_EFL_OF },
2846	{ "dn", "up", X86_EFL_DF },
2847	{ "ei", "di", X86_EFL_IF },
2848	{ "tf", NULL, X86_EFL_TF },
2849	{ "nt", "pl", X86_EFL_SF },
2850	{ "nz", "zr", X86_EFL_ZF },
2851	{ "ac", "na", X86_EFL_AF },
2852	{ "po", "pe", X86_EFL_PF },
2853	{ "cy", "nc", X86_EFL_CF },
2854	};
2855	char *psz = pszEFlags;
2856	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2857	{
2858	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2859	if (pszAdd)
2860	{
2861	strcpy(psz, pszAdd);
2862	psz += strlen(pszAdd);
2863	*psz++ = ' ';
2864	}
2865	}
2866	psz[-1] = '\0';
2867	}
2868
2869
2870	/**
2871	* Formats a full register dump.
2872	*
2873	* @param pVM The cross context VM structure.
2874	* @param pCtx The context to format.
2875	* @param pCtxCore The context core to format.
2876	* @param pHlp Output functions.
2877	* @param enmType The dump type.
2878	* @param pszPrefix Register name prefix.
2879	*/
2880	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2881	const char *pszPrefix)
2882	{
2883	NOREF(pVM);
2884
2885	/*
2886	* Format the EFLAGS.
2887	*/
2888	uint32_t efl = pCtxCore->eflags.u32;
2889	char szEFlags[80];
2890	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2891
2892	/*
2893	* Format the registers.
2894	*/
2895	switch (enmType)
2896	{
2897	case CPUMDUMPTYPE_TERSE:
2898	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2899	pHlp->pfnPrintf(pHlp,
2900	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2901	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2902	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2903	"%sr14=%016RX64 %sr15=%016RX64\n"
2904	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2905	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2906	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2907	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2908	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2909	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2910	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2911	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2912	else
2913	pHlp->pfnPrintf(pHlp,
2914	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2915	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2916	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2917	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2918	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2919	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2920	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2921	break;
2922
2923	case CPUMDUMPTYPE_DEFAULT:
2924	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2925	pHlp->pfnPrintf(pHlp,
2926	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2927	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2928	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2929	"%sr14=%016RX64 %sr15=%016RX64\n"
2930	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2931	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2932	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2933	,
2934	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2935	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2936	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2937	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2938	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2939	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2940	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2941	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2942	else
2943	pHlp->pfnPrintf(pHlp,
2944	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2945	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2946	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2947	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2948	,
2949	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2950	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2951	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2952	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2953	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2954	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2955	break;
2956
2957	case CPUMDUMPTYPE_VERBOSE:
2958	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2959	pHlp->pfnPrintf(pHlp,
2960	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2961	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2962	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2963	"%sr14=%016RX64 %sr15=%016RX64\n"
2964	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2965	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2966	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2967	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2968	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2969	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2970	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2971	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2972	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2973	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2974	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2975	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2976	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2977	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2978	,
2979	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2980	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2981	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2982	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2983	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2984	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2985	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2986	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2987	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2988	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2989	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2990	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2991	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2992	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2993	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2994	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2995	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2996	else
2997	pHlp->pfnPrintf(pHlp,
2998	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2999	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3000	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3001	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3002	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3003	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3004	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3005	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3006	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3007	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3008	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3009	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3010	,
3011	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3012	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3013	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3014	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3015	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3016	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3017	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3018	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3019	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3020	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3021	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3022	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3023
3024	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3025	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3026	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3027	if (pCtx->CTX_SUFF(pXState))
3028	{
3029	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
3030	pHlp->pfnPrintf(pHlp,
3031	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3032	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3033	,
3034	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3035	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3036	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3037	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3038	);
3039	/*
3040	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3041	* not (FP)R0-7 as Intel SDM suggests.
3042	*/
3043	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3044	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3045	{
3046	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3047	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3048	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3049	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3050	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3051	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3052	iExponent -= 16383; /* subtract bias */
3053	/** @todo This isn't entirenly correct and needs more work! */
3054	pHlp->pfnPrintf(pHlp,
3055	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3056	pszPrefix, iST, pszPrefix, iFPR,
3057	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3058	uTag, chSign, iInteger, u64Fraction, iExponent);
3059	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3060	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3061	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3062	else
3063	pHlp->pfnPrintf(pHlp, "\n");
3064	}
3065
3066	/* XMM/YMM/ZMM registers. */
3067	if (pCtx->fXStateMask & XSAVE_C_YMM)
3068	{
3069	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3070	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3071	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3072	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3073	pszPrefix, i, i < 10 ? " " : "",
3074	pYmmHiCtx->aYmmHi[i].au32[3],
3075	pYmmHiCtx->aYmmHi[i].au32[2],
3076	pYmmHiCtx->aYmmHi[i].au32[1],
3077	pYmmHiCtx->aYmmHi[i].au32[0],
3078	pFpuCtx->aXMM[i].au32[3],
3079	pFpuCtx->aXMM[i].au32[2],
3080	pFpuCtx->aXMM[i].au32[1],
3081	pFpuCtx->aXMM[i].au32[0]);
3082	else
3083	{
3084	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3085	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3086	pHlp->pfnPrintf(pHlp,
3087	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3088	pszPrefix, i, i < 10 ? " " : "",
3089	pZmmHi256->aHi256Regs[i].au32[7],
3090	pZmmHi256->aHi256Regs[i].au32[6],
3091	pZmmHi256->aHi256Regs[i].au32[5],
3092	pZmmHi256->aHi256Regs[i].au32[4],
3093	pZmmHi256->aHi256Regs[i].au32[3],
3094	pZmmHi256->aHi256Regs[i].au32[2],
3095	pZmmHi256->aHi256Regs[i].au32[1],
3096	pZmmHi256->aHi256Regs[i].au32[0],
3097	pYmmHiCtx->aYmmHi[i].au32[3],
3098	pYmmHiCtx->aYmmHi[i].au32[2],
3099	pYmmHiCtx->aYmmHi[i].au32[1],
3100	pYmmHiCtx->aYmmHi[i].au32[0],
3101	pFpuCtx->aXMM[i].au32[3],
3102	pFpuCtx->aXMM[i].au32[2],
3103	pFpuCtx->aXMM[i].au32[1],
3104	pFpuCtx->aXMM[i].au32[0]);
3105
3106	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3107	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3108	pHlp->pfnPrintf(pHlp,
3109	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3110	pszPrefix, i + 16,
3111	pZmm16Hi->aRegs[i].au32[15],
3112	pZmm16Hi->aRegs[i].au32[14],
3113	pZmm16Hi->aRegs[i].au32[13],
3114	pZmm16Hi->aRegs[i].au32[12],
3115	pZmm16Hi->aRegs[i].au32[11],
3116	pZmm16Hi->aRegs[i].au32[10],
3117	pZmm16Hi->aRegs[i].au32[9],
3118	pZmm16Hi->aRegs[i].au32[8],
3119	pZmm16Hi->aRegs[i].au32[7],
3120	pZmm16Hi->aRegs[i].au32[6],
3121	pZmm16Hi->aRegs[i].au32[5],
3122	pZmm16Hi->aRegs[i].au32[4],
3123	pZmm16Hi->aRegs[i].au32[3],
3124	pZmm16Hi->aRegs[i].au32[2],
3125	pZmm16Hi->aRegs[i].au32[1],
3126	pZmm16Hi->aRegs[i].au32[0]);
3127	}
3128	}
3129	else
3130	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3131	pHlp->pfnPrintf(pHlp,
3132	i & 1
3133	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3134	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3135	pszPrefix, i, i < 10 ? " " : "",
3136	pFpuCtx->aXMM[i].au32[3],
3137	pFpuCtx->aXMM[i].au32[2],
3138	pFpuCtx->aXMM[i].au32[1],
3139	pFpuCtx->aXMM[i].au32[0]);
3140
3141	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3142	{
3143	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3144	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3145	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3146	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3147	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3148	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3149	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3150	}
3151
3152	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3153	{
3154	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3155	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3156	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3157	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3158	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3159	}
3160
3161	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3162	{
3163	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3164	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3165	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3166	}
3167
3168	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3169	if (pFpuCtx->au32RsrvdRest[i])
3170	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3171	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3172	}
3173
3174	pHlp->pfnPrintf(pHlp,
3175	"%sEFER =%016RX64\n"
3176	"%sPAT =%016RX64\n"
3177	"%sSTAR =%016RX64\n"
3178	"%sCSTAR =%016RX64\n"
3179	"%sLSTAR =%016RX64\n"
3180	"%sSFMASK =%016RX64\n"
3181	"%sKERNELGSBASE =%016RX64\n",
3182	pszPrefix, pCtx->msrEFER,
3183	pszPrefix, pCtx->msrPAT,
3184	pszPrefix, pCtx->msrSTAR,
3185	pszPrefix, pCtx->msrCSTAR,
3186	pszPrefix, pCtx->msrLSTAR,
3187	pszPrefix, pCtx->msrSFMASK,
3188	pszPrefix, pCtx->msrKERNELGSBASE);
3189	break;
3190	}
3191	}
3192
3193
3194	/**
3195	* Display all cpu states and any other cpum info.
3196	*
3197	* @param pVM The cross context VM structure.
3198	* @param pHlp The info helper functions.
3199	* @param pszArgs Arguments, ignored.
3200	*/
3201	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3202	{
3203	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3204	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3205	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3206	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3207	cpumR3InfoHost(pVM, pHlp, pszArgs);
3208	}
3209
3210
3211	/**
3212	* Parses the info argument.
3213	*
3214	* The argument starts with 'verbose', 'terse' or 'default' and then
3215	* continues with the comment string.
3216	*
3217	* @param pszArgs The pointer to the argument string.
3218	* @param penmType Where to store the dump type request.
3219	* @param ppszComment Where to store the pointer to the comment string.
3220	*/
3221	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3222	{
3223	if (!pszArgs)
3224	{
3225	*penmType = CPUMDUMPTYPE_DEFAULT;
3226	*ppszComment = "";
3227	}
3228	else
3229	{
3230	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3231	{
3232	pszArgs += 7;
3233	*penmType = CPUMDUMPTYPE_VERBOSE;
3234	}
3235	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3236	{
3237	pszArgs += 5;
3238	*penmType = CPUMDUMPTYPE_TERSE;
3239	}
3240	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3241	{
3242	pszArgs += 7;
3243	*penmType = CPUMDUMPTYPE_DEFAULT;
3244	}
3245	else
3246	*penmType = CPUMDUMPTYPE_DEFAULT;
3247	*ppszComment = RTStrStripL(pszArgs);
3248	}
3249	}
3250
3251
3252	/**
3253	* Display the guest cpu state.
3254	*
3255	* @param pVM The cross context VM structure.
3256	* @param pHlp The info helper functions.
3257	* @param pszArgs Arguments.
3258	*/
3259	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3260	{
3261	CPUMDUMPTYPE enmType;
3262	const char *pszComment;
3263	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3264
3265	PVMCPU pVCpu = VMMGetCpu(pVM);
3266	if (!pVCpu)
3267	pVCpu = &pVM->aCpus[0];
3268
3269	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3270
3271	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3272	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3273	}
3274
3275
3276	/**
3277	* Displays an SVM VMCB control area.
3278	*
3279	* @param pHlp The info helper functions.
3280	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3281	* @param pszPrefix Caller specified string prefix.
3282	*/
3283	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3284	{
3285	AssertReturnVoid(pHlp);
3286	AssertReturnVoid(pVmcbCtrl);
3287
3288	pHlp->pfnPrintf(pHlp, "%su16InterceptRdCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3289	pHlp->pfnPrintf(pHlp, "%su16InterceptWrCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3290	pHlp->pfnPrintf(pHlp, "%su16InterceptRdDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3291	pHlp->pfnPrintf(pHlp, "%su16InterceptWrDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3292	pHlp->pfnPrintf(pHlp, "%su32InterceptXcpt = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3293	pHlp->pfnPrintf(pHlp, "%su64InterceptCtrl = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3294	pHlp->pfnPrintf(pHlp, "%su16PauseFilterThreshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3295	pHlp->pfnPrintf(pHlp, "%su16PauseFilterCount = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3296	pHlp->pfnPrintf(pHlp, "%su64IOPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3297	pHlp->pfnPrintf(pHlp, "%su64MSRPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3298	pHlp->pfnPrintf(pHlp, "%su64TSCOffset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3299	pHlp->pfnPrintf(pHlp, "%sTLBCtrl\n", pszPrefix);
3300	pHlp->pfnPrintf(pHlp, "%s u32ASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3301	pHlp->pfnPrintf(pHlp, "%s u8TLBFlush = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3302	pHlp->pfnPrintf(pHlp, "%sIntCtrl\n", pszPrefix);
3303	pHlp->pfnPrintf(pHlp, "%s u8VTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3304	pHlp->pfnPrintf(pHlp, "%s u1VIrqPending = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3305	pHlp->pfnPrintf(pHlp, "%s u1VGif = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3306	pHlp->pfnPrintf(pHlp, "%s u4VIntrPrio = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3307	pHlp->pfnPrintf(pHlp, "%s u1IgnoreTPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3308	pHlp->pfnPrintf(pHlp, "%s u1VIntrMasking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3309	pHlp->pfnPrintf(pHlp, "%s u1VGifEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3310	pHlp->pfnPrintf(pHlp, "%s u1AvicEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3311	pHlp->pfnPrintf(pHlp, "%s u8VIntrVector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3312	pHlp->pfnPrintf(pHlp, "%sIntShadow\n", pszPrefix);
3313	pHlp->pfnPrintf(pHlp, "%s u1IntShadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3314	pHlp->pfnPrintf(pHlp, "%s u1GuestIntMask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3315	pHlp->pfnPrintf(pHlp, "%su64ExitCode = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3316	pHlp->pfnPrintf(pHlp, "%su64ExitInfo1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3317	pHlp->pfnPrintf(pHlp, "%su64ExitInfo2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3318	pHlp->pfnPrintf(pHlp, "%sExitIntInfo\n", pszPrefix);
3319	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3320	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3321	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3322	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3323	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3324	pHlp->pfnPrintf(pHlp, "%sNestedPaging and SEV\n", pszPrefix);
3325	pHlp->pfnPrintf(pHlp, "%s u1NestedPaging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3326	pHlp->pfnPrintf(pHlp, "%s u1Sev = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3327	pHlp->pfnPrintf(pHlp, "%s u1SevEs = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3328	pHlp->pfnPrintf(pHlp, "%sAvicBar\n", pszPrefix);
3329	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3330	pHlp->pfnPrintf(pHlp, "%sEventInject\n", pszPrefix);
3331	pHlp->pfnPrintf(pHlp, "%s EventInject\n", pszPrefix);
3332	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3333	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3334	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3335	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3336	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3337	pHlp->pfnPrintf(pHlp, "%su64NestedPagingCR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3338	pHlp->pfnPrintf(pHlp, "%sLBR virtualization\n", pszPrefix);
3339	pHlp->pfnPrintf(pHlp, "%s u1LbrVirt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3340	pHlp->pfnPrintf(pHlp, "%s u1VirtVmsaveVmload = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3341	pHlp->pfnPrintf(pHlp, "%su32VmcbCleanBits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3342	pHlp->pfnPrintf(pHlp, "%su64NextRIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3343	pHlp->pfnPrintf(pHlp, "%scbInstrFetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3344	pHlp->pfnPrintf(pHlp, "%sabInstr = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3345	pHlp->pfnPrintf(pHlp, "%sAvicBackingPagePtr\n", pszPrefix);
3346	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3347	pHlp->pfnPrintf(pHlp, "%sAvicLogicalTablePtr\n", pszPrefix);
3348	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3349	pHlp->pfnPrintf(pHlp, "%sAvicPhysicalTablePtr\n", pszPrefix);
3350	pHlp->pfnPrintf(pHlp, "%s u8LastGuestCoreId = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3351	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3352	}
3353
3354
3355	/**
3356	* Helper for dumping the SVM VMCB selector registers.
3357	*
3358	* @param pHlp The info helper functions.
3359	* @param pSel Pointer to the SVM selector register.
3360	* @param pszName Name of the selector.
3361	* @param pszPrefix Caller specified string prefix.
3362	*/
3363	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3364	{
3365	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3366	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3367	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3368	}
3369
3370
3371	/**
3372	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3373	*
3374	* @param pHlp The info helper functions.
3375	* @param pXdtr Pointer to the descriptor table register.
3376	* @param pszName Name of the descriptor table register.
3377	* @param pszPrefix Caller specified string prefix.
3378	*/
3379	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3380	{
3381	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3382	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3383	}
3384
3385
3386	/**
3387	* Displays an SVM VMCB state-save area.
3388	*
3389	* @param pHlp The info helper functions.
3390	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3391	* @param pszPrefix Caller specified string prefix.
3392	*/
3393	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3394	{
3395	AssertReturnVoid(pHlp);
3396	AssertReturnVoid(pVmcbStateSave);
3397
3398	char szEFlags[80];
3399	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3400
3401	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3402	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3403	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3404	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3405	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3406	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3407	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3408	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3409	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3410	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3411	pHlp->pfnPrintf(pHlp, "%su8CPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3412	pHlp->pfnPrintf(pHlp, "%su64EFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3413	pHlp->pfnPrintf(pHlp, "%su64CR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3414	pHlp->pfnPrintf(pHlp, "%su64CR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3415	pHlp->pfnPrintf(pHlp, "%su64CR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3416	pHlp->pfnPrintf(pHlp, "%su64DR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3417	pHlp->pfnPrintf(pHlp, "%su64DR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3418	pHlp->pfnPrintf(pHlp, "%su64RFlags = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3419	pHlp->pfnPrintf(pHlp, "%su64RIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3420	pHlp->pfnPrintf(pHlp, "%su64RSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3421	pHlp->pfnPrintf(pHlp, "%su64RAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3422	pHlp->pfnPrintf(pHlp, "%su64STAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3423	pHlp->pfnPrintf(pHlp, "%su64LSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3424	pHlp->pfnPrintf(pHlp, "%su64CSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3425	pHlp->pfnPrintf(pHlp, "%su64SFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3426	pHlp->pfnPrintf(pHlp, "%su64KernelGSBase = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3427	pHlp->pfnPrintf(pHlp, "%su64SysEnterCS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3428	pHlp->pfnPrintf(pHlp, "%su64SysEnterEIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3429	pHlp->pfnPrintf(pHlp, "%su64SysEnterESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3430	pHlp->pfnPrintf(pHlp, "%su64CR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3431	pHlp->pfnPrintf(pHlp, "%su64PAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3432	pHlp->pfnPrintf(pHlp, "%su64DBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3433	pHlp->pfnPrintf(pHlp, "%su64BR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3434	pHlp->pfnPrintf(pHlp, "%su64BR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3435	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPFROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3436	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPTO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3437	}
3438
3439
3440	/**
3441	* Display the guest's hardware-virtualization cpu state.
3442	*
3443	* @param pVM The cross context VM structure.
3444	* @param pHlp The info helper functions.
3445	* @param pszArgs Arguments, ignored.
3446	*/
3447	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3448	{
3449	RT_NOREF(pszArgs);
3450
3451	PVMCPU pVCpu = VMMGetCpu(pVM);
3452	if (!pVCpu)
3453	pVCpu = &pVM->aCpus[0];
3454
3455	/*
3456	* Figure out what to dump.
3457	*
3458	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
3459	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
3460	* dump hwvirt. state when the guest CPU is executing a nested-guest.
3461	*/
3462	/** @todo perhaps make this configurable through pszArgs, depending on how much
3463	* noise we wish to accept when nested hwvirt. isn't used. */
3464	#define CPUMHWVIRTDUMP_NONE (0)
3465	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
3466	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
3467	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
3468	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
3469
3470	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3471	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
3472	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
3473	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
3474	uint8_t const idxHwvirtState = fSvm ? CPUMHWVIRTDUMP_SVM : (fVmx ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE);
3475	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
3476	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
3477	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
3478	uint32_t fDumpState = idxHwvirtState \| CPUMHWVIRTDUMP_COMMON;
3479
3480	/*
3481	* Dump it.
3482	*/
3483	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
3484
3485	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
3486	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
3487
3488	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, (fDumpState & (CPUMHWVIRTDUMP_SVM \| CPUMHWVIRTDUMP_VMX)) ?
3489	":" : "");
3490	if (fDumpState & CPUMHWVIRTDUMP_SVM)
3491	{
3492	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
3493
3494	char szEFlags[80];
3495	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
3496	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
3497	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
3498	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
3499	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
3500	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
3501	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.pVmcbR3->guest, " " /* pszPrefix */);
3502	pHlp->pfnPrintf(pHlp, " HostState:\n");
3503	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
3504	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
3505	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
3506	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
3507	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
3508	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
3509	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
3510	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
3511	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
3512	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3513	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
3514	pSel = &pCtx->hwvirt.svm.HostState.cs;
3515	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3516	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
3517	pSel = &pCtx->hwvirt.svm.HostState.ss;
3518	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3519	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
3520	pSel = &pCtx->hwvirt.svm.HostState.ds;
3521	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3522	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
3523	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
3524	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
3525	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
3526	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
3527	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
3528	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
3529	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
3530	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
3531	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
3532	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
3533	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
3534	}
3535
3536	if (fDumpState & CPUMHWVIRTDUMP_VMX)
3537	{
3538	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
3539	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
3540	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
3541	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMVmxGetDiagDesc(pCtx->hwvirt.vmx.enmDiag));
3542	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, HMVmxGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
3543	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
3544	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
3545	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
3546	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
3547	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
3548	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
3549
3550	/** @todo NSTVMX: Dump remaining/new fields. */
3551	}
3552
3553	#undef CPUMHWVIRTDUMP_NONE
3554	#undef CPUMHWVIRTDUMP_COMMON
3555	#undef CPUMHWVIRTDUMP_SVM
3556	#undef CPUMHWVIRTDUMP_VMX
3557	#undef CPUMHWVIRTDUMP_LAST
3558	#undef CPUMHWVIRTDUMP_ALL
3559	}
3560
3561	/**
3562	* Display the current guest instruction
3563	*
3564	* @param pVM The cross context VM structure.
3565	* @param pHlp The info helper functions.
3566	* @param pszArgs Arguments, ignored.
3567	*/
3568	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3569	{
3570	NOREF(pszArgs);
3571
3572	PVMCPU pVCpu = VMMGetCpu(pVM);
3573	if (!pVCpu)
3574	pVCpu = &pVM->aCpus[0];
3575
3576	char szInstruction[256];
3577	szInstruction[0] = '\0';
3578	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3579	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
3580	}
3581
3582
3583	/**
3584	* Display the hypervisor cpu state.
3585	*
3586	* @param pVM The cross context VM structure.
3587	* @param pHlp The info helper functions.
3588	* @param pszArgs Arguments, ignored.
3589	*/
3590	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3591	{
3592	PVMCPU pVCpu = VMMGetCpu(pVM);
3593	if (!pVCpu)
3594	pVCpu = &pVM->aCpus[0];
3595
3596	CPUMDUMPTYPE enmType;
3597	const char *pszComment;
3598	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3599	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3600	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3601	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3602	}
3603
3604
3605	/**
3606	* Display the host cpu state.
3607	*
3608	* @param pVM The cross context VM structure.
3609	* @param pHlp The info helper functions.
3610	* @param pszArgs Arguments, ignored.
3611	*/
3612	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3613	{
3614	CPUMDUMPTYPE enmType;
3615	const char *pszComment;
3616	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3617	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3618
3619	PVMCPU pVCpu = VMMGetCpu(pVM);
3620	if (!pVCpu)
3621	pVCpu = &pVM->aCpus[0];
3622	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
3623
3624	/*
3625	* Format the EFLAGS.
3626	*/
3627	#if HC_ARCH_BITS == 32
3628	uint32_t efl = pCtx->eflags.u32;
3629	#else
3630	uint64_t efl = pCtx->rflags;
3631	#endif
3632	char szEFlags[80];
3633	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3634
3635	/*
3636	* Format the registers.
3637	*/
3638	#if HC_ARCH_BITS == 32
3639	pHlp->pfnPrintf(pHlp,
3640	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3641	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3642	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3643	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3644	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3645	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3646	,
3647	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
3648	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3649	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3650	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
3651	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3652	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3653	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3654	#else
3655	pHlp->pfnPrintf(pHlp,
3656	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3657	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3658	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3659	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3660	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3661	"r14=%016RX64 r15=%016RX64\n"
3662	"iopl=%d %31s\n"
3663	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3664	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3665	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
3666	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3667	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3668	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3669	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3670	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3671	,
3672	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
3673	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3674	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
3675	/pCtx->r8, pCtx->r9,/ pCtx->r10,
3676	pCtx->r11, pCtx->r12, pCtx->r13,
3677	pCtx->r14, pCtx->r15,
3678	X86_EFL_GET_IOPL(efl), szEFlags,
3679	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3680	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
3681	pCtx->cr4, pCtx->ldtr, pCtx->tr,
3682	pCtx->dr0, pCtx->dr1, pCtx->dr2,
3683	pCtx->dr3, pCtx->dr6, pCtx->dr7,
3684	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3685	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3686	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3687	#endif
3688	}
3689
3690	/**
3691	* Structure used when disassembling and instructions in DBGF.
3692	* This is used so the reader function can get the stuff it needs.
3693	*/
3694	typedef struct CPUMDISASSTATE
3695	{
3696	/** Pointer to the CPU structure. */
3697	PDISCPUSTATE pCpu;
3698	/** Pointer to the VM. */
3699	PVM pVM;
3700	/** Pointer to the VMCPU. */
3701	PVMCPU pVCpu;
3702	/** Pointer to the first byte in the segment. */
3703	RTGCUINTPTR GCPtrSegBase;
3704	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3705	RTGCUINTPTR GCPtrSegEnd;
3706	/** The size of the segment minus 1. */
3707	RTGCUINTPTR cbSegLimit;
3708	/** Pointer to the current page - R3 Ptr. */
3709	void const *pvPageR3;
3710	/** Pointer to the current page - GC Ptr. */
3711	RTGCPTR pvPageGC;
3712	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3713	PGMPAGEMAPLOCK PageMapLock;
3714	/** Whether the PageMapLock is valid or not. */
3715	bool fLocked;
3716	/** 64 bits mode or not. */
3717	bool f64Bits;
3718	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3719
3720
3721	/**
3722	* @callback_method_impl{FNDISREADBYTES}
3723	*/
3724	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
3725	{
3726	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
3727	for (;;)
3728	{
3729	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
3730
3731	/*
3732	* Need to update the page translation?
3733	*/
3734	if ( !pState->pvPageR3
3735	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3736	{
3737	int rc = VINF_SUCCESS;
3738
3739	/* translate the address */
3740	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3741	if ( VM_IS_RAW_MODE_ENABLED(pState->pVM)
3742	&& MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
3743	{
3744	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3745	if (!pState->pvPageR3)
3746	rc = VERR_INVALID_POINTER;
3747	}
3748	else
3749	{
3750	/* Release mapping lock previously acquired. */
3751	if (pState->fLocked)
3752	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3753	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3754	pState->fLocked = RT_SUCCESS_NP(rc);
3755	}
3756	if (RT_FAILURE(rc))
3757	{
3758	pState->pvPageR3 = NULL;
3759	return rc;
3760	}
3761	}
3762
3763	/*
3764	* Check the segment limit.
3765	*/
3766	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
3767	return VERR_OUT_OF_SELECTOR_BOUNDS;
3768
3769	/*
3770	* Calc how much we can read.
3771	*/
3772	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3773	if (!pState->f64Bits)
3774	{
3775	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3776	if (cb > cbSeg && cbSeg)
3777	cb = cbSeg;
3778	}
3779	if (cb > cbMaxRead)
3780	cb = cbMaxRead;
3781
3782	/*
3783	* Read and advance or exit.
3784	*/
3785	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3786	offInstr += (uint8_t)cb;
3787	if (cb >= cbMinRead)
3788	{
3789	pDis->cbCachedInstr = offInstr;
3790	return VINF_SUCCESS;
3791	}
3792	cbMinRead -= (uint8_t)cb;
3793	cbMaxRead -= (uint8_t)cb;
3794	}
3795	}
3796
3797
3798	/**
3799	* Disassemble an instruction and return the information in the provided structure.
3800	*
3801	* @returns VBox status code.
3802	* @param pVM The cross context VM structure.
3803	* @param pVCpu The cross context virtual CPU structure.
3804	* @param pCtx Pointer to the guest CPU context.
3805	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3806	* @param pCpu Disassembly state.
3807	* @param pszPrefix String prefix for logging (debug only).
3808	*
3809	*/
3810	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
3811	const char *pszPrefix)
3812	{
3813	CPUMDISASSTATE State;
3814	int rc;
3815
3816	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3817	State.pCpu = pCpu;
3818	State.pvPageGC = 0;
3819	State.pvPageR3 = NULL;
3820	State.pVM = pVM;
3821	State.pVCpu = pVCpu;
3822	State.fLocked = false;
3823	State.f64Bits = false;
3824
3825	/*
3826	* Get selector information.
3827	*/
3828	DISCPUMODE enmDisCpuMode;
3829	if ( (pCtx->cr0 & X86_CR0_PE)
3830	&& pCtx->eflags.Bits.u1VM == 0)
3831	{
3832	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
3833	{
3834	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3835	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
3836	# endif
3837	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
3838	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
3839	}
3840	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
3841	State.GCPtrSegBase = pCtx->cs.u64Base;
3842	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
3843	State.cbSegLimit = pCtx->cs.u32Limit;
3844	enmDisCpuMode = (State.f64Bits)
3845	? DISCPUMODE_64BIT
3846	: pCtx->cs.Attr.n.u1DefBig
3847	? DISCPUMODE_32BIT
3848	: DISCPUMODE_16BIT;
3849	}
3850	else
3851	{
3852	/* real or V86 mode */
3853	enmDisCpuMode = DISCPUMODE_16BIT;
3854	State.GCPtrSegBase = pCtx->cs.Sel * 16;
3855	State.GCPtrSegEnd = 0xFFFFFFFF;
3856	State.cbSegLimit = 0xFFFFFFFF;
3857	}
3858
3859	/*
3860	* Disassemble the instruction.
3861	*/
3862	uint32_t cbInstr;
3863	#ifndef LOG_ENABLED
3864	RT_NOREF_PV(pszPrefix);
3865	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
3866	if (RT_SUCCESS(rc))
3867	{
3868	#else
3869	char szOutput[160];
3870	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
3871	pCpu, &cbInstr, szOutput, sizeof(szOutput));
3872	if (RT_SUCCESS(rc))
3873	{
3874	/* log it */
3875	if (pszPrefix)
3876	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3877	else
3878	Log(("%s", szOutput));
3879	#endif
3880	rc = VINF_SUCCESS;
3881	}
3882	else
3883	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
3884
3885	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3886	if (State.fLocked)
3887	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3888
3889	return rc;
3890	}
3891
3892
3893
3894	/**
3895	* API for controlling a few of the CPU features found in CR4.
3896	*
3897	* Currently only X86_CR4_TSD is accepted as input.
3898	*
3899	* @returns VBox status code.
3900	*
3901	* @param pVM The cross context VM structure.
3902	* @param fOr The CR4 OR mask.
3903	* @param fAnd The CR4 AND mask.
3904	*/
3905	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3906	{
3907	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3908	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3909
3910	pVM->cpum.s.CR4.OrMask &= fAnd;
3911	pVM->cpum.s.CR4.OrMask \|= fOr;
3912
3913	return VINF_SUCCESS;
3914	}
3915
3916
3917	/**
3918	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3919	*
3920	* Only REM should ever call this function!
3921	*
3922	* @returns The changed flags.
3923	* @param pVCpu The cross context virtual CPU structure.
3924	* @param puCpl Where to return the current privilege level (CPL).
3925	*/
3926	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3927	{
3928	Assert(!pVCpu->cpum.s.fRawEntered);
3929	Assert(!pVCpu->cpum.s.fRemEntered);
3930
3931	/*
3932	* Get the CPL first.
3933	*/
3934	*puCpl = CPUMGetGuestCPL(pVCpu);
3935
3936	/*
3937	* Get and reset the flags.
3938	*/
3939	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3940	pVCpu->cpum.s.fChanged = 0;
3941
3942	/** @todo change the switcher to use the fChanged flags. */
3943	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3944	{
3945	fFlags \|= CPUM_CHANGED_FPU_REM;
3946	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3947	}
3948
3949	pVCpu->cpum.s.fRemEntered = true;
3950	return fFlags;
3951	}
3952
3953
3954	/**
3955	* Leaves REM.
3956	*
3957	* @param pVCpu The cross context virtual CPU structure.
3958	* @param fNoOutOfSyncSels This is @c false if there are out of sync
3959	* registers.
3960	*/
3961	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
3962	{
3963	Assert(!pVCpu->cpum.s.fRawEntered);
3964	Assert(pVCpu->cpum.s.fRemEntered);
3965
3966	RT_NOREF_PV(fNoOutOfSyncSels);
3967
3968	pVCpu->cpum.s.fRemEntered = false;
3969	}
3970
3971
3972	/**
3973	* Called when the ring-3 init phase completes.
3974	*
3975	* @returns VBox status code.
3976	* @param pVM The cross context VM structure.
3977	* @param enmWhat Which init phase.
3978	*/
3979	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
3980	{
3981	switch (enmWhat)
3982	{
3983	case VMINITCOMPLETED_RING3:
3984	{
3985	/*
3986	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
3987	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
3988	*/
3989	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3990	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3991	{
3992	PVMCPU pVCpu = &pVM->aCpus[i];
3993	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
3994	if (fSupportsLongMode)
3995	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3996	}
3997
3998	/* Register statistic counters for MSRs. */
3999	cpumR3MsrRegStats(pVM);
4000	break;
4001	}
4002
4003	default:
4004	break;
4005	}
4006	return VINF_SUCCESS;
4007	}
4008
4009
4010	/**
4011	* Called when the ring-0 init phases completed.
4012	*
4013	* @param pVM The cross context VM structure.
4014	*/
4015	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
4016	{
4017	/*
4018	* Log the cpuid.
4019	*/
4020	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4021	RTCPUSET OnlineSet;
4022	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4023	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4024	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4025	RTCPUID cCores = RTMpGetCoreCount();
4026	if (cCores)
4027	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4028	LogRel(("*********************** CPUID dump **********************\n"));
4029	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4030	LogRel(("\n"));
4031	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4032	RTLogRelSetBuffering(fOldBuffered);
4033	LogRel(("****************** End of CPUID dump ********************\n"));
4034	}
4035

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 76397

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