CPUMR3CpuId.cpp@ 49966

Last change on this file since 49966 was 49893, checked in by vboxsync, 11 years ago
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1	/* $Id: CPUMR3CpuId.cpp 49893 2013-12-13 00:40:20Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_CPUM
22	#include <VBox/vmm/cpum.h>
23	#include "CPUMInternal.h"
24	#include <VBox/vmm/vm.h>
25
26	#include <VBox/err.h>
27	#include <iprt/asm-amd64-x86.h>
28	#include <iprt/ctype.h>
29	#include <iprt/mem.h>
30	#include <iprt/stream.h>
31	#include <iprt/string.h>
32
33
34	/*******************************************************************************
35	* Global Variables *
36	*******************************************************************************/
37	/**
38	* The intel pentium family.
39	*/
40	static const CPUMMICROARCH g_aenmIntelFamily06[] =
41	{
42	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
43	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
44	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
45	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
46	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
47	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
48	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
49	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
50	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
51	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
52	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
53	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
54	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
55	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
56	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
57	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
58	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
59	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
60	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
61	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
63	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
64	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
65	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
66	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
67	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
68	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
69	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
70	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
71	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
72	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
73	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
74	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
75	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
80	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
81	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
82	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
83	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
85	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
86	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
87	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
88	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
89	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
90	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
91	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
96	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
97	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
98	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
99	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
101	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
102	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
103	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
104	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
105	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
106	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
107	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
112	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
113	/* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
114	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
115	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
117	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
118	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
120	/* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
121	/* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
122	};
123
124
125
126	/**
127	* Figures out the (sub-)micro architecture given a bit of CPUID info.
128	*
129	* @returns Micro architecture.
130	* @param enmVendor The CPU vendor .
131	* @param bFamily The CPU family.
132	* @param bModel The CPU model.
133	* @param bStepping The CPU stepping.
134	*/
135	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
136	uint8_t bModel, uint8_t bStepping)
137	{
138	if (enmVendor == CPUMCPUVENDOR_AMD)
139	{
140	switch (bFamily)
141	{
142	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
143	case 0x03: return kCpumMicroarch_AMD_Am386;
144	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
145	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
146	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
147	case 0x06:
148	switch (bModel)
149	{
150	case 0: kCpumMicroarch_AMD_K7_Palomino;
151	case 1: kCpumMicroarch_AMD_K7_Palomino;
152	case 2: kCpumMicroarch_AMD_K7_Palomino;
153	case 3: kCpumMicroarch_AMD_K7_Spitfire;
154	case 4: kCpumMicroarch_AMD_K7_Thunderbird;
155	case 6: kCpumMicroarch_AMD_K7_Palomino;
156	case 7: kCpumMicroarch_AMD_K7_Morgan;
157	case 8: kCpumMicroarch_AMD_K7_Thoroughbred;
158	case 10: kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
159	}
160	return kCpumMicroarch_AMD_K7_Unknown;
161	case 0x0f:
162	/*
163	* This family is a friggin mess. Trying my best to make some
164	* sense out of it. Too much happened in the 0x0f family to
165	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
166	*
167	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
168	* cpu-world.com, and other places:
169	* - 130nm:
170	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
171	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
172	* - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
173	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
174	* - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
175	* - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
176	* - 90nm:
177	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
178	* - Oakville: 10FC0/DH-D0.
179	* - Georgetown: 10FC0/DH-D0.
180	* - Sonora: 10FC0/DH-D0.
181	* - Venus: 20F71/SH-E4
182	* - Troy: 20F51/SH-E4
183	* - Athens: 20F51/SH-E4
184	* - San Diego: 20F71/SH-E4.
185	* - Lancaster: 20F42/SH-E5
186	* - Newark: 20F42/SH-E5.
187	* - Albany: 20FC2/DH-E6.
188	* - Roma: 20FC2/DH-E6.
189	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
190	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
191	* - 90nm introducing Dual core:
192	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
193	* - Italy: 20F10/JH-E1, 20F12/JH-E6
194	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
195	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
196	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
197	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheeper models):
198	* - Santa Ana: 40F32/JH-F2, /-F3
199	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
200	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
201	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
202	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
203	* - Keene: 40FC2/DH-F2.
204	* - Richmond: 40FC2/DH-F2
205	* - Taylor: 40F82/BH-F2
206	* - Trinidad: 40F82/BH-F2
207	*
208	* - 65nm:
209	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
210	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
211	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
212	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
213	* - Sherman: /-G1, 70FC2/DH-G2.
214	* - Huron: 70FF2/DH-G2.
215	*/
216	if (bModel < 0x10)
217	return kCpumMicroarch_AMD_K8_130nm;
218	if (bModel >= 0x60 && bModel < 0x80)
219	return kCpumMicroarch_AMD_K8_65nm;
220	if (bModel >= 0x40)
221	return kCpumMicroarch_AMD_K8_90nm_AMDV;
222	switch (bModel)
223	{
224	case 0x21:
225	case 0x23:
226	case 0x2b:
227	case 0x2f:
228	case 0x37:
229	case 0x3f:
230	return kCpumMicroarch_AMD_K8_90nm_DualCore;
231	}
232	return kCpumMicroarch_AMD_K8_90nm;
233	case 0x10:
234	return kCpumMicroarch_AMD_K10;
235	case 0x11:
236	return kCpumMicroarch_AMD_K10_Lion;
237	case 0x12:
238	return kCpumMicroarch_AMD_K10_Llano;
239	case 0x14:
240	return kCpumMicroarch_AMD_Bobcat;
241	case 0x15:
242	switch (bModel)
243	{
244	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
245	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
246	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
247	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
248	case 0x11: /* ?? */
249	case 0x12: /* ?? */
250	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
251	}
252	return kCpumMicroarch_AMD_15h_Unknown;
253	case 0x16:
254	return kCpumMicroarch_AMD_Jaguar;
255
256	}
257	return kCpumMicroarch_AMD_Unknown;
258	}
259
260	if (enmVendor == CPUMCPUVENDOR_INTEL)
261	{
262	switch (bFamily)
263	{
264	case 3:
265	return kCpumMicroarch_Intel_80386;
266	case 4:
267	return kCpumMicroarch_Intel_80486;
268	case 5:
269	return kCpumMicroarch_Intel_P5;
270	case 6:
271	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
272	return g_aenmIntelFamily06[bModel];
273	return kCpumMicroarch_Intel_Atom_Unknown;
274	case 15:
275	switch (bModel)
276	{
277	case 0: return kCpumMicroarch_Intel_NB_Willamette;
278	case 1: return kCpumMicroarch_Intel_NB_Willamette;
279	case 2: return kCpumMicroarch_Intel_NB_Northwood;
280	case 3: return kCpumMicroarch_Intel_NB_Prescott;
281	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
282	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
283	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
284	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
285	default: return kCpumMicroarch_Intel_NB_Unknown;
286	}
287	break;
288	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
289	case 1:
290	return kCpumMicroarch_Intel_8086;
291	case 2:
292	return kCpumMicroarch_Intel_80286;
293	}
294	return kCpumMicroarch_Intel_Unknown;
295	}
296
297	if (enmVendor == CPUMCPUVENDOR_VIA)
298	{
299	switch (bFamily)
300	{
301	case 5:
302	switch (bModel)
303	{
304	case 1: return kCpumMicroarch_Centaur_C6;
305	case 4: return kCpumMicroarch_Centaur_C6;
306	case 8: return kCpumMicroarch_Centaur_C2;
307	case 9: return kCpumMicroarch_Centaur_C3;
308	}
309	break;
310
311	case 6:
312	switch (bModel)
313	{
314	case 5: return kCpumMicroarch_VIA_C3_M2;
315	case 6: return kCpumMicroarch_VIA_C3_C5A;
316	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
317	case 8: return kCpumMicroarch_VIA_C3_C5N;
318	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
319	case 10: return kCpumMicroarch_VIA_C7_C5J;
320	case 15: return kCpumMicroarch_VIA_Isaiah;
321	}
322	break;
323	}
324	return kCpumMicroarch_VIA_Unknown;
325	}
326
327	if (enmVendor == CPUMCPUVENDOR_CYRIX)
328	{
329	switch (bFamily)
330	{
331	case 4:
332	switch (bModel)
333	{
334	case 9: return kCpumMicroarch_Cyrix_5x86;
335	}
336	break;
337
338	case 5:
339	switch (bModel)
340	{
341	case 2: return kCpumMicroarch_Cyrix_M1;
342	case 4: return kCpumMicroarch_Cyrix_MediaGX;
343	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
344	}
345	break;
346
347	case 6:
348	switch (bModel)
349	{
350	case 0: return kCpumMicroarch_Cyrix_M2;
351	}
352	break;
353
354	}
355	return kCpumMicroarch_Cyrix_Unknown;
356	}
357
358	return kCpumMicroarch_Unknown;
359	}
360
361
362	/**
363	* Translates a microarchitecture enum value to the corresponding string
364	* constant.
365	*
366	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
367	* NULL if the value is invalid.
368	*
369	* @param enmMicroarch The enum value to convert.
370	*/
371	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
372	{
373	switch (enmMicroarch)
374	{
375	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
376	CASE_RET_STR(kCpumMicroarch_Intel_8086);
377	CASE_RET_STR(kCpumMicroarch_Intel_80186);
378	CASE_RET_STR(kCpumMicroarch_Intel_80286);
379	CASE_RET_STR(kCpumMicroarch_Intel_80386);
380	CASE_RET_STR(kCpumMicroarch_Intel_80486);
381	CASE_RET_STR(kCpumMicroarch_Intel_P5);
382
383	CASE_RET_STR(kCpumMicroarch_Intel_P6);
384	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
385	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
386
387	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
388	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
389	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
390
391	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
392	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
393
394	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
395	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
396	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
397	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
398	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
399	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
400	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
401	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
402
403	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
404	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
405	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
406	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
407	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
408	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
409	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
410
411	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
412	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
413	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
414	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
415	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
416	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
417	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
418
419	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
420
421	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
422	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
423	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
424	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
425	CASE_RET_STR(kCpumMicroarch_AMD_K5);
426	CASE_RET_STR(kCpumMicroarch_AMD_K6);
427
428	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
429	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
430	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
431	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
432	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
433	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
434	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
435
436	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
437	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
438	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
439	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
440	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
441
442	CASE_RET_STR(kCpumMicroarch_AMD_K10);
443	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
444	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
445	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
446	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
447
448	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
449	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
450	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
451	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
452	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
453
454	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
455
456	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
457
458	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
459	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
460	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
461	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
462	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
463	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
464	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
465	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
466	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
467	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
468	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
469	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
470	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
471
472	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
473	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
474	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
475	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
476	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
477	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
478
479	CASE_RET_STR(kCpumMicroarch_Unknown);
480
481	#undef CASE_RET_STR
482	case kCpumMicroarch_Invalid:
483	case kCpumMicroarch_Intel_End:
484	case kCpumMicroarch_Intel_Core7_End:
485	case kCpumMicroarch_Intel_Atom_End:
486	case kCpumMicroarch_Intel_P6_Core_Atom_End:
487	case kCpumMicroarch_Intel_NB_End:
488	case kCpumMicroarch_AMD_K7_End:
489	case kCpumMicroarch_AMD_K8_End:
490	case kCpumMicroarch_AMD_15h_End:
491	case kCpumMicroarch_AMD_16h_End:
492	case kCpumMicroarch_AMD_End:
493	case kCpumMicroarch_VIA_End:
494	case kCpumMicroarch_Cyrix_End:
495	case kCpumMicroarch_32BitHack:
496	break;
497	/* no default! */
498	}
499
500	return NULL;
501	}
502
503
504
505	/**
506	* Gets a matching leaf in the CPUID leaf array.
507	*
508	* @returns Pointer to the matching leaf, or NULL if not found.
509	* @param paLeaves The CPUID leaves to search. This is sorted.
510	* @param cLeaves The number of leaves in the array.
511	* @param uLeaf The leaf to locate.
512	* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
513	*/
514	PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
515	{
516	/* Lazy bird does linear lookup here since this is only used for the
517	occational CPUID overrides. */
518	for (uint32_t i = 0; i < cLeaves; i++)
519	if ( paLeaves[i].uLeaf == uLeaf
520	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
521	return &paLeaves[i];
522	return NULL;
523	}
524
525
526	/**
527	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
528	*
529	* @returns true if found, false it not.
530	* @param paLeaves The CPUID leaves to search. This is sorted.
531	* @param cLeaves The number of leaves in the array.
532	* @param uLeaf The leaf to locate.
533	* @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
534	* @param pLegacy The legacy output leaf.
535	*/
536	bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf, PCPUMCPUID pLeagcy)
537	{
538	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
539	if (pLeaf)
540	{
541	pLeagcy->eax = pLeaf->uEax;
542	pLeagcy->ebx = pLeaf->uEbx;
543	pLeagcy->ecx = pLeaf->uEcx;
544	pLeagcy->edx = pLeaf->uEdx;
545	return true;
546	}
547	return false;
548	}
549
550
551	/**
552	* Ensures that the CPUID leaf array can hold one more leaf.
553	*
554	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
555	* failure.
556	* @param ppaLeaves Pointer to the variable holding the array
557	* pointer (input/output).
558	* @param cLeaves The current array size.
559	*/
560	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
561	{
562	uint32_t cAllocated = RT_ALIGN(cLeaves, 16);
563	if (cLeaves + 1 > cAllocated)
564	{
565	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
566	if (!pvNew)
567	{
568	RTMemFree(*ppaLeaves);
569	*ppaLeaves = NULL;
570	return NULL;
571	}
572	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
573	}
574	return *ppaLeaves;
575	}
576
577
578	/**
579	* Append a CPUID leaf or sub-leaf.
580	*
581	* ASSUMES linear insertion order, so we'll won't need to do any searching or
582	* replace anything. Use cpumR3CpuIdInsert for those cases.
583	*
584	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
585	* the caller need do no more work.
586	* @param ppaLeaves Pointer to the the pointer to the array of sorted
587	* CPUID leaves and sub-leaves.
588	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
589	* @param uLeaf The leaf we're adding.
590	* @param uSubLeaf The sub-leaf number.
591	* @param fSubLeafMask The sub-leaf mask.
592	* @param uEax The EAX value.
593	* @param uEbx The EBX value.
594	* @param uEcx The ECX value.
595	* @param uEdx The EDX value.
596	* @param fFlags The flags.
597	*/
598	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
599	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
600	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
601	{
602	if (!cpumR3CpuIdEnsureSpace(ppaLeaves, *pcLeaves))
603	return VERR_NO_MEMORY;
604
605	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
606	Assert( *pcLeaves == 0
607	\|\| pNew[-1].uLeaf < uLeaf
608	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
609
610	pNew->uLeaf = uLeaf;
611	pNew->uSubLeaf = uSubLeaf;
612	pNew->fSubLeafMask = fSubLeafMask;
613	pNew->uEax = uEax;
614	pNew->uEbx = uEbx;
615	pNew->uEcx = uEcx;
616	pNew->uEdx = uEdx;
617	pNew->fFlags = fFlags;
618
619	*pcLeaves += 1;
620	return VINF_SUCCESS;
621	}
622
623
624	/**
625	* Inserts a CPU ID leaf, replacing any existing ones.
626	*
627	* When inserting a simple leaf where we already got a series of subleaves with
628	* the same leaf number (eax), the simple leaf will replace the whole series.
629	*
630	* This ASSUMES that the leave array is still on the normal heap and has only
631	* been allocated/reallocated by the cpumR3CpuIdEnsureSpace function.
632	*
633	* @returns VBox status code.
634	* @param ppaLeaves Pointer to the the pointer to the array of sorted
635	* CPUID leaves and sub-leaves.
636	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
637	* @param pNewLeaf Pointer to the data of the new leaf we're about to
638	* insert.
639	*/
640	int cpumR3CpuIdInsert(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
641	{
642	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
643	uint32_t cLeaves = *pcLeaves;
644
645	/*
646	* Validate the new leaf a little.
647	*/
648	AssertReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED), VERR_INVALID_FLAGS);
649	AssertReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0, VERR_INVALID_PARAMETER);
650	AssertReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1), VERR_INVALID_PARAMETER);
651	AssertReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf, VERR_INVALID_PARAMETER);
652
653
654	/*
655	* Find insertion point. The lazy bird uses the same excuse as in
656	* cpumR3CpuIdGetLeaf().
657	*/
658	uint32_t i = 0;
659	while ( i < cLeaves
660	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
661	i++;
662	if ( i < cLeaves
663	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
664	{
665	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
666	{
667	/*
668	* The subleaf mask differs, replace all existing leaves with the
669	* same leaf number.
670	*/
671	uint32_t c = 1;
672	while ( i + c < cLeaves
673	&& paLeaves[i + c].uSubLeaf == pNewLeaf->uLeaf)
674	c++;
675	if (c > 1 && i + c < cLeaves)
676	{
677	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
678	*pcLeaves = cLeaves -= c - 1;
679	}
680
681	paLeaves[i] = *pNewLeaf;
682	return VINF_SUCCESS;
683	}
684
685	/* Find subleaf insertion point. */
686	while ( i < cLeaves
687	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf)
688	i++;
689
690	/*
691	* If we've got an exactly matching leaf, replace it.
692	*/
693	if ( paLeaves[i].uLeaf == pNewLeaf->uLeaf
694	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
695	{
696	paLeaves[i] = *pNewLeaf;
697	return VINF_SUCCESS;
698	}
699	}
700
701	/*
702	* Adding a new leaf at 'i'.
703	*/
704	paLeaves = cpumR3CpuIdEnsureSpace(ppaLeaves, cLeaves);
705	if (!paLeaves)
706	return VERR_NO_MEMORY;
707
708	if (i < cLeaves)
709	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
710	*pcLeaves += 1;
711	paLeaves[i] = *pNewLeaf;
712	return VINF_SUCCESS;
713	}
714
715
716	/**
717	* Removes a range of CPUID leaves.
718	*
719	* This will not reallocate the array.
720	*
721	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
722	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
723	* @param uFirst The first leaf.
724	* @param uLast The last leaf.
725	*/
726	void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
727	{
728	uint32_t cLeaves = *pcLeaves;
729
730	Assert(uFirst <= uLast);
731
732	/*
733	* Find the first one.
734	*/
735	uint32_t iFirst = 0;
736	while ( iFirst < cLeaves
737	&& paLeaves[iFirst].uLeaf < uFirst)
738	iFirst++;
739
740	/*
741	* Find the end (last + 1).
742	*/
743	uint32_t iEnd = iFirst;
744	while ( iEnd < cLeaves
745	&& paLeaves[iEnd].uLeaf <= uLast)
746	iEnd++;
747
748	/*
749	* Adjust the array if anything needs removing.
750	*/
751	if (iFirst < iEnd)
752	{
753	if (iEnd < cLeaves)
754	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
755	*pcLeaves = cLeaves -= (iEnd - iFirst);
756	}
757	}
758
759
760
761	/**
762	* Checks if ECX make a difference when reading a given CPUID leaf.
763	*
764	* @returns @c true if it does, @c false if it doesn't.
765	* @param uLeaf The leaf we're reading.
766	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
767	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
768	* final sub-leaf.
769	*/
770	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
771	{
772	*pfFinalEcxUnchanged = false;
773
774	uint32_t auPrev[4];
775	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
776
777	/* Look for sub-leaves. */
778	uint32_t uSubLeaf = 1;
779	for (;;)
780	{
781	uint32_t auCur[4];
782	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
783	if (memcmp(auCur, auPrev, sizeof(auCur)))
784	break;
785
786	/* Advance / give up. */
787	uSubLeaf++;
788	if (uSubLeaf >= 64)
789	{
790	*pcSubLeaves = 1;
791	return false;
792	}
793	}
794
795	/* Count sub-leaves. */
796	uSubLeaf = 0;
797	for (;;)
798	{
799	uint32_t auCur[4];
800	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
801
802	/* Exactly when this terminates isn't quite consistent. When working
803	0xb, we should probably only check if ebx == 0... */
804	if ( auCur[0] == 0
805	&& auCur[1] == 0
806	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
807	&& (auCur[3] == 0 \|\| uLeaf == 0xb) )
808	{
809	if (auCur[2] == uSubLeaf)
810	*pfFinalEcxUnchanged = true;
811	*pcSubLeaves = uSubLeaf + 1;
812	return true;
813	}
814
815	/* Advance / give up. */
816	uSubLeaf++;
817	if (uSubLeaf >= 128)
818	{
819	*pcSubLeaves = UINT32_MAX;
820	return true;
821	}
822	}
823	}
824
825
826	/**
827	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
828	*
829	* @returns VBox status code.
830	* @param ppaLeaves Where to return the array pointer on success.
831	* Use RTMemFree to release.
832	* @param pcLeaves Where to return the size of the array on
833	* success.
834	*/
835	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
836	{
837	*ppaLeaves = NULL;
838	*pcLeaves = 0;
839
840	/*
841	* Try out various candidates. This must be sorted!
842	*/
843	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
844	{
845	{ UINT32_C(0x00000000), false },
846	{ UINT32_C(0x10000000), false },
847	{ UINT32_C(0x20000000), false },
848	{ UINT32_C(0x30000000), false },
849	{ UINT32_C(0x40000000), false },
850	{ UINT32_C(0x50000000), false },
851	{ UINT32_C(0x60000000), false },
852	{ UINT32_C(0x70000000), false },
853	{ UINT32_C(0x80000000), false },
854	{ UINT32_C(0x80860000), false },
855	{ UINT32_C(0x8ffffffe), true },
856	{ UINT32_C(0x8fffffff), true },
857	{ UINT32_C(0x90000000), false },
858	{ UINT32_C(0xa0000000), false },
859	{ UINT32_C(0xb0000000), false },
860	{ UINT32_C(0xc0000000), false },
861	{ UINT32_C(0xd0000000), false },
862	{ UINT32_C(0xe0000000), false },
863	{ UINT32_C(0xf0000000), false },
864	};
865
866	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
867	{
868	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
869	uint32_t uEax, uEbx, uEcx, uEdx;
870	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
871
872	/*
873	* Does EAX look like a typical leaf count value?
874	*/
875	if ( uEax > uLeaf
876	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
877	{
878	/* Yes, dump them. */
879	uint32_t cLeaves = uEax - uLeaf + 1;
880	while (cLeaves-- > 0)
881	{
882	/* Check three times here to reduce the chance of CPU migration
883	resulting in false positives with things like the APIC ID. */
884	uint32_t cSubLeaves;
885	bool fFinalEcxUnchanged;
886	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
887	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
888	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
889	{
890	if (cSubLeaves > 16)
891	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
892	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
893	{
894	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
895	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
896	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx,
897	uSubLeaf + 1 == cSubLeaves && fFinalEcxUnchanged
898	? CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED : 0);
899	if (RT_FAILURE(rc))
900	return rc;
901	}
902	}
903	else
904	{
905	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
906	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
907	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
908	if (RT_FAILURE(rc))
909	return rc;
910	}
911
912	/* next */
913	uLeaf++;
914	}
915	}
916	/*
917	* Special CPUIDs needs special handling as they don't follow the
918	* leaf count principle used above.
919	*/
920	else if (s_aCandidates[iOuter].fSpecial)
921	{
922	bool fKeep = false;
923	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
924	fKeep = true;
925	else if ( uLeaf == 0x8fffffff
926	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
927	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
928	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
929	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
930	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
931	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
932	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
933	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
934	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
935	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
936	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
937	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
938	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
939	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
940	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
941	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
942	fKeep = true;
943	if (fKeep)
944	{
945	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
946	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
947	if (RT_FAILURE(rc))
948	return rc;
949	}
950	}
951	}
952
953	return VINF_SUCCESS;
954	}
955
956
957	/**
958	* Determines the method the CPU uses to handle unknown CPUID leaves.
959	*
960	* @returns VBox status code.
961	* @param penmUnknownMethod Where to return the method.
962	* @param pDefUnknown Where to return default unknown values. This
963	* will be set, even if the resulting method
964	* doesn't actually needs it.
965	*/
966	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
967	{
968	uint32_t uLastStd = ASMCpuId_EAX(0);
969	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
970	if (!ASMIsValidExtRange(uLastExt))
971	uLastExt = 0x80000000;
972
973	uint32_t auChecks[] =
974	{
975	uLastStd + 1,
976	uLastStd + 5,
977	uLastStd + 8,
978	uLastStd + 32,
979	uLastStd + 251,
980	uLastExt + 1,
981	uLastExt + 8,
982	uLastExt + 15,
983	uLastExt + 63,
984	uLastExt + 255,
985	0x7fbbffcc,
986	0x833f7872,
987	0xefff2353,
988	0x35779456,
989	0x1ef6d33e,
990	};
991
992	static const uint32_t s_auValues[] =
993	{
994	0xa95d2156,
995	0x00000001,
996	0x00000002,
997	0x00000008,
998	0x00000000,
999	0x55773399,
1000	0x93401769,
1001	0x12039587,
1002	};
1003
1004	/*
1005	* Simple method, all zeros.
1006	*/
1007	*penmUnknownMethod = CPUMUKNOWNCPUID_DEFAULTS;
1008	pDefUnknown->eax = 0;
1009	pDefUnknown->ebx = 0;
1010	pDefUnknown->ecx = 0;
1011	pDefUnknown->edx = 0;
1012
1013	/*
1014	* Intel has been observed returning the last standard leaf.
1015	*/
1016	uint32_t auLast[4];
1017	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1018
1019	uint32_t cChecks = RT_ELEMENTS(auChecks);
1020	while (cChecks > 0)
1021	{
1022	uint32_t auCur[4];
1023	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1024	if (memcmp(auCur, auLast, sizeof(auCur)))
1025	break;
1026	cChecks--;
1027	}
1028	if (cChecks == 0)
1029	{
1030	/* Now, what happens when the input changes? Esp. ECX. */
1031	uint32_t cTotal = 0;
1032	uint32_t cSame = 0;
1033	uint32_t cLastWithEcx = 0;
1034	uint32_t cNeither = 0;
1035	uint32_t cValues = RT_ELEMENTS(s_auValues);
1036	while (cValues > 0)
1037	{
1038	uint32_t uValue = s_auValues[cValues - 1];
1039	uint32_t auLastWithEcx[4];
1040	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1041	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1042
1043	cChecks = RT_ELEMENTS(auChecks);
1044	while (cChecks > 0)
1045	{
1046	uint32_t auCur[4];
1047	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1048	if (!memcmp(auCur, auLast, sizeof(auCur)))
1049	{
1050	cSame++;
1051	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1052	cLastWithEcx++;
1053	}
1054	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1055	cLastWithEcx++;
1056	else
1057	cNeither++;
1058	cTotal++;
1059	cChecks--;
1060	}
1061	cValues--;
1062	}
1063
1064	RTStrmPrintf(g_pStdErr, "cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal);
1065	if (cSame == cTotal)
1066	*penmUnknownMethod = CPUMUKNOWNCPUID_LAST_STD_LEAF;
1067	else if (cLastWithEcx == cTotal)
1068	*penmUnknownMethod = CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1069	else
1070	*penmUnknownMethod = CPUMUKNOWNCPUID_LAST_STD_LEAF;
1071	pDefUnknown->eax = auLast[0];
1072	pDefUnknown->ebx = auLast[1];
1073	pDefUnknown->ecx = auLast[2];
1074	pDefUnknown->edx = auLast[3];
1075	return VINF_SUCCESS;
1076	}
1077
1078	/*
1079	* Unchanged register values?
1080	*/
1081	cChecks = RT_ELEMENTS(auChecks);
1082	while (cChecks > 0)
1083	{
1084	uint32_t const uLeaf = auChecks[cChecks - 1];
1085	uint32_t cValues = RT_ELEMENTS(s_auValues);
1086	while (cValues > 0)
1087	{
1088	uint32_t uValue = s_auValues[cValues - 1];
1089	uint32_t auCur[4];
1090	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1091	if ( auCur[0] != uLeaf
1092	\|\| auCur[1] != uValue
1093	\|\| auCur[2] != uValue
1094	\|\| auCur[3] != uValue)
1095	break;
1096	cValues--;
1097	}
1098	if (cValues != 0)
1099	break;
1100	cChecks--;
1101	}
1102	if (cChecks == 0)
1103	{
1104	*penmUnknownMethod = CPUMUKNOWNCPUID_PASSTHRU;
1105	return VINF_SUCCESS;
1106	}
1107
1108	/*
1109	* Just go with the simple method.
1110	*/
1111	return VINF_SUCCESS;
1112	}
1113
1114
1115	/**
1116	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1117	*
1118	* @returns Read only name string.
1119	* @param enmUnknownMethod The method to translate.
1120	*/
1121	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUKNOWNCPUID enmUnknownMethod)
1122	{
1123	switch (enmUnknownMethod)
1124	{
1125	case CPUMUKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1126	case CPUMUKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1127	case CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1128	case CPUMUKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1129
1130	case CPUMUKNOWNCPUID_INVALID:
1131	case CPUMUKNOWNCPUID_END:
1132	case CPUMUKNOWNCPUID_32BIT_HACK:
1133	break;
1134	}
1135	return "Invalid-unknown-CPUID-method";
1136	}
1137
1138
1139	/**
1140	* Detect the CPU vendor give n the
1141	*
1142	* @returns The vendor.
1143	* @param uEAX EAX from CPUID(0).
1144	* @param uEBX EBX from CPUID(0).
1145	* @param uECX ECX from CPUID(0).
1146	* @param uEDX EDX from CPUID(0).
1147	*/
1148	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1149	{
1150	if (ASMIsValidStdRange(uEAX))
1151	{
1152	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1153	return CPUMCPUVENDOR_AMD;
1154
1155	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1156	return CPUMCPUVENDOR_INTEL;
1157
1158	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1159	return CPUMCPUVENDOR_VIA;
1160
1161	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1162	&& uECX == UINT32_C(0x64616574)
1163	&& uEDX == UINT32_C(0x736E4978))
1164	return CPUMCPUVENDOR_CYRIX;
1165
1166	/* "Geode by NSC", example: family 5, model 9. */
1167
1168	/** @todo detect the other buggers... */
1169	}
1170
1171	return CPUMCPUVENDOR_UNKNOWN;
1172	}
1173
1174
1175	/**
1176	* Translates a CPU vendor enum value into the corresponding string constant.
1177	*
1178	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1179	* value name. This can be useful when generating code.
1180	*
1181	* @returns Read only name string.
1182	* @param enmVendor The CPU vendor value.
1183	*/
1184	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1185	{
1186	switch (enmVendor)
1187	{
1188	case CPUMCPUVENDOR_INTEL: return "INTEL";
1189	case CPUMCPUVENDOR_AMD: return "AMD";
1190	case CPUMCPUVENDOR_VIA: return "VIA";
1191	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1192	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1193
1194	case CPUMCPUVENDOR_INVALID:
1195	case CPUMCPUVENDOR_32BIT_HACK:
1196	break;
1197	}
1198	return "Invalid-cpu-vendor";
1199	}
1200
1201
1202	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1203	{
1204	/* Could do binary search, doing linear now because I'm lazy. */
1205	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1206	while (cLeaves-- > 0)
1207	{
1208	if (pLeaf->uLeaf == uLeaf)
1209	return pLeaf;
1210	pLeaf++;
1211	}
1212	return NULL;
1213	}
1214
1215
1216	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1217	{
1218	RT_ZERO(*pFeatures);
1219	if (cLeaves >= 2)
1220	{
1221	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1222	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1223
1224	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(paLeaves[0].uEax,
1225	paLeaves[0].uEbx,
1226	paLeaves[0].uEcx,
1227	paLeaves[0].uEdx);
1228	pFeatures->uFamily = ASMGetCpuFamily(paLeaves[1].uEax);
1229	pFeatures->uModel = ASMGetCpuModel(paLeaves[1].uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1230	pFeatures->uStepping = ASMGetCpuStepping(paLeaves[1].uEax);
1231	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1232	pFeatures->uFamily,
1233	pFeatures->uModel,
1234	pFeatures->uStepping);
1235
1236	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1237	if (pLeaf)
1238	pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1239	else if (paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1240	pFeatures->cMaxPhysAddrWidth = 36;
1241	else
1242	pFeatures->cMaxPhysAddrWidth = 32;
1243
1244	/* Standard features. */
1245	pFeatures->fMsr = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_MSR);
1246	pFeatures->fApic = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_APIC);
1247	pFeatures->fX2Apic = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1248	pFeatures->fPse = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE);
1249	pFeatures->fPse36 = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1250	pFeatures->fPae = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAE);
1251	pFeatures->fPat = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAT);
1252	pFeatures->fFxSaveRstor = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1253	pFeatures->fSysEnter = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_SEP);
1254	pFeatures->fHypervisorPresent = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_HVP);
1255	pFeatures->fMonitorMWait = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1256
1257	/* Extended features. */
1258	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1259	if (pExtLeaf)
1260	{
1261	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1262	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1263	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1264	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1265	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1266	}
1267
1268	if ( pExtLeaf
1269	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1270	{
1271	/* AMD features. */
1272	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1273	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1274	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1275	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1276	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1277	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1278	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1279	}
1280
1281	/*
1282	* Quirks.
1283	*/
1284	pFeatures->fLeakyFxSR = pExtLeaf
1285	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1286	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1287	&& pFeatures->uFamily >= 6 /* K7 and up */;
1288	}
1289	else
1290	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1291	return VINF_SUCCESS;
1292	}
1293

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 49966

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