CPUMR3CpuId.cpp@ 95638

Last change on this file since 95638 was 95361, checked in by vboxsync, 2 years ago
VMM/CPUM: Pass thru the POPCNT CPUID flag. Corrected ABM passthru. bugref:9898
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File size: 271.6 KB

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1	/* $Id: CPUMR3CpuId.cpp 95361 2022-06-23 21:47:01Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vmcc.h>
30	#include <VBox/sup.h>
31
32	#include <VBox/err.h>
33	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
34	# include <iprt/asm-amd64-x86.h>
35	#endif
36	#include <iprt/ctype.h>
37	#include <iprt/mem.h>
38	#include <iprt/string.h>
39	#include <iprt/x86-helpers.h>
40
41
42	/*********************************************************************************************************************************
43	* Defined Constants And Macros *
44	*********************************************************************************************************************************/
45	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
46	#define CPUM_CPUID_MAX_LEAVES 2048
47
48
49	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
50	/**
51	* Determins the host CPU MXCSR mask.
52	*
53	* @returns MXCSR mask.
54	*/
55	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
56	{
57	if ( ASMHasCpuId()
58	&& RTX86IsValidStdRange(ASMCpuId_EAX(0))
59	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
60	{
61	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
62	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
63	RT_ZERO(*pState);
64	ASMFxSave(pState);
65	if (pState->MXCSR_MASK == 0)
66	return 0xffbf;
67	return pState->MXCSR_MASK;
68	}
69	return 0;
70	}
71	#endif
72
73
74
75	#ifndef IN_VBOX_CPU_REPORT
76	/**
77	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
78	*
79	* @returns true if found, false it not.
80	* @param paLeaves The CPUID leaves to search. This is sorted.
81	* @param cLeaves The number of leaves in the array.
82	* @param uLeaf The leaf to locate.
83	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
84	* @param pLegacy The legacy output leaf.
85	*/
86	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
87	PCPUMCPUID pLegacy)
88	{
89	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, uLeaf, uSubLeaf);
90	if (pLeaf)
91	{
92	pLegacy->uEax = pLeaf->uEax;
93	pLegacy->uEbx = pLeaf->uEbx;
94	pLegacy->uEcx = pLeaf->uEcx;
95	pLegacy->uEdx = pLeaf->uEdx;
96	return true;
97	}
98	return false;
99	}
100	#endif /* IN_VBOX_CPU_REPORT */
101
102
103	/**
104	* Inserts a CPU ID leaf, replacing any existing ones.
105	*
106	* When inserting a simple leaf where we already got a series of sub-leaves with
107	* the same leaf number (eax), the simple leaf will replace the whole series.
108	*
109	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
110	* host-context heap and has only been allocated/reallocated by the
111	* cpumCpuIdEnsureSpace function.
112	*
113	* @returns VBox status code.
114	* @param pVM The cross context VM structure. If NULL, use
115	* the process heap, otherwise the VM's hyper heap.
116	* @param ppaLeaves Pointer to the pointer to the array of sorted
117	* CPUID leaves and sub-leaves. Must be NULL if using
118	* the hyper heap.
119	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
120	* be NULL if using the hyper heap.
121	* @param pNewLeaf Pointer to the data of the new leaf we're about to
122	* insert.
123	*/
124	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
125	{
126	/*
127	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
128	*/
129	if (pVM)
130	{
131	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
132	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
133	AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
134
135	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
136	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
137	}
138
139	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
140	uint32_t cLeaves = *pcLeaves;
141
142	/*
143	* Validate the new leaf a little.
144	*/
145	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
146	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
147	VERR_INVALID_FLAGS);
148	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
149	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
150	VERR_INVALID_PARAMETER);
151	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
152	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
153	VERR_INVALID_PARAMETER);
154	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
155	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
156	VERR_INVALID_PARAMETER);
157
158	/*
159	* Find insertion point. The lazy bird uses the same excuse as in
160	* cpumCpuIdGetLeaf(), but optimizes for linear insertion (saved state).
161	*/
162	uint32_t i;
163	if ( cLeaves > 0
164	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
165	{
166	/* Add at end. */
167	i = cLeaves;
168	}
169	else if ( cLeaves > 0
170	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
171	{
172	/* Either replacing the last leaf or dealing with sub-leaves. Spool
173	back to the first sub-leaf to pretend we did the linear search. */
174	i = cLeaves - 1;
175	while ( i > 0
176	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
177	i--;
178	}
179	else
180	{
181	/* Linear search from the start. */
182	i = 0;
183	while ( i < cLeaves
184	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
185	i++;
186	}
187	if ( i < cLeaves
188	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
189	{
190	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
191	{
192	/*
193	* The sub-leaf mask differs, replace all existing leaves with the
194	* same leaf number.
195	*/
196	uint32_t c = 1;
197	while ( i + c < cLeaves
198	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
199	c++;
200	if (c > 1 && i + c < cLeaves)
201	{
202	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
203	*pcLeaves = cLeaves -= c - 1;
204	}
205
206	paLeaves[i] = *pNewLeaf;
207	#ifdef VBOX_STRICT
208	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
209	#endif
210	return VINF_SUCCESS;
211	}
212
213	/* Find sub-leaf insertion point. */
214	while ( i < cLeaves
215	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
216	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
217	i++;
218
219	/*
220	* If we've got an exactly matching leaf, replace it.
221	*/
222	if ( i < cLeaves
223	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
224	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
225	{
226	paLeaves[i] = *pNewLeaf;
227	#ifdef VBOX_STRICT
228	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
229	#endif
230	return VINF_SUCCESS;
231	}
232	}
233
234	/*
235	* Adding a new leaf at 'i'.
236	*/
237	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
238	paLeaves = cpumCpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
239	if (!paLeaves)
240	return VERR_NO_MEMORY;
241
242	if (i < cLeaves)
243	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
244	*pcLeaves += 1;
245	paLeaves[i] = *pNewLeaf;
246
247	#ifdef VBOX_STRICT
248	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
249	#endif
250	return VINF_SUCCESS;
251	}
252
253
254	#ifndef IN_VBOX_CPU_REPORT
255	/**
256	* Removes a range of CPUID leaves.
257	*
258	* This will not reallocate the array.
259	*
260	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
261	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
262	* @param uFirst The first leaf.
263	* @param uLast The last leaf.
264	*/
265	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
266	{
267	uint32_t cLeaves = *pcLeaves;
268
269	Assert(uFirst <= uLast);
270
271	/*
272	* Find the first one.
273	*/
274	uint32_t iFirst = 0;
275	while ( iFirst < cLeaves
276	&& paLeaves[iFirst].uLeaf < uFirst)
277	iFirst++;
278
279	/*
280	* Find the end (last + 1).
281	*/
282	uint32_t iEnd = iFirst;
283	while ( iEnd < cLeaves
284	&& paLeaves[iEnd].uLeaf <= uLast)
285	iEnd++;
286
287	/*
288	* Adjust the array if anything needs removing.
289	*/
290	if (iFirst < iEnd)
291	{
292	if (iEnd < cLeaves)
293	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
294	*pcLeaves = cLeaves -= (iEnd - iFirst);
295	}
296
297	# ifdef VBOX_STRICT
298	cpumCpuIdAssertOrder(paLeaves, *pcLeaves);
299	# endif
300	}
301	#endif /* IN_VBOX_CPU_REPORT */
302
303
304	/**
305	* Gets a CPU ID leaf.
306	*
307	* @returns VBox status code.
308	* @param pVM The cross context VM structure.
309	* @param pLeaf Where to store the found leaf.
310	* @param uLeaf The leaf to locate.
311	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
312	*/
313	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
314	{
315	PCPUMCPUIDLEAF pcLeaf = cpumCpuIdGetLeafInt(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
316	uLeaf, uSubLeaf);
317	if (pcLeaf)
318	{
319	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
320	return VINF_SUCCESS;
321	}
322
323	return VERR_NOT_FOUND;
324	}
325
326
327	/**
328	* Gets all the leaves.
329	*
330	* This only works after the CPUID leaves have been initialized. The interface
331	* is intended for NEM and configuring CPUID leaves for the native hypervisor.
332	*
333	* @returns Pointer to the array of leaves. NULL on failure.
334	* @param pVM The cross context VM structure.
335	* @param pcLeaves Where to return the number of leaves.
336	*/
337	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves)
338	{
339	*pcLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
340	return pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
341	}
342
343
344	/**
345	* Inserts a CPU ID leaf, replacing any existing ones.
346	*
347	* @returns VBox status code.
348	* @param pVM The cross context VM structure.
349	* @param pNewLeaf Pointer to the leaf being inserted.
350	*/
351	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
352	{
353	/*
354	* Validate parameters.
355	*/
356	AssertReturn(pVM, VERR_INVALID_PARAMETER);
357	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
358
359	/*
360	* Disallow replacing CPU ID leaves that this API currently cannot manage.
361	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
362	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
363	*/
364	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
365	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
366	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
367	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
368	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
369	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
370	{
371	return VERR_NOT_SUPPORTED;
372	}
373
374	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
375	}
376
377
378	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
379	/**
380	* Determines the method the CPU uses to handle unknown CPUID leaves.
381	*
382	* @returns VBox status code.
383	* @param penmUnknownMethod Where to return the method.
384	* @param pDefUnknown Where to return default unknown values. This
385	* will be set, even if the resulting method
386	* doesn't actually needs it.
387	*/
388	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
389	{
390	uint32_t uLastStd = ASMCpuId_EAX(0);
391	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
392	if (!RTX86IsValidExtRange(uLastExt))
393	uLastExt = 0x80000000;
394
395	uint32_t auChecks[] =
396	{
397	uLastStd + 1,
398	uLastStd + 5,
399	uLastStd + 8,
400	uLastStd + 32,
401	uLastStd + 251,
402	uLastExt + 1,
403	uLastExt + 8,
404	uLastExt + 15,
405	uLastExt + 63,
406	uLastExt + 255,
407	0x7fbbffcc,
408	0x833f7872,
409	0xefff2353,
410	0x35779456,
411	0x1ef6d33e,
412	};
413
414	static const uint32_t s_auValues[] =
415	{
416	0xa95d2156,
417	0x00000001,
418	0x00000002,
419	0x00000008,
420	0x00000000,
421	0x55773399,
422	0x93401769,
423	0x12039587,
424	};
425
426	/*
427	* Simple method, all zeros.
428	*/
429	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
430	pDefUnknown->uEax = 0;
431	pDefUnknown->uEbx = 0;
432	pDefUnknown->uEcx = 0;
433	pDefUnknown->uEdx = 0;
434
435	/*
436	* Intel has been observed returning the last standard leaf.
437	*/
438	uint32_t auLast[4];
439	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
440
441	uint32_t cChecks = RT_ELEMENTS(auChecks);
442	while (cChecks > 0)
443	{
444	uint32_t auCur[4];
445	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
446	if (memcmp(auCur, auLast, sizeof(auCur)))
447	break;
448	cChecks--;
449	}
450	if (cChecks == 0)
451	{
452	/* Now, what happens when the input changes? Esp. ECX. */
453	uint32_t cTotal = 0;
454	uint32_t cSame = 0;
455	uint32_t cLastWithEcx = 0;
456	uint32_t cNeither = 0;
457	uint32_t cValues = RT_ELEMENTS(s_auValues);
458	while (cValues > 0)
459	{
460	uint32_t uValue = s_auValues[cValues - 1];
461	uint32_t auLastWithEcx[4];
462	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
463	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
464
465	cChecks = RT_ELEMENTS(auChecks);
466	while (cChecks > 0)
467	{
468	uint32_t auCur[4];
469	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
470	if (!memcmp(auCur, auLast, sizeof(auCur)))
471	{
472	cSame++;
473	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
474	cLastWithEcx++;
475	}
476	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
477	cLastWithEcx++;
478	else
479	cNeither++;
480	cTotal++;
481	cChecks--;
482	}
483	cValues--;
484	}
485
486	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
487	if (cSame == cTotal)
488	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
489	else if (cLastWithEcx == cTotal)
490	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
491	else
492	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
493	pDefUnknown->uEax = auLast[0];
494	pDefUnknown->uEbx = auLast[1];
495	pDefUnknown->uEcx = auLast[2];
496	pDefUnknown->uEdx = auLast[3];
497	return VINF_SUCCESS;
498	}
499
500	/*
501	* Unchanged register values?
502	*/
503	cChecks = RT_ELEMENTS(auChecks);
504	while (cChecks > 0)
505	{
506	uint32_t const uLeaf = auChecks[cChecks - 1];
507	uint32_t cValues = RT_ELEMENTS(s_auValues);
508	while (cValues > 0)
509	{
510	uint32_t uValue = s_auValues[cValues - 1];
511	uint32_t auCur[4];
512	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
513	if ( auCur[0] != uLeaf
514	\|\| auCur[1] != uValue
515	\|\| auCur[2] != uValue
516	\|\| auCur[3] != uValue)
517	break;
518	cValues--;
519	}
520	if (cValues != 0)
521	break;
522	cChecks--;
523	}
524	if (cChecks == 0)
525	{
526	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
527	return VINF_SUCCESS;
528	}
529
530	/*
531	* Just go with the simple method.
532	*/
533	return VINF_SUCCESS;
534	}
535	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
536
537
538	/**
539	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
540	*
541	* @returns Read only name string.
542	* @param enmUnknownMethod The method to translate.
543	*/
544	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
545	{
546	switch (enmUnknownMethod)
547	{
548	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
549	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
550	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
551	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
552
553	case CPUMUNKNOWNCPUID_INVALID:
554	case CPUMUNKNOWNCPUID_END:
555	case CPUMUNKNOWNCPUID_32BIT_HACK:
556	break;
557	}
558	return "Invalid-unknown-CPUID-method";
559	}
560
561
562	/*
563	*
564	* Init related code.
565	* Init related code.
566	* Init related code.
567	*
568	*
569	*/
570	#ifndef IN_VBOX_CPU_REPORT
571
572
573	/**
574	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
575	*
576	* This ignores the fSubLeafMask.
577	*
578	* @returns Pointer to the matching leaf, or NULL if not found.
579	* @param pCpum The CPUM instance data.
580	* @param uLeaf The leaf to locate.
581	* @param uSubLeaf The subleaf to locate.
582	*/
583	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
584	{
585	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
586	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
587	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
588	if (iEnd)
589	{
590	uint32_t iBegin = 0;
591	for (;;)
592	{
593	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
594	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
595	if (uNeedle < uCur)
596	{
597	if (i > iBegin)
598	iEnd = i;
599	else
600	break;
601	}
602	else if (uNeedle > uCur)
603	{
604	if (i + 1 < iEnd)
605	iBegin = i + 1;
606	else
607	break;
608	}
609	else
610	return &paLeaves[i];
611	}
612	}
613	return NULL;
614	}
615
616
617	/**
618	* Loads MSR range overrides.
619	*
620	* This must be called before the MSR ranges are moved from the normal heap to
621	* the hyper heap!
622	*
623	* @returns VBox status code (VMSetError called).
624	* @param pVM The cross context VM structure.
625	* @param pMsrNode The CFGM node with the MSR overrides.
626	*/
627	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
628	{
629	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
630	{
631	/*
632	* Assemble a valid MSR range.
633	*/
634	CPUMMSRRANGE MsrRange;
635	MsrRange.offCpumCpu = 0;
636	MsrRange.fReserved = 0;
637
638	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
639	if (RT_FAILURE(rc))
640	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
641
642	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
643	if (RT_FAILURE(rc))
644	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
645	MsrRange.szName, rc);
646
647	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
648	if (RT_FAILURE(rc))
649	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
650	MsrRange.szName, rc);
651
652	char szType[32];
653	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
654	if (RT_FAILURE(rc))
655	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
656	MsrRange.szName, rc);
657	if (!RTStrICmp(szType, "FixedValue"))
658	{
659	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
660	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
661
662	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
663	if (RT_FAILURE(rc))
664	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
665	MsrRange.szName, rc);
666
667	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
668	if (RT_FAILURE(rc))
669	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
670	MsrRange.szName, rc);
671
672	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
673	if (RT_FAILURE(rc))
674	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
675	MsrRange.szName, rc);
676	}
677	else
678	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
679	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
680
681	/*
682	* Insert the range into the table (replaces/splits/shrinks existing
683	* MSR ranges).
684	*/
685	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
686	&MsrRange);
687	if (RT_FAILURE(rc))
688	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
689	}
690
691	return VINF_SUCCESS;
692	}
693
694
695	/**
696	* Loads CPUID leaf overrides.
697	*
698	* This must be called before the CPUID leaves are moved from the normal
699	* heap to the hyper heap!
700	*
701	* @returns VBox status code (VMSetError called).
702	* @param pVM The cross context VM structure.
703	* @param pParentNode The CFGM node with the CPUID leaves.
704	* @param pszLabel How to label the overrides we're loading.
705	*/
706	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
707	{
708	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
709	{
710	/*
711	* Get the leaf and subleaf numbers.
712	*/
713	char szName[128];
714	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
715	if (RT_FAILURE(rc))
716	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
717
718	/* The leaf number is either specified directly or thru the node name. */
719	uint32_t uLeaf;
720	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
721	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
722	{
723	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
724	if (rc != VINF_SUCCESS)
725	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
726	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
727	}
728	else if (RT_FAILURE(rc))
729	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
730	pszLabel, szName, rc);
731
732	uint32_t uSubLeaf;
733	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
734	if (RT_FAILURE(rc))
735	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
736	pszLabel, szName, rc);
737
738	uint32_t fSubLeafMask;
739	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
740	if (RT_FAILURE(rc))
741	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
742	pszLabel, szName, rc);
743
744	/*
745	* Look up the specified leaf, since the output register values
746	* defaults to any existing values. This allows overriding a single
747	* register, without needing to know the other values.
748	*/
749	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
750	CPUMCPUIDLEAF Leaf;
751	if (pLeaf)
752	Leaf = *pLeaf;
753	else
754	RT_ZERO(Leaf);
755	Leaf.uLeaf = uLeaf;
756	Leaf.uSubLeaf = uSubLeaf;
757	Leaf.fSubLeafMask = fSubLeafMask;
758
759	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
760	if (RT_FAILURE(rc))
761	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
762	pszLabel, szName, rc);
763	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
764	if (RT_FAILURE(rc))
765	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
766	pszLabel, szName, rc);
767	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
768	if (RT_FAILURE(rc))
769	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
770	pszLabel, szName, rc);
771	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
772	if (RT_FAILURE(rc))
773	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
774	pszLabel, szName, rc);
775
776	/*
777	* Insert the leaf into the table (replaces existing ones).
778	*/
779	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
780	&Leaf);
781	if (RT_FAILURE(rc))
782	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
783	}
784
785	return VINF_SUCCESS;
786	}
787
788
789
790	/**
791	* Fetches overrides for a CPUID leaf.
792	*
793	* @returns VBox status code.
794	* @param pLeaf The leaf to load the overrides into.
795	* @param pCfgNode The CFGM node containing the overrides
796	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
797	* @param iLeaf The CPUID leaf number.
798	*/
799	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
800	{
801	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
802	if (pLeafNode)
803	{
804	uint32_t u32;
805	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
806	if (RT_SUCCESS(rc))
807	pLeaf->uEax = u32;
808	else
809	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
810
811	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
812	if (RT_SUCCESS(rc))
813	pLeaf->uEbx = u32;
814	else
815	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
816
817	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
818	if (RT_SUCCESS(rc))
819	pLeaf->uEcx = u32;
820	else
821	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
822
823	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
824	if (RT_SUCCESS(rc))
825	pLeaf->uEdx = u32;
826	else
827	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
828
829	}
830	return VINF_SUCCESS;
831	}
832
833
834	/**
835	* Load the overrides for a set of CPUID leaves.
836	*
837	* @returns VBox status code.
838	* @param paLeaves The leaf array.
839	* @param cLeaves The number of leaves.
840	* @param uStart The start leaf number.
841	* @param pCfgNode The CFGM node containing the overrides
842	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
843	*/
844	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
845	{
846	for (uint32_t i = 0; i < cLeaves; i++)
847	{
848	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
849	if (RT_FAILURE(rc))
850	return rc;
851	}
852
853	return VINF_SUCCESS;
854	}
855
856
857	/**
858	* Installs the CPUID leaves and explods the data into structures like
859	* GuestFeatures and CPUMCTX::aoffXState.
860	*
861	* @returns VBox status code.
862	* @param pVM The cross context VM structure.
863	* @param pCpum The CPUM part of @a VM.
864	* @param paLeaves The leaves. These will be copied (but not freed).
865	* @param cLeaves The number of leaves.
866	* @param pMsrs The MSRs.
867	*/
868	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
869	{
870	# ifdef VBOX_STRICT
871	cpumCpuIdAssertOrder(paLeaves, cLeaves);
872	# endif
873
874	/*
875	* Install the CPUID information.
876	*/
877	AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
878	("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
879	VERR_CPUM_IPE_1); /** @todo better status! */
880	if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
881	memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
882	pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
883	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
884
885	/*
886	* Update the default CPUID leaf if necessary.
887	*/
888	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
889	{
890	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
891	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
892	{
893	/* We don't use CPUID(0).eax here because of the NT hack that only
894	changes that value without actually removing any leaves. */
895	uint32_t i = 0;
896	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
897	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
898	{
899	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
900	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
901	i++;
902	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
903	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
904	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
905	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
906	}
907	break;
908	}
909	default:
910	break;
911	}
912
913	/*
914	* Explode the guest CPU features.
915	*/
916	int rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
917	&pCpum->GuestFeatures);
918	AssertLogRelRCReturn(rc, rc);
919
920	/*
921	* Adjust the scalable bus frequency according to the CPUID information
922	* we're now using.
923	*/
924	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
925	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
926	? UINT64_C(100000000) /* 100MHz */
927	: UINT64_C(133333333); /* 133MHz */
928
929	/*
930	* Populate the legacy arrays. Currently used for everything, later only
931	* for patch manager.
932	*/
933	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
934	{
935	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
936	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
937	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
938	};
939	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
940	{
941	uint32_t cLeft = aOldRanges[i].cCpuIds;
942	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
943	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
944	while (cLeft-- > 0)
945	{
946	uLeaf--;
947	pLegacyLeaf--;
948
949	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
950	if (pLeaf)
951	{
952	pLegacyLeaf->uEax = pLeaf->uEax;
953	pLegacyLeaf->uEbx = pLeaf->uEbx;
954	pLegacyLeaf->uEcx = pLeaf->uEcx;
955	pLegacyLeaf->uEdx = pLeaf->uEdx;
956	}
957	else
958	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
959	}
960	}
961
962	/*
963	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
964	*/
965	PVMCPU pVCpu0 = pVM->apCpusR3[0];
966	AssertCompile(sizeof(pVCpu0->cpum.s.Guest.abXState) == CPUM_MAX_XSAVE_AREA_SIZE);
967	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
968	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
969	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
970	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
971	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
972	{
973	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
974	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
975	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
976	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
977	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
978	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
979	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
980	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
981	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
982	pCpum->GuestFeatures.cbMaxExtendedState),
983	VERR_CPUM_IPE_1);
984	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
985	}
986
987	/* Copy the CPU #0 data to the other CPUs. */
988	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
989	{
990	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
991	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
992	}
993
994	return VINF_SUCCESS;
995	}
996
997
998	/** @name Instruction Set Extension Options
999	* @{ */
1000	/** Configuration option type (extended boolean, really). */
1001	typedef uint8_t CPUMISAEXTCFG;
1002	/** Always disable the extension. */
1003	#define CPUMISAEXTCFG_DISABLED false
1004	/** Enable the extension if it's supported by the host CPU. */
1005	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
1006	/** Enable the extension if it's supported by the host CPU, but don't let
1007	* the portable CPUID feature disable it. */
1008	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
1009	/** Always enable the extension. */
1010	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
1011	/** @} */
1012
1013	/**
1014	* CPUID Configuration (from CFGM).
1015	*
1016	* @remarks The members aren't document since we would only be duplicating the
1017	* \@cfgm entries in cpumR3CpuIdReadConfig.
1018	*/
1019	typedef struct CPUMCPUIDCONFIG
1020	{
1021	bool fNt4LeafLimit;
1022	bool fInvariantTsc;
1023	bool fForceVme;
1024	bool fNestedHWVirt;
1025
1026	CPUMISAEXTCFG enmCmpXchg16b;
1027	CPUMISAEXTCFG enmMonitor;
1028	CPUMISAEXTCFG enmMWaitExtensions;
1029	CPUMISAEXTCFG enmSse41;
1030	CPUMISAEXTCFG enmSse42;
1031	CPUMISAEXTCFG enmAvx;
1032	CPUMISAEXTCFG enmAvx2;
1033	CPUMISAEXTCFG enmXSave;
1034	CPUMISAEXTCFG enmAesNi;
1035	CPUMISAEXTCFG enmPClMul;
1036	CPUMISAEXTCFG enmPopCnt;
1037	CPUMISAEXTCFG enmMovBe;
1038	CPUMISAEXTCFG enmRdRand;
1039	CPUMISAEXTCFG enmRdSeed;
1040	CPUMISAEXTCFG enmCLFlushOpt;
1041	CPUMISAEXTCFG enmFsGsBase;
1042	CPUMISAEXTCFG enmPcid;
1043	CPUMISAEXTCFG enmInvpcid;
1044	CPUMISAEXTCFG enmFlushCmdMsr;
1045	CPUMISAEXTCFG enmMdsClear;
1046	CPUMISAEXTCFG enmArchCapMsr;
1047
1048	CPUMISAEXTCFG enmAbm;
1049	CPUMISAEXTCFG enmSse4A;
1050	CPUMISAEXTCFG enmMisAlnSse;
1051	CPUMISAEXTCFG enm3dNowPrf;
1052	CPUMISAEXTCFG enmAmdExtMmx;
1053
1054	uint32_t uMaxStdLeaf;
1055	uint32_t uMaxExtLeaf;
1056	uint32_t uMaxCentaurLeaf;
1057	uint32_t uMaxIntelFamilyModelStep;
1058	char szCpuName[128];
1059	} CPUMCPUIDCONFIG;
1060	/** Pointer to CPUID config (from CFGM). */
1061	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
1062
1063
1064	/**
1065	* Mini CPU selection support for making Mac OS X happy.
1066	*
1067	* Executes the /CPUM/MaxIntelFamilyModelStep config.
1068	*
1069	* @param pCpum The CPUM instance data.
1070	* @param pConfig The CPUID configuration we've read from CFGM.
1071	*/
1072	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1073	{
1074	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1075	{
1076	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1077	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(RTX86GetCpuStepping(pStdFeatureLeaf->uEax),
1078	RTX86GetCpuModelIntel(pStdFeatureLeaf->uEax),
1079	RTX86GetCpuFamily(pStdFeatureLeaf->uEax),
1080	0);
1081	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
1082	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1083	{
1084	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
1085	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1086	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1087	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1088	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1089	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1090	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1091	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1092	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1093	pStdFeatureLeaf->uEax = uNew;
1094	}
1095	}
1096	}
1097
1098
1099
1100	/**
1101	* Limit it the number of entries, zapping the remainder.
1102	*
1103	* The limits are masking off stuff about power saving and similar, this
1104	* is perhaps a bit crudely done as there is probably some relatively harmless
1105	* info too in these leaves (like words about having a constant TSC).
1106	*
1107	* @param pCpum The CPUM instance data.
1108	* @param pConfig The CPUID configuration we've read from CFGM.
1109	*/
1110	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1111	{
1112	/*
1113	* Standard leaves.
1114	*/
1115	uint32_t uSubLeaf = 0;
1116	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
1117	if (pCurLeaf)
1118	{
1119	uint32_t uLimit = pCurLeaf->uEax;
1120	if (uLimit <= UINT32_C(0x000fffff))
1121	{
1122	if (uLimit > pConfig->uMaxStdLeaf)
1123	{
1124	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
1125	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1126	uLimit + 1, UINT32_C(0x000fffff));
1127	}
1128
1129	/* NT4 hack, no zapping of extra leaves here. */
1130	if (pConfig->fNt4LeafLimit && uLimit > 3)
1131	pCurLeaf->uEax = uLimit = 3;
1132
1133	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
1134	pCurLeaf->uEax = uLimit;
1135	}
1136	else
1137	{
1138	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
1139	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1140	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
1141	}
1142	}
1143
1144	/*
1145	* Extended leaves.
1146	*/
1147	uSubLeaf = 0;
1148	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
1149	if (pCurLeaf)
1150	{
1151	uint32_t uLimit = pCurLeaf->uEax;
1152	if ( uLimit >= UINT32_C(0x80000000)
1153	&& uLimit <= UINT32_C(0x800fffff))
1154	{
1155	if (uLimit > pConfig->uMaxExtLeaf)
1156	{
1157	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
1158	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1159	uLimit + 1, UINT32_C(0x800fffff));
1160	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
1161	pCurLeaf->uEax = uLimit;
1162	}
1163	}
1164	else
1165	{
1166	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
1167	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1168	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
1169	}
1170	}
1171
1172	/*
1173	* Centaur leaves (VIA).
1174	*/
1175	uSubLeaf = 0;
1176	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
1177	if (pCurLeaf)
1178	{
1179	uint32_t uLimit = pCurLeaf->uEax;
1180	if ( uLimit >= UINT32_C(0xc0000000)
1181	&& uLimit <= UINT32_C(0xc00fffff))
1182	{
1183	if (uLimit > pConfig->uMaxCentaurLeaf)
1184	{
1185	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
1186	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1187	uLimit + 1, UINT32_C(0xcfffffff));
1188	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
1189	pCurLeaf->uEax = uLimit;
1190	}
1191	}
1192	else
1193	{
1194	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
1195	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1196	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
1197	}
1198	}
1199	}
1200
1201
1202	/**
1203	* Clears a CPUID leaf and all sub-leaves (to zero).
1204	*
1205	* @param pCpum The CPUM instance data.
1206	* @param uLeaf The leaf to clear.
1207	*/
1208	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
1209	{
1210	uint32_t uSubLeaf = 0;
1211	PCPUMCPUIDLEAF pCurLeaf;
1212	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
1213	{
1214	pCurLeaf->uEax = 0;
1215	pCurLeaf->uEbx = 0;
1216	pCurLeaf->uEcx = 0;
1217	pCurLeaf->uEdx = 0;
1218	uSubLeaf++;
1219	}
1220	}
1221
1222
1223	/**
1224	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
1225	* the given leaf.
1226	*
1227	* @returns pLeaf.
1228	* @param pCpum The CPUM instance data.
1229	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
1230	*/
1231	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
1232	{
1233	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
1234	if (pLeaf->fSubLeafMask != 0)
1235	{
1236	/*
1237	* Figure out how many sub-leaves in need of removal (we'll keep the first).
1238	* Log everything while we're at it.
1239	*/
1240	LogRel(("CPUM:\n"
1241	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
1242	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
1243	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
1244	for (;;)
1245	{
1246	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
1247	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
1248	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
1249	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
1250	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
1251	break;
1252	pSubLeaf++;
1253	}
1254	LogRel(("CPUM:\n"));
1255
1256	/*
1257	* Remove the offending sub-leaves.
1258	*/
1259	if (pSubLeaf != pLeaf)
1260	{
1261	if (pSubLeaf != pLast)
1262	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
1263	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
1264	}
1265
1266	/*
1267	* Convert the first sub-leaf into a single leaf.
1268	*/
1269	pLeaf->uSubLeaf = 0;
1270	pLeaf->fSubLeafMask = 0;
1271	}
1272	return pLeaf;
1273	}
1274
1275
1276	/**
1277	* Sanitizes and adjust the CPUID leaves.
1278	*
1279	* Drop features that aren't virtualized (or virtualizable). Adjust information
1280	* and capabilities to fit the virtualized hardware. Remove information the
1281	* guest shouldn't have (because it's wrong in the virtual world or because it
1282	* gives away host details) or that we don't have documentation for and no idea
1283	* what means.
1284	*
1285	* @returns VBox status code.
1286	* @param pVM The cross context VM structure (for cCpus).
1287	* @param pCpum The CPUM instance data.
1288	* @param pConfig The CPUID configuration we've read from CFGM.
1289	*/
1290	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1291	{
1292	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
1293	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
1294	{ \
1295	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
1296	(a_pLeafReg) &= ~(uint32_t)(fMask); \
1297	}
1298	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
1299	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
1300	{ \
1301	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1302	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1303	}
1304	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
1305	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
1306	&& ((a_pLeafReg) & (fBitMask)) \
1307	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
1308	{ \
1309	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1310	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1311	}
1312	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
1313
1314	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
1315	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
1316	PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
1317	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
1318	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
1319	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
1320	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
1321	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
1322
1323	/* Cpuid 1:
1324	* EAX: CPU model, family and stepping.
1325	*
1326	* ECX + EDX: Supported features. Only report features we can support.
1327	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1328	* options may require adjusting (i.e. stripping what was enabled).
1329	*
1330	* EBX: Branding, CLFLUSH line size, logical processors per package and
1331	* initial APIC ID.
1332	*/
1333	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
1334	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
1335	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
1336
1337	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
1338	\| X86_CPUID_FEATURE_EDX_VME
1339	\| X86_CPUID_FEATURE_EDX_DE
1340	\| X86_CPUID_FEATURE_EDX_PSE
1341	\| X86_CPUID_FEATURE_EDX_TSC
1342	\| X86_CPUID_FEATURE_EDX_MSR
1343	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
1344	\| X86_CPUID_FEATURE_EDX_MCE
1345	\| X86_CPUID_FEATURE_EDX_CX8
1346	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
1347	//\| RT_BIT_32(10) - not defined
1348	\| X86_CPUID_FEATURE_EDX_SEP
1349	\| X86_CPUID_FEATURE_EDX_MTRR
1350	\| X86_CPUID_FEATURE_EDX_PGE
1351	\| X86_CPUID_FEATURE_EDX_MCA
1352	\| X86_CPUID_FEATURE_EDX_CMOV
1353	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
1354	\| X86_CPUID_FEATURE_EDX_PSE36
1355	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
1356	\| X86_CPUID_FEATURE_EDX_CLFSH
1357	//\| RT_BIT_32(20) - not defined
1358	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
1359	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
1360	\| X86_CPUID_FEATURE_EDX_MMX
1361	\| X86_CPUID_FEATURE_EDX_FXSR
1362	\| X86_CPUID_FEATURE_EDX_SSE
1363	\| X86_CPUID_FEATURE_EDX_SSE2
1364	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
1365	\| X86_CPUID_FEATURE_EDX_HTT
1366	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
1367	//\| RT_BIT_32(30) - not defined
1368	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
1369	;
1370	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
1371	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
1372	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
1373	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
1374	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
1375	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
1376	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
1377	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
1378	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
1379	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
1380	\| X86_CPUID_FEATURE_ECX_SSSE3
1381	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
1382	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
1383	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fMovCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
1384	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
1385	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1386	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
1387	\| PASSTHRU_FEATURE(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
1388	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
1389	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
1390	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
1391	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
1392	\| PASSTHRU_FEATURE_TODO(pConfig->enmMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
1393	\| PASSTHRU_FEATURE(pConfig->enmPopCnt, pHstFeat->fPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
1394	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
1395	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
1396	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
1397	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
1398	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
1399	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
1400	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
1401	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
1402	;
1403
1404	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1405	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1406	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
1407	{
1408	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
1409	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
1410	}
1411
1412	if (pCpum->u8PortableCpuIdLevel > 0)
1413	{
1414	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
1415	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
1416	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
1417	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
1418	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
1419	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
1420	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
1421	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
1422	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
1423	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
1424	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
1425	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
1426	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
1427	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
1428	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
1429	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
1430	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
1431	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
1432	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
1433	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
1434
1435	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP ///??
1436	\| X86_CPUID_FEATURE_EDX_PSN
1437	\| X86_CPUID_FEATURE_EDX_DS
1438	\| X86_CPUID_FEATURE_EDX_ACPI
1439	\| X86_CPUID_FEATURE_EDX_SS
1440	\| X86_CPUID_FEATURE_EDX_TM
1441	\| X86_CPUID_FEATURE_EDX_PBE
1442	)));
1443	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
1444	\| X86_CPUID_FEATURE_ECX_CPLDS
1445	\| X86_CPUID_FEATURE_ECX_AES
1446	\| X86_CPUID_FEATURE_ECX_VMX
1447	\| X86_CPUID_FEATURE_ECX_SMX
1448	\| X86_CPUID_FEATURE_ECX_EST
1449	\| X86_CPUID_FEATURE_ECX_TM2
1450	\| X86_CPUID_FEATURE_ECX_CNTXID
1451	\| X86_CPUID_FEATURE_ECX_FMA
1452	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1453	\| X86_CPUID_FEATURE_ECX_PDCM
1454	\| X86_CPUID_FEATURE_ECX_DCA
1455	\| X86_CPUID_FEATURE_ECX_OSXSAVE
1456	)));
1457	}
1458
1459	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
1460	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
1461
1462	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
1463	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
1464	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
1465	*/
1466	#ifdef VBOX_WITH_MULTI_CORE
1467	if (pVM->cCpus > 1)
1468	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
1469	#endif
1470	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
1471	{
1472	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
1473	core times the number of CPU cores per processor */
1474	#ifdef VBOX_WITH_MULTI_CORE
1475	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
1476	#else
1477	/* Single logical processor in a package. */
1478	pStdFeatureLeaf->uEbx \|= (1 << 16);
1479	#endif
1480	}
1481
1482	uint32_t uMicrocodeRev;
1483	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
1484	if (RT_SUCCESS(rc))
1485	{
1486	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
1487	}
1488	else
1489	{
1490	uMicrocodeRev = 0;
1491	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
1492	}
1493
1494	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
1495	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
1496	*/
1497	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
1498	/** @todo The following ASSUMES that Hygon uses the same version numbering
1499	* as AMD and that they shipped buggy firmware. */
1500	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
1501	&& uMicrocodeRev < 0x8001126
1502	&& !pConfig->fForceVme)
1503	{
1504	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
1505	LogRel(("CPUM: Zen VME workaround engaged\n"));
1506	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
1507	}
1508
1509	/* Force standard feature bits. */
1510	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
1511	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
1512	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
1513	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
1514	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
1515	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
1516	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1517	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
1518	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1519	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
1520	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
1521	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
1522	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1523	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
1524	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
1525	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
1526	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
1527	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
1528	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1529	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
1530	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
1531	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
1532
1533	pStdFeatureLeaf = NULL; /* Must refetch! */
1534
1535	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
1536	* AMD:
1537	* EAX: CPU model, family and stepping.
1538	*
1539	* ECX + EDX: Supported features. Only report features we can support.
1540	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1541	* options may require adjusting (i.e. stripping what was enabled).
1542	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
1543	*
1544	* EBX: Branding ID and package type (or reserved).
1545	*
1546	* Intel and probably most others:
1547	* EAX: 0
1548	* EBX: 0
1549	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
1550	*/
1551	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
1552	if (pExtFeatureLeaf)
1553	{
1554	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
1555
1556	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
1557	\| X86_CPUID_AMD_FEATURE_EDX_VME
1558	\| X86_CPUID_AMD_FEATURE_EDX_DE
1559	\| X86_CPUID_AMD_FEATURE_EDX_PSE
1560	\| X86_CPUID_AMD_FEATURE_EDX_TSC
1561	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
1562	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
1563	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
1564	\| X86_CPUID_AMD_FEATURE_EDX_CX8
1565	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
1566	//\| RT_BIT_32(10) - reserved
1567	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1568	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
1569	\| X86_CPUID_AMD_FEATURE_EDX_PGE
1570	\| X86_CPUID_AMD_FEATURE_EDX_MCA
1571	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
1572	\| X86_CPUID_AMD_FEATURE_EDX_PAT
1573	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
1574	//\| RT_BIT_32(18) - reserved
1575	//\| RT_BIT_32(19) - reserved
1576	\| X86_CPUID_EXT_FEATURE_EDX_NX
1577	//\| RT_BIT_32(21) - reserved
1578	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
1579	\| X86_CPUID_AMD_FEATURE_EDX_MMX
1580	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
1581	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
1582	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1583	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
1584	//\| RT_BIT_32(28) - reserved
1585	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
1586	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
1587	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
1588	;
1589	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1590	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
1591	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
1592	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1593	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
1594	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1595	\| PASSTHRU_FEATURE(pConfig->enmAbm, pHstFeat->fAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
1596	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
1597	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
1598	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1599	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1600	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
1601	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
1602	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1603	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
1604	//\| RT_BIT_32(14) - reserved
1605	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
1606	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
1607	//\| RT_BIT_32(17) - reserved
1608	//\| RT_BIT_32(18) - reserved
1609	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
1610	//\| RT_BIT_32(20) - reserved
1611	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
1612	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
1613	//\| RT_BIT_32(23) - reserved
1614	//\| RT_BIT_32(24) - reserved
1615	//\| RT_BIT_32(25) - reserved
1616	//\| RT_BIT_32(26) - reserved
1617	//\| RT_BIT_32(27) - reserved
1618	//\| RT_BIT_32(28) - reserved
1619	//\| RT_BIT_32(29) - reserved
1620	//\| RT_BIT_32(30) - reserved
1621	//\| RT_BIT_32(31) - reserved
1622	;
1623	#ifdef VBOX_WITH_MULTI_CORE
1624	if ( pVM->cCpus > 1
1625	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
1626	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
1627	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
1628	#endif
1629
1630	if (pCpum->u8PortableCpuIdLevel > 0)
1631	{
1632	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1633	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
1634	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
1635	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
1636	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
1637	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
1638	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
1639	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
1640	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
1641	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
1642	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1643	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1644	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1645	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1646	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1647	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1648
1649	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
1650	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1651	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1652	\| X86_CPUID_AMD_FEATURE_ECX_IBS
1653	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1654	\| X86_CPUID_AMD_FEATURE_ECX_WDT
1655	\| X86_CPUID_AMD_FEATURE_ECX_LWP
1656	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
1657	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
1658	\| UINT32_C(0xff964000)
1659	)));
1660	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
1661	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1662	\| RT_BIT(18)
1663	\| RT_BIT(19)
1664	\| RT_BIT(21)
1665	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
1666	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1667	\| RT_BIT(28)
1668	)));
1669	}
1670
1671	/* Force extended feature bits. */
1672	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
1673	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
1674	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
1675	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
1676	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
1677	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
1678	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
1679	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
1680	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1681	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
1682	}
1683	pExtFeatureLeaf = NULL; /* Must refetch! */
1684
1685
1686	/* Cpuid 2:
1687	* Intel: (Nondeterministic) Cache and TLB information
1688	* AMD: Reserved
1689	* VIA: Reserved
1690	* Safe to expose.
1691	*/
1692	uint32_t uSubLeaf = 0;
1693	PCPUMCPUIDLEAF pCurLeaf;
1694	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
1695	{
1696	if ((pCurLeaf->uEax & 0xff) > 1)
1697	{
1698	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
1699	pCurLeaf->uEax &= UINT32_C(0xffffff01);
1700	}
1701	uSubLeaf++;
1702	}
1703
1704	/* Cpuid 3:
1705	* Intel: EAX, EBX - reserved (transmeta uses these)
1706	* ECX, EDX - Processor Serial Number if available, otherwise reserved
1707	* AMD: Reserved
1708	* VIA: Reserved
1709	* Safe to expose
1710	*/
1711	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1712	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
1713	{
1714	uSubLeaf = 0;
1715	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
1716	{
1717	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1718	if (pCpum->u8PortableCpuIdLevel > 0)
1719	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1720	uSubLeaf++;
1721	}
1722	}
1723
1724	/* Cpuid 4 + ECX:
1725	* Intel: Deterministic Cache Parameters Leaf.
1726	* AMD: Reserved
1727	* VIA: Reserved
1728	* Safe to expose, except for EAX:
1729	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1730	* Bits 31-26: Maximum number of processor cores in this physical package**
1731	* Note: These SMP values are constant regardless of ECX
1732	*/
1733	uSubLeaf = 0;
1734	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
1735	{
1736	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
1737	#ifdef VBOX_WITH_MULTI_CORE
1738	if ( pVM->cCpus > 1
1739	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1740	{
1741	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1742	/* One logical processor with possibly multiple cores. */
1743	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1744	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
1745	}
1746	#endif
1747	uSubLeaf++;
1748	}
1749
1750	/* Cpuid 5: Monitor/mwait Leaf
1751	* Intel: ECX, EDX - reserved
1752	* EAX, EBX - Smallest and largest monitor line size
1753	* AMD: EDX - reserved
1754	* EAX, EBX - Smallest and largest monitor line size
1755	* ECX - extensions (ignored for now)
1756	* VIA: Reserved
1757	* Safe to expose
1758	*/
1759	uSubLeaf = 0;
1760	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
1761	{
1762	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1763	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
1764	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1765
1766	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1767	if (pConfig->enmMWaitExtensions)
1768	{
1769	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1770	/** @todo for now we just expose host's MWAIT C-states, although conceptually
1771	it shall be part of our power management virtualization model */
1772	#if 0
1773	/* MWAIT sub C-states */
1774	pCurLeaf->uEdx =
1775	(0 << 0) /* 0 in C0 */ \|
1776	(2 << 4) /* 2 in C1 */ \|
1777	(2 << 8) /* 2 in C2 */ \|
1778	(2 << 12) /* 2 in C3 */ \|
1779	(0 << 16) /* 0 in C4 */
1780	;
1781	#endif
1782	}
1783	else
1784	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1785	uSubLeaf++;
1786	}
1787
1788	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
1789	* Intel: Various stuff.
1790	* AMD: EAX, EBX, EDX - reserved.
1791	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
1792	* present. Same as intel.
1793	* VIA: ??
1794	*
1795	* We clear everything here for now.
1796	*/
1797	cpumR3CpuIdZeroLeaf(pCpum, 6);
1798
1799	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
1800	* EAX: Number of sub leaves.
1801	* EBX+ECX+EDX: Feature flags
1802	*
1803	* We only have documentation for one sub-leaf, so clear all other (no need
1804	* to remove them as such, just set them to zero).
1805	*
1806	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1807	* options may require adjusting (i.e. stripping what was enabled).
1808	*/
1809	uSubLeaf = 0;
1810	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
1811	{
1812	switch (uSubLeaf)
1813	{
1814	case 0:
1815	{
1816	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
1817	pCurLeaf->uEbx &= 0
1818	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
1819	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
1820	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
1821	\| X86_CPUID_STEXT_FEATURE_EBX_BMI1
1822	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
1823	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
1824	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
1825	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
1826	\| X86_CPUID_STEXT_FEATURE_EBX_BMI2
1827	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
1828	\| PASSTHRU_FEATURE(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
1829	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
1830	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
1831	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
1832	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
1833	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
1834	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
1835	//\| RT_BIT(17) - reserved
1836	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
1837	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
1838	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
1839	//\| RT_BIT(21) - reserved
1840	//\| RT_BIT(22) - reserved
1841	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
1842	//\| RT_BIT(24) - reserved
1843	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
1844	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
1845	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
1846	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
1847	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
1848	//\| RT_BIT(30) - reserved
1849	//\| RT_BIT(31) - reserved
1850	;
1851	pCurLeaf->uEcx &= 0
1852	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
1853	;
1854	pCurLeaf->uEdx &= 0
1855	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
1856	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
1857	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
1858	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
1859	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
1860	;
1861
1862	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1863	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1864	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
1865	{
1866	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1867	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
1868	}
1869
1870	if (pCpum->u8PortableCpuIdLevel > 0)
1871	{
1872	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
1873	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
1874	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
1875	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
1876	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
1877	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
1878	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1879	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
1880	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
1881	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
1882	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
1883	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
1884	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
1885	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
1886	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
1887	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
1888	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
1889	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
1890	}
1891
1892	/* Dependencies. */
1893	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
1894	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1895
1896	/* Force standard feature bits. */
1897	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
1898	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
1899	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1900	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
1901	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
1902	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
1903	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1904	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
1905	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
1906	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1907	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1908	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
1909	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
1910	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1911	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1912	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
1913	break;
1914	}
1915
1916	default:
1917	/* Invalid index, all values are zero. */
1918	pCurLeaf->uEax = 0;
1919	pCurLeaf->uEbx = 0;
1920	pCurLeaf->uEcx = 0;
1921	pCurLeaf->uEdx = 0;
1922	break;
1923	}
1924	uSubLeaf++;
1925	}
1926
1927	/* Cpuid 8: Marked as reserved by Intel and AMD.
1928	* We zero this since we don't know what it may have been used for.
1929	*/
1930	cpumR3CpuIdZeroLeaf(pCpum, 8);
1931
1932	/* Cpuid 9: Direct Cache Access (DCA) Parameters
1933	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1934	* EBX, ECX, EDX - reserved.
1935	* AMD: Reserved
1936	* VIA: ??
1937	*
1938	* We zero this.
1939	*/
1940	cpumR3CpuIdZeroLeaf(pCpum, 9);
1941
1942	/* Cpuid 0xa: Architectural Performance Monitor Features
1943	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1944	* EBX, ECX, EDX - reserved.
1945	* AMD: Reserved
1946	* VIA: ??
1947	*
1948	* We zero this, for now at least.
1949	*/
1950	cpumR3CpuIdZeroLeaf(pCpum, 10);
1951
1952	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
1953	* Intel: EAX - APCI ID shift right for next level.
1954	* EBX - Factory configured cores/threads at this level.
1955	* ECX - Level number (same as input) and level type (1,2,0).
1956	* EDX - Extended initial APIC ID.
1957	* AMD: Reserved
1958	* VIA: ??
1959	*/
1960	uSubLeaf = 0;
1961	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
1962	{
1963	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
1964	{
1965	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
1966	if (bLevelType == 1)
1967	{
1968	/* Thread level - we don't do threads at the moment. */
1969	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
1970	pCurLeaf->uEbx = 1;
1971	}
1972	else if (bLevelType == 2)
1973	{
1974	/* Core level. */
1975	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
1976	#ifdef VBOX_WITH_MULTI_CORE
1977	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
1978	pCurLeaf->uEax++;
1979	#endif
1980	pCurLeaf->uEbx = pVM->cCpus;
1981	}
1982	else
1983	{
1984	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
1985	pCurLeaf->uEax = 0;
1986	pCurLeaf->uEbx = 0;
1987	pCurLeaf->uEcx = 0;
1988	}
1989	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
1990	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
1991	}
1992	else
1993	{
1994	pCurLeaf->uEax = 0;
1995	pCurLeaf->uEbx = 0;
1996	pCurLeaf->uEcx = 0;
1997	pCurLeaf->uEdx = 0;
1998	}
1999	uSubLeaf++;
2000	}
2001
2002	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
2003	* We zero this since we don't know what it may have been used for.
2004	*/
2005	cpumR3CpuIdZeroLeaf(pCpum, 12);
2006
2007	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
2008	* ECX=0: EAX - Valid bits in XCR0[31:0].
2009	* EBX - Maximum state size as per current XCR0 value.
2010	* ECX - Maximum state size for all supported features.
2011	* EDX - Valid bits in XCR0[63:32].
2012	* ECX=1: EAX - Various X-features.
2013	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
2014	* ECX - Valid bits in IA32_XSS[31:0].
2015	* EDX - Valid bits in IA32_XSS[63:32].
2016	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
2017	* if the bit invalid all four registers are set to zero.
2018	* EAX - The state size for this feature.
2019	* EBX - The state byte offset of this feature.
2020	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
2021	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
2022	*
2023	* Clear them all as we don't currently implement extended CPU state.
2024	*/
2025	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
2026	uint64_t fGuestXcr0Mask = 0;
2027	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2028	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
2029	{
2030	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
2031	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
2032	fGuestXcr0Mask \|= XSAVE_C_YMM;
2033	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
2034	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
2035	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
2036	fGuestXcr0Mask &= pCpum->fXStateHostMask;
2037
2038	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
2039	}
2040	pStdFeatureLeaf = NULL;
2041	pCpum->fXStateGuestMask = fGuestXcr0Mask;
2042
2043	/* Work the sub-leaves. */
2044	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
2045	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
2046	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
2047	{
2048	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
2049	if (pCurLeaf)
2050	{
2051	if (fGuestXcr0Mask)
2052	{
2053	switch (uSubLeaf)
2054	{
2055	case 0:
2056	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
2057	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
2058	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2059	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
2060	VERR_CPUM_IPE_1);
2061	cbXSaveMaxActual = pCurLeaf->uEcx;
2062	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
2063	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
2064	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
2065	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
2066	VERR_CPUM_IPE_2);
2067	continue;
2068	case 1:
2069	pCurLeaf->uEax &= 0;
2070	pCurLeaf->uEcx &= 0;
2071	pCurLeaf->uEdx &= 0;
2072	/** @todo what about checking ebx? */
2073	continue;
2074	default:
2075	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
2076	{
2077	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
2078	&& pCurLeaf->uEax > 0
2079	&& pCurLeaf->uEbx < cbXSaveMaxActual
2080	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2081	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
2082	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
2083	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
2084	VERR_CPUM_IPE_2);
2085	AssertLogRel(!(pCurLeaf->uEcx & 1));
2086	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
2087	pCurLeaf->uEdx = 0; /* it's reserved... */
2088	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
2089	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
2090	continue;
2091	}
2092	break;
2093	}
2094	}
2095
2096	/* Clear the leaf. */
2097	pCurLeaf->uEax = 0;
2098	pCurLeaf->uEbx = 0;
2099	pCurLeaf->uEcx = 0;
2100	pCurLeaf->uEdx = 0;
2101	}
2102	}
2103
2104	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
2105	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
2106	{
2107	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
2108	if (pCurLeaf)
2109	{
2110	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
2111	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
2112	pCurLeaf->uEbx = cbXSaveMaxReport;
2113	pCurLeaf->uEcx = cbXSaveMaxReport;
2114	}
2115	}
2116
2117	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
2118	* We zero this since we don't know what it may have been used for.
2119	*/
2120	cpumR3CpuIdZeroLeaf(pCpum, 14);
2121
2122	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
2123	* also known as Intel Resource Director Technology (RDT) Monitoring
2124	* We zero this as we don't currently virtualize PQM.
2125	*/
2126	cpumR3CpuIdZeroLeaf(pCpum, 15);
2127
2128	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
2129	* also known as Intel Resource Director Technology (RDT) Allocation
2130	* We zero this as we don't currently virtualize PQE.
2131	*/
2132	cpumR3CpuIdZeroLeaf(pCpum, 16);
2133
2134	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
2135	* We zero this since we don't know what it may have been used for.
2136	*/
2137	cpumR3CpuIdZeroLeaf(pCpum, 17);
2138
2139	/* Cpuid 0x12 + ECX: SGX resource enumeration.
2140	* We zero this as we don't currently virtualize this.
2141	*/
2142	cpumR3CpuIdZeroLeaf(pCpum, 18);
2143
2144	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
2145	* We zero this since we don't know what it may have been used for.
2146	*/
2147	cpumR3CpuIdZeroLeaf(pCpum, 19);
2148
2149	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
2150	* We zero this as we don't currently virtualize this.
2151	*/
2152	cpumR3CpuIdZeroLeaf(pCpum, 20);
2153
2154	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
2155	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
2156	* EAX - denominator (unsigned).
2157	* EBX - numerator (unsigned).
2158	* ECX, EDX - reserved.
2159	* AMD: Reserved / undefined / not implemented.
2160	* VIA: Reserved / undefined / not implemented.
2161	* We zero this as we don't currently virtualize this.
2162	*/
2163	cpumR3CpuIdZeroLeaf(pCpum, 21);
2164
2165	/* Cpuid 0x16: Processor frequency info
2166	* Intel: EAX - Core base frequency in MHz.
2167	* EBX - Core maximum frequency in MHz.
2168	* ECX - Bus (reference) frequency in MHz.
2169	* EDX - Reserved.
2170	* AMD: Reserved / undefined / not implemented.
2171	* VIA: Reserved / undefined / not implemented.
2172	* We zero this as we don't currently virtualize this.
2173	*/
2174	cpumR3CpuIdZeroLeaf(pCpum, 22);
2175
2176	/* Cpuid 0x17..0x10000000: Unknown.
2177	* We don't know these and what they mean, so remove them. */
2178	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2179	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
2180
2181
2182	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
2183	* We remove all these as we're a hypervisor and must provide our own.
2184	*/
2185	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2186	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
2187
2188
2189	/* Cpuid 0x80000000 is harmless. */
2190
2191	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
2192
2193	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
2194
2195	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
2196	* Safe to pass on to the guest.
2197	*
2198	* AMD: 0x800000005 L1 cache information
2199	* 0x800000006 L2/L3 cache information
2200	* Intel: 0x800000005 reserved
2201	* 0x800000006 L2 cache information
2202	* VIA: 0x800000005 TLB and L1 cache information
2203	* 0x800000006 L2 cache information
2204	*/
2205
2206	/* Cpuid 0x800000007: Advanced Power Management Information.
2207	* AMD: EAX: Processor feedback capabilities.
2208	* EBX: RAS capabilites.
2209	* ECX: Advanced power monitoring interface.
2210	* EDX: Enhanced power management capabilities.
2211	* Intel: EAX, EBX, ECX - reserved.
2212	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
2213	* VIA: Reserved
2214	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
2215	*/
2216	uSubLeaf = 0;
2217	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
2218	{
2219	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
2220	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2221	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2222	{
2223	/*
2224	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
2225	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
2226	* bit is now configurable.
2227	*/
2228	pCurLeaf->uEdx &= 0
2229	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
2230	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
2231	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
2232	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
2233	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
2234	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
2235	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
2236	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
2237	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
2238	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
2239	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
2240	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
2241	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
2242	\| 0;
2243	}
2244	else
2245	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2246	if (!pConfig->fInvariantTsc)
2247	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2248	uSubLeaf++;
2249	}
2250
2251	/* Cpuid 0x80000008:
2252	* AMD: EBX, EDX - reserved
2253	* EAX: Virtual/Physical/Guest address Size
2254	* ECX: Number of cores + APICIdCoreIdSize
2255	* Intel: EAX: Virtual/Physical address Size
2256	* EBX, ECX, EDX - reserved
2257	* VIA: EAX: Virtual/Physical address Size
2258	* EBX, ECX, EDX - reserved
2259	*
2260	* We only expose the virtual+pysical address size to the guest atm.
2261	* On AMD we set the core count, but not the apic id stuff as we're
2262	* currently not doing the apic id assignments in a complatible manner.
2263	*/
2264	uSubLeaf = 0;
2265	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
2266	{
2267	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
2268	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
2269	pCurLeaf->uEdx = 0; /* reserved */
2270
2271	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
2272	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
2273	pCurLeaf->uEcx = 0;
2274	#ifdef VBOX_WITH_MULTI_CORE
2275	if ( pVM->cCpus > 1
2276	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2277	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
2278	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
2279	#endif
2280	uSubLeaf++;
2281	}
2282
2283	/* Cpuid 0x80000009: Reserved
2284	* We zero this since we don't know what it may have been used for.
2285	*/
2286	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
2287
2288	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
2289	* AMD: EAX - SVM revision.
2290	* EBX - Number of ASIDs.
2291	* ECX - Reserved.
2292	* EDX - SVM Feature identification.
2293	*/
2294	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2295	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2296	{
2297	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2298	if ( pExtFeatureLeaf
2299	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
2300	{
2301	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
2302	if (pSvmFeatureLeaf)
2303	{
2304	pSvmFeatureLeaf->uEax = 0x1;
2305	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
2306	pSvmFeatureLeaf->uEcx = 0;
2307	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
2308	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
2309	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
2310	}
2311	else
2312	{
2313	/* Should never happen. */
2314	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
2315	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2316	}
2317	}
2318	else
2319	{
2320	/* If SVM is not supported, this is reserved, zero out. */
2321	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2322	}
2323	}
2324	else
2325	{
2326	/* Cpuid 0x8000000a: Reserved on Intel.
2327	* We zero this since we don't know what it may have been used for.
2328	*/
2329	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2330	}
2331
2332	/* Cpuid 0x8000000b thru 0x80000018: Reserved
2333	* We clear these as we don't know what purpose they might have. */
2334	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
2335	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
2336
2337	/* Cpuid 0x80000019: TLB configuration
2338	* Seems to be harmless, pass them thru as is. */
2339
2340	/* Cpuid 0x8000001a: Peformance optimization identifiers.
2341	* Strip anything we don't know what is or addresses feature we don't implement. */
2342	uSubLeaf = 0;
2343	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
2344	{
2345	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
2346	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
2347	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
2348	;
2349	pCurLeaf->uEbx = 0; /* reserved */
2350	pCurLeaf->uEcx = 0; /* reserved */
2351	pCurLeaf->uEdx = 0; /* reserved */
2352	uSubLeaf++;
2353	}
2354
2355	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
2356	* Clear this as we don't currently virtualize this feature. */
2357	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
2358
2359	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
2360	* Clear this as we don't currently virtualize this feature. */
2361	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
2362
2363	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
2364	* We need to sanitize the cores per cache (EAX[25:14]).
2365	*
2366	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
2367	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
2368	* slightly different meaning.
2369	*/
2370	uSubLeaf = 0;
2371	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
2372	{
2373	#ifdef VBOX_WITH_MULTI_CORE
2374	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
2375	if (cCores > pVM->cCpus)
2376	cCores = pVM->cCpus;
2377	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2378	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
2379	#else
2380	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2381	#endif
2382	uSubLeaf++;
2383	}
2384
2385	/* Cpuid 0x8000001e: Get APIC / unit / node information.
2386	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
2387	* setup, we have one compute unit with all the cores in it. Single node.
2388	*/
2389	uSubLeaf = 0;
2390	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
2391	{
2392	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
2393	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2394	{
2395	#ifdef VBOX_WITH_MULTI_CORE
2396	pCurLeaf->uEbx = pVM->cCpus < 0x100
2397	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
2398	#else
2399	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
2400	#endif
2401	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
2402	}
2403	else
2404	{
2405	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
2406	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
2407	pCurLeaf->uEbx = 0; /* Reserved. */
2408	pCurLeaf->uEcx = 0; /* Reserved. */
2409	}
2410	pCurLeaf->uEdx = 0; /* Reserved. */
2411	uSubLeaf++;
2412	}
2413
2414	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
2415	* We don't know these and what they mean, so remove them. */
2416	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2417	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
2418
2419	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
2420	* Just pass it thru for now. */
2421
2422	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
2423	* Just pass it thru for now. */
2424
2425	/* Cpuid 0xc0000000: Centaur stuff.
2426	* Harmless, pass it thru. */
2427
2428	/* Cpuid 0xc0000001: Centaur features.
2429	* VIA: EAX - Family, model, stepping.
2430	* EDX - Centaur extended feature flags. Nothing interesting, except may
2431	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
2432	* EBX, ECX - reserved.
2433	* We keep EAX but strips the rest.
2434	*/
2435	uSubLeaf = 0;
2436	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
2437	{
2438	pCurLeaf->uEbx = 0;
2439	pCurLeaf->uEcx = 0;
2440	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
2441	uSubLeaf++;
2442	}
2443
2444	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
2445	* We only have fixed stale values, but should be harmless. */
2446
2447	/* Cpuid 0xc0000003: Reserved.
2448	* We zero this since we don't know what it may have been used for.
2449	*/
2450	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
2451
2452	/* Cpuid 0xc0000004: Centaur Performance Info.
2453	* We only have fixed stale values, but should be harmless. */
2454
2455
2456	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
2457	* We don't know these and what they mean, so remove them. */
2458	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2459	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
2460
2461	return VINF_SUCCESS;
2462	#undef PORTABLE_DISABLE_FEATURE_BIT
2463	#undef PORTABLE_CLEAR_BITS_WHEN
2464	}
2465
2466
2467	/**
2468	* Reads a value in /CPUM/IsaExts/ node.
2469	*
2470	* @returns VBox status code (error message raised).
2471	* @param pVM The cross context VM structure. (For errors.)
2472	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2473	* @param pszValueName The value / extension name.
2474	* @param penmValue Where to return the choice.
2475	* @param enmDefault The default choice.
2476	*/
2477	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2478	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2479	{
2480	/*
2481	* Try integer encoding first.
2482	*/
2483	uint64_t uValue;
2484	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
2485	if (RT_SUCCESS(rc))
2486	switch (uValue)
2487	{
2488	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
2489	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
2490	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
2491	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
2492	default:
2493	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2494	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2495	pszValueName, uValue);
2496	}
2497	/*
2498	* If missing, use default.
2499	*/
2500	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
2501	*penmValue = enmDefault;
2502	else
2503	{
2504	if (rc == VERR_CFGM_NOT_INTEGER)
2505	{
2506	/*
2507	* Not an integer, try read it as a string.
2508	*/
2509	char szValue[32];
2510	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
2511	if (RT_SUCCESS(rc))
2512	{
2513	RTStrToLower(szValue);
2514	size_t cchValue = strlen(szValue);
2515	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
2516	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
2517	*penmValue = CPUMISAEXTCFG_DISABLED;
2518	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
2519	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
2520	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
2521	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
2522	else if (EQ("portable"))
2523	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
2524	else if (EQ("default") \|\| EQ("def"))
2525	*penmValue = enmDefault;
2526	else
2527	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2528	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2529	pszValueName, uValue);
2530	#undef EQ
2531	}
2532	}
2533	if (RT_FAILURE(rc))
2534	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
2535	}
2536	return VINF_SUCCESS;
2537	}
2538
2539
2540	/**
2541	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
2542	*
2543	* @returns VBox status code (error message raised).
2544	* @param pVM The cross context VM structure. (For errors.)
2545	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2546	* @param pszValueName The value / extension name.
2547	* @param penmValue Where to return the choice.
2548	* @param enmDefault The default choice.
2549	* @param fAllowed Allowed choice. Applied both to the result and to
2550	* the default value.
2551	*/
2552	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2553	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
2554	{
2555	int rc;
2556	if (fAllowed)
2557	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2558	else
2559	{
2560	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
2561	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
2562	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
2563	*penmValue = CPUMISAEXTCFG_DISABLED;
2564	}
2565	return rc;
2566	}
2567
2568
2569	/**
2570	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
2571	*
2572	* @returns VBox status code (error message raised).
2573	* @param pVM The cross context VM structure. (For errors.)
2574	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2575	* @param pCpumCfg The /CPUM node (can be NULL).
2576	* @param pszValueName The value / extension name.
2577	* @param penmValue Where to return the choice.
2578	* @param enmDefault The default choice.
2579	*/
2580	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
2581	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2582	{
2583	if (CFGMR3Exists(pCpumCfg, pszValueName))
2584	{
2585	if (!CFGMR3Exists(pIsaExts, pszValueName))
2586	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
2587	else
2588	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
2589	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
2590	pszValueName, pszValueName);
2591
2592	bool fLegacy;
2593	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
2594	if (RT_SUCCESS(rc))
2595	{
2596	*penmValue = fLegacy;
2597	return VINF_SUCCESS;
2598	}
2599	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
2600	}
2601
2602	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2603	}
2604
2605
2606	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
2607	{
2608	int rc;
2609
2610	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
2611	* When non-zero CPUID features that could cause portability issues will be
2612	* stripped. The higher the value the more features gets stripped. Higher
2613	* values should only be used when older CPUs are involved since it may
2614	* harm performance and maybe also cause problems with specific guests. */
2615	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
2616	AssertLogRelRCReturn(rc, rc);
2617
2618	/** @cfgm{/CPUM/GuestCpuName, string}
2619	* The name of the CPU we're to emulate. The default is the host CPU.
2620	* Note! CPUs other than "host" one is currently unsupported. */
2621	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
2622	AssertLogRelRCReturn(rc, rc);
2623
2624	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
2625	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
2626	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
2627	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
2628	*/
2629	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
2630	AssertLogRelRCReturn(rc, rc);
2631
2632	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
2633	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
2634	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
2635	* 64-bit linux guests which assume the presence of AMD performance counters
2636	* that we do not virtualize.
2637	*/
2638	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
2639	AssertLogRelRCReturn(rc, rc);
2640
2641	/** @cfgm{/CPUM/ForceVme, boolean, false}
2642	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
2643	* By default the flag is passed thru as is from the host CPU, except
2644	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
2645	* guests and DOS boxes in general.
2646	*/
2647	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
2648	AssertLogRelRCReturn(rc, rc);
2649
2650	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
2651	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
2652	* probably going to be a temporary hack, so don't depend on this.
2653	* The 1st byte of the value is the stepping, the 2nd byte value is the model
2654	* number and the 3rd byte value is the family, and the 4th value must be zero.
2655	*/
2656	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
2657	AssertLogRelRCReturn(rc, rc);
2658
2659	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
2660	* The last standard leaf to keep. The actual last value that is stored in EAX
2661	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
2662	* removed. (This works independently of and differently from NT4LeafLimit.)
2663	* The default is usually set to what we're able to reasonably sanitize.
2664	*/
2665	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
2666	AssertLogRelRCReturn(rc, rc);
2667
2668	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
2669	* The last extended leaf to keep. The actual last value that is stored in EAX
2670	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
2671	* leaf are removed. The default is set to what we're able to sanitize.
2672	*/
2673	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
2674	AssertLogRelRCReturn(rc, rc);
2675
2676	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
2677	* The last extended leaf to keep. The actual last value that is stored in EAX
2678	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
2679	* leaf are removed. The default is set to what we're able to sanitize.
2680	*/
2681	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
2682	AssertLogRelRCReturn(rc, rc);
2683
2684	bool fQueryNestedHwvirt = false
2685	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2686	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2687	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
2688	#endif
2689	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2690	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
2691	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
2692	#endif
2693	;
2694	if (fQueryNestedHwvirt)
2695	{
2696	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
2697	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
2698	* The default is false, and when enabled requires a 64-bit CPU with support for
2699	* nested-paging and AMD-V or unrestricted guest mode.
2700	*/
2701	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
2702	AssertLogRelRCReturn(rc, rc);
2703	if (pConfig->fNestedHWVirt)
2704	{
2705	/** @todo Think about enabling this later with NEM/KVM. */
2706	if (VM_IS_NEM_ENABLED(pVM))
2707	{
2708	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used! (later)\n"));
2709	pConfig->fNestedHWVirt = false;
2710	}
2711	else if (!fNestedPagingAndFullGuestExec)
2712	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
2713	"Cannot enable nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n");
2714	}
2715
2716	if (pConfig->fNestedHWVirt)
2717	{
2718	/** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
2719	* Whether to expose the VMX-preemption timer feature to the guest (if also
2720	* supported by the host hardware). When disabled will prevent exposing the
2721	* VMX-preemption timer feature to the guest even if the host supports it.
2722	*
2723	* @todo Currently disabled, see @bugref{9180#c108}.
2724	*/
2725	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &pVM->cpum.s.fNestedVmxPreemptTimer, false);
2726	AssertLogRelRCReturn(rc, rc);
2727
2728	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2729	/** @cfgm{/CPUM/NestedVmxEpt, bool, true}
2730	* Whether to expose the EPT feature to the guest. The default is false. When
2731	* disabled will automatically prevent exposing features that rely on
2732	*/
2733	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &pVM->cpum.s.fNestedVmxEpt, false);
2734	AssertLogRelRCReturn(rc, rc);
2735
2736	/** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
2737	* Whether to expose the Unrestricted Guest feature to the guest. The default is
2738	* false. When disabled will automatically prevent exposing features that rely on
2739	* it.
2740	*/
2741	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &pVM->cpum.s.fNestedVmxUnrestrictedGuest, false);
2742	AssertLogRelRCReturn(rc, rc);
2743
2744	if ( pVM->cpum.s.fNestedVmxUnrestrictedGuest
2745	&& !pVM->cpum.s.fNestedVmxEpt)
2746	{
2747	LogRel(("CPUM: WARNING! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
2748	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
2749	}
2750	#endif
2751	}
2752	}
2753
2754	/*
2755	* Instruction Set Architecture (ISA) Extensions.
2756	*/
2757	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
2758	if (pIsaExts)
2759	{
2760	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
2761	"CMPXCHG16B"
2762	"\|MONITOR"
2763	"\|MWaitExtensions"
2764	"\|SSE4.1"
2765	"\|SSE4.2"
2766	"\|XSAVE"
2767	"\|AVX"
2768	"\|AVX2"
2769	"\|AESNI"
2770	"\|PCLMUL"
2771	"\|POPCNT"
2772	"\|MOVBE"
2773	"\|RDRAND"
2774	"\|RDSEED"
2775	"\|CLFLUSHOPT"
2776	"\|FSGSBASE"
2777	"\|PCID"
2778	"\|INVPCID"
2779	"\|FlushCmdMsr"
2780	"\|ABM"
2781	"\|SSE4A"
2782	"\|MISALNSSE"
2783	"\|3DNOWPRF"
2784	"\|AXMMX"
2785	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
2786	if (RT_FAILURE(rc))
2787	return rc;
2788	}
2789
2790	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
2791	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
2792	* hardware virtualization have it.
2793	*/
2794	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
2795	AssertLogRelRCReturn(rc, rc);
2796
2797	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
2798	* Expose MONITOR/MWAIT instructions to the guest.
2799	*/
2800	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
2801	AssertLogRelRCReturn(rc, rc);
2802
2803	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
2804	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
2805	* break on interrupt feature (bit 1).
2806	*/
2807	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
2808	AssertLogRelRCReturn(rc, rc);
2809
2810	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
2811	* Expose SSE4.1 to the guest if available.
2812	*/
2813	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
2814	AssertLogRelRCReturn(rc, rc);
2815
2816	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
2817	* Expose SSE4.2 to the guest if available.
2818	*/
2819	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
2820	AssertLogRelRCReturn(rc, rc);
2821
2822	bool const fMayHaveXSave = pVM->cpum.s.HostFeatures.fXSaveRstor
2823	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
2824	&& ( VM_IS_NEM_ENABLED(pVM)
2825	? NEMHCGetFeatures(pVM) & NEM_FEAT_F_XSAVE_XRSTOR
2826	: VM_IS_EXEC_ENGINE_IEM(pVM)
2827	? false /** @todo IEM and XSAVE @bugref{9898} */
2828	: fNestedPagingAndFullGuestExec);
2829	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
2830
2831	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
2832	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
2833	* default is to only expose this to VMs with nested paging and AMD-V or
2834	* unrestricted guest execution mode. Not possible to force this one without
2835	* host support at the moment.
2836	*/
2837	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
2838	fMayHaveXSave /fAllowed/);
2839	AssertLogRelRCReturn(rc, rc);
2840
2841	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
2842	* Expose the AVX instruction set extensions to the guest if available and
2843	* XSAVE is exposed too. For the time being the default is to only expose this
2844	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2845	*/
2846	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
2847	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2848	AssertLogRelRCReturn(rc, rc);
2849
2850	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
2851	* Expose the AVX2 instruction set extensions to the guest if available and
2852	* XSAVE is exposed too. For the time being the default is to only expose this
2853	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2854	*/
2855	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
2856	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2857	AssertLogRelRCReturn(rc, rc);
2858
2859	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
2860	* Whether to expose the AES instructions to the guest. For the time being the
2861	* default is to only do this for VMs with nested paging and AMD-V or
2862	* unrestricted guest mode.
2863	*/
2864	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
2865	AssertLogRelRCReturn(rc, rc);
2866
2867	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
2868	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
2869	* being the default is to only do this for VMs with nested paging and AMD-V or
2870	* unrestricted guest mode.
2871	*/
2872	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
2873	AssertLogRelRCReturn(rc, rc);
2874
2875	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, true}
2876	* Whether to expose the POPCNT instructions to the guest.
2877	*/
2878	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2879	AssertLogRelRCReturn(rc, rc);
2880
2881	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
2882	* Whether to expose the MOVBE instructions to the guest. For the time
2883	* being the default is to only do this for VMs with nested paging and AMD-V or
2884	* unrestricted guest mode.
2885	*/
2886	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
2887	AssertLogRelRCReturn(rc, rc);
2888
2889	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
2890	* Whether to expose the RDRAND instructions to the guest. For the time being
2891	* the default is to only do this for VMs with nested paging and AMD-V or
2892	* unrestricted guest mode.
2893	*/
2894	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
2895	AssertLogRelRCReturn(rc, rc);
2896
2897	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
2898	* Whether to expose the RDSEED instructions to the guest. For the time being
2899	* the default is to only do this for VMs with nested paging and AMD-V or
2900	* unrestricted guest mode.
2901	*/
2902	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
2903	AssertLogRelRCReturn(rc, rc);
2904
2905	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
2906	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
2907	* being the default is to only do this for VMs with nested paging and AMD-V or
2908	* unrestricted guest mode.
2909	*/
2910	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
2911	AssertLogRelRCReturn(rc, rc);
2912
2913	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
2914	* Whether to expose the read/write FSGSBASE instructions to the guest.
2915	*/
2916	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
2917	AssertLogRelRCReturn(rc, rc);
2918
2919	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
2920	* Whether to expose the PCID feature to the guest.
2921	*/
2922	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
2923	AssertLogRelRCReturn(rc, rc);
2924
2925	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
2926	* Whether to expose the INVPCID instruction to the guest.
2927	*/
2928	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
2929	AssertLogRelRCReturn(rc, rc);
2930
2931	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
2932	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
2933	*/
2934	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2935	AssertLogRelRCReturn(rc, rc);
2936
2937	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
2938	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
2939	* the guest. Requires FlushCmdMsr to be present too.
2940	*/
2941	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2942	AssertLogRelRCReturn(rc, rc);
2943
2944	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
2945	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
2946	*/
2947	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2948	AssertLogRelRCReturn(rc, rc);
2949
2950
2951	/* AMD: */
2952
2953	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, true}
2954	* Whether to expose the AMD ABM instructions to the guest.
2955	*/
2956	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2957	AssertLogRelRCReturn(rc, rc);
2958
2959	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
2960	* Whether to expose the AMD SSE4A instructions to the guest. For the time
2961	* being the default is to only do this for VMs with nested paging and AMD-V or
2962	* unrestricted guest mode.
2963	*/
2964	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
2965	AssertLogRelRCReturn(rc, rc);
2966
2967	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
2968	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
2969	* the time being the default is to only do this for VMs with nested paging and
2970	* AMD-V or unrestricted guest mode.
2971	*/
2972	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
2973	AssertLogRelRCReturn(rc, rc);
2974
2975	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
2976	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
2977	* For the time being the default is to only do this for VMs with nested paging
2978	* and AMD-V or unrestricted guest mode.
2979	*/
2980	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
2981	AssertLogRelRCReturn(rc, rc);
2982
2983	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
2984	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
2985	* the default is to only do this for VMs with nested paging and AMD-V or
2986	* unrestricted guest mode.
2987	*/
2988	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
2989	AssertLogRelRCReturn(rc, rc);
2990
2991	return VINF_SUCCESS;
2992	}
2993
2994
2995	/**
2996	* Initializes the emulated CPU's CPUID & MSR information.
2997	*
2998	* @returns VBox status code.
2999	* @param pVM The cross context VM structure.
3000	* @param pHostMsrs Pointer to the host MSRs.
3001	*/
3002	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
3003	{
3004	Assert(pHostMsrs);
3005
3006	PCPUM pCpum = &pVM->cpum.s;
3007	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3008
3009	/*
3010	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
3011	* on construction and manage everything from here on.
3012	*/
3013	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3014	{
3015	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3016	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
3017	}
3018
3019	/*
3020	* Read the configuration.
3021	*/
3022	CPUMCPUIDCONFIG Config;
3023	RT_ZERO(Config);
3024
3025	bool const fNestedPagingAndFullGuestExec = VM_IS_NEM_ENABLED(pVM)
3026	\|\| HMAreNestedPagingAndFullGuestExecEnabled(pVM);
3027	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, fNestedPagingAndFullGuestExec);
3028	AssertRCReturn(rc, rc);
3029
3030	/*
3031	* Get the guest CPU data from the database and/or the host.
3032	*
3033	* The CPUID and MSRs are currently living on the regular heap to avoid
3034	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3035	* API for the hyper heap). This means special cleanup considerations.
3036	*/
3037	/** @todo The hyper heap will be removed ASAP, so the final destination is
3038	* now a fixed sized arrays in the VM structure. Maybe we can simplify
3039	* this allocation fun a little now? Or maybe it's too convenient for
3040	* the CPU reporter code... No time to figure that out now. */
3041	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3042	if (RT_FAILURE(rc))
3043	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3044	? VMSetError(pVM, rc, RT_SRC_POS,
3045	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3046	: rc;
3047
3048	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
3049	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
3050	{
3051	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
3052	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3053	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
3054	}
3055	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3056	#else
3057	LogRel(("CPUM: MXCSR_MASK=%#x\n", pCpum->GuestInfo.fMxCsrMask));
3058	#endif
3059
3060	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3061	* Overrides the guest MSRs.
3062	*/
3063	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3064
3065	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3066	* Overrides the CPUID leaf values (from the host CPU usually) used for
3067	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3068	* values when moving a VM to a different machine. Another use is restricting
3069	* (or extending) the feature set exposed to the guest. */
3070	if (RT_SUCCESS(rc))
3071	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3072
3073	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3074	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3075	"Found unsupported configuration node '/CPUM/CPUID/'. "
3076	"Please use IMachine::setCPUIDLeaf() instead.");
3077
3078	CPUMMSRS GuestMsrs;
3079	RT_ZERO(GuestMsrs);
3080
3081	/*
3082	* Pre-explode the CPUID info.
3083	*/
3084	if (RT_SUCCESS(rc))
3085	rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
3086	&pCpum->GuestFeatures);
3087
3088	/*
3089	* Sanitize the cpuid information passed on to the guest.
3090	*/
3091	if (RT_SUCCESS(rc))
3092	{
3093	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3094	if (RT_SUCCESS(rc))
3095	{
3096	cpumR3CpuIdLimitLeaves(pCpum, &Config);
3097	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3098	}
3099	}
3100
3101	/*
3102	* Setup MSRs introduced in microcode updates or that are otherwise not in
3103	* the CPU profile, but are advertised in the CPUID info we just sanitized.
3104	*/
3105	if (RT_SUCCESS(rc))
3106	rc = cpumR3MsrReconcileWithCpuId(pVM);
3107	/*
3108	* MSR fudging.
3109	*/
3110	if (RT_SUCCESS(rc))
3111	{
3112	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3113	* Fudges some common MSRs if not present in the selected CPU database entry.
3114	* This is for trying to keep VMs running when moved between different hosts
3115	* and different CPU vendors. */
3116	bool fEnable;
3117	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3118	if (RT_SUCCESS(rc) && fEnable)
3119	{
3120	rc = cpumR3MsrApplyFudge(pVM);
3121	AssertLogRelRC(rc);
3122	}
3123	}
3124	if (RT_SUCCESS(rc))
3125	{
3126	/*
3127	* Move the MSR and CPUID arrays over to the static VM structure allocations
3128	* and explode guest CPU features again.
3129	*/
3130	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
3131	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
3132	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
3133	RTMemFree(pvFree);
3134
3135	AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
3136	("%u\n", pCpum->GuestInfo.cMsrRanges));
3137	memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
3138	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
3139	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3140	pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
3141
3142	AssertLogRelRCReturn(rc, rc);
3143
3144	/*
3145	* Finally, initialize guest VMX MSRs.
3146	*
3147	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
3148	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
3149	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
3150	*/
3151	/** @todo r=bird: given that long mode never used to be enabled before the
3152	* VMINITCOMPLETED_RING0 state, and we're a lot earlier here in ring-3
3153	* init, the above comment cannot be entirely accurate. */
3154	if (pVM->cpum.s.GuestFeatures.fVmx)
3155	{
3156	Assert(Config.fNestedHWVirt);
3157	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
3158
3159	/* Copy MSRs to all VCPUs */
3160	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
3161	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3162	{
3163	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3164	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
3165	}
3166	}
3167
3168	/*
3169	* Some more configuration that we're applying at the end of everything
3170	* via the CPUMR3SetGuestCpuIdFeature API.
3171	*/
3172
3173	/* Check if 64-bit guest supported was enabled. */
3174	bool fEnable64bit;
3175	rc = CFGMR3QueryBoolDef(pCpumCfg, "Enable64bit", &fEnable64bit, false);
3176	AssertRCReturn(rc, rc);
3177	if (fEnable64bit)
3178	{
3179	/* In case of a CPU upgrade: */
3180	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
3181	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
3182	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3183	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
3184	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3185
3186	/* The actual feature: */
3187	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
3188	}
3189
3190	/* Check if PAE was explicitely enabled by the user. */
3191	bool fEnable;
3192	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, fEnable64bit);
3193	AssertRCReturn(rc, rc);
3194	if (fEnable && !pVM->cpum.s.GuestFeatures.fPae)
3195	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3196
3197	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
3198	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, fEnable64bit);
3199	AssertRCReturn(rc, rc);
3200	if (fEnable && !pVM->cpum.s.GuestFeatures.fNoExecute)
3201	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3202
3203	/* Check if speculation control is enabled. */
3204	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
3205	AssertRCReturn(rc, rc);
3206	if (fEnable)
3207	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
3208	else
3209	{
3210	/*
3211	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
3212	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
3213	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
3214	*
3215	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
3216	* EIP: _raw_spin_lock+0x14/0x30
3217	* EFLAGS: 00010046 CPU: 0
3218	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
3219	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
3220	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
3221	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
3222	* Call Trace:
3223	* speculative_store_bypass_update+0x8e/0x180
3224	* ssb_prctl_set+0xc0/0xe0
3225	* arch_seccomp_spec_mitigate+0x1d/0x20
3226	* do_seccomp+0x3cb/0x610
3227	* SyS_seccomp+0x16/0x20
3228	* do_fast_syscall_32+0x7f/0x1d0
3229	* entry_SYSENTER_32+0x4e/0x7c
3230	*
3231	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
3232	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
3233	*
3234	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
3235	* guest to not even try.
3236	*/
3237	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3238	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3239	{
3240	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
3241	if (pLeaf)
3242	{
3243	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
3244	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
3245	}
3246	}
3247	}
3248
3249	return VINF_SUCCESS;
3250	}
3251
3252	/*
3253	* Failed before switching to hyper heap.
3254	*/
3255	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
3256	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
3257	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3258	pCpum->GuestInfo.paMsrRangesR3 = NULL;
3259	return rc;
3260	}
3261
3262
3263	/**
3264	* Sets a CPUID feature bit during VM initialization.
3265	*
3266	* Since the CPUID feature bits are generally related to CPU features, other
3267	* CPUM configuration like MSRs can also be modified by calls to this API.
3268	*
3269	* @param pVM The cross context VM structure.
3270	* @param enmFeature The feature to set.
3271	*/
3272	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3273	{
3274	PCPUMCPUIDLEAF pLeaf;
3275	PCPUMMSRRANGE pMsrRange;
3276
3277	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3278	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3279	if (!pVM->cpum.s.HostFeatures. a_fFeature) \
3280	{ \
3281	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when the host doesn't support it!\n")); \
3282	return; \
3283	} else do { } while (0)
3284	#else
3285	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) do { } while (0)
3286	#endif
3287
3288	#define GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3289	do \
3290	{ \
3291	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001)); \
3292	if (!pLeaf) \
3293	{ \
3294	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when no 0x80000001 CPUID leaf!\n")); \
3295	return; \
3296	} \
3297	CHECK_X86_HOST_FEATURE_RET(a_fFeature,a_szFeature); \
3298	} while (0)
3299
3300	switch (enmFeature)
3301	{
3302	/*
3303	* Set the APIC bit in both feature masks.
3304	*/
3305	case CPUMCPUIDFEATURE_APIC:
3306	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3307	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3308	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
3309
3310	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3311	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3312	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
3313
3314	pVM->cpum.s.GuestFeatures.fApic = 1;
3315
3316	/* Make sure we've got the APICBASE MSR present. */
3317	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3318	if (!pMsrRange)
3319	{
3320	static CPUMMSRRANGE const s_ApicBase =
3321	{
3322	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
3323	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
3324	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3325	/.szName = / "IA32_APIC_BASE"
3326	};
3327	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
3328	AssertLogRelRC(rc);
3329	}
3330
3331	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
3332	break;
3333
3334	/*
3335	* Set the x2APIC bit in the standard feature mask.
3336	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
3337	*/
3338	case CPUMCPUIDFEATURE_X2APIC:
3339	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3340	if (pLeaf)
3341	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
3342	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
3343
3344	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
3345	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3346	if (pMsrRange)
3347	{
3348	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
3349	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
3350	}
3351
3352	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
3353	break;
3354
3355	/*
3356	* Set the sysenter/sysexit bit in the standard feature mask.
3357	* Assumes the caller knows what it's doing! (host must support these)
3358	*/
3359	case CPUMCPUIDFEATURE_SEP:
3360	CHECK_X86_HOST_FEATURE_RET(fSysEnter, "SEP");
3361	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3362	if (pLeaf)
3363	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
3364	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
3365	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
3366	break;
3367
3368	/*
3369	* Set the syscall/sysret bit in the extended feature mask.
3370	* Assumes the caller knows what it's doing! (host must support these)
3371	*/
3372	case CPUMCPUIDFEATURE_SYSCALL:
3373	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fSysCall, "SYSCALL/SYSRET");
3374
3375	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
3376	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
3377	pVM->cpum.s.GuestFeatures.fSysCall = 1;
3378	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
3379	break;
3380
3381	/*
3382	* Set the PAE bit in both feature masks.
3383	* Assumes the caller knows what it's doing! (host must support these)
3384	*/
3385	case CPUMCPUIDFEATURE_PAE:
3386	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3387	if (pLeaf)
3388	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
3389
3390	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3391	if ( pLeaf
3392	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3393	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3394	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
3395
3396	pVM->cpum.s.GuestFeatures.fPae = 1;
3397	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
3398	break;
3399
3400	/*
3401	* Set the LONG MODE bit in the extended feature mask.
3402	* Assumes the caller knows what it's doing! (host must support these)
3403	*/
3404	case CPUMCPUIDFEATURE_LONG_MODE:
3405	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLongMode, "LONG MODE");
3406
3407	/* Valid for both Intel and AMD. */
3408	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
3409	pVM->cpum.s.GuestFeatures.fLongMode = 1;
3410	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
3411	if (pVM->cpum.s.GuestFeatures.fVmx)
3412	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3413	{
3414	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3415	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
3416	}
3417	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
3418	break;
3419
3420	/*
3421	* Set the NX/XD bit in the extended feature mask.
3422	* Assumes the caller knows what it's doing! (host must support these)
3423	*/
3424	case CPUMCPUIDFEATURE_NX:
3425	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fNoExecute, "NX/XD");
3426
3427	/* Valid for both Intel and AMD. */
3428	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
3429	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
3430	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
3431	break;
3432
3433
3434	/*
3435	* Set the LAHF/SAHF support in 64-bit mode.
3436	* Assumes the caller knows what it's doing! (host must support this)
3437	*/
3438	case CPUMCPUIDFEATURE_LAHF:
3439	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLahfSahf, "LAHF/SAHF");
3440
3441	/* Valid for both Intel and AMD. */
3442	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
3443	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
3444	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
3445	break;
3446
3447	/*
3448	* Set the RDTSCP support bit.
3449	* Assumes the caller knows what it's doing! (host must support this)
3450	*/
3451	case CPUMCPUIDFEATURE_RDTSCP:
3452	if (pVM->cpum.s.u8PortableCpuIdLevel > 0)
3453	return;
3454	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fRdTscP, "RDTSCP");
3455	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3456
3457	/* Valid for both Intel and AMD. */
3458	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
3459	pVM->cpum.s.HostFeatures.fRdTscP = 1;
3460	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
3461	break;
3462
3463	/*
3464	* Set the Hypervisor Present bit in the standard feature mask.
3465	*/
3466	case CPUMCPUIDFEATURE_HVP:
3467	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3468	if (pLeaf)
3469	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
3470	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
3471	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
3472	break;
3473
3474	/*
3475	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
3476	* on Intel CPUs, and different on AMDs.
3477	*/
3478	case CPUMCPUIDFEATURE_SPEC_CTRL:
3479	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3480	{
3481	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
3482	if ( !pLeaf
3483	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
3484	{
3485	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
3486	return;
3487	}
3488
3489	/* The feature can be enabled. Let's see what we can actually do. */
3490	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
3491
3492	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
3493	if (pVM->cpum.s.HostFeatures.fIbrs)
3494	{
3495	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
3496	pVM->cpum.s.GuestFeatures.fIbrs = 1;
3497	if (pVM->cpum.s.HostFeatures.fStibp)
3498	{
3499	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
3500	pVM->cpum.s.GuestFeatures.fStibp = 1;
3501	}
3502
3503	/* Make sure we have the speculation control MSR... */
3504	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
3505	if (!pMsrRange)
3506	{
3507	static CPUMMSRRANGE const s_SpecCtrl =
3508	{
3509	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
3510	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
3511	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3512	/.szName = / "IA32_SPEC_CTRL"
3513	};
3514	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3515	AssertLogRelRC(rc);
3516	}
3517
3518	/* ... and the predictor command MSR. */
3519	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
3520	if (!pMsrRange)
3521	{
3522	/** @todo incorrect fWrGpMask. */
3523	static CPUMMSRRANGE const s_SpecCtrl =
3524	{
3525	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
3526	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
3527	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3528	/.szName = / "IA32_PRED_CMD"
3529	};
3530	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3531	AssertLogRelRC(rc);
3532	}
3533
3534	}
3535
3536	if (pVM->cpum.s.HostFeatures.fArchCap)
3537	{
3538	/* Install the architectural capabilities MSR. */
3539	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
3540	if (!pMsrRange)
3541	{
3542	static CPUMMSRRANGE const s_ArchCaps =
3543	{
3544	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
3545	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
3546	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
3547	/.szName = / "IA32_ARCH_CAPABILITIES"
3548	};
3549	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
3550	AssertLogRelRC(rc);
3551	}
3552
3553	/* Advertise IBRS_ALL if present at this point... */
3554	if (pVM->cpum.s.HostFeatures.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
3555	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
3556	}
3557
3558	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
3559	}
3560	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3561	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3562	{
3563	/* The precise details of AMD's implementation are not yet clear. */
3564	}
3565	break;
3566
3567	default:
3568	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
3569	break;
3570	}
3571
3572	/** @todo can probably kill this as this API is now init time only... */
3573	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3574	{
3575	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3576	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
3577	}
3578
3579	#undef GET_8000_0001_CHECK_X86_HOST_FEATURE_RET
3580	#undef CHECK_X86_HOST_FEATURE_RET
3581	}
3582
3583
3584	/**
3585	* Queries a CPUID feature bit.
3586	*
3587	* @returns boolean for feature presence
3588	* @param pVM The cross context VM structure.
3589	* @param enmFeature The feature to query.
3590	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
3591	*/
3592	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3593	{
3594	switch (enmFeature)
3595	{
3596	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
3597	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
3598	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
3599	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
3600	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
3601	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
3602	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
3603	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
3604	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
3605	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
3606	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
3607	case CPUMCPUIDFEATURE_INVALID:
3608	case CPUMCPUIDFEATURE_32BIT_HACK:
3609	break;
3610	}
3611	AssertFailed();
3612	return false;
3613	}
3614
3615
3616	/**
3617	* Clears a CPUID feature bit.
3618	*
3619	* @param pVM The cross context VM structure.
3620	* @param enmFeature The feature to clear.
3621	*
3622	* @deprecated Probably better to default the feature to disabled and only allow
3623	* setting (enabling) it during construction.
3624	*/
3625	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3626	{
3627	PCPUMCPUIDLEAF pLeaf;
3628	switch (enmFeature)
3629	{
3630	case CPUMCPUIDFEATURE_APIC:
3631	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
3632	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3633	if (pLeaf)
3634	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
3635
3636	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3637	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3638	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
3639
3640	pVM->cpum.s.GuestFeatures.fApic = 0;
3641	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
3642	break;
3643
3644	case CPUMCPUIDFEATURE_X2APIC:
3645	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
3646	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3647	if (pLeaf)
3648	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
3649	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
3650	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
3651	break;
3652
3653	#if 0
3654	case CPUMCPUIDFEATURE_PAE:
3655	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3656	if (pLeaf)
3657	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
3658
3659	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3660	if ( pLeaf
3661	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3662	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3663	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
3664
3665	pVM->cpum.s.GuestFeatures.fPae = 0;
3666	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
3667	break;
3668
3669	case CPUMCPUIDFEATURE_LONG_MODE:
3670	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3671	if (pLeaf)
3672	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
3673	pVM->cpum.s.GuestFeatures.fLongMode = 0;
3674	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
3675	if (pVM->cpum.s.GuestFeatures.fVmx)
3676	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3677	{
3678	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3679	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
3680	}
3681	break;
3682
3683	case CPUMCPUIDFEATURE_LAHF:
3684	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3685	if (pLeaf)
3686	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
3687	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
3688	break;
3689	#endif
3690	case CPUMCPUIDFEATURE_RDTSCP:
3691	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3692	if (pLeaf)
3693	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
3694	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
3695	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
3696	break;
3697
3698	#if 0
3699	case CPUMCPUIDFEATURE_HVP:
3700	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3701	if (pLeaf)
3702	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
3703	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
3704	break;
3705
3706	case CPUMCPUIDFEATURE_SPEC_CTRL:
3707	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
3708	if (pLeaf)
3709	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
3710	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
3711	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
3712	break;
3713	#endif
3714	default:
3715	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
3716	break;
3717	}
3718
3719	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3720	{
3721	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3722	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
3723	}
3724	}
3725
3726
3727	/*
3728	*
3729	*
3730	* Saved state related code.
3731	* Saved state related code.
3732	* Saved state related code.
3733	*
3734	*
3735	*/
3736
3737	/**
3738	* Called both in pass 0 and the final pass.
3739	*
3740	* @param pVM The cross context VM structure.
3741	* @param pSSM The saved state handle.
3742	*/
3743	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
3744	{
3745	/*
3746	* Save all the CPU ID leaves.
3747	*/
3748	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
3749	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3750	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
3751	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
3752
3753	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
3754
3755	/*
3756	* Save a good portion of the raw CPU IDs as well as they may come in
3757	* handy when validating features for raw mode.
3758	*/
3759	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3760	CPUMCPUID aRawStd[16];
3761	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
3762	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3763	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
3764	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
3765
3766	CPUMCPUID aRawExt[32];
3767	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
3768	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
3769	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
3770	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
3771
3772	#else
3773	/* Two zero counts on non-x86 hosts. */
3774	SSMR3PutU32(pSSM, 0);
3775	SSMR3PutU32(pSSM, 0);
3776	#endif
3777	}
3778
3779
3780	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
3781	{
3782	uint32_t cCpuIds;
3783	int rc = SSMR3GetU32(pSSM, &cCpuIds);
3784	if (RT_SUCCESS(rc))
3785	{
3786	if (cCpuIds < 64)
3787	{
3788	for (uint32_t i = 0; i < cCpuIds; i++)
3789	{
3790	CPUMCPUID CpuId;
3791	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
3792	if (RT_FAILURE(rc))
3793	break;
3794
3795	CPUMCPUIDLEAF NewLeaf;
3796	NewLeaf.uLeaf = uBase + i;
3797	NewLeaf.uSubLeaf = 0;
3798	NewLeaf.fSubLeafMask = 0;
3799	NewLeaf.uEax = CpuId.uEax;
3800	NewLeaf.uEbx = CpuId.uEbx;
3801	NewLeaf.uEcx = CpuId.uEcx;
3802	NewLeaf.uEdx = CpuId.uEdx;
3803	NewLeaf.fFlags = 0;
3804	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
3805	}
3806	}
3807	else
3808	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3809	}
3810	if (RT_FAILURE(rc))
3811	{
3812	RTMemFree(*ppaLeaves);
3813	*ppaLeaves = NULL;
3814	*pcLeaves = 0;
3815	}
3816	return rc;
3817	}
3818
3819
3820	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
3821	{
3822	*ppaLeaves = NULL;
3823	*pcLeaves = 0;
3824
3825	int rc;
3826	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
3827	{
3828	/*
3829	* The new format. Starts by declaring the leave size and count.
3830	*/
3831	uint32_t cbLeaf;
3832	SSMR3GetU32(pSSM, &cbLeaf);
3833	uint32_t cLeaves;
3834	rc = SSMR3GetU32(pSSM, &cLeaves);
3835	if (RT_SUCCESS(rc))
3836	{
3837	if (cbLeaf == sizeof(**ppaLeaves))
3838	{
3839	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
3840	{
3841	/*
3842	* Load the leaves one by one.
3843	*
3844	* The uPrev stuff is a kludge for working around a week worth of bad saved
3845	* states during the CPUID revamp in March 2015. We saved too many leaves
3846	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
3847	* garbage entires at the end of the array when restoring. We also had
3848	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
3849	* this kludge doesn't deal correctly with that, but who cares...
3850	*/
3851	uint32_t uPrev = 0;
3852	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
3853	{
3854	CPUMCPUIDLEAF Leaf;
3855	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
3856	if (RT_SUCCESS(rc))
3857	{
3858	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
3859	\|\| Leaf.uLeaf >= uPrev)
3860	{
3861	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3862	uPrev = Leaf.uLeaf;
3863	}
3864	else
3865	uPrev = UINT32_MAX;
3866	}
3867	}
3868	}
3869	else
3870	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
3871	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
3872	}
3873	else
3874	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
3875	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
3876	}
3877	}
3878	else
3879	{
3880	/*
3881	* The old format with its three inflexible arrays.
3882	*/
3883	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
3884	if (RT_SUCCESS(rc))
3885	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
3886	if (RT_SUCCESS(rc))
3887	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
3888	if (RT_SUCCESS(rc))
3889	{
3890	/*
3891	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
3892	*/
3893	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(ppaLeaves, pcLeaves, 0, 0);
3894	if ( pLeaf
3895	&& RTX86IsIntelCpu(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
3896	{
3897	CPUMCPUIDLEAF Leaf;
3898	Leaf.uLeaf = 4;
3899	Leaf.fSubLeafMask = UINT32_MAX;
3900	Leaf.uSubLeaf = 0;
3901	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
3902	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
3903	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
3904	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
3905	\| UINT32_C(63); /* system coherency line size - 1 */
3906	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
3907	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
3908	\| (UINT32_C(1) << 5) /* cache level */
3909	\| UINT32_C(1); /* cache type (data) */
3910	Leaf.fFlags = 0;
3911	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3912	if (RT_SUCCESS(rc))
3913	{
3914	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
3915	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3916	}
3917	if (RT_SUCCESS(rc))
3918	{
3919	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
3920	Leaf.uEcx = 4095; /* sets - 1 */
3921	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
3922	Leaf.uEbx \|= UINT32_C(23) << 22;
3923	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
3924	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
3925	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
3926	Leaf.uEax \|= UINT32_C(2) << 5;
3927	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
3928	}
3929	}
3930	}
3931	}
3932	return rc;
3933	}
3934
3935
3936	/**
3937	* Loads the CPU ID leaves saved by pass 0, inner worker.
3938	*
3939	* @returns VBox status code.
3940	* @param pVM The cross context VM structure.
3941	* @param pSSM The saved state handle.
3942	* @param uVersion The format version.
3943	* @param paLeaves Guest CPUID leaves loaded from the state.
3944	* @param cLeaves The number of leaves in @a paLeaves.
3945	* @param pMsrs The guest MSRs.
3946	*/
3947	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
3948	{
3949	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
3950	#if !defined(RT_ARCH_AMD64) && !defined(RT_ARCH_X86)
3951	AssertMsgFailed(("Port me!"));
3952	#endif
3953
3954	/*
3955	* Continue loading the state into stack buffers.
3956	*/
3957	CPUMCPUID GuestDefCpuId;
3958	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
3959	AssertRCReturn(rc, rc);
3960
3961	CPUMCPUID aRawStd[16];
3962	uint32_t cRawStd;
3963	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
3964	if (cRawStd > RT_ELEMENTS(aRawStd))
3965	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3966	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
3967	AssertRCReturn(rc, rc);
3968	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
3969	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3970	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
3971	#else
3972	RT_ZERO(aRawStd[i]);
3973	#endif
3974
3975	CPUMCPUID aRawExt[32];
3976	uint32_t cRawExt;
3977	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
3978	if (cRawExt > RT_ELEMENTS(aRawExt))
3979	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3980	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
3981	AssertRCReturn(rc, rc);
3982	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
3983	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3984	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
3985	#else
3986	RT_ZERO(aRawExt[i]);
3987	#endif
3988
3989	/*
3990	* Get the raw CPU IDs for the current host.
3991	*/
3992	CPUMCPUID aHostRawStd[16];
3993	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3994	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
3995	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
3996	#else
3997	RT_ZERO(aHostRawStd);
3998	#endif
3999
4000	CPUMCPUID aHostRawExt[32];
4001	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4002	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4003	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4004	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4005	#else
4006	RT_ZERO(aHostRawExt);
4007	#endif
4008
4009	/*
4010	* Get the host and guest overrides so we don't reject the state because
4011	* some feature was enabled thru these interfaces.
4012	* Note! We currently only need the feature leaves, so skip rest.
4013	*/
4014	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4015	CPUMCPUID aHostOverrideStd[2];
4016	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4017	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4018
4019	CPUMCPUID aHostOverrideExt[2];
4020	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4021	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4022
4023	/*
4024	* This can be skipped.
4025	*/
4026	bool fStrictCpuIdChecks;
4027	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4028
4029	/*
4030	* Define a bunch of macros for simplifying the santizing/checking code below.
4031	*/
4032	/* Generic expression + failure message. */
4033	#define CPUID_CHECK_RET(expr, fmt) \
4034	do { \
4035	if (!(expr)) \
4036	{ \
4037	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4038	if (fStrictCpuIdChecks) \
4039	{ \
4040	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4041	RTStrFree(pszMsg); \
4042	return rcCpuid; \
4043	} \
4044	LogRel(("CPUM: %s\n", pszMsg)); \
4045	RTStrFree(pszMsg); \
4046	} \
4047	} while (0)
4048	#define CPUID_CHECK_WRN(expr, fmt) \
4049	do { \
4050	if (!(expr)) \
4051	LogRel(fmt); \
4052	} while (0)
4053
4054	/* For comparing two values and bitch if they differs. */
4055	#define CPUID_CHECK2_RET(what, host, saved) \
4056	do { \
4057	if ((host) != (saved)) \
4058	{ \
4059	if (fStrictCpuIdChecks) \
4060	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4061	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4062	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4063	} \
4064	} while (0)
4065	#define CPUID_CHECK2_WRN(what, host, saved) \
4066	do { \
4067	if ((host) != (saved)) \
4068	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4069	} while (0)
4070
4071	/* For checking raw cpu features (raw mode). */
4072	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4073	do { \
4074	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4075	{ \
4076	if (fStrictCpuIdChecks) \
4077	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4078	N_(#bit " mismatch: host=%d saved=%d"), \
4079	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4080	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4081	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4082	} \
4083	} while (0)
4084	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4085	do { \
4086	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4087	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4088	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4089	} while (0)
4090	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4091
4092	/* For checking guest features. */
4093	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4094	do { \
4095	if ( (aGuestCpuId##set [1].reg & bit) \
4096	&& !(aHostRaw##set [1].reg & bit) \
4097	&& !(aHostOverride##set [1].reg & bit) \
4098	) \
4099	{ \
4100	if (fStrictCpuIdChecks) \
4101	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4102	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4103	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4104	} \
4105	} while (0)
4106	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4107	do { \
4108	if ( (aGuestCpuId##set [1].reg & bit) \
4109	&& !(aHostRaw##set [1].reg & bit) \
4110	&& !(aHostOverride##set [1].reg & bit) \
4111	) \
4112	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4113	} while (0)
4114	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4115	do { \
4116	if ( (aGuestCpuId##set [1].reg & bit) \
4117	&& !(aHostRaw##set [1].reg & bit) \
4118	&& !(aHostOverride##set [1].reg & bit) \
4119	) \
4120	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4121	} while (0)
4122	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4123
4124	/* For checking guest features if AMD guest CPU. */
4125	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4126	do { \
4127	if ( (aGuestCpuId##set [1].reg & bit) \
4128	&& fGuestAmd \
4129	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4130	&& !(aHostOverride##set [1].reg & bit) \
4131	) \
4132	{ \
4133	if (fStrictCpuIdChecks) \
4134	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4135	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4136	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4137	} \
4138	} while (0)
4139	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4140	do { \
4141	if ( (aGuestCpuId##set [1].reg & bit) \
4142	&& fGuestAmd \
4143	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4144	&& !(aHostOverride##set [1].reg & bit) \
4145	) \
4146	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4147	} while (0)
4148	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4149	do { \
4150	if ( (aGuestCpuId##set [1].reg & bit) \
4151	&& fGuestAmd \
4152	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4153	&& !(aHostOverride##set [1].reg & bit) \
4154	) \
4155	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4156	} while (0)
4157	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4158
4159	/* For checking AMD features which have a corresponding bit in the standard
4160	range. (Intel defines very few bits in the extended feature sets.) */
4161	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4162	do { \
4163	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4164	&& !(fHostAmd \
4165	? aHostRawExt[1].reg & (ExtBit) \
4166	: aHostRawStd[1].reg & (StdBit)) \
4167	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4168	) \
4169	{ \
4170	if (fStrictCpuIdChecks) \
4171	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4172	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4173	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4174	} \
4175	} while (0)
4176	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4177	do { \
4178	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4179	&& !(fHostAmd \
4180	? aHostRawExt[1].reg & (ExtBit) \
4181	: aHostRawStd[1].reg & (StdBit)) \
4182	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4183	) \
4184	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4185	} while (0)
4186	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4187	do { \
4188	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4189	&& !(fHostAmd \
4190	? aHostRawExt[1].reg & (ExtBit) \
4191	: aHostRawStd[1].reg & (StdBit)) \
4192	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4193	) \
4194	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4195	} while (0)
4196	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4197
4198
4199	/*
4200	* Verify that we can support the features already exposed to the guest on
4201	* this host.
4202	*
4203	* Most of the features we're emulating requires intercepting instruction
4204	* and doing it the slow way, so there is no need to warn when they aren't
4205	* present in the host CPU. Thus we use IGN instead of EMU on these.
4206	*
4207	* Trailing comments:
4208	* "EMU" - Possible to emulate, could be lots of work and very slow.
4209	* "EMU?" - Can this be emulated?
4210	*/
4211	CPUMCPUID aGuestCpuIdStd[2];
4212	RT_ZERO(aGuestCpuIdStd);
4213	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4214
4215	/* CPUID(1).ecx */
4216	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4217	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4218	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4219	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4220	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4221	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4222	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4223	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4224	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4225	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4226	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4227	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4228	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4229	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4230	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4231	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4232	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4233	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4234	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4235	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4236	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4237	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4238	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4239	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4240	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4241	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4242	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4243	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4244	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4245	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4246	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4247	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4248
4249	/* CPUID(1).edx */
4250	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4251	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4252	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4253	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4254	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4255	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4256	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4257	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4258	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4259	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4260	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4261	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4262	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4263	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4264	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4265	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4266	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4267	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4268	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4269	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4270	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4271	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4272	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4273	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4274	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4275	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4276	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4277	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4278	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4279	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4280	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4281	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4282
4283	/* CPUID(0x80000000). */
4284	CPUMCPUID aGuestCpuIdExt[2];
4285	RT_ZERO(aGuestCpuIdExt);
4286	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4287	{
4288	/** @todo deal with no 0x80000001 on the host. */
4289	bool const fHostAmd = RTX86IsAmdCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
4290	\|\| RTX86IsHygonCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4291	bool const fGuestAmd = RTX86IsAmdCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
4292	\|\| RTX86IsHygonCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4293
4294	/* CPUID(0x80000001).ecx */
4295	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4296	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4297	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4298	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4299	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4300	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4301	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4302	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4303	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4304	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4305	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4306	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4307	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4308	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4309	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4310	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4311	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4312	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4313	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4314	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4315	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4316	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4317	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4318	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4319	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4320	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4321	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4322	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4323	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4324	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4325	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4326	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4327
4328	/* CPUID(0x80000001).edx */
4329	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4330	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4331	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4332	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4333	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4334	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4335	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4336	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4337	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4338	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4339	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4340	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4341	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4342	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4343	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4344	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4345	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4346	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4347	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4348	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4349	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4350	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4351	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4352	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4353	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4354	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4355	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4356	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4357	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4358	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4359	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4360	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4361	}
4362
4363	/** @todo check leaf 7 */
4364
4365	/* CPUID(d) - XCR0 stuff - takes ECX as input.
4366	* ECX=0: EAX - Valid bits in XCR0[31:0].
4367	* EBX - Maximum state size as per current XCR0 value.
4368	* ECX - Maximum state size for all supported features.
4369	* EDX - Valid bits in XCR0[63:32].
4370	* ECX=1: EAX - Various X-features.
4371	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
4372	* ECX - Valid bits in IA32_XSS[31:0].
4373	* EDX - Valid bits in IA32_XSS[63:32].
4374	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4375	* if the bit invalid all four registers are set to zero.
4376	* EAX - The state size for this feature.
4377	* EBX - The state byte offset of this feature.
4378	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4379	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
4380	*/
4381	uint64_t fGuestXcr0Mask = 0;
4382	PCPUMCPUIDLEAF pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4383	if ( pCurLeaf
4384	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4385	&& ( pCurLeaf->uEax
4386	\|\| pCurLeaf->uEbx
4387	\|\| pCurLeaf->uEcx
4388	\|\| pCurLeaf->uEdx) )
4389	{
4390	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4391	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4392	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4393	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4394	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4395	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
4396	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4397	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
4398
4399	/* We don't support any additional features yet. */
4400	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4401	if (pCurLeaf && pCurLeaf->uEax)
4402	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4403	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4404	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
4405	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4406	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4407	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4408
4409
4410	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4411	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4412	{
4413	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4414	if (pCurLeaf)
4415	{
4416	/* If advertised, the state component offset and size must match the one used by host. */
4417	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
4418	{
4419	CPUMCPUID RawHost;
4420	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
4421	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4422	if ( RawHost.uEbx != pCurLeaf->uEbx
4423	\|\| RawHost.uEax != pCurLeaf->uEax)
4424	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4425	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
4426	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
4427	}
4428	}
4429	}
4430	#endif
4431	}
4432	/* Clear leaf 0xd just in case we're loading an old state... */
4433	else if (pCurLeaf)
4434	{
4435	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
4436	{
4437	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4438	if (pCurLeaf)
4439	{
4440	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
4441	\|\| ( pCurLeaf->uEax == 0
4442	&& pCurLeaf->uEbx == 0
4443	&& pCurLeaf->uEcx == 0
4444	&& pCurLeaf->uEdx == 0),
4445	("uVersion=%#x; %#x %#x %#x %#x\n",
4446	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
4447	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
4448	}
4449	}
4450	}
4451
4452	/* Update the fXStateGuestMask value for the VM. */
4453	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
4454	{
4455	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
4456	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
4457	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
4458	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4459	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
4460	}
4461
4462	#undef CPUID_CHECK_RET
4463	#undef CPUID_CHECK_WRN
4464	#undef CPUID_CHECK2_RET
4465	#undef CPUID_CHECK2_WRN
4466	#undef CPUID_RAW_FEATURE_RET
4467	#undef CPUID_RAW_FEATURE_WRN
4468	#undef CPUID_RAW_FEATURE_IGN
4469	#undef CPUID_GST_FEATURE_RET
4470	#undef CPUID_GST_FEATURE_WRN
4471	#undef CPUID_GST_FEATURE_EMU
4472	#undef CPUID_GST_FEATURE_IGN
4473	#undef CPUID_GST_FEATURE2_RET
4474	#undef CPUID_GST_FEATURE2_WRN
4475	#undef CPUID_GST_FEATURE2_EMU
4476	#undef CPUID_GST_FEATURE2_IGN
4477	#undef CPUID_GST_AMD_FEATURE_RET
4478	#undef CPUID_GST_AMD_FEATURE_WRN
4479	#undef CPUID_GST_AMD_FEATURE_EMU
4480	#undef CPUID_GST_AMD_FEATURE_IGN
4481
4482	/*
4483	* We're good, commit the CPU ID leaves.
4484	*/
4485	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
4486	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
4487	AssertLogRelRCReturn(rc, rc);
4488
4489	return VINF_SUCCESS;
4490	}
4491
4492
4493	/**
4494	* Loads the CPU ID leaves saved by pass 0.
4495	*
4496	* @returns VBox status code.
4497	* @param pVM The cross context VM structure.
4498	* @param pSSM The saved state handle.
4499	* @param uVersion The format version.
4500	* @param pMsrs The guest MSRs.
4501	*/
4502	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
4503	{
4504	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4505
4506	/*
4507	* Load the CPUID leaves array first and call worker to do the rest, just so
4508	* we can free the memory when we need to without ending up in column 1000.
4509	*/
4510	PCPUMCPUIDLEAF paLeaves;
4511	uint32_t cLeaves;
4512	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
4513	AssertRC(rc);
4514	if (RT_SUCCESS(rc))
4515	{
4516	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
4517	RTMemFree(paLeaves);
4518	}
4519	return rc;
4520	}
4521
4522
4523
4524	/**
4525	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
4526	*
4527	* @returns VBox status code.
4528	* @param pVM The cross context VM structure.
4529	* @param pSSM The saved state handle.
4530	* @param uVersion The format version.
4531	*/
4532	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
4533	{
4534	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4535
4536	/*
4537	* Restore the CPUID leaves.
4538	*
4539	* Note that we support restoring less than the current amount of standard
4540	* leaves because we've been allowed more is newer version of VBox.
4541	*/
4542	uint32_t cElements;
4543	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4544	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
4545	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4546	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
4547
4548	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4549	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
4550	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4551	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
4552
4553	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4554	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
4555	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4556	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
4557
4558	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4559
4560	/*
4561	* Check that the basic cpuid id information is unchanged.
4562	*/
4563	/** @todo we should check the 64 bits capabilities too! */
4564	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
4565	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4566	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
4567	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
4568	#endif
4569	uint32_t au32CpuIdSaved[8];
4570	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
4571	if (RT_SUCCESS(rc))
4572	{
4573	/* Ignore CPU stepping. */
4574	au32CpuId[4] &= 0xfffffff0;
4575	au32CpuIdSaved[4] &= 0xfffffff0;
4576
4577	/* Ignore APIC ID (AMD specs). */
4578	au32CpuId[5] &= ~0xff000000;
4579	au32CpuIdSaved[5] &= ~0xff000000;
4580
4581	/* Ignore the number of Logical CPUs (AMD specs). */
4582	au32CpuId[5] &= ~0x00ff0000;
4583	au32CpuIdSaved[5] &= ~0x00ff0000;
4584
4585	/* Ignore some advanced capability bits, that we don't expose to the guest. */
4586	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
4587	\| X86_CPUID_FEATURE_ECX_VMX
4588	\| X86_CPUID_FEATURE_ECX_SMX
4589	\| X86_CPUID_FEATURE_ECX_EST
4590	\| X86_CPUID_FEATURE_ECX_TM2
4591	\| X86_CPUID_FEATURE_ECX_CNTXID
4592	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4593	\| X86_CPUID_FEATURE_ECX_PDCM
4594	\| X86_CPUID_FEATURE_ECX_DCA
4595	\| X86_CPUID_FEATURE_ECX_X2APIC
4596	);
4597	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
4598	\| X86_CPUID_FEATURE_ECX_VMX
4599	\| X86_CPUID_FEATURE_ECX_SMX
4600	\| X86_CPUID_FEATURE_ECX_EST
4601	\| X86_CPUID_FEATURE_ECX_TM2
4602	\| X86_CPUID_FEATURE_ECX_CNTXID
4603	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4604	\| X86_CPUID_FEATURE_ECX_PDCM
4605	\| X86_CPUID_FEATURE_ECX_DCA
4606	\| X86_CPUID_FEATURE_ECX_X2APIC
4607	);
4608
4609	/* Make sure we don't forget to update the masks when enabling
4610	* features in the future.
4611	*/
4612	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
4613	( X86_CPUID_FEATURE_ECX_DTES64
4614	\| X86_CPUID_FEATURE_ECX_VMX
4615	\| X86_CPUID_FEATURE_ECX_SMX
4616	\| X86_CPUID_FEATURE_ECX_EST
4617	\| X86_CPUID_FEATURE_ECX_TM2
4618	\| X86_CPUID_FEATURE_ECX_CNTXID
4619	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4620	\| X86_CPUID_FEATURE_ECX_PDCM
4621	\| X86_CPUID_FEATURE_ECX_DCA
4622	\| X86_CPUID_FEATURE_ECX_X2APIC
4623	)));
4624	/* do the compare */
4625	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
4626	{
4627	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
4628	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
4629	"Saved=%.*Rhxs\n"
4630	"Real =%.*Rhxs\n",
4631	sizeof(au32CpuIdSaved), au32CpuIdSaved,
4632	sizeof(au32CpuId), au32CpuId));
4633	else
4634	{
4635	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
4636	"Saved=%.*Rhxs\n"
4637	"Real =%.*Rhxs\n",
4638	sizeof(au32CpuIdSaved), au32CpuIdSaved,
4639	sizeof(au32CpuId), au32CpuId));
4640	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
4641	}
4642	}
4643	}
4644
4645	return rc;
4646	}
4647
4648
4649
4650	/*
4651	*
4652	*
4653	* CPUID Info Handler.
4654	* CPUID Info Handler.
4655	* CPUID Info Handler.
4656	*
4657	*
4658	*/
4659
4660
4661
4662	/**
4663	* Get L1 cache / TLS associativity.
4664	*/
4665	static const char getCacheAss(unsigned u, char pszBuf)
4666	{
4667	if (u == 0)
4668	return "res0 ";
4669	if (u == 1)
4670	return "direct";
4671	if (u == 255)
4672	return "fully";
4673	if (u >= 256)
4674	return "???";
4675
4676	RTStrPrintf(pszBuf, 16, "%d way", u);
4677	return pszBuf;
4678	}
4679
4680
4681	/**
4682	* Get L2 cache associativity.
4683	*/
4684	const char *getL2CacheAss(unsigned u)
4685	{
4686	switch (u)
4687	{
4688	case 0: return "off ";
4689	case 1: return "direct";
4690	case 2: return "2 way ";
4691	case 3: return "res3 ";
4692	case 4: return "4 way ";
4693	case 5: return "res5 ";
4694	case 6: return "8 way ";
4695	case 7: return "res7 ";
4696	case 8: return "16 way";
4697	case 9: return "res9 ";
4698	case 10: return "res10 ";
4699	case 11: return "res11 ";
4700	case 12: return "res12 ";
4701	case 13: return "res13 ";
4702	case 14: return "res14 ";
4703	case 15: return "fully ";
4704	default: return "????";
4705	}
4706	}
4707
4708
4709	/** CPUID(1).EDX field descriptions. */
4710	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
4711	{
4712	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
4713	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
4714	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
4715	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
4716	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
4717	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
4718	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
4719	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
4720	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
4721	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
4722	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
4723	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
4724	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
4725	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
4726	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
4727	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
4728	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
4729	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
4730	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
4731	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
4732	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
4733	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
4734	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
4735	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
4736	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
4737	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
4738	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
4739	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
4740	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
4741	DBGFREGSUBFIELD_TERMINATOR()
4742	};
4743
4744	/** CPUID(1).ECX field descriptions. */
4745	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
4746	{
4747	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
4748	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
4749	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
4750	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
4751	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
4752	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
4753	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
4754	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
4755	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
4756	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
4757	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
4758	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
4759	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
4760	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
4761	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
4762	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
4763	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
4764	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
4765	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
4766	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
4767	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
4768	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
4769	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
4770	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
4771	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
4772	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
4773	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
4774	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
4775	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
4776	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
4777	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
4778	DBGFREGSUBFIELD_TERMINATOR()
4779	};
4780
4781	/** CPUID(7,0).EBX field descriptions. */
4782	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
4783	{
4784	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
4785	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
4786	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
4787	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
4788	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
4789	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
4790	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
4791	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
4792	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
4793	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
4794	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
4795	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
4796	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
4797	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
4798	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
4799	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
4800	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
4801	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
4802	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
4803	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
4804	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
4805	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
4806	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
4807	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
4808	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
4809	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
4810	DBGFREGSUBFIELD_TERMINATOR()
4811	};
4812
4813	/** CPUID(7,0).ECX field descriptions. */
4814	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
4815	{
4816	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
4817	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
4818	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
4819	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
4820	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
4821	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
4822	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
4823	DBGFREGSUBFIELD_TERMINATOR()
4824	};
4825
4826	/** CPUID(7,0).EDX field descriptions. */
4827	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
4828	{
4829	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
4830	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
4831	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
4832	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
4833	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
4834	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
4835	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
4836	DBGFREGSUBFIELD_TERMINATOR()
4837	};
4838
4839
4840	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
4841	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
4842	{
4843	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
4844	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
4845	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
4846	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
4847	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
4848	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
4849	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
4850	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
4851	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
4852	DBGFREGSUBFIELD_TERMINATOR()
4853	};
4854
4855	/** CPUID(13,1).EAX field descriptions. */
4856	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
4857	{
4858	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
4859	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
4860	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
4861	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
4862	DBGFREGSUBFIELD_TERMINATOR()
4863	};
4864
4865
4866	/** CPUID(0x80000001,0).EDX field descriptions. */
4867	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
4868	{
4869	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
4870	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
4871	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
4872	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
4873	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
4874	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
4875	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
4876	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
4877	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
4878	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
4879	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
4880	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
4881	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
4882	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
4883	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
4884	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
4885	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
4886	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
4887	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
4888	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
4889	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
4890	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
4891	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
4892	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
4893	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
4894	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
4895	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
4896	DBGFREGSUBFIELD_TERMINATOR()
4897	};
4898
4899	/** CPUID(0x80000001,0).ECX field descriptions. */
4900	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
4901	{
4902	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
4903	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
4904	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
4905	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
4906	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
4907	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
4908	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
4909	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
4910	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
4911	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
4912	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
4913	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
4914	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
4915	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
4916	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
4917	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
4918	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
4919	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
4920	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
4921	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
4922	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
4923	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
4924	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
4925	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
4926	DBGFREGSUBFIELD_RO("MWAITX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
4927	DBGFREGSUBFIELD_TERMINATOR()
4928	};
4929
4930	/** CPUID(0x8000000a,0).EDX field descriptions. */
4931	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
4932	{
4933	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
4934	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
4935	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
4936	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
4937	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
4938	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
4939	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
4940	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
4941	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
4942	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
4943	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
4944	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
4945	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
4946	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
4947	DBGFREGSUBFIELD_TERMINATOR()
4948	};
4949
4950
4951	/** CPUID(0x80000007,0).EDX field descriptions. */
4952	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
4953	{
4954	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
4955	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
4956	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
4957	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
4958	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
4959	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
4960	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
4961	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
4962	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
4963	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
4964	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
4965	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
4966	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
4967	DBGFREGSUBFIELD_TERMINATOR()
4968	};
4969
4970	/** CPUID(0x80000008,0).EBX field descriptions. */
4971	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
4972	{
4973	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
4974	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
4975	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
4976	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
4977	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
4978	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
4979	DBGFREGSUBFIELD_TERMINATOR()
4980	};
4981
4982
4983	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
4984	const char *pszLeadIn, uint32_t cchWidth)
4985	{
4986	if (pszLeadIn)
4987	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
4988
4989	for (uint32_t iBit = 0; iBit < 32; iBit++)
4990	if (RT_BIT_32(iBit) & uVal)
4991	{
4992	while ( pDesc->pszName != NULL
4993	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
4994	pDesc++;
4995	if ( pDesc->pszName != NULL
4996	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
4997	{
4998	if (pDesc->cBits == 1)
4999	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5000	else
5001	{
5002	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5003	if (pDesc->cBits < 32)
5004	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5005	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5006	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5007	}
5008	}
5009	else
5010	pHlp->pfnPrintf(pHlp, " %u", iBit);
5011	}
5012	if (pszLeadIn)
5013	pHlp->pfnPrintf(pHlp, "\n");
5014	}
5015
5016
5017	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5018	const char *pszLeadIn, uint32_t cchWidth)
5019	{
5020	if (pszLeadIn)
5021	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5022
5023	for (uint32_t iBit = 0; iBit < 64; iBit++)
5024	if (RT_BIT_64(iBit) & uVal)
5025	{
5026	while ( pDesc->pszName != NULL
5027	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5028	pDesc++;
5029	if ( pDesc->pszName != NULL
5030	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5031	{
5032	if (pDesc->cBits == 1)
5033	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5034	else
5035	{
5036	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5037	if (pDesc->cBits < 64)
5038	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5039	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5040	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5041	}
5042	}
5043	else
5044	pHlp->pfnPrintf(pHlp, " %u", iBit);
5045	}
5046	if (pszLeadIn)
5047	pHlp->pfnPrintf(pHlp, "\n");
5048	}
5049
5050
5051	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5052	const char *pszLeadIn, uint32_t cchWidth)
5053	{
5054	if (!uVal)
5055	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5056	else
5057	{
5058	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5059	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5060	pHlp->pfnPrintf(pHlp, " )\n");
5061	}
5062	}
5063
5064
5065	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5066	uint32_t cchWidth)
5067	{
5068	uint32_t uCombined = uVal1 \| uVal2;
5069	for (uint32_t iBit = 0; iBit < 32; iBit++)
5070	if ( (RT_BIT_32(iBit) & uCombined)
5071	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5072	{
5073	while ( pDesc->pszName != NULL
5074	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5075	pDesc++;
5076
5077	if ( pDesc->pszName != NULL
5078	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5079	{
5080	size_t cchMnemonic = strlen(pDesc->pszName);
5081	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5082	size_t cchDesc = strlen(pszDesc);
5083	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5084	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5085	if (pDesc->cBits < 32)
5086	{
5087	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5088	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5089	}
5090
5091	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
5092	pDesc->pszName, pszDesc,
5093	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5094	uFieldValue1, uFieldValue2);
5095
5096	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5097	pDesc++;
5098	}
5099	else
5100	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5101	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5102	}
5103	}
5104
5105
5106	/**
5107	* Produces a detailed summary of standard leaf 0x00000001.
5108	*
5109	* @param pHlp The info helper functions.
5110	* @param pCurLeaf The 0x00000001 leaf.
5111	* @param fVerbose Whether to be very verbose or not.
5112	* @param fIntel Set if intel CPU.
5113	*/
5114	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5115	{
5116	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5117	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5118	uint32_t uEAX = pCurLeaf->uEax;
5119	uint32_t uEBX = pCurLeaf->uEbx;
5120
5121	pHlp->pfnPrintf(pHlp,
5122	"%36s %2d \tExtended: %d \tEffective: %d\n"
5123	"%36s %2d \tExtended: %d \tEffective: %d\n"
5124	"%36s %d\n"
5125	"%36s %d (%s)\n"
5126	"%36s %#04x\n"
5127	"%36s %d\n"
5128	"%36s %d\n"
5129	"%36s %#04x\n"
5130	,
5131	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
5132	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
5133	"Stepping:", RTX86GetCpuStepping(uEAX),
5134	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5135	"APIC ID:", (uEBX >> 24) & 0xff,
5136	"Logical CPUs:",(uEBX >> 16) & 0xff,
5137	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
5138	"Brand ID:", (uEBX >> 0) & 0xff);
5139	if (fVerbose)
5140	{
5141	CPUMCPUID Host = {0};
5142	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5143	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5144	#endif
5145	pHlp->pfnPrintf(pHlp, "Features\n");
5146	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5147	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5148	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5149	}
5150	else
5151	{
5152	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5153	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5154	}
5155	}
5156
5157
5158	/**
5159	* Produces a detailed summary of standard leaf 0x00000007.
5160	*
5161	* @param pHlp The info helper functions.
5162	* @param paLeaves The CPUID leaves array.
5163	* @param cLeaves The number of leaves in the array.
5164	* @param pCurLeaf The first 0x00000007 leaf.
5165	* @param fVerbose Whether to be very verbose or not.
5166	*/
5167	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5168	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5169	{
5170	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5171	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5172	for (;;)
5173	{
5174	CPUMCPUID Host = {0};
5175	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5176	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5177	#endif
5178
5179	switch (pCurLeaf->uSubLeaf)
5180	{
5181	case 0:
5182	if (fVerbose)
5183	{
5184	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5185	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5186	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5187	if (pCurLeaf->uEdx \|\| Host.uEdx)
5188	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
5189	}
5190	else
5191	{
5192	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5193	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5194	if (pCurLeaf->uEdx)
5195	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
5196	}
5197	break;
5198
5199	default:
5200	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
5201	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5202	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5203	break;
5204
5205	}
5206
5207	/* advance. */
5208	pCurLeaf++;
5209	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5210	\|\| pCurLeaf->uLeaf != 0x7)
5211	break;
5212	}
5213	}
5214
5215
5216	/**
5217	* Produces a detailed summary of standard leaf 0x0000000d.
5218	*
5219	* @param pHlp The info helper functions.
5220	* @param paLeaves The CPUID leaves array.
5221	* @param cLeaves The number of leaves in the array.
5222	* @param pCurLeaf The first 0x00000007 leaf.
5223	* @param fVerbose Whether to be very verbose or not.
5224	*/
5225	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5226	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5227	{
5228	RT_NOREF_PV(fVerbose);
5229	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5230	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5231	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5232	{
5233	CPUMCPUID Host = {0};
5234	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5235	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5236	#endif
5237
5238	switch (uSubLeaf)
5239	{
5240	case 0:
5241	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5242	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5243	pCurLeaf->uEbx, pCurLeaf->uEcx);
5244	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5245
5246	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5247	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5248	"Valid XCR0 bits, guest:", 42);
5249	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5250	"Valid XCR0 bits, host:", 42);
5251	break;
5252
5253	case 1:
5254	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5255	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5256	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5257
5258	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5259	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
5260	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
5261
5262	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5263	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5264	" Valid IA32_XSS bits, guest:", 42);
5265	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5266	" Valid IA32_XSS bits, host:", 42);
5267	break;
5268
5269	default:
5270	if ( pCurLeaf
5271	&& pCurLeaf->uSubLeaf == uSubLeaf
5272	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
5273	{
5274	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5275	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5276	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5277	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5278	if (pCurLeaf->uEdx)
5279	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5280	pHlp->pfnPrintf(pHlp, " --");
5281	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5282	pHlp->pfnPrintf(pHlp, "\n");
5283	}
5284	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
5285	{
5286	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5287	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5288	if (Host.uEcx & ~RT_BIT_32(0))
5289	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5290	if (Host.uEdx)
5291	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5292	pHlp->pfnPrintf(pHlp, " --");
5293	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5294	pHlp->pfnPrintf(pHlp, "\n");
5295	}
5296	break;
5297
5298	}
5299
5300	/* advance. */
5301	if (pCurLeaf)
5302	{
5303	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5304	&& pCurLeaf->uSubLeaf <= uSubLeaf
5305	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5306	pCurLeaf++;
5307	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5308	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5309	pCurLeaf = NULL;
5310	}
5311	}
5312	}
5313
5314
5315	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5316	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5317	{
5318	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5319	&& pCurLeaf->uLeaf <= uUpToLeaf)
5320	{
5321	pHlp->pfnPrintf(pHlp,
5322	" %s\n"
5323	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5324	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5325	&& pCurLeaf->uLeaf <= uUpToLeaf)
5326	{
5327	CPUMCPUID Host = {0};
5328	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5329	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5330	#endif
5331	pHlp->pfnPrintf(pHlp,
5332	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5333	"Hst: %08x %08x %08x %08x\n",
5334	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5335	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5336	pCurLeaf++;
5337	}
5338	}
5339
5340	return pCurLeaf;
5341	}
5342
5343
5344	/**
5345	* Display the guest CpuId leaves.
5346	*
5347	* @param pVM The cross context VM structure.
5348	* @param pHlp The info helper functions.
5349	* @param pszArgs "terse", "default" or "verbose".
5350	*/
5351	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5352	{
5353	/*
5354	* Parse the argument.
5355	*/
5356	unsigned iVerbosity = 1;
5357	if (pszArgs)
5358	{
5359	pszArgs = RTStrStripL(pszArgs);
5360	if (!strcmp(pszArgs, "terse"))
5361	iVerbosity--;
5362	else if (!strcmp(pszArgs, "verbose"))
5363	iVerbosity++;
5364	}
5365
5366	uint32_t uLeaf;
5367	CPUMCPUID Host = {0};
5368	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5369	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5370	PCCPUMCPUIDLEAF pCurLeaf;
5371	PCCPUMCPUIDLEAF pNextLeaf;
5372	bool const fIntel = RTX86IsIntelCpu(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5373	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5374	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5375
5376	/*
5377	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5378	*/
5379	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5380	uint32_t cHstMax = ASMCpuId_EAX(0);
5381	#else
5382	uint32_t cHstMax = 0;
5383	#endif
5384	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5385	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5386	pHlp->pfnPrintf(pHlp,
5387	" Raw Standard CPUID Leaves\n"
5388	" Leaf/sub-leaf eax ebx ecx edx\n");
5389	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5390	{
5391	uint32_t cMaxSubLeaves = 1;
5392	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
5393	cMaxSubLeaves = 16;
5394	else if (uLeaf == 0xd)
5395	cMaxSubLeaves = 128;
5396
5397	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5398	{
5399	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5400	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5401	#endif
5402	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5403	&& pCurLeaf->uLeaf == uLeaf
5404	&& pCurLeaf->uSubLeaf == uSubLeaf)
5405	{
5406	pHlp->pfnPrintf(pHlp,
5407	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5408	"Hst: %08x %08x %08x %08x\n",
5409	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5410	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5411	pCurLeaf++;
5412	}
5413	else if ( uLeaf != 0xd
5414	\|\| uSubLeaf <= 1
5415	\|\| Host.uEbx != 0 )
5416	pHlp->pfnPrintf(pHlp,
5417	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5418	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5419
5420	/* Done? */
5421	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5422	\|\| pCurLeaf->uLeaf != uLeaf)
5423	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
5424	\|\| (uLeaf == 0x7 && Host.uEax == 0)
5425	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
5426	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5427	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
5428	)
5429	)
5430	break;
5431	}
5432	}
5433	pNextLeaf = pCurLeaf;
5434
5435	/*
5436	* If verbose, decode it.
5437	*/
5438	if (iVerbosity && paLeaves[0].uLeaf == 0)
5439	pHlp->pfnPrintf(pHlp,
5440	"%36s %.04s%.04s%.04s\n"
5441	"%36s 0x00000000-%#010x\n"
5442	,
5443	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5444	"Supports:", paLeaves[0].uEax);
5445
5446	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5447	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
5448
5449	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5450	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5451
5452	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5453	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5454
5455	pCurLeaf = pNextLeaf;
5456
5457	/*
5458	* Hypervisor leaves.
5459	*
5460	* Unlike most of the other leaves reported, the guest hypervisor leaves
5461	* aren't a subset of the host CPUID bits.
5462	*/
5463	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5464
5465	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5466	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5467	#endif
5468	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5469	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5470	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5471	cMax = RT_MAX(cHstMax, cGstMax);
5472	if (cMax >= UINT32_C(0x40000000))
5473	{
5474	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5475
5476	/** @todo dump these in more detail. */
5477
5478	pCurLeaf = pNextLeaf;
5479	}
5480
5481
5482	/*
5483	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
5484	* Implemented after AMD specs.
5485	*/
5486	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
5487
5488	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5489	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5490	#endif
5491	cHstMax = RTX86IsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5492	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
5493	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5494	cMax = RT_MAX(cHstMax, cGstMax);
5495	if (cMax >= UINT32_C(0x80000000))
5496	{
5497
5498	pHlp->pfnPrintf(pHlp,
5499	" Raw Extended CPUID Leaves\n"
5500	" Leaf/sub-leaf eax ebx ecx edx\n");
5501	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
5502	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
5503	{
5504	uint32_t cMaxSubLeaves = 1;
5505	if (uLeaf == UINT32_C(0x8000001d))
5506	cMaxSubLeaves = 16;
5507
5508	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5509	{
5510	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5511	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5512	#endif
5513	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5514	&& pCurLeaf->uLeaf == uLeaf
5515	&& pCurLeaf->uSubLeaf == uSubLeaf)
5516	{
5517	pHlp->pfnPrintf(pHlp,
5518	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5519	"Hst: %08x %08x %08x %08x\n",
5520	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5521	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5522	pCurLeaf++;
5523	}
5524	else if ( uLeaf != 0xd
5525	\|\| uSubLeaf <= 1
5526	\|\| Host.uEbx != 0 )
5527	pHlp->pfnPrintf(pHlp,
5528	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5529	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5530
5531	/* Done? */
5532	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5533	\|\| pCurLeaf->uLeaf != uLeaf)
5534	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
5535	break;
5536	}
5537	}
5538	pNextLeaf = pCurLeaf;
5539
5540	/*
5541	* Understandable output
5542	*/
5543	if (iVerbosity)
5544	pHlp->pfnPrintf(pHlp,
5545	"Ext Name: %.4s%.4s%.4s\n"
5546	"Ext Supports: 0x80000000-%#010x\n",
5547	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
5548
5549	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
5550	if (iVerbosity && pCurLeaf)
5551	{
5552	uint32_t uEAX = pCurLeaf->uEax;
5553	pHlp->pfnPrintf(pHlp,
5554	"Family: %d \tExtended: %d \tEffective: %d\n"
5555	"Model: %d \tExtended: %d \tEffective: %d\n"
5556	"Stepping: %d\n"
5557	"Brand ID: %#05x\n",
5558	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
5559	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
5560	RTX86GetCpuStepping(uEAX),
5561	pCurLeaf->uEbx & 0xfff);
5562
5563	if (iVerbosity == 1)
5564	{
5565	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
5566	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
5567	}
5568	else
5569	{
5570	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5571	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5572	#endif
5573	pHlp->pfnPrintf(pHlp, "Ext Features\n");
5574	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5575	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
5576	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
5577	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
5578	{
5579	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
5580	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5581	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5582	#endif
5583	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
5584	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
5585	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
5586	}
5587	}
5588	}
5589
5590	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
5591	{
5592	char szString[443+1] = {0};
5593	uint32_t pu32 = (uint32_t )szString;
5594	*pu32++ = pCurLeaf->uEax;
5595	*pu32++ = pCurLeaf->uEbx;
5596	*pu32++ = pCurLeaf->uEcx;
5597	*pu32++ = pCurLeaf->uEdx;
5598	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
5599	if (pCurLeaf)
5600	{
5601	*pu32++ = pCurLeaf->uEax;
5602	*pu32++ = pCurLeaf->uEbx;
5603	*pu32++ = pCurLeaf->uEcx;
5604	*pu32++ = pCurLeaf->uEdx;
5605	}
5606	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
5607	if (pCurLeaf)
5608	{
5609	*pu32++ = pCurLeaf->uEax;
5610	*pu32++ = pCurLeaf->uEbx;
5611	*pu32++ = pCurLeaf->uEcx;
5612	*pu32++ = pCurLeaf->uEdx;
5613	}
5614	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
5615	}
5616
5617	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
5618	{
5619	uint32_t uEAX = pCurLeaf->uEax;
5620	uint32_t uEBX = pCurLeaf->uEbx;
5621	uint32_t uECX = pCurLeaf->uEcx;
5622	uint32_t uEDX = pCurLeaf->uEdx;
5623	char sz1[32];
5624	char sz2[32];
5625
5626	pHlp->pfnPrintf(pHlp,
5627	"TLB 2/4M Instr/Uni: %s %3d entries\n"
5628	"TLB 2/4M Data: %s %3d entries\n",
5629	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
5630	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
5631	pHlp->pfnPrintf(pHlp,
5632	"TLB 4K Instr/Uni: %s %3d entries\n"
5633	"TLB 4K Data: %s %3d entries\n",
5634	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
5635	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
5636	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
5637	"L1 Instr Cache Lines Per Tag: %d\n"
5638	"L1 Instr Cache Associativity: %s\n"
5639	"L1 Instr Cache Size: %d KB\n",
5640	(uEDX >> 0) & 0xff,
5641	(uEDX >> 8) & 0xff,
5642	getCacheAss((uEDX >> 16) & 0xff, sz1),
5643	(uEDX >> 24) & 0xff);
5644	pHlp->pfnPrintf(pHlp,
5645	"L1 Data Cache Line Size: %d bytes\n"
5646	"L1 Data Cache Lines Per Tag: %d\n"
5647	"L1 Data Cache Associativity: %s\n"
5648	"L1 Data Cache Size: %d KB\n",
5649	(uECX >> 0) & 0xff,
5650	(uECX >> 8) & 0xff,
5651	getCacheAss((uECX >> 16) & 0xff, sz1),
5652	(uECX >> 24) & 0xff);
5653	}
5654
5655	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
5656	{
5657	uint32_t uEAX = pCurLeaf->uEax;
5658	uint32_t uEBX = pCurLeaf->uEbx;
5659	uint32_t uEDX = pCurLeaf->uEdx;
5660
5661	pHlp->pfnPrintf(pHlp,
5662	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
5663	"L2 TLB 2/4M Data: %s %4d entries\n",
5664	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
5665	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
5666	pHlp->pfnPrintf(pHlp,
5667	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
5668	"L2 TLB 4K Data: %s %4d entries\n",
5669	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
5670	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
5671	pHlp->pfnPrintf(pHlp,
5672	"L2 Cache Line Size: %d bytes\n"
5673	"L2 Cache Lines Per Tag: %d\n"
5674	"L2 Cache Associativity: %s\n"
5675	"L2 Cache Size: %d KB\n",
5676	(uEDX >> 0) & 0xff,
5677	(uEDX >> 8) & 0xf,
5678	getL2CacheAss((uEDX >> 12) & 0xf),
5679	(uEDX >> 16) & 0xffff);
5680	}
5681
5682	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
5683	{
5684	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5685	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5686	#endif
5687	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
5688	{
5689	if (iVerbosity < 1)
5690	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
5691	else
5692	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
5693	}
5694	}
5695
5696	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
5697	if (pCurLeaf != NULL)
5698	{
5699	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5700	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5701	#endif
5702	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
5703	{
5704	if (iVerbosity < 1)
5705	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
5706	else
5707	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
5708	}
5709
5710	if (iVerbosity)
5711	{
5712	uint32_t uEAX = pCurLeaf->uEax;
5713	uint32_t uECX = pCurLeaf->uEcx;
5714
5715	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
5716	* AMD if we get 0, the guest physical address width should be taken from
5717	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
5718	* for guests using nested paging. */
5719	pHlp->pfnPrintf(pHlp,
5720	"Physical Address Width: %d bits\n"
5721	"Virtual Address Width: %d bits\n"
5722	"Guest Physical Address Width: %d bits\n",
5723	(uEAX >> 0) & 0xff,
5724	(uEAX >> 8) & 0xff,
5725	(uEAX >> 16) & 0xff);
5726
5727	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
5728	* count here). */
5729	pHlp->pfnPrintf(pHlp,
5730	"Physical Core Count: %d\n",
5731	((uECX >> 0) & 0xff) + 1);
5732	}
5733	}
5734
5735	pCurLeaf = pNextLeaf;
5736	}
5737
5738
5739
5740	/*
5741	* Centaur.
5742	*/
5743	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
5744
5745	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5746	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5747	#endif
5748	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
5749	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
5750	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
5751	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
5752	cMax = RT_MAX(cHstMax, cGstMax);
5753	if (cMax >= UINT32_C(0xc0000000))
5754	{
5755	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
5756
5757	/*
5758	* Understandable output
5759	*/
5760	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
5761	pHlp->pfnPrintf(pHlp,
5762	"Centaur Supports: 0xc0000000-%#010x\n",
5763	pCurLeaf->uEax);
5764
5765	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
5766	{
5767	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5768	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5769	#endif
5770	uint32_t uEdxGst = pCurLeaf->uEdx;
5771	uint32_t uEdxHst = Host.uEdx;
5772
5773	if (iVerbosity == 1)
5774	{
5775	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
5776	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
5777	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
5778	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
5779	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
5780	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
5781	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
5782	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
5783	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
5784	/* possibly indicating MM/HE and MM/HE-E on older chips... */
5785	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
5786	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
5787	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
5788	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
5789	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
5790	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
5791	for (unsigned iBit = 14; iBit < 32; iBit++)
5792	if (uEdxGst & RT_BIT(iBit))
5793	pHlp->pfnPrintf(pHlp, " %d", iBit);
5794	pHlp->pfnPrintf(pHlp, "\n");
5795	}
5796	else
5797	{
5798	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
5799	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
5800	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
5801	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
5802	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
5803	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
5804	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
5805	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
5806	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
5807	/* possibly indicating MM/HE and MM/HE-E on older chips... */
5808	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
5809	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
5810	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
5811	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
5812	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
5813	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
5814	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
5815	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
5816	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
5817	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
5818	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
5819	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
5820	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
5821	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
5822	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
5823	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
5824	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
5825	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
5826	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
5827	for (unsigned iBit = 27; iBit < 32; iBit++)
5828	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
5829	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
5830	pHlp->pfnPrintf(pHlp, "\n");
5831	}
5832	}
5833
5834	pCurLeaf = pNextLeaf;
5835	}
5836
5837	/*
5838	* The remainder.
5839	*/
5840	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
5841	}
5842
5843	#endif /* !IN_VBOX_CPU_REPORT */
5844

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 95638

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