CPUMR3CpuId.cpp@ 73281

Last change on this file since 73281 was 73274, checked in by vboxsync, 6 years ago
VMM: Nested VMX: bugref:9180 Reports bits of IA32_FEATURE_CONTROL, start implementing IA32_VMX_BASIC MSRs, cleanups.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 337.4 KB

Line
1	/* $Id: CPUMR3CpuId.cpp 73274 2018-07-20 15:40:10Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/nem.h>
27	#include <VBox/vmm/ssm.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/mm.h>
31	#include <VBox/sup.h>
32
33	#include <VBox/err.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/ctype.h>
36	#include <iprt/mem.h>
37	#include <iprt/string.h>
38
39
40	/*********************************************************************************************************************************
41	* Defined Constants And Macros *
42	*********************************************************************************************************************************/
43	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
44	#define CPUM_CPUID_MAX_LEAVES 2048
45	/* Max size we accept for the XSAVE area. */
46	#define CPUM_MAX_XSAVE_AREA_SIZE 10240
47	/* Min size we accept for the XSAVE area. */
48	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
49
50
51	/*********************************************************************************************************************************
52	* Global Variables *
53	*********************************************************************************************************************************/
54	/**
55	* The intel pentium family.
56	*/
57	static const CPUMMICROARCH g_aenmIntelFamily06[] =
58	{
59	/* [ 0(0x00)] = / kCpumMicroarch_Intel_P6, / Pentium Pro A-step (says sandpile.org). */
60	/* [ 1(0x01)] = / kCpumMicroarch_Intel_P6, / Pentium Pro */
61	/* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
62	/* [ 3(0x03)] = / kCpumMicroarch_Intel_P6_II, / PII Klamath */
63	/* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
64	/* [ 5(0x05)] = / kCpumMicroarch_Intel_P6_II, / PII Deschutes */
65	/* [ 6(0x06)] = / kCpumMicroarch_Intel_P6_II, / Celeron Mendocino. */
66	/* [ 7(0x07)] = / kCpumMicroarch_Intel_P6_III, / PIII Katmai. */
67	/* [ 8(0x08)] = / kCpumMicroarch_Intel_P6_III, / PIII Coppermine (includes Celeron). */
68	/* [ 9(0x09)] = / kCpumMicroarch_Intel_P6_M_Banias, / Pentium/Celeron M Banias. */
69	/* [10(0x0a)] = / kCpumMicroarch_Intel_P6_III, / PIII Xeon */
70	/* [11(0x0b)] = / kCpumMicroarch_Intel_P6_III, / PIII Tualatin (includes Celeron). */
71	/* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
72	/* [13(0x0d)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Pentium/Celeron M Dothan. */
73	/* [14(0x0e)] = / kCpumMicroarch_Intel_Core_Yonah, / Core Yonah (Enhanced Pentium M). */
74	/* [15(0x0f)] = / kCpumMicroarch_Intel_Core2_Merom, / Merom */
75	/* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
76	/* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
77	/* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
78	/* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
79	/* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
80	/* [21(0x15)] = / kCpumMicroarch_Intel_P6_M_Dothan, / Tolapai - System-on-a-chip. */
81	/* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
82	/* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
83	/* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
84	/* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
85	/* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
86	/* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
87	/* [28(0x1c)] = / kCpumMicroarch_Intel_Atom_Bonnell, / Diamonville, Pineview, */
88	/* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
89	/* [30(0x1e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Clarksfield, Lynnfield, Jasper Forest. */
90	/* [31(0x1f)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
91	/* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
92	/* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
93	/* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
94	/* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
95	/* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
96	/* [37(0x25)] = / kCpumMicroarch_Intel_Core7_Westmere, / Arrandale, Clarksdale. */
97	/* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
98	/* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
99	/* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
100	/* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
101	/* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
102	/* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
103	/* [44(0x2c)] = / kCpumMicroarch_Intel_Core7_Westmere, / Gulftown, Westmere-EP. */
104	/* [45(0x2d)] = / kCpumMicroarch_Intel_Core7_SandyBridge, / SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
105	/* [46(0x2e)] = / kCpumMicroarch_Intel_Core7_Nehalem, / Beckton (Xeon). */
106	/* [47(0x2f)] = / kCpumMicroarch_Intel_Core7_Westmere, / Westmere-EX. */
107	/* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
108	/* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
109	/* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
110	/* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
111	/* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
112	/* [53(0x35)] = / kCpumMicroarch_Intel_Atom_Saltwell, / ?? */
113	/* [54(0x36)] = / kCpumMicroarch_Intel_Atom_Saltwell, / Cedarview, ++ */
114	/* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
115	/* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
116	/* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
117	/* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
118	/* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
119	/* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
120	/* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
121	/* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
122	/* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
123	/* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
124	/* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
125	/* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
126	/* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
127	/* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
128	/* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
129	/* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
130	/* [71(0x47)] = / kCpumMicroarch_Intel_Core7_Broadwell, / i7-5775C */
131	/* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
132	/* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
133	/* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
134	/* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
135	/* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
136	/* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
137	/* [78(0x4e)] = / kCpumMicroarch_Intel_Core7_Skylake, / unconfirmed */
138	/* [79(0x4f)] = / kCpumMicroarch_Intel_Core7_Broadwell, / unconfirmed, Broadwell-E */
139	/* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
140	/* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
141	/* [82(0x52)] = */ kCpumMicroarch_Intel_Unknown,
142	/* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
143	/* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
144	/* [85(0x55)] = / kCpumMicroarch_Intel_Core7_Skylake, / server cpu */
145	/* [86(0x56)] = / kCpumMicroarch_Intel_Core7_Broadwell, / Xeon D-1540, Broadwell-DE */
146	/* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
147	/* [88(0x58)] = */ kCpumMicroarch_Intel_Unknown,
148	/* [89(0x59)] = */ kCpumMicroarch_Intel_Unknown,
149	/* [90(0x5a)] = / kCpumMicroarch_Intel_Atom_Silvermont, / Moorefield */
150	/* [91(0x5b)] = */ kCpumMicroarch_Intel_Unknown,
151	/* [92(0x5c)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Apollo Lake */
152	/* [93(0x5d)] = / kCpumMicroarch_Intel_Atom_Silvermont, / x3-C3230 */
153	/* [94(0x5e)] = / kCpumMicroarch_Intel_Core7_Skylake, / i7-6700K */
154	/* [95(0x5f)] = / kCpumMicroarch_Intel_Atom_Goldmont, / Denverton */
155	/* [96(0x60)] = */ kCpumMicroarch_Intel_Unknown,
156	/* [97(0x61)] = */ kCpumMicroarch_Intel_Unknown,
157	/* [98(0x62)] = */ kCpumMicroarch_Intel_Unknown,
158	/* [99(0x63)] = */ kCpumMicroarch_Intel_Unknown,
159	/[100(0x64)] = / kCpumMicroarch_Intel_Unknown,
160	/[101(0x65)] = / kCpumMicroarch_Intel_Atom_Silvermont, /* SoFIA */
161	/[102(0x66)] = / kCpumMicroarch_Intel_Core7_CannonLake, /* unconfirmed */
162	/[103(0x67)] = / kCpumMicroarch_Intel_Unknown,
163	/[104(0x68)] = / kCpumMicroarch_Intel_Unknown,
164	/[105(0x69)] = / kCpumMicroarch_Intel_Unknown,
165	/[106(0x6a)] = / kCpumMicroarch_Intel_Unknown,
166	/[107(0x6b)] = / kCpumMicroarch_Intel_Unknown,
167	/[108(0x6c)] = / kCpumMicroarch_Intel_Unknown,
168	/[109(0x6d)] = / kCpumMicroarch_Intel_Unknown,
169	/[110(0x6e)] = / kCpumMicroarch_Intel_Unknown,
170	/[111(0x6f)] = / kCpumMicroarch_Intel_Unknown,
171	/[112(0x70)] = / kCpumMicroarch_Intel_Unknown,
172	/[113(0x71)] = / kCpumMicroarch_Intel_Unknown,
173	/[114(0x72)] = / kCpumMicroarch_Intel_Unknown,
174	/[115(0x73)] = / kCpumMicroarch_Intel_Unknown,
175	/[116(0x74)] = / kCpumMicroarch_Intel_Unknown,
176	/[117(0x75)] = / kCpumMicroarch_Intel_Unknown,
177	/[118(0x76)] = / kCpumMicroarch_Intel_Unknown,
178	/[119(0x77)] = / kCpumMicroarch_Intel_Unknown,
179	/[120(0x78)] = / kCpumMicroarch_Intel_Unknown,
180	/[121(0x79)] = / kCpumMicroarch_Intel_Unknown,
181	/[122(0x7a)] = / kCpumMicroarch_Intel_Atom_GoldmontPlus,
182	/[123(0x7b)] = / kCpumMicroarch_Intel_Unknown,
183	/[124(0x7c)] = / kCpumMicroarch_Intel_Unknown,
184	/[125(0x7d)] = / kCpumMicroarch_Intel_Unknown,
185	/[126(0x7e)] = / kCpumMicroarch_Intel_Core7_IceLake, /* unconfirmed */
186	/[127(0x7f)] = / kCpumMicroarch_Intel_Unknown,
187	/[128(0x80)] = / kCpumMicroarch_Intel_Unknown,
188	/[129(0x81)] = / kCpumMicroarch_Intel_Unknown,
189	/[130(0x82)] = / kCpumMicroarch_Intel_Unknown,
190	/[131(0x83)] = / kCpumMicroarch_Intel_Unknown,
191	/[132(0x84)] = / kCpumMicroarch_Intel_Unknown,
192	/[133(0x85)] = / kCpumMicroarch_Intel_Phi_KnightsMill,
193	/[134(0x86)] = / kCpumMicroarch_Intel_Unknown,
194	/[135(0x87)] = / kCpumMicroarch_Intel_Unknown,
195	/[136(0x88)] = / kCpumMicroarch_Intel_Unknown,
196	/[137(0x89)] = / kCpumMicroarch_Intel_Unknown,
197	/[138(0x8a)] = / kCpumMicroarch_Intel_Unknown,
198	/[139(0x8b)] = / kCpumMicroarch_Intel_Unknown,
199	/[140(0x8c)] = / kCpumMicroarch_Intel_Unknown,
200	/[141(0x8d)] = / kCpumMicroarch_Intel_Unknown,
201	/[142(0x8e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
202	/[143(0x8f)] = / kCpumMicroarch_Intel_Unknown,
203	/[144(0x90)] = / kCpumMicroarch_Intel_Unknown,
204	/[145(0x91)] = / kCpumMicroarch_Intel_Unknown,
205	/[146(0x92)] = / kCpumMicroarch_Intel_Unknown,
206	/[147(0x93)] = / kCpumMicroarch_Intel_Unknown,
207	/[148(0x94)] = / kCpumMicroarch_Intel_Unknown,
208	/[149(0x95)] = / kCpumMicroarch_Intel_Unknown,
209	/[150(0x96)] = / kCpumMicroarch_Intel_Unknown,
210	/[151(0x97)] = / kCpumMicroarch_Intel_Unknown,
211	/[152(0x98)] = / kCpumMicroarch_Intel_Unknown,
212	/[153(0x99)] = / kCpumMicroarch_Intel_Unknown,
213	/[154(0x9a)] = / kCpumMicroarch_Intel_Unknown,
214	/[155(0x9b)] = / kCpumMicroarch_Intel_Unknown,
215	/[156(0x9c)] = / kCpumMicroarch_Intel_Unknown,
216	/[157(0x9d)] = / kCpumMicroarch_Intel_Unknown,
217	/[158(0x9e)] = / kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
218	/[159(0x9f)] = / kCpumMicroarch_Intel_Unknown,
219	};
220	AssertCompile(RT_ELEMENTS(g_aenmIntelFamily06) == 0x9f+1);
221
222
223	/**
224	* Figures out the (sub-)micro architecture given a bit of CPUID info.
225	*
226	* @returns Micro architecture.
227	* @param enmVendor The CPU vendor .
228	* @param bFamily The CPU family.
229	* @param bModel The CPU model.
230	* @param bStepping The CPU stepping.
231	*/
232	VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
233	uint8_t bModel, uint8_t bStepping)
234	{
235	if (enmVendor == CPUMCPUVENDOR_AMD)
236	{
237	switch (bFamily)
238	{
239	case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
240	case 0x03: return kCpumMicroarch_AMD_Am386;
241	case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
242	case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
243	case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
244	case 0x06:
245	switch (bModel)
246	{
247	case 0: return kCpumMicroarch_AMD_K7_Palomino;
248	case 1: return kCpumMicroarch_AMD_K7_Palomino;
249	case 2: return kCpumMicroarch_AMD_K7_Palomino;
250	case 3: return kCpumMicroarch_AMD_K7_Spitfire;
251	case 4: return kCpumMicroarch_AMD_K7_Thunderbird;
252	case 6: return kCpumMicroarch_AMD_K7_Palomino;
253	case 7: return kCpumMicroarch_AMD_K7_Morgan;
254	case 8: return kCpumMicroarch_AMD_K7_Thoroughbred;
255	case 10: return kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
256	}
257	return kCpumMicroarch_AMD_K7_Unknown;
258	case 0x0f:
259	/*
260	* This family is a friggin mess. Trying my best to make some
261	* sense out of it. Too much happened in the 0x0f family to
262	* lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
263	*
264	* Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
265	* cpu-world.com, and other places:
266	* - 130nm:
267	* - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
268	* - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
269	* - Newcastle: FC0/DH-CG (erratum #180: FE0/DH-CG), FF0/DH-CG
270	* - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
271	* - Odessa: FC0/DH-CG (erratum #180: FE0/DH-CG)
272	* - Paris: FF0/DH-CG, FC0/DH-CG (erratum #180: FE0/DH-CG),
273	* - 90nm:
274	* - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
275	* - Oakville: 10FC0/DH-D0.
276	* - Georgetown: 10FC0/DH-D0.
277	* - Sonora: 10FC0/DH-D0.
278	* - Venus: 20F71/SH-E4
279	* - Troy: 20F51/SH-E4
280	* - Athens: 20F51/SH-E4
281	* - San Diego: 20F71/SH-E4.
282	* - Lancaster: 20F42/SH-E5
283	* - Newark: 20F42/SH-E5.
284	* - Albany: 20FC2/DH-E6.
285	* - Roma: 20FC2/DH-E6.
286	* - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
287	* - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
288	* - 90nm introducing Dual core:
289	* - Denmark: 20F30/JH-E1, 20F32/JH-E6
290	* - Italy: 20F10/JH-E1, 20F12/JH-E6
291	* - Egypt: 20F10/JH-E1, 20F12/JH-E6
292	* - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
293	* - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
294	* - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheaper models):
295	* - Santa Ana: 40F32/JH-F2, /-F3
296	* - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
297	* - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
298	* - Manila: 50FF2/DH-F2, 40FF2/DH-F2
299	* - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
300	* - Keene: 40FC2/DH-F2.
301	* - Richmond: 40FC2/DH-F2
302	* - Taylor: 40F82/BH-F2
303	* - Trinidad: 40F82/BH-F2
304	*
305	* - 65nm:
306	* - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
307	* - Tyler: 60F81/BH-G1, 60F82/BH-G2.
308	* - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
309	* - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
310	* - Sherman: /-G1, 70FC2/DH-G2.
311	* - Huron: 70FF2/DH-G2.
312	*/
313	if (bModel < 0x10)
314	return kCpumMicroarch_AMD_K8_130nm;
315	if (bModel >= 0x60 && bModel < 0x80)
316	return kCpumMicroarch_AMD_K8_65nm;
317	if (bModel >= 0x40)
318	return kCpumMicroarch_AMD_K8_90nm_AMDV;
319	switch (bModel)
320	{
321	case 0x21:
322	case 0x23:
323	case 0x2b:
324	case 0x2f:
325	case 0x37:
326	case 0x3f:
327	return kCpumMicroarch_AMD_K8_90nm_DualCore;
328	}
329	return kCpumMicroarch_AMD_K8_90nm;
330	case 0x10:
331	return kCpumMicroarch_AMD_K10;
332	case 0x11:
333	return kCpumMicroarch_AMD_K10_Lion;
334	case 0x12:
335	return kCpumMicroarch_AMD_K10_Llano;
336	case 0x14:
337	return kCpumMicroarch_AMD_Bobcat;
338	case 0x15:
339	switch (bModel)
340	{
341	case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
342	case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
343	case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
344	case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
345	case 0x11: /* ?? */
346	case 0x12: /* ?? */
347	case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
348	}
349	return kCpumMicroarch_AMD_15h_Unknown;
350	case 0x16:
351	return kCpumMicroarch_AMD_Jaguar;
352	case 0x17:
353	return kCpumMicroarch_AMD_Zen_Ryzen;
354	}
355	return kCpumMicroarch_AMD_Unknown;
356	}
357
358	if (enmVendor == CPUMCPUVENDOR_INTEL)
359	{
360	switch (bFamily)
361	{
362	case 3:
363	return kCpumMicroarch_Intel_80386;
364	case 4:
365	return kCpumMicroarch_Intel_80486;
366	case 5:
367	return kCpumMicroarch_Intel_P5;
368	case 6:
369	if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
370	{
371	CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
372	if ( enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
373	&& bStepping >= 0xa)
374	enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
375	return enmMicroArch;
376	}
377	return kCpumMicroarch_Intel_Atom_Unknown;
378	case 15:
379	switch (bModel)
380	{
381	case 0: return kCpumMicroarch_Intel_NB_Willamette;
382	case 1: return kCpumMicroarch_Intel_NB_Willamette;
383	case 2: return kCpumMicroarch_Intel_NB_Northwood;
384	case 3: return kCpumMicroarch_Intel_NB_Prescott;
385	case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
386	case 5: return kCpumMicroarch_Intel_NB_Unknown; /??/
387	case 6: return kCpumMicroarch_Intel_NB_CedarMill;
388	case 7: return kCpumMicroarch_Intel_NB_Gallatin;
389	default: return kCpumMicroarch_Intel_NB_Unknown;
390	}
391	break;
392	/* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
393	case 0:
394	return kCpumMicroarch_Intel_8086;
395	case 1:
396	return kCpumMicroarch_Intel_80186;
397	case 2:
398	return kCpumMicroarch_Intel_80286;
399	}
400	return kCpumMicroarch_Intel_Unknown;
401	}
402
403	if (enmVendor == CPUMCPUVENDOR_VIA)
404	{
405	switch (bFamily)
406	{
407	case 5:
408	switch (bModel)
409	{
410	case 1: return kCpumMicroarch_Centaur_C6;
411	case 4: return kCpumMicroarch_Centaur_C6;
412	case 8: return kCpumMicroarch_Centaur_C2;
413	case 9: return kCpumMicroarch_Centaur_C3;
414	}
415	break;
416
417	case 6:
418	switch (bModel)
419	{
420	case 5: return kCpumMicroarch_VIA_C3_M2;
421	case 6: return kCpumMicroarch_VIA_C3_C5A;
422	case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
423	case 8: return kCpumMicroarch_VIA_C3_C5N;
424	case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
425	case 10: return kCpumMicroarch_VIA_C7_C5J;
426	case 15: return kCpumMicroarch_VIA_Isaiah;
427	}
428	break;
429	}
430	return kCpumMicroarch_VIA_Unknown;
431	}
432
433	if (enmVendor == CPUMCPUVENDOR_CYRIX)
434	{
435	switch (bFamily)
436	{
437	case 4:
438	switch (bModel)
439	{
440	case 9: return kCpumMicroarch_Cyrix_5x86;
441	}
442	break;
443
444	case 5:
445	switch (bModel)
446	{
447	case 2: return kCpumMicroarch_Cyrix_M1;
448	case 4: return kCpumMicroarch_Cyrix_MediaGX;
449	case 5: return kCpumMicroarch_Cyrix_MediaGXm;
450	}
451	break;
452
453	case 6:
454	switch (bModel)
455	{
456	case 0: return kCpumMicroarch_Cyrix_M2;
457	}
458	break;
459
460	}
461	return kCpumMicroarch_Cyrix_Unknown;
462	}
463
464	return kCpumMicroarch_Unknown;
465	}
466
467
468	/**
469	* Translates a microarchitecture enum value to the corresponding string
470	* constant.
471	*
472	* @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
473	* NULL if the value is invalid.
474	*
475	* @param enmMicroarch The enum value to convert.
476	*/
477	VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
478	{
479	switch (enmMicroarch)
480	{
481	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
482	CASE_RET_STR(kCpumMicroarch_Intel_8086);
483	CASE_RET_STR(kCpumMicroarch_Intel_80186);
484	CASE_RET_STR(kCpumMicroarch_Intel_80286);
485	CASE_RET_STR(kCpumMicroarch_Intel_80386);
486	CASE_RET_STR(kCpumMicroarch_Intel_80486);
487	CASE_RET_STR(kCpumMicroarch_Intel_P5);
488
489	CASE_RET_STR(kCpumMicroarch_Intel_P6);
490	CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
491	CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
492
493	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
494	CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
495	CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
496
497	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
498	CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
499
500	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
501	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
502	CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
503	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
504	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
505	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
506	CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
507	CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
508	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
509	CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
510	CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
511	CASE_RET_STR(kCpumMicroarch_Intel_Core7_TigerLake);
512
513	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
514	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
515	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
516	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
517	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
518	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
519	CASE_RET_STR(kCpumMicroarch_Intel_Atom_GoldmontPlus);
520	CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
521
522	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsFerry);
523	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsCorner);
524	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsLanding);
525	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsHill);
526	CASE_RET_STR(kCpumMicroarch_Intel_Phi_KnightsMill);
527
528	CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
529	CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
530	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
531	CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
532	CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
533	CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
534	CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
535
536	CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
537
538	CASE_RET_STR(kCpumMicroarch_AMD_Am286);
539	CASE_RET_STR(kCpumMicroarch_AMD_Am386);
540	CASE_RET_STR(kCpumMicroarch_AMD_Am486);
541	CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
542	CASE_RET_STR(kCpumMicroarch_AMD_K5);
543	CASE_RET_STR(kCpumMicroarch_AMD_K6);
544
545	CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
546	CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
547	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
548	CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
549	CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
550	CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
551	CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
552
553	CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
554	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
555	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
556	CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
557	CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
558
559	CASE_RET_STR(kCpumMicroarch_AMD_K10);
560	CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
561	CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
562	CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
563	CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
564
565	CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
566	CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
567	CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
568	CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
569	CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
570
571	CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
572
573	CASE_RET_STR(kCpumMicroarch_AMD_Zen_Ryzen);
574
575	CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
576
577	CASE_RET_STR(kCpumMicroarch_Centaur_C6);
578	CASE_RET_STR(kCpumMicroarch_Centaur_C2);
579	CASE_RET_STR(kCpumMicroarch_Centaur_C3);
580	CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
581	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
582	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
583	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
584	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
585	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
586	CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
587	CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
588	CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
589	CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
590
591	CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
592	CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
593	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
594	CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
595	CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
596	CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
597
598	CASE_RET_STR(kCpumMicroarch_NEC_V20);
599	CASE_RET_STR(kCpumMicroarch_NEC_V30);
600
601	CASE_RET_STR(kCpumMicroarch_Unknown);
602
603	#undef CASE_RET_STR
604	case kCpumMicroarch_Invalid:
605	case kCpumMicroarch_Intel_End:
606	case kCpumMicroarch_Intel_Core2_End:
607	case kCpumMicroarch_Intel_Core7_End:
608	case kCpumMicroarch_Intel_Atom_End:
609	case kCpumMicroarch_Intel_P6_Core_Atom_End:
610	case kCpumMicroarch_Intel_Phi_End:
611	case kCpumMicroarch_Intel_NB_End:
612	case kCpumMicroarch_AMD_K7_End:
613	case kCpumMicroarch_AMD_K8_End:
614	case kCpumMicroarch_AMD_15h_End:
615	case kCpumMicroarch_AMD_16h_End:
616	case kCpumMicroarch_AMD_Zen_End:
617	case kCpumMicroarch_AMD_End:
618	case kCpumMicroarch_VIA_End:
619	case kCpumMicroarch_Cyrix_End:
620	case kCpumMicroarch_NEC_End:
621	case kCpumMicroarch_32BitHack:
622	break;
623	/* no default! */
624	}
625
626	return NULL;
627	}
628
629
630	/**
631	* Determins the host CPU MXCSR mask.
632	*
633	* @returns MXCSR mask.
634	*/
635	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
636	{
637	if ( ASMHasCpuId()
638	&& ASMIsValidStdRange(ASMCpuId_EAX(0))
639	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
640	{
641	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
642	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
643	RT_ZERO(*pState);
644	ASMFxSave(pState);
645	if (pState->MXCSR_MASK == 0)
646	return 0xffbf;
647	return pState->MXCSR_MASK;
648	}
649	return 0;
650	}
651
652
653	/**
654	* Gets a matching leaf in the CPUID leaf array.
655	*
656	* @returns Pointer to the matching leaf, or NULL if not found.
657	* @param paLeaves The CPUID leaves to search. This is sorted.
658	* @param cLeaves The number of leaves in the array.
659	* @param uLeaf The leaf to locate.
660	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
661	*/
662	static PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
663	{
664	/* Lazy bird does linear lookup here since this is only used for the
665	occational CPUID overrides. */
666	for (uint32_t i = 0; i < cLeaves; i++)
667	if ( paLeaves[i].uLeaf == uLeaf
668	&& paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
669	return &paLeaves[i];
670	return NULL;
671	}
672
673
674	#ifndef IN_VBOX_CPU_REPORT
675	/**
676	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
677	*
678	* @returns true if found, false it not.
679	* @param paLeaves The CPUID leaves to search. This is sorted.
680	* @param cLeaves The number of leaves in the array.
681	* @param uLeaf The leaf to locate.
682	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
683	* @param pLegacy The legacy output leaf.
684	*/
685	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
686	PCPUMCPUID pLegacy)
687	{
688	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
689	if (pLeaf)
690	{
691	pLegacy->uEax = pLeaf->uEax;
692	pLegacy->uEbx = pLeaf->uEbx;
693	pLegacy->uEcx = pLeaf->uEcx;
694	pLegacy->uEdx = pLeaf->uEdx;
695	return true;
696	}
697	return false;
698	}
699	#endif /* IN_VBOX_CPU_REPORT */
700
701
702	/**
703	* Ensures that the CPUID leaf array can hold one more leaf.
704	*
705	* @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
706	* failure.
707	* @param pVM The cross context VM structure. If NULL, use
708	* the process heap, otherwise the VM's hyper heap.
709	* @param ppaLeaves Pointer to the variable holding the array pointer
710	* (input/output).
711	* @param cLeaves The current array size.
712	*
713	* @remarks This function will automatically update the R0 and RC pointers when
714	* using the hyper heap, which means @a ppaLeaves and @a cLeaves must
715	* be the corresponding VM's CPUID arrays (which is asserted).
716	*/
717	static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
718	{
719	/*
720	* If pVM is not specified, we're on the regular heap and can waste a
721	* little space to speed things up.
722	*/
723	uint32_t cAllocated;
724	if (!pVM)
725	{
726	cAllocated = RT_ALIGN(cLeaves, 16);
727	if (cLeaves + 1 > cAllocated)
728	{
729	void pvNew = RTMemRealloc(ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
730	if (pvNew)
731	*ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
732	else
733	{
734	RTMemFree(*ppaLeaves);
735	*ppaLeaves = NULL;
736	}
737	}
738	}
739	/*
740	* Otherwise, we're on the hyper heap and are probably just inserting
741	* one or two leaves and should conserve space.
742	*/
743	else
744	{
745	#ifdef IN_VBOX_CPU_REPORT
746	AssertReleaseFailed();
747	#else
748	Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
749	Assert(cLeaves == pVM->cpum.s.GuestInfo.cCpuIdLeaves);
750
751	size_t cb = cLeaves * sizeof(**ppaLeaves);
752	size_t cbNew = (cLeaves + 1) * sizeof(**ppaLeaves);
753	int rc = MMR3HyperRealloc(pVM, ppaLeaves, cb, 32, MM_TAG_CPUM_CPUID, cbNew, (void *)ppaLeaves);
754	if (RT_SUCCESS(rc))
755	{
756	/* Update the R0 and RC pointers. */
757	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, *ppaLeaves);
758	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, *ppaLeaves);
759	}
760	else
761	{
762	*ppaLeaves = NULL;
763	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
764	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
765	LogRel(("CPUM: cpumR3CpuIdEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
766	}
767	#endif
768	}
769	return *ppaLeaves;
770	}
771
772
773	/**
774	* Append a CPUID leaf or sub-leaf.
775	*
776	* ASSUMES linear insertion order, so we'll won't need to do any searching or
777	* replace anything. Use cpumR3CpuIdInsert() for those cases.
778	*
779	* @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
780	* the caller need do no more work.
781	* @param ppaLeaves Pointer to the pointer to the array of sorted
782	* CPUID leaves and sub-leaves.
783	* @param pcLeaves Where we keep the leaf count for *ppaLeaves.
784	* @param uLeaf The leaf we're adding.
785	* @param uSubLeaf The sub-leaf number.
786	* @param fSubLeafMask The sub-leaf mask.
787	* @param uEax The EAX value.
788	* @param uEbx The EBX value.
789	* @param uEcx The ECX value.
790	* @param uEdx The EDX value.
791	* @param fFlags The flags.
792	*/
793	static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves,
794	uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
795	uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
796	{
797	if (!cpumR3CpuIdEnsureSpace(NULL /* pVM /, ppaLeaves, pcLeaves))
798	return VERR_NO_MEMORY;
799
800	PCPUMCPUIDLEAF pNew = &(ppaLeaves)[pcLeaves];
801	Assert( *pcLeaves == 0
802	\|\| pNew[-1].uLeaf < uLeaf
803	\|\| (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
804
805	pNew->uLeaf = uLeaf;
806	pNew->uSubLeaf = uSubLeaf;
807	pNew->fSubLeafMask = fSubLeafMask;
808	pNew->uEax = uEax;
809	pNew->uEbx = uEbx;
810	pNew->uEcx = uEcx;
811	pNew->uEdx = uEdx;
812	pNew->fFlags = fFlags;
813
814	*pcLeaves += 1;
815	return VINF_SUCCESS;
816	}
817
818
819	/**
820	* Checks that we've updated the CPUID leaves array correctly.
821	*
822	* This is a no-op in non-strict builds.
823	*
824	* @param paLeaves The leaves array.
825	* @param cLeaves The number of leaves.
826	*/
827	static void cpumR3CpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
828	{
829	#ifdef VBOX_STRICT
830	for (uint32_t i = 1; i < cLeaves; i++)
831	if (paLeaves[i].uLeaf != paLeaves[i - 1].uLeaf)
832	AssertMsg(paLeaves[i].uLeaf > paLeaves[i - 1].uLeaf, ("%#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i - 1].uLeaf));
833	else
834	{
835	AssertMsg(paLeaves[i].uSubLeaf > paLeaves[i - 1].uSubLeaf,
836	("%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i - 1].uSubLeaf));
837	AssertMsg(paLeaves[i].fSubLeafMask == paLeaves[i - 1].fSubLeafMask,
838	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fSubLeafMask, paLeaves[i - 1].fSubLeafMask));
839	AssertMsg(paLeaves[i].fFlags == paLeaves[i - 1].fFlags,
840	("%#x/%#x: %#x vs %#x\n", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf, paLeaves[i].fFlags, paLeaves[i - 1].fFlags));
841	}
842	#else
843	NOREF(paLeaves);
844	NOREF(cLeaves);
845	#endif
846	}
847
848
849	/**
850	* Inserts a CPU ID leaf, replacing any existing ones.
851	*
852	* When inserting a simple leaf where we already got a series of sub-leaves with
853	* the same leaf number (eax), the simple leaf will replace the whole series.
854	*
855	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
856	* host-context heap and has only been allocated/reallocated by the
857	* cpumR3CpuIdEnsureSpace function.
858	*
859	* @returns VBox status code.
860	* @param pVM The cross context VM structure. If NULL, use
861	* the process heap, otherwise the VM's hyper heap.
862	* @param ppaLeaves Pointer to the pointer to the array of sorted
863	* CPUID leaves and sub-leaves. Must be NULL if using
864	* the hyper heap.
865	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
866	* be NULL if using the hyper heap.
867	* @param pNewLeaf Pointer to the data of the new leaf we're about to
868	* insert.
869	*/
870	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
871	{
872	/*
873	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
874	*/
875	if (pVM)
876	{
877	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
878	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
879
880	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
881	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
882	}
883
884	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
885	uint32_t cLeaves = *pcLeaves;
886
887	/*
888	* Validate the new leaf a little.
889	*/
890	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
891	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
892	VERR_INVALID_FLAGS);
893	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
894	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
895	VERR_INVALID_PARAMETER);
896	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
897	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
898	VERR_INVALID_PARAMETER);
899	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
900	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
901	VERR_INVALID_PARAMETER);
902
903	/*
904	* Find insertion point. The lazy bird uses the same excuse as in
905	* cpumR3CpuIdGetLeaf(), but optimizes for linear insertion (saved state).
906	*/
907	uint32_t i;
908	if ( cLeaves > 0
909	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
910	{
911	/* Add at end. */
912	i = cLeaves;
913	}
914	else if ( cLeaves > 0
915	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
916	{
917	/* Either replacing the last leaf or dealing with sub-leaves. Spool
918	back to the first sub-leaf to pretend we did the linear search. */
919	i = cLeaves - 1;
920	while ( i > 0
921	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
922	i--;
923	}
924	else
925	{
926	/* Linear search from the start. */
927	i = 0;
928	while ( i < cLeaves
929	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
930	i++;
931	}
932	if ( i < cLeaves
933	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
934	{
935	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
936	{
937	/*
938	* The sub-leaf mask differs, replace all existing leaves with the
939	* same leaf number.
940	*/
941	uint32_t c = 1;
942	while ( i + c < cLeaves
943	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
944	c++;
945	if (c > 1 && i + c < cLeaves)
946	{
947	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
948	*pcLeaves = cLeaves -= c - 1;
949	}
950
951	paLeaves[i] = *pNewLeaf;
952	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
953	return VINF_SUCCESS;
954	}
955
956	/* Find sub-leaf insertion point. */
957	while ( i < cLeaves
958	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
959	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
960	i++;
961
962	/*
963	* If we've got an exactly matching leaf, replace it.
964	*/
965	if ( i < cLeaves
966	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
967	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
968	{
969	paLeaves[i] = *pNewLeaf;
970	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
971	return VINF_SUCCESS;
972	}
973	}
974
975	/*
976	* Adding a new leaf at 'i'.
977	*/
978	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
979	paLeaves = cpumR3CpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
980	if (!paLeaves)
981	return VERR_NO_MEMORY;
982
983	if (i < cLeaves)
984	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
985	*pcLeaves += 1;
986	paLeaves[i] = *pNewLeaf;
987
988	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
989	return VINF_SUCCESS;
990	}
991
992
993	#ifndef IN_VBOX_CPU_REPORT
994	/**
995	* Removes a range of CPUID leaves.
996	*
997	* This will not reallocate the array.
998	*
999	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
1000	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
1001	* @param uFirst The first leaf.
1002	* @param uLast The last leaf.
1003	*/
1004	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
1005	{
1006	uint32_t cLeaves = *pcLeaves;
1007
1008	Assert(uFirst <= uLast);
1009
1010	/*
1011	* Find the first one.
1012	*/
1013	uint32_t iFirst = 0;
1014	while ( iFirst < cLeaves
1015	&& paLeaves[iFirst].uLeaf < uFirst)
1016	iFirst++;
1017
1018	/*
1019	* Find the end (last + 1).
1020	*/
1021	uint32_t iEnd = iFirst;
1022	while ( iEnd < cLeaves
1023	&& paLeaves[iEnd].uLeaf <= uLast)
1024	iEnd++;
1025
1026	/*
1027	* Adjust the array if anything needs removing.
1028	*/
1029	if (iFirst < iEnd)
1030	{
1031	if (iEnd < cLeaves)
1032	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
1033	*pcLeaves = cLeaves -= (iEnd - iFirst);
1034	}
1035
1036	cpumR3CpuIdAssertOrder(paLeaves, *pcLeaves);
1037	}
1038	#endif /* IN_VBOX_CPU_REPORT */
1039
1040
1041	/**
1042	* Checks if ECX make a difference when reading a given CPUID leaf.
1043	*
1044	* @returns @c true if it does, @c false if it doesn't.
1045	* @param uLeaf The leaf we're reading.
1046	* @param pcSubLeaves Number of sub-leaves accessible via ECX.
1047	* @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
1048	* final sub-leaf (for leaf 0xb only).
1049	*/
1050	static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t pcSubLeaves, bool pfFinalEcxUnchanged)
1051	{
1052	*pfFinalEcxUnchanged = false;
1053
1054	uint32_t auCur[4];
1055	uint32_t auPrev[4];
1056	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
1057
1058	/* Look for sub-leaves. */
1059	uint32_t uSubLeaf = 1;
1060	for (;;)
1061	{
1062	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1063	if (memcmp(auCur, auPrev, sizeof(auCur)))
1064	break;
1065
1066	/* Advance / give up. */
1067	uSubLeaf++;
1068	if (uSubLeaf >= 64)
1069	{
1070	*pcSubLeaves = 1;
1071	return false;
1072	}
1073	}
1074
1075	/* Count sub-leaves. */
1076	uint32_t cMinLeaves = uLeaf == 0xd ? 64 : 0;
1077	uint32_t cRepeats = 0;
1078	uSubLeaf = 0;
1079	for (;;)
1080	{
1081	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1082
1083	/* Figuring out when to stop isn't entirely straight forward as we need
1084	to cover undocumented behavior up to a point and implementation shortcuts. */
1085
1086	/* 1. Look for more than 4 repeating value sets. */
1087	if ( auCur[0] == auPrev[0]
1088	&& auCur[1] == auPrev[1]
1089	&& ( auCur[2] == auPrev[2]
1090	\|\| ( auCur[2] == uSubLeaf
1091	&& auPrev[2] == uSubLeaf - 1) )
1092	&& auCur[3] == auPrev[3])
1093	{
1094	if ( uLeaf != 0xd
1095	\|\| uSubLeaf >= 64
1096	\|\| ( auCur[0] == 0
1097	&& auCur[1] == 0
1098	&& auCur[2] == 0
1099	&& auCur[3] == 0
1100	&& auPrev[2] == 0) )
1101	cRepeats++;
1102	if (cRepeats > 4 && uSubLeaf >= cMinLeaves)
1103	break;
1104	}
1105	else
1106	cRepeats = 0;
1107
1108	/* 2. Look for zero values. */
1109	if ( auCur[0] == 0
1110	&& auCur[1] == 0
1111	&& (auCur[2] == 0 \|\| auCur[2] == uSubLeaf)
1112	&& (auCur[3] == 0 \|\| uLeaf == 0xb /* edx is fixed */)
1113	&& uSubLeaf >= cMinLeaves)
1114	{
1115	cRepeats = 0;
1116	break;
1117	}
1118
1119	/* 3. Leaf 0xb level type 0 check. */
1120	if ( uLeaf == 0xb
1121	&& (auCur[2] & 0xff00) == 0
1122	&& (auPrev[2] & 0xff00) == 0)
1123	{
1124	cRepeats = 0;
1125	break;
1126	}
1127
1128	/* 99. Give up. */
1129	if (uSubLeaf >= 128)
1130	{
1131	#ifndef IN_VBOX_CPU_REPORT
1132	/* Ok, limit it according to the documentation if possible just to
1133	avoid annoying users with these detection issues. */
1134	uint32_t cDocLimit = UINT32_MAX;
1135	if (uLeaf == 0x4)
1136	cDocLimit = 4;
1137	else if (uLeaf == 0x7)
1138	cDocLimit = 1;
1139	else if (uLeaf == 0xd)
1140	cDocLimit = 63;
1141	else if (uLeaf == 0xf)
1142	cDocLimit = 2;
1143	if (cDocLimit != UINT32_MAX)
1144	{
1145	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1146	*pcSubLeaves = cDocLimit + 3;
1147	return true;
1148	}
1149	#endif
1150	*pcSubLeaves = UINT32_MAX;
1151	return true;
1152	}
1153
1154	/* Advance. */
1155	uSubLeaf++;
1156	memcpy(auPrev, auCur, sizeof(auCur));
1157	}
1158
1159	/* Standard exit. */
1160	*pfFinalEcxUnchanged = auCur[2] == uSubLeaf && uLeaf == 0xb;
1161	*pcSubLeaves = uSubLeaf + 1 - cRepeats;
1162	if (*pcSubLeaves == 0)
1163	*pcSubLeaves = 1;
1164	return true;
1165	}
1166
1167
1168	/**
1169	* Gets a CPU ID leaf.
1170	*
1171	* @returns VBox status code.
1172	* @param pVM The cross context VM structure.
1173	* @param pLeaf Where to store the found leaf.
1174	* @param uLeaf The leaf to locate.
1175	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
1176	*/
1177	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
1178	{
1179	PCPUMCPUIDLEAF pcLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
1180	uLeaf, uSubLeaf);
1181	if (pcLeaf)
1182	{
1183	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
1184	return VINF_SUCCESS;
1185	}
1186
1187	return VERR_NOT_FOUND;
1188	}
1189
1190
1191	/**
1192	* Inserts a CPU ID leaf, replacing any existing ones.
1193	*
1194	* @returns VBox status code.
1195	* @param pVM The cross context VM structure.
1196	* @param pNewLeaf Pointer to the leaf being inserted.
1197	*/
1198	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
1199	{
1200	/*
1201	* Validate parameters.
1202	*/
1203	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1204	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
1205
1206	/*
1207	* Disallow replacing CPU ID leaves that this API currently cannot manage.
1208	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
1209	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
1210	*/
1211	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
1212	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
1213	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
1214	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
1215	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
1216	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
1217	{
1218	return VERR_NOT_SUPPORTED;
1219	}
1220
1221	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
1222	}
1223
1224	/**
1225	* Collects CPUID leaves and sub-leaves, returning a sorted array of them.
1226	*
1227	* @returns VBox status code.
1228	* @param ppaLeaves Where to return the array pointer on success.
1229	* Use RTMemFree to release.
1230	* @param pcLeaves Where to return the size of the array on
1231	* success.
1232	*/
1233	VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
1234	{
1235	*ppaLeaves = NULL;
1236	*pcLeaves = 0;
1237
1238	/*
1239	* Try out various candidates. This must be sorted!
1240	*/
1241	static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
1242	{
1243	{ UINT32_C(0x00000000), false },
1244	{ UINT32_C(0x10000000), false },
1245	{ UINT32_C(0x20000000), false },
1246	{ UINT32_C(0x30000000), false },
1247	{ UINT32_C(0x40000000), false },
1248	{ UINT32_C(0x50000000), false },
1249	{ UINT32_C(0x60000000), false },
1250	{ UINT32_C(0x70000000), false },
1251	{ UINT32_C(0x80000000), false },
1252	{ UINT32_C(0x80860000), false },
1253	{ UINT32_C(0x8ffffffe), true },
1254	{ UINT32_C(0x8fffffff), true },
1255	{ UINT32_C(0x90000000), false },
1256	{ UINT32_C(0xa0000000), false },
1257	{ UINT32_C(0xb0000000), false },
1258	{ UINT32_C(0xc0000000), false },
1259	{ UINT32_C(0xd0000000), false },
1260	{ UINT32_C(0xe0000000), false },
1261	{ UINT32_C(0xf0000000), false },
1262	};
1263
1264	for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
1265	{
1266	uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
1267	uint32_t uEax, uEbx, uEcx, uEdx;
1268	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1269
1270	/*
1271	* Does EAX look like a typical leaf count value?
1272	*/
1273	if ( uEax > uLeaf
1274	&& uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
1275	{
1276	/* Yes, dump them. */
1277	uint32_t cLeaves = uEax - uLeaf + 1;
1278	while (cLeaves-- > 0)
1279	{
1280	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
1281
1282	uint32_t fFlags = 0;
1283
1284	/* There are currently three known leaves containing an APIC ID
1285	that needs EMT specific attention */
1286	if (uLeaf == 1)
1287	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1288	else if (uLeaf == 0xb && uEcx != 0)
1289	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1290	else if ( uLeaf == UINT32_C(0x8000001e)
1291	&& ( uEax
1292	\|\| uEbx
1293	\|\| uEdx
1294	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1295	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
1296
1297	/* The APIC bit is per-VCpu and needs flagging. */
1298	if (uLeaf == 1)
1299	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1300	else if ( uLeaf == UINT32_C(0x80000001)
1301	&& ( (uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC)
1302	\|\| ASMIsAmdCpuEx((ppaLeaves)[0].uEbx, (ppaLeaves)[0].uEcx, (*ppaLeaves)[0].uEdx)) )
1303	fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_APIC;
1304
1305	/* Check three times here to reduce the chance of CPU migration
1306	resulting in false positives with things like the APIC ID. */
1307	uint32_t cSubLeaves;
1308	bool fFinalEcxUnchanged;
1309	if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1310	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
1311	&& cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
1312	{
1313	if (cSubLeaves > (uLeaf == 0xd ? 68U : 16U))
1314	{
1315	/* This shouldn't happen. But in case it does, file all
1316	relevant details in the release log. */
1317	LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
1318	LogRel(("------------------ dump of problematic sub-leaves -----------------\n"));
1319	for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
1320	{
1321	uint32_t auTmp[4];
1322	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
1323	LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
1324	uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
1325	}
1326	LogRel(("----------------- dump of what we've found so far -----------------\n"));
1327	for (uint32_t i = 0 ; i < *pcLeaves; i++)
1328	LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
1329	(ppaLeaves)[i].uLeaf, (ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
1330	(ppaLeaves)[i].uEax, (ppaLeaves)[i].uEbx, (ppaLeaves)[i].uEcx, (ppaLeaves)[i].uEdx));
1331	LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
1332	return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
1333	}
1334
1335	if (fFinalEcxUnchanged)
1336	fFlags \|= CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
1337
1338	for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
1339	{
1340	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
1341	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1342	uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx, fFlags);
1343	if (RT_FAILURE(rc))
1344	return rc;
1345	}
1346	}
1347	else
1348	{
1349	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1350	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, fFlags);
1351	if (RT_FAILURE(rc))
1352	return rc;
1353	}
1354
1355	/* next */
1356	uLeaf++;
1357	}
1358	}
1359	/*
1360	* Special CPUIDs needs special handling as they don't follow the
1361	* leaf count principle used above.
1362	*/
1363	else if (s_aCandidates[iOuter].fSpecial)
1364	{
1365	bool fKeep = false;
1366	if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
1367	fKeep = true;
1368	else if ( uLeaf == 0x8fffffff
1369	&& RT_C_IS_PRINT(RT_BYTE1(uEax))
1370	&& RT_C_IS_PRINT(RT_BYTE2(uEax))
1371	&& RT_C_IS_PRINT(RT_BYTE3(uEax))
1372	&& RT_C_IS_PRINT(RT_BYTE4(uEax))
1373	&& RT_C_IS_PRINT(RT_BYTE1(uEbx))
1374	&& RT_C_IS_PRINT(RT_BYTE2(uEbx))
1375	&& RT_C_IS_PRINT(RT_BYTE3(uEbx))
1376	&& RT_C_IS_PRINT(RT_BYTE4(uEbx))
1377	&& RT_C_IS_PRINT(RT_BYTE1(uEcx))
1378	&& RT_C_IS_PRINT(RT_BYTE2(uEcx))
1379	&& RT_C_IS_PRINT(RT_BYTE3(uEcx))
1380	&& RT_C_IS_PRINT(RT_BYTE4(uEcx))
1381	&& RT_C_IS_PRINT(RT_BYTE1(uEdx))
1382	&& RT_C_IS_PRINT(RT_BYTE2(uEdx))
1383	&& RT_C_IS_PRINT(RT_BYTE3(uEdx))
1384	&& RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1385	fKeep = true;
1386	if (fKeep)
1387	{
1388	int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1389	uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1390	if (RT_FAILURE(rc))
1391	return rc;
1392	}
1393	}
1394	}
1395
1396	cpumR3CpuIdAssertOrder(ppaLeaves, pcLeaves);
1397	return VINF_SUCCESS;
1398	}
1399
1400
1401	/**
1402	* Determines the method the CPU uses to handle unknown CPUID leaves.
1403	*
1404	* @returns VBox status code.
1405	* @param penmUnknownMethod Where to return the method.
1406	* @param pDefUnknown Where to return default unknown values. This
1407	* will be set, even if the resulting method
1408	* doesn't actually needs it.
1409	*/
1410	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1411	{
1412	uint32_t uLastStd = ASMCpuId_EAX(0);
1413	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1414	if (!ASMIsValidExtRange(uLastExt))
1415	uLastExt = 0x80000000;
1416
1417	uint32_t auChecks[] =
1418	{
1419	uLastStd + 1,
1420	uLastStd + 5,
1421	uLastStd + 8,
1422	uLastStd + 32,
1423	uLastStd + 251,
1424	uLastExt + 1,
1425	uLastExt + 8,
1426	uLastExt + 15,
1427	uLastExt + 63,
1428	uLastExt + 255,
1429	0x7fbbffcc,
1430	0x833f7872,
1431	0xefff2353,
1432	0x35779456,
1433	0x1ef6d33e,
1434	};
1435
1436	static const uint32_t s_auValues[] =
1437	{
1438	0xa95d2156,
1439	0x00000001,
1440	0x00000002,
1441	0x00000008,
1442	0x00000000,
1443	0x55773399,
1444	0x93401769,
1445	0x12039587,
1446	};
1447
1448	/*
1449	* Simple method, all zeros.
1450	*/
1451	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
1452	pDefUnknown->uEax = 0;
1453	pDefUnknown->uEbx = 0;
1454	pDefUnknown->uEcx = 0;
1455	pDefUnknown->uEdx = 0;
1456
1457	/*
1458	* Intel has been observed returning the last standard leaf.
1459	*/
1460	uint32_t auLast[4];
1461	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1462
1463	uint32_t cChecks = RT_ELEMENTS(auChecks);
1464	while (cChecks > 0)
1465	{
1466	uint32_t auCur[4];
1467	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1468	if (memcmp(auCur, auLast, sizeof(auCur)))
1469	break;
1470	cChecks--;
1471	}
1472	if (cChecks == 0)
1473	{
1474	/* Now, what happens when the input changes? Esp. ECX. */
1475	uint32_t cTotal = 0;
1476	uint32_t cSame = 0;
1477	uint32_t cLastWithEcx = 0;
1478	uint32_t cNeither = 0;
1479	uint32_t cValues = RT_ELEMENTS(s_auValues);
1480	while (cValues > 0)
1481	{
1482	uint32_t uValue = s_auValues[cValues - 1];
1483	uint32_t auLastWithEcx[4];
1484	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1485	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1486
1487	cChecks = RT_ELEMENTS(auChecks);
1488	while (cChecks > 0)
1489	{
1490	uint32_t auCur[4];
1491	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1492	if (!memcmp(auCur, auLast, sizeof(auCur)))
1493	{
1494	cSame++;
1495	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1496	cLastWithEcx++;
1497	}
1498	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1499	cLastWithEcx++;
1500	else
1501	cNeither++;
1502	cTotal++;
1503	cChecks--;
1504	}
1505	cValues--;
1506	}
1507
1508	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1509	if (cSame == cTotal)
1510	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1511	else if (cLastWithEcx == cTotal)
1512	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1513	else
1514	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
1515	pDefUnknown->uEax = auLast[0];
1516	pDefUnknown->uEbx = auLast[1];
1517	pDefUnknown->uEcx = auLast[2];
1518	pDefUnknown->uEdx = auLast[3];
1519	return VINF_SUCCESS;
1520	}
1521
1522	/*
1523	* Unchanged register values?
1524	*/
1525	cChecks = RT_ELEMENTS(auChecks);
1526	while (cChecks > 0)
1527	{
1528	uint32_t const uLeaf = auChecks[cChecks - 1];
1529	uint32_t cValues = RT_ELEMENTS(s_auValues);
1530	while (cValues > 0)
1531	{
1532	uint32_t uValue = s_auValues[cValues - 1];
1533	uint32_t auCur[4];
1534	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1535	if ( auCur[0] != uLeaf
1536	\|\| auCur[1] != uValue
1537	\|\| auCur[2] != uValue
1538	\|\| auCur[3] != uValue)
1539	break;
1540	cValues--;
1541	}
1542	if (cValues != 0)
1543	break;
1544	cChecks--;
1545	}
1546	if (cChecks == 0)
1547	{
1548	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
1549	return VINF_SUCCESS;
1550	}
1551
1552	/*
1553	* Just go with the simple method.
1554	*/
1555	return VINF_SUCCESS;
1556	}
1557
1558
1559	/**
1560	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
1561	*
1562	* @returns Read only name string.
1563	* @param enmUnknownMethod The method to translate.
1564	*/
1565	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
1566	{
1567	switch (enmUnknownMethod)
1568	{
1569	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1570	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1571	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1572	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1573
1574	case CPUMUNKNOWNCPUID_INVALID:
1575	case CPUMUNKNOWNCPUID_END:
1576	case CPUMUNKNOWNCPUID_32BIT_HACK:
1577	break;
1578	}
1579	return "Invalid-unknown-CPUID-method";
1580	}
1581
1582
1583	/**
1584	* Detect the CPU vendor give n the
1585	*
1586	* @returns The vendor.
1587	* @param uEAX EAX from CPUID(0).
1588	* @param uEBX EBX from CPUID(0).
1589	* @param uECX ECX from CPUID(0).
1590	* @param uEDX EDX from CPUID(0).
1591	*/
1592	VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1593	{
1594	if (ASMIsValidStdRange(uEAX))
1595	{
1596	if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1597	return CPUMCPUVENDOR_AMD;
1598
1599	if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1600	return CPUMCPUVENDOR_INTEL;
1601
1602	if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1603	return CPUMCPUVENDOR_VIA;
1604
1605	if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1606	&& uECX == UINT32_C(0x64616574)
1607	&& uEDX == UINT32_C(0x736E4978))
1608	return CPUMCPUVENDOR_CYRIX;
1609
1610	/* "Geode by NSC", example: family 5, model 9. */
1611
1612	/** @todo detect the other buggers... */
1613	}
1614
1615	return CPUMCPUVENDOR_UNKNOWN;
1616	}
1617
1618
1619	/**
1620	* Translates a CPU vendor enum value into the corresponding string constant.
1621	*
1622	* The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1623	* value name. This can be useful when generating code.
1624	*
1625	* @returns Read only name string.
1626	* @param enmVendor The CPU vendor value.
1627	*/
1628	VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1629	{
1630	switch (enmVendor)
1631	{
1632	case CPUMCPUVENDOR_INTEL: return "INTEL";
1633	case CPUMCPUVENDOR_AMD: return "AMD";
1634	case CPUMCPUVENDOR_VIA: return "VIA";
1635	case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1636	case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1637
1638	case CPUMCPUVENDOR_INVALID:
1639	case CPUMCPUVENDOR_32BIT_HACK:
1640	break;
1641	}
1642	return "Invalid-cpu-vendor";
1643	}
1644
1645
1646	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1647	{
1648	/* Could do binary search, doing linear now because I'm lazy. */
1649	PCCPUMCPUIDLEAF pLeaf = paLeaves;
1650	while (cLeaves-- > 0)
1651	{
1652	if (pLeaf->uLeaf == uLeaf)
1653	return pLeaf;
1654	pLeaf++;
1655	}
1656	return NULL;
1657	}
1658
1659
1660	static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeafEx(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
1661	{
1662	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, uLeaf);
1663	if ( !pLeaf
1664	\|\| pLeaf->uSubLeaf != (uSubLeaf & pLeaf->fSubLeafMask))
1665	return pLeaf;
1666
1667	/* Linear sub-leaf search. Lazy as usual. */
1668	cLeaves -= pLeaf - paLeaves;
1669	while ( cLeaves-- > 0
1670	&& pLeaf->uLeaf == uLeaf)
1671	{
1672	if (pLeaf->uSubLeaf == (uSubLeaf & pLeaf->fSubLeafMask))
1673	return pLeaf;
1674	pLeaf++;
1675	}
1676
1677	return NULL;
1678	}
1679
1680
1681	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1682	{
1683	RT_ZERO(*pFeatures);
1684	if (cLeaves >= 2)
1685	{
1686	AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1687	AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1688	PCCPUMCPUIDLEAF const pStd0Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 0, 0);
1689	AssertLogRelReturn(pStd0Leaf, VERR_CPUM_IPE_1);
1690	PCCPUMCPUIDLEAF const pStd1Leaf = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 1, 0);
1691	AssertLogRelReturn(pStd1Leaf, VERR_CPUM_IPE_1);
1692
1693	pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(pStd0Leaf->uEax,
1694	pStd0Leaf->uEbx,
1695	pStd0Leaf->uEcx,
1696	pStd0Leaf->uEdx);
1697	pFeatures->uFamily = ASMGetCpuFamily(pStd1Leaf->uEax);
1698	pFeatures->uModel = ASMGetCpuModel(pStd1Leaf->uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1699	pFeatures->uStepping = ASMGetCpuStepping(pStd1Leaf->uEax);
1700	pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1701	pFeatures->uFamily,
1702	pFeatures->uModel,
1703	pFeatures->uStepping);
1704
1705	PCCPUMCPUIDLEAF const pExtLeaf8 = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1706	if (pExtLeaf8)
1707	pFeatures->cMaxPhysAddrWidth = pExtLeaf8->uEax & 0xff;
1708	else if (pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1709	pFeatures->cMaxPhysAddrWidth = 36;
1710	else
1711	pFeatures->cMaxPhysAddrWidth = 32;
1712
1713	/* Standard features. */
1714	pFeatures->fMsr = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MSR);
1715	pFeatures->fApic = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_APIC);
1716	pFeatures->fX2Apic = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1717	pFeatures->fPse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE);
1718	pFeatures->fPse36 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1719	pFeatures->fPae = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAE);
1720	pFeatures->fPat = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_PAT);
1721	pFeatures->fFxSaveRstor = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1722	pFeatures->fXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE);
1723	pFeatures->fOpSysXSaveRstor = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_OSXSAVE);
1724	pFeatures->fMmx = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_MMX);
1725	pFeatures->fSse = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE);
1726	pFeatures->fSse2 = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SSE2);
1727	pFeatures->fSse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE3);
1728	pFeatures->fSsse3 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSSE3);
1729	pFeatures->fSse41 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_1);
1730	pFeatures->fSse42 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_SSE4_2);
1731	pFeatures->fAvx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_AVX);
1732	pFeatures->fTsc = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_TSC);
1733	pFeatures->fSysEnter = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_SEP);
1734	pFeatures->fHypervisorPresent = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_HVP);
1735	pFeatures->fMonitorMWait = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1736	pFeatures->fMovCmpXchg16b = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_CX16);
1737	pFeatures->fClFlush = RT_BOOL(pStd1Leaf->uEdx & X86_CPUID_FEATURE_EDX_CLFSH);
1738	pFeatures->fPcid = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
1739	pFeatures->fVmx = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
1740	if (pFeatures->fVmx)
1741	{ /** @todo Support other VMX features */ }
1742
1743	/* Structured extended features. */
1744	PCCPUMCPUIDLEAF const pSxfLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 7, 0);
1745	if (pSxfLeaf0)
1746	{
1747	pFeatures->fFsGsBase = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
1748	pFeatures->fAvx2 = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2);
1749	pFeatures->fAvx512Foundation = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1750	pFeatures->fClFlushOpt = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT);
1751	pFeatures->fInvpcid = RT_BOOL(pSxfLeaf0->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID);
1752
1753	pFeatures->fIbpb = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB);
1754	pFeatures->fIbrs = pFeatures->fIbpb;
1755	pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
1756	#if 0 // Disabled until IA32_ARCH_CAPABILITIES support can be tested
1757	pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
1758	#endif
1759	}
1760
1761	/* MWAIT/MONITOR leaf. */
1762	PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
1763	if (pMWaitLeaf)
1764	{
1765	pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1766	== (X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
1767	}
1768
1769	/* Extended features. */
1770	PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1771	if (pExtLeaf)
1772	{
1773	pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1774	pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1775	pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1776	pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1777	pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1778	pFeatures->fMovCr8In32Bit = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_CMPL);
1779	pFeatures->f3DNow = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1780	pFeatures->f3DNowPrefetch = (pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1781	\|\| (pExtLeaf->uEdx & ( X86_CPUID_EXT_FEATURE_EDX_LONG_MODE
1782	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW));
1783	}
1784
1785	if ( pExtLeaf
1786	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1787	{
1788	/* AMD features. */
1789	pFeatures->fMsr \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1790	pFeatures->fApic \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1791	pFeatures->fPse \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1792	pFeatures->fPse36 \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1793	pFeatures->fPae \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1794	pFeatures->fPat \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1795	pFeatures->fFxSaveRstor \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1796	pFeatures->fMmx \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
1797	pFeatures->fTsc \|= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
1798	pFeatures->fIbpb \|= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
1799	pFeatures->fAmdMmxExts = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1800	pFeatures->fXop = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
1801	pFeatures->fSvm = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
1802	if (pFeatures->fSvm)
1803	{
1804	PCCPUMCPUIDLEAF pSvmLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x8000000a);
1805	AssertLogRelReturn(pSvmLeaf, VERR_CPUM_IPE_1);
1806	pFeatures->fSvmNestedPaging = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING);
1807	pFeatures->fSvmLbrVirt = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1808	pFeatures->fSvmSvmLock = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK);
1809	pFeatures->fSvmNextRipSave = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
1810	pFeatures->fSvmTscRateMsr = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR);
1811	pFeatures->fSvmVmcbClean = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
1812	pFeatures->fSvmFlusbByAsid = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID);
1813	pFeatures->fSvmDecodeAssists = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
1814	pFeatures->fSvmPauseFilter = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1815	pFeatures->fSvmPauseFilterThreshold = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1816	pFeatures->fSvmAvic = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_AVIC);
1817	pFeatures->fSvmVirtVmsaveVmload = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1818	pFeatures->fSvmVGif = RT_BOOL(pSvmLeaf->uEdx & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1819	pFeatures->uSvmMaxAsid = pSvmLeaf->uEbx;
1820	}
1821	}
1822
1823	/*
1824	* Quirks.
1825	*/
1826	pFeatures->fLeakyFxSR = pExtLeaf
1827	&& (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1828	&& pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1829	&& pFeatures->uFamily >= 6 /* K7 and up */;
1830
1831	/*
1832	* Max extended (/FPU) state.
1833	*/
1834	pFeatures->cbMaxExtendedState = pFeatures->fFxSaveRstor ? sizeof(X86FXSTATE) : sizeof(X86FPUSTATE);
1835	if (pFeatures->fXSaveRstor)
1836	{
1837	PCCPUMCPUIDLEAF const pXStateLeaf0 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 0);
1838	if (pXStateLeaf0)
1839	{
1840	if ( pXStateLeaf0->uEcx >= sizeof(X86FXSTATE)
1841	&& pXStateLeaf0->uEcx <= CPUM_MAX_XSAVE_AREA_SIZE
1842	&& RT_ALIGN_32(pXStateLeaf0->uEcx, 8) == pXStateLeaf0->uEcx
1843	&& pXStateLeaf0->uEbx >= sizeof(X86FXSTATE)
1844	&& pXStateLeaf0->uEbx <= pXStateLeaf0->uEcx
1845	&& RT_ALIGN_32(pXStateLeaf0->uEbx, 8) == pXStateLeaf0->uEbx)
1846	{
1847	pFeatures->cbMaxExtendedState = pXStateLeaf0->uEcx;
1848
1849	/* (paranoia:) */
1850	PCCPUMCPUIDLEAF const pXStateLeaf1 = cpumR3CpuIdFindLeafEx(paLeaves, cLeaves, 13, 1);
1851	if ( pXStateLeaf1
1852	&& pXStateLeaf1->uEbx > pFeatures->cbMaxExtendedState
1853	&& pXStateLeaf1->uEbx <= CPUM_MAX_XSAVE_AREA_SIZE
1854	&& (pXStateLeaf1->uEcx \|\| pXStateLeaf1->uEdx) )
1855	pFeatures->cbMaxExtendedState = pXStateLeaf1->uEbx;
1856	}
1857	else
1858	AssertLogRelMsgFailedStmt(("Unexpected max/cur XSAVE area sizes: %#x/%#x\n", pXStateLeaf0->uEcx, pXStateLeaf0->uEbx),
1859	pFeatures->fXSaveRstor = 0);
1860	}
1861	else
1862	AssertLogRelMsgFailedStmt(("Expected leaf eax=0xd/ecx=0 with the XSAVE/XRSTOR feature!\n"),
1863	pFeatures->fXSaveRstor = 0);
1864	}
1865	}
1866	else
1867	AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1868	return VINF_SUCCESS;
1869	}
1870
1871
1872	/*
1873	*
1874	* Init related code.
1875	* Init related code.
1876	* Init related code.
1877	*
1878	*
1879	*/
1880	#ifdef VBOX_IN_VMM
1881
1882
1883	/**
1884	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
1885	*
1886	* This ignores the fSubLeafMask.
1887	*
1888	* @returns Pointer to the matching leaf, or NULL if not found.
1889	* @param paLeaves The CPUID leaves to search. This is sorted.
1890	* @param cLeaves The number of leaves in the array.
1891	* @param uLeaf The leaf to locate.
1892	* @param uSubLeaf The subleaf to locate.
1893	*/
1894	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
1895	{
1896	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
1897	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
1898	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
1899	if (iEnd)
1900	{
1901	uint32_t iBegin = 0;
1902	for (;;)
1903	{
1904	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
1905	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
1906	if (uNeedle < uCur)
1907	{
1908	if (i > iBegin)
1909	iEnd = i;
1910	else
1911	break;
1912	}
1913	else if (uNeedle > uCur)
1914	{
1915	if (i + 1 < iEnd)
1916	iBegin = i + 1;
1917	else
1918	break;
1919	}
1920	else
1921	return &paLeaves[i];
1922	}
1923	}
1924	return NULL;
1925	}
1926
1927
1928	/**
1929	* Loads MSR range overrides.
1930	*
1931	* This must be called before the MSR ranges are moved from the normal heap to
1932	* the hyper heap!
1933	*
1934	* @returns VBox status code (VMSetError called).
1935	* @param pVM The cross context VM structure.
1936	* @param pMsrNode The CFGM node with the MSR overrides.
1937	*/
1938	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
1939	{
1940	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
1941	{
1942	/*
1943	* Assemble a valid MSR range.
1944	*/
1945	CPUMMSRRANGE MsrRange;
1946	MsrRange.offCpumCpu = 0;
1947	MsrRange.fReserved = 0;
1948
1949	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
1950	if (RT_FAILURE(rc))
1951	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
1952
1953	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
1954	if (RT_FAILURE(rc))
1955	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
1956	MsrRange.szName, rc);
1957
1958	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
1959	if (RT_FAILURE(rc))
1960	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
1961	MsrRange.szName, rc);
1962
1963	char szType[32];
1964	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
1965	if (RT_FAILURE(rc))
1966	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
1967	MsrRange.szName, rc);
1968	if (!RTStrICmp(szType, "FixedValue"))
1969	{
1970	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
1971	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
1972
1973	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
1974	if (RT_FAILURE(rc))
1975	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
1976	MsrRange.szName, rc);
1977
1978	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
1979	if (RT_FAILURE(rc))
1980	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
1981	MsrRange.szName, rc);
1982
1983	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
1984	if (RT_FAILURE(rc))
1985	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
1986	MsrRange.szName, rc);
1987	}
1988	else
1989	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1990	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
1991
1992	/*
1993	* Insert the range into the table (replaces/splits/shrinks existing
1994	* MSR ranges).
1995	*/
1996	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
1997	&MsrRange);
1998	if (RT_FAILURE(rc))
1999	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
2000	}
2001
2002	return VINF_SUCCESS;
2003	}
2004
2005
2006	/**
2007	* Loads CPUID leaf overrides.
2008	*
2009	* This must be called before the CPUID leaves are moved from the normal
2010	* heap to the hyper heap!
2011	*
2012	* @returns VBox status code (VMSetError called).
2013	* @param pVM The cross context VM structure.
2014	* @param pParentNode The CFGM node with the CPUID leaves.
2015	* @param pszLabel How to label the overrides we're loading.
2016	*/
2017	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
2018	{
2019	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
2020	{
2021	/*
2022	* Get the leaf and subleaf numbers.
2023	*/
2024	char szName[128];
2025	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
2026	if (RT_FAILURE(rc))
2027	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
2028
2029	/* The leaf number is either specified directly or thru the node name. */
2030	uint32_t uLeaf;
2031	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
2032	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2033	{
2034	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
2035	if (rc != VINF_SUCCESS)
2036	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
2037	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
2038	}
2039	else if (RT_FAILURE(rc))
2040	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
2041	pszLabel, szName, rc);
2042
2043	uint32_t uSubLeaf;
2044	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
2045	if (RT_FAILURE(rc))
2046	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
2047	pszLabel, szName, rc);
2048
2049	uint32_t fSubLeafMask;
2050	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
2051	if (RT_FAILURE(rc))
2052	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
2053	pszLabel, szName, rc);
2054
2055	/*
2056	* Look up the specified leaf, since the output register values
2057	* defaults to any existing values. This allows overriding a single
2058	* register, without needing to know the other values.
2059	*/
2060	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
2061	CPUMCPUIDLEAF Leaf;
2062	if (pLeaf)
2063	Leaf = *pLeaf;
2064	else
2065	RT_ZERO(Leaf);
2066	Leaf.uLeaf = uLeaf;
2067	Leaf.uSubLeaf = uSubLeaf;
2068	Leaf.fSubLeafMask = fSubLeafMask;
2069
2070	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
2071	if (RT_FAILURE(rc))
2072	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
2073	pszLabel, szName, rc);
2074	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
2075	if (RT_FAILURE(rc))
2076	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
2077	pszLabel, szName, rc);
2078	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
2079	if (RT_FAILURE(rc))
2080	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
2081	pszLabel, szName, rc);
2082	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
2083	if (RT_FAILURE(rc))
2084	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
2085	pszLabel, szName, rc);
2086
2087	/*
2088	* Insert the leaf into the table (replaces existing ones).
2089	*/
2090	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
2091	&Leaf);
2092	if (RT_FAILURE(rc))
2093	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
2094	}
2095
2096	return VINF_SUCCESS;
2097	}
2098
2099
2100
2101	/**
2102	* Fetches overrides for a CPUID leaf.
2103	*
2104	* @returns VBox status code.
2105	* @param pLeaf The leaf to load the overrides into.
2106	* @param pCfgNode The CFGM node containing the overrides
2107	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2108	* @param iLeaf The CPUID leaf number.
2109	*/
2110	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
2111	{
2112	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
2113	if (pLeafNode)
2114	{
2115	uint32_t u32;
2116	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
2117	if (RT_SUCCESS(rc))
2118	pLeaf->uEax = u32;
2119	else
2120	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2121
2122	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
2123	if (RT_SUCCESS(rc))
2124	pLeaf->uEbx = u32;
2125	else
2126	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2127
2128	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
2129	if (RT_SUCCESS(rc))
2130	pLeaf->uEcx = u32;
2131	else
2132	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2133
2134	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
2135	if (RT_SUCCESS(rc))
2136	pLeaf->uEdx = u32;
2137	else
2138	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
2139
2140	}
2141	return VINF_SUCCESS;
2142	}
2143
2144
2145	/**
2146	* Load the overrides for a set of CPUID leaves.
2147	*
2148	* @returns VBox status code.
2149	* @param paLeaves The leaf array.
2150	* @param cLeaves The number of leaves.
2151	* @param uStart The start leaf number.
2152	* @param pCfgNode The CFGM node containing the overrides
2153	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
2154	*/
2155	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
2156	{
2157	for (uint32_t i = 0; i < cLeaves; i++)
2158	{
2159	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
2160	if (RT_FAILURE(rc))
2161	return rc;
2162	}
2163
2164	return VINF_SUCCESS;
2165	}
2166
2167
2168	/**
2169	* Installs the CPUID leaves and explods the data into structures like
2170	* GuestFeatures and CPUMCTX::aoffXState.
2171	*
2172	* @returns VBox status code.
2173	* @param pVM The cross context VM structure.
2174	* @param pCpum The CPUM part of @a VM.
2175	* @param paLeaves The leaves. These will be copied (but not freed).
2176	* @param cLeaves The number of leaves.
2177	*/
2178	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
2179	{
2180	cpumR3CpuIdAssertOrder(paLeaves, cLeaves);
2181
2182	/*
2183	* Install the CPUID information.
2184	*/
2185	int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
2186	MM_TAG_CPUM_CPUID, (void **)&pCpum->GuestInfo.paCpuIdLeavesR3);
2187
2188	AssertLogRelRCReturn(rc, rc);
2189	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
2190	pCpum->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2191	pCpum->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paCpuIdLeavesR3);
2192	Assert(MMHyperR0ToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesR0) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2193	Assert(MMHyperRCToR3(pVM, pCpum->GuestInfo.paCpuIdLeavesRC) == (void *)pCpum->GuestInfo.paCpuIdLeavesR3);
2194
2195	/*
2196	* Update the default CPUID leaf if necessary.
2197	*/
2198	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
2199	{
2200	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
2201	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
2202	{
2203	/* We don't use CPUID(0).eax here because of the NT hack that only
2204	changes that value without actually removing any leaves. */
2205	uint32_t i = 0;
2206	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
2207	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
2208	{
2209	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
2210	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
2211	i++;
2212	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
2213	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
2214	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
2215	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
2216	}
2217	break;
2218	}
2219	default:
2220	break;
2221	}
2222
2223	/*
2224	* Explode the guest CPU features.
2225	*/
2226	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
2227	AssertLogRelRCReturn(rc, rc);
2228
2229	/*
2230	* Adjust the scalable bus frequency according to the CPUID information
2231	* we're now using.
2232	*/
2233	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
2234	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
2235	? UINT64_C(100000000) /* 100MHz */
2236	: UINT64_C(133333333); /* 133MHz */
2237
2238	/*
2239	* Populate the legacy arrays. Currently used for everything, later only
2240	* for patch manager.
2241	*/
2242	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
2243	{
2244	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
2245	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
2246	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
2247	};
2248	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
2249	{
2250	uint32_t cLeft = aOldRanges[i].cCpuIds;
2251	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
2252	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
2253	while (cLeft-- > 0)
2254	{
2255	uLeaf--;
2256	pLegacyLeaf--;
2257
2258	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
2259	if (pLeaf)
2260	{
2261	pLegacyLeaf->uEax = pLeaf->uEax;
2262	pLegacyLeaf->uEbx = pLeaf->uEbx;
2263	pLegacyLeaf->uEcx = pLeaf->uEcx;
2264	pLegacyLeaf->uEdx = pLeaf->uEdx;
2265	}
2266	else
2267	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
2268	}
2269	}
2270
2271	/*
2272	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
2273	*/
2274	memset(&pVM->aCpus[0].cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Guest.aoffXState));
2275	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
2276	pVM->aCpus[0].cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
2277	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
2278	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
2279	{
2280	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
2281	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2282	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
2283	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
2284	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2285	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
2286	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
2287	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
2288	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
2289	pCpum->GuestFeatures.cbMaxExtendedState),
2290	VERR_CPUM_IPE_1);
2291	pVM->aCpus[0].cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
2292	}
2293	memset(&pVM->aCpus[0].cpum.s.Hyper.aoffXState[0], 0xff, sizeof(pVM->aCpus[0].cpum.s.Hyper.aoffXState));
2294
2295	/* Copy the CPU #0 data to the other CPUs. */
2296	for (VMCPUID iCpu = 1; iCpu < pVM->cCpus; iCpu++)
2297	{
2298	memcpy(&pVM->aCpus[iCpu].cpum.s.Guest.aoffXState[0], &pVM->aCpus[0].cpum.s.Guest.aoffXState[0],
2299	sizeof(pVM->aCpus[iCpu].cpum.s.Guest.aoffXState));
2300	memcpy(&pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState[0], &pVM->aCpus[0].cpum.s.Hyper.aoffXState[0],
2301	sizeof(pVM->aCpus[iCpu].cpum.s.Hyper.aoffXState));
2302	}
2303
2304	return VINF_SUCCESS;
2305	}
2306
2307
2308	/** @name Instruction Set Extension Options
2309	* @{ */
2310	/** Configuration option type (extended boolean, really). */
2311	typedef uint8_t CPUMISAEXTCFG;
2312	/** Always disable the extension. */
2313	#define CPUMISAEXTCFG_DISABLED false
2314	/** Enable the extension if it's supported by the host CPU. */
2315	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
2316	/** Enable the extension if it's supported by the host CPU, but don't let
2317	* the portable CPUID feature disable it. */
2318	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
2319	/** Always enable the extension. */
2320	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
2321	/** @} */
2322
2323	/**
2324	* CPUID Configuration (from CFGM).
2325	*
2326	* @remarks The members aren't document since we would only be duplicating the
2327	* \@cfgm entries in cpumR3CpuIdReadConfig.
2328	*/
2329	typedef struct CPUMCPUIDCONFIG
2330	{
2331	bool fNt4LeafLimit;
2332	bool fInvariantTsc;
2333	bool fForceVme;
2334	bool fNestedHWVirt;
2335
2336	CPUMISAEXTCFG enmCmpXchg16b;
2337	CPUMISAEXTCFG enmMonitor;
2338	CPUMISAEXTCFG enmMWaitExtensions;
2339	CPUMISAEXTCFG enmSse41;
2340	CPUMISAEXTCFG enmSse42;
2341	CPUMISAEXTCFG enmAvx;
2342	CPUMISAEXTCFG enmAvx2;
2343	CPUMISAEXTCFG enmXSave;
2344	CPUMISAEXTCFG enmAesNi;
2345	CPUMISAEXTCFG enmPClMul;
2346	CPUMISAEXTCFG enmPopCnt;
2347	CPUMISAEXTCFG enmMovBe;
2348	CPUMISAEXTCFG enmRdRand;
2349	CPUMISAEXTCFG enmRdSeed;
2350	CPUMISAEXTCFG enmCLFlushOpt;
2351	CPUMISAEXTCFG enmFsGsBase;
2352	CPUMISAEXTCFG enmPcid;
2353	CPUMISAEXTCFG enmInvpcid;
2354
2355	CPUMISAEXTCFG enmAbm;
2356	CPUMISAEXTCFG enmSse4A;
2357	CPUMISAEXTCFG enmMisAlnSse;
2358	CPUMISAEXTCFG enm3dNowPrf;
2359	CPUMISAEXTCFG enmAmdExtMmx;
2360
2361	uint32_t uMaxStdLeaf;
2362	uint32_t uMaxExtLeaf;
2363	uint32_t uMaxCentaurLeaf;
2364	uint32_t uMaxIntelFamilyModelStep;
2365	char szCpuName[128];
2366	} CPUMCPUIDCONFIG;
2367	/** Pointer to CPUID config (from CFGM). */
2368	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
2369
2370
2371	/**
2372	* Mini CPU selection support for making Mac OS X happy.
2373	*
2374	* Executes the /CPUM/MaxIntelFamilyModelStep config.
2375	*
2376	* @param pCpum The CPUM instance data.
2377	* @param pConfig The CPUID configuration we've read from CFGM.
2378	*/
2379	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2380	{
2381	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
2382	{
2383	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2384	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
2385	ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
2386	ASMGetCpuFamily(pStdFeatureLeaf->uEax),
2387	0);
2388	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
2389	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
2390	{
2391	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
2392	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
2393	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
2394	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
2395	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
2396	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
2397	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
2398	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
2399	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
2400	pStdFeatureLeaf->uEax = uNew;
2401	}
2402	}
2403	}
2404
2405
2406
2407	/**
2408	* Limit it the number of entries, zapping the remainder.
2409	*
2410	* The limits are masking off stuff about power saving and similar, this
2411	* is perhaps a bit crudely done as there is probably some relatively harmless
2412	* info too in these leaves (like words about having a constant TSC).
2413	*
2414	* @param pCpum The CPUM instance data.
2415	* @param pConfig The CPUID configuration we've read from CFGM.
2416	*/
2417	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2418	{
2419	/*
2420	* Standard leaves.
2421	*/
2422	uint32_t uSubLeaf = 0;
2423	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
2424	if (pCurLeaf)
2425	{
2426	uint32_t uLimit = pCurLeaf->uEax;
2427	if (uLimit <= UINT32_C(0x000fffff))
2428	{
2429	if (uLimit > pConfig->uMaxStdLeaf)
2430	{
2431	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
2432	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2433	uLimit + 1, UINT32_C(0x000fffff));
2434	}
2435
2436	/* NT4 hack, no zapping of extra leaves here. */
2437	if (pConfig->fNt4LeafLimit && uLimit > 3)
2438	pCurLeaf->uEax = uLimit = 3;
2439
2440	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
2441	pCurLeaf->uEax = uLimit;
2442	}
2443	else
2444	{
2445	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
2446	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2447	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
2448	}
2449	}
2450
2451	/*
2452	* Extended leaves.
2453	*/
2454	uSubLeaf = 0;
2455	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
2456	if (pCurLeaf)
2457	{
2458	uint32_t uLimit = pCurLeaf->uEax;
2459	if ( uLimit >= UINT32_C(0x80000000)
2460	&& uLimit <= UINT32_C(0x800fffff))
2461	{
2462	if (uLimit > pConfig->uMaxExtLeaf)
2463	{
2464	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
2465	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2466	uLimit + 1, UINT32_C(0x800fffff));
2467	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
2468	pCurLeaf->uEax = uLimit;
2469	}
2470	}
2471	else
2472	{
2473	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
2474	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2475	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
2476	}
2477	}
2478
2479	/*
2480	* Centaur leaves (VIA).
2481	*/
2482	uSubLeaf = 0;
2483	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
2484	if (pCurLeaf)
2485	{
2486	uint32_t uLimit = pCurLeaf->uEax;
2487	if ( uLimit >= UINT32_C(0xc0000000)
2488	&& uLimit <= UINT32_C(0xc00fffff))
2489	{
2490	if (uLimit > pConfig->uMaxCentaurLeaf)
2491	{
2492	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
2493	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2494	uLimit + 1, UINT32_C(0xcfffffff));
2495	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
2496	pCurLeaf->uEax = uLimit;
2497	}
2498	}
2499	else
2500	{
2501	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
2502	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2503	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
2504	}
2505	}
2506	}
2507
2508
2509	/**
2510	* Clears a CPUID leaf and all sub-leaves (to zero).
2511	*
2512	* @param pCpum The CPUM instance data.
2513	* @param uLeaf The leaf to clear.
2514	*/
2515	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
2516	{
2517	uint32_t uSubLeaf = 0;
2518	PCPUMCPUIDLEAF pCurLeaf;
2519	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
2520	{
2521	pCurLeaf->uEax = 0;
2522	pCurLeaf->uEbx = 0;
2523	pCurLeaf->uEcx = 0;
2524	pCurLeaf->uEdx = 0;
2525	uSubLeaf++;
2526	}
2527	}
2528
2529
2530	/**
2531	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
2532	* the given leaf.
2533	*
2534	* @returns pLeaf.
2535	* @param pCpum The CPUM instance data.
2536	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
2537	*/
2538	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
2539	{
2540	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
2541	if (pLeaf->fSubLeafMask != 0)
2542	{
2543	/*
2544	* Figure out how many sub-leaves in need of removal (we'll keep the first).
2545	* Log everything while we're at it.
2546	*/
2547	LogRel(("CPUM:\n"
2548	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
2549	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
2550	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
2551	for (;;)
2552	{
2553	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
2554	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
2555	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
2556	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
2557	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
2558	break;
2559	pSubLeaf++;
2560	}
2561	LogRel(("CPUM:\n"));
2562
2563	/*
2564	* Remove the offending sub-leaves.
2565	*/
2566	if (pSubLeaf != pLeaf)
2567	{
2568	if (pSubLeaf != pLast)
2569	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
2570	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
2571	}
2572
2573	/*
2574	* Convert the first sub-leaf into a single leaf.
2575	*/
2576	pLeaf->uSubLeaf = 0;
2577	pLeaf->fSubLeafMask = 0;
2578	}
2579	return pLeaf;
2580	}
2581
2582
2583	/**
2584	* Sanitizes and adjust the CPUID leaves.
2585	*
2586	* Drop features that aren't virtualized (or virtualizable). Adjust information
2587	* and capabilities to fit the virtualized hardware. Remove information the
2588	* guest shouldn't have (because it's wrong in the virtual world or because it
2589	* gives away host details) or that we don't have documentation for and no idea
2590	* what means.
2591	*
2592	* @returns VBox status code.
2593	* @param pVM The cross context VM structure (for cCpus).
2594	* @param pCpum The CPUM instance data.
2595	* @param pConfig The CPUID configuration we've read from CFGM.
2596	*/
2597	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
2598	{
2599	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
2600	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
2601	{ \
2602	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
2603	(a_pLeafReg) &= ~(uint32_t)(fMask); \
2604	}
2605	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
2606	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
2607	{ \
2608	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2609	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2610	}
2611	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
2612	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
2613	&& ((a_pLeafReg) & (fBitMask)) \
2614	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
2615	{ \
2616	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
2617	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
2618	}
2619	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
2620
2621	/* Cpuid 1:
2622	* EAX: CPU model, family and stepping.
2623	*
2624	* ECX + EDX: Supported features. Only report features we can support.
2625	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2626	* options may require adjusting (i.e. stripping what was enabled).
2627	*
2628	* EBX: Branding, CLFLUSH line size, logical processors per package and
2629	* initial APIC ID.
2630	*/
2631	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
2632	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
2633	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
2634
2635	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
2636	\| X86_CPUID_FEATURE_EDX_VME
2637	\| X86_CPUID_FEATURE_EDX_DE
2638	\| X86_CPUID_FEATURE_EDX_PSE
2639	\| X86_CPUID_FEATURE_EDX_TSC
2640	\| X86_CPUID_FEATURE_EDX_MSR
2641	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
2642	\| X86_CPUID_FEATURE_EDX_MCE
2643	\| X86_CPUID_FEATURE_EDX_CX8
2644	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
2645	//\| RT_BIT_32(10) - not defined
2646	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
2647	//\| X86_CPUID_FEATURE_EDX_SEP
2648	\| X86_CPUID_FEATURE_EDX_MTRR
2649	\| X86_CPUID_FEATURE_EDX_PGE
2650	\| X86_CPUID_FEATURE_EDX_MCA
2651	\| X86_CPUID_FEATURE_EDX_CMOV
2652	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
2653	\| X86_CPUID_FEATURE_EDX_PSE36
2654	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
2655	\| X86_CPUID_FEATURE_EDX_CLFSH
2656	//\| RT_BIT_32(20) - not defined
2657	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
2658	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
2659	\| X86_CPUID_FEATURE_EDX_MMX
2660	\| X86_CPUID_FEATURE_EDX_FXSR
2661	\| X86_CPUID_FEATURE_EDX_SSE
2662	\| X86_CPUID_FEATURE_EDX_SSE2
2663	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
2664	\| X86_CPUID_FEATURE_EDX_HTT
2665	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
2666	//\| RT_BIT_32(30) - not defined
2667	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
2668	;
2669	pStdFeatureLeaf->uEcx &= 0
2670	\| X86_CPUID_FEATURE_ECX_SSE3
2671	\| (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0)
2672	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
2673	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
2674	\| ((pConfig->enmMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
2675	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
2676	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
2677	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
2678	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
2679	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
2680	\| X86_CPUID_FEATURE_ECX_SSSE3
2681	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
2682	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
2683	\| (pConfig->enmCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
2684	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
2685	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2686	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
2687	\| (pConfig->enmPcid ? X86_CPUID_FEATURE_ECX_PCID : 0)
2688	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
2689	\| (pConfig->enmSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
2690	\| (pConfig->enmSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
2691	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
2692	\| (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0)
2693	\| (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0)
2694	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
2695	\| (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0)
2696	\| (pConfig->enmXSave ? X86_CPUID_FEATURE_ECX_XSAVE : 0 )
2697	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
2698	\| (pConfig->enmAvx ? X86_CPUID_FEATURE_ECX_AVX : 0)
2699	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
2700	\| (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0)
2701	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
2702	;
2703
2704	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
2705	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
2706	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
2707	{
2708	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
2709	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
2710	}
2711
2712	if (pCpum->u8PortableCpuIdLevel > 0)
2713	{
2714	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
2715	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
2716	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
2717	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
2718	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
2719	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
2720	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
2721	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
2722	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
2723	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
2724	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
2725	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
2726	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
2727	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
2728	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
2729	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
2730	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
2731	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
2732	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
2733	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
2734
2735	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
2736	\| X86_CPUID_FEATURE_EDX_PSN
2737	\| X86_CPUID_FEATURE_EDX_DS
2738	\| X86_CPUID_FEATURE_EDX_ACPI
2739	\| X86_CPUID_FEATURE_EDX_SS
2740	\| X86_CPUID_FEATURE_EDX_TM
2741	\| X86_CPUID_FEATURE_EDX_PBE
2742	)));
2743	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
2744	\| X86_CPUID_FEATURE_ECX_CPLDS
2745	\| X86_CPUID_FEATURE_ECX_AES
2746	\| X86_CPUID_FEATURE_ECX_VMX
2747	\| X86_CPUID_FEATURE_ECX_SMX
2748	\| X86_CPUID_FEATURE_ECX_EST
2749	\| X86_CPUID_FEATURE_ECX_TM2
2750	\| X86_CPUID_FEATURE_ECX_CNTXID
2751	\| X86_CPUID_FEATURE_ECX_FMA
2752	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2753	\| X86_CPUID_FEATURE_ECX_PDCM
2754	\| X86_CPUID_FEATURE_ECX_DCA
2755	\| X86_CPUID_FEATURE_ECX_OSXSAVE
2756	)));
2757	}
2758
2759	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
2760	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
2761
2762	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
2763	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
2764	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
2765	*/
2766	#ifdef VBOX_WITH_MULTI_CORE
2767	if (pVM->cCpus > 1)
2768	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
2769	#endif
2770	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
2771	{
2772	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
2773	core times the number of CPU cores per processor */
2774	#ifdef VBOX_WITH_MULTI_CORE
2775	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
2776	#else
2777	/* Single logical processor in a package. */
2778	pStdFeatureLeaf->uEbx \|= (1 << 16);
2779	#endif
2780	}
2781
2782	uint32_t uMicrocodeRev;
2783	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
2784	if (RT_SUCCESS(rc))
2785	{
2786	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
2787	}
2788	else
2789	{
2790	uMicrocodeRev = 0;
2791	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
2792	}
2793
2794	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
2795	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
2796	*/
2797	if ( (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen)
2798	&& uMicrocodeRev < 0x8001126
2799	&& !pConfig->fForceVme)
2800	{
2801	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
2802	LogRel(("CPUM: Zen VME workaround engaged\n"));
2803	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
2804	}
2805
2806	/* Force standard feature bits. */
2807	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
2808	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
2809	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
2810	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
2811	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
2812	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
2813	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2814	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
2815	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
2816	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
2817	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
2818	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
2819	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
2820	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
2821	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
2822	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
2823	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
2824	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
2825	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2826	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
2827	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
2828	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
2829
2830	pStdFeatureLeaf = NULL; /* Must refetch! */
2831
2832	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
2833	* AMD:
2834	* EAX: CPU model, family and stepping.
2835	*
2836	* ECX + EDX: Supported features. Only report features we can support.
2837	* Note! When enabling new features the Synthetic CPU and Portable CPUID
2838	* options may require adjusting (i.e. stripping what was enabled).
2839	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
2840	*
2841	* EBX: Branding ID and package type (or reserved).
2842	*
2843	* Intel and probably most others:
2844	* EAX: 0
2845	* EBX: 0
2846	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
2847	*/
2848	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2849	if (pExtFeatureLeaf)
2850	{
2851	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
2852
2853	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
2854	\| X86_CPUID_AMD_FEATURE_EDX_VME
2855	\| X86_CPUID_AMD_FEATURE_EDX_DE
2856	\| X86_CPUID_AMD_FEATURE_EDX_PSE
2857	\| X86_CPUID_AMD_FEATURE_EDX_TSC
2858	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
2859	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
2860	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
2861	\| X86_CPUID_AMD_FEATURE_EDX_CX8
2862	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
2863	//\| RT_BIT_32(10) - reserved
2864	/* Note! We don't report sysenter/sysexit support due to our inability to keep the IOPL part of
2865	eflags in sync while in ring 1 (see @bugref{1757}). HM enables them later. */
2866	//\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2867	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
2868	\| X86_CPUID_AMD_FEATURE_EDX_PGE
2869	\| X86_CPUID_AMD_FEATURE_EDX_MCA
2870	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
2871	\| X86_CPUID_AMD_FEATURE_EDX_PAT
2872	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
2873	//\| RT_BIT_32(18) - reserved
2874	//\| RT_BIT_32(19) - reserved
2875	//\| X86_CPUID_EXT_FEATURE_EDX_NX - enabled later by PGM
2876	//\| RT_BIT_32(21) - reserved
2877	\| (pConfig->enmAmdExtMmx ? X86_CPUID_AMD_FEATURE_EDX_AXMMX : 0)
2878	\| X86_CPUID_AMD_FEATURE_EDX_MMX
2879	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
2880	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
2881	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2882	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
2883	//\| RT_BIT_32(28) - reserved
2884	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
2885	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
2886	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
2887	;
2888	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
2889	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
2890	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
2891	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2892	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
2893	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
2894	\| (pConfig->enmAbm ? X86_CPUID_AMD_FEATURE_ECX_ABM : 0)
2895	\| (pConfig->enmSse4A ? X86_CPUID_AMD_FEATURE_ECX_SSE4A : 0)
2896	\| (pConfig->enmMisAlnSse ? X86_CPUID_AMD_FEATURE_ECX_MISALNSSE : 0)
2897	\| (pConfig->enm3dNowPrf ? X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF : 0)
2898	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2899	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
2900	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
2901	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2902	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
2903	//\| RT_BIT_32(14) - reserved
2904	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
2905	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
2906	//\| RT_BIT_32(17) - reserved
2907	//\| RT_BIT_32(18) - reserved
2908	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
2909	//\| RT_BIT_32(20) - reserved
2910	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
2911	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
2912	//\| RT_BIT_32(23) - reserved
2913	//\| RT_BIT_32(24) - reserved
2914	//\| RT_BIT_32(25) - reserved
2915	//\| RT_BIT_32(26) - reserved
2916	//\| RT_BIT_32(27) - reserved
2917	//\| RT_BIT_32(28) - reserved
2918	//\| RT_BIT_32(29) - reserved
2919	//\| RT_BIT_32(30) - reserved
2920	//\| RT_BIT_32(31) - reserved
2921	;
2922	#ifdef VBOX_WITH_MULTI_CORE
2923	if ( pVM->cCpus > 1
2924	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
2925	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
2926	#endif
2927
2928	if (pCpum->u8PortableCpuIdLevel > 0)
2929	{
2930	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2931	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
2932	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
2933	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
2934	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
2935	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
2936	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
2937	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
2938	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
2939	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
2940	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2941	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2942	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2943	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2944	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2945	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2946
2947	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
2948	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
2949	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
2950	\| X86_CPUID_AMD_FEATURE_ECX_IBS
2951	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
2952	\| X86_CPUID_AMD_FEATURE_ECX_WDT
2953	\| X86_CPUID_AMD_FEATURE_ECX_LWP
2954	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
2955	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
2956	\| UINT32_C(0xff964000)
2957	)));
2958	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
2959	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
2960	\| RT_BIT(18)
2961	\| RT_BIT(19)
2962	\| RT_BIT(21)
2963	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
2964	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
2965	\| RT_BIT(28)
2966	)));
2967	}
2968
2969	/* Force extended feature bits. */
2970	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
2971	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
2972	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
2973	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
2974	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
2975	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
2976	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
2977	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
2978	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
2979	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
2980	}
2981	pExtFeatureLeaf = NULL; /* Must refetch! */
2982
2983
2984	/* Cpuid 2:
2985	* Intel: (Nondeterministic) Cache and TLB information
2986	* AMD: Reserved
2987	* VIA: Reserved
2988	* Safe to expose.
2989	*/
2990	uint32_t uSubLeaf = 0;
2991	PCPUMCPUIDLEAF pCurLeaf;
2992	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
2993	{
2994	if ((pCurLeaf->uEax & 0xff) > 1)
2995	{
2996	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
2997	pCurLeaf->uEax &= UINT32_C(0xffffff01);
2998	}
2999	uSubLeaf++;
3000	}
3001
3002	/* Cpuid 3:
3003	* Intel: EAX, EBX - reserved (transmeta uses these)
3004	* ECX, EDX - Processor Serial Number if available, otherwise reserved
3005	* AMD: Reserved
3006	* VIA: Reserved
3007	* Safe to expose
3008	*/
3009	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3010	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
3011	{
3012	uSubLeaf = 0;
3013	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
3014	{
3015	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3016	if (pCpum->u8PortableCpuIdLevel > 0)
3017	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3018	uSubLeaf++;
3019	}
3020	}
3021
3022	/* Cpuid 4 + ECX:
3023	* Intel: Deterministic Cache Parameters Leaf.
3024	* AMD: Reserved
3025	* VIA: Reserved
3026	* Safe to expose, except for EAX:
3027	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
3028	* Bits 31-26: Maximum number of processor cores in this physical package**
3029	* Note: These SMP values are constant regardless of ECX
3030	*/
3031	uSubLeaf = 0;
3032	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
3033	{
3034	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
3035	#ifdef VBOX_WITH_MULTI_CORE
3036	if ( pVM->cCpus > 1
3037	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3038	{
3039	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
3040	/* One logical processor with possibly multiple cores. */
3041	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
3042	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
3043	}
3044	#endif
3045	uSubLeaf++;
3046	}
3047
3048	/* Cpuid 5: Monitor/mwait Leaf
3049	* Intel: ECX, EDX - reserved
3050	* EAX, EBX - Smallest and largest monitor line size
3051	* AMD: EDX - reserved
3052	* EAX, EBX - Smallest and largest monitor line size
3053	* ECX - extensions (ignored for now)
3054	* VIA: Reserved
3055	* Safe to expose
3056	*/
3057	uSubLeaf = 0;
3058	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
3059	{
3060	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3061	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
3062	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
3063
3064	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3065	if (pConfig->enmMWaitExtensions)
3066	{
3067	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
3068	/** @todo for now we just expose host's MWAIT C-states, although conceptually
3069	it shall be part of our power management virtualization model */
3070	#if 0
3071	/* MWAIT sub C-states */
3072	pCurLeaf->uEdx =
3073	(0 << 0) /* 0 in C0 */ \|
3074	(2 << 4) /* 2 in C1 */ \|
3075	(2 << 8) /* 2 in C2 */ \|
3076	(2 << 12) /* 2 in C3 */ \|
3077	(0 << 16) /* 0 in C4 */
3078	;
3079	#endif
3080	}
3081	else
3082	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
3083	uSubLeaf++;
3084	}
3085
3086	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
3087	* Intel: Various stuff.
3088	* AMD: EAX, EBX, EDX - reserved.
3089	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
3090	* present. Same as intel.
3091	* VIA: ??
3092	*
3093	* We clear everything here for now.
3094	*/
3095	cpumR3CpuIdZeroLeaf(pCpum, 6);
3096
3097	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
3098	* EAX: Number of sub leaves.
3099	* EBX+ECX+EDX: Feature flags
3100	*
3101	* We only have documentation for one sub-leaf, so clear all other (no need
3102	* to remove them as such, just set them to zero).
3103	*
3104	* Note! When enabling new features the Synthetic CPU and Portable CPUID
3105	* options may require adjusting (i.e. stripping what was enabled).
3106	*/
3107	uSubLeaf = 0;
3108	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
3109	{
3110	switch (uSubLeaf)
3111	{
3112	case 0:
3113	{
3114	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
3115	pCurLeaf->uEbx &= 0
3116	\| (pConfig->enmFsGsBase ? X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE : 0)
3117	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
3118	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
3119	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT(3)
3120	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
3121	\| (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
3122	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
3123	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
3124	//\| X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT(8)
3125	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
3126	\| (pConfig->enmInvpcid ? X86_CPUID_STEXT_FEATURE_EBX_INVPCID : 0)
3127	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
3128	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
3129	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
3130	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
3131	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
3132	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
3133	//\| RT_BIT(17) - reserved
3134	\| (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0)
3135	//\| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19)
3136	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
3137	//\| RT_BIT(21) - reserved
3138	//\| RT_BIT(22) - reserved
3139	\| (pConfig->enmCLFlushOpt ? X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT : 0)
3140	//\| RT_BIT(24) - reserved
3141	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
3142	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
3143	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
3144	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
3145	//\| X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT(29)
3146	//\| RT_BIT(30) - reserved
3147	//\| RT_BIT(31) - reserved
3148	;
3149	pCurLeaf->uEcx &= 0
3150	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
3151	;
3152	pCurLeaf->uEdx &= 0
3153	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
3154	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
3155	//\| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT(29)
3156	;
3157
3158	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
3159	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
3160	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
3161	{
3162	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3163	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
3164	}
3165
3166	if (pCpum->u8PortableCpuIdLevel > 0)
3167	{
3168	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
3169	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
3170	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
3171	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
3172	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
3173	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
3174	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
3175	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
3176	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
3177	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
3178	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
3179	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
3180	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
3181	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA);
3182	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
3183	}
3184
3185	/* Force standard feature bits. */
3186	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
3187	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
3188	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
3189	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
3190	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
3191	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
3192	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
3193	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
3194	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
3195	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
3196	break;
3197	}
3198
3199	default:
3200	/* Invalid index, all values are zero. */
3201	pCurLeaf->uEax = 0;
3202	pCurLeaf->uEbx = 0;
3203	pCurLeaf->uEcx = 0;
3204	pCurLeaf->uEdx = 0;
3205	break;
3206	}
3207	uSubLeaf++;
3208	}
3209
3210	/* Cpuid 8: Marked as reserved by Intel and AMD.
3211	* We zero this since we don't know what it may have been used for.
3212	*/
3213	cpumR3CpuIdZeroLeaf(pCpum, 8);
3214
3215	/* Cpuid 9: Direct Cache Access (DCA) Parameters
3216	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3217	* EBX, ECX, EDX - reserved.
3218	* AMD: Reserved
3219	* VIA: ??
3220	*
3221	* We zero this.
3222	*/
3223	cpumR3CpuIdZeroLeaf(pCpum, 9);
3224
3225	/* Cpuid 0xa: Architectural Performance Monitor Features
3226	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
3227	* EBX, ECX, EDX - reserved.
3228	* AMD: Reserved
3229	* VIA: ??
3230	*
3231	* We zero this, for now at least.
3232	*/
3233	cpumR3CpuIdZeroLeaf(pCpum, 10);
3234
3235	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
3236	* Intel: EAX - APCI ID shift right for next level.
3237	* EBX - Factory configured cores/threads at this level.
3238	* ECX - Level number (same as input) and level type (1,2,0).
3239	* EDX - Extended initial APIC ID.
3240	* AMD: Reserved
3241	* VIA: ??
3242	*/
3243	uSubLeaf = 0;
3244	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
3245	{
3246	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3247	{
3248	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
3249	if (bLevelType == 1)
3250	{
3251	/* Thread level - we don't do threads at the moment. */
3252	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
3253	pCurLeaf->uEbx = 1;
3254	}
3255	else if (bLevelType == 2)
3256	{
3257	/* Core level. */
3258	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
3259	#ifdef VBOX_WITH_MULTI_CORE
3260	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
3261	pCurLeaf->uEax++;
3262	#endif
3263	pCurLeaf->uEbx = pVM->cCpus;
3264	}
3265	else
3266	{
3267	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
3268	pCurLeaf->uEax = 0;
3269	pCurLeaf->uEbx = 0;
3270	pCurLeaf->uEcx = 0;
3271	}
3272	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
3273	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
3274	}
3275	else
3276	{
3277	pCurLeaf->uEax = 0;
3278	pCurLeaf->uEbx = 0;
3279	pCurLeaf->uEcx = 0;
3280	pCurLeaf->uEdx = 0;
3281	}
3282	uSubLeaf++;
3283	}
3284
3285	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
3286	* We zero this since we don't know what it may have been used for.
3287	*/
3288	cpumR3CpuIdZeroLeaf(pCpum, 12);
3289
3290	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
3291	* ECX=0: EAX - Valid bits in XCR0[31:0].
3292	* EBX - Maximum state size as per current XCR0 value.
3293	* ECX - Maximum state size for all supported features.
3294	* EDX - Valid bits in XCR0[63:32].
3295	* ECX=1: EAX - Various X-features.
3296	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
3297	* ECX - Valid bits in IA32_XSS[31:0].
3298	* EDX - Valid bits in IA32_XSS[63:32].
3299	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
3300	* if the bit invalid all four registers are set to zero.
3301	* EAX - The state size for this feature.
3302	* EBX - The state byte offset of this feature.
3303	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
3304	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
3305	*
3306	* Clear them all as we don't currently implement extended CPU state.
3307	*/
3308	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
3309	uint64_t fGuestXcr0Mask = 0;
3310	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
3311	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
3312	{
3313	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
3314	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
3315	fGuestXcr0Mask \|= XSAVE_C_YMM;
3316	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
3317	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
3318	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
3319	fGuestXcr0Mask &= pCpum->fXStateHostMask;
3320
3321	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
3322	}
3323	pStdFeatureLeaf = NULL;
3324	pCpum->fXStateGuestMask = fGuestXcr0Mask;
3325
3326	/* Work the sub-leaves. */
3327	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
3328	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
3329	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
3330	{
3331	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
3332	if (pCurLeaf)
3333	{
3334	if (fGuestXcr0Mask)
3335	{
3336	switch (uSubLeaf)
3337	{
3338	case 0:
3339	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
3340	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
3341	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
3342	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
3343	VERR_CPUM_IPE_1);
3344	cbXSaveMaxActual = pCurLeaf->uEcx;
3345	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
3346	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
3347	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
3348	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
3349	VERR_CPUM_IPE_2);
3350	continue;
3351	case 1:
3352	pCurLeaf->uEax &= 0;
3353	pCurLeaf->uEcx &= 0;
3354	pCurLeaf->uEdx &= 0;
3355	/** @todo what about checking ebx? */
3356	continue;
3357	default:
3358	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
3359	{
3360	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
3361	&& pCurLeaf->uEax > 0
3362	&& pCurLeaf->uEbx < cbXSaveMaxActual
3363	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
3364	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
3365	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
3366	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
3367	VERR_CPUM_IPE_2);
3368	AssertLogRel(!(pCurLeaf->uEcx & 1));
3369	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
3370	pCurLeaf->uEdx = 0; /* it's reserved... */
3371	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
3372	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
3373	continue;
3374	}
3375	break;
3376	}
3377	}
3378
3379	/* Clear the leaf. */
3380	pCurLeaf->uEax = 0;
3381	pCurLeaf->uEbx = 0;
3382	pCurLeaf->uEcx = 0;
3383	pCurLeaf->uEdx = 0;
3384	}
3385	}
3386
3387	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
3388	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
3389	{
3390	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
3391	if (pCurLeaf)
3392	{
3393	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
3394	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
3395	pCurLeaf->uEbx = cbXSaveMaxReport;
3396	pCurLeaf->uEcx = cbXSaveMaxReport;
3397	}
3398	}
3399
3400	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
3401	* We zero this since we don't know what it may have been used for.
3402	*/
3403	cpumR3CpuIdZeroLeaf(pCpum, 14);
3404
3405	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
3406	* also known as Intel Resource Director Technology (RDT) Monitoring
3407	* We zero this as we don't currently virtualize PQM.
3408	*/
3409	cpumR3CpuIdZeroLeaf(pCpum, 15);
3410
3411	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
3412	* also known as Intel Resource Director Technology (RDT) Allocation
3413	* We zero this as we don't currently virtualize PQE.
3414	*/
3415	cpumR3CpuIdZeroLeaf(pCpum, 16);
3416
3417	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
3418	* We zero this since we don't know what it may have been used for.
3419	*/
3420	cpumR3CpuIdZeroLeaf(pCpum, 17);
3421
3422	/* Cpuid 0x12 + ECX: SGX resource enumeration.
3423	* We zero this as we don't currently virtualize this.
3424	*/
3425	cpumR3CpuIdZeroLeaf(pCpum, 18);
3426
3427	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
3428	* We zero this since we don't know what it may have been used for.
3429	*/
3430	cpumR3CpuIdZeroLeaf(pCpum, 19);
3431
3432	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
3433	* We zero this as we don't currently virtualize this.
3434	*/
3435	cpumR3CpuIdZeroLeaf(pCpum, 20);
3436
3437	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
3438	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
3439	* EAX - denominator (unsigned).
3440	* EBX - numerator (unsigned).
3441	* ECX, EDX - reserved.
3442	* AMD: Reserved / undefined / not implemented.
3443	* VIA: Reserved / undefined / not implemented.
3444	* We zero this as we don't currently virtualize this.
3445	*/
3446	cpumR3CpuIdZeroLeaf(pCpum, 21);
3447
3448	/* Cpuid 0x16: Processor frequency info
3449	* Intel: EAX - Core base frequency in MHz.
3450	* EBX - Core maximum frequency in MHz.
3451	* ECX - Bus (reference) frequency in MHz.
3452	* EDX - Reserved.
3453	* AMD: Reserved / undefined / not implemented.
3454	* VIA: Reserved / undefined / not implemented.
3455	* We zero this as we don't currently virtualize this.
3456	*/
3457	cpumR3CpuIdZeroLeaf(pCpum, 22);
3458
3459	/* Cpuid 0x17..0x10000000: Unknown.
3460	* We don't know these and what they mean, so remove them. */
3461	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3462	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
3463
3464
3465	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
3466	* We remove all these as we're a hypervisor and must provide our own.
3467	*/
3468	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3469	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
3470
3471
3472	/* Cpuid 0x80000000 is harmless. */
3473
3474	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
3475
3476	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
3477
3478	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
3479	* Safe to pass on to the guest.
3480	*
3481	* AMD: 0x800000005 L1 cache information
3482	* 0x800000006 L2/L3 cache information
3483	* Intel: 0x800000005 reserved
3484	* 0x800000006 L2 cache information
3485	* VIA: 0x800000005 TLB and L1 cache information
3486	* 0x800000006 L2 cache information
3487	*/
3488
3489	/* Cpuid 0x800000007: Advanced Power Management Information.
3490	* AMD: EAX: Processor feedback capabilities.
3491	* EBX: RAS capabilites.
3492	* ECX: Advanced power monitoring interface.
3493	* EDX: Enhanced power management capabilities.
3494	* Intel: EAX, EBX, ECX - reserved.
3495	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
3496	* VIA: Reserved
3497	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
3498	*/
3499	uSubLeaf = 0;
3500	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
3501	{
3502	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
3503	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3504	{
3505	/*
3506	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
3507	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
3508	* bit is now configurable.
3509	*/
3510	pCurLeaf->uEdx &= 0
3511	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
3512	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
3513	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
3514	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
3515	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
3516	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
3517	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
3518	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
3519	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
3520	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
3521	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
3522	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
3523	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
3524	\| 0;
3525	}
3526	else
3527	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3528	if (!pConfig->fInvariantTsc)
3529	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
3530	uSubLeaf++;
3531	}
3532
3533	/* Cpuid 0x80000008:
3534	* AMD: EBX, EDX - reserved
3535	* EAX: Virtual/Physical/Guest address Size
3536	* ECX: Number of cores + APICIdCoreIdSize
3537	* Intel: EAX: Virtual/Physical address Size
3538	* EBX, ECX, EDX - reserved
3539	* VIA: EAX: Virtual/Physical address Size
3540	* EBX, ECX, EDX - reserved
3541	*
3542	* We only expose the virtual+pysical address size to the guest atm.
3543	* On AMD we set the core count, but not the apic id stuff as we're
3544	* currently not doing the apic id assignments in a complatible manner.
3545	*/
3546	uSubLeaf = 0;
3547	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
3548	{
3549	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
3550	pCurLeaf->uEbx = 0; /* reserved - [12] == IBPB */
3551	pCurLeaf->uEdx = 0; /* reserved */
3552
3553	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
3554	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
3555	pCurLeaf->uEcx = 0;
3556	#ifdef VBOX_WITH_MULTI_CORE
3557	if ( pVM->cCpus > 1
3558	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
3559	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
3560	#endif
3561	uSubLeaf++;
3562	}
3563
3564	/* Cpuid 0x80000009: Reserved
3565	* We zero this since we don't know what it may have been used for.
3566	*/
3567	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
3568
3569	/* Cpuid 0x8000000a: SVM Information
3570	* AMD: EAX - SVM revision.
3571	* EBX - Number of ASIDs.
3572	* ECX - Reserved.
3573	* EDX - SVM Feature identification.
3574	*/
3575	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
3576	if (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
3577	{
3578	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
3579	pSvmFeatureLeaf->uEax = 0x1;
3580	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
3581	pSvmFeatureLeaf->uEcx = 0;
3582	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
3583	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
3584	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
3585	}
3586	else
3587	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
3588
3589	/* Cpuid 0x8000000b thru 0x80000018: Reserved
3590	* We clear these as we don't know what purpose they might have. */
3591	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
3592	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
3593
3594	/* Cpuid 0x80000019: TLB configuration
3595	* Seems to be harmless, pass them thru as is. */
3596
3597	/* Cpuid 0x8000001a: Peformance optimization identifiers.
3598	* Strip anything we don't know what is or addresses feature we don't implement. */
3599	uSubLeaf = 0;
3600	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
3601	{
3602	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
3603	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
3604	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
3605	;
3606	pCurLeaf->uEbx = 0; /* reserved */
3607	pCurLeaf->uEcx = 0; /* reserved */
3608	pCurLeaf->uEdx = 0; /* reserved */
3609	uSubLeaf++;
3610	}
3611
3612	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
3613	* Clear this as we don't currently virtualize this feature. */
3614	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
3615
3616	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
3617	* Clear this as we don't currently virtualize this feature. */
3618	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
3619
3620	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
3621	* We need to sanitize the cores per cache (EAX[25:14]).
3622	*
3623	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
3624	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
3625	* slightly different meaning.
3626	*/
3627	uSubLeaf = 0;
3628	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
3629	{
3630	#ifdef VBOX_WITH_MULTI_CORE
3631	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
3632	if (cCores > pVM->cCpus)
3633	cCores = pVM->cCpus;
3634	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3635	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
3636	#else
3637	pCurLeaf->uEax &= UINT32_C(0x00003fff);
3638	#endif
3639	uSubLeaf++;
3640	}
3641
3642	/* Cpuid 0x8000001e: Get APIC / unit / node information.
3643	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
3644	* setup, we have one compute unit with all the cores in it. Single node.
3645	*/
3646	uSubLeaf = 0;
3647	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
3648	{
3649	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
3650	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
3651	{
3652	#ifdef VBOX_WITH_MULTI_CORE
3653	pCurLeaf->uEbx = pVM->cCpus < 0x100
3654	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
3655	#else
3656	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
3657	#endif
3658	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
3659	}
3660	else
3661	{
3662	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
3663	pCurLeaf->uEbx = 0; /* Reserved. */
3664	pCurLeaf->uEcx = 0; /* Reserved. */
3665	}
3666	pCurLeaf->uEdx = 0; /* Reserved. */
3667	uSubLeaf++;
3668	}
3669
3670	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
3671	* We don't know these and what they mean, so remove them. */
3672	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3673	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
3674
3675	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
3676	* Just pass it thru for now. */
3677
3678	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
3679	* Just pass it thru for now. */
3680
3681	/* Cpuid 0xc0000000: Centaur stuff.
3682	* Harmless, pass it thru. */
3683
3684	/* Cpuid 0xc0000001: Centaur features.
3685	* VIA: EAX - Family, model, stepping.
3686	* EDX - Centaur extended feature flags. Nothing interesting, except may
3687	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
3688	* EBX, ECX - reserved.
3689	* We keep EAX but strips the rest.
3690	*/
3691	uSubLeaf = 0;
3692	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
3693	{
3694	pCurLeaf->uEbx = 0;
3695	pCurLeaf->uEcx = 0;
3696	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
3697	uSubLeaf++;
3698	}
3699
3700	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
3701	* We only have fixed stale values, but should be harmless. */
3702
3703	/* Cpuid 0xc0000003: Reserved.
3704	* We zero this since we don't know what it may have been used for.
3705	*/
3706	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
3707
3708	/* Cpuid 0xc0000004: Centaur Performance Info.
3709	* We only have fixed stale values, but should be harmless. */
3710
3711
3712	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
3713	* We don't know these and what they mean, so remove them. */
3714	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
3715	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
3716
3717	return VINF_SUCCESS;
3718	#undef PORTABLE_DISABLE_FEATURE_BIT
3719	#undef PORTABLE_CLEAR_BITS_WHEN
3720	}
3721
3722
3723	/**
3724	* Reads a value in /CPUM/IsaExts/ node.
3725	*
3726	* @returns VBox status code (error message raised).
3727	* @param pVM The cross context VM structure. (For errors.)
3728	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3729	* @param pszValueName The value / extension name.
3730	* @param penmValue Where to return the choice.
3731	* @param enmDefault The default choice.
3732	*/
3733	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3734	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3735	{
3736	/*
3737	* Try integer encoding first.
3738	*/
3739	uint64_t uValue;
3740	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
3741	if (RT_SUCCESS(rc))
3742	switch (uValue)
3743	{
3744	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
3745	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
3746	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
3747	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
3748	default:
3749	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3750	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3751	pszValueName, uValue);
3752	}
3753	/*
3754	* If missing, use default.
3755	*/
3756	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
3757	*penmValue = enmDefault;
3758	else
3759	{
3760	if (rc == VERR_CFGM_NOT_INTEGER)
3761	{
3762	/*
3763	* Not an integer, try read it as a string.
3764	*/
3765	char szValue[32];
3766	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
3767	if (RT_SUCCESS(rc))
3768	{
3769	RTStrToLower(szValue);
3770	size_t cchValue = strlen(szValue);
3771	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
3772	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
3773	*penmValue = CPUMISAEXTCFG_DISABLED;
3774	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
3775	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
3776	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
3777	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
3778	else if (EQ("portable"))
3779	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
3780	else if (EQ("default") \|\| EQ("def"))
3781	*penmValue = enmDefault;
3782	else
3783	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
3784	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
3785	pszValueName, uValue);
3786	#undef EQ
3787	}
3788	}
3789	if (RT_FAILURE(rc))
3790	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
3791	}
3792	return VINF_SUCCESS;
3793	}
3794
3795
3796	/**
3797	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
3798	*
3799	* @returns VBox status code (error message raised).
3800	* @param pVM The cross context VM structure. (For errors.)
3801	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3802	* @param pszValueName The value / extension name.
3803	* @param penmValue Where to return the choice.
3804	* @param enmDefault The default choice.
3805	* @param fAllowed Allowed choice. Applied both to the result and to
3806	* the default value.
3807	*/
3808	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
3809	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
3810	{
3811	int rc;
3812	if (fAllowed)
3813	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3814	else
3815	{
3816	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
3817	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
3818	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
3819	*penmValue = CPUMISAEXTCFG_DISABLED;
3820	}
3821	return rc;
3822	}
3823
3824
3825	/**
3826	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
3827	*
3828	* @returns VBox status code (error message raised).
3829	* @param pVM The cross context VM structure. (For errors.)
3830	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
3831	* @param pCpumCfg The /CPUM node (can be NULL).
3832	* @param pszValueName The value / extension name.
3833	* @param penmValue Where to return the choice.
3834	* @param enmDefault The default choice.
3835	*/
3836	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
3837	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
3838	{
3839	if (CFGMR3Exists(pCpumCfg, pszValueName))
3840	{
3841	if (!CFGMR3Exists(pIsaExts, pszValueName))
3842	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
3843	else
3844	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
3845	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
3846	pszValueName, pszValueName);
3847
3848	bool fLegacy;
3849	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
3850	if (RT_SUCCESS(rc))
3851	{
3852	*penmValue = fLegacy;
3853	return VINF_SUCCESS;
3854	}
3855	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
3856	}
3857
3858	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
3859	}
3860
3861
3862	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
3863	{
3864	int rc;
3865
3866	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
3867	* When non-zero CPUID features that could cause portability issues will be
3868	* stripped. The higher the value the more features gets stripped. Higher
3869	* values should only be used when older CPUs are involved since it may
3870	* harm performance and maybe also cause problems with specific guests. */
3871	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
3872	AssertLogRelRCReturn(rc, rc);
3873
3874	/** @cfgm{/CPUM/GuestCpuName, string}
3875	* The name of the CPU we're to emulate. The default is the host CPU.
3876	* Note! CPUs other than "host" one is currently unsupported. */
3877	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
3878	AssertLogRelRCReturn(rc, rc);
3879
3880	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
3881	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
3882	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
3883	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
3884	*/
3885	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
3886	AssertLogRelRCReturn(rc, rc);
3887
3888	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
3889	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
3890	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
3891	* 64-bit linux guests which assume the presence of AMD performance counters
3892	* that we do not virtualize.
3893	*/
3894	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
3895	AssertLogRelRCReturn(rc, rc);
3896
3897	/** @cfgm{/CPUM/ForceVme, boolean, false}
3898	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
3899	* By default the flag is passed thru as is from the host CPU, except
3900	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
3901	* guests and DOS boxes in general.
3902	*/
3903	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
3904	AssertLogRelRCReturn(rc, rc);
3905
3906	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
3907	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
3908	* probably going to be a temporary hack, so don't depend on this.
3909	* The 1st byte of the value is the stepping, the 2nd byte value is the model
3910	* number and the 3rd byte value is the family, and the 4th value must be zero.
3911	*/
3912	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
3913	AssertLogRelRCReturn(rc, rc);
3914
3915	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
3916	* The last standard leaf to keep. The actual last value that is stored in EAX
3917	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
3918	* removed. (This works independently of and differently from NT4LeafLimit.)
3919	* The default is usually set to what we're able to reasonably sanitize.
3920	*/
3921	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
3922	AssertLogRelRCReturn(rc, rc);
3923
3924	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
3925	* The last extended leaf to keep. The actual last value that is stored in EAX
3926	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
3927	* leaf are removed. The default is set to what we're able to sanitize.
3928	*/
3929	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
3930	AssertLogRelRCReturn(rc, rc);
3931
3932	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
3933	* The last extended leaf to keep. The actual last value that is stored in EAX
3934	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
3935	* leaf are removed. The default is set to what we're able to sanitize.
3936	*/
3937	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
3938	AssertLogRelRCReturn(rc, rc);
3939
3940	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
3941	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
3942	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
3943	* The default is false, and when enabled requires nested paging and AMD-V or
3944	* unrestricted guest mode.
3945	*/
3946	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
3947	AssertLogRelRCReturn(rc, rc);
3948	if ( pConfig->fNestedHWVirt
3949	&& !fNestedPagingAndFullGuestExec)
3950	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
3951	"Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
3952
3953	/** @todo Think about enabling this later with NEM/KVM. */
3954	if ( pConfig->fNestedHWVirt
3955	&& VM_IS_NEM_ENABLED(pVM))
3956	{
3957	LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
3958	pConfig->fNestedHWVirt = false;
3959	}
3960	#endif
3961
3962	/*
3963	* Instruction Set Architecture (ISA) Extensions.
3964	*/
3965	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
3966	if (pIsaExts)
3967	{
3968	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
3969	"CMPXCHG16B"
3970	"\|MONITOR"
3971	"\|MWaitExtensions"
3972	"\|SSE4.1"
3973	"\|SSE4.2"
3974	"\|XSAVE"
3975	"\|AVX"
3976	"\|AVX2"
3977	"\|AESNI"
3978	"\|PCLMUL"
3979	"\|POPCNT"
3980	"\|MOVBE"
3981	"\|RDRAND"
3982	"\|RDSEED"
3983	"\|CLFLUSHOPT"
3984	"\|FSGSBASE"
3985	"\|PCID"
3986	"\|INVPCID"
3987	"\|ABM"
3988	"\|SSE4A"
3989	"\|MISALNSSE"
3990	"\|3DNOWPRF"
3991	"\|AXMMX"
3992	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
3993	if (RT_FAILURE(rc))
3994	return rc;
3995	}
3996
3997	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, depends}
3998	* Expose CMPXCHG16B to the guest if supported by the host. For the time
3999	* being the default is to only do this for VMs with nested paging and AMD-V or
4000	* unrestricted guest mode.
4001	*/
4002	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, fNestedPagingAndFullGuestExec);
4003	AssertLogRelRCReturn(rc, rc);
4004
4005	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
4006	* Expose MONITOR/MWAIT instructions to the guest.
4007	*/
4008	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
4009	AssertLogRelRCReturn(rc, rc);
4010
4011	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
4012	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
4013	* break on interrupt feature (bit 1).
4014	*/
4015	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
4016	AssertLogRelRCReturn(rc, rc);
4017
4018	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
4019	* Expose SSE4.1 to the guest if available.
4020	*/
4021	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
4022	AssertLogRelRCReturn(rc, rc);
4023
4024	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
4025	* Expose SSE4.2 to the guest if available.
4026	*/
4027	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
4028	AssertLogRelRCReturn(rc, rc);
4029
4030	bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
4031	&& pVM->cpum.s.HostFeatures.fXSaveRstor
4032	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
4033	#if HC_ARCH_BITS == 32 /* Seems this may be broken when doing 64-bit on 32-bit, just disable it for now. */
4034	&& ( !HMIsLongModeAllowed(pVM)
4035	\|\| NEMHCIsLongModeAllowed(pVM))
4036	#endif
4037	;
4038	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
4039
4040	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
4041	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
4042	* default is to only expose this to VMs with nested paging and AMD-V or
4043	* unrestricted guest execution mode. Not possible to force this one without
4044	* host support at the moment.
4045	*/
4046	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
4047	fMayHaveXSave /fAllowed/);
4048	AssertLogRelRCReturn(rc, rc);
4049
4050	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
4051	* Expose the AVX instruction set extensions to the guest if available and
4052	* XSAVE is exposed too. For the time being the default is to only expose this
4053	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4054	*/
4055	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
4056	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4057	AssertLogRelRCReturn(rc, rc);
4058
4059	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
4060	* Expose the AVX2 instruction set extensions to the guest if available and
4061	* XSAVE is exposed too. For the time being the default is to only expose this
4062	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
4063	*/
4064	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
4065	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
4066	AssertLogRelRCReturn(rc, rc);
4067
4068	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
4069	* Whether to expose the AES instructions to the guest. For the time being the
4070	* default is to only do this for VMs with nested paging and AMD-V or
4071	* unrestricted guest mode.
4072	*/
4073	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
4074	AssertLogRelRCReturn(rc, rc);
4075
4076	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
4077	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
4078	* being the default is to only do this for VMs with nested paging and AMD-V or
4079	* unrestricted guest mode.
4080	*/
4081	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
4082	AssertLogRelRCReturn(rc, rc);
4083
4084	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends}
4085	* Whether to expose the POPCNT instructions to the guest. For the time
4086	* being the default is to only do this for VMs with nested paging and AMD-V or
4087	* unrestricted guest mode.
4088	*/
4089	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec);
4090	AssertLogRelRCReturn(rc, rc);
4091
4092	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
4093	* Whether to expose the MOVBE instructions to the guest. For the time
4094	* being the default is to only do this for VMs with nested paging and AMD-V or
4095	* unrestricted guest mode.
4096	*/
4097	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec);
4098	AssertLogRelRCReturn(rc, rc);
4099
4100	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
4101	* Whether to expose the RDRAND instructions to the guest. For the time being
4102	* the default is to only do this for VMs with nested paging and AMD-V or
4103	* unrestricted guest mode.
4104	*/
4105	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
4106	AssertLogRelRCReturn(rc, rc);
4107
4108	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
4109	* Whether to expose the RDSEED instructions to the guest. For the time being
4110	* the default is to only do this for VMs with nested paging and AMD-V or
4111	* unrestricted guest mode.
4112	*/
4113	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
4114	AssertLogRelRCReturn(rc, rc);
4115
4116	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
4117	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
4118	* being the default is to only do this for VMs with nested paging and AMD-V or
4119	* unrestricted guest mode.
4120	*/
4121	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
4122	AssertLogRelRCReturn(rc, rc);
4123
4124	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
4125	* Whether to expose the read/write FSGSBASE instructions to the guest.
4126	*/
4127	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
4128	AssertLogRelRCReturn(rc, rc);
4129
4130	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
4131	* Whether to expose the PCID feature to the guest.
4132	*/
4133	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
4134	AssertLogRelRCReturn(rc, rc);
4135
4136	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
4137	* Whether to expose the INVPCID instruction to the guest.
4138	*/
4139	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
4140	AssertLogRelRCReturn(rc, rc);
4141
4142
4143	/* AMD: */
4144
4145	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, depends}
4146	* Whether to expose the AMD ABM instructions to the guest. For the time
4147	* being the default is to only do this for VMs with nested paging and AMD-V or
4148	* unrestricted guest mode.
4149	*/
4150	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, fNestedPagingAndFullGuestExec);
4151	AssertLogRelRCReturn(rc, rc);
4152
4153	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
4154	* Whether to expose the AMD SSE4A instructions to the guest. For the time
4155	* being the default is to only do this for VMs with nested paging and AMD-V or
4156	* unrestricted guest mode.
4157	*/
4158	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
4159	AssertLogRelRCReturn(rc, rc);
4160
4161	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
4162	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
4163	* the time being the default is to only do this for VMs with nested paging and
4164	* AMD-V or unrestricted guest mode.
4165	*/
4166	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
4167	AssertLogRelRCReturn(rc, rc);
4168
4169	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
4170	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
4171	* For the time being the default is to only do this for VMs with nested paging
4172	* and AMD-V or unrestricted guest mode.
4173	*/
4174	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
4175	AssertLogRelRCReturn(rc, rc);
4176
4177	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
4178	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
4179	* the default is to only do this for VMs with nested paging and AMD-V or
4180	* unrestricted guest mode.
4181	*/
4182	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
4183	AssertLogRelRCReturn(rc, rc);
4184
4185	return VINF_SUCCESS;
4186	}
4187
4188
4189	/**
4190	* Initializes the emulated CPU's CPUID & MSR information.
4191	*
4192	* @returns VBox status code.
4193	* @param pVM The cross context VM structure.
4194	*/
4195	int cpumR3InitCpuIdAndMsrs(PVM pVM)
4196	{
4197	PCPUM pCpum = &pVM->cpum.s;
4198	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
4199
4200	/*
4201	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
4202	* on construction and manage everything from here on.
4203	*/
4204	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
4205	pVM->aCpus[iCpu].cpum.s.fCpuIdApicFeatureVisible = true;
4206
4207	/*
4208	* Read the configuration.
4209	*/
4210	CPUMCPUIDCONFIG Config;
4211	RT_ZERO(Config);
4212
4213	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));
4214	AssertRCReturn(rc, rc);
4215
4216	/*
4217	* Get the guest CPU data from the database and/or the host.
4218	*
4219	* The CPUID and MSRs are currently living on the regular heap to avoid
4220	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
4221	* API for the hyper heap). This means special cleanup considerations.
4222	*/
4223	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
4224	if (RT_FAILURE(rc))
4225	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
4226	? VMSetError(pVM, rc, RT_SRC_POS,
4227	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
4228	: rc;
4229
4230	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
4231	{
4232	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
4233	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4234	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
4235	}
4236	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
4237
4238	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
4239	* Overrides the guest MSRs.
4240	*/
4241	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
4242
4243	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
4244	* Overrides the CPUID leaf values (from the host CPU usually) used for
4245	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
4246	* values when moving a VM to a different machine. Another use is restricting
4247	* (or extending) the feature set exposed to the guest. */
4248	if (RT_SUCCESS(rc))
4249	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
4250
4251	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
4252	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
4253	"Found unsupported configuration node '/CPUM/CPUID/'. "
4254	"Please use IMachine::setCPUIDLeaf() instead.");
4255
4256	/*
4257	* Pre-explode the CPUID info.
4258	*/
4259	if (RT_SUCCESS(rc))
4260	rc = cpumR3CpuIdExplodeFeatures(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &pCpum->GuestFeatures);
4261
4262	/*
4263	* Sanitize the cpuid information passed on to the guest.
4264	*/
4265	if (RT_SUCCESS(rc))
4266	{
4267	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
4268	if (RT_SUCCESS(rc))
4269	{
4270	cpumR3CpuIdLimitLeaves(pCpum, &Config);
4271	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
4272	}
4273	}
4274
4275	/*
4276	* MSR fudging.
4277	*/
4278	if (RT_SUCCESS(rc))
4279	{
4280	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
4281	* Fudges some common MSRs if not present in the selected CPU database entry.
4282	* This is for trying to keep VMs running when moved between different hosts
4283	* and different CPU vendors. */
4284	bool fEnable;
4285	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
4286	if (RT_SUCCESS(rc) && fEnable)
4287	{
4288	rc = cpumR3MsrApplyFudge(pVM);
4289	AssertLogRelRC(rc);
4290	}
4291	}
4292	if (RT_SUCCESS(rc))
4293	{
4294	/*
4295	* Move the MSR and CPUID arrays over on the hypervisor heap, and explode
4296	* guest CPU features again.
4297	*/
4298	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
4299	int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
4300	pCpum->GuestInfo.cCpuIdLeaves);
4301	RTMemFree(pvFree);
4302
4303	pvFree = pCpum->GuestInfo.paMsrRangesR3;
4304	int rc2 = MMHyperDupMem(pVM, pvFree,
4305	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges, 32,
4306	MM_TAG_CPUM_MSRS, (void **)&pCpum->GuestInfo.paMsrRangesR3);
4307	RTMemFree(pvFree);
4308	AssertLogRelRCReturn(rc1, rc1);
4309	AssertLogRelRCReturn(rc2, rc2);
4310
4311	pCpum->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCpum->GuestInfo.paMsrRangesR3);
4312	pCpum->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCpum->GuestInfo.paMsrRangesR3);
4313
4314
4315	/*
4316	* Some more configuration that we're applying at the end of everything
4317	* via the CPUMSetGuestCpuIdFeature API.
4318	*/
4319
4320	/* Check if PAE was explicitely enabled by the user. */
4321	bool fEnable;
4322	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false);
4323	AssertRCReturn(rc, rc);
4324	if (fEnable)
4325	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
4326
4327	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
4328	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false);
4329	AssertRCReturn(rc, rc);
4330	if (fEnable)
4331	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
4332
4333	/* Check if speculation control is enabled. */
4334	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
4335	AssertRCReturn(rc, rc);
4336	if (fEnable)
4337	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
4338
4339	return VINF_SUCCESS;
4340	}
4341
4342	/*
4343	* Failed before switching to hyper heap.
4344	*/
4345	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
4346	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
4347	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
4348	pCpum->GuestInfo.paMsrRangesR3 = NULL;
4349	return rc;
4350	}
4351
4352
4353	/**
4354	* Sets a CPUID feature bit during VM initialization.
4355	*
4356	* Since the CPUID feature bits are generally related to CPU features, other
4357	* CPUM configuration like MSRs can also be modified by calls to this API.
4358	*
4359	* @param pVM The cross context VM structure.
4360	* @param enmFeature The feature to set.
4361	*/
4362	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4363	{
4364	PCPUMCPUIDLEAF pLeaf;
4365	PCPUMMSRRANGE pMsrRange;
4366
4367	switch (enmFeature)
4368	{
4369	/*
4370	* Set the APIC bit in both feature masks.
4371	*/
4372	case CPUMCPUIDFEATURE_APIC:
4373	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4374	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4375	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
4376
4377	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4378	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4379	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
4380
4381	pVM->cpum.s.GuestFeatures.fApic = 1;
4382
4383	/* Make sure we've got the APICBASE MSR present. */
4384	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4385	if (!pMsrRange)
4386	{
4387	static CPUMMSRRANGE const s_ApicBase =
4388	{
4389	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
4390	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
4391	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4392	/.szName = / "IA32_APIC_BASE"
4393	};
4394	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
4395	AssertLogRelRC(rc);
4396	}
4397
4398	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
4399	break;
4400
4401	/*
4402	* Set the x2APIC bit in the standard feature mask.
4403	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
4404	*/
4405	case CPUMCPUIDFEATURE_X2APIC:
4406	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4407	if (pLeaf)
4408	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
4409	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
4410
4411	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
4412	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
4413	if (pMsrRange)
4414	{
4415	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
4416	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
4417	}
4418
4419	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
4420	break;
4421
4422	/*
4423	* Set the sysenter/sysexit bit in the standard feature mask.
4424	* Assumes the caller knows what it's doing! (host must support these)
4425	*/
4426	case CPUMCPUIDFEATURE_SEP:
4427	if (!pVM->cpum.s.HostFeatures.fSysEnter)
4428	{
4429	AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
4430	return;
4431	}
4432
4433	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4434	if (pLeaf)
4435	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
4436	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
4437	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
4438	break;
4439
4440	/*
4441	* Set the syscall/sysret bit in the extended feature mask.
4442	* Assumes the caller knows what it's doing! (host must support these)
4443	*/
4444	case CPUMCPUIDFEATURE_SYSCALL:
4445	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4446	if ( !pLeaf
4447	\|\| !pVM->cpum.s.HostFeatures.fSysCall)
4448	{
4449	#if HC_ARCH_BITS == 32
4450	/* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32-bit
4451	mode by Intel, even when the cpu is capable of doing so in
4452	64-bit mode. Long mode requires syscall support. */
4453	if (!pVM->cpum.s.HostFeatures.fLongMode)
4454	#endif
4455	{
4456	LogRel(("CPUM: WARNING! Can't turn on SYSCALL/SYSRET when the host doesn't support it!\n"));
4457	return;
4458	}
4459	}
4460
4461	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
4462	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
4463	pVM->cpum.s.GuestFeatures.fSysCall = 1;
4464	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
4465	break;
4466
4467	/*
4468	* Set the PAE bit in both feature masks.
4469	* Assumes the caller knows what it's doing! (host must support these)
4470	*/
4471	case CPUMCPUIDFEATURE_PAE:
4472	if (!pVM->cpum.s.HostFeatures.fPae)
4473	{
4474	LogRel(("CPUM: WARNING! Can't turn on PAE when the host doesn't support it!\n"));
4475	return;
4476	}
4477
4478	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4479	if (pLeaf)
4480	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
4481
4482	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4483	if ( pLeaf
4484	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4485	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
4486
4487	pVM->cpum.s.GuestFeatures.fPae = 1;
4488	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
4489	break;
4490
4491	/*
4492	* Set the LONG MODE bit in the extended feature mask.
4493	* Assumes the caller knows what it's doing! (host must support these)
4494	*/
4495	case CPUMCPUIDFEATURE_LONG_MODE:
4496	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4497	if ( !pLeaf
4498	\|\| !pVM->cpum.s.HostFeatures.fLongMode)
4499	{
4500	LogRel(("CPUM: WARNING! Can't turn on LONG MODE when the host doesn't support it!\n"));
4501	return;
4502	}
4503
4504	/* Valid for both Intel and AMD. */
4505	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4506	pVM->cpum.s.GuestFeatures.fLongMode = 1;
4507	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
4508	break;
4509
4510	/*
4511	* Set the NX/XD bit in the extended feature mask.
4512	* Assumes the caller knows what it's doing! (host must support these)
4513	*/
4514	case CPUMCPUIDFEATURE_NX:
4515	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4516	if ( !pLeaf
4517	\|\| !pVM->cpum.s.HostFeatures.fNoExecute)
4518	{
4519	LogRel(("CPUM: WARNING! Can't turn on NX/XD when the host doesn't support it!\n"));
4520	return;
4521	}
4522
4523	/* Valid for both Intel and AMD. */
4524	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
4525	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
4526	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
4527	break;
4528
4529
4530	/*
4531	* Set the LAHF/SAHF support in 64-bit mode.
4532	* Assumes the caller knows what it's doing! (host must support this)
4533	*/
4534	case CPUMCPUIDFEATURE_LAHF:
4535	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4536	if ( !pLeaf
4537	\|\| !pVM->cpum.s.HostFeatures.fLahfSahf)
4538	{
4539	LogRel(("CPUM: WARNING! Can't turn on LAHF/SAHF when the host doesn't support it!\n"));
4540	return;
4541	}
4542
4543	/* Valid for both Intel and AMD. */
4544	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4545	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
4546	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
4547	break;
4548
4549	/*
4550	* Set the page attribute table bit. This is alternative page level
4551	* cache control that doesn't much matter when everything is
4552	* virtualized, though it may when passing thru device memory.
4553	*/
4554	case CPUMCPUIDFEATURE_PAT:
4555	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4556	if (pLeaf)
4557	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAT;
4558
4559	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4560	if ( pLeaf
4561	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4562	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAT;
4563
4564	pVM->cpum.s.GuestFeatures.fPat = 1;
4565	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAT\n"));
4566	break;
4567
4568	/*
4569	* Set the RDTSCP support bit.
4570	* Assumes the caller knows what it's doing! (host must support this)
4571	*/
4572	case CPUMCPUIDFEATURE_RDTSCP:
4573	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4574	if ( !pLeaf
4575	\|\| !pVM->cpum.s.HostFeatures.fRdTscP
4576	\|\| pVM->cpum.s.u8PortableCpuIdLevel > 0)
4577	{
4578	if (!pVM->cpum.s.u8PortableCpuIdLevel)
4579	LogRel(("CPUM: WARNING! Can't turn on RDTSCP when the host doesn't support it!\n"));
4580	return;
4581	}
4582
4583	/* Valid for both Intel and AMD. */
4584	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4585	pVM->cpum.s.HostFeatures.fRdTscP = 1;
4586	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
4587	break;
4588
4589	/*
4590	* Set the Hypervisor Present bit in the standard feature mask.
4591	*/
4592	case CPUMCPUIDFEATURE_HVP:
4593	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4594	if (pLeaf)
4595	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
4596	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
4597	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
4598	break;
4599
4600	/*
4601	* Set the MWAIT Extensions Present bit in the MWAIT/MONITOR leaf.
4602	* This currently includes the Present bit and MWAITBREAK bit as well.
4603	*/
4604	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4605	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4606	if ( !pLeaf
4607	\|\| !pVM->cpum.s.HostFeatures.fMWaitExtensions)
4608	{
4609	LogRel(("CPUM: WARNING! Can't turn on MWAIT Extensions when the host doesn't support it!\n"));
4610	return;
4611	}
4612
4613	/* Valid for both Intel and AMD. */
4614	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx \|= X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
4615	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 1;
4616	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled MWAIT Extensions.\n"));
4617	break;
4618
4619	/*
4620	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
4621	* on Intel CPUs, and different on AMDs.
4622	*/
4623	case CPUMCPUIDFEATURE_SPEC_CTRL:
4624	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
4625	{
4626	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4627	if ( !pLeaf
4628	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
4629	{
4630	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
4631	return;
4632	}
4633
4634	/* The feature can be enabled. Let's see what we can actually do. */
4635	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
4636
4637	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
4638	if (pVM->cpum.s.HostFeatures.fIbrs)
4639	{
4640	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
4641	pVM->cpum.s.GuestFeatures.fIbrs = 1;
4642	if (pVM->cpum.s.HostFeatures.fStibp)
4643	{
4644	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
4645	pVM->cpum.s.GuestFeatures.fStibp = 1;
4646	}
4647
4648	/* Make sure we have the speculation control MSR... */
4649	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
4650	if (!pMsrRange)
4651	{
4652	static CPUMMSRRANGE const s_SpecCtrl =
4653	{
4654	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
4655	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
4656	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4657	/.szName = / "IA32_SPEC_CTRL"
4658	};
4659	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4660	AssertLogRelRC(rc);
4661	}
4662
4663	/* ... and the predictor command MSR. */
4664	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
4665	if (!pMsrRange)
4666	{
4667	static CPUMMSRRANGE const s_SpecCtrl =
4668	{
4669	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
4670	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
4671	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
4672	/.szName = / "IA32_PRED_CMD"
4673	};
4674	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
4675	AssertLogRelRC(rc);
4676	}
4677
4678	}
4679
4680	if (pVM->cpum.s.HostFeatures.fArchCap) {
4681	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
4682
4683	/* Install the architectural capabilities MSR. */
4684	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
4685	if (!pMsrRange)
4686	{
4687	static CPUMMSRRANGE const s_ArchCaps =
4688	{
4689	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
4690	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
4691	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
4692	/.szName = / "IA32_ARCH_CAPABILITIES"
4693	};
4694	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
4695	AssertLogRelRC(rc);
4696	}
4697	}
4698
4699	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
4700	}
4701	else if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4702	{
4703	/* The precise details of AMD's implementation are not yet clear. */
4704	}
4705	break;
4706
4707	default:
4708	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4709	break;
4710	}
4711
4712	/** @todo can probably kill this as this API is now init time only... */
4713	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4714	{
4715	PVMCPU pVCpu = &pVM->aCpus[i];
4716	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4717	}
4718	}
4719
4720
4721	/**
4722	* Queries a CPUID feature bit.
4723	*
4724	* @returns boolean for feature presence
4725	* @param pVM The cross context VM structure.
4726	* @param enmFeature The feature to query.
4727	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
4728	*/
4729	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4730	{
4731	switch (enmFeature)
4732	{
4733	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
4734	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
4735	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
4736	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
4737	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
4738	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
4739	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
4740	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
4741	case CPUMCPUIDFEATURE_PAT: return pVM->cpum.s.GuestFeatures.fPat;
4742	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
4743	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
4744	case CPUMCPUIDFEATURE_MWAIT_EXTS: return pVM->cpum.s.GuestFeatures.fMWaitExtensions;
4745	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
4746
4747	case CPUMCPUIDFEATURE_INVALID:
4748	case CPUMCPUIDFEATURE_32BIT_HACK:
4749	break;
4750	}
4751	AssertFailed();
4752	return false;
4753	}
4754
4755
4756	/**
4757	* Clears a CPUID feature bit.
4758	*
4759	* @param pVM The cross context VM structure.
4760	* @param enmFeature The feature to clear.
4761	*
4762	* @deprecated Probably better to default the feature to disabled and only allow
4763	* setting (enabling) it during construction.
4764	*/
4765	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
4766	{
4767	PCPUMCPUIDLEAF pLeaf;
4768	switch (enmFeature)
4769	{
4770	case CPUMCPUIDFEATURE_APIC:
4771	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
4772	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4773	if (pLeaf)
4774	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
4775
4776	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4777	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4778	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4779
4780	pVM->cpum.s.GuestFeatures.fApic = 0;
4781	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4782	break;
4783
4784	case CPUMCPUIDFEATURE_X2APIC:
4785	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4786	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4787	if (pLeaf)
4788	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4789	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4790	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4791	break;
4792
4793	case CPUMCPUIDFEATURE_PAE:
4794	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4795	if (pLeaf)
4796	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4797
4798	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4799	if ( pLeaf
4800	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4801	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4802
4803	pVM->cpum.s.GuestFeatures.fPae = 0;
4804	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4805	break;
4806
4807	case CPUMCPUIDFEATURE_PAT:
4808	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4809	if (pLeaf)
4810	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAT;
4811
4812	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4813	if ( pLeaf
4814	&& pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
4815	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
4816
4817	pVM->cpum.s.GuestFeatures.fPat = 0;
4818	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAT!\n"));
4819	break;
4820
4821	case CPUMCPUIDFEATURE_LONG_MODE:
4822	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4823	if (pLeaf)
4824	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4825	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4826	break;
4827
4828	case CPUMCPUIDFEATURE_LAHF:
4829	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4830	if (pLeaf)
4831	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4832	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4833	break;
4834
4835	case CPUMCPUIDFEATURE_RDTSCP:
4836	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4837	if (pLeaf)
4838	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4839	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4840	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4841	break;
4842
4843	case CPUMCPUIDFEATURE_HVP:
4844	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4845	if (pLeaf)
4846	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4847	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4848	break;
4849
4850	case CPUMCPUIDFEATURE_MWAIT_EXTS:
4851	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000005));
4852	if (pLeaf)
4853	pVM->cpum.s.aGuestCpuIdPatmStd[5].uEcx = pLeaf->uEcx &= ~(X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
4854	pVM->cpum.s.GuestFeatures.fMWaitExtensions = 0;
4855	Log(("CPUM: ClearGuestCpuIdFeature: Disabled MWAIT Extensions!\n"));
4856	break;
4857
4858	case CPUMCPUIDFEATURE_SPEC_CTRL:
4859	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4860	if (pLeaf)
4861	/pVM->cpum.s.aGuestCpuIdPatmStd[7].uEdx =/ pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP \| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
4862	pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
4863	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
4864	break;
4865
4866	default:
4867	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4868	break;
4869	}
4870
4871	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4872	{
4873	PVMCPU pVCpu = &pVM->aCpus[i];
4874	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4875	}
4876	}
4877
4878
4879
4880	/*
4881	*
4882	*
4883	* Saved state related code.
4884	* Saved state related code.
4885	* Saved state related code.
4886	*
4887	*
4888	*/
4889
4890	/**
4891	* Called both in pass 0 and the final pass.
4892	*
4893	* @param pVM The cross context VM structure.
4894	* @param pSSM The saved state handle.
4895	*/
4896	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4897	{
4898	/*
4899	* Save all the CPU ID leaves.
4900	*/
4901	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4902	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4903	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4904	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4905
4906	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4907
4908	/*
4909	* Save a good portion of the raw CPU IDs as well as they may come in
4910	* handy when validating features for raw mode.
4911	*/
4912	CPUMCPUID aRawStd[16];
4913	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4914	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4915	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4916	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4917
4918	CPUMCPUID aRawExt[32];
4919	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4920	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4921	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4922	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4923	}
4924
4925
4926	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4927	{
4928	uint32_t cCpuIds;
4929	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4930	if (RT_SUCCESS(rc))
4931	{
4932	if (cCpuIds < 64)
4933	{
4934	for (uint32_t i = 0; i < cCpuIds; i++)
4935	{
4936	CPUMCPUID CpuId;
4937	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4938	if (RT_FAILURE(rc))
4939	break;
4940
4941	CPUMCPUIDLEAF NewLeaf;
4942	NewLeaf.uLeaf = uBase + i;
4943	NewLeaf.uSubLeaf = 0;
4944	NewLeaf.fSubLeafMask = 0;
4945	NewLeaf.uEax = CpuId.uEax;
4946	NewLeaf.uEbx = CpuId.uEbx;
4947	NewLeaf.uEcx = CpuId.uEcx;
4948	NewLeaf.uEdx = CpuId.uEdx;
4949	NewLeaf.fFlags = 0;
4950	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4951	}
4952	}
4953	else
4954	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4955	}
4956	if (RT_FAILURE(rc))
4957	{
4958	RTMemFree(*ppaLeaves);
4959	*ppaLeaves = NULL;
4960	*pcLeaves = 0;
4961	}
4962	return rc;
4963	}
4964
4965
4966	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4967	{
4968	*ppaLeaves = NULL;
4969	*pcLeaves = 0;
4970
4971	int rc;
4972	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4973	{
4974	/*
4975	* The new format. Starts by declaring the leave size and count.
4976	*/
4977	uint32_t cbLeaf;
4978	SSMR3GetU32(pSSM, &cbLeaf);
4979	uint32_t cLeaves;
4980	rc = SSMR3GetU32(pSSM, &cLeaves);
4981	if (RT_SUCCESS(rc))
4982	{
4983	if (cbLeaf == sizeof(**ppaLeaves))
4984	{
4985	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4986	{
4987	/*
4988	* Load the leaves one by one.
4989	*
4990	* The uPrev stuff is a kludge for working around a week worth of bad saved
4991	* states during the CPUID revamp in March 2015. We saved too many leaves
4992	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4993	* garbage entires at the end of the array when restoring. We also had
4994	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4995	* this kludge doesn't deal correctly with that, but who cares...
4996	*/
4997	uint32_t uPrev = 0;
4998	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4999	{
5000	CPUMCPUIDLEAF Leaf;
5001	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
5002	if (RT_SUCCESS(rc))
5003	{
5004	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
5005	\|\| Leaf.uLeaf >= uPrev)
5006	{
5007	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5008	uPrev = Leaf.uLeaf;
5009	}
5010	else
5011	uPrev = UINT32_MAX;
5012	}
5013	}
5014	}
5015	else
5016	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
5017	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
5018	}
5019	else
5020	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
5021	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
5022	}
5023	}
5024	else
5025	{
5026	/*
5027	* The old format with its three inflexible arrays.
5028	*/
5029	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
5030	if (RT_SUCCESS(rc))
5031	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
5032	if (RT_SUCCESS(rc))
5033	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
5034	if (RT_SUCCESS(rc))
5035	{
5036	/*
5037	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
5038	*/
5039	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(ppaLeaves, pcLeaves, 0, 0);
5040	if ( pLeaf
5041	&& ASMIsIntelCpuEx(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
5042	{
5043	CPUMCPUIDLEAF Leaf;
5044	Leaf.uLeaf = 4;
5045	Leaf.fSubLeafMask = UINT32_MAX;
5046	Leaf.uSubLeaf = 0;
5047	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
5048	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
5049	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
5050	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
5051	\| UINT32_C(63); /* system coherency line size - 1 */
5052	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
5053	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
5054	\| (UINT32_C(1) << 5) /* cache level */
5055	\| UINT32_C(1); /* cache type (data) */
5056	Leaf.fFlags = 0;
5057	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5058	if (RT_SUCCESS(rc))
5059	{
5060	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
5061	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5062	}
5063	if (RT_SUCCESS(rc))
5064	{
5065	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
5066	Leaf.uEcx = 4095; /* sets - 1 */
5067	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
5068	Leaf.uEbx \|= UINT32_C(23) << 22;
5069	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
5070	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
5071	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
5072	Leaf.uEax \|= UINT32_C(2) << 5;
5073	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
5074	}
5075	}
5076	}
5077	}
5078	return rc;
5079	}
5080
5081
5082	/**
5083	* Loads the CPU ID leaves saved by pass 0, inner worker.
5084	*
5085	* @returns VBox status code.
5086	* @param pVM The cross context VM structure.
5087	* @param pSSM The saved state handle.
5088	* @param uVersion The format version.
5089	* @param paLeaves Guest CPUID leaves loaded from the state.
5090	* @param cLeaves The number of leaves in @a paLeaves.
5091	*/
5092	int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
5093	{
5094	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5095
5096	/*
5097	* Continue loading the state into stack buffers.
5098	*/
5099	CPUMCPUID GuestDefCpuId;
5100	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
5101	AssertRCReturn(rc, rc);
5102
5103	CPUMCPUID aRawStd[16];
5104	uint32_t cRawStd;
5105	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
5106	if (cRawStd > RT_ELEMENTS(aRawStd))
5107	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5108	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
5109	AssertRCReturn(rc, rc);
5110	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
5111	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
5112
5113	CPUMCPUID aRawExt[32];
5114	uint32_t cRawExt;
5115	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
5116	if (cRawExt > RT_ELEMENTS(aRawExt))
5117	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5118	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
5119	AssertRCReturn(rc, rc);
5120	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
5121	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
5122
5123	/*
5124	* Get the raw CPU IDs for the current host.
5125	*/
5126	CPUMCPUID aHostRawStd[16];
5127	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
5128	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
5129
5130	CPUMCPUID aHostRawExt[32];
5131	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
5132	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
5133	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
5134
5135	/*
5136	* Get the host and guest overrides so we don't reject the state because
5137	* some feature was enabled thru these interfaces.
5138	* Note! We currently only need the feature leaves, so skip rest.
5139	*/
5140	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
5141	CPUMCPUID aHostOverrideStd[2];
5142	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
5143	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
5144
5145	CPUMCPUID aHostOverrideExt[2];
5146	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
5147	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
5148
5149	/*
5150	* This can be skipped.
5151	*/
5152	bool fStrictCpuIdChecks;
5153	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
5154
5155	/*
5156	* Define a bunch of macros for simplifying the santizing/checking code below.
5157	*/
5158	/* Generic expression + failure message. */
5159	#define CPUID_CHECK_RET(expr, fmt) \
5160	do { \
5161	if (!(expr)) \
5162	{ \
5163	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
5164	if (fStrictCpuIdChecks) \
5165	{ \
5166	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
5167	RTStrFree(pszMsg); \
5168	return rcCpuid; \
5169	} \
5170	LogRel(("CPUM: %s\n", pszMsg)); \
5171	RTStrFree(pszMsg); \
5172	} \
5173	} while (0)
5174	#define CPUID_CHECK_WRN(expr, fmt) \
5175	do { \
5176	if (!(expr)) \
5177	LogRel(fmt); \
5178	} while (0)
5179
5180	/* For comparing two values and bitch if they differs. */
5181	#define CPUID_CHECK2_RET(what, host, saved) \
5182	do { \
5183	if ((host) != (saved)) \
5184	{ \
5185	if (fStrictCpuIdChecks) \
5186	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5187	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
5188	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5189	} \
5190	} while (0)
5191	#define CPUID_CHECK2_WRN(what, host, saved) \
5192	do { \
5193	if ((host) != (saved)) \
5194	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
5195	} while (0)
5196
5197	/* For checking raw cpu features (raw mode). */
5198	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
5199	do { \
5200	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5201	{ \
5202	if (fStrictCpuIdChecks) \
5203	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5204	N_(#bit " mismatch: host=%d saved=%d"), \
5205	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
5206	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5207	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5208	} \
5209	} while (0)
5210	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
5211	do { \
5212	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
5213	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
5214	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
5215	} while (0)
5216	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
5217
5218	/* For checking guest features. */
5219	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
5220	do { \
5221	if ( (aGuestCpuId##set [1].reg & bit) \
5222	&& !(aHostRaw##set [1].reg & bit) \
5223	&& !(aHostOverride##set [1].reg & bit) \
5224	) \
5225	{ \
5226	if (fStrictCpuIdChecks) \
5227	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5228	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5229	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5230	} \
5231	} while (0)
5232	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
5233	do { \
5234	if ( (aGuestCpuId##set [1].reg & bit) \
5235	&& !(aHostRaw##set [1].reg & bit) \
5236	&& !(aHostOverride##set [1].reg & bit) \
5237	) \
5238	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5239	} while (0)
5240	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
5241	do { \
5242	if ( (aGuestCpuId##set [1].reg & bit) \
5243	&& !(aHostRaw##set [1].reg & bit) \
5244	&& !(aHostOverride##set [1].reg & bit) \
5245	) \
5246	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5247	} while (0)
5248	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
5249
5250	/* For checking guest features if AMD guest CPU. */
5251	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
5252	do { \
5253	if ( (aGuestCpuId##set [1].reg & bit) \
5254	&& fGuestAmd \
5255	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5256	&& !(aHostOverride##set [1].reg & bit) \
5257	) \
5258	{ \
5259	if (fStrictCpuIdChecks) \
5260	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5261	N_(#bit " is not supported by the host but has already exposed to the guest")); \
5262	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5263	} \
5264	} while (0)
5265	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
5266	do { \
5267	if ( (aGuestCpuId##set [1].reg & bit) \
5268	&& fGuestAmd \
5269	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5270	&& !(aHostOverride##set [1].reg & bit) \
5271	) \
5272	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
5273	} while (0)
5274	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
5275	do { \
5276	if ( (aGuestCpuId##set [1].reg & bit) \
5277	&& fGuestAmd \
5278	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
5279	&& !(aHostOverride##set [1].reg & bit) \
5280	) \
5281	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5282	} while (0)
5283	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
5284
5285	/* For checking AMD features which have a corresponding bit in the standard
5286	range. (Intel defines very few bits in the extended feature sets.) */
5287	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
5288	do { \
5289	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5290	&& !(fHostAmd \
5291	? aHostRawExt[1].reg & (ExtBit) \
5292	: aHostRawStd[1].reg & (StdBit)) \
5293	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5294	) \
5295	{ \
5296	if (fStrictCpuIdChecks) \
5297	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
5298	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
5299	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5300	} \
5301	} while (0)
5302	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
5303	do { \
5304	if ( (aGuestCpuId[1].reg & (ExtBit)) \
5305	&& !(fHostAmd \
5306	? aHostRawExt[1].reg & (ExtBit) \
5307	: aHostRawStd[1].reg & (StdBit)) \
5308	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5309	) \
5310	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
5311	} while (0)
5312	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
5313	do { \
5314	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
5315	&& !(fHostAmd \
5316	? aHostRawExt[1].reg & (ExtBit) \
5317	: aHostRawStd[1].reg & (StdBit)) \
5318	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
5319	) \
5320	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
5321	} while (0)
5322	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
5323
5324	/*
5325	* For raw-mode we'll require that the CPUs are very similar since we don't
5326	* intercept CPUID instructions for user mode applications.
5327	*/
5328	if (VM_IS_RAW_MODE_ENABLED(pVM))
5329	{
5330	/* CPUID(0) */
5331	CPUID_CHECK_RET( aHostRawStd[0].uEbx == aRawStd[0].uEbx
5332	&& aHostRawStd[0].uEcx == aRawStd[0].uEcx
5333	&& aHostRawStd[0].uEdx == aRawStd[0].uEdx,
5334	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5335	&aHostRawStd[0].uEbx, &aHostRawStd[0].uEdx, &aHostRawStd[0].uEcx,
5336	&aRawStd[0].uEbx, &aRawStd[0].uEdx, &aRawStd[0].uEcx));
5337	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].uEax, aRawStd[0].uEax);
5338	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3);
5339	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5340
5341	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].uEbx, aRawStd[0].uEcx, aRawStd[0].uEdx);
5342
5343	/* CPUID(1).eax */
5344	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].uEax), ASMGetCpuFamily(aRawStd[1].uEax));
5345	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].uEax, fIntel), ASMGetCpuModel(aRawStd[1].uEax, fIntel));
5346	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].uEax >> 12) & 3, (aRawStd[1].uEax >> 12) & 3 );
5347
5348	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
5349	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].uEbx & 0xff, aRawStd[1].uEbx & 0xff);
5350	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].uEbx >> 8) & 0xff, (aRawStd[1].uEbx >> 8) & 0xff);
5351
5352	/* CPUID(1).ecx */
5353	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3);
5354	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL);
5355	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64);
5356	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5357	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS);
5358	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX);
5359	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX);
5360	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_EST);
5361	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2);
5362	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3);
5363	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID);
5364	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(11) /reserved/ );
5365	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA);
5366	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16);
5367	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
5368	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM);
5369	CPUID_RAW_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5370	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5371	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA);
5372	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1);
5373	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2);
5374	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5375	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE);
5376	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT);
5377	CPUID_RAW_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5378	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES);
5379	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE);
5380	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5381	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX);
5382	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5383	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5384	CPUID_RAW_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP);
5385
5386	/* CPUID(1).edx */
5387	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5388	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5389	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE);
5390	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5391	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC);
5392	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR);
5393	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5394	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5395	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8);
5396	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5397	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5398	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5399	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5400	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5401	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5402	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV);
5403	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5404	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5405	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5406	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH);
5407	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5408	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_DS);
5409	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI);
5410	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX);
5411	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR);
5412	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE);
5413	CPUID_RAW_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2);
5414	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SS);
5415	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT);
5416	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_TM);
5417	CPUID_RAW_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/);
5418	CPUID_RAW_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE);
5419
5420	/* CPUID(2) - config, mostly about caches. ignore. */
5421	/* CPUID(3) - processor serial number. ignore. */
5422	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
5423	/* CPUID(5) - mwait/monitor config. ignore. */
5424	/* CPUID(6) - power management. ignore. */
5425	/* CPUID(7) - ???. ignore. */
5426	/* CPUID(8) - ???. ignore. */
5427	/* CPUID(9) - DCA. ignore for now. */
5428	/* CPUID(a) - PeMo info. ignore for now. */
5429	/* CPUID(b) - topology info - takes ECX as input. ignore. */
5430
5431	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
5432	CPUID_CHECK_WRN( aRawStd[0].uEax < UINT32_C(0x0000000d)
5433	\|\| aHostRawStd[0].uEax >= UINT32_C(0x0000000d),
5434	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
5435	if ( aRawStd[0].uEax >= UINT32_C(0x0000000d)
5436	&& aHostRawStd[0].uEax >= UINT32_C(0x0000000d))
5437	{
5438	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].uEax, aRawStd[0xd].uEax);
5439	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].uEdx, aRawStd[0xd].uEdx);
5440	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].uEbx, aRawStd[0xd].uEbx);
5441	/** @todo XSAVE: Stricter XSAVE feature checks for raw-mode. */
5442	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].uEcx, aRawStd[0xd].uEcx);
5443	}
5444
5445	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
5446	Note! Intel have/is marking many of the fields here as reserved. We
5447	will verify them as if it's an AMD CPU. */
5448	CPUID_CHECK_RET( (aHostRawExt[0].uEax >= UINT32_C(0x80000001) && aHostRawExt[0].uEax <= UINT32_C(0x8000007f))
5449	\|\| !(aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f)),
5450	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
5451	if (aRawExt[0].uEax >= UINT32_C(0x80000001) && aRawExt[0].uEax <= UINT32_C(0x8000007f))
5452	{
5453	CPUID_CHECK_RET( aHostRawExt[0].uEbx == aRawExt[0].uEbx
5454	&& aHostRawExt[0].uEcx == aRawExt[0].uEcx
5455	&& aHostRawExt[0].uEdx == aRawExt[0].uEdx,
5456	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
5457	&aHostRawExt[0].uEbx, &aHostRawExt[0].uEdx, &aHostRawExt[0].uEcx,
5458	&aRawExt[0].uEbx, &aRawExt[0].uEdx, &aRawExt[0].uEcx));
5459	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].uEax, aRawExt[0].uEax);
5460
5461	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
5462	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].uEax), ASMGetCpuFamily(aRawExt[1].uEax));
5463	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].uEax, fIntel), ASMGetCpuModel(aRawExt[1].uEax, fIntel));
5464	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].uEax >> 12) & 3, (aRawExt[1].uEax >> 12) & 3 );
5465	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].uEax >> 14) & 3, (aRawExt[1].uEax >> 14) & 3 );
5466	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].uEax >> 28, aRawExt[1].uEax >> 28);
5467
5468	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
5469	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].uEbx & 0xffff, aRawExt[1].uEbx & 0xffff);
5470	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].uEbx >> 16) & 0xfff, (aRawExt[1].uEbx >> 16) & 0xfff);
5471	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].uEbx >> 28) & 0xf, (aRawExt[1].uEbx >> 28) & 0xf);
5472
5473	/* CPUID(0x80000001).ecx */
5474	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
5475	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
5476	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM);
5477	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
5478	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
5479	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM);
5480	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
5481	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
5482	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
5483	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
5484	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS);
5485	CPUID_RAW_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP);
5486	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
5487	CPUID_RAW_FEATURE_IGN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT);
5488	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5489	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5490	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5491	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5492	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5493	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5494	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5495	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5496	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5497	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5498	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5499	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5500	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5501	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5502	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5503	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5504	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5505	CPUID_RAW_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5506
5507	/* CPUID(0x80000001).edx */
5508	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU);
5509	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_VME);
5510	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_DE);
5511	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE);
5512	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC);
5513	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR);
5514	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE);
5515	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE);
5516	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8);
5517	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC);
5518	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5519	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SEP);
5520	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
5521	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE);
5522	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA);
5523	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
5524	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT);
5525	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
5526	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5527	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5528	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5529	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(21) /reserved/);
5530	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5531	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX);
5532	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
5533	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5534	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5535	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5536	CPUID_RAW_FEATURE_IGN(Ext, uEdx, RT_BIT_32(28) /reserved/);
5537	CPUID_RAW_FEATURE_IGN(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5538	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5539	CPUID_RAW_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5540
5541	/** @todo verify the rest as well. */
5542	}
5543	}
5544
5545
5546
5547	/*
5548	* Verify that we can support the features already exposed to the guest on
5549	* this host.
5550	*
5551	* Most of the features we're emulating requires intercepting instruction
5552	* and doing it the slow way, so there is no need to warn when they aren't
5553	* present in the host CPU. Thus we use IGN instead of EMU on these.
5554	*
5555	* Trailing comments:
5556	* "EMU" - Possible to emulate, could be lots of work and very slow.
5557	* "EMU?" - Can this be emulated?
5558	*/
5559	CPUMCPUID aGuestCpuIdStd[2];
5560	RT_ZERO(aGuestCpuIdStd);
5561	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
5562
5563	/* CPUID(1).ecx */
5564	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
5565	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
5566	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
5567	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
5568	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
5569	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
5570	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
5571	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
5572	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
5573	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
5574	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
5575	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
5576	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
5577	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
5578	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
5579	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
5580	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
5581	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
5582	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
5583	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
5584	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
5585	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
5586	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
5587	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
5588	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
5589	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
5590	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
5591	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
5592	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
5593	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
5594	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
5595	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
5596
5597	/* CPUID(1).edx */
5598	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
5599	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
5600	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
5601	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
5602	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5603	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5604	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
5605	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
5606	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5607	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
5608	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
5609	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
5610	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
5611	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
5612	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
5613	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5614	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
5615	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
5616	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
5617	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
5618	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
5619	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
5620	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
5621	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5622	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5623	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
5624	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
5625	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
5626	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
5627	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
5628	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
5629	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
5630
5631	/* CPUID(0x80000000). */
5632	CPUMCPUID aGuestCpuIdExt[2];
5633	RT_ZERO(aGuestCpuIdExt);
5634	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
5635	{
5636	/** @todo deal with no 0x80000001 on the host. */
5637	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
5638	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
5639
5640	/* CPUID(0x80000001).ecx */
5641	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
5642	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
5643	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
5644	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
5645	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
5646	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
5647	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
5648	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
5649	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
5650	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
5651	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
5652	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
5653	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
5654	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
5655	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
5656	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
5657	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
5658	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
5659	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
5660	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
5661	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
5662	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
5663	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
5664	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
5665	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
5666	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
5667	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
5668	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
5669	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
5670	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
5671	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
5672	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
5673
5674	/* CPUID(0x80000001).edx */
5675	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
5676	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
5677	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
5678	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
5679	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
5680	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
5681	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
5682	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
5683	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
5684	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
5685	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
5686	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
5687	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
5688	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
5689	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
5690	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
5691	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
5692	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
5693	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
5694	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
5695	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
5696	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
5697	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
5698	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
5699	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
5700	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
5701	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
5702	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
5703	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
5704	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
5705	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
5706	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
5707	}
5708
5709	/** @todo check leaf 7 */
5710
5711	/* CPUID(d) - XCR0 stuff - takes ECX as input.
5712	* ECX=0: EAX - Valid bits in XCR0[31:0].
5713	* EBX - Maximum state size as per current XCR0 value.
5714	* ECX - Maximum state size for all supported features.
5715	* EDX - Valid bits in XCR0[63:32].
5716	* ECX=1: EAX - Various X-features.
5717	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
5718	* ECX - Valid bits in IA32_XSS[31:0].
5719	* EDX - Valid bits in IA32_XSS[63:32].
5720	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
5721	* if the bit invalid all four registers are set to zero.
5722	* EAX - The state size for this feature.
5723	* EBX - The state byte offset of this feature.
5724	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
5725	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
5726	*/
5727	uint64_t fGuestXcr0Mask = 0;
5728	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
5729	if ( pCurLeaf
5730	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
5731	&& ( pCurLeaf->uEax
5732	\|\| pCurLeaf->uEbx
5733	\|\| pCurLeaf->uEcx
5734	\|\| pCurLeaf->uEdx) )
5735	{
5736	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
5737	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
5738	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5739	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
5740	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
5741	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
5742	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5743	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
5744
5745	/* We don't support any additional features yet. */
5746	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
5747	if (pCurLeaf && pCurLeaf->uEax)
5748	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5749	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
5750	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
5751	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5752	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
5753	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
5754
5755
5756	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
5757	{
5758	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5759	if (pCurLeaf)
5760	{
5761	/* If advertised, the state component offset and size must match the one used by host. */
5762	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
5763	{
5764	CPUMCPUID RawHost;
5765	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
5766	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
5767	if ( RawHost.uEbx != pCurLeaf->uEbx
5768	\|\| RawHost.uEax != pCurLeaf->uEax)
5769	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5770	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
5771	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
5772	}
5773	}
5774	}
5775	}
5776	/* Clear leaf 0xd just in case we're loading an old state... */
5777	else if (pCurLeaf)
5778	{
5779	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5780	{
5781	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
5782	if (pCurLeaf)
5783	{
5784	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
5785	\|\| ( pCurLeaf->uEax == 0
5786	&& pCurLeaf->uEbx == 0
5787	&& pCurLeaf->uEcx == 0
5788	&& pCurLeaf->uEdx == 0),
5789	("uVersion=%#x; %#x %#x %#x %#x\n",
5790	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
5791	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
5792	}
5793	}
5794	}
5795
5796	/* Update the fXStateGuestMask value for the VM. */
5797	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
5798	{
5799	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
5800	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
5801	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
5802	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
5803	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
5804	}
5805
5806	#undef CPUID_CHECK_RET
5807	#undef CPUID_CHECK_WRN
5808	#undef CPUID_CHECK2_RET
5809	#undef CPUID_CHECK2_WRN
5810	#undef CPUID_RAW_FEATURE_RET
5811	#undef CPUID_RAW_FEATURE_WRN
5812	#undef CPUID_RAW_FEATURE_IGN
5813	#undef CPUID_GST_FEATURE_RET
5814	#undef CPUID_GST_FEATURE_WRN
5815	#undef CPUID_GST_FEATURE_EMU
5816	#undef CPUID_GST_FEATURE_IGN
5817	#undef CPUID_GST_FEATURE2_RET
5818	#undef CPUID_GST_FEATURE2_WRN
5819	#undef CPUID_GST_FEATURE2_EMU
5820	#undef CPUID_GST_FEATURE2_IGN
5821	#undef CPUID_GST_AMD_FEATURE_RET
5822	#undef CPUID_GST_AMD_FEATURE_WRN
5823	#undef CPUID_GST_AMD_FEATURE_EMU
5824	#undef CPUID_GST_AMD_FEATURE_IGN
5825
5826	/*
5827	* We're good, commit the CPU ID leaves.
5828	*/
5829	MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
5830	pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 = NULL;
5831	pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
5832	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
5833	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
5834	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
5835	AssertLogRelRCReturn(rc, rc);
5836
5837	return VINF_SUCCESS;
5838	}
5839
5840
5841	/**
5842	* Loads the CPU ID leaves saved by pass 0.
5843	*
5844	* @returns VBox status code.
5845	* @param pVM The cross context VM structure.
5846	* @param pSSM The saved state handle.
5847	* @param uVersion The format version.
5848	*/
5849	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5850	{
5851	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5852
5853	/*
5854	* Load the CPUID leaves array first and call worker to do the rest, just so
5855	* we can free the memory when we need to without ending up in column 1000.
5856	*/
5857	PCPUMCPUIDLEAF paLeaves;
5858	uint32_t cLeaves;
5859	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
5860	AssertRC(rc);
5861	if (RT_SUCCESS(rc))
5862	{
5863	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves);
5864	RTMemFree(paLeaves);
5865	}
5866	return rc;
5867	}
5868
5869
5870
5871	/**
5872	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
5873	*
5874	* @returns VBox status code.
5875	* @param pVM The cross context VM structure.
5876	* @param pSSM The saved state handle.
5877	* @param uVersion The format version.
5878	*/
5879	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
5880	{
5881	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
5882
5883	/*
5884	* Restore the CPUID leaves.
5885	*
5886	* Note that we support restoring less than the current amount of standard
5887	* leaves because we've been allowed more is newer version of VBox.
5888	*/
5889	uint32_t cElements;
5890	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5891	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
5892	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5893	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
5894
5895	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5896	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
5897	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5898	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
5899
5900	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
5901	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
5902	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
5903	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
5904
5905	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
5906
5907	/*
5908	* Check that the basic cpuid id information is unchanged.
5909	*/
5910	/** @todo we should check the 64 bits capabilities too! */
5911	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
5912	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
5913	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
5914	uint32_t au32CpuIdSaved[8];
5915	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
5916	if (RT_SUCCESS(rc))
5917	{
5918	/* Ignore CPU stepping. */
5919	au32CpuId[4] &= 0xfffffff0;
5920	au32CpuIdSaved[4] &= 0xfffffff0;
5921
5922	/* Ignore APIC ID (AMD specs). */
5923	au32CpuId[5] &= ~0xff000000;
5924	au32CpuIdSaved[5] &= ~0xff000000;
5925
5926	/* Ignore the number of Logical CPUs (AMD specs). */
5927	au32CpuId[5] &= ~0x00ff0000;
5928	au32CpuIdSaved[5] &= ~0x00ff0000;
5929
5930	/* Ignore some advanced capability bits, that we don't expose to the guest. */
5931	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5932	\| X86_CPUID_FEATURE_ECX_VMX
5933	\| X86_CPUID_FEATURE_ECX_SMX
5934	\| X86_CPUID_FEATURE_ECX_EST
5935	\| X86_CPUID_FEATURE_ECX_TM2
5936	\| X86_CPUID_FEATURE_ECX_CNTXID
5937	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5938	\| X86_CPUID_FEATURE_ECX_PDCM
5939	\| X86_CPUID_FEATURE_ECX_DCA
5940	\| X86_CPUID_FEATURE_ECX_X2APIC
5941	);
5942	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
5943	\| X86_CPUID_FEATURE_ECX_VMX
5944	\| X86_CPUID_FEATURE_ECX_SMX
5945	\| X86_CPUID_FEATURE_ECX_EST
5946	\| X86_CPUID_FEATURE_ECX_TM2
5947	\| X86_CPUID_FEATURE_ECX_CNTXID
5948	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5949	\| X86_CPUID_FEATURE_ECX_PDCM
5950	\| X86_CPUID_FEATURE_ECX_DCA
5951	\| X86_CPUID_FEATURE_ECX_X2APIC
5952	);
5953
5954	/* Make sure we don't forget to update the masks when enabling
5955	* features in the future.
5956	*/
5957	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5958	( X86_CPUID_FEATURE_ECX_DTES64
5959	\| X86_CPUID_FEATURE_ECX_VMX
5960	\| X86_CPUID_FEATURE_ECX_SMX
5961	\| X86_CPUID_FEATURE_ECX_EST
5962	\| X86_CPUID_FEATURE_ECX_TM2
5963	\| X86_CPUID_FEATURE_ECX_CNTXID
5964	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5965	\| X86_CPUID_FEATURE_ECX_PDCM
5966	\| X86_CPUID_FEATURE_ECX_DCA
5967	\| X86_CPUID_FEATURE_ECX_X2APIC
5968	)));
5969	/* do the compare */
5970	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5971	{
5972	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5973	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5974	"Saved=%.*Rhxs\n"
5975	"Real =%.*Rhxs\n",
5976	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5977	sizeof(au32CpuId), au32CpuId));
5978	else
5979	{
5980	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5981	"Saved=%.*Rhxs\n"
5982	"Real =%.*Rhxs\n",
5983	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5984	sizeof(au32CpuId), au32CpuId));
5985	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5986	}
5987	}
5988	}
5989
5990	return rc;
5991	}
5992
5993
5994
5995	/*
5996	*
5997	*
5998	* CPUID Info Handler.
5999	* CPUID Info Handler.
6000	* CPUID Info Handler.
6001	*
6002	*
6003	*/
6004
6005
6006
6007	/**
6008	* Get L1 cache / TLS associativity.
6009	*/
6010	static const char getCacheAss(unsigned u, char pszBuf)
6011	{
6012	if (u == 0)
6013	return "res0 ";
6014	if (u == 1)
6015	return "direct";
6016	if (u == 255)
6017	return "fully";
6018	if (u >= 256)
6019	return "???";
6020
6021	RTStrPrintf(pszBuf, 16, "%d way", u);
6022	return pszBuf;
6023	}
6024
6025
6026	/**
6027	* Get L2 cache associativity.
6028	*/
6029	const char *getL2CacheAss(unsigned u)
6030	{
6031	switch (u)
6032	{
6033	case 0: return "off ";
6034	case 1: return "direct";
6035	case 2: return "2 way ";
6036	case 3: return "res3 ";
6037	case 4: return "4 way ";
6038	case 5: return "res5 ";
6039	case 6: return "8 way ";
6040	case 7: return "res7 ";
6041	case 8: return "16 way";
6042	case 9: return "res9 ";
6043	case 10: return "res10 ";
6044	case 11: return "res11 ";
6045	case 12: return "res12 ";
6046	case 13: return "res13 ";
6047	case 14: return "res14 ";
6048	case 15: return "fully ";
6049	default: return "????";
6050	}
6051	}
6052
6053
6054	/** CPUID(1).EDX field descriptions. */
6055	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
6056	{
6057	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6058	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6059	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6060	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6061	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6062	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
6063	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6064	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6065	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6066	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6067	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
6068	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6069	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6070	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6071	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6072	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6073	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6074	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
6075	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
6076	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
6077	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
6078	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6079	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
6080	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
6081	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
6082	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
6083	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
6084	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
6085	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
6086	DBGFREGSUBFIELD_TERMINATOR()
6087	};
6088
6089	/** CPUID(1).ECX field descriptions. */
6090	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
6091	{
6092	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
6093	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
6094	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
6095	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
6096	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
6097	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
6098	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
6099	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
6100	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
6101	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
6102	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
6103	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
6104	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
6105	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
6106	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
6107	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
6108	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
6109	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
6110	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
6111	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
6112	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
6113	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
6114	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
6115	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
6116	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
6117	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
6118	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
6119	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
6120	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
6121	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
6122	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
6123	DBGFREGSUBFIELD_TERMINATOR()
6124	};
6125
6126	/** CPUID(7,0).EBX field descriptions. */
6127	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
6128	{
6129	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
6130	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
6131	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
6132	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
6133	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
6134	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
6135	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
6136	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
6137	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
6138	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
6139	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
6140	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
6141	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
6142	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
6143	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
6144	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
6145	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
6146	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
6147	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
6148	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
6149	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
6150	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
6151	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
6152	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
6153	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
6154	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
6155	DBGFREGSUBFIELD_TERMINATOR()
6156	};
6157
6158	/** CPUID(7,0).ECX field descriptions. */
6159	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
6160	{
6161	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
6162	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
6163	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
6164	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
6165	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
6166	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
6167	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
6168	DBGFREGSUBFIELD_TERMINATOR()
6169	};
6170
6171	/** CPUID(7,0).EDX field descriptions. */
6172	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
6173	{
6174	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
6175	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
6176	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
6177	DBGFREGSUBFIELD_TERMINATOR()
6178	};
6179
6180
6181	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
6182	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
6183	{
6184	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
6185	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
6186	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
6187	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
6188	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
6189	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
6190	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
6191	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
6192	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
6193	DBGFREGSUBFIELD_TERMINATOR()
6194	};
6195
6196	/** CPUID(13,1).EAX field descriptions. */
6197	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
6198	{
6199	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
6200	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
6201	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
6202	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
6203	DBGFREGSUBFIELD_TERMINATOR()
6204	};
6205
6206
6207	/** CPUID(0x80000001,0).EDX field descriptions. */
6208	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
6209	{
6210	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
6211	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
6212	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
6213	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
6214	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
6215	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
6216	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
6217	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
6218	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
6219	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
6220	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
6221	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
6222	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
6223	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
6224	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
6225	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
6226	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
6227	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
6228	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
6229	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
6230	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
6231	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
6232	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
6233	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
6234	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
6235	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
6236	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
6237	DBGFREGSUBFIELD_TERMINATOR()
6238	};
6239
6240	/** CPUID(0x80000001,0).ECX field descriptions. */
6241	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
6242	{
6243	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
6244	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
6245	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
6246	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
6247	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
6248	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
6249	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
6250	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
6251	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
6252	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
6253	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
6254	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
6255	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
6256	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
6257	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
6258	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
6259	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
6260	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
6261	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
6262	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
6263	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
6264	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
6265	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
6266	DBGFREGSUBFIELD_TERMINATOR()
6267	};
6268
6269	/** CPUID(0x8000000a,0).EDX field descriptions. */
6270	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
6271	{
6272	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
6273	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
6274	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
6275	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
6276	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
6277	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
6278	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
6279	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
6280	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
6281	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
6282	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
6283	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
6284	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
6285	DBGFREGSUBFIELD_TERMINATOR()
6286	};
6287
6288
6289	/** CPUID(0x80000007,0).EDX field descriptions. */
6290	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
6291	{
6292	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
6293	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
6294	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6295	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
6296	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
6297	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
6298	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
6299	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
6300	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
6301	DBGFREGSUBFIELD_RO("CBP\0" "Core Performance Boost", 9, 1, 0),
6302	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
6303	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
6304	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
6305	DBGFREGSUBFIELD_TERMINATOR()
6306	};
6307
6308	/** CPUID(0x80000008,0).EBX field descriptions. */
6309	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
6310	{
6311	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
6312	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
6313	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR*)", 2, 1, 0),
6314	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
6315	DBGFREGSUBFIELD_TERMINATOR()
6316	};
6317
6318
6319	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
6320	const char *pszLeadIn, uint32_t cchWidth)
6321	{
6322	if (pszLeadIn)
6323	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6324
6325	for (uint32_t iBit = 0; iBit < 32; iBit++)
6326	if (RT_BIT_32(iBit) & uVal)
6327	{
6328	while ( pDesc->pszName != NULL
6329	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6330	pDesc++;
6331	if ( pDesc->pszName != NULL
6332	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6333	{
6334	if (pDesc->cBits == 1)
6335	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6336	else
6337	{
6338	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
6339	if (pDesc->cBits < 32)
6340	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6341	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
6342	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6343	}
6344	}
6345	else
6346	pHlp->pfnPrintf(pHlp, " %u", iBit);
6347	}
6348	if (pszLeadIn)
6349	pHlp->pfnPrintf(pHlp, "\n");
6350	}
6351
6352
6353	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6354	const char *pszLeadIn, uint32_t cchWidth)
6355	{
6356	if (pszLeadIn)
6357	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
6358
6359	for (uint32_t iBit = 0; iBit < 64; iBit++)
6360	if (RT_BIT_64(iBit) & uVal)
6361	{
6362	while ( pDesc->pszName != NULL
6363	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6364	pDesc++;
6365	if ( pDesc->pszName != NULL
6366	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6367	{
6368	if (pDesc->cBits == 1)
6369	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
6370	else
6371	{
6372	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
6373	if (pDesc->cBits < 64)
6374	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
6375	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
6376	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
6377	}
6378	}
6379	else
6380	pHlp->pfnPrintf(pHlp, " %u", iBit);
6381	}
6382	if (pszLeadIn)
6383	pHlp->pfnPrintf(pHlp, "\n");
6384	}
6385
6386
6387	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
6388	const char *pszLeadIn, uint32_t cchWidth)
6389	{
6390	if (!uVal)
6391	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6392	else
6393	{
6394	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
6395	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
6396	pHlp->pfnPrintf(pHlp, " )\n");
6397	}
6398	}
6399
6400
6401	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
6402	uint32_t cchWidth)
6403	{
6404	uint32_t uCombined = uVal1 \| uVal2;
6405	for (uint32_t iBit = 0; iBit < 32; iBit++)
6406	if ( (RT_BIT_32(iBit) & uCombined)
6407	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
6408	{
6409	while ( pDesc->pszName != NULL
6410	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
6411	pDesc++;
6412
6413	if ( pDesc->pszName != NULL
6414	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
6415	{
6416	size_t cchMnemonic = strlen(pDesc->pszName);
6417	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
6418	size_t cchDesc = strlen(pszDesc);
6419	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
6420	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
6421	if (pDesc->cBits < 32)
6422	{
6423	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6424	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
6425	}
6426
6427	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
6428	pDesc->pszName, pszDesc,
6429	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
6430	uFieldValue1, uFieldValue2);
6431
6432	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
6433	pDesc++;
6434	}
6435	else
6436	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
6437	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
6438	}
6439	}
6440
6441
6442	/**
6443	* Produces a detailed summary of standard leaf 0x00000001.
6444	*
6445	* @param pHlp The info helper functions.
6446	* @param pCurLeaf The 0x00000001 leaf.
6447	* @param fVerbose Whether to be very verbose or not.
6448	* @param fIntel Set if intel CPU.
6449	*/
6450	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
6451	{
6452	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
6453	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
6454	uint32_t uEAX = pCurLeaf->uEax;
6455	uint32_t uEBX = pCurLeaf->uEbx;
6456
6457	pHlp->pfnPrintf(pHlp,
6458	"%36s %2d \tExtended: %d \tEffective: %d\n"
6459	"%36s %2d \tExtended: %d \tEffective: %d\n"
6460	"%36s %d\n"
6461	"%36s %d (%s)\n"
6462	"%36s %#04x\n"
6463	"%36s %d\n"
6464	"%36s %d\n"
6465	"%36s %#04x\n"
6466	,
6467	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6468	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6469	"Stepping:", ASMGetCpuStepping(uEAX),
6470	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
6471	"APIC ID:", (uEBX >> 24) & 0xff,
6472	"Logical CPUs:",(uEBX >> 16) & 0xff,
6473	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
6474	"Brand ID:", (uEBX >> 0) & 0xff);
6475	if (fVerbose)
6476	{
6477	CPUMCPUID Host;
6478	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6479	pHlp->pfnPrintf(pHlp, "Features\n");
6480	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6481	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
6482	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
6483	}
6484	else
6485	{
6486	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
6487	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
6488	}
6489	}
6490
6491
6492	/**
6493	* Produces a detailed summary of standard leaf 0x00000007.
6494	*
6495	* @param pHlp The info helper functions.
6496	* @param paLeaves The CPUID leaves array.
6497	* @param cLeaves The number of leaves in the array.
6498	* @param pCurLeaf The first 0x00000007 leaf.
6499	* @param fVerbose Whether to be very verbose or not.
6500	*/
6501	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6502	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6503	{
6504	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
6505	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
6506	for (;;)
6507	{
6508	CPUMCPUID Host;
6509	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6510
6511	switch (pCurLeaf->uSubLeaf)
6512	{
6513	case 0:
6514	if (fVerbose)
6515	{
6516	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6517	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
6518	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
6519	if (pCurLeaf->uEdx \|\| Host.uEdx)
6520	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
6521	}
6522	else
6523	{
6524	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
6525	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
6526	if (pCurLeaf->uEdx)
6527	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
6528	}
6529	break;
6530
6531	default:
6532	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
6533	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
6534	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
6535	break;
6536
6537	}
6538
6539	/* advance. */
6540	pCurLeaf++;
6541	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6542	\|\| pCurLeaf->uLeaf != 0x7)
6543	break;
6544	}
6545	}
6546
6547
6548	/**
6549	* Produces a detailed summary of standard leaf 0x0000000d.
6550	*
6551	* @param pHlp The info helper functions.
6552	* @param paLeaves The CPUID leaves array.
6553	* @param cLeaves The number of leaves in the array.
6554	* @param pCurLeaf The first 0x00000007 leaf.
6555	* @param fVerbose Whether to be very verbose or not.
6556	*/
6557	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6558	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
6559	{
6560	RT_NOREF_PV(fVerbose);
6561	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
6562	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
6563	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
6564	{
6565	CPUMCPUID Host;
6566	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6567
6568	switch (uSubLeaf)
6569	{
6570	case 0:
6571	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6572	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
6573	pCurLeaf->uEbx, pCurLeaf->uEcx);
6574	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
6575
6576	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6577	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
6578	"Valid XCR0 bits, guest:", 42);
6579	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
6580	"Valid XCR0 bits, host:", 42);
6581	break;
6582
6583	case 1:
6584	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6585	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
6586	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
6587
6588	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6589	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
6590	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
6591
6592	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
6593	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
6594	" Valid IA32_XSS bits, guest:", 42);
6595	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
6596	" Valid IA32_XSS bits, host:", 42);
6597	break;
6598
6599	default:
6600	if ( pCurLeaf
6601	&& pCurLeaf->uSubLeaf == uSubLeaf
6602	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
6603	{
6604	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
6605	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6606	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
6607	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
6608	if (pCurLeaf->uEdx)
6609	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
6610	pHlp->pfnPrintf(pHlp, " --");
6611	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6612	pHlp->pfnPrintf(pHlp, "\n");
6613	}
6614	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
6615	{
6616	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
6617	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
6618	if (Host.uEcx & ~RT_BIT_32(0))
6619	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
6620	if (Host.uEdx)
6621	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
6622	pHlp->pfnPrintf(pHlp, " --");
6623	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
6624	pHlp->pfnPrintf(pHlp, "\n");
6625	}
6626	break;
6627
6628	}
6629
6630	/* advance. */
6631	if (pCurLeaf)
6632	{
6633	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6634	&& pCurLeaf->uSubLeaf <= uSubLeaf
6635	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
6636	pCurLeaf++;
6637	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6638	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
6639	pCurLeaf = NULL;
6640	}
6641	}
6642	}
6643
6644
6645	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
6646	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
6647	{
6648	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6649	&& pCurLeaf->uLeaf <= uUpToLeaf)
6650	{
6651	pHlp->pfnPrintf(pHlp,
6652	" %s\n"
6653	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
6654	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6655	&& pCurLeaf->uLeaf <= uUpToLeaf)
6656	{
6657	CPUMCPUID Host;
6658	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6659	pHlp->pfnPrintf(pHlp,
6660	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6661	"Hst: %08x %08x %08x %08x\n",
6662	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6663	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6664	pCurLeaf++;
6665	}
6666	}
6667
6668	return pCurLeaf;
6669	}
6670
6671
6672	/**
6673	* Display the guest CpuId leaves.
6674	*
6675	* @param pVM The cross context VM structure.
6676	* @param pHlp The info helper functions.
6677	* @param pszArgs "terse", "default" or "verbose".
6678	*/
6679	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
6680	{
6681	/*
6682	* Parse the argument.
6683	*/
6684	unsigned iVerbosity = 1;
6685	if (pszArgs)
6686	{
6687	pszArgs = RTStrStripL(pszArgs);
6688	if (!strcmp(pszArgs, "terse"))
6689	iVerbosity--;
6690	else if (!strcmp(pszArgs, "verbose"))
6691	iVerbosity++;
6692	}
6693
6694	uint32_t uLeaf;
6695	CPUMCPUID Host;
6696	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
6697	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
6698	PCCPUMCPUIDLEAF pCurLeaf;
6699	PCCPUMCPUIDLEAF pNextLeaf;
6700	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
6701	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
6702	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
6703
6704	/*
6705	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
6706	*/
6707	uint32_t cHstMax = ASMCpuId_EAX(0);
6708	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
6709	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
6710	pHlp->pfnPrintf(pHlp,
6711	" Raw Standard CPUID Leaves\n"
6712	" Leaf/sub-leaf eax ebx ecx edx\n");
6713	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
6714	{
6715	uint32_t cMaxSubLeaves = 1;
6716	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
6717	cMaxSubLeaves = 16;
6718	else if (uLeaf == 0xd)
6719	cMaxSubLeaves = 128;
6720
6721	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6722	{
6723	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6724	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6725	&& pCurLeaf->uLeaf == uLeaf
6726	&& pCurLeaf->uSubLeaf == uSubLeaf)
6727	{
6728	pHlp->pfnPrintf(pHlp,
6729	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6730	"Hst: %08x %08x %08x %08x\n",
6731	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6732	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6733	pCurLeaf++;
6734	}
6735	else if ( uLeaf != 0xd
6736	\|\| uSubLeaf <= 1
6737	\|\| Host.uEbx != 0 )
6738	pHlp->pfnPrintf(pHlp,
6739	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6740	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6741
6742	/* Done? */
6743	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6744	\|\| pCurLeaf->uLeaf != uLeaf)
6745	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
6746	\|\| (uLeaf == 0x7 && Host.uEax == 0)
6747	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
6748	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
6749	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
6750	)
6751	)
6752	break;
6753	}
6754	}
6755	pNextLeaf = pCurLeaf;
6756
6757	/*
6758	* If verbose, decode it.
6759	*/
6760	if (iVerbosity && paLeaves[0].uLeaf == 0)
6761	pHlp->pfnPrintf(pHlp,
6762	"%36s %.04s%.04s%.04s\n"
6763	"%36s 0x00000000-%#010x\n"
6764	,
6765	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
6766	"Supports:", paLeaves[0].uEax);
6767
6768	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
6769	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
6770
6771	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
6772	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6773
6774	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
6775	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
6776
6777	pCurLeaf = pNextLeaf;
6778
6779	/*
6780	* Hypervisor leaves.
6781	*
6782	* Unlike most of the other leaves reported, the guest hypervisor leaves
6783	* aren't a subset of the host CPUID bits.
6784	*/
6785	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
6786
6787	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6788	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
6789	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
6790	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
6791	cMax = RT_MAX(cHstMax, cGstMax);
6792	if (cMax >= UINT32_C(0x40000000))
6793	{
6794	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
6795
6796	/** @todo dump these in more detail. */
6797
6798	pCurLeaf = pNextLeaf;
6799	}
6800
6801
6802	/*
6803	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
6804	* Implemented after AMD specs.
6805	*/
6806	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
6807
6808	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6809	cHstMax = ASMIsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
6810	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
6811	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
6812	cMax = RT_MAX(cHstMax, cGstMax);
6813	if (cMax >= UINT32_C(0x80000000))
6814	{
6815
6816	pHlp->pfnPrintf(pHlp,
6817	" Raw Extended CPUID Leaves\n"
6818	" Leaf/sub-leaf eax ebx ecx edx\n");
6819	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
6820	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
6821	{
6822	uint32_t cMaxSubLeaves = 1;
6823	if (uLeaf == UINT32_C(0x8000001d))
6824	cMaxSubLeaves = 16;
6825
6826	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
6827	{
6828	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6829	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
6830	&& pCurLeaf->uLeaf == uLeaf
6831	&& pCurLeaf->uSubLeaf == uSubLeaf)
6832	{
6833	pHlp->pfnPrintf(pHlp,
6834	"Gst: %08x/%04x %08x %08x %08x %08x\n"
6835	"Hst: %08x %08x %08x %08x\n",
6836	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
6837	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6838	pCurLeaf++;
6839	}
6840	else if ( uLeaf != 0xd
6841	\|\| uSubLeaf <= 1
6842	\|\| Host.uEbx != 0 )
6843	pHlp->pfnPrintf(pHlp,
6844	"Hst: %08x/%04x %08x %08x %08x %08x\n",
6845	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
6846
6847	/* Done? */
6848	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
6849	\|\| pCurLeaf->uLeaf != uLeaf)
6850	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
6851	break;
6852	}
6853	}
6854	pNextLeaf = pCurLeaf;
6855
6856	/*
6857	* Understandable output
6858	*/
6859	if (iVerbosity)
6860	pHlp->pfnPrintf(pHlp,
6861	"Ext Name: %.4s%.4s%.4s\n"
6862	"Ext Supports: 0x80000000-%#010x\n",
6863	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
6864
6865	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
6866	if (iVerbosity && pCurLeaf)
6867	{
6868	uint32_t uEAX = pCurLeaf->uEax;
6869	pHlp->pfnPrintf(pHlp,
6870	"Family: %d \tExtended: %d \tEffective: %d\n"
6871	"Model: %d \tExtended: %d \tEffective: %d\n"
6872	"Stepping: %d\n"
6873	"Brand ID: %#05x\n",
6874	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
6875	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
6876	ASMGetCpuStepping(uEAX),
6877	pCurLeaf->uEbx & 0xfff);
6878
6879	if (iVerbosity == 1)
6880	{
6881	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
6882	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
6883	}
6884	else
6885	{
6886	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6887	pHlp->pfnPrintf(pHlp, "Ext Features\n");
6888	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
6889	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
6890	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
6891	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
6892	{
6893	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6894	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6895	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6896	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6897	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6898	}
6899	}
6900	}
6901
6902	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6903	{
6904	char szString[443+1] = {0};
6905	uint32_t pu32 = (uint32_t )szString;
6906	*pu32++ = pCurLeaf->uEax;
6907	*pu32++ = pCurLeaf->uEbx;
6908	*pu32++ = pCurLeaf->uEcx;
6909	*pu32++ = pCurLeaf->uEdx;
6910	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6911	if (pCurLeaf)
6912	{
6913	*pu32++ = pCurLeaf->uEax;
6914	*pu32++ = pCurLeaf->uEbx;
6915	*pu32++ = pCurLeaf->uEcx;
6916	*pu32++ = pCurLeaf->uEdx;
6917	}
6918	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6919	if (pCurLeaf)
6920	{
6921	*pu32++ = pCurLeaf->uEax;
6922	*pu32++ = pCurLeaf->uEbx;
6923	*pu32++ = pCurLeaf->uEcx;
6924	*pu32++ = pCurLeaf->uEdx;
6925	}
6926	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6927	}
6928
6929	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6930	{
6931	uint32_t uEAX = pCurLeaf->uEax;
6932	uint32_t uEBX = pCurLeaf->uEbx;
6933	uint32_t uECX = pCurLeaf->uEcx;
6934	uint32_t uEDX = pCurLeaf->uEdx;
6935	char sz1[32];
6936	char sz2[32];
6937
6938	pHlp->pfnPrintf(pHlp,
6939	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6940	"TLB 2/4M Data: %s %3d entries\n",
6941	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6942	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6943	pHlp->pfnPrintf(pHlp,
6944	"TLB 4K Instr/Uni: %s %3d entries\n"
6945	"TLB 4K Data: %s %3d entries\n",
6946	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6947	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6948	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6949	"L1 Instr Cache Lines Per Tag: %d\n"
6950	"L1 Instr Cache Associativity: %s\n"
6951	"L1 Instr Cache Size: %d KB\n",
6952	(uEDX >> 0) & 0xff,
6953	(uEDX >> 8) & 0xff,
6954	getCacheAss((uEDX >> 16) & 0xff, sz1),
6955	(uEDX >> 24) & 0xff);
6956	pHlp->pfnPrintf(pHlp,
6957	"L1 Data Cache Line Size: %d bytes\n"
6958	"L1 Data Cache Lines Per Tag: %d\n"
6959	"L1 Data Cache Associativity: %s\n"
6960	"L1 Data Cache Size: %d KB\n",
6961	(uECX >> 0) & 0xff,
6962	(uECX >> 8) & 0xff,
6963	getCacheAss((uECX >> 16) & 0xff, sz1),
6964	(uECX >> 24) & 0xff);
6965	}
6966
6967	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6968	{
6969	uint32_t uEAX = pCurLeaf->uEax;
6970	uint32_t uEBX = pCurLeaf->uEbx;
6971	uint32_t uEDX = pCurLeaf->uEdx;
6972
6973	pHlp->pfnPrintf(pHlp,
6974	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6975	"L2 TLB 2/4M Data: %s %4d entries\n",
6976	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6977	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6978	pHlp->pfnPrintf(pHlp,
6979	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6980	"L2 TLB 4K Data: %s %4d entries\n",
6981	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6982	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6983	pHlp->pfnPrintf(pHlp,
6984	"L2 Cache Line Size: %d bytes\n"
6985	"L2 Cache Lines Per Tag: %d\n"
6986	"L2 Cache Associativity: %s\n"
6987	"L2 Cache Size: %d KB\n",
6988	(uEDX >> 0) & 0xff,
6989	(uEDX >> 8) & 0xf,
6990	getL2CacheAss((uEDX >> 12) & 0xf),
6991	(uEDX >> 16) & 0xffff);
6992	}
6993
6994	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6995	{
6996	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6997	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
6998	{
6999	if (iVerbosity < 1)
7000	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
7001	else
7002	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
7003	}
7004	}
7005
7006	pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
7007	if (pCurLeaf != NULL)
7008	{
7009	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7010	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
7011	{
7012	if (iVerbosity < 1)
7013	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
7014	else
7015	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
7016	}
7017
7018	if (iVerbosity)
7019	{
7020	uint32_t uEAX = pCurLeaf->uEax;
7021	uint32_t uECX = pCurLeaf->uEcx;
7022
7023	pHlp->pfnPrintf(pHlp,
7024	"Physical Address Width: %d bits\n"
7025	"Virtual Address Width: %d bits\n"
7026	"Guest Physical Address Width: %d bits\n",
7027	(uEAX >> 0) & 0xff,
7028	(uEAX >> 8) & 0xff,
7029	(uEAX >> 16) & 0xff);
7030	pHlp->pfnPrintf(pHlp,
7031	"Physical Core Count: %d\n",
7032	((uECX >> 0) & 0xff) + 1);
7033	}
7034	}
7035
7036	pCurLeaf = pNextLeaf;
7037	}
7038
7039
7040
7041	/*
7042	* Centaur.
7043	*/
7044	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
7045
7046	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7047	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
7048	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
7049	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
7050	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
7051	cMax = RT_MAX(cHstMax, cGstMax);
7052	if (cMax >= UINT32_C(0xc0000000))
7053	{
7054	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
7055
7056	/*
7057	* Understandable output
7058	*/
7059	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
7060	pHlp->pfnPrintf(pHlp,
7061	"Centaur Supports: 0xc0000000-%#010x\n",
7062	pCurLeaf->uEax);
7063
7064	if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
7065	{
7066	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
7067	uint32_t uEdxGst = pCurLeaf->uEdx;
7068	uint32_t uEdxHst = Host.uEdx;
7069
7070	if (iVerbosity == 1)
7071	{
7072	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
7073	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
7074	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
7075	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
7076	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
7077	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
7078	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
7079	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
7080	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
7081	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7082	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
7083	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
7084	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
7085	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
7086	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
7087	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
7088	for (unsigned iBit = 14; iBit < 32; iBit++)
7089	if (uEdxGst & RT_BIT(iBit))
7090	pHlp->pfnPrintf(pHlp, " %d", iBit);
7091	pHlp->pfnPrintf(pHlp, "\n");
7092	}
7093	else
7094	{
7095	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
7096	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
7097	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
7098	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
7099	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
7100	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
7101	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
7102	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
7103	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
7104	/* possibly indicating MM/HE and MM/HE-E on older chips... */
7105	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
7106	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
7107	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
7108	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
7109	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
7110	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
7111	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
7112	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
7113	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
7114	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
7115	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
7116	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
7117	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
7118	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
7119	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
7120	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
7121	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
7122	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
7123	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
7124	for (unsigned iBit = 27; iBit < 32; iBit++)
7125	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
7126	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
7127	pHlp->pfnPrintf(pHlp, "\n");
7128	}
7129	}
7130
7131	pCurLeaf = pNextLeaf;
7132	}
7133
7134	/*
7135	* The remainder.
7136	*/
7137	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
7138	}
7139
7140
7141
7142
7143
7144	/*
7145	*
7146	*
7147	* PATM interfaces.
7148	* PATM interfaces.
7149	* PATM interfaces.
7150	*
7151	*
7152	*/
7153
7154
7155	# if defined(VBOX_WITH_RAW_MODE) \|\| defined(DOXYGEN_RUNNING)
7156	/** @name Patchmanager CPUID legacy table APIs
7157	* @{
7158	*/
7159
7160	/**
7161	* Gets a pointer to the default CPUID leaf.
7162	*
7163	* @returns Raw-mode pointer to the default CPUID leaf (read-only).
7164	* @param pVM The cross context VM structure.
7165	* @remark Intended for PATM only.
7166	*/
7167	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmDefRCPtr(PVM pVM)
7168	{
7169	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestInfo.DefCpuId);
7170	}
7171
7172
7173	/**
7174	* Gets a number of standard CPUID leaves (PATM only).
7175	*
7176	* @returns Number of leaves.
7177	* @param pVM The cross context VM structure.
7178	* @remark Intended for PATM - legacy, don't use in new code.
7179	*/
7180	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmStdMax(PVM pVM)
7181	{
7182	RT_NOREF_PV(pVM);
7183	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd);
7184	}
7185
7186
7187	/**
7188	* Gets a number of extended CPUID leaves (PATM only).
7189	*
7190	* @returns Number of leaves.
7191	* @param pVM The cross context VM structure.
7192	* @remark Intended for PATM - legacy, don't use in new code.
7193	*/
7194	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmExtMax(PVM pVM)
7195	{
7196	RT_NOREF_PV(pVM);
7197	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt);
7198	}
7199
7200
7201	/**
7202	* Gets a number of centaur CPUID leaves.
7203	*
7204	* @returns Number of leaves.
7205	* @param pVM The cross context VM structure.
7206	* @remark Intended for PATM - legacy, don't use in new code.
7207	*/
7208	VMMR3_INT_DECL(uint32_t) CPUMR3GetGuestCpuIdPatmCentaurMax(PVM pVM)
7209	{
7210	RT_NOREF_PV(pVM);
7211	return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur);
7212	}
7213
7214
7215	/**
7216	* Gets a pointer to the array of standard CPUID leaves.
7217	*
7218	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
7219	*
7220	* @returns Raw-mode pointer to the standard CPUID leaves (read-only).
7221	* @param pVM The cross context VM structure.
7222	* @remark Intended for PATM - legacy, don't use in new code.
7223	*/
7224	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmStdRCPtr(PVM pVM)
7225	{
7226	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmStd[0]);
7227	}
7228
7229
7230	/**
7231	* Gets a pointer to the array of extended CPUID leaves.
7232	*
7233	* CPUMGetGuestCpuIdExtMax() give the size of the array.
7234	*
7235	* @returns Raw-mode pointer to the extended CPUID leaves (read-only).
7236	* @param pVM The cross context VM structure.
7237	* @remark Intended for PATM - legacy, don't use in new code.
7238	*/
7239	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmExtRCPtr(PVM pVM)
7240	{
7241	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmExt[0]);
7242	}
7243
7244
7245	/**
7246	* Gets a pointer to the array of centaur CPUID leaves.
7247	*
7248	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
7249	*
7250	* @returns Raw-mode pointer to the centaur CPUID leaves (read-only).
7251	* @param pVM The cross context VM structure.
7252	* @remark Intended for PATM - legacy, don't use in new code.
7253	*/
7254	VMMR3_INT_DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdPatmCentaurRCPtr(PVM pVM)
7255	{
7256	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0]);
7257	}
7258
7259	/** @} */
7260	# endif /* VBOX_WITH_RAW_MODE \|\| DOXYGEN_RUNNING */
7261
7262	#endif /* VBOX_IN_VMM */
7263

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 73281

Download in other formats: