VirtualBox

Changeset 73274 in vbox


Ignore:
Timestamp:
Jul 20, 2018 3:40:10 PM (7 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
123881
Message:

VMM: Nested VMX: bugref:9180 Reports bits of IA32_FEATURE_CONTROL, start implementing IA32_VMX_BASIC MSRs, cleanups.

Location:
trunk
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/cpum.h

    r73257 r73274  
    11181118
    11191119    /** @todo VMX features. */
    1120     uint32_t        auPadding[1];
     1120    /** VMX: INS/OUTS VM-exit instruction info. */
     1121    uint32_t        fVmxInsOutInfo : 1;
     1122    uint32_t        fVmxPadding0 : 31;
    11211123} CPUMFEATURES;
    11221124#ifndef VBOX_FOR_DTRACE_LIB

  • trunk/include/VBox/vmm/hm_vmx.h

    r73256 r73274  
    10911091 */
    10921092/** VMCS revision identifier used by the processor. */
    1093 #define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a)                      ((a) & 0x7FFFFFFF)
    1094 /** Size of the VMCS. */
    1095 #define MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(a)                    (((a) >> 32) & 0x1FFF)
    1096 /** Width of physical address used for the VMCS.
    1097  *  0 -> limited to the available amount of physical ram
    1098  *  1 -> within the first 4 GB
    1099  */
    1100 #define MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(a)              (((a) >> 48) & 1)
    1101 /** Whether the processor supports the dual-monitor treatment of
    1102  *  system-management interrupts and system-management code. (always 1) */
    1103 #define MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(a)                (((a) >> 49) & 1)
    1104 /** Memory type that must be used for the VMCS. */
    1105 #define MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(a)                (((a) >> 50) & 0xF)
    1106 /** Whether the processor provides additional information for exits due to
    1107  *  INS/OUTS. */
    1108 #define MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(a)                (((a) >> 54) & 1)
     1093#define MSR_IA32_VMX_BASIC_VMCS_ID(a)                      ((a) & 0x7FFFFFFF)
     1094/** Shift to get the VMCS size. */
     1095#define MSR_IA32_VMX_BASIC_VMCS_SIZE_SHIFT                 32
     1096/** VMCS size in bytes. */
     1097#define MSR_IA32_VMX_BASIC_VMCS_SIZE(a)                    (((a) >> 32) & 0x1FFF)
     1098/** Shift to get the width of physical addresses and associated memory regions. */
     1099#define MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH_SHIFT           48
     1100/** Width of physical addresses used for the VMCS and associated memory regions. */
     1101#define MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH(a)              (((a) >> 48) & 1)
     1102/** Shift to get the dual-monitor treatment of SMI and SMM. */
     1103#define MSR_IA32_VMX_BASIC_DUAL_MON_SHIFT                  49
     1104/** Dual-monitor treatment of SMI and SMM supported. */
     1105#define MSR_IA32_VMX_BASIC_DUAL_MON(a)                     (((a) >> 49) & 1)
     1106/** Shift to get the memory type that must be used for the VMCS and associated
     1107 *  memory regions. */
     1108#define MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE_SHIFT             50
     1109/** Memory type that must be used for the VMCS and associated memory regions. */
     1110#define MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE(a)                (((a) >> 50) & 0xF)
     1111/** Shift to get the additional VM-exit information for INS/OUTS. */
     1112#define MSR_IA32_VMX_BASIC_VMCS_INS_OUTS_SHIFT             54
     1113/** Additional VM-exit information for INS/OUTS. */
     1114#define MSR_IA32_VMX_BASIC_VMCS_INS_OUTS(a)                (((a) >> 54) & 1)
     1115/** Shift to get the VMCS true controls. */
     1116#define MSR_IA32_VMX_BASIC_TRUE_CONTROLS_SHIFT             55
    11091117/** Whether default 1 bits in control MSRs (pin/proc/exit/entry) may be
    11101118 *  cleared to 0 and that 'true' control MSRs are supported. */
    1111 #define MSR_IA32_VMX_BASIC_INFO_TRUE_CONTROLS(a)                (((a) >> 55) & 1)
     1119#define MSR_IA32_VMX_BASIC_TRUE_CONTROLS(a)                (((a) >> 55) & 1)
    11121120/** @} */
    11131121
    … …  
    11181126/** Relationship between the preemption timer and tsc; count down every time bit
    11191127 *  x of the tsc changes. */
    1120 #define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a)                    ((a) & 0x1f)
     1128#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a)                    ((a) & 0x1F)
    11211129/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
    11221130#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a)               (((a) >> 5) & 1)
    … …  
    15161524 * @{
    15171525 */
    1518 #define VMX_EXIT_REASON_BASIC(a)                                ((a) & 0xffff)
     1526#define VMX_EXIT_REASON_BASIC(a)                                ((a) & 0xFFFF)
    15191527/** @} */
    15201528
    … …  
    15321540 * @{
    15331541 */
    1534 #define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a)                    ((a) & 0xff)
     1542#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a)                    ((a) & 0xFF)
    15351543#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT                   8
    15361544#define VMX_EXIT_INTERRUPTION_INFO_TYPE(a)                      (((a) >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7)
    … …  
    15611569 * @{
    15621570 */
    1563 #define VMX_IDT_VECTORING_INFO_VECTOR(a)                        ((a) & 0xff)
     1571#define VMX_IDT_VECTORING_INFO_VECTOR(a)                        ((a) & 0xFF)
    15641572#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT                       8
    15651573#define VMX_IDT_VECTORING_INFO_TYPE(a)                          (((a) >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)
    … …  
    17271735 * @{
    17281736 */
    1729 #define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a)          ((a) & 0xffff)
     1737#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a)          ((a) & 0xFFFF)
    17301738#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a)              (((a) >> 30) & 0x3)
    17311739/** Task switch caused by a call instruction. */
    … …  
    17791787#define VMX_EXIT_QUAL_IO_ENCODING(a)                   (((a) >> 6) & 1)
    17801788/** 16-31: IO Port (0-0xffff). */
    1781 #define VMX_EXIT_QUAL_IO_PORT(a)                       (((a) >> 16) & 0xffff)
     1789#define VMX_EXIT_QUAL_IO_PORT(a)                       (((a) >> 16) & 0xFFFF)
    17821790/* Rest reserved. */
    17831791/** @} */
    … …  
    20032011
    20042012
     2013/** VMCS revision identifier used for emulating VMX (bit 31 MBZ). Bump this
     2014 *  arbitarily chosen identifier if incompatible changes to the layout of our VMCS
     2015 *  structure is done. */
     2016#define VMX_VMCS_REVISION_ID                                    UINT32_C(0x1d000001)
     2017AssertCompile(!(VMX_VMCS_REVISION_ID & RT_BIT(31)));
     2018/** VMCS (and related regions) memory type - Uncacheable. */
     2019#define VMX_VMCS_MEM_TYPE_UC                                    0
     2020/** VMCS (and related regions) memory type - Write back. */
     2021#define VMX_VMCS_MEM_TYPE_WB                                    6
     2022
     2023
    20052024/** @defgroup grp_hm_vmx_asm    VMX Assembly Helpers
    20062025 * @{

  • trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp

    r73257 r73274  
    2424#include <VBox/vmm/apic.h>
    2525#include <VBox/vmm/hm.h>
     26#include <VBox/vmm/hm_vmx.h>
    2627#include <VBox/vmm/tm.h>
    2728#include <VBox/vmm/gim.h>
    … …  
    12901291static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxBasic(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
    12911292{
    1292     RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
    1293     *puValue = 0;
     1293    RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
     1294    if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
     1295    {
     1296        uint64_t const fVmcsRevisionId  = VMX_VMCS_REVISION_ID;
     1297        uint64_t const f32BitAddrLimit  = 0;
     1298        uint64_t const fDualMonSmiSmm   = 0;
     1299        uint64_t const fVmcsMemType     = VMX_VMCS_MEM_TYPE_WB;
     1300        uint64_t const fVmcsInsOutsInfo = pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmxInsOutInfo;
     1301        *puValue = fVmcsRevisionId
     1302                 | (f32BitAddrLimit  << MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH_SHIFT)
     1303                 | (fDualMonSmiSmm   << MSR_IA32_VMX_BASIC_DUAL_MON_SHIFT)
     1304                 | (fVmcsMemType     << MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE_SHIFT)
     1305                 | (fVmcsInsOutsInfo << MSR_IA32_VMX_BASIC_VMCS_INS_OUTS_SHIFT);
     1306    }
     1307    else
     1308        *puValue = 0;
    12941309    return VINF_SUCCESS;
    12951310}

  • trunk/src/VBox/VMM/VMMR0/HMR0.cpp

    r73264 r73274  
    393393             * depends on bit 49 of MSR_IA32_VMX_BASIC_INFO while table 35-2 says that this MSR
    394394             * is available if either VMX or SMX is supported. */
    395             if (MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(g_HmR0.vmx.Msrs.u64BasicInfo))
     395            if (MSR_IA32_VMX_BASIC_DUAL_MON(g_HmR0.vmx.Msrs.u64BasicInfo))
    396396                g_HmR0.vmx.u64HostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
    397397            g_HmR0.vmx.Msrs.VmxPinCtls.u    = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
    … …  
    436436
    437437                /* Set revision dword at the beginning of the structure. */
    438                 *(uint32_t *)pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HmR0.vmx.Msrs.u64BasicInfo);
     438                *(uint32_t *)pvScatchPage = MSR_IA32_VMX_BASIC_VMCS_ID(g_HmR0.vmx.Msrs.u64BasicInfo);
    439439
    440440                /* Make sure we don't get rescheduled to another cpu during this probe. */

  • trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

    r73266 r73274  
    790790    {
    791791        /* Write the VMCS revision dword to the VMXON region. */
    792         *(uint32_t *)pvCpuPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo);
     792        *(uint32_t *)pvCpuPage = MSR_IA32_VMX_BASIC_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo);
    793793    }
    794794
    … …  
    968968
    969969    /* The VMCS size cannot be more than 4096 bytes. See Intel spec. Appendix A.1 "Basic VMX Information". */
    970     AssertReturnStmt(MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo) <= PAGE_SIZE,
     970    AssertReturnStmt(MSR_IA32_VMX_BASIC_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo) <= PAGE_SIZE,
    971971                     (&pVM->aCpus[0])->hm.s.u32HMError = VMX_UFC_INVALID_VMCS_SIZE,
    972972                     VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO);
    … …  
    27852785
    27862786        /* Set revision dword at the beginning of the VMCS structure. */
    2787         *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo);
     2787        *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs = MSR_IA32_VMX_BASIC_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo);
    27882788
    27892789        /* Initialize our VMCS region in memory, set the VMCS launch state to "clear". */
    … …  
    1213112131            Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
    1213212132            AssertReturn(pCtx->dx == uIOPort, VERR_VMX_IPE_2);
    12133             if (MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))
     12133            if (MSR_IA32_VMX_BASIC_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))
    1213412134            {
    1213512135                int rc2  = hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);

  • trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp

    r73235 r73274  
    17381738        pFeatures->fPcid                = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
    17391739        pFeatures->fVmx                 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
     1740        if (pFeatures->fVmx)
     1741        { /** @todo Support other VMX features */ }
    17401742
    17411743        /* Structured extended features. */

  • trunk/src/VBox/VMM/VMMR3/HM.cpp

    r73266 r73274  
    328328#undef EXIT_REASON
    329329
    330 /** @def HMVMX_REPORT_FEATURE
     330/** @def HMVMX_REPORT_FEAT
    331331 * Reports VT-x feature to the release log.
    332332 *
    … …  
    336336 * @param   featflag        Mask of the feature to report.
    337337 */
    338 #define HMVMX_REPORT_FEATURE(allowed1, disallowed0, strdesc, featflag) \
     338#define HMVMX_REPORT_FEAT(allowed1, disallowed0, strdesc, featflag) \
    339339    do { \
    340340        if ((allowed1) & (featflag)) \
    … …  
    349349    } while (0)
    350350
    351 /** @def HMVMX_REPORT_ALLOWED_FEATURE
     351/** @def HMVMX_REPORT_ALLOWED_FEAT
    352352 * Reports an allowed VT-x feature to the release log.
    353353 *
    … …  
    356356 * @param   featflag        Mask of the feature to report.
    357357 */
    358 #define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, strdesc, featflag) \
     358#define HMVMX_REPORT_ALLOWED_FEAT(allowed1, strdesc, featflag) \
    359359    do { \
    360360        if ((allowed1) & (featflag)) \
    … …  
    364364    } while (0)
    365365
    366 /** @def HMVMX_REPORT_MSR_CAPABILITY
     366/** @def HMVMX_REPORT_MSR_CAP
    367367 * Reports MSR feature capability.
    368368 *
    … …  
    371371 * @param   cap             Mask of the feature to report.
    372372 */
    373 #define HMVMX_REPORT_MSR_CAPABILITY(msrcaps, strdesc, cap) \
     373#define HMVMX_REPORT_MSR_CAP(msrcaps, strdesc, cap) \
    374374    do { \
    375375        if ((msrcaps) & (cap)) \
    … …  
    13341334
    13351335/**
     1336 * Returns the VMCS (and associated regions') memory type given the IA32_VMX_BASIC
     1337 * MSR.
     1338 *
     1339 * @returns The descriptive memory type.
     1340 * @param   uMsrVmxBasic        IA32_VMX_BASIC MSR value.
     1341 */
     1342static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
     1343{
     1344    uint8_t const uMemType = MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE(uMsrVmxBasic);
     1345    switch (uMemType)
     1346    {
     1347        case VMX_VMCS_MEM_TYPE_WB: return "Write Back (WB)";
     1348        case VMX_VMCS_MEM_TYPE_UC: return "Uncacheable (UC)";
     1349    }
     1350    return "Unknown";
     1351}
     1352
     1353
     1354/**
    13361355 * Finish VT-x initialization (after ring-0 init).
    13371356 *
    … …  
    13531372    LogRel(("HM: Host EFER                       = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
    13541373    LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL        = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
    1355     LogRel(("HM: MSR_IA32_FEATURE_CONTROL        = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
     1374
     1375    val = pVM->hm.s.vmx.Msrs.u64FeatureCtrl;
     1376    LogRel(("HM: MSR_IA32_FEATURE_CONTROL        = %#RX64\n", val));
     1377    HMVMX_REPORT_MSR_CAP(val, "LOCK",             MSR_IA32_FEATURE_CONTROL_LOCK);
     1378    HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON",        MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
     1379    HMVMX_REPORT_MSR_CAP(val, "VMXON",            MSR_IA32_FEATURE_CONTROL_VMXON);
     1380    HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
     1381    HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
     1382    HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
     1383    HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
     1384    HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
     1385    HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
     1386    HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
     1387    HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
     1388    HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN",    MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
     1389    HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN",    MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
     1390    HMVMX_REPORT_MSR_CAP(val, "LMCE",             MSR_IA32_FEATURE_CONTROL_LMCE);
    13561391    if (!(pVM->hm.s.vmx.Msrs.u64FeatureCtrl & MSR_IA32_FEATURE_CONTROL_LOCK))
    1357         LogRel(("HM:   IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
    1358     LogRel(("HM: MSR_IA32_VMX_BASIC_INFO         = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
    1359     LogRel(("HM:   VMCS id                         = %#x\n",      MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
    1360     LogRel(("HM:   VMCS size                       = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
    1361     LogRel(("HM:   VMCS physical address limit     = %s\n",       MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
    1362     LogRel(("HM:   VMCS memory type                = %#x\n",      MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
    1363     LogRel(("HM:   Dual-monitor treatment support  = %RTbool\n",  MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
    1364     LogRel(("HM:   OUTS & INS instruction-info     = %RTbool\n",  MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
    1365     LogRel(("HM:   Supports true capability MSRs   = %RTbool\n",  MSR_IA32_VMX_BASIC_INFO_TRUE_CONTROLS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
     1392        LogRel(("HM:   MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
     1393
     1394    LogRel(("HM: MSR_IA32_VMX_BASIC              = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
     1395    LogRel(("HM:   VMCS id                         = %#x\n",      MSR_IA32_VMX_BASIC_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
     1396    LogRel(("HM:   VMCS size                       = %u bytes\n", MSR_IA32_VMX_BASIC_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
     1397    LogRel(("HM:   VMCS physical address limit     = %s\n",       MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
     1398    LogRel(("HM:   VMCS memory type                = %s\n",       hmR3VmxGetMemTypeDesc(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
     1399    LogRel(("HM:   Dual-monitor treatment support  = %RTbool\n",  MSR_IA32_VMX_BASIC_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
     1400    LogRel(("HM:   OUTS & INS instruction-info     = %RTbool\n",  MSR_IA32_VMX_BASIC_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
     1401    LogRel(("HM:   Supports true capability MSRs   = %RTbool\n",  MSR_IA32_VMX_BASIC_TRUE_CONTROLS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
    13661402    LogRel(("HM: Max resume loops                = %u\n", pVM->hm.s.cMaxResumeLoops));
    13671403
    … …  
    13691405    val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
    13701406    zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
    1371     HMVMX_REPORT_FEATURE(val, zap, "EXT_INT_EXIT",  VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
    1372     HMVMX_REPORT_FEATURE(val, zap, "NMI_EXIT",      VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
    1373     HMVMX_REPORT_FEATURE(val, zap, "VIRTUAL_NMI",   VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
    1374     HMVMX_REPORT_FEATURE(val, zap, "PREEMPT_TIMER", VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
    1375     HMVMX_REPORT_FEATURE(val, zap, "POSTED_INTR",   VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
     1407    HMVMX_REPORT_FEAT(val, zap, "EXT_INT_EXIT",  VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
     1408    HMVMX_REPORT_FEAT(val, zap, "NMI_EXIT",      VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
     1409    HMVMX_REPORT_FEAT(val, zap, "VIRTUAL_NMI",   VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
     1410    HMVMX_REPORT_FEAT(val, zap, "PREEMPT_TIMER", VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
     1411    HMVMX_REPORT_FEAT(val, zap, "POSTED_INTR",   VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
    13761412
    13771413    LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS     = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
    13781414    val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
    13791415    zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
    1380     HMVMX_REPORT_FEATURE(val, zap, "INT_WINDOW_EXIT",         VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
    1381     HMVMX_REPORT_FEATURE(val, zap, "USE_TSC_OFFSETTING",      VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
    1382     HMVMX_REPORT_FEATURE(val, zap, "HLT_EXIT",                VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
    1383     HMVMX_REPORT_FEATURE(val, zap, "INVLPG_EXIT",             VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
    1384     HMVMX_REPORT_FEATURE(val, zap, "MWAIT_EXIT",              VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
    1385     HMVMX_REPORT_FEATURE(val, zap, "RDPMC_EXIT",              VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
    1386     HMVMX_REPORT_FEATURE(val, zap, "RDTSC_EXIT",              VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
    1387     HMVMX_REPORT_FEATURE(val, zap, "CR3_LOAD_EXIT",           VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
    1388     HMVMX_REPORT_FEATURE(val, zap, "CR3_STORE_EXIT",          VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
    1389     HMVMX_REPORT_FEATURE(val, zap, "CR8_LOAD_EXIT",           VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
    1390     HMVMX_REPORT_FEATURE(val, zap, "CR8_STORE_EXIT",          VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
    1391     HMVMX_REPORT_FEATURE(val, zap, "USE_TPR_SHADOW",          VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
    1392     HMVMX_REPORT_FEATURE(val, zap, "NMI_WINDOW_EXIT",         VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
    1393     HMVMX_REPORT_FEATURE(val, zap, "MOV_DR_EXIT",             VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
    1394     HMVMX_REPORT_FEATURE(val, zap, "UNCOND_IO_EXIT",          VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
    1395     HMVMX_REPORT_FEATURE(val, zap, "USE_IO_BITMAPS",          VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
    1396     HMVMX_REPORT_FEATURE(val, zap, "MONITOR_TRAP_FLAG",       VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
    1397     HMVMX_REPORT_FEATURE(val, zap, "USE_MSR_BITMAPS",         VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
    1398     HMVMX_REPORT_FEATURE(val, zap, "MONITOR_EXIT",            VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
    1399     HMVMX_REPORT_FEATURE(val, zap, "PAUSE_EXIT",              VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
    1400     HMVMX_REPORT_FEATURE(val, zap, "USE_SECONDARY_EXEC_CTRL", VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
     1416    HMVMX_REPORT_FEAT(val, zap, "INT_WINDOW_EXIT",         VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
     1417    HMVMX_REPORT_FEAT(val, zap, "USE_TSC_OFFSETTING",      VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
     1418    HMVMX_REPORT_FEAT(val, zap, "HLT_EXIT",                VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
     1419    HMVMX_REPORT_FEAT(val, zap, "INVLPG_EXIT",             VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
     1420    HMVMX_REPORT_FEAT(val, zap, "MWAIT_EXIT",              VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
     1421    HMVMX_REPORT_FEAT(val, zap, "RDPMC_EXIT",              VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
     1422    HMVMX_REPORT_FEAT(val, zap, "RDTSC_EXIT",              VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
     1423    HMVMX_REPORT_FEAT(val, zap, "CR3_LOAD_EXIT",           VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
     1424    HMVMX_REPORT_FEAT(val, zap, "CR3_STORE_EXIT",          VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
     1425    HMVMX_REPORT_FEAT(val, zap, "CR8_LOAD_EXIT",           VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
     1426    HMVMX_REPORT_FEAT(val, zap, "CR8_STORE_EXIT",          VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
     1427    HMVMX_REPORT_FEAT(val, zap, "USE_TPR_SHADOW",          VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
     1428    HMVMX_REPORT_FEAT(val, zap, "NMI_WINDOW_EXIT",         VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
     1429    HMVMX_REPORT_FEAT(val, zap, "MOV_DR_EXIT",             VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
     1430    HMVMX_REPORT_FEAT(val, zap, "UNCOND_IO_EXIT",          VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
     1431    HMVMX_REPORT_FEAT(val, zap, "USE_IO_BITMAPS",          VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
     1432    HMVMX_REPORT_FEAT(val, zap, "MONITOR_TRAP_FLAG",       VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
     1433    HMVMX_REPORT_FEAT(val, zap, "USE_MSR_BITMAPS",         VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
     1434    HMVMX_REPORT_FEAT(val, zap, "MONITOR_EXIT",            VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
     1435    HMVMX_REPORT_FEAT(val, zap, "PAUSE_EXIT",              VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
     1436    HMVMX_REPORT_FEAT(val, zap, "USE_SECONDARY_EXEC_CTRL", VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
    14011437    if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
    14021438    {
    … …  
    14041440        val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
    14051441        zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
    1406         HMVMX_REPORT_FEATURE(val, zap, "VIRT_APIC",             VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
    1407         HMVMX_REPORT_FEATURE(val, zap, "EPT",                   VMX_VMCS_CTRL_PROC_EXEC2_EPT);
    1408         HMVMX_REPORT_FEATURE(val, zap, "DESCRIPTOR_TABLE_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
    1409         HMVMX_REPORT_FEATURE(val, zap, "RDTSCP",                VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
    1410         HMVMX_REPORT_FEATURE(val, zap, "VIRT_X2APIC",           VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
    1411         HMVMX_REPORT_FEATURE(val, zap, "VPID",                  VMX_VMCS_CTRL_PROC_EXEC2_VPID);
    1412         HMVMX_REPORT_FEATURE(val, zap, "WBINVD_EXIT",           VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
    1413         HMVMX_REPORT_FEATURE(val, zap, "UNRESTRICTED_GUEST",    VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
    1414         HMVMX_REPORT_FEATURE(val, zap, "APIC_REG_VIRT",         VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
    1415         HMVMX_REPORT_FEATURE(val, zap, "VIRT_INTR_DELIVERY",    VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
    1416         HMVMX_REPORT_FEATURE(val, zap, "PAUSE_LOOP_EXIT",       VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
    1417         HMVMX_REPORT_FEATURE(val, zap, "RDRAND_EXIT",           VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
    1418         HMVMX_REPORT_FEATURE(val, zap, "INVPCID",               VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
    1419         HMVMX_REPORT_FEATURE(val, zap, "VMFUNC",                VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
    1420         HMVMX_REPORT_FEATURE(val, zap, "VMCS_SHADOWING",        VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
    1421         HMVMX_REPORT_FEATURE(val, zap, "ENCLS_EXIT",            VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT);
    1422         HMVMX_REPORT_FEATURE(val, zap, "RDSEED_EXIT",           VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
    1423         HMVMX_REPORT_FEATURE(val, zap, "PML",                   VMX_VMCS_CTRL_PROC_EXEC2_PML);
    1424         HMVMX_REPORT_FEATURE(val, zap, "EPT_VE",                VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
    1425         HMVMX_REPORT_FEATURE(val, zap, "CONCEAL_FROM_PT",       VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT);
    1426         HMVMX_REPORT_FEATURE(val, zap, "XSAVES_XRSTORS",        VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS);
    1427         HMVMX_REPORT_FEATURE(val, zap, "TSC_SCALING",           VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING);
     1442        HMVMX_REPORT_FEAT(val, zap, "VIRT_APIC",             VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
     1443        HMVMX_REPORT_FEAT(val, zap, "EPT",                   VMX_VMCS_CTRL_PROC_EXEC2_EPT);
     1444        HMVMX_REPORT_FEAT(val, zap, "DESCRIPTOR_TABLE_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
     1445        HMVMX_REPORT_FEAT(val, zap, "RDTSCP",                VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
     1446        HMVMX_REPORT_FEAT(val, zap, "VIRT_X2APIC",           VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
     1447        HMVMX_REPORT_FEAT(val, zap, "VPID",                  VMX_VMCS_CTRL_PROC_EXEC2_VPID);
     1448        HMVMX_REPORT_FEAT(val, zap, "WBINVD_EXIT",           VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
     1449        HMVMX_REPORT_FEAT(val, zap, "UNRESTRICTED_GUEST",    VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
     1450        HMVMX_REPORT_FEAT(val, zap, "APIC_REG_VIRT",         VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
     1451        HMVMX_REPORT_FEAT(val, zap, "VIRT_INTR_DELIVERY",    VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
     1452        HMVMX_REPORT_FEAT(val, zap, "PAUSE_LOOP_EXIT",       VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
     1453        HMVMX_REPORT_FEAT(val, zap, "RDRAND_EXIT",           VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
     1454        HMVMX_REPORT_FEAT(val, zap, "INVPCID",               VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
     1455        HMVMX_REPORT_FEAT(val, zap, "VMFUNC",                VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
     1456        HMVMX_REPORT_FEAT(val, zap, "VMCS_SHADOWING",        VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
     1457        HMVMX_REPORT_FEAT(val, zap, "ENCLS_EXIT",            VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT);
     1458        HMVMX_REPORT_FEAT(val, zap, "RDSEED_EXIT",           VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
     1459        HMVMX_REPORT_FEAT(val, zap, "PML",                   VMX_VMCS_CTRL_PROC_EXEC2_PML);
     1460        HMVMX_REPORT_FEAT(val, zap, "EPT_VE",                VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
     1461        HMVMX_REPORT_FEAT(val, zap, "CONCEAL_FROM_PT",       VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT);
     1462        HMVMX_REPORT_FEAT(val, zap, "XSAVES_XRSTORS",        VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS);
     1463        HMVMX_REPORT_FEAT(val, zap, "TSC_SCALING",           VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING);
    14281464    }
    14291465
    … …  
    14311467    val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
    14321468    zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
    1433     HMVMX_REPORT_FEATURE(val, zap, "LOAD_DEBUG",          VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
    1434     HMVMX_REPORT_FEATURE(val, zap, "IA32E_MODE_GUEST",    VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
    1435     HMVMX_REPORT_FEATURE(val, zap, "ENTRY_SMM",           VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
    1436     HMVMX_REPORT_FEATURE(val, zap, "DEACTIVATE_DUALMON",  VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
    1437     HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PERF_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
    1438     HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PAT_MSR",  VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
    1439     HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_EFER_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
     1469    HMVMX_REPORT_FEAT(val, zap, "LOAD_DEBUG",          VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
     1470    HMVMX_REPORT_FEAT(val, zap, "IA32E_MODE_GUEST",    VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
     1471    HMVMX_REPORT_FEAT(val, zap, "ENTRY_SMM",           VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
     1472    HMVMX_REPORT_FEAT(val, zap, "DEACTIVATE_DUALMON",  VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
     1473    HMVMX_REPORT_FEAT(val, zap, "LOAD_GUEST_PERF_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
     1474    HMVMX_REPORT_FEAT(val, zap, "LOAD_GUEST_PAT_MSR",  VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
     1475    HMVMX_REPORT_FEAT(val, zap, "LOAD_GUEST_EFER_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
    14401476
    14411477    LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS          = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
    14421478    val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
    14431479    zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
    1444     HMVMX_REPORT_FEATURE(val, zap, "SAVE_DEBUG",             VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
    1445     HMVMX_REPORT_FEATURE(val, zap, "HOST_ADDR_SPACE_SIZE",   VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
    1446     HMVMX_REPORT_FEATURE(val, zap, "LOAD_PERF_MSR",          VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
    1447     HMVMX_REPORT_FEATURE(val, zap, "ACK_EXT_INT",            VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
    1448     HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_PAT_MSR",     VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
    1449     HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_PAT_MSR",      VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
    1450     HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_EFER_MSR",    VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
    1451     HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_EFER_MSR",     VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
    1452     HMVMX_REPORT_FEATURE(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
     1480    HMVMX_REPORT_FEAT(val, zap, "SAVE_DEBUG",             VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
     1481    HMVMX_REPORT_FEAT(val, zap, "HOST_ADDR_SPACE_SIZE",   VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
     1482    HMVMX_REPORT_FEAT(val, zap, "LOAD_PERF_MSR",          VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
     1483    HMVMX_REPORT_FEAT(val, zap, "ACK_EXT_INT",            VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
     1484    HMVMX_REPORT_FEAT(val, zap, "SAVE_GUEST_PAT_MSR",     VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
     1485    HMVMX_REPORT_FEAT(val, zap, "LOAD_HOST_PAT_MSR",      VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
     1486    HMVMX_REPORT_FEAT(val, zap, "SAVE_GUEST_EFER_MSR",    VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
     1487    HMVMX_REPORT_FEAT(val, zap, "LOAD_HOST_EFER_MSR",     VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
     1488    HMVMX_REPORT_FEAT(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
    14531489
    14541490    if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
    … …  
    14561492        val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
    14571493        LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP       = %#RX64\n", val));
    1458         HMVMX_REPORT_MSR_CAPABILITY(val, "RWX_X_ONLY",                            MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
    1459         HMVMX_REPORT_MSR_CAPABILITY(val, "PAGE_WALK_LENGTH_4",                    MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
    1460         HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_UC",                                MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
    1461         HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_WB",                                MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
    1462         HMVMX_REPORT_MSR_CAPABILITY(val, "PDE_2M",                                MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
    1463         HMVMX_REPORT_MSR_CAPABILITY(val, "PDPTE_1G",                              MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
    1464         HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT",                                MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
    1465         HMVMX_REPORT_MSR_CAPABILITY(val, "EPT_ACCESS_DIRTY",                      MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
    1466         HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_SINGLE_CONTEXT",                 MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
    1467         HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_ALL_CONTEXTS",                   MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
    1468         HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID",                               MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
    1469         HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_INDIV_ADDR",                    MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
    1470         HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT",                MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
    1471         HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_ALL_CONTEXTS",                  MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
    1472         HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
     1494        HMVMX_REPORT_MSR_CAP(val, "RWX_X_ONLY",                            MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
     1495        HMVMX_REPORT_MSR_CAP(val, "PAGE_WALK_LENGTH_4",                    MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
     1496        HMVMX_REPORT_MSR_CAP(val, "EMT_UC",                                MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
     1497        HMVMX_REPORT_MSR_CAP(val, "EMT_WB",                                MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
     1498        HMVMX_REPORT_MSR_CAP(val, "PDE_2M",                                MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
     1499        HMVMX_REPORT_MSR_CAP(val, "PDPTE_1G",                              MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
     1500        HMVMX_REPORT_MSR_CAP(val, "INVEPT",                                MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
     1501        HMVMX_REPORT_MSR_CAP(val, "EPT_ACCESS_DIRTY",                      MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
     1502        HMVMX_REPORT_MSR_CAP(val, "INVEPT_SINGLE_CONTEXT",                 MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
     1503        HMVMX_REPORT_MSR_CAP(val, "INVEPT_ALL_CONTEXTS",                   MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
     1504        HMVMX_REPORT_MSR_CAP(val, "INVVPID",                               MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
     1505        HMVMX_REPORT_MSR_CAP(val, "INVVPID_INDIV_ADDR",                    MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
     1506        HMVMX_REPORT_MSR_CAP(val, "INVVPID_SINGLE_CONTEXT",                MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
     1507        HMVMX_REPORT_MSR_CAP(val, "INVVPID_ALL_CONTEXTS",                  MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
     1508        HMVMX_REPORT_MSR_CAP(val, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
    14731509    }
    14741510
    … …  
    15081544    {
    15091545        LogRel(("HM: MSR_IA32_VMX_VMFUNC             = %#RX64\n", val));
    1510         HMVMX_REPORT_ALLOWED_FEATURE(val, "EPTP_SWITCHING", VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
     1546        HMVMX_REPORT_ALLOWED_FEAT(val, "EPTP_SWITCHING", VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
    15111547    }
    15121548
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