CPUMR3Db.cpp@ 49966

Last change on this file since 49966 was 49966, checked in by vboxsync, 11 years ago
CPUM: Added AMD Athlon64 3200+ (130nm) and Pentium4 (mod 4, w/ 64-bit).
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1	/* $Id: CPUMR3Db.cpp 49966 2013-12-17 20:43:23Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_CPUM
22	#include <VBox/vmm/cpum.h>
23	#include "CPUMInternal.h"
24	#include <VBox/vmm/vm.h>
25
26	#include <VBox/err.h>
27	#include <iprt/asm-amd64-x86.h>
28	#include <iprt/mem.h>
29	#include <iprt/string.h>
30
31
32	/*******************************************************************************
33	* Structures and Typedefs *
34	*******************************************************************************/
35	typedef struct CPUMDBENTRY
36	{
37	/** The CPU name. */
38	const char *pszName;
39	/** The full CPU name. */
40	const char *pszFullName;
41	/** The CPU vendor (CPUMCPUVENDOR). */
42	uint8_t enmVendor;
43	/** The CPU family. */
44	uint8_t uFamily;
45	/** The CPU model. */
46	uint8_t uModel;
47	/** The CPU stepping. */
48	uint8_t uStepping;
49	/** The microarchitecture. */
50	CPUMMICROARCH enmMicroarch;
51	/** Flags (TBD). */
52	uint32_t fFlags;
53	/** The maximum physical address with of the CPU. This should correspond to
54	* the value in CPUID leaf 0x80000008 when present. */
55	uint8_t cMaxPhysAddrWidth;
56	/** Pointer to an array of CPUID leaves. */
57	PCCPUMCPUIDLEAF paCpuIdLeaves;
58	/** The number of CPUID leaves in the array paCpuIdLeaves points to. */
59	uint32_t cCpuIdLeaves;
60	/** The method used to deal with unknown CPUID leaves. */
61	CPUMUKNOWNCPUID enmUnknownCpuId;
62	/** The default unknown CPUID value. */
63	CPUMCPUID DefUnknownCpuId;
64
65	/** MSR mask. Several microarchitectures ignore higher bits of the */
66	uint32_t fMsrMask;
67
68	/** The number of ranges in the table pointed to b paMsrRanges. */
69	uint32_t cMsrRanges;
70	/** MSR ranges for this CPU. */
71	PCCPUMMSRRANGE paMsrRanges;
72	} CPUMDBENTRY;
73
74
75	/*******************************************************************************
76	* Defined Constants And Macros *
77	*******************************************************************************/
78
79	/** @def NULL_ALONE
80	* For eliminating an unnecessary data dependency in standalone builds (for
81	* VBoxSVC). */
82	/** @def ZERO_ALONE
83	* For eliminating an unnecessary data size dependency in standalone builds (for
84	* VBoxSVC). */
85	#ifndef CPUM_DB_STANDALONE
86	# define NULL_ALONE(a_aTable) a_aTable
87	# define ZERO_ALONE(a_cTable) a_cTable
88	#else
89	# define NULL_ALONE(a_aTable) NULL
90	# define ZERO_ALONE(a_cTable) 0
91	#endif
92
93
94	/** @name Short macros for the MSR range entries.
95	*
96	* These are rather cryptic, but this is to reduce the attack on the right
97	* margin.
98	*
99	* @{ */
100	/** Alias one MSR onto another (a_uTarget). */
101	#define MAL(a_uMsr, a_szName, a_uTarget) \
102	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
103	/** Functions handles everything. */
104	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
105	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
106	/** Functions handles everything, with GP mask. */
107	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
108	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
109	/** Function handlers, read-only. */
110	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
111	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
112	/** Function handlers, ignore all writes. */
113	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
114	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
115	/** Function handlers, with value. */
116	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
117	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
118	/** Function handlers, with write ignore mask. */
119	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
120	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
121	/** Function handlers, extended version. */
122	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
123	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
124	/** Function handlers, with CPUMCPU storage variable. */
125	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
126	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
127	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
128	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
129	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
130	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
131	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
132	/** Read-only fixed value. */
133	#define MVO(a_uMsr, a_szName, a_uValue) \
134	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
135	/** Read-only fixed value, ignores all writes. */
136	#define MVI(a_uMsr, a_szName, a_uValue) \
137	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
138	/** Read fixed value, ignore writes outside GP mask. */
139	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
140	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
141	/** Read fixed value, extended version with both GP and ignore masks. */
142	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
143	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
144	/** The short form, no CPUM backing. */
145	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
146	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
147	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
148
149	/** Range: Functions handles everything. */
150	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
151	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
152	/** Range: Read fixed value, read-only. */
153	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
154	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
155	/** Range: Read fixed value, ignore writes. */
156	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
157	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
158	/** Range: The short form, no CPUM backing. */
159	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
160	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
161	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
162
163	/** Internal form used by the macros. */
164	#ifdef VBOX_WITH_STATISTICS
165	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
166	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
167	{ 0 }, { 0 }, { 0 }, { 0 } }
168	#else
169	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
170	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
171	#endif
172	/** @} */
173
174
175	#include "cpus/Intel_Core_i7_3960X.h"
176	#include "cpus/Intel_Core_i5_3570.h"
177	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
178	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
179	#include "cpus/Intel_Pentium_4_3_00GHz.h"
180
181	#include "cpus/AMD_FX_8150_Eight_Core.h"
182	#include "cpus/AMD_Phenom_II_X6_1100T.h"
183	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
184	#include "cpus/AMD_Athlon_64_3200.h"
185
186
187
188	/**
189	* The database entries.
190	*
191	* Warning! The first entry is special. It is the fallback for unknown
192	* processors. Thus, it better be pretty representative.
193	*/
194	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
195	{
196	#ifdef VBOX_CPUDB_Intel_Core_i5_3570
197	&g_Entry_Intel_Core_i5_3570,
198	#endif
199	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
200	&g_Entry_Intel_Core_i7_3960X,
201	#endif
202	#ifdef Intel_Pentium_M_processor_2_00GHz
203	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
204	#endif
205	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
206	&g_Entry_Intel_Xeon_X5482_3_20GHz,
207	#endif
208	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
209	&g_Entry_Intel_Pentium_4_3_00GHz,
210	#endif
211
212	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
213	&g_Entry_AMD_FX_8150_Eight_Core,
214	#endif
215	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
216	&g_Entry_AMD_Phenom_II_X6_1100T,
217	#endif
218	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
219	&g_Entry_Quad_Core_AMD_Opteron_2384,
220	#endif
221	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
222	&g_Entry_AMD_Athlon_64_3200,
223	#endif
224	};
225
226
227	#ifndef CPUM_DB_STANDALONE
228
229	/**
230	* Binary search used by cpumR3MsrRangesInsert and has some special properties
231	* wrt to mismatches.
232	*
233	* @returns Insert location.
234	* @param paMsrRanges The MSR ranges to search.
235	* @param cMsrRanges The number of MSR ranges.
236	* @param uMsr What to search for.
237	*/
238	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
239	{
240	if (!cMsrRanges)
241	return 0;
242
243	uint32_t iStart = 0;
244	uint32_t iLast = cMsrRanges - 1;
245	for (;;)
246	{
247	uint32_t i = iStart + (iLast - iStart + 1) / 2;
248	if ( uMsr >= paMsrRanges[i].uFirst
249	&& uMsr <= paMsrRanges[i].uLast)
250	return i;
251	if (uMsr < paMsrRanges[i].uFirst)
252	{
253	if (i <= iStart)
254	return i;
255	iLast = i - 1;
256	}
257	else
258	{
259	if (i >= iLast)
260	{
261	if (i < cMsrRanges)
262	i++;
263	return i;
264	}
265	iStart = i + 1;
266	}
267	}
268	}
269
270
271	/**
272	* Ensures that there is space for at least @a cNewRanges in the table,
273	* reallocating the table if necessary.
274	*
275	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
276	* @a *ppaMsrRanges is freed and set to NULL.
277	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
278	* @param cMsrRanges The current number of ranges.
279	* @param cNewRanges The number of ranges to be added.
280	*/
281	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
282	{
283	uint32_t cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
284	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
285	{
286	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
287	void pvNew = RTMemRealloc(ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
288	if (!pvNew)
289	{
290	RTMemFree(*ppaMsrRanges);
291	*ppaMsrRanges = NULL;
292	return NULL;
293	}
294	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
295	}
296	return *ppaMsrRanges;
297	}
298
299
300	/**
301	* Inserts a new MSR range in into an sorted MSR range array.
302	*
303	* If the new MSR range overlaps existing ranges, the existing ones will be
304	* adjusted/removed to fit in the new one.
305	*
306	* @returns VBox status code.
307	* @retval VINF_SUCCESS
308	* @retval VERR_NO_MEMORY
309	*
310	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
311	* @param pcMsrRanges The variable holding number of ranges.
312	* @param pNewRange The new range.
313	*/
314	int cpumR3MsrRangesInsert(PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
315	{
316	uint32_t cMsrRanges = *pcMsrRanges;
317	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
318
319	Assert(pNewRange->uLast >= pNewRange->uFirst);
320	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
321	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
322
323	/*
324	* Optimize the linear insertion case where we add new entries at the end.
325	*/
326	if ( cMsrRanges > 0
327	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
328	{
329	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
330	if (!paMsrRanges)
331	return VERR_NO_MEMORY;
332	paMsrRanges[cMsrRanges] = *pNewRange;
333	*pcMsrRanges += 1;
334	}
335	else
336	{
337	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
338	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
339	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
340
341	/*
342	* Adding an entirely new entry?
343	*/
344	if ( i >= cMsrRanges
345	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
346	{
347	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
348	if (!paMsrRanges)
349	return VERR_NO_MEMORY;
350	if (i < cMsrRanges)
351	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
352	paMsrRanges[i] = *pNewRange;
353	*pcMsrRanges += 1;
354	}
355	/*
356	* Replace existing entry?
357	*/
358	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
359	&& pNewRange->uLast == paMsrRanges[i].uLast)
360	paMsrRanges[i] = *pNewRange;
361	/*
362	* Splitting an existing entry?
363	*/
364	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
365	&& pNewRange->uLast < paMsrRanges[i].uLast)
366	{
367	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 2);
368	if (!paMsrRanges)
369	return VERR_NO_MEMORY;
370	if (i < cMsrRanges)
371	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
372	paMsrRanges[i + 1] = *pNewRange;
373	paMsrRanges[i + 2] = paMsrRanges[i];
374	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
375	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
376	*pcMsrRanges += 2;
377	}
378	/*
379	* Complicated scenarios that can affect more than one range.
380	*
381	* The current code does not optimize memmove calls when replacing
382	* one or more existing ranges, because it's tedious to deal with and
383	* not expected to be a frequent usage scenario.
384	*/
385	else
386	{
387	/* Adjust start of first match? */
388	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
389	&& pNewRange->uLast < paMsrRanges[i].uLast)
390	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
391	else
392	{
393	/* Adjust end of first match? */
394	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
395	{
396	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
397	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
398	i++;
399	}
400	/* Replace the whole first match (lazy bird). */
401	else
402	{
403	if (i + 1 < cMsrRanges)
404	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
405	cMsrRanges = *pcMsrRanges -= 1;
406	}
407
408	/* Do the new range affect more ranges? */
409	while ( i < cMsrRanges
410	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
411	{
412	if (pNewRange->uLast < paMsrRanges[i].uLast)
413	{
414	/* Adjust the start of it, then we're done. */
415	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
416	break;
417	}
418
419	/* Remove it entirely. */
420	if (i + 1 < cMsrRanges)
421	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
422	cMsrRanges = *pcMsrRanges -= 1;
423	}
424	}
425
426	/* Now, perform a normal insertion. */
427	paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
428	if (!paMsrRanges)
429	return VERR_NO_MEMORY;
430	if (i < cMsrRanges)
431	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
432	paMsrRanges[i] = *pNewRange;
433	*pcMsrRanges += 1;
434	}
435	}
436
437	return VINF_SUCCESS;
438	}
439
440
441	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
442	{
443	CPUMDBENTRY const *pEntry = NULL;
444	int rc;
445
446	if (!strcmp(pszName, "host"))
447	{
448	/*
449	* Create a CPU database entry for the host CPU. This means getting
450	* the CPUID bits from the real CPU and grabbing the closest matching
451	* database entry for MSRs.
452	*/
453	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
454	if (RT_FAILURE(rc))
455	return rc;
456	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
457	if (RT_FAILURE(rc))
458	return rc;
459
460	/* Lookup database entry for MSRs. */
461	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
462	pInfo->paCpuIdLeavesR3[0].uEbx,
463	pInfo->paCpuIdLeavesR3[0].uEcx,
464	pInfo->paCpuIdLeavesR3[0].uEdx);
465	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
466	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
467	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
468	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
469	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
470
471	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
472	{
473	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
474	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
475	{
476	/* Anything from the same vendor is better than nothing: */
477	if (!pEntry)
478	pEntry = pCur;
479	/* Newer micro arch is better than an older one: */
480	else if ( pEntry->enmMicroarch < enmMicroarch
481	&& pCur->enmMicroarch >= enmMicroarch)
482	pEntry = pCur;
483	/* Prefer a micro arch match: */
484	else if ( pEntry->enmMicroarch != enmMicroarch
485	&& pCur->enmMicroarch == enmMicroarch)
486	pEntry = pCur;
487	/* If the micro arch matches, check model and stepping. Stop
488	looping if we get an exact match. */
489	else if ( pEntry->enmMicroarch == enmMicroarch
490	&& pCur->enmMicroarch == enmMicroarch)
491	{
492	if (pCur->uModel == uModel)
493	{
494	/* Perfect match? */
495	if (pCur->uStepping == uStepping)
496	{
497	pEntry = pCur;
498	break;
499	}
500
501	/* Better model match? */
502	if (pEntry->uModel != uModel)
503	pEntry = pCur;
504	/* The one with the closest stepping, prefering ones over earlier ones. */
505	else if ( pCur->uStepping > uStepping
506	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
507	: pCur->uStepping > pEntry->uStepping)
508	pEntry = pCur;
509	}
510	/* The one with the closest model, prefering later ones over earlier ones. */
511	else if ( pCur->uModel > uModel
512	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
513	: pCur->uModel > pEntry->uModel)
514	pEntry = pCur;
515	}
516	}
517	}
518
519	if (pEntry)
520	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
521	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
522	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
523	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
524	else
525	{
526	pEntry = g_apCpumDbEntries[0];
527	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'.\n",
528	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
529	pEntry->pszName));
530	}
531	}
532	else
533	{
534	/*
535	* We're supposed to be emulating a specific CPU that is included in
536	* our CPU database. The CPUID tables needs to be copied onto the
537	* heap so the caller can modify them and so they can be freed like
538	* in the host case above.
539	*/
540	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
541	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
542	{
543	pEntry = g_apCpumDbEntries[i];
544	break;
545	}
546	if (!pEntry)
547	{
548	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
549	return VERR_CPUM_DB_CPU_NOT_FOUND;
550	}
551
552	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
553	if (pEntry->cCpuIdLeaves)
554	{
555	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDup(pEntry->paCpuIdLeaves,
556	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves);
557	if (!pInfo->paCpuIdLeavesR3)
558	return VERR_NO_MEMORY;
559	}
560	else
561	pInfo->paCpuIdLeavesR3 = NULL;
562
563	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
564	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
565
566	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
567	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
568	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
569	}
570
571	pInfo->fMsrMask = pEntry->fMsrMask;
572	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
573	pInfo->uPadding = 0;
574	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
575	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
576	pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
577	pInfo->paMsrRangesRC = NIL_RTRCPTR;
578
579	/*
580	* Copy the MSR range.
581	*/
582	uint32_t cMsrs = 0;
583	PCPUMMSRRANGE paMsrs = NULL;
584
585	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
586	uint32_t cLeft = pEntry->cMsrRanges;
587	while (cLeft-- > 0)
588	{
589	rc = cpumR3MsrRangesInsert(&paMsrs, &cMsrs, pCurMsr);
590	if (RT_FAILURE(rc))
591	{
592	Assert(!paMsrs); /* The above function frees this. */
593	RTMemFree(pInfo->paCpuIdLeavesR3);
594	pInfo->paCpuIdLeavesR3 = NULL;
595	return rc;
596	}
597	pCurMsr++;
598	}
599
600	pInfo->paMsrRangesR3 = paMsrs;
601	pInfo->cMsrRanges = cMsrs;
602	return VINF_SUCCESS;
603	}
604
605
606	/**
607	* Register statistics for the MSRs.
608	*
609	* This must not be called before the MSRs have been finalized and moved to the
610	* hyper heap.
611	*
612	* @returns VBox status code.
613	* @param pVM Pointer to the cross context VM structure.
614	*/
615	int cpumR3MsrRegStats(PVM pVM)
616	{
617	/*
618	* Global statistics.
619	*/
620	PCPUM pCpum = &pVM->cpum.s;
621	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
622	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
623	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
624	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
625	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
626	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
627	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
628	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
629	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
630	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
631	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
632	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
633	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
634	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
635
636
637	# ifdef VBOX_WITH_STATISTICS
638	/*
639	* Per range.
640	*/
641	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
642	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
643	for (uint32_t i = 0; i < cRanges; i++)
644	{
645	char szName[160];
646	ssize_t cchName;
647
648	if (paRanges[i].uFirst == paRanges[i].uLast)
649	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
650	paRanges[i].uFirst, paRanges[i].szName);
651	else
652	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
653	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
654
655	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
656	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
657
658	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
659	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
660
661	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
662	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
663
664	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
665	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
666	}
667	# endif /* VBOX_WITH_STATISTICS */
668
669	return VINF_SUCCESS;
670	}
671
672	#endif /* !CPUM_DB_STANDALONE */
673

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 49966

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